PE9702 ES中文资料
MSM66507中文资料
66P207OLMS-66K Series 16-Bit MicrocontrollerGENERAL DESCRIPTIONThe MSM66201/66207 is a high performance microcontroller that employs OKI original nX-8/ 200 CPU core. This chip includes a 16-bit CPU, ROM, RAM, I/O ports, multifunction 16-bit timers, 10-bit A/D converter, serial I/O port, and pulse width modulator (PWM). The MSM66P201/66P207 is the OTP (One-Time Programmable) version of the MSM66201/66207.FEATURES•64K address space for program memory:Internal ROM :MSM6620116K bytesMSM6620732K bytes •64K address space for data memory:Internal RAM :MSM66201512 bytesMSM662071024 bytes •High-speed executionMinimum cycle for instruction:400ns @ 10MHz•Powerful instruction set:Instruction set superior in orthogonal matrix8/16-bit data transfer instructions8/16-bit arithmetic instructionsMultiplication and division operation instructionsBit manipulation instructionsBit logic instrucitonsROM table reference instructions •Abundant addressing modes:Register addressingPage addressingPointing register indirect addressingStack addressingImmediate value addressing•I/O portInput-output port:5 ports ¥ 8 bits(Each bit can be assigned to input or output) Input port:1 port ¥ 8 bits•Built-in multifunctional 16-bit timer:4Following 4 modes can be set for each timer:Auto-reload timer modeClock output modeCapture register modeReal time output mode•Serial port:1 channel (Synchronous/UART switchablemode with baud rate generators)•16-bit pulse width modulator:2•Watchdog timer•Transition detector:4•10-bit A/D converter:8 channels•InterruptsNonmaskable:1Maskable:Internal 16/external 2•Stand-by functionSTOP mode:Software clock stop modeHALT mode:Software CPU stop modeHOLD mode:Hardware CPU stop mode•Package64-pin plastic shrink DIP (SDIP64-P-750-1.78):(MSM66201-¥¥¥SS) (MSM66P201-¥¥¥SS)(MSM66207-¥¥¥SS) (MSM66P207-¥¥¥SS) 64-pin plastic QFP (QFP64-P-1414-0.80-BK):(MSM66201-¥¥¥GSBK)(MSM66207¥¥¥GS-BK)68-pin plastic QFJ (PLCC) (QFJ68-P-S950-1.27):(MSM66201-¥¥¥JS) (MSM66P201-¥¥¥JS)(MSM66207-¥¥¥JS) (MSM66P207-¥¥¥JS) 64-pin ceramic piggyback (ADIP64-C-750-1.78):(MSM66G207VS)(¥¥¥ indicates the code number.)*The piggyback type is used only for engineering samples.BLOCK DIAGRAMPP P P P P P P P P P P P P P P P AE A D YL ES E NDRD 0/P 0.0D 7/P 0.78 /P 1.015/P 1.7P0P1P2P3P4P5DD¥ 8 ¥ 8PIN CONFIGURATION (TOP VIEW)2012345678910111213141516171819CLKOUT/P2.3AD0/P0.0AD1/P0.1AD2/P0.2AD3/P0.3AD4/P0.4AD5/P0.5AD6/P0.6AD7/P0.7A8/P1.0A9/P1.1A10/P1.2A11/P1.3A12/P1.4A13/P1.5A14/P1.6A15/P1.7P2.0P2.1P2.2P3.7/TM3IO V DD V REF AGND P5.7/AI7P5.6/AI6P5.5/AI5P5.4/AI4P5.3/AI3P5.2/AI2P5.1/AI1P5.0/AI0P4.7/TRNS3P4.6/TRNS2P4.5/TRNS1P4.4/TRNS0P4.3/PWM1P4.2/PWM0P4.1/TM1CK P4.0/TM0CK 4564636261605958575655545352515049484746212223242526272829303132444342414039383736353433RESOUTP3.6/TM2IO ALE P3.5/TM1IO PSEN P3.4/TM0IO RD P3.3/INT1WR P3.2/INT0READYP3.1/RXD EA P3.0/TXD FLT P2.7/RXC RES P2.6/TXC OSC0P2.5/HLDA OSC1P2.4/HOLD GNDNMI64-Pin Plastic Shrink DIPPIN CONFIGURATION (TOP VIEW) (Continued)A8/P1.0A9/P1.1A10/P1.2A11/P1.3A12/P1.4A13/P1.5A14/P1.6A15/P1.7P2.0P2.1P2.2P5.2/AI2P5.1/AI1P5.0/AI0P4.7/TRNS3P4.6/TRNS2P4.5/TRNS1P4.4/TRNS0P4.3/PWM1P4.2/PWM0P4.1/TM1CK P4.0/TM0CK 0.7/A D 70.6/A D 60.5/A D 50.4/A D 40.3/A D 30.2/A D 20.1/A D 10.0/A D 0D DR E FG N DW R R E A D Y E A F L T R E S O S C 0O S C 1G N D N M I H O L D /P 2.4H L D A /P 2.5CLKOUT/P2.3RESOUT ALE PSEN RD T X C /P 2.6R X C /P 2.7T X D /P 3.0R X D /P 3.1I N T 0/P 3.2P3.7/TM3IO P3.6/TM2IO P3.5/TM1IO P3.4/TM0IO P3.3/INT15.7/A I 75.6/A I 65.5/A I 55.4/A I 45.3/A I 364-Pin Plastic QFPPIN CONFIGURATION (TOP VIEW) (Continued)AI3/P5.3AI4/P5.4AI5/P5.5AI6/P5.6AI7/P5.7AGND V REF V DD AD0/P0.0AD1/P0.1AD2/P0.2AD3/P0.3AD4/P0.4AD5/P0.5AD6/P0.6AD7/P0.7P3.2/INT0P3.1/RXD P3.0/TXD P2.7/RXC P2.6/TXC P2.5/HLDA P2.4/HOLD NMI GND OSC1OSC0RES FLT EA READY WRA 8/P 1.0A 9/P 1.1A 10/P 1.2A 11/P 1.3A 12/P 1.4A 13/P 1.5A 14/P 1.6A 15/P 1.7P 2.0P 2.1P 2.2C L K O U T /P 2.3R E S O U T A L E P S E N R D P 5.2/A I 2P 5.1/A I 1P 5.0/A I 0P 4.7/T R N S 3P 4.6/T R N S 2P 4.5/T R N S 1P 4.4/T R N S 0P 4.3/P W M 1P 4.1/T M 1C KP 4.0/T M 0C KN CP 3.7/T M 3I OP 3.6/T M 2I OP 3.5/T M 1I OP 3.4/T M 0I OP 3.3/I N T 1V DD N C P 4.2/P W M 0GNDNC : No-connection pin 68-Pin Plastic QFJ (PLCC)PIN DESCRIPTIONType DescriptionSymbol P0.0–P0.7/AD0–AD7P1.0–P1.7/A8–A15P2.0–P2.2P2.5/HLDA P2.6/T X C AD: Outputs the lower 8 bits of program counter during external program memory fetch, and receives the addressed instruction under the control of PSEN . This pin also outputs the address and outputs or inputs data during an external data memory access instruction, under the control of ALE, RD , and WR . P1:8-bit input-output port. Each bit can be assigned to input or output.A:Outputs the upper 8 bits of program counter (PC 8–15) during external program memory fetch. This pin also outputs the upper 8 bits of address during external data memory access instructions.P2:8-bit input-output port. Each bit can be assigned to input or output.T X C:Transmitter clock input/output pin.P3:8-bit input-output port. Each bit can be assigned to input or output.P2.4/HOLD HOLD:Input pin to request the CPU to enter the hardware power-down state.P3.0/T X D P3.1/R X D P0: 8-bit input-output port. Each bit can be assigned to input or output.I/OI/OI/OT X D:Transmitter data output pin.I/OHLDA:HOLD ACKNOWLEDGE: the HLDA signal appears in response to the HOLD signal and indicates that the CPU has entered the power-down state.P2.3/CLKOUT CLKOUT:Output pin for supplying a clock to peripheral circuits.P2.7/R X C R X C:Receiver clock input/output pin.P3.2/INT0R X D:Receiver data input pin.P3.3/INT1INT :Interrupt request input pin.Falling edge trigger or level trigger is selectable.P3.4/TM0IO TM0IO-TM3IO:One of the following signals is output or input.P3.5/TM1IO P3.6/TM2IO P3.7/TM3IO•Clock at twice the frequency range of the 16-bit timer overflow •Load trigger signal to the capture register input •Setting value outputWhether the signal is input or output depends on the mode.P4.0/TM0CK P4:8-bit input-output port. Each bit can be assigned to input or output.P4.1/TM1CK TM0CK, TM1CK:Clock input pins of timer 0, timer 1.P4.2/PWM0P4.3/PWM1P4.4 – P4.7/TRANS0 – TRANS3TRANS:Transition detector.The input pins which sense the falling edge and set the flag.PWM:16-bit pulse-width modulator output pin.I/OP5.0 – P5.7/AI0 –AI7P5:8-bit input port.AI:Analog signal input pin for A/D converter.IPIN DESCRIPTION (Continued)RESOUT Outputs "H" level in the case of internal reset.Reset to"L" level by program.ALEAddress Latch Enable:PSEN Program Strobe Enable:RD Output strobe activated during a bus read cycle.Used to enable data onto the bus from the external data memory.WR Output strobe during a bus write cycle.Used as write strobe to external data memory.I READY Used when the CPU accesses low-speed peripherals.EA Normaly set to "H" level.If set to "L" level, the CPU fetches the code from external program memory.FLT If FLT is "H" level, ALE, WR , RD , PSEN are set to "H" level when reset.If FLT is set to "L", ALE, WR , RD , PSEN are set to floating level when reset.RES RESET input pin.OSC0OSC1Basic clock oscillation pin.NMI Non-maskable interrupt input pin (falling edge).V REF Reference voltage input pin for A/D converter.AGND Ground for A/D converter.V DD System power supply.GNDGround.Type DescriptionSymbol O OO O O I I I I I O ————The timing pulse to latch the lower 8 bits of the address output from port 0 when the CPU accesses the external memory.The strobe pulse to fetch to external program memory.Basic clock oscillation pin.REGISTERSAccumulatorACC15Control Register (CR)PSWBit 15 : Carry flag (CY)Bit 14 : Zero flag (ZF)Bit 13 : Half carry flag (HC)Bit 12 : Data descriptor (DD)Bit 8 : Master interrupt priority flag (MIP)Bit 9,5,4: User flag (MIP)Bit 2-0 : System control base 2-0 (SCB2-0)PC LRB SSP15150Index Register 1Index Register 2Data Pointer User Stack PointerPointing Register (PR)Local RegisterR1R3R5R7R0R2R4R6ER0ER1ER2ER3707SFRAddress (HEX)Name Symbol R/W8/16-bitOperationReset0000 0001 0002 0003 0004I 0005I 0006 0007 0010I 0011 0012I 0013 0018 0019 001A 001B 001C I System stack printerLocal register baseProgram status wordAccumulatorStandby control registerWatchdog timerPeripheral control registerStop code acceptorInterrupt request registerInterrupt enable registerExternal Iinterrupt control registerSSP(ASSP)LRB(ALRB)PSWL(APSW)PSWHACCSBYCONWDTPRPHFSTPACPIEEXICONIRQR/WWR/WW8/1688/16FFHFFHundefinedC8H0CH00H00HF8HFDH"0"00H00H00H00HFCH00H/WDTis stopped0020 0021 0022 0023 0024 0025 0026I 0028 0029 002A 002C 002D 002E 002F 0030 0031Port 0 data registerTimer 0 counterP3IOP3SFP4P4IOTM0R/W8undefined Port 0 mode registerPort 2 secondary function control registerP3P2SFP2IOP2P1IOP1P0IOP0P4SFPort 5P500320033Timer 0 register TMR0 00340035Timer 1 counter TM10036 0037Timer 1 register TMR1Port 1 data registerPort 1 mode registerPort 2 data registerPort 2 mode registerPort 3 secondary function control registerPort 3 data registerPort 3 mode registerPort 4 secondary function control registerPort 4 data registerPort 4 mode registerRR/W1600Hundefined00Hundefined00H07Hundefined00H00Hundefined00H00H—00H00H00H00H00H00H00H00HNote: A I mark in the address column indicates that there is a bit that does not exist in the register.Addres (HEX)Name AbbreviatedNameR/W8/16-bitOperationReset003A 003B 003C 003D 003E 003F 0040 0041 0042 0043 0046I 0048 0049 004A I004C 004D Timer 2 registerTCON2TCON3TRNSITSTTM1600HTimer 0 control registerTCON1TCON0TMR3TM3TMR2STTMRSTTMC004E I0050I 0051 0054 0055 0056I 0058I 0059I Timer 3 counterTimer 3 registerTimer 3 control registerTimer 1 control registerTimer 2 control registerTransition detector registerSerial port transmission baud rate generator counter00H00H00H00H00H00H00H00H00Hundefined00H00H0CH00H00H0EH80Hundefined00HundefinedF0H80HA0HSRTMSRTMRSRTMCSTCONSerial port transmission baud rate generator registerSerial port transmission baud rate generator controlregisterSerial port transmission mode control registerSerial port transmission data buffer registerSerial port receiving error registerA/D scan mode registerA/D select mode registerA/D conversion result register 0Serial port receiving baud rate generator counterSerial port receiving baud rate generator registerSerial port receiving baud rate generator controlregisterSerial port receiving mode control registerSerial port receiving data buffer register0060I 0061STBUFSRCONSRBUFSRSTATADSCANADSELADCR0R/WWR/WRR/WR88/16undefined0038 0039Timer 2 counter00HTM200HSFR (Continued)Note: A I mark in the address column indicates that there is a bit that does not exist in the register.SFR (Continued)Note: A I mark in the address column indicates that there is a bit that does not exist in theregister.Address (HEX)NameAbbreviated NameR/W8/16-bit operationReset0062I 0063A/D conversion result register 1ADCR10064I 0065ADCR20066I 0067ADCR30068I 0069ADCR4006A I 006B ADCR5R8/16undefined006C I 006D ADCR6006E I 006F ADCR700700071PWMC000H 00H 00720073PWM 0 register PWMR000H 00H 00740075PWM 1 counter PWMC100H 00H 00760077PWM 1 register PWMR100H 00H 0078007APWM 0 control register PWCON000H 00H8PWM 1 countrol registerPWCON1R/WA/D conversion result register 2A/D conversion result register 4A/D conversion result register 5A/D conversion result register 6A/D conversion result register 7PWM 0 counter A/D conversion result register 3ADDRESSING MODESThe MSM66201/66207 provides independent 64K-byte data and 64K-byte program space with various types of addressing modes. These modes are shown below, for both RAM (for data space) and ROM (for program space).1.RAM Addressing Modes (for data space)1.1Register Direct Addressing1.2Displacement Addressinga)Zero Pageb)Direct Page1.3Pointing Register (PR) Indirect AddressingData Point (DP) Indirecta)b)User Stack Pointer (USP) Indirectc)Index Register (X1, X2) Indirect1.4Immediate Addressing2.ROM Addressing Modes (for program space) 2.1Direct Addressing2.2Simple Indirect Addressinga)Local Register Indirectb)Pointing Register Indirect1)Data Pointer (DP) Indirect2)User Stack Pointer (USP) Indirect3)Index Register (X1, X2) Indirectc)System Stack Pointer (SSP) Indirectd)Local Register Base (LRB) Indirecte)RAM Indirect2.3Double Indirect Addressinga)Data Pointer (DP) Double Indirectb)User Stack Pointer (USP) Double Indirectc)Index Register (X1, X2) Double Indirect2.4Indirect Addressing with 16-bit Offseta)Pointing Register Indirect 1)Data Pointer (DP) Indirect2)User Stack Pointer (USP) Indirect3)Index Register (X1, X2) Indirectb)RAM IndirectMEMORY MAPS Program Memory Space0000H 7FFFH * FFFFH0000H0027H0028H0037H0038H7FFFH *InternalROM AreaVectorTableArea(40 bytes)ExternalMemoryVCALTableArea(16 bytes) * MSM66201 : 3FFFHData Memory SpaceFFFFH0000H007FH0080H00BFH00C0H047FH *SFR Area SpecialFunctionRegistorsPORT, A/DC,TIMER, PWM,etc....PR AreaPR0PR1PR2PR3PR4PR5PR6PR7(Low Order)X2DPUSP* MSM66201 : 027FH(High Order)80828486X1ABSOLUTE MAXIMUM RATINGSParameter Supply Voltage Input Voltage Output VoltageAnalog Input VoltagePower DissipationStorage Temperature SymbolV DDConditionGND=AGND=0V—Rating–0.3 to 7.0UnitV IV OV AIP DT STG64-pin shrink DIP64-pin QFP–0.3 to V DD+0.3–0.3 to V DD+0.3–0.3 to V REF930565–55 to +150VmW°CAnalog Ref. Voltage V REF–0.3 to V DD+0.3Ta=85°Cper Package68-pin QFJ1120(Ta=25°C) RECOMMENDED OPERATING CONDITIONSParameter Supply Voltage Memory Hold Voltage Operating Frequency Ambient TemperatureFan Out SymbolV DDCondition Range4.5 to5.5UnitV DDHf OSCNMOS loadP02.0 to 5.50 to 10202VMHz—Ta–40 to +85°C TTL loadP1, P2, P3, P41f OSC £ 10MHzf OSC = 0HzV DD = 5V ±10%—ELECTRICAL CHARACTERISTICSDC CharacteristicsNote:1Applied to P02Applied to P1, P2, P3 and P43Applied to P54Applied to ALE, PSEN , RD , WR and RESOUT 5Applied to RES and NMI 6Applied to READY and EA 7Applied to FLT 8Applied to OSC 0*V DD or GND for ports serving as the input pin. No load for any other.**Applied to MSM66P201/66P207ParameterSymbolConditionMin.Max.Unit"H" Input Voltage 1, 3, 6"H" Input Voltage 5, 7V IH2.44.04.23.6V DD +0.3V DD +0.3V DD +0.3V DD +0.3—"H" Input Voltage 8"H" Input Voltage 2Typ.—"L" Input Voltage 1, 2, 3, 6V IL–0.3–0.3–0.30.80.80.4V"L" Input Voltage 5, 7"L" Input Voltage 8V OH 4.24.2——I O = –400m A "H" Output Voltage 1, 4"H" Output Voltage 2V OL——0.40.4I O = 3.2mA "L" Output Voltage 1, 4"L" Output Voltage 2I O = –200m A I O = 1.6mAInput Leakage Current 3, 6, 7I IH /I IL———1/–11/–2010/–10m AV I = V DD /0VInput Current 5Input Current 8"H" Output Current 1"H" Output Current 2I OHI OL –2–1105————mAV O = 2.4V"L" Output Current 1"L" Output Current 2I LO —±2m A Output Leakage Current 1, 2, 4V O = V DD /0V C I C O ————pF Input Capacitance Output Capacitance 57f = 1MHz Ta = 25°C I DDS ——10100m ACurrent Consumption (during STOP) *0.21V DD = 2V I DDH —**—1015Current Consumption (during HALT)68f OSC = 10MHz No LoadI DD—**—3540mACurrent Consumption2030———————————————————(V DD = 5V ± 10%, Ta = –40 to +85°C) I REF ——210Analog Reference Power Supply Current 0.30.5A/D in operation A/D stopped mA m A —AC Characteristics•External program memory control•External data memory controlParameter Symbol ConditionMin.Max.Unit Clock (OSC) Pulse ALE Pulse Width RD Pulse Width WR Pulse Width RD Pulse Delay Time WR Pulse Delay Time Low Address Setup Time Low Address Hold Time High Address Setup Time Data Hold Timet f W t AW t RW t WW t RAD t WAD t AAS t AAH t AAD t DH—C L = 50pF 503t f W –204t f W –204t f W –20t f W –20t f W –202t f W –35t f W –20t f W –20t f W –20————t f W +20t f W +202t f W +20t f W +40t f W +40t f W +40ns(V DD =5V±10%, Ta=–40 to +85°C)Data Delay Time t DD t f W –20t f W +40Memory Data Hold Time t MH 0t f W –20Memory Data Setup Time t MS 100—High Address Hold Time t AWH t f W –20t f W +40High Address Hold Time t ARH t f W –20t f W +40Parameter Symbol ConditionMin.Max.Unit Clock (OSC) Pulse ALE Pulse Width PSEN Pulse Width PSEN Pulse Delay Time Low Address Setup time Low Address Hold Time High Address Delay Time High Address Hold Time Instruction Setup Time Instruction Hold Timet f W t AW t PW t PAD t AAS t AAH t AAD t APH t IS t IH—C L = 50pF 503t f W –204t f W –20t f W –202t f W –35t f W –20t f W –20t f W –201000———t f W +202t f W +20t f W +40t f W +40t f W +40—t f W –20ns(V DD =5V±10%, Ta=–40 to +85°C)CLKALEAD0-7A8-15PSENAD0-7A8-15RDAD0-7A8-15WR• Serial port control Master modeSlave modeParameter Symbol ConditionMin.Max.UnitClock (OSC) Pulse Width Serial Clock Pulse Width Input Data Setup Time Input Data Hold Timet f W t SCKW t STMXS t STMXH t SRMXS t SRMXH—508t f W 8t f W +406t f W –202t f W +1050——————ns —C L =50pF Output Data Setup Time Output Data Hold Time (V DD =5V±10%, Ta=–40 to +85°C)Parameter Symbol ConditionMin.Max.UnitClock (OSC) Pulse Width Serial Clock Pulse Width Input Data Setup Time Input Data Hold Timet f W t SCKW t STSXS t STSXH t SRSXS t SRSXH—508t f W 6t f W +406t f W –20100100——————ns —C L =50pF Output Data Setup Time Output Data Hold Time (V DD =5V±10%, Ta=–40 to +85°C)SCKSDOUT (TXD)SDIN (RXD)SCKSDOUT (TXD)SDIN(RXD)A/D Converter Characteristics • Operating range• A/D Converter accuracy Normal operation modeParameter SymbolConditionMin.Unit Resolution Crosstalkn E A E R E CSee the recommendedcircuit.V R =V DD V AG =GND=0V Analog input source impedance£5k WOne channel conversion timet C =64m s————BitAbsolute Error Relative Error *———————±0.5*———±0.510+3.0–3.5±1.5*10±1.0Typ.Max.E Z 0Zero Point Error 0——+3.0+2.0E F –0.5LSBFull Scale Error–1.0——–3.5–3.5Differential Linearity Error E D ——————+3.0+2.0+2.0–3.5(V DD =5V±10%, f OSC =10MHz, Ta=–40 to +85°C)*V DD =5V, Ta=25°CHALT/HOLD operation modeParameter SymbolConditionMin.Unit Resolution Crosstalkn E A E R E CSee the recommendedcircuit.V R =V DD V AG =GND=0VAnalog input source impedance£5k WOne channel conversion timet C =64m s————BitAbsolute Error Relative Error *———————±0.5*———±0.510+2.0–3.5±1.0*10±0.5Typ.Max.E Z +0.5Zero Point Error +0.5——+2.0+1.0E F –1.0LSBFull Scale Error–1.5——–3.5–2.0Differential Linearity Error E D ——————+2.0+1.0+1.0–2.0(V DD =5V±10%, f OSC =10MHz, Ta=–40 to +85°C)*V DD =5V, Ta=25°CParameter Symbol Condition Min.Max.Unit Power Supply Voltage Analog Reference Voltage Operating TemperatureV DD V R V AI R R T opf OSC £ 10MHz4.54.5V AG —–405.5V DD V R —+85V k W °CV AG = GND = 0V Analog Input Voltage Analog Reference Power Voltage Resistance Typ.———16—V DD = 5V ± 10%• Recommended circuit+5V0VR I (Analog input source impedance) £ 5k W• A/D Converter conversion characteristics 13FF000E Z MINE Z MAXVREF [V]Analog InputConversion CodeConversion Characteristics Diagram 1Absolute error (E A )The absolute error indicates a difference between actual conversion and ideal conversion,excluding a quantizing error. The absolute error of the A/D converter gets larger as it approaches the zero point or full scale. (Refer to Conversion Characteristics Diagram 1.)Relative error (E R )The relative error indicates a deviation from a line which connects the center point of the zero point conversion width with that of the full scale conversion width, excluding a quantizing error.The relative error of this A/D converter is almost due to a differential linearity error.Zero point error (Ez) and full scale error (E F )The zero point error and full scale error indicate a difference between actual conversion and ideal conversion at the zero point and full scale, respectively. (Refer to Conversion Characteristics Diagram 1.)A/D Converter Conversion Characteristics 2 (temperature characteristics)Conversion CharacteristicsConversion CharacteristicsDiagram 2-1Diagram 2-2Differential linearity error (E D )The differential linearity error indicates a difference between the actual conversion width (actual step width) and ideal value (1LSB).With this A/D converter, a voltage for actual conversion is shifted and the inclination of a voltage is changed, with changes of temperature (see Conversion Characteristics Diagram 2-1). Specifications described in the foregoing tables are established from Eta shown in Conversion Characteristics Diagram 2-1 (E D =Eta–1LSB). Conversion Characteristics Diagram 2-2 shows temperature characteristics of differential linearity of Es in Conversion Characteristics Diagram 2-1.3FF[HEX]000E SEta[V]–40°C+25°C+85°C+4[LSB]0Temparature Ta+3+2+1–40+85During normal operation During HALTE SConversion CodeAnalog InputESDifferential Linearity[°C](Unit : mm)PACKAGE DIMENSIONSNotes for Mounting the Surface Mount Type PackageThe SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage.Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).SDIP64-P-750-1.78Package material Lead frame material Pin treatmentSolder plate thickness Package weight (g)Epoxy resin Cu alloySolder plating 5 m m or more 8.70 TYP.(Unit : mm)Notes for Mounting the Surface Mount Type PackageThe SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage.Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).QFP64-P-1414-0.80-BKPackage material Lead frame material Pin treatmentSolder plate thickness Package weight (g)Epoxy resin 42 alloySolder plating 5 m m or more 0.87 TYP.Mirror finish(Unit : mm)Notes for Mounting the Surface Mount Type PackageThe SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage.Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).QFJ68-P-S950-1.27Package material Lead frame material Pin treatmentSolder plate thickness Package weight (g)Epoxy resin Cu alloySolder plating 5 m m or more 4.50 TYP.Mirror finish(Unit : mm)Notes for Mounting the Surface Mount Type PackageThe SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage.Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).ADIP64-C-750-1.78。
DS9702A-04P(2)
DS9702/A-04 April 2004FeaturesPin ConfigurationsApplications80m Ω, 500mA/1.1A High-Side Power Switches with FlagFor marking information, contact our sales representative directly or through a RichTek distributor located in your area, otherwise visit our website for detail.Ordering InformationMarking InformationGeneral Description(TOP VIEW)SOT-25The RT9702 and RT9702A are cost-effective, low voltage,single N-Channel MOSFET high-side power switches,optimized for self-powered and bus- powered Universal Serial Bus (USB) applications. The RT9702/A equipped with a charge pump circuitry to drive the internal MOSFET switch; the switch's low R DS(ON), 80m Ω, meets USB voltage drop requirements; and a flag output is available to indicate fault conditions to the local USB controller.Additional features include soft-start to limit inrush current during plug-in, thermal shutdown to prevent catastrophic switch failure from high-current loads, under-voltage lockout (UVLO) to ensure that the device remains off unless there is a valid input voltage present, fault current is limited to typically 800mA for RT9702 in single port and 1.5A for RT9702A in dual ports in accordance with the USB power requirements, lower quiescent current as 25µA making this device ideal for portable battery-operated equipment.The RT9702/A is available in SOT-25 package requiringminimum board space and smallest components.CE GND FLGVINVOUTCompliant to USB SpecificationsBuilt-In (Typically 80m Ω) N-Channel MOSFETOutput Can Be Forced Higher Than Input (Off-State)Low Supply Current:25µA Typical at Switch On State 1µA Typical at Switch Off StateGuaranteed 500mA/RT9702 and 1.1A/RT9702A Continuous Load CurrentWide Input Voltage Ranges: 2V to 5.5V Open-Drain Fault Flag OutputHot Plug-In Application (Soft-Start)1.7V Typical Under-Voltage Lockout (UVLO) Current Limiting Protection Thermal Shutdown ProtectionReverse Current Flow Blocking (no body diode) Smallest SOT-25 Package Minimizes Board SpaceUL Approved −E219878USB Bus/Self Powered Hubs USB PeripheralsACPI Power DistributionPC Card Hot SwapNotebook, Motherboard PCs Battery-Powered Equipment Hot-Plug Power SuppliesBattery-Charger CircuitsFunction Block DiagramFunctional Pin DescriptionTypical Application CircuitPull-Up Resistor (10K to 100K)Note: A low-ESR 150µF aluminum electrolytic or tantalum between V OUT and GND is strongly recommended to meet the 330mV maximum droop requirement in the hub V BUS . (see Application Information Section for further details)FLGVOUTVINCEDS9702/A-04 April 2004I LR FGV Test Circuits1234Note: Above test circuits reflected the graphs shown on “Typical Operating Characteristics ”are as follows:−Turn-On Rising & Falling Time vs. Temperature, Turn-On & Off Response, Flag Response−Supply Current vs. Input Voltage & Temperature, Switch Off Supply Current vs. Temperature, Turn-Off Leakage Current vs. Temperature−On-Resistance vs. Input Voltage & Temperature−CE Threshold Voltage vs. Input Voltage & Temperature, Flag Delay Time vs. Input Voltage & Temperature, UVLO Threshold vs. Temperature, UVLO at Rising & Falling−Current Limit vs. Input Voltage/Temperature, Short Circuit Current Response, Short Circuit Current vs. Temperature, Inrush Current Response, Soft-start Response, Ramped Load Response, Current Limit Transient Response, Thermal Shutdown ResponseV R DS(ON)V I VINI LR FGVI LR FGV IN12345Absolute Maximum Ratings (Note 1)Electrical CharacteristicsSupply Voltage ---------------------------------------------------------------------------------------------------------6.5VChip Enable Input Voltage ------------------------------------------------------------------------------------------−0.3V to 6.5V Flag Voltage ------------------------------------------------------------------------------------------------------------6.5VPower Dissipation, P D @ T A = 25°CSOT-25------------------------------------------------------------------------------------------------------------------0.25WPackage Thermal ResistanceSOT-25, θJA -------------------------------------------------------------------------------------------250°C/W Junction Temperature ------------------------------------------------------------------------------------------------150°C Lead Temperature (Soldering, 10 sec.)-------------------------------------------------------------------------260°CStorage Temperature Range ---------------------------------------------------------------------------------------−65°C to 150°CESD Susceptibility (Note 2)HBM (Human Body Mode)-----------------------------------------------------------------------------------------8kV MM (Machine Mode)-------------------------------------------------------------------------------------------------800VRecommended Operating Conditions (Note 3)Supply Input Voltage -------------------------------------------------------------------------------------------------2V to 5.5V Chip Enable Input Voltage ------------------------------------------------------------------------------------------0V to 5.5VJunction Temperature Range --------------------------------------------------------------------------------------−20°C to 100°C(V IN = 5V, C IN = C OUT = 1µF, T A = 25°C, unless otherwise specified)To be continuedParameter SymbolNote 1. Stresses beyond those listed under“Absolute Maximum Ratings”may cause permanent damage to the device.These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum ratingconditions for extended periods may affect device reliability.Note 2. Devices are ESD sensitive. Handling precaution recommended. The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into input and output pins.Note 3. The device is not guaranteed to function outside its operating conditions.Note 4. The FLAG delay time is input voltage dependent, see“ Typical Operating Characteristics” graph for further details. DS9702/A-04 April Current Limit vs. Temperature0.400.600.801.001.201.401.601.802.002.202.40-40-2020406080100120Temperature 5Typical Operating Characteristics(U.U.T: RT9702ACB, unless otherwise indicated)Supply Curent vs. Input Voltage051015202530354022.533.544.555.5Input Voltage (V)2On-Resistance vs. Input Voltage02040608010012014016022.533.544.555.5Input Voltage (V)(m Ω)3On-Resistance vs. Temperature20406080100120140160-40-20020406080100120Temperature 3(m Ω)(°C)Supply Current vs. Temperature510152025303540-40-20020406080100120Temperature 2(°C)(°C)Current Limit vs. Input Voltage1.001.201.401.601.802.0022.533.544.555.5Input Voltage (V)5DS9702/A-04 April 2004Short Circuit Current vs. Temperature 0.600.801.001.201.401.601.802.00-40-20020406080100120Temperature CE Threshold Voltage vs. Input Voltage00.40.81.21.622.422.533.544.555.5Input Voltage (V)4CE Threshhold Voltage vs. Temperature0.40.81.21.622.4-40-20020406080100120Temperature (°C)4Turn-On Rising Time vs. Temperature 0901********450540630720-40-2020406080100120Temperature (°C)(u s )1Turn-Off Falling Time vs. Temperature 020406080100120140-40-2020406080100120Temperature (°C)(u s)1(°C)5V IN =5V, S 2=S 3=On C I N =33uF C OUT =0.1uFShort Circuit Current ResponseTime (5ms / DIV)51 2V O U T (V )I O U T (A )5FLAG Delay Time vs. Input Voltage0481216202422.533.544.555.5Input Voltage (V)4UVLO Threshold vs. Temperature00.511.522.533.5-40-2020406080100120Temperature (°C)4Turn-Off Leakage Current vs. Temperature0.511.522.533.5-40-20020406080100120Temperature (°C)FLAG Delay Time vs. Temperature78910111213141516-40-2020406080100120Temperature (°C)4(u A)2Switch Off Supply Current vs. Temperature-1-0.8-0.6-0.4-0.200.20.40.60.81-40-2020406080100120Temperature (°C)2V IN =5V, R L =1Ω C I N =33uF S 2=On, S 3=OffShort Circuit Current ResponseTime (10ms / DIV)12I O U T (A )3455C OUT =1000uF C OUT =220uFC OUT =1uFDS9702/A-04 April 2004Time (100µs / DIV) V C E(5I V )V O U T(1V )V IN =5V, R L=30Ω C I N =33uF, C OUT =1uF S 1=On Turn- On ResponseV IN =5V, R L = 30Ω C I N =33uF,COUT =1uF S1=On 1 V I N(1I V )V O U T(1I V )Time (1ms / DIV)UVLO at RisingV IN =5V, R L = 30Ω C I N =33uF, C OUT =1uFV INV OUT 4V I N/D I V )V O U T(1V /Time (10m s / DIV)UVLO at FallingV IN =5V, R L = 30Ω C I N =33uF, C OUT =1uFVINV OUT4V C E(5V )I L(0.I V )Time (50µs / DIV)Soft- Start ResponseV IN =5V, R L =1Ω C I N =33uF, C OUT =1uFS 2:Off OnS 3= Off↓5 I L(0.I V )V O U T(5V )Time (100ms / DIV)Ramped Load ResponseV IN =5V R L =1k Ω 1Ω C I N =33uF,C OUT =1uF↓4.9V1.1A5V C E(5V )V O U T (5V ) I L(0.5I V )Time (100µs / DIV)Turn- Off ResponseV IN =5V, R L = 30Ω S 1=OffC I N =33uF C OUT =1uF1I L(0.I V )V C E(5V )Time (2.5ms / DIV)Flag Response (Enable into Short Circuit) C I N =33uF,C OUT =1uFR L =0Ω , S 1=OnV F L G(5V ) 12ms (t D )RT9702CB1Time (10ms / DIV)12ms (t D)I L(1I V )V O U TV )Flag ResponseR L =1Ω S 1=OnV F L G1I O U T(1V )Time (5us / DIV)Current Limit Transient Respones V IN =5V,C I N =C OUT =33uF S 2=On ,S 3=Off,R L =1ΩV T R I G G E R(5V )5I O U T(1A/D I V ) SV C E/D I V )Time (50ms / DIV)I O U T (1A /D I V )u C I N =33uF C OUT =1uFThermal Shutdown Response511DS9702/A-04 April 2004In order to eliminate the upstream voltage droop caused by the large inrush current during hot-plug events,the “soft-start ”feature effectively isolates the power source from extremely large capacitive loads, satisfying the USB voltage droop requirements.Fault FlagThe RT9702/A provides a FLG signal pin which is an N-Channel open drain MOSFET output. This open drain output goes low when V OUT < V IN – 1V, current limit or the die temperature exceeds 130°C approximately. The FLG output is capable of sinking a 10mA load to typically 200mV above ground. The FLG pin requires a pull-up resistor, this resistor should be large in value to reduce energy drain. A 100k Ω pull-up resistor works well for most applications. In the case of an over-current condition, FLG will be asserted only after the flag response delay time,t D , has elapsed. This ensures that FLG is asserted only upon valid over-current conditions and that erroneous error reporting is eliminated.For example, false over-current conditions may occur during hot-plug events when extremely large capacitive loads are connected and causes a high transient inrush current that exceeds the current limit threshold. The FLG response delay time t D is typically 10ms.Under-Voltage LockoutUnder-voltage lockout (UVLO) prevents the MOSFET switch from turning on until input voltage exceeds approximately 1.7V. If input voltage drops below approximately 1.3V, UVLO turns off the MOSFET switch,FLG will be asserted accordingly. Under-voltage detection functions only when the switch is enabled.Current Limiting and Short-Circuit Protection The current limit circuitry prevents damage to the MOSFET switch and the hub downstream port but can deliver load current up to the current limit threshold of typically 800mA through the switch of RT9702 and 1.5A for RT9702A respectively. When a heavy load or short circuit is applied to an enabled switch, a large transient current may flow until the current limit circuitry responds.Applications InformationThe RT9702 and RT9702A are single N-Channel MOSFET high-side power switches with active-high enable input, optimized for self-powered and bus-powered Universal Serial Bus (USB) applications. The RT9702/A equipped with a charge pump circuitry to drive the internal NMOS switch; the switch's low R DS(ON), 80m Ω, meets USB voltage drop requirements; and a flag output is available to indicate fault conditions to the local USB controller.Input and OutputV IN (input) is the power source connection to the internal circuitry and the drain of the MOSFET . V OUT (output) is the source of the MOSFET . In a typical application, current flows through the switch from V IN to V OUT toward the load.If V OUT is greater than V IN , current will flow from V OUT to V IN since the MOSFET is bidirectional when on.Unlike a normal MOSFET , there is no a parasitic body diode between drain and source of the MOSFET , the RT9702/A prevents reverse current flow if V OUT being externally forced to a higher voltage than V IN when the output disabled (V CE < 0.8V).Chip Enable InputThe switch will be disabled when the CE pin is in a logic low condition. During this condition, the internal circuitry and MOSFET are turned off, reducing the supply current to 0.1µA Typical. The maximum guaranteed voltage for a logic low at the CE pin is 0.8V. A minimum guaranteed voltage of 2V at the CE pin will turn the RT9702/A back on. Floating the input may cause unpredictable operation.CE should not be allowed to go negative with respect to GND. The CE pin may be directly tied to V IN to keep the part on.Soft Start for Hot Plug-In ApplicationsGSD G Normal MOSFET RT9702/A12DS9702/A-04 April 2004 Thermal ShutdownThermal shutdown is employed to protect the device from damage if the die temperature exceeds approxi- mately 130°C. If enabled, the switch automatically restarts when the die temperature falls 20°C. The output and FLG signal will continue to cycle on and off until the device is disabled or the fault is removed.Power DissipationThe device s junction temperature depends on several factors such as the load, PCB layout, ambient temperature and package type. The output pin of RT9702/A can deliver a current of up to 500mA, and 1.1A respectively over the full operating junction temperature range. However, the maximum output current must be derated at higher ambient temperature to ensure the junction temperature does not exceed 100°C. With all possible conditions, the junction temperature must be within the range specified under operating conditions. Power dissipation can be calculated based on the output current and the R DS(ON) of switch as below.P D = R DS(ON) x I OUT 2Although the devices are rated for 500mA and 1.1A of output current, but the application may limit the amount of output current based on the total power dissipation and the ambient temperature. The final operating junction temperature for any set of conditions can be estimated by the following thermal equation:P D (MAX) = ( T J (MAX) - T A ) / θJAWhere T J (MAX) is the maximum junction temperature of the die (100°C) and T A is the maximum ambient temperature. The junction to ambient thermal resistance (θJA ) for SOT-25 package at recommended minimum footprint is 250°C/W (θJA is layout dependent).Universal Serial Bus (USB) & Power Distribution The goal of USB is to be enabled device from different vendors to interoperate in an open architecture. USB features include ease of use for the end user, a wide rangeof workloads and applications, robustness, synergy with the PC industry, and low-cost implement- ation. Benefits include self-identifying peripherals, dynamically attachable and reconfigurable peripherals, multiple connections (support for concurrent operation of many devices),support for as many as 127 physical devices, and compatibility with PC Plug-and-Play architecture.The Universal Serial Bus connects USB devices with a USB host: each USB system has one USB host. USB devices are classified either as hubs, which provide additional attachment points to the USB, or as functions,which provide capabilities to the system (for example, a digital joystick). Hub devices are then classified as either Bus-Power Hubs or Self-Powered Hubs.A Bus-Powered Hub draws all of the power to any internal functions and downstream ports from the USB connector power pins. The hub may draw up to 500mA from the upstream device. External ports in a Bus-Powered Hub can supply up to 100mA per port, with a maximum of four external ports.Self-Powered Hub power for the internal functions and downstream ports does not come from the USB, although the USB interface may draw up to 100mA from its upstream connect, to allow the interface to function when the remainder of the hub is powered down. The hub must be able to supply up to 500mA on all of its external downstream ports. Please refer to Universal Serial Specification Revision 2.0 for more details on designing compliant USB hub and host systems.Over-Current protection devices such as fuses and PTC resistors (also called polyfuse or polyswitch) have slow trip times, high on-resistance, and lack the necessary circuitry for USB-required fault reporting.The faster trip time of the RT9702/A power distribution allow designers to design hubs that can operate through faults. The RT9702/A have low on-resistance and internal fault-reporting circuitry that help the designer to meet voltage regulation and fault notification requirements.Once this current limit threshold is exceeded the device enters constant current mode until the thermal shutdown occurs or the fault is removed.13DS9702/A-04 April 2004Output Filter CapacitorA low-ESR 150µF aluminum electrolytic or tantalum between V OUT and GND is strongly recommended to meet the 330mV maximum droop requirement in the hub V BUS (Per USB 2.0, output ports must have a minimum 120µF of low-ESR bulk capacitance per hub). Standard bypass methods should be used to minimize inductance and resistance between the bypass capacitor and the downstream connector to reduce EMI and decouple voltage droop caused when downstream cables are hot-insertion transients. Ferrite beads in series with V BUS , the ground line and the 0.1µF bypass capacitors at the power connector pins are recommended for EMI and ESD protection. The bypass capacitor itself should have a low dissipation factor to allow decoupling at higher frequencies.Fault Flag Filtering (Optional)The transient inrush current to downstream capacitance may cause a short-duration error flag, which may cause erroneous over-current reporting. A simple 1ms RC low-pass filter (10K Ω and 0.1µF) in the flag line (see Typical Application Circuit) eliminates short-duration transients.Voltage DropThe USB specification states a minimum port-output voltage in two locations on the bus, 4.75V out of a Self-Powered Hub port and 4.40V out of a Bus-Powered Hub port. As with the Self-Powered Hub, all resistive voltage drops for the Bus-Powered Hub must be accounted for to guarantee voltage regulation (see Figure 7-47 of Universal Serial Specification Revision 2.0 ).The following calculation determines V OUT (MIN) for multi-ple ports (N PORTS ) ganged together through one switch (if using one switch per port, N PORTS is equal to 1):V OUT (MIN) = 4.75V − [ I I x ( 4 • R CONN + 2 • R CABLE ) ] − (0.1A x N PORTS x R SWITCH )− V PCB WhereR CONN = Resistance of connector contacts (two contacts per connector)R CABLE = Resistance of upstream cable wires (one 5V and one GND)R SWITCH = Resistance of power switch (80m Ω typical for RT9702/A)V PCB = PCB voltage dropThe USB specification defines the maximum resistance per contact (R CONN ) of the USB connector to be 30m Ωand the drop across the PCB and switch to be 100mV.This basically leaves two variables in the equation: the resistance of the switch and the resistance of the cable.If the hub consumes the maximum current (I I ) of 500mA,the maximum resistance of the cable is 90m Ω.The resistance of the switch is defined as follows:R SWITCH = { 4.75V - 4.4V -[ 0.5A x ( 4 • 30m Ω + 2 • 90m Ω ) ]-V PCB }÷( 0.1A x N PORTS )= (200mV - V PCB )÷( 0.1A x N PORTS )If the voltage drop across the PCB is limited to 100mV,the maximum resistance for the switch is 250m Ω for four ports ganged together. The RT9702/A, with its maximum 100m Ω on-resistance over temperature, easily meets this requirement.Because the devices are also power switches, the designer of self-powered hubs has the flexibility to turn off power to output ports. Unlike a normal MOSFET , the devices have controlled rise and fall times to provide the needed inrush current limiting required for the bus-powered hub power switch.Supply Filter/Bypass CapacitorA 1µF low-ESR ceramic capacitor from V IN to GND,located at the device is strongly recommended to prevent the input voltage drooping during hot-plug events.However, higher capacitor values will further reduce the voltage droop on the input. Furthermore, without the bypass capacitor, an output short may cause sufficient ringing on the input (from source lead inductance) to destroy the internal control circuitry. The input transient must not exceed 6.5V of the absolute maximum supply voltage even for a short duration.14DS9702/A-04 April 2004V OUTVI NV BUSBoard LayoutESDBecause USB is a hot insertion and removal system, USB components (especially the connector pins) are subject to electrostatic discharge (ESD) and should be qualified to IEC801.2. The RT9702/A is designed to withstand a 8kV human body mode, as defined in MIL-STD-883C.The requirements in IEC801.2 are much more stringent and require additional capacitors for the RT9702/A to withstand the higher ESD energy.Low-ESR 1µF ceramic bypass capacitors and output capacitors should be placed as closely as possible to the V IN and V OUT pins to increase the ESD immunity. The RT9702/A may pass the requirements of IEC 1000-4-2(EN 50082-1) level-4 for 15kV air discharge and 8kV contact discharge tests when these capacitors are added.PCB LayoutIn order to meet the voltage drop, droop, and EMI requirements, careful PCB layout is necessary. The following guidelines must be considered:Keep all V BUS traces as short as possible and use at least 50-mil, 2 ounce copper for all V BUS traces.Avoid vias as much as possible. If vias are necessary,make them as large as feasible.Place a ground plane under all circuitry to lower both resistance and inductance and improve DC and transient performance (Use a separate ground and power plans if possible).Place cuts in the ground plane between ports to help reduce the coupling of transients between ports.Locate the output capacitor and ferrite beads as close to the USB connectors as possible to lower impedance (mainly inductance) between the port and the capacitor and improve transient load performance.Locate the RT9702/A as close as possible to the output port to limit switching noise.Locate the ceramic bypass capacitors as close as possible to the V IN pins of the RT9702/A.RICHTEK TECHNOLOGY CORP.Headquarter5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C.Tel: (8863)5526789 Fax: (8863)5526611RICHTEK TECHNOLOGY CORP.Taipei Office (Marketing)8F-1, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C.Tel: (8862)89191466 Fax: (8862)89191465Email: marketing@15DS9702/A-04 April 2004Outline DimensionA1HLSOT- 25 Surface Mount Package。
HD74ALVC2G08US中文资料
Item Propagation delay time
•
VCC = 3.3±0.3 V
Symbol tPLH tPHL Min 1.0 Typ Max 2.8 Unit ns Test conditions CL = 30 pF FROM (Input) A or B TO (Output) Y
Conditions
Output voltage range
Output : H or L VCC : OFF
Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND Maximum power dissipation *3 at Ta = 25°C (in still air) Storage temperature Notes:
Package type SSOP-8 pin Package code TTP-8DB Package suffix US Taping code E (3,000 pcs / Reel)
HD74ALVC2G08
Outline and Article Indication
• HD74ALVC2G08
µA µA µA pF
VIN = 3.6 V or GND VIN = VCC or GND, IO = 0 VIN or VO = 0 to 3.6 V VIN = VCC or GND
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.
ES6178FF中文资料
ES6178 PINOUT DIAGRAM
The device pinout for the ES6178 is shown in Figure 1.
SAM0527-052705
ES6178
Figure 1 ES6178 Device Pinout
VEE LA4 LA5 LA6 LA7 LA8 LA9 VSS VCC LA10 LA11 LA12 LA13 LA14 LA15 LA16 VSS VEE LA17 LA18 LA19 LA20 LA21 RESET# TDMDX/RSEL VSS VEE TDMDR TDMCLK TDMFS TDMTSC# TWS/SEL_PLL2 TSD0/SEL_PLL0 VSS VCC TSD1/SEL_PLL1 TSD2 TSD3 MCLK TBCK SEL_PLL3/SPDIF_OUT SPDIF_IN VSS VCC RSD RWS RBCK CAMIN3/PIXIN3 XIN XOUT AVEE AVSS 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 VSS HA1/AUX4[3] HA0/AUX4[2] HCS3FX#/AUX3[6] HCS1FX#/AUX3[7] HIOCS16#/AUX3[4]/CAMCLK/PIXIN_CLK HRD#/DCI_ACK#/AUX4[6] HWR#/DCI_CLK/AUX4[5] VEE VSS HIORDY/AUX3[3] HRST#/AUX3[5] HIRQ/DCI_ERR#/AUX4[7] HRRQ#/AUX4[0]/CAMIN2/PIXIN2 HWRQ#/DCI_REQ#/AUX4[1] HD15/AUX2[7]/IR HD14/AUX2[6] VCC VSS HD13/AUX2[5]/SP HD12/AUX2[4]/C2PO HD11/AUX2[3]//IRQ HD10/AUX2[2] HD9/AUX2[1] HD8/DCI_FDS#/AUX2[0]/VFD_CLK HD7/DCI7/AUX1[7]/VFD_DIN VEE VSS HD6/DCI6/AUX1[6]/VFD_DOUT HD5/DCI5/AUX1[5] HD4/DCI4/AUX1[4] HD3/DCI3/AUX1[3] HD2/DCI2/AUX1[2] HD1/DCI1/AUX1[1] HD0/DCI0/AUX1[0] VCC VSS HSYNC#/AUX3[0]/CAMIN7/PIXIN7 VSYNC#/AUX3[1]/CAMIN6/PIXIN6 PCLKQSCN/AUX3[2]/CAMIN5/PIXIN5 PCLK2XSCN/CAMIN4/PIXIN4 FDAC/YUV7/PIXOUT7 VDAC/YUV6/PIXOUT6 YDAC/YUV5/PIXOUT5 ADVSS ADVEE RSET/YUV4/PIXOUT4 COMP/YUV3/PIXOUT3 CDAC/YUV2/PIXOUT2 VREF/YUV1/PIXOUT1 UDAC/YUV0/PIXOUT0 DCLK
MEMORY存储芯片MAX202EPE+中文规格书
400kΩ
T1 +5V
4 T2IN
400kΩ
T2 +5V
TTL/CMOS INPUTS
14 T3IN
400kΩ
T3 +5V
15 T4IN
400kΩ
T4 +5V
19 T5IN
400kΩ T5
V+ 9
0.1µF +6.3V
V- 13
0.1µF +16V
T1OUT 2
T2OUT 3
T3OUT 1
RS-232 OUTPUTS
Benefits and Features
● Saves Board Space • Integrated Charge Pump Circuitry Eliminates the Need for a Bipolar ±12V Supply Enables Single Supply Operation From Either +5V or 9V to +12V
General Description
MAX200-MAX209, MAX211, and MAX213 are a family of RS-232 and V.28 transceivers with integrated charge pump circuitry for single +5V supply operation.
(derate 9.09mW/°C above +70°C)............................727mW 24-Pin Wide SO (derate 11.76mW/°C above +70°C)...941mW 24-Pin SSOP (derate 8.00mW/°C above +70°C).........640mW 24-Pin CERDIP (derate 12.50mW/°C above +70°C)....1000mW 28-Pin Wide SO (derate 12.50mW/°C above +70°C)...1000mW 28-Pin SSOP (derate 9.52mW/°C above +70°C).........762mW Operating Temperature Ranges MAX2_ _C_ _......................................................0°C to +70°C MAX2_ _E_ _.................................................. -40°C to +85°C MAX2_ _ M_ _............................................... -55°C to +125°C Storage Temperature Range............................. -65°C to +160°C Lead Temperature (soldering, 10s) (Note 1).................... +300°C
9702_s10_ms_22
UNIVERSITY OF CAMBRIDGE INTERNATIONAL EXAMINATIONSGCE Advanced Subsidiary Level and GCE Advanced LevelMARK SCHEME for the May/June 2010 question paperfor the guidance of teachers9702 PHYSICS9702/22 Paper 2 (AS Structured Questions)This mark scheme is published as an aid to teachers and candidates, to indicate the requirements of the examination. It shows the basis on which Examiners were instructed to award marks. It does not indicate the details of the discussions that took place at an Examiners’ meeting before marking began, which would have considered the acceptability of alternative answers.Mark schemes must be read in conjunction with the question papers and the report on the examination.•CIE will not enter into discussions or correspondence in connection with these mark schemes. CIE is publ ishing the mark schemes for the May/June 2010 question papers for most IGCSE, GCE Advanced Level and Advanced Subsidiary Level syllabuses and some Ordinary Level syllabuses.1 (a) micrometer/screw gauge/digital callipers ………………………………………. B1 [1]look/check for zero error ……………………………………………………. B1 [1](b) (i)take several readings ……………………………………………………….. M1(ii)around the circumference/along the wire …………………………………. A1 [2]2 (a) e.g. initial speed is zeroaccelerationconstantstraight line motion(any two, one mark each) ……………………………………………………………….B2 [2] s =½a t 2(b) (i)0.79 = ½ × 9.8 × t 2 ………………………………………………………….. C1t = 0.40 s allow 1 SF or greater ……………………………………………. A12 or3 SF answer ……………………………………………………….. A1 [3]distance travelled by end of time interval = 90 cm ………………………. C1(ii)0.90 = ½ × 9.8 × t 2t = 0.43 s allow 2 SF or greater ……………………………………………. C1time interval = 0.03 s ………………………………………………………... A1 [3](c)(air resistance) means ball’s speed/acceleration is less ……………………… M1length of image is shorter ………………………………………………………… A1 [2]3 (a) (i) force is rate of change of momentum ………………………………………… B1 [1](ii) force on body A is equal in magnitude to force on body B (from A) …………M1forces are in opposite directions ……………………………………………… A1forces are of the same kind ………………………………………………………A1 [3]1 F A = – F B ……………………………………………………………………. B1 [1](b) (i)2 t A = t B ……………………………………………………………………… B1 [1](ii)∆p = F A t A = – F B t B ………………………………………………………….. B1 [1] graph: momentum change occurs at same times for both spheres …………. B1(c)final momentum of sphere B is to the right …………………………………….. M1and of magnitude 5 N s …………………………………………………………… A1 [3]4 (a) e.g. no energy transferamplitude varies along its length/nodes and antinodesneighbouring points (in inter-nodal loop) vibrate in phase, etc.(any two, 1 mark each to max 2 ………………………………………………………..B2 [2](b) (i) λ= (330 × 102)/550 ………………………………………………………….. M1λ= 60cm ……………………………………………………………………… A0 [1] (ii) node labelled at piston ………………………………………………………. B1 antinode labelled at open end of tube ……………………………………… B1additional node and antinode in correct positions along tube …………… B1 [3] (c)at lowest frequency, length = λ/4 ………………………………………………... C1λ = 1.8 mfrequency = 330/1.8 ………………………………………………………………. C1180Hz ………………………………………………………………………….... A1 [3] =5 (a) (i) Young modulus = stress/strain ……………………………………………… C1data chosen using point in linear region of graph ………………………… M1Young modulus = (2.1 × 108)/(1.9 × 10–3)×1011 Pa ……………………………………………………………….. A1 [3]1.1=(ii) This mark was removed from the assessment, owing to a power-of-teninconsistency in the printed question paper.area between lines represents energy/area under curve represents energy .. M1(b)when rubber is stretched and then released/two areas are different ……...... A1this energy seen as thermal energy/heating/difference represents energyreleased as heat …………………………………………………………………… A1 [3]6 (a) either P∝V2or P = V2/R …………………………………………………………. C1reduction = (2302 – 2202)/2302= 8.5 % ………………………………………………………………….. A1 [2] zero ……………………………………………………………………………. A1 [1] (b) (i)(ii) 0.3(0)A ……………………………………………………………………….. A1 [1] correct plots to within ± 1mm ………………………………………………. B1 [1] (c) (i)reasonable line/curve through points giving current as 0.12A(ii)allow± 0.005A) ………………………………………………………………. B1 [1](iii) V = IR…………………………………………………………………………. C1 V = 0.12 × 5.0= 0.6(0)V …………………………………………………………………... A1 [2] circuit acts as a potential divider/current divides/current in AC not the same as(d)current in BC ………………………………………………………………………. B1resistance between A and C not equal to resistance between C and B ……. B1or current in wire AC × R is not equal to current in wire BC × R B1 [2] any 2 statements7 (a) (i) either helium nucleusor contains 2 protons and 2 neutrons ………………………………… B1 [1](ii) e.g. range is a few cm in air/sheet of thin paperspeed up to 0.1 ccauses dense ionisation in airpositively charged or deflected in magnetic or electric fields(any two, 1 each to max 2) ………………………………………………….. B2 [2](b) (i) α42 ……………………………………………………………………………… B1either p11or H11……………………………………………………………….. B1 [2] (ii) 1 initially, α-particle must have some kinetic energy ………………….. B1 [1]2 1.1 MeV = 1.1 × 1.6 × 10–13 = 1.76 × 10–13 J …………………………. C1(ii)E K = ½mv2 ……………………………………………………………….. C11.76 × 10–13 = ½ × 4 × 1.66 × 10–27 × v2 ……………………………… C1v = 7.3 × 106 m s–1 ……………………………………………………..... A1 [4]use of 1.67 × 10–27 kg for mass is a maximum of 3/4。
EETUQ2A272KJ中文资料(panasonic)中文数据手册「EasyDatasheet - 矽搜」
00 Nov. 2012
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铝电解电容器/ UQ
■ 标准产品
耐力：85°C 2000ħ
机箱尺寸
W.V.
Cap.
（120赫兹） Dia.
长度
(±20 %)
型号
PET套
码头长度
4.0 mm
（无顶板）
规范
最小包装台数
波纹
tan δ
当前
（120赫兹）
（120赫兹） (+20 °C)
■ 纹波电流频率修正系数
额定电压
16 V.DC to 100 V.DC /C.F. 160 V.DC to 450 V.DC /C.F.
频率（Hz）
50
60
100
120
500
1k
10 k可
0.93
0.95
0.99
1.00
1.05
1.08
1.15
0.75
0.80
0.95
1.00
1.20
1.25
1.40
0.8
4.0±0.5 2.0 max. Terminal
(t=0.8)
(3.5)
1.5±0.2
Top of spin
Standard terminal type doesnot require terminal trimming process.
Design and specifications are each subject to change without notice. Ask factory for the current technical specifications before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately.
2299327中文资料
Ambient temperature (storage/transport) Number of positions Number of positions, control side Number of connectors, control side Number of positions, module side Number of connectors, modul side Fixed cable length Single wire, cross section AWG Conductor construction: Number of litz wires: Single wire, material External diameter Cable, preassembly Shielding Certificates / Approvals
-20 °C ... 70 °C 16 16 1 16 1 2m 0.14 mm 26 7 Cu tin-plated 6.5 mm Insulation displacement, IEC 60352-4/DIN EN 60352-4 no
2
Approval logo
requested approbations Certification Certifications applied for: GOST UL / CUL
Technical data General Nominal voltage UN < 50 V AC 60 V DC Max. current carrying capacity per path Max. conductor resistance Ambient temperature (operation) 1A 0.16 Ω/m -20 °C ... 50 °C
5082-A801-KQ000中文资料
Features• Low Power Consumption • Industry Standard Size• Industry Standard Pinout • Choice of Character Size7.6 mm (0.30 in), 10 mm (0.40 in), 10.9 mm (0.43 in), 14.2 mm (0.56 in), 20 mm (0.80 in)• Choice of ColorsAlGaAs Red, High Efficiency Red (HER), Yellow, Green• Excellent Appearance Evenly Lighted Segments±50° Viewing Angle• Design FlexibilityCommon Anode or Common CathodeSingle and Dual DigitLeft and Right Hand Decimal Points±1. Overflow Character• Categorized for Luminous IntensityYellow and Green Categorized for ColorUse of Like Categories Yields a Uniform Display• Excellent for Long Digit String Multiplexing DescriptionThese low current seven segment displays are designed for applica-tions requiring low power consumption. They are tested and selected for their excellent low current characteristics to ensure that the segments are matched at low currents. Drive currents as low as 1 mA per segment are available.Pin for pin equivalent displays are also available in a standard current or high light ambient design. The standard current displays are available in all colors and are ideal for most applica-tions. The high light ambient displays are ideal for sunlight ambients or long string lengths. For additional information see the 7.6 mm Micro Bright Seven Segment Displays, 10 mm Seven Segment Displays, 7.6 mm/10.9 mm Seven Segment Displays, 14.2 mm Seven Segment Displays, 20 mm Seven Segment Displays, or High Light Ambient Seven Segment Displays data sheets.Low Current Seven SegmentDisplays Technical Data HDSP-335x SeriesHDSP-555x SeriesHDSP-751x SeriesHDSP-A10x Series HDSP-A80x Series HDSP-A90x Series HDSP-E10x Series HDSP-F10x Series HDSP-G10x Series HDSP-H10x Series HDSP-K12x, K70x Series HDSP-N10x SeriesHDSP-N40x SeriesDevicesAlGaAs HER Yellow Green Package HDSP-HDSP-HDSP-HDSP-Description Drawing A1017511A801A9017.6 mm Common Anode Right Hand Decimal A A1037513A803A9037.6 mm Common Cathode Right Hand Decimal B A1077517A807A9077.6 mm Common Anode ±1. Overflow C A1087518A808A9087.6 mm Common Cathode ±1. Overflow D F10110 mm Common Anode Right Hand Decimal E F10310 mm Common Cathode Right Hand Decimal F F10710 mm Common Anode ±1. Overflow G F10810 mm Common Cathode ±1. Overflow H G10110 mm Two Digit Common Anode Right Hand Decimal X G10310 mm Two Digit Common Cathode Right Hand Decimal Y E100335010.9 mm Common Anode Left Hand Decimal I E101335110.9 mm Common Anode Right Hand Decimal J E103335310.9 mm Common Cathode Right Hand Decimal K E106335610.9 mm Universal ±1. Overflow[1]L H101555114.2 mm Common Anode Right Hand Decimal M H103555314.2 mm Common Cathode Right Hand Decimal N H107555714.2 mm Common Anode ±1. Overflow O H108555814.2 mm Common Cathode ±1. Overflow P K121K70114.2 mm Two Digit Common Anode Right Hand Decimal R K123K70314.2 mm Two Digit Common Cathode Right Hand Decimal S N10020 mm Common Anode Left Hand Decimal Q N101N40120 mm Common Anode Right Hand Decimal T N103N40320 mm Common Cathode Right Hand Decimal U N10520 mm Common Cathode Left Hand Decimal V N106N40620 mm Universal ±1. Overflow[1]W Note:1. Universal pinout brings the anode and cathode of each segment’s LED out to separate pins. See internal diagrams L or W.Part Numbering System5082-x xx x-x x x xxHDSP-x xx x-x x x xxMechanical Options[1]00: No mechanical optionColor Bin Options[1,2]0: No color bin limitationMaximum Intensity Bin[1,2]0: No maximum intensity bin limitationMinimum Intensity Bin[1,2]0: No minimum intensity bin limitationDevice Configuration/Color[1]G: GreenDevice Specific Configuration[1]Refer to respective datasheetPackage[1]Refer to Respective datasheetNotes:1. For codes not listed in the figure above, please refer to the respective datasheet or contact your nearest Agilent representative fordetails.2. Bin options refer to shippable bins for a part-number. Color and Intensity Bins are typically restricted to 1 bin per tube (excep-tions may apply). Please refer to respective datasheet for specific bin limit information.Package DimensionsPackage Dimensions (cont.)Package Dimensions (cont.)*The Side View of package indicates Country of Origin.Package Dimensions (cont.)Package Dimensions (cont.)Package Dimensions (cont.)Internal Circuit DiagramInternal Circuit Diagram (cont.)Absolute Maximum RatingsAlGaAs Red - HDSP-HERA10X/E10X/H10X HDSP-751X/Yellow GreenK12X/N10X/N40X335X/555X/HDSP-A80X HDSP-A90X Description F10X, G10X Series K70X Series Series Series Units Average Power per Segment or DP375264mW Peak Forward Current per 45mA Segment or DPDC Forward Current per15[1]15[2]mA Segment or DPOperating Temperature Range-20 to +100-40 to +100°C Storage Temperature Range -55 to +100°C Reverse Voltage per Segment 3.0V or DPWave Soldering Temperature for 3Seconds (1.60 mm [0.063 in.] below 250°C seating body)Notes:1. Derate above 91°C at 0.53 mA/°C.2. Derate HER/Yellow above 80°C at 0.38 mA/°C and Green above 71°C at 0.31 mA/°C.Electrical/Optical Characteristics at T A = 25°CAlGaAs RedDeviceSeriesHDSP-Parameter Symbol Min.Typ.Max.Units Test Conditions315600I F = 1 mA A10x3600I F = 5 mA330650I F = 1 mAF10x, G10x3900I F = 5 mA390650I F = 1 mA E10x Luminous Intensity/Segment[1,2]I Vµcd(Digit Average)3900I F = 5 mA400700I F = 1 mAH10x, K12x4200I F = 5 mA270590I F = 1 mAN10x, N40x3500I F = 5 mA1.6I F = 1 mAForward Voltage/Segment or DP V F 1.7V I F = 5 mA1.82.2I F = 20 mA PkAll Devices Peak WavelengthλPEAK645nmDominant Wavelength[3]λd637nmReverse Voltage/Segment or DP[4]V R 3.015V I R = 100 µATemperature Coefficient of∆V F/°C-2 mV mV/°CV F/Segment or DPA10x255F10x, G10x320E10x340Thermal Resistance LED RθJ-PIN°C/W/SegH10x, K12x Junction-to-Pin400N10x, N40x430High Efficiency RedDeviceSeriesHDSP-Parameter Symbol Min.Typ.Max.Units Test Conditions160270I F = 2 mA 751x1050I F = 5 mA200300I F = 2 mA Luminous Intensity/Segment[1,2]I V mcd(Digit Average)1200I F = 5 mA335x, 555x,K70x270370I F = 2 mA1480I F = 5 mA1.6I F = 2 mAForward Voltage/Segment or DP V F 1.7V I F = 5 mA2.1 2.5I F = 20 mA Pk All Devices Peak WavelengthλPEAK635nmDominant Wavelength[3]λd626nmReverse Voltage/Segment or DP[4]V R 3.030V I R = 100 µATemperature Coefficient of∆V F/°C-2mV/°CV F/Segment or DP751x200335x Thermal Resistance LED RθJ-PIN280°C/WJunction-to-Pin555x, K70x345YellowDeviceSeriesHDSP-Parameter Symbol Min.Typ.Max.Units Test Conditions Luminous Intensity/Segment[1,2]250420I F = 4 mA(Digit Average)I V mcd1300I F = 10 mA1.7I F = 4 mAForward Voltage/Segment or DP V F 1.8V I F = 5 mA A80x2.1 2.5I F = 20 mA PkPeak WavelengthλPEAK583nmDominant Wavelength[3,5]λd581.5585592.5nmReverse Voltage/Segment or DP[4]V R 3.030V I R = 100 µATemperature Coefficient of∆V F/°C-2mV/°CV F/Segment or DPThermal Resistance LED RθJ-PIN200°C/WJunction-to-PinGreenDeviceSeriesHDSP-Parameter Symbol Min.Typ.Max.Units Test Conditions Luminous Intensity/Segment[1,2]250475I F = 4 mA(Digit Average)I V mcd1500I F = 10 mA1.9I F = 4 mAForward Voltage/Segment or DP V F 2.0V I F = 10 mA A90x2.1 2.5I F = 20 mA PkPeak WavelengthλPEAK566nmDominant Wavelength[3,5]λd571577nmReverse Voltage/Segment or DP[4]V R 3.030V I R = 100 µATemperature Coefficient of∆V F/°C-2mV/°CV F/Segment or DPThermal Resistance LED RθJ-PIN200°C/WJunction-to-PinNotes:1. Device case temperature is 25°C prior to the intensity measurement.2. The digits are categorized for luminous intensity. The intensity category is designated by a letter on the side of the package.3. The dominant wavelength, λd, is derived from the CIE chromaticity diagram and is the single wavelength which defines the color of thedevice.4. Typical specification for reference only. Do not exceed absolute maximum ratings.5. The yellow (HDSP-A800) and Green (HDSP-A900) displays are categorized for dominant wavelength. The category is designated by anumber adjacent to the luminous intensity category letter.Figure 1. Maximum AllowableAverage or DC Current vs. Ambient Temperature.Figure 2. Forward Current vs.Forward Voltage.AlGaAs RedFigure 4. Relative Efficiency (Luminous Intensity per UnitCurrent) vs. Peak Current.Figure 3. Relative Luminous Intensity vs. DC Forward Current.Figure 5. Maximum Allowable Average or DC Current vs. Ambient Temperature.Figure 6. Forward Current vs. Forward Voltage.HER, Yellow, GreenFigure 7. Relative Luminous Intensityvs. DC Forward Current.Figure 8. Relative Efficiency(Luminous Intensity per UnitCurrent) vs. Peak Current.Intensity Bin Limits (mcd)AlGaAs RedHDSP-A10xIV Bin Category Min.Max.E0.3150.520F0.4280.759G0.621 1.16H0.945 1.71I 1.40 2.56J 2.10 3.84K 3.14 5.75L 4.708.55HDSP-E10x/F10x/G10xIV Bin Category Min.Max.D0.3910.650E0.5320.923F0.755 1.39G 1.13 2.08H 1.70 3.14HDSP-H10x/K12xIV Bin Category Min.Max.C0.4150.690D0.5650.990E0.810 1.50F 1.20 2.20G 1.80 3.30H 2.73 5.00I 4.097.50HDSP-N10xIV Bin Category Min.Max.A0.2700.400B0.3250.500C0.4150.690D0.5650.990E0.810 1.50F 1.20 2.20G 1.80 3.30H 2.73 5.00I 4.097.50Intensity Bin Limits (mcd), continued HERHDSP-751xIV Bin Category Min.Max.B0.1600.240C0.2000.300D0.2500.385E0.3150.520F0.4280.759G0.621 1.16HDSP-751xIV Bin Category Min.Max.B0.2400.366C0.3000.477D0.3910.650E0.5320.923F0.755 1.39G 1.13 2.08H 1.70 3.14HDSP-555x/K70xIV Bin Category Min.Max.A0.2700.400B0.3250.500C0.4150.690D0.5650.990E0.810 1.50F 1.20 2.20G 1.80 3.30H 2.73 5.00I 4.097.50Intensity Bin Limits (mcd), continued YellowHDSP-A80xIV Bin Category Min.Max.D0.2500.385E0.3150.520F0.4250.760G0.625 1.14H0.940 1.70I 1.40 2.56J 2.10 3.84K 3.14 5.76L 4.718.64M7.0713.00N10.6019.40O15.9029.20P23.9043.80Q35.8065.60GreenHDSP-A90xIV Bin Category Min.Max.E0.3150.520F0.4250.760G0.625 1.14H0.940 1.70I 1.40 2.56J 2.10 3.84K 3.14 5.76L 4.718.64M7.0713.00N10.6019.40O15.9029.20P23.9043.80Q35.8065.60Electrical/OpticalFor more information on electrical/optical characteristics, please see Application Note 1005.Contrast Enhancement For information on contrast enhancement, please see Application Note 1015.Soldering/Cleaning Cleaning agents from the ketone family (acetone, methyl ethyl ketone, etc.) and from the chorinated hydrocarbon family (methylene chloride, trichloro-ethylene, carbon tetrachloride, etc.) are not recommended for cleaning LED parts. All of these various solvents attack or dissolve the encapsulating epoxies used to form the package of plastic LED parts.For information on soldering LEDs, please refer to Application Note 1027.Note:All categories are established for classification of products. Productsmay not be available in all categories. Please contact your localAgilent representatives for further clarification/information.Color Categories/semiconductorsFor product information and a complete list ofdistributors, please go to our web site.For technical assistance call:Americas/Canada: +1 (800) 235-0312 or(916) 788 6763Europe: +49 (0) 6441 92460China: 10800 650 0017Hong Kong: (+65) 6271 2451India, Australia, New Zealand: (+65) 6271 2394Japan: (+81 3) 3335-8152(Domestic/International), or0120-61-1280(Domestic Only)Korea: (+65) 6271 2194Malaysia, Singapore: (+65) 6271 2054Taiwan: (+65) 6271 2654Data subject to change.Copyright © 2005 Agilent Technologies, Inc.Obsoletes 5988-8412ENJanuary 19, 20055989-0080EN。
RD8.2ES资料
Document No. D13935EJ6V0DS00 (6th edition) (Previous No. DC-2140)Date Published March 1999 N CP(K) Printed in Japan©1984 DATA SHEET2Data Sheet D13935EJ6V0DS00ELECTRICAL CHARACTERISTICS (T A = 25 °C)MIN.MAX.I Z (mA)MAX.I Z (mA)MAX.I Z (mA)MAX.V R (V)AB 1.88 2.24RD2.0ESAB1 1.88 2.125100510000.51200.5AB2 2.01 2.24AB 2.11 2.44RD2.2ES AB1 2.11 2.345100510000.51200.7AB2 2.22 2.44AB 2.32 2.65RD2.4ES AB1 2.32 2.545100510000.5120 1.0AB2 2.41 2.65AB 2.52 2.93RD2.7ES AB1 2.52 2.775110510000.5100 1.0AB2 2.68 2.93AB 2.84 3.24RD3.0ES AB1 2.84 3.0851********.550 1.0AB2 2.99 3.24AB 3.15 3.54RD3.3ES AB1 3.15 3.395120510000.520 1.0AB2 3.31 3.54AB 3.46 3.84RD3.6ES AB1 3.46 3.695120511000.510 1.0AB2 3.60 3.84AB 3.74 4.16RD3.9ES AB1 3.74 4.015120512000.55 1.0AB2 3.89 4.16AB 4.04 4.57RD4.3ES AB1 4.04 4.295120512000.55 1.0AB2 4.17 4.43AB3 4.30 4.57AB 4.44 4.93RD4.7ES AB1 4.44 4.685100512000.55 1.0AB2 4.55 4.80AB3 4.68 4.93AB 4.81 5.37RD5.1ES AB1 4.81 5.0757*******.55 1.5AB2 4.94 5.20AB3 5.09 5.37AB 5.28 5.91RD5.6ES AB1 5.28 5.5554059000.55 2.5AB2 5.45 5.73AB3 5.61 5.91AB 5.78 6.44RD6.2ES AB1 5.78 6.0953055000.55 3.0AB2 5.96 6.27AB3 6.12 6.44AB 6.297.01RD6.8ES AB1 6.29 6.6352551500.52 3.5AB2 6.49 6.83AB3 6.667.01AB 6.857.67RD7.5ES AB1 6.857.2252551200.50.5 4.0AB27.077.45AB37.297.67AB 7.538.45RD8.2ES AB17.537.9252051200.50.5 5.0AB27.788.19AB38.038.45AB 8.299.30RD9.1ES AB18.298.7352051200.50.5 6.0AB28.579.01AB38.839.30AB 9.1210.39RD10ES AB19.129.6552051200.50.27.0AB29.4610.02AB39.8210.39Type NumberSuffix Zener Voltage V Z (V)Note 1Dynamic ImpedanceZ Z (Ω)Note 2Knee Dynamic Impedance Z ZK (Ω)Note 2Reverse CurrentI R (µA)3Data Sheet D13935EJ6V0DS00Type NumberSuffix Zener Voltage V Z (V)Note 1Dynamic ImpedanceZ Z (Ω)Note 2Knee Dynamic Impedance Z ZK (Ω)Note 2Reverse CurrentI R (µA)MIN.MAX.I Z (mA)MAX.I Z (mA)MAX.I Z (mA)MAX.V R (V)AB 10.1811.38RD11ESAB110.1810.7152051200.50.28.0AB210.5011.05AB310.8211.38AB 11.1312.35RD12ES AB111.1311.7152551100.50.29.0AB211.4412.03AB311.7412.35AB 12.1113.66RD13ES AB112.1112.7552551100.50.210AB212.5513.21AB312.9913.66AB 13.4415.09RD15ES AB113.4414.1352551100.50.211AB213.8914.62AB314.3515.09AB 14.8016.51RD16ES AB114.8015.5752551500.50.212AB215.2516.04AB315.6916.51AB 16.2218.33RD18ES AB116.2217.0653051500.50.213AB216.8217.70AB317.4218.33AB 18.1420.45RD20ES AB118.1419.0753052000.50.215AB218.8019.76AB319.4520.45AB 20.1522.63AB120.1521.20RD22ES AB220.6421.7153052000.50.217AB321.0822.17AB421.5222.63AB 22.0524.85AB122.0523.18RD24ES AB222.6123.7753552000.50.219AB323.1224.31AB423.6324.85AB 24.2627.64AB124.2625.52RD27ES AB224.9726.2654552500.50.221AB325.6326.95AB426.2927.64AB 26.9930.51AB126.9928.39RD30ES AB227.7029.1355552500.50.223AB328.3629.82AB429.0230.51AB 29.6833.11AB129.6831.22RD33ES AB230.3231.8856552500.50.225AB330.9032.50AB431.4933.11AB 32.1435.77AB132.1433.79RD36ES AB232.7934.4957552500.50.227AB333.4035.13AB434.0135.77AB 34.6838.52AB134.6836.47RD39ES AB235.3637.1958552500.50.230AB336.0037.85AB436.6338.52Notes 1.tested with pulse (40 ms)2.Z Z and Z ZK are measured at lz by given a very small A.C. current signal.3.Suffix AB is Suffix AB1, AB2, AB3 or AB4.4Data Sheet D13935EJ6V0DS00TYPICAL CHARACTERISTICS (T A = 25 °C)Fig. 1ZENER CURRENT vs.ZENER VOLTAGEFig. 2ZENER CURRENT vs.ZENER VOLTAGEFig. 3ZENER CURRENT vs.ZENER VOLTAGEFig. 4ZENER CURRENT vs.ZENER VOLTAGEFig. 5ZENER CURRENT vs.ZENER VOLTAGE100 m10 m 1 m100 10 1100 n 10 n 1 nV Z – Zener Voltage – VI Z – Z e n e r C u r r e n t– Aµµµ100 m10 m1 m 100 10 1 100 n 10 n 1 nV Z – Zener Voltage – VI Z – Z e n e r C u r r e n t – Aµµµ100 m10 m1 m100101 100 n10 n1 nV Z – Zener Voltage – VI Z – Z e n e r C u r r e n t – Aµµµ100 m10 m1 m100 10 1 100 n 10 n 1 nV Z – Zener Voltage – VI Z – Z e n e r C u r r e n t – Aµµµ100 m 10 m 1 m100 10 1 100 n 10 n 1 nV Z – Zener Voltage – VI Z – Z e n e r C u r r e n t – Aµµµ5Data Sheet D13935EJ6V0DS00Fig. 6POWER DISSIPATION vs.AMBIENT TEMPERATUREFig. 7THERMAL RESISTANCE vs.SIZE OF P.C BOARDFig. 8DYNAMIC IMPEDANCE vs.ZENER CURRENTFig. 9ZENER VOLTAGE TEMPERATURECOEFFICIENT vs. ZENER VOLTAGE3240241680–8–16–24–32–40γZ – V Z T e m p e r a t u r e C o e f f i c i e n c e – m V /°C500400300200100020*********T A – Ambient Temperature – °C P – P o w e r D i s s i p a t i o n – m W12014016018020050040030020010002040S – Size of P.C. Board – mm 2R t h – T h e r m a l R e s i s t a n c e – °C /W6080100Z Z – D y n a m i c I m p e d a n c e – Ωt T – Pulse Width – s6Data Sheet D13935EJ6V0DS00Fig. 11 TRANSIENT THERMAL IMPEDANCE CHARACTERISTIC1000100101t – Time – sZ t h – T r a n s i e n t T h e r m a l I m p e d a n c e – °C /W[MEMO]7Data Sheet D13935EJ6V0DS00[MEMO]•The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.•No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.•NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrightsor other intellectual property rights of NEC Corporation or others.•Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibilityof the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information.•While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features.•NEC devices are classified into the following three quality grades:"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications ofa device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application.Standard:Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronicequipment and industrial robotsSpecial:Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designedfor life support)Specific:Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc.The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.M7 98.8 2。
2SK2902中文资料(fuji)中文数据手册「EasyDatasheet - 矽搜」
VGS [V]
典型漏源通态电阻
RDS（ON）= F（ID）：为80μs脉冲试验,总胆固醇= 25°C
gfs [s]
] RDS(on) [m
ID [A]
ID [A]
2
芯片中文手册,看全文,戳
2SK2902-01MR
漏源通态电阻
RDS(on)=f(Tch):ID=22.5A,VGS=10V
] RDS(on)[m
富士功率MOSFET
栅极阈值电压与总胆固醇
VGS(th)=f(Tch):VDS=VGS,ID=10mA
VGS(th) [V]
Tch [°C]
典型栅极电荷特性
VGS=f(Qg):ID=45A,Tch=25°C
Tch [°C] 典型电容
C=f(VDS):VGS=0V,f=1MHz
VGS [V] C [F]
c = 25°C除非另有说明）
符号
BV DSS VGS(th)
IDSS
IGSS RDS(on) gf s Ciss Coss Crss td(on) tr td (of f ) tf IAV VSD trr Qrr
测试条件
ID=1mA VGS=0V ID=10mAV DS=VGS V DS=60V VGS=0V VGS=±30VV DS=0V ID=22.5AV GS=10V ID=22.5AV DS=25V V DS=25V V GS =0V f=1MHz VCC=30VI D=45A VGS=10V
RGS=10
Tch=25°C Tch=125°C
L=100 µH T ch=25°C IF=45AV GS=0VT ch=25°C IF=45AV GS=0V -di/dt=100A/µs T ch=25°C
浩康科技与Velosti发布USB3.0超高速硬件加密优盘方案说明书
设为主页 | 登录 | 现在注册 | 订阅电子快讯 | 杂志订阅首页新闻设计中心专题下载视频论坛博客小组微博在线研讨会热点搜索：Webench设计大赛谐振放大器PSoC4充电器网络分析仪尝试E源搜索，享受专业体验文章搜索高级搜索温馨提示：访问论坛和博客的设置方法[特刊] 新一期《分销与供应链特刊》订阅《EDN电子技术设计》杂志研发、品管、热分析全套红外解决方案作者: 浩康科技上网日期: 2013年05月27日打印版订阅存储器热点厂商方案推荐：加英特尔官方微博获得专业技术支持浩康科技联同Velosti发布USB3.0超高速硬件加密优盘关键字：USB3.0 硬件加密优盘浩康科技2013年5月21日，香港浩康科技（Crypton Tech）发布了USB3.0超高速AES / UCA硬件加密优盘方案。
在高速数据传输领域，数据传输速度和保密性是两个最重要的考察指标，该方案成功满足了这两个指标。
方案采用Velosti USB3.0 控制器 (以32位ARM架构为基础 )，内置AES /UCA 硬件加密机制，具有保密性好，极难破解的特点，而且速度比一般USB2.0优盘快 10 倍左右。
方案特点以ARM 32bits为基础，快速进行AES加密支持USB3.0并向下兼容 (有USB-IF USB3.0证书及FIPS加密证书 )密码输入错误10次时，优盘将自动格式化优盘采用AES硬件配合个人密码进行加密采用UCA 保密, 用户可选择只有在特定电脑上才能读取优盘资料，加强保密性，不怕密码外泄UCA 保密基于用户密码和电脑签名等信息，计算出保密信息，极难破解。
支持Mac/Windows XP/Vista/7/8系统方案内容方案采用四层沉金板，Velosti VLS5100 搭配32GB MLC ( 16GB x 2) 闪存芯片，外围元器件较少，布线简单。
浩康科技联同Velosti发布USB3.0超高速硬件加密优盘更多电子元器件Datasheet下载>>热门文章与存储相关的五项突破，彻底改变了成本与复杂性的规则东芝推出全球写入速度最快的新系列SD存储卡PMC推出12Gb/s SAS存储解决方案提升SSD闪存性能更多精品文章网友推荐相关文章与存储相关的五项突破，彻底改变了成本与复杂性的规则(2013-09-16)LSI选择Cypress并行nvSRAM非易失性存储器(2013-09-11)东芝推出全球写入速度最快的新系列SD存储卡(2013-09-09)PMC推出12Gb/s SAS存储解决方案提升SSD闪存性能(2013-09-06)2018年全球大数据市场规模将达463.4亿美元(2013-09-05)整合远程服务器和存储设备，实现安全与高效(2013-09-04)数据手册相关热门搜索最近更新元器件热门器件型号热门厂商线性调节器RT9058-25GVL表贴型晶振EQRD32A1J-106.250M交流转直流电源HLG-120H-C1050D电池管理S-8230BAB-I6T1U纸质电容PFD1C152J精彩在线研讨会EDN China > 产品新闻 > 嵌入式系统 > 存储器 > 正文 2013原创博客大赛不限话题月月给你惊喜好礼！TI WEBENCH设计大赛等你参加！投票数:收藏订阅杂志东芝TX03微控制器阵容再添新成员全球首个基于软件的Super-Resolution技...分享到:相关文章力科公司携手百佳泰等共同举办USB3.0专题...富士通推出业界领先PC外围使用的USB3.0–...与存储相关的五项突破，彻底改变了成本与...LSI选择Cypress并行nvSRAM非易失性存储器东芝推出全球写入速度最快的新系列SD存储卡PMC推出12Gb/s SAS存储解决方案提升SSD闪...编辑推荐“推特”吧，工程师们！采用非隔离驱动器的LED灯泡减小了体积与...简化多输出隔离DC-DC转换器设计的栅极驱...用1V电源使激光驱动器保护加倍恢复反激变压器的漏泄能量WinPath4处理器可扩大LTE回传网络容量我来评论您的昵称：香港的游客(您将以游客身份发表，请登录 | 注册)评论：验证码：分享：评论最多文章中移动4G商业化倒计时全年417亿砸向建... ( 3 )方块统计：一种快速估算PCB走线电阻的... ( 2 )智能机硬件“核战”:八核是噱头还是创... ( 2 )手机产业链“核战”:八核竞争难避免 ( 2 )中国发明新晶体管,提高国际芯片制造话... ( 2 )恩智浦将优势技术运用于智能交通和汽车... ( 2 )黑客帝国到来:芯片植入脑意念控制动作 ( 2 )智能手机市场:透着血腥味的强者乐园 ( 1 )一款小型化高压小功率电源的设计 ( 1 )FinFET引爆投资热半导体业战火重燃 ( 1 )商情观察2018年全球大数据市场规模将达463.4亿美元人命关天:FRAM在医疗设备中的应用现状全球速度最快嵌入式存储芯片实现量产2013年第一季度全球SSD出货劲增NAND闪存2013年第一季度意外出现短缺2013第一季度移动DRAM表现逊色新品导读LSI选择Cypress并行nvSRAM非易失性存储器东芝推出全球写入速度最快的新系列SD存储卡PMC推出12Gb/s SAS存储解决方案提升SSD闪...北京石竹科技推出迷你规格SATA 6Gbps固态...世界唯一自加密0.5TB 2.5”SATA SLC固态...恩智浦推出双向电压I2C总线转换缓冲器浩康科技联同Velosti发布USB3.0超高速硬件加密优盘《电子设计技术》网站版权所有，谢绝转载本文链接：浩康科技联同Velosti发布USB3.0超高速硬件加密优盘/ART_8800512114_29_35573_NP_63e510f0.HTM[10月16日]一堂课成为红外专家，研发、品管、热分析轻松搞定！[10月22日]新的宽禁带大功率半导体测量技术[10月23日]全新锂电池性能及安全性测试方案[10月24日] AMD嵌入式解决方案 - 针对嵌入式应用程序的DASH实施[10月29日]如何简化与测试包络跟踪功率放大器的功率附加效率测量信号微小幅度变化的示波器技巧Spansion SPI NOR Flash在嵌入式产品的应用力科示波器调制信号时频域分析嵌入式设计调试挑战与低成本综合解决方案恩智浦半导体I2C总线多路复用器和开关介绍数模转换器的信号处理应用模数转换器设计基础专题聚焦2013 IIC China第十八届国际集成电路研讨会暨展览会(IIC China)为前瞻创新技术、行业资讯交流的平台，本次展会将吸引众多国际知名厂商带来新的产业机遇...每月定期向您递送电子元器件规格书网中的最新元器件数据手册下载、库存信息及技术参数更新。
NTE2372资料
Gate–to–Source Forward Leakage Gate–to–Source Reverse Leakage Total Gate Charge Gate–to–Source Charge Gate–to–Drain (“Miller”) Charge Turn–On Delay Time Rise Time Turn–Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capaticance
元器件交易网
NTE2372 MOSFET P–Ch, Enhancement Mode High Speed Switch
Features: D Dynamic dv/dt Rating D Fast Switching D Ease of Paralleling D Simple Drive Requirements D TO220 Case Style Absolute Maximum Ratings: Continuous Drain Current (VGS = 10V), ID TC = +25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5A TC = +100°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0A Pulsed Drain Current (Note 1), IDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14A Power Dissipation (TC = +25°C), PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40W Derate Linearly Above 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.32W/°C Gate–to–Source Voltage, VGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 Inductive Current, Clamp, ILM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14A Peak Diode Recovery dv/dt (Note 2), dv/dt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0V/ns Operating Junction Temperature Range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55° to +150°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55° to +150°C Lead Temperature (During Soldering, 1.6mm from case for 10sec), TL . . . . . . . . . . . . . . . . . +300°C Mounting Torque (6–32 or M3 Screw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 lbfin (1.1Nm) Thermal Resistance, Junction–to–Case, RthJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1°C/W Thermal Resistance, Junction–to–Ambient, RthJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62°C/W Typical Thermal Resistance, Case–to–Sink (Flat, Greased Surface), RthCS . . . . . . . . . . . . 0.5°C/W Note 1. Repetitive rating; pulse width limited by maximum junction temperature. Note 2. ISD ≤ 3.5A, di/dt ≤ 95A/µs, VDD ≤ V(BR)DSS, TJ ≤ +150°C Note 3. Pules Width ≤ 300µs, Duty Cycle ≤ 2%.
LM9702中文资料
Related ProductsItem Description Part NumberDevelopment Kit LM9702 digital image processor camera development kit. This kit includesthe above mentioned camera base board, a power supply board, statusLCD board, power adapter, windows application software SNAPS DEV.LM9702DEV-KITCamera Board LM9702/04 digital image processor camera base board.LM9702CAMBOARDLM9704CAMBOARDSoftware Devlopment Kit This kit includes CR16C software development tools, National’s CameraOperating System (NCOS) & an iTAG emulator.CR16-IM02-00Compact-Flash Adaptor This is a small 16 bit CompactFlash adaptor board that can be attached tothe LM9702CamBoard/LM9704CamBoard allowing CompactFlash cards tobe connected to the main system memory busLM97COMPACFLASHSD/MMC Adaptor This is a small SD/MMC adaptor board that can be attached to theLM9702CamBoard/LM9704CamBoard allowing SD and MMC cards to beconnected to the LM9702/LM9704 digital image processorLM97SDCARDHead Boards VGA color sensor LM9627VGA monochrome sensor LM9617VGA color sensor LM9628VGA monochrome sensor LM9618128x100 monochrome sensor LM9630VGA monochrome sensor LM9637VGA color sensor LM9647SXGA monochrome sensor LM9638SXGA color sensor LM9648LM9627HEADBOARDLM9617HEADBOARDLM9628HEADBOARDLM9618HEADBOARDLM9630HEADBOARDLM9637HEADBOARDLM9647HEADBOARDLM9638HEADBOARDLM9648HEADBOARDLens Kits 1/3” lens kit for the LM9627, LM9617, LM9628 or LM96181/5” lens kit for the LM96301/4” lens kit for the LM9647, LM96371/2” lens kit for the LM9648, LM9638LM96-1/3LENSKITLM96-1/5LENSKITLM96-1/4LENSKITLM96-1/2LENSKIT LM9702 Real Time Digital Image ProcessorLIFE SUPPORT POLICYNATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into the body, or(b) support or sustain life, and whose failure to perform whenproperly used in accordance with instructions for use pro-vided in the labeling, can be reasonably expected to result ina significant injury to the user.2. A critical component is any component of a life supportdevice or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.National Semiconductor CorporationAmericasT el: 1-800-272-9959 Fax: 1-800-737-7018 Email: support @ National Semiconductor EuropeFax: +49 (0) 1 80-530 85 86Email: europe.support @ Deutsch Tel: +49 (0) 69 9508 6208English T el: +44 (0) 870 24 0 2171Francais T el: +33 (0) 1 41 91 8790National SemiconductorAsia Pacific CustomerResponse GroupTel: 65-2544466Fax: 65-2504466Email: ap.support@National SemiconductorJapan Ltd.Tel: 81-3-5639-7560Fax: 81-3-5639-7507Package Information。
9702_s02_qp_2
F = Ar v Re =
qv r
F = Br 2qv 2
9702/2 M/J02
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4 Answer all the questions in the spaces provided. 1 Make reasonable estimates of the following quantities. (a) mass of an apple mass = ............................................... kg (b) number of joules of energy in 1 kilowatt-hour number = ................................................... (c) wavelength of red light in a vacuum wavelength = ............................................... m (d) pressure due to a depth of 10 m of water pressure = .............................................. Pa [1] [1] [1] [1]
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2SC2690A中文资料(nec)中文数据手册「EasyDatasheet - 矽搜」
（1）"NEC电子"作为本声明中表示NEC电子公司,也包括它 控股子公司.
（2）"本公司产品"是指由或为NEC电子开发或制造任何产品（如 文所定义）.
M8E 02. ,f = 1.0兆赫
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hFE 分类
打标
R
Q
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60至120
100至200
备注 测试条件：V CE = 5.0 V, I C = 0.3 A
P 160至320
MIN. TYP. MAX. 单元
1.0 µA
1.0 µA 35 150
60 140 320
0.4 0.7
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1.0 1.3
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3.8 ±0.2
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2SA2690 2SA2690A
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订购信息
零件号
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2SC2690 2SC2690-AZ Note
TO-126 (MP-5) TO-126 (MP-5)
2SC2690A 2SC2690A-AZ Note
TO-126 (MP-5) TO-126 (MP-5)
注意 无铅（此产品不含Pb在外部电极）.
封 装 图 （ 单 位 ： mm）
8.5 MAX. 3.2 ±0.2
·视频设备,家用电子电器,机械工具,个人电子设备和工业机器人.
"专业"：运输设备（汽车,火车,运输舶等）,交通控制系统,防灾 系统,反犯罪系统,安全设备和医疗设备（不包括专门为生命而设计）.
TRS-9702光缆应急抢修系统说明书
2. 使用说明 .................................................................................................................. 9
2.1 光缆端头预处理 ................................................................................................................9 2.2 装载和搬运 .....................................................................................................................12 2.3 应急抢修.........................................................................................................................12 2.3.1 接续准备 ..................................................................................................................12 2.3.2 光纤接续 ..................................................................................................................13 2.3.3 接头的保护 ..............................................................................................................16 2.3.4 说明 .........................................................................................................................16 2.4 光缆回收.........................................................................................................................16 2.4.1 从光缆抢修接头盒中撤去故障光缆和应急用光缆。.................................................16 2.4.2 收存应急用光缆和装载系统 .....................................................................................17 2.5 系统使用注意事项 ..........................................................................................................18
MBM29F160TE-70PFTN中文资料
DS05-20879-2EFUJITSU SEMICONDUCTORDATA SHEETFLASH MEMORYCMOS16M (2M × 8/1M × 16) BITMBM29F160TE/BE -55/-70/-90s GENERAL DESCRIPTIONThe MBM29F160TE/BE is a 16M-bit, 5.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words of 16 bits each. The MBM29F160TE/BE is offered in a 48-pin TSOP (I) package. The device is designed to be programmed in-system with the standard system 5.0 V V CC supply. 12.0 V V PP is not required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers.The standard MBM29F160TE/BE offers access times of 55 ns, 70 ns and 90 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls.The MBM29F160TE/BE is pin and command set compatible with JEDEC standard E 2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 12.0 V Flash or EPROM devices.(Continued)s PRODUCT LINE UPMBM29F160TE-55/-70/-90/MBM29F160BE-55/-70/-90(Continued)The MBM29F160TE/BE is programmed by executing the program command sequence. This will invoke the Embedded Program TM* Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margins. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase TM* Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margins.Any individual sector is typically erased and verified in 1.0 second. (If already preprogrammed.)The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The MBM29F160TE/BE is erased when shipped from the factory.The device features single 5.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low V CC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been comleted, the device internally resets to the read mode.The MBM29F160TE/BE also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the address locations being programmed or erased. These locations need re-writing after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up firmware from the Flash memory.Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. The MBM29F160TE/BE memory electrically erases all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection.* : Embedded Erase TM and Embedded Program TM are trademarks of Advanced Micro Devices, Inc.2MBM29F160TE-55/-70/-90/MBM29F160BE-55/-70/-90s FEATURES•0.23 µm Process Technology•Single 5.0 V read, program and eraseMinimizes system level power requirements•Compatible with JEDEC-standard commandsUses same software commands as E2PROMs•Compatible with JEDEC-standard world-wide pinouts48-pin TSOP (I) (Package suffix: TN-Normal Bend Type, TR-Reversed Bend Type)•Minimum 100,000 program/erase cycles•High performance55 ns maximum access time•Sector erase architectureOne 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word modeOne 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte modeAny combination of sectors can be concurrently erased. Also supports full chip erase•Boot Code Sector ArchitectureT = Top sectorB = Bottom sector•Embedded Erase AlgorithmsAutomatically pre-programs and erases the chip or any sector•Embedded Program AlgorithmsAutomatically programs and verifies data at specified address•Data Polling and Toggle Bit feature for detection of program or erase cycle completion•Ready/Busy output (RY/BY)Hardware method for detection of program or erase cycle completion•Low V CC write inhibit ≤ 4.2 V•Erase Suspend/ResumeSuspends the erase operation to allow a read data and/or program in another sector within the same devic •Hardware RESET pinResets internal state machine to the read mode•Sector protectionHardware method disables any combination of sectors from program or erase operations•Temporary sector unprotectionTemporary sector unprotection via the RESET pin•In accordance with CFI (Common Flash Memory Interface)•WP Input pin (Hardware Protect)At V IL, allows protection of boot sectors, regardless of sector protection/unprotection statusAt V IH, allows removal of boot sector protectionAt open, allows removal of boot sector protection (MBM29F160TE/BE)3MBM29F160TE-55/-70/-90/MBM29F160BE-55/-70/-90 s PIN ASSIGNMENT4MBM29F160TE-55/-70/-90/MBM29F160BE-55/-70/-90 s BLOCK DIAGRAM5MBM29F160TE-55/-70/-90/MBM29F160BE-55/-70/-90s FLEXIBLE SECTOR-ERASE ARCHITECTURE•One 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word mode.•One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte mode.•Individual-sector, multiple-sector, or bulk-erase capability.•Individual or multiple-sector protection is user definable.Sector Sector Size(× 8) Address Range(× 16) Address Range SA064 Kbytes or 32 Kwords00000H to 0FFFFH00000H to 07FFFH SA164 Kbytes or 32 Kwords10000H to 1FFFFH08000H to 0FFFFH SA264 Kbytes or 32 Kwords20000H to 2FFFFH10000H to 17FFFH SA364 Kbytes or 32 Kwords30000H to 3FFFFH18000H to 1FFFFH SA464 Kbytes or 32 Kwords40000H to 4FFFFH20000H to 27FFFH SA564 Kbytes or 32 Kwords50000H to 5FFFFH28000H to 2FFFFH SA664 Kbytes or 32 Kwords60000H to 6FFFFH30000H to 37FFFH SA764 Kbytes or 32 Kwords70000H to 7FFFFH38000H to 3FFFFH SA864 Kbytes or 32 Kwords80000H to 8FFFFH40000H to 47FFFH SA964 Kbytes or 32 Kwords90000H to 9FFFFH48000H to 4FFFFH SA1064 Kbytes or 32 Kwords A0000H to AFFFFH50000H to 57FFFH SA1164 Kbytes or 32 Kwords B0000H to BFFFFH58000H to 5FFFFH SA1264 Kbytes or 32 Kwords C0000H to CFFFFH60000H to 67FFFH SA1364 Kbytes or 32 Kwords D0000H to DFFFFH68000H to 6FFFFH SA1464 Kbytes or 32 Kwords E0000H to EFFFFH70000H to 77FFFH SA1564 Kbytes or 32 Kwords F0000H to FFFFFH78000H to 7FFFFH SA1664 Kbytes or 32 Kwords100000H to 10FFFFH80000H to 87FFFH SA1764 Kbytes or 32 Kwords110000H to 11FFFFH88000H to 8FFFFH SA1864 Kbytes or 32 Kwords120000H to 12FFFFH90000H to 97FFFH SA1964 Kbytes or 32 Kwords130000H to 13FFFFH98000H to 9FFFFH SA2064 Kbytes or 32 Kwords140000H to 14FFFFH A0000H to A7FFFH SA2164 Kbytes or 32 Kwords150000H to 15FFFFH A8000H to AFFFFH SA2264 Kbytes or 32 Kwords160000H to 16FFFFH B0000H to B7FFFH SA2364 Kbytes or 32 Kwords170000H to 17FFFFH B8000H to BFFFFH SA2464 Kbytes or 32 Kwords180000H to 18FFFFH C0000H to C7FFFH SA2564 Kbytes or 32 Kwords190000H to 19FFFFH C8000H to CFFFFH SA2664 Kbytes or 32 Kwords1A0000H to 1AFFFFH D0000H to D7FFFH SA2764 Kbytes or 32 Kwords1B0000H to 1BFFFFH D8000H to DFFFFH SA2864 Kbytes or 32 Kwords1C0000H to 1CFFFFH E0000H to E7FFFH SA2964 Kbytes or 32 Kwords1D0000H to 1DFFFFH E8000H to EFFFFH SA3064 Kbytes or 32 Kwords1E0000H to 1EFFFFH F0000H to F7FFFH SA3132 Kbytes or 16 Kwords1F0000H to 1F7FFFH F8000H to FBFFFH SA328 Kbytes or 4 Kwords1F8000H to 1F9FFFH FC000H to FCFFFH SA338 Kbytes or 4 Kwords1FA000H to 1FBFFFH FD000H to FDFFFH SA3416 Kbytes or 8 Kwords1FC000H to 1FFFFFH FE000H to FFFFFHMBM29F160TE Top Boot Sector Architecture6MBM29F160TE-55/-70/-90/MBM29F160BE-55/-70/-90Sector Sector Size(× 8) Address Range(× 16) Address RangeSA016 Kbytes or 8 Kwords00000H to 03FFFH00000H to 01FFFHSA18 Kbytes or 4 Kwords04000H to 05FFFH02000H to 02FFFHSA28 Kbytes or 4 Kwords06000H to 07FFFH03000H to 03FFFHSA332 Kbytes or 16 Kwords08000H to 0FFFFH04000H to 07FFFHSA464 Kbytes or 32 Kwords10000H to 1FFFFH08000H to 0FFFFHSA564 Kbytes or 32 Kwords20000H to 2FFFFH10000H to 17FFFHSA664 Kbytes or 32 Kwords30000H to 3FFFFH18000H to 1FFFFHSA764 Kbytes or 32 Kwords40000H to 4FFFFH20000H to 27FFFHSA864 Kbytes or 32 Kwords50000H to 5FFFFH28000H to 2FFFFHSA964 Kbytes or 32 Kwords60000H to 6FFFFH30000H to 37FFFHSA1064 Kbytes or 32 Kwords70000H to 7FFFFH38000H to 3FFFFHSA1164 Kbytes or 32 Kwords80000H to 8FFFFH40000H to 47FFFHSA1264 Kbytes or 32 Kwords90000H to 9FFFFH48000H to 4FFFFHSA1364 Kbytes or 32 Kwords A0000H to AFFFFH50000H to 57FFFHSA1464 Kbytes or 32 Kwords B0000H to BFFFFH58000H to 5FFFFHSA1564 Kbytes or 32 Kwords C0000H to CFFFFH60000H to 67FFFHSA1664 Kbytes or 32 Kwords D0000H to DFFFFH68000H to 6FFFFHSA1764 Kbytes or 32 Kwords E0000H to EFFFFH70000H to 77FFFHSA1864 Kbytes or 32 Kwords F0000H to FFFFFH78000H to 7FFFFHSA1964 Kbytes or 32 Kwords100000H to 10FFFFH80000H to 87FFFHSA2064 Kbytes or 32 Kwords110000H to 11FFFFH88000H to 8FFFFHSA2164 Kbytes or 32 Kwords120000H to 12FFFFH90000H to 97FFFHSA2264 Kbytes or 32 Kwords130000H to 13FFFFH98000H to 9FFFFHSA2364 Kbytes or 32 Kwords140000H to 14FFFFH A0000H to A7FFFHSA2464 Kbytes or 32 Kwords150000H to 15FFFFH A8000H to AFFFFHSA2564 Kbytes or 32 Kwords160000H to 16FFFFH B0000H to B7FFFHSA2664 Kbytes or 32 Kwords170000H to 17FFFFH B8000H to BFFFFHSA2764 Kbytes or 32 Kwords180000H to 18FFFFH C0000H to C7FFFHSA2864 Kbytes or 32 Kwords190000H to 19FFFFH C8000H to CFFFFHSA2964 Kbytes or 32 Kwords1A0000H to 1AFFFFH D0000H to D7FFFHSA3064 Kbytes or 32 Kwords1B0000H to 1BFFFFH D8000H to DFFFFHSA3164 Kbytes or 32 Kwords1C0000H to 1CFFFFH E0000H to E7FFFHSA3264 Kbytes or 32 Kwords1D0000H to 1DFFFFH E8000H to EFFFFHSA3364 Kbytes or 32 Kwords1E0000H to 1EFFFFH F0000H to F7FFFHSA3464 Kbytes or 32 Kwords1F0000H to 1FFFFFH F8000H to FFFFFHMBM29F160BE Bottom Boot Sector Architecture7MBM29F160TE -55/-70/-90/MBM29F160BE -55/-70/-908s LOGIC SYMBOLLTable 1 MBM29L V160TE/BE Pin Configuration PinFunctionA -1, A 0 to A 19Address Inputs DQ 0 to DQ 15Data Inputs/Outputs CE Chip Enable OE Output Enable WE Write Enable RY/BY Ready/Busy OutputRESET Hardware Reset Pin/T emporary Sector Unprotection BYTE Selects 8-bit or 16-bit mode N.C.Pin Not Connected Internally V SS Device GroundV CCDevice Power SupplyMBM29F160TE -55/-70/-90/MBM29F160BE -55/-70/-909s DEVICE BUS OPERATIONSLegend: L = V IL , H = V IH , X = V IL or V IH . = pulse input. See DC Characteristics for voltage levels.Notes:1.Manufacturer and device codes may also be accessed via a command register write sequence. SeeTable 7.2.Refer to the section on Sector Protection.3.WE can be V IL if OE is V IL , OE at V IH initiates the write operations.4.V CC =5.0 V ±10%Table 2 MBM29F160TE/BE User Bus Operation (BYTE = V IH )OperationCE OE WE A 0A 1A 6A 9DQ 0 to DQ 15RESET WP Auto-Select Manufacture Code (1)L L H L L L V ID Code H X Auto-Select Device Code (1)L L H H L L V ID Code H X Read (3)L L H A 0A 1A 6A 9D OUT H X Standby H X X X X X X HIGH-Z H X Output Disable L H H X X X X HIGH-Z H X Write (Program/Erase)L H LA 0A 1A 6A 9D IN H X Enable Sector Protection (2), (4)L V ID L H L V ID X H X Verify Sector Protection (2), (4)L L H L H L V ID Code H X Temporary Sector Unprotection X X X X X X X X V ID X Reset (Hardware)/Standby X X X X X X X HIGH-Z L X Boot Block Write ProtectionXXX XXXXXXLTable 3 MBM29F160TE/BE User Bus Operation (BYTE = V IL )OperationCE OE WE DQ 15/A -1A 0A 1A 6A 9DQ 0 to DQ 7RESET WP Auto-Select Manufacture Code (1)L L H L L L L V ID Code H X Auto-Select Device Code (1)L L H L H L L V ID Code H X Read (3)L L H A -1A 0A 1A 6A 9D OUT H X Standby H X X X X X X X HIGH-Z H X Output Disable L H H X X X X X HIGH-Z H X Write (Program/Erase)L H LA -1A 0A 1A 6A 9D IN H X Enable Sector Protection (2), (4)L V ID L L H L V ID X H X Verify Sector Protection (2), (4)L L H L L H L V ID Code H X Temporary Sector Unprotection X X X X X X X X X V ID X Reset (Hardware)/Standby X X X X X X X X HIGH-Z L X Boot Block Write ProtectionXXXXXXXXXXLMBM29F160TE-55/-70/-90/MBM29F160BE-55/-70/-90s FUNCTIONAL DESCRIPTIONRead ModeThe MBM29F160TE/BE has two control functions which must be satisfied in order to obtain data at the outputs.CE is the power control and should be used for a device selection. OE is the output control and should be used to gate data to the output pins if a device is selected.Address access time (t ACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (t CE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the addresses have been stable for at least t ACC - t OE time.) When reading out a data without changing addresses after power-u, it is necessary to input hardware reset or change CE pin from "H" tp "L".Standby ModeThere are two ways to implement the standby mode on the MBM29F160TE/BE devices. One is by using both the CE and RESET pins; the other via the RESET pin only.When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at V CC ±0.3 V.Under this condition the current consumed is less than 5 µA max. During Embedded Algorithm operation, V CC Active current (I CC2) is required even CE = “H”. The device can be read with standard access time (t CE) from either of these standby modes.When using the RESET pin only, a CMOS standby mode is achieved with the RESET input held at V SS ±0.3 V (CE = “H” or “L”). Under this condition the current consumed is less than 5 µA max. Once the RESET pin is taken high, the device requires t RH of wake up time before outputs are valid for read access.In the standby mode, the outputs are in the high-impedance state, independent of the OE input.Output DisableIf the OE input is at a logic high level (V IH), output from the device is disabled. This will cause the output pins to be in a high-impedance state.AutoselectThe Autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. The intent is to allow programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. The Autoselect command may also be used to check the status of write-protected sectors. (See Tables 4.1 and 4.2.) This mode is functional over the entire temperature range of the device.To activate this mode, the programming equipment must force V ID (11.5 V to 12.5 V) on address pin A9. Two identifier bytes may then be sequenced from the devices outputs by toggling address A0 from V IL to V IH. All addresses are DON’T CARES except A0, A1, and A6 (A-1). (See Table 2 or Table 3.)The manufacturer and device codes may also be read via the command register, for instances when the MBM29F160TE/BE is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 6, Command Definitions.Byte 0 (A0 = V IL) represents the manufacture’s code (Fujitsu = 04H) and byte 1 (A0 = V IH) represents the device identifier code (MBM29F160TE = D2H and MBM29F160BE = D8H for x 8 mode; MBM29F160TE = 22D2H and MBM29F160BE = 22D8H for x 16 mode). These two bytes/words are given in the Table 4.1 and 4.2. All identifiers for manufactures and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the Autoselect, A1 must be V IL. (See Tables 4.1 and 4.2.)10MBM29F160TE -55/-70/-90/MBM29F160BE -55/-70/-90*1:A -1 is for Byte mode.*2:Outputs 01H at protected sector addresses and outputs 00H at unprotected sector addresses.(B): Byte mode (W): Word modeTable 4.1 MBM29F160TE/BE Sector Protection Verify Autoselect Code TypeA 12 to A 19A 6A 1A 0A -1*1Code (HEX)Manufacture’s CodeXV IL V IL V IL V IL 04H Device CodeMBM29F160TEByte XV ILV ILV IHV IL D2H Word X 22D2H MBM29F160BEByte X V IL V IL V IH V IL D8H WordX 22D8H Sector Protection Sector AddressesV ILV IHV ILV IL01H*2Table 4.2 Expanded Autoselect Code TableTypeCode DQ 15DQ 14DQ 13DQ 12DQ 11DQ 10DQ 9DQ 8DQ 7DQ 6DQ 5DQ 4DQ 3DQ 2DQ 1DQ 0Manufacture’s Code04H A -1/0000000000000100Device CodeMBM29F160TE(B)D2H A -1HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 11010010(W)22D2H 01111010010MBM29F160BE(B)D8H A -1HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 11001000(W)22D8H010001011001000Sector Protection 01H A -1/01MBM29F160TE-55/-70/-90/MBM29F160BE-55/-70/-90Table 5 Sector Address Tables (MBM29F160TE)SectorAddress A19A18A17A16A15A14A13A12(× 8) Address Range(× 16) Address Range SA000000X X X00000H to 0FFFFH00000H to 07FFFH SA100001X X X10000H to 1FFFFH08000H to 0FFFFH SA200010X X X20000H to 2FFFFH10000H to 17FFFH SA300011X X X30000H to 3FFFFH18000H to 1FFFFH SA400100X X X40000H to 4FFFFH20000H to 27FFFH SA500101X X X50000H to 5FFFFH28000H to 2FFFFH SA600110X X X60000H to 6FFFFH30000H to 37FFFH SA700111X X X70000H to 7FFFFH38000H to 3FFFFH SA801000X X X80000H to 8FFFFH40000H to 47FFFH SA901001X X X90000H to 9FFFFH48000H to 4FFFFH SA1001010X X X A0000H to AFFFFH50000H to 57FFFH SA1101011X X X B0000H to BFFFFH58000H to 5FFFFH SA1201100X X X C0000H to CFFFFH60000H to 67FFFH SA1301101X X X D0000H to DFFFFH68000H to 6FFFFH SA1401110X X X E0000H to EFFFFH70000H to 77FFFH SA1501111X X X F0000H to FFFFFH78000H to 7FFFFH SA1610000X X X100000H to 10FFFFH80000H to 87FFFH SA1710001X X X110000H to 11FFFFH88000H to 8FFFFH SA1810010X X X120000H to 12FFFFH90000H to 97FFFH SA1910011X X X130000H to 13FFFFH98000H to 9FFFFH SA2010100X X X140000H to 14FFFFH A0000H to A7FFFH SA2110101X X X150000H to 15FFFFH A8000H to AFFFFH SA2210110X X X160000H to 16FFFFH B0000H to B7FFFH SA2310111X X X170000H to 17FFFFH B8000H to BFFFFH SA2411000X X X180000H to 18FFFFH C0000H to C7FFFH SA2511001X X X190000H to 19FFFFH C8000H to CFFFFH SA2611010X X X1A0000H to 1AFFFFH D0000H to D7FFFH SA2711011X X X1B0000H to 1BFFFFH D8000H to DFFFFH SA2811100X X X1C0000H to 1CFFFFH E0000H to E7FFFH SA2911101X X X1D0000H to 1DFFFFH E8000H to EFFFFH SA3011110X X X1E0000H to 1EFFFFH F0000H to F7FFFH SA31111110X X1F0000H to1F7FFFH F8000H to FBFFFH SA32111111001F8000H to1F9FFFH FC000H to FCFFFH SA33111111011FA000H to1FBFFFH FD000H to FDFFFHMBM29F160TE-55/-70/-90/MBM29F160BE-55/-70/-90Table 6 Sector Address Tables (MBM29F160BE)SectorAddress A19A18A17A16A15A14A13A12(× 8) Address Range(× 16) Address Range SA00000000X00000H to 03FFFH00000H to 01FFFH SA10000001004000H to 05FFFH02000H to 02FFFH SA20000001106000H to 07FFFH03000H to 03FFFH SA30000010X08000H to 0FFFFH04000H to 07FFFH SA400001X X X10000H to 1FFFFH08000H to 0FFFFH SA500010X X X20000H to 2FFFFH10000H to 17FFFH SA600011X X X30000H to 3FFFFH18000H to 1FFFFH SA700100X X X40000H to 4FFFFH20000H to 27FFFH SA800101X X X50000H to 5FFFFH28000H to 2FFFFH SA900110X X X60000H to 6FFFFH30000H to 37FFFH SA1000111X X X70000H to 7FFFFH38000H to 3FFFFH SA1101000X X X80000H to 8FFFFH40000H to 47FFFH SA1201001X X X90000H to 9FFFFH48000H to 4FFFFH SA1301010X X X A0000H to AFFFFH50000H to 57FFFH SA1401011X X X B0000H to BFFFFH58000H to 5FFFFH SA1501100X X X C0000H to CFFFFH60000H to 67FFFH SA1601101X X X D0000H to DFFFFH68000H to 6FFFFH SA1701110X X X E0000H to EFFFFH70000H to 77FFFH SA1801111X X X F0000H to FFFFFH78000H to 7FFFFH SA1910000X X X100000H to 1FFFFFH80000H to 87FFFH SA2010001X X X110000H to 11FFFFH88000H to 8FFFFH SA2110010X X X120000H to 12FFFFH90000H to 97FFFH SA2210011X X X130000H to 13FFFFH98000H to 9FFFFH SA2310100X X X140000H to 14FFFFH A0000H to A7FFFH SA2410101X X X150000H to 15FFFFH A8000H to 8FFFFH SA2510110X X X160000H to 16FFFFH B0000H to B7FFFH SA2610111X X X170000H to 17FFFFH B8000H to BFFFFH SA2711000X X X180000H to 18FFFFH C0000H to C7FFFH SA2811001X X X190000H to 19FFFFH C8000H to CFFFFH SA2911010X X X1A0000H to 1AFFFFH D0000H to D7FFFH SA3011011X X X1B0000H to 1BFFFFH D8000H to DFFFFH SA3111100X X X1C0000H to 1CFFFFH E0000H to E7FFFH SA3211101X X X1D0000H to 1DFFFFH E8000H to EFFFFH SA3311110X X X1E0000H to 1EFFFFH F0000H to F7FFFHMBM29F160TE-55/-70/-90/MBM29F160BE-55/-70/-90WriteDevice erasure and programming are accomplished via the command register. The command register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device.The command register itself does not occupy any addressable memory location. The register is latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to V IL, while CE is at V IL and OE is at V IH. Addresses are latched on the falling edge of CE or WE, whichever occurs later, while data is latched on the rising edge of CE or WE pulse, whichever occurs first. Standard microprocessor write timings are used.Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. Write Protect (WP)The write Protect function provides a hardware method of protecting certain boot sectors without using V ID.If the system asserts V IL on the WP pin, the device disables program and erase functions in the "outermost" 16K byte boot sectors independently of whether this sector was protected or unprotected using the method described in "Sector / Sector Block Protection and Unprotection". The outmost 16K byte boot sector is the sector containing the lowest addresses in a bottom-boot-configured devices, or the sector containing the highest addresses in a top-boot-configured device.If the system asserts V IH on the WP pin, the devices reverts to whether the outmost 16K byte boot sector was last set to be protected or unprotected. That is, sector protection or unprotection for this sector depends on whether it was last protected or unprotected using the method describe in "Sector / Sector Block Protection and Unprotection".Sector ProtectionThe MBM29F160TE/BE features hardware sector protection. This feature will disable both program and erase operations in any number of sectors (0 through 34). The sector protection feature is enabled using programming equipment at the user’s site. The device is shipped with all sectors unprotected.To activate this mode, the programming equipment must force V ID on address pin A9 and control pin OE, (suggest V ID = 11.5V), CE = V IL, and A6 = V IL. The sector addresses (A19, A18, A17, A16, A15, A14, A13, and A12) should be set to the sector to be protected. Tables 5 and 6 define the sector address for each of the thirty five (35) individual sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector addresses must be held constant during the WE pulse. See figures 16 and 24 for sector protection waveforms and algorithm.To verify programming of the protection circuitry, the programming equipment must force V ID on address pin A9 with CE and OE at V IL and WE at V IH. Scanning the sector addresses (A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the devices will read 00H for unprotected sector. In this mode, the lower order addresses, except for A0, A1, and A6 are DON’T CARES. Address locations with A1 = V IL are reserved for Autoselect manufacturer and device codes. A-1 requires to apply to V IL in byte mode.It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performinga read operation at the address location XX02H, where the higher order addresses pins (A19, A18, A17, A16, A15,A14, A13, and A12) represents the sector address will produce a logical “1” at DQ0 for a protected sector. See Tables 4.1 and 4.2 for Autoselect codes.Temporary Sector UnprotectionThis feature allows temporary unprotection of previously protected sectors of the MBM29F160TE/BE devices in order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage(12 V). During this mode, formerly protected sectors can be programmed or erased by selecting the sectorMBM29F160TE -55/-70/-90/MBM29F160BE -55/-70/-90Notes:1.Address bits A 11 to A 19 = X = “H” or “L” for all address commands except or Program Address (PA) andSector Address (SA).2.Bus operations are defined in Tables 2 and3.3.RA =Address of the memory location to be read.PA =Address of the memory location to be programmed. Addresses are latched on the falling edge ofthe WE pulse.SA =Address of the sector to be erased. The combination of A 19, A 18, A 17, A 16, A 15, A 14, A 13, and A 12 willuniquely select any sector.4.RD =Data read from location RA during read operation.PD =Data to be programmed at location PA. Data is latched on the rising edge of WE.5.The system should generate the following address patterns:Word Mode: 555H or 2AAH to addresses A 0 to A 10Byte Mode: AAAH or 555H to addresses A -1 to A 106.Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.Table 7 MBM29F160TE/BE Standard Command DefinitionsCommand Sequence (Notes 1, 2, 3, 5)Bus Write Cycles Req'dFirst Bus Write Cycle Second Bus Write Cycle Third Bus Write Cycle Fourth Bus Read/Write Cycle Fifth Bus Write Cycle Sixth Bus Write Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read/Reset (Note 6)Word/Byte 1XXXH F0H RA RD ————————Read/Reset (Note 6)Word 3555H AAH 2AAH 55H 555H F0H RA RD ————Byte AAAH 555H AAAH Autoselect Word 3555H AAH 2AAH 55H 555H 90H ——————Byte AAAH 555H AAAH Byte/Word Program (Notes 3, 4)Word 4555H AAH 2AAH 55H 555H A0H PA PD ————Byte AAAH 555H AAAH Chip EraseWord 6555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H Byte AAAH 555H AAAH AAAH 555H AAH Sector Erase (Note 3)Word 6555H AAH2AAH 55H555H 80H555H AAH2AAH 55HSA30HByte AAAH555HAAAHAAAH555HSector Erase Suspend Word /Byte 1Erase can be suspended during sector erase with addr. ("H" or "L"). Data (B0H)Sector Erase ResumeWord /Byte1Erase can be resumed after suspend with addr. ("H" or "L"). Data (30H)。
ES2G中文资料
ES2G
2.0A SURFACE MOUNT SUPER-FAST RECTIFIER Features
NEW PRODUCT
· · · · · ·
Glass Passivated Die Construction Super-Fast Recovery Time For High Efficiency Low Forward Voltage Drop and High Current Capability Surge Overload Rating to 50A Peak Ideally Suited for Automated Assembly Plastic Material: UL Flammability Classification Rating 94V-0
(+) (-)
0A -0.25A
1.0Ω NI
Oscilloscope (Note 1)
(+)
Notes: 1. Rise Time = 7.0ns max. Input Impedance = 1.0MΩ, 22pF. 2. Rise Time = 10ns max. Input Impedance = 50Ω.
B
SMB Dim A Min 3.30 4.06 1.96 0.15 5.00 0.10 0.76 2.00 Max 3.94 4.57 2.21 0.31 5.59 0.20 1.52 2.62
A
C
B C D E G H J
Mechanical Data
· · · · · Case: Molded Plastic Terminals: Solder Plated Terminal Solderable per MIL-STD-202, Method 208 Polarity: Cathode Band or Cathode Notch Weight: 0.093 grams (approx.) Marking: Type Number
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Description
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing recommended. R Counter bit0 (LSB). R Counter bit1. R Counter bit2. R Counter bit3. Ground. Parallel data bus bit0 (LSB). M Counter bit0 (LSB). Parallel data bus bit1. M Counter bit1. Parallel data bus bit2. M Counter bit2. Parallel data bus bit3. M Counter bit3. Same as pin 1. Same as pin 1. Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary register data is transferred to the secondary register on S_WR or Hop_WR rising edge.
Interface Mode
ALL Direct Direct Direct Direct ALL Parallel Direct Parallel Direct Parallel Direct Parallel Direct ALL ALL Serial
Type
(Note 1) Input Input Input Input (Note 1) Input Input Input Input Input Input Input Input (Note 1) (Note 1) Input
Fin Fin
Prescaler 10 / 11
Main Counter 13
fpห้องสมุดไป่ตู้
D(7:0) 8 Sdata Pre_en M(6:0) A(3:0) R(3:0) fr
Primary 20-bit 20 Latch
Secondary 20-bit Latch
20 20
20 16
Phase Detector
File No. 70/0036~00C |
9
D2 M2
10
D3 M3
11 12 13
VDD VDD S_WR
Copyright Peregrine Semiconductor Corp. 2003
UTSi CMOS RFIC SOLUTIONS
Page 2 of 15
PE9702
Advance Information
FSELP, A0 E_WR, A1 M2_WR, A2 Smode, A3 Bmode VDD M1_WR A_WR Hop_WR Fin Fin
Table 1. Pin Descriptions
Pin No.
1 2 3 4 5 6 7 8
Pin Name
VDD R0 R1 R2 R3 GND D0 M0 D1 M1
Advance Information
Figure 2. Pin Configuration
GND GND GND Enh VDD LD R3 R2 R1 R0 fr
6
D0, M0 D1, M1 D2, M2 D3, M3 VDD VDD S_WR, D4, M4 Sdata, D5, M5 Sclk, D6, M6 FSELS, D7, Pre_en GND
Pin No.
Pin Name
D4 M4 Sdata
Interface Mode
Parallel Direct Serial Parallel Direct Serial Parallel Direct Serial Parallel Direct ALL Parallel Direct Serial
Type
Input Input Input Input Input Input Input Input Input Input Input Parallel data bus bit4 M Counter bit4
Description
Binary serial data input. Input data entered MSB first. Parallel data bus bit5. M Counter bit5. Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk. Parallel data bus bit6. M Counter bit6. Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for programming of internal counters while in Serial Interface Mode. Parallel data bus bit7 (MSB). Prescaler enable, active “low”. When “high”, Fin bypasses the prescaler. Ground.
14
D5 M5 Sclk
15
D6 M6 FSELS
16
D7
Pre_en
17
GND FSELP A0
18
Input Input Input Input Input Input Input Input Input Input (Note 1) Input Input Input Input Input
Selects contents of primary register (FSELP=1) or secondary register (FSELP=0) for programming of internal counters while in Parallel Interface Mode. A Counter bit0 (LSB). Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into the enhancement register on the rising edge of Sclk. Enhancement register write. D[7:0] are latched into the enhancement register on the rising edge of E_WR. A Counter bit1. M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising edge of M2_WR. A Counter bit2. Selects serial bus interface mode (Bmode=0, Smode=1) or Parallel Interface Mode (Bmode=0, Smode=0). A Counter bit3 (MSB). Selects direct interface mode (Bmode=1). Same as pin 1. M1 write. D[7:0] are latched into the primary register (Pre_en, M[6:0]) on the rising edge of M1_WR. A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising edge of A_WR. Hop write. The contents of the primary register are latched into the secondary register on the rising edge of Hop_WR. Prescaler input from the VCO. 3.0 GHz max frequency. Prescaler complementary input. A bypass capacitor in series with a 51 Ω resistor should be placed as close as possible to this pin and be connected directly to the ground plane. Ground.
3.0 GHz Integer-N PLL for Rad Hard Applications
Features • 3.0 GHz operation • ÷10/11 dual modulus prescaler • Internal phase detector • Serial, parallel or hardwired programmable • Ultra-low phase noise • SEU < 10-9 errors / bit-day • 100 Krad (Si) total dose • 44-lead CQFJ
5
4
3
2
1
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
fc VDD_fc PD_U PD_D VDD Cext VDD Dout VDD_fp fp GND