SED1278DOA中文资料
ADC12138CIMSA资料
ADC12130/ADC12132/ADC12138Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/HoldGeneral DescriptionThe ADC12130,ADC12132and ADC12138are 12-bit plus sign successive approximation A/D converters with serial I/O and configurable input multiplexer.The ADC12132and ADC12138have a 2and an 8channel multiplexer,respec-tively.The differential multiplexer outputs and A/D inputs are available on the MUXOUT1,MUXOUT2,A/DIN1and A/DIN2pins.The ADC12130has a two channel multiplexer with the multiplexer outputs and A/D inputs internally connected.The ADC12130family is tested with a 5MHz clock.On request,these A/Ds go through a self calibration process that adjusts linearity,zero and full-scale errors to typically less than ±1LSB each.The analog inputs can be configured to operate in various combinations of single-ended,differential,or pseudo-differential modes.A fully differential unipolar analog input range (0V to +5V)can be accommodated with a single +5V supply.In the differential modes,valid outputs are ob-tained even when the negative inputs are greater than the positive because of the 12-bit plus sign output data format.The serial I/O is configured to comply with the NSC MI-CROWIRE ™.For voltage references,see the LM4040or LM4041.Featuresn Serial I/O (MICROWIRE,SPI and QSPI Compatible)n 2or 8channel differential or single-ended multiplexer n Analog input sample/hold function n Power down moden Programmable acquisition timen Variable digital output word length and format n No zero or full scale adjustment requiredn0V to 5V analog input range with single 5V power supplyKey Specificationsn Resolution:12-bit plus signn 12-bit plus sign conversion time:8.8µs (max)n 12-bit plus sign throughput time:14µs (max)n Integral linearity error:±2LSB (max)n Single supply: 3.3V or 5V ±10%nPower consumption —3.3V 15mW (max)—3.3V power down 40µW (typ)—5V 33mW (max)—5V power down 100µW (typ)Applicationsn Pen-based computers n Digitizersn Global positioning systemsADC12138Simplified Block DiagramTRI-STATE ®is a registered trademark of National Semiconductor Corporation.COPS ™microcontrollers,HPC ™and MICROWIRE ™are trademarks of National Semiconductor Corporation.DS012079-1March 2000ADC12130/ADC12132/ADC12138Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold©2000National Semiconductor Corporation Ordering InformationIndustrial Temperature Range−40˚C ≤T A ≤+85˚C NS Package Number ADC12130CIN N16E,Dual-In-Line ADC12130CIWM M16B,Wide Body SOADC12132CIMSA MSA20,SSOP ADC12138CIN N28B,Dual-In-LineADC12138CIWM M28B ADC12138CIMSAMSA28,SSOPConnection Diagrams16-Pin Dual-In-Line and Wide Body SO PackagesDS012079-2Top View20-Pin SSOP PackageDS012079-47Top View28-Pin Dual-In-Line,SSOP and Wide Body SO PackagesDS012079-3Top ViewA D C 12130/A D C 12132/A D C 12138 2Pin DescriptionsCCLK The clock applied to this input controls the su-cessive approximation conversion time intervaland the acquisition time.The rise and fall timesof the clock edges should not exceed1µs. SCLK This is the serial data clock input.The clock applied to this input controls the rate at whichthe serial data exchange occurs.The risingedge loads the information on the DI pin intothe multiplexer address and mode select shiftregister.This address controls which channelof the analog input multiplexer(MUX)is se-lected and the mode of operation for the A/D.With CS low,the falling edge of SCLK shiftsthe data resulting from the previous ADC con-version out on DO,with the exception of thefirst bit of data.When CS is low continuously,the first bit of the data is clocked out on the ris-ing edge of EOC(end of conversion).WhenCS is toggled,the falling edge of CS alwaysclocks out the first bit of data.CS should bebrought low when SCLK is low.The rise andfall times of the clock edges should not exceed1µs.DI This is the serial data input pin.The data ap-plied to this pin is shifted by the rising edge ofSCLK into the multiplexer address and modeselect register.Table2through Table4showthe assignment of the multiplexer address andthe mode select data.DO The data output pin.This pin is an active push/ pull output when CS is low.When CS is high,this output is TRI-STATE.The A/D conversionresult(DB0–DB12)and converter status dataare clocked out by the falling edge of SCLK onthis pin.The word length and format of this re-sult can vary(see Table1).The word lengthand format are controlled by the data shiftedinto the multiplexer address and mode selectregister(see Table4).EOC This pin is an active push/pull output and indi-cates the status of the ADC12130/2/8.Whenlow,it signals that the A/D is busy with a con-version,auto-calibration,auto-zero or powerdown cycle.The rising edge of EOC signalsthe end of one of these cycles.CS This is the chip select pin.When a logic low is applied to this pin,the rising edge of SCLKshifts the data on DI into the address register.This low also brings DO out of TRI-STATE.With CS low,the falling edge of SCLK shiftsthe data resulting from the previous ADC con-version out on DO,with the exception of thefirst bit of data.When CS is low continuously,the first bit of the data is clocked out on the ris-ing edge of EOC(end of conversion).WhenCS is toggled,the falling edge of CS alwaysclocks out the first bit of data.CS should bebrought low when SCLK is low.The fallingedge of CS resets a conversion in progressand starts the sequence for a new conversion.When CS is brought back low during a conver-sion,that conversion is prematurely termi-nated.The data in the output latches may becorrupted.Therefore,when CS is brought backlow during a conversion in progress the dataoutput at that time should be ignored.CS mayalso be left continuously low.In this case it isimperative that the correct number of SCLKpulses be applied to the ADC in order to re-main synchronous.After the ADC supplypower is applied it expects to see13clockpulses for each I/O sequence.The number ofclock pulses the ADC expects is the same asthe digital output word length.This word lengthcan be modified by the data shifted in on theDO pin.Table4details the data required.DOR This is the data output ready pin.This pin is anactive push/pull output.It is low when the con-version result is being shifted out and goeshigh to signal that all the data has been shiftedout.CONV A logic low is required on this pin to programany mode or change the ADC’s configurationas listed in the Mode Programming Table(Table4)such as12-bit conversion,Auto Cal,Auto Zero etc.When this pin is high the ADC isplaced in the read data only mode.While in theread data only mode,bringing CS low andpulsing SCLK will only clock out on DO anydata stored in the ADCs output shift register.The data on DI will be neglected.A new con-version will not be started and the ADC will re-main in the mode and/or configuration previ-ously programmed.Read data only cannot beperformed while a conversion,Auto-Cal orAuto-Zero are in progress.PD This is the power down pin.When PD is highthe A/D is powered down;when PD is low theA/D is powered up.The A/D takes a maximumof700µs to power up after the command isgiven.CH0–CH7These are the analog inputs of the MUX.Achannel input is selected by the address infor-mation at the DI pin,which is loaded on the ris-ing edge of SCLK into the address register(see Table2and Table3).The voltage applied to these inputs should notexceed V A+or go below GND.Exceeding thisrange on an unselected channel will corruptthe reading of a selected channel.COM This pin is another analog input pin.It is usedas a pseudo ground when the analog multi-plexer is single-ended.MUXOUT1,MUXOUT2These are the multiplexer outputpins.A/DIN1,A/DIN2These are the converter input pins.MUXOUT1is usually tied to A/DIN1.MUXOUT2is usuallytied to A/DIN2.If external circuitry is placed be-tween MUXOUT1and A/DIN1,or MUXOUT2and A/DIN2it may be necessary to protectthese pins.The voltage at these pins shouldnot exceed V A+or go below AGND(see Figure5).V REF+This is the positive analog voltage referenceinput.In order to maintain accuracy,the volt-age range of V REF(V REF=V REF+−V REF−)isADC12130/ADC12132/ADC121383Pin Descriptions(Continued)1V DC to 5.0V DC and the voltage at V REF +cannot exceed V A +.See Figure 6for recom-mended bypassing.V REF −The negative voltage reference input.In order to maintain accuracy,the voltage at this pin must not go below GND or exceed V A +.(See Figure 6).V A +,V D +These are the analog and digital power supply pins.V A +and V D +are not connected together on the chip.These pins should be tied to the same power supply and bypassed separately (see Figure 6).The operating voltage range of V A +and V D +is 3.0V DC to 5.5V DC .DGND This is the digital ground pin (see Figure 6).AGNDThis is the analog ground pin (see Figure 6).A D C 12130/A D C 12132/A D C 12138 4Absolute Maximum Ratings (Notes 1,2)If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.Positive Supply Voltage (V +=V A +=V D +)6.5VVoltage at Inputs and Outputs except CH0–CH7and COM −0.3V to V ++0.3V Voltage at Analog Inputs CH0–CH7and COM GND −5V to V ++5V|V A +−V D +|300mV Input Current at Any Pin (Note 3)±30mA Package Input Current (Note 3)±120mAPackage Dissipation at T A =25˚C (Note 4)500mWESD Susceptability (Note 5)Human Body Model 1500V Soldering InformationN Packages (10seconds)260˚C SO Package (Note 6):Vapor Phase (60seconds)215˚C Infrared (15seconds)220˚CStorage Temperature −65˚C to +150˚COperating Ratings (Notes 1,2)Operating Temperature RangeT MIN ≤T A ≤T MAXADC12130CIN,ADC12130CIWM,ADC12132CIMSA,ADC12138CIMSA,ADC12138CIN,ADC12138CIWM −40˚C ≤T A ≤+85˚CSupply Voltage (V +=V A +=V D +)+3.0V to +5.5V|V A +−V D +|≤100mV V REF +0V to V A +V REF −0V to V REF +V REF (V REF +−V REF −)1V to V A +V REF Common Mode Voltage Range0.1V A +to 0.6V A +A/DIN1,A/DIN2,MUXOUT1and MUXOUT2Voltage Range 0V to V A +A/D IN Common Mode Voltage Range0V to V A +Converter Electrical CharacteristicsThe following specifications apply for (V +=V A +=V D +=+5V,V REF +=+4.096V,and fully differential input with fixed 2.048V common-mode voltage)or (V +=V A +=V D +=3.3V,V REF +=2.5V and fully-differential input with fixed 1.250Vcommon-mode voltage),V REF −=0V,12-bit +sign conversion mode,source impedance for analog inputs,V REF −and V REF +≤25Ω,f CK =f SK =5MHz,and 10(t CK )acquisition time unless otherwise specified.Boldface limits apply for T A =T J =T MIN to T MAX ;all other limits T A =T J =25˚C.(Notes 7,8,9)SymbolParameterConditionsTypical (Note 10)Limits Units (Limits)(Note 11)STATIC CONVERTER CHARACTERISTICSResolution12+signBits (min)+ILE Positive Integral Linearity Error After Auto-Cal (Notes 12,18)±1/2±2LSB (max)−ILE Negative Integral Linearity Error After Auto-Cal (Notes 12,18)±1/2±2LSB (max)DNLDifferential Non-Linearity After Auto-Cal±1.5LSB (max)Positive Full-Scale Error After Auto-Cal (Notes 12,18)±1/2±3.0LSB (max)Negative Full-Scale Error After Auto-Cal (Notes 12,18)±1/2±3.0LSB (max)Offset ErrorAfter Auto-Cal (Notes 5,18)±1/2±2LSB (max)V IN (+)=V IN (−)=2.048VDC Common Mode ErrorAfter Auto-Cal (Note 15)±2LSB (max)TUETotal Unadjusted ErrorAfter Auto-Cal ±1LSB(Notes 12,13,14)ADC12130/ADC12132/ADC121385Converter Electrical CharacteristicsThe following specifications apply for (V +=V A +=V D +=+5V,V REF +=+4.096V,and fully differential input with fixed 2.048V common-mode voltage)or (V +=V A +=V D +=3.3V,V REF +=+2.5V and fully-differential input with fixed 1.250Vcommon-mode voltage),V REF −=0V,12-bit +sign conversion mode,source impedance for analog inputs,V REF −and V REF +≤25Ω,f CK =f SK =5MHz,and 10(t CK )acquisition time unless otherwise specified.Boldface limits apply for T A =T J =T MIN to T MAX ;all other limits T A =T J =25˚C.(Notes 7,8,9)(Continued)SymbolParameterConditionsTypical (Note 10)Limits Units (Limits)(Note 11)STATIC CONVERTER CHARACTERISTICS (Continued)Multiplexer Channel to Channel ±0.05LSBMatchingPower Supply SensitivityV +=+5V ±10%V REF =+4.096VOffset Error ±0.5LSB +Full-Scale Error ±0.5LSB −Full-Scale Error±0.5LSB +Integral Linearity Error ±0.5LSB −Integral Linearity Error±0.5LSBUNIPOLAR DYNAMIC CONVERTER CHARACTERISTICS S/(N+D)Signal-to-Noise Plus f IN =1kHz,V IN =5V PP ,V REF +=5.0V 69.4dB Distortion Ratiof IN =20kHz,V IN =5V PP ,V REF +=5.0V 68.3dB f IN =40kHz,V IN =5V PP ,V REF +=5.0V 65.7dB −3dB Full Power BandwidthV IN =5V PP ,where S/(N+D)drops 3dB 31kHzDIFFERENTIAL DYNAMIC CONVERTER CHARACTERISTICSS/(N+D)Signal-to-Noise Plus f IN =1kHz,V IN =±5V,V REF +=5.0V 77.0dB Distortion Ratiof IN =20kHz,V IN =±5V,V REF +=5.0V 73.9dB f IN =40kHz,V IN =±5V,V REF +=5.0V 67.0dB −3dB Full Power BandwidthV IN =±5V,where S/(N+D)drops 3dB40kHzElectrical CharacteristicsThe following specifications apply for (V +=V A +=V D +=+5V,V REF +=+4.096V,and fully differential input with fixed 2.048V common-mode voltage)or (V +=V A +=V D +=+3.3V,V REF +=2.5V and fully-differential input with fixed 1.250Vcommon-mode voltage),V REF −=0V,12-bit +sign conversion mode,source impedance for analog inputs,V REF −and V REF +≤25Ω,f CK =f SK =5MHz,and 10(t CK )acquisition time unless otherwise specified.Boldface limits apply for T A =T J =T MIN to T MAX ;all other limits T A =T J =25˚C.(Notes 7,8,9)SymbolParameterConditionsTypical Limits Units (Note 10)(Note 11)(Limits)REFERENCE INPUT,ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS C REF Reference Input Capacitance 85pF C A/DA/DIN1and A/DIN2Analog Input 75pF CapacitanceA/DIN1and A/DIN2Analog Input V IN =+5.0V or ±0.1µALeakage CurrentV IN =0VCH0–CH7and COM Input VoltageGND −0.05VV A ++0.05C CH CH0–CH7and COM Input Capacitance10pF C MUXOUTMUX Output Capacitance 20pF Off Channel Leakage (Note 16)On Channel =5V and −0.01µA CH0–CH7and COM PinsOff Channel =0V On Channel =0V and 0.01µAOff Channel =5VA D C 12130/A D C 12132/A D C 12138 6Electrical Characteristics(Continued)The following specifications apply for(V+=V A+=V D+=+5V,V REF+=+4.096V,and fully differential input with fixed2.048V common-mode voltage)or(V+=V A+=V D+=+3.3V,V REF+=2.5V and fully-differential input with fixed1.250Vcommon-mode voltage),V REF−=0V,12-bit+sign conversion mode,source impedance for analog inputs,V REF−and V REF+≤25Ω,f CK=f SK=5MHz,and10(t CK)acquisition time unless otherwise specified.Boldface limits apply for T A=T J=T MIN to T MAX;all other limits T A=T J=25˚C.(Notes7,8,9)Symbol Parameter Conditions Typical Limits Units(Note10)(Note11)(Limits) REFERENCE INPUT,ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICSOn Channel Leakage(Note16)On Channel=5V and0.01µACH0–CH7and COM Pins Off Channel=0VOn Channel=0V and−0.01µAOff Channel=5VMUXOUT1and MUXOUT2V MUXOUT=5.0V or0.01µALeakage Current V MUXOUT=0VR ON MUX On Resistance V IN=2.5V and8501900Ω(max)V MUXOUT=2.4VR ON Matching Channel to Channel V IN=2.5V and5%V MUXOUT=2.4VChannel to Channel Crosstalk V IN=5V PP,f IN=40kHz−72dBMUX Bandwidth90kHz DC and Logic Electrical CharacteristicsThe following specifications apply for(V+=V A+=V D+=+5V,V REF+=+4.096V,and fully-differential input with fixed2.048V common-mode voltage)or(V+=V A+=V D+=+3.3V,V REF+=+2.5V and fully-differential input with fixed1.250Vcommon-mode voltage),V REF−=0V,12-bit+sign conversion mode,source impedance for analog inputs,V REF−and V REF+≤25Ω,f CK=f SK=5MHz,and10(t CK)acquisition time unless otherwise specified.Boldface limits apply for T A=T J=T MIN to T MAX;all other limits T A=T J=25˚C.(Notes7,8,9)Symbol Parameter Conditions Typical(Note10)V+=V A+=V+=V A+=Units(Limits) V D+=3.3V V D+=5VLimits Limits(Note11)(Note11)CCLK,CS,CONV,DI,PD AND SCLK INPUT CHARACTERISTICSV IN(1)Logical“1”InputVoltageV A+=V D+=V++10% 2.0 2.0V(min)V IN(0)Logical“0”InputVoltageV A+=V D+=V+−10%0.80.8V(max)I IN(1)Logical“1”InputCurrentV IN=V+0.005 1.0 1.0µA(max)I IN(0)Logical“0”InputCurrentV IN=0V−0.005−1.0−1.0µA(min) DO,EOC AND DOR DIGITAL OUTPUT CHARACTERISTICSV OUT(1)Logical“1”V A+=V D+=V+−10%,Output Voltage I OUT=−360µA 2.4 2.4V(min)V A+=V D+=V+−10%, 2.9 4.25V(min)I OUT=−10µAV OUT(0)Logical“0”V A+=V D+=V+−10%Output Voltage I OUT=1.6mA0.40.4V(max) I OUT TRI-STATE V OUT=0V−0.1−3.0−3.0µA(max)Output Current V OUT=V+−0.1 3.0 3.0+I SC Output ShortCircuit SourceCurrent V OUT=0V−14mAADC12130/ADC12132/ADC121387DC and Logic Electrical Characteristics(Continued)The following specifications apply for (V +=V A +=V D +=+5V,V REF +=+4.096V,and fully-differential input with fixed 2.048V common-mode voltage)or (V +=V A +=V D +=+3.3V,V REF +=+2.5V and fully-differential input with fixed 1.250Vcommon-mode voltage),V REF −=0V,12-bit +sign conversion mode,source impedance for analog inputs,V REF −and V REF +≤25Ω,f CK =f SK =5MHz,and 10(t CK )acquisition time unless otherwise specified.Boldface limits apply for T A =T J =T MIN to T MAX ;all other limits T A =T J =25˚C.(Notes 7,8,9)SymbolParameterConditionsTypical (Note 10)V +=V A +=V +=V A +=Units (Limits)V D +=3.3V V D +=5V Limits Limits (Note 11)(Note 11)DO,EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS −I SCOutput Short Circuit Sink Current V OUT =V D +16mAPOWER SUPPLY CHARACTERISTICS I D +Digital Supply 1.52.5mA (max)CurrentCS =HIGH,Powered Down,CCLK on 600µA CS =HIGH,Powered Down,CCLK off20µA I A +Positive Analog 3.04.0mA (max)Supply CurrentCS =HIGH,Powered Down,CCLK on 10µA CS =HIGH,Powered Down,CCLK off0.1µAI REFReference Input CurrentCS =HIGH,Powered Down,CCLK on 70µA CS =HIGH,Powered Down,CCLK off0.1µAAC Electrical CharacteristicsThe following specifications apply for (V +=V A +=V D +=+5V,V REF +=+4.096V,and fully-differential input with fixed 2.048V common-mode voltage)or (V +=V A +=V D +=+3.3V,V REF +=+2.5V and fully-differential input with fixed 1.250Vcommon-mode voltage),V REF −=0V,12-bit +sign conversion mode,source impedance for analog inputs,V REF −and V REF +≤25Ω,f CK =f SK =5MHz,and 10(t CK )acquisition time unless otherwise specified.Boldface limits apply for T A =T J =T MIN to T MAX ;all other limits T A =T J =25˚C.(Note 17)SymbolParameterConditionsTypical Limits Units (Note 10)(Note 11)(Limits)f CK Conversion Clock 105MHz (max)(CCLK)Frequency 1MHz (min)f SKSerial Data Clock 105MHz (max)SCLK Frequency 0Hz (min)Conversion Clock 40%(min)Duty Cycle 60%(max)Serial Data Clock 40%(min)Duty Cycle60%(max)t CConversion Time12-Bit +Sign or 12-Bit44(t CK )44(t CK )(max)8.8µs (max)A D C 12130/A D C 12132/A D C 12138 8AC Electrical Characteristics(Continued)The following specifications apply for(V+=V A+=V D+=+5V,V REF+=+4.096V,and fully-differential input with fixed2.048V common-mode voltage)or(V+=V A+=V D+=+3.3V,V REF+=+2.5V and fully-differential input with fixed1.250Vcommon-mode voltage),V REF−=0V,12-bit+sign conversion mode,source impedance for analog inputs,V REF−and V REF+≤25Ω,f CK=f SK=5MHz,and10(t CK)acquisition time unless otherwise specified.Boldface limits apply for T A=T J=T MIN to T MAX;all other limits T A=T J=25˚C.(Note17)Symbol Parameter Conditions Typical Limits Units(Note 10)(Note11)(Limits)t A Acquisition Time6Cycles Programmed6(t CK)6(t CK)(min) (Note19)7(t CK)(max)1.2µs(min)1.4µs(max)10Cycles Programmed10(t CK)10(t CK)(min)11(t CK)(max)2.0µs(min)2.2µs(max)18Cycles Programmed18(t CK)18(t CK)(min)19(t CK)(max)3.6µs(min)3.8µs(max)34Cycles Programmed34(t CK)34(t CK)(min)35(t CK)(max)6.8µs(min)7.0µs(max)t CAL Self-Calibration Time4944(t CK)4944(t CK)(max)988.8µs(max)t AZ Auto-Zero Time76(t CK)76(t CK)(max)15.2µs(max)t SYNC Self-Calibration or2(t CK)2(t CK)(min) Auto-Zero Synchronization3(t CK)(max)Time from DOR0.40µs(min)0.60µs(max)t DOR DOR High Time when CS is Low9(t SK)9(t SK)(max) Continuously for Read Data and SoftwarePower Up/Down1.8µs(max)t CONV CONV Valid Data Time8(t SK)8(t SK)(max)1.6µs(max)AC Electrical CharacteristicsThe following specifications apply for(V+=V A+=V D+=+5V,V REF+=+4.096V,and fully-differential input with fixed2.048V common-mode voltage)or(V+=V A+=V D+=+3.3V,V REF+=+2.5V and fully-differential input with fixed1.250Vcommon-mode voltage),V REF−=0V,12-bit+sign conversion mode,source impedance for analog inputs,V REF−and V REF+≤25Ω,f CK=f SK=5MHz,and10(t CK)acquisition time unless otherwise specified.Boldface limits apply for T A=T J=T MIN to T MAX;all other limits T A=T J=25˚C.(Note17)(Continued)Symbol Parameter Conditions Typical Limits Units(Note10)(Note11)(Limits)t HPU Hardware Power-Up Time,Time from500700µs(max) PD Falling Edge to EOC Rising Edget SPU Software Power-Up Time,Time fromSerial Data Clock Falling Edge to500700µs(max)EOC Rising Edget ACC Access Time Delay from2560ns(max) CS Falling Edge to DO Data ValidADC12130/ADC12132/ADC121389AC Electrical Characteristics(Continued)The following specifications apply for (V +=V A +=V D +=+5V,V REF +=+4.096V,and fully-differential input with fixed 2.048V common-mode voltage)or (V +=V A +=V D +=+3.3V,V REF +=+2.5V and fully-differential input with fixed 1.250Vcommon-mode voltage),V REF −=0V,12-bit +sign conversion mode,source impedance for analog inputs,V REF −and V REF +≤25Ω,f CK =f SK =5MHz,and 10(t CK )acquisition time unless otherwise specified.Boldface limits apply for T A =T J =T MIN to T MAX ;all other limits T A =T J =25˚C.(Note 17)(Continued)Symbol ParameterConditionsTypical Limits Units (Note 10)(Note 11)(Limits)t SET-UP Set-Up Time of CS Falling Edge to 50ns (min)Serial Data Clock Rising Edge t DELAY Delay from SCLK Falling 05ns (min)Edge to CS Falling Edge t 1H ,t 0H Delay from CS Rising Edge to R L =3k,C L =100pF70100ns (max)DO TRI-STATE ®t HDI DI Hold Time from Serial Data 515ns (min)Clock Rising Edget SDI DI Set-Up Time from Serial Data 510ns (min)Clock Rising Edget HDO DO Hold Time from Serial Data R L =3k,C L =100pF3565ns (max)Clock Falling Edge5ns (min)t DDO Delay from Serial Data Clock 5090ns (max)Falling Edge to DO Data Valid t RDO DO Rise Time,TRI-STATE to High R L =3k,C L =100pF1040ns (max)DO Rise Time,Low to High 1040ns (max)t FDO DO Fall Time,TRI-STATE to Low R L =3k,C L =100pF 1540ns (max)DO Fall Time,High to Low 1540ns (max)t CD Delay from CS Falling Edge 4580ns (max)to DOR Falling Edget SD Delay from Serial Data Clock Falling 4580ns (max)Edge to DOR Rising Edge C IN Capacitance of Logic Inputs 10pF C OUTCapacitance of Logic Outputs20pFNote 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.Operating Ratings indicate conditions for which the device is func-tional,but do not guarantee specific performance limits.For guaranteed specifications and test conditions,see the Electrical Characteristics.The guaranteed speci-fications apply only for the test conditions listed.Some performance characteristics may degrade when the device is not operated under the listed test conditions.Note 2:All voltages are measured with respect to GND,unless otherwise specified.Note 3:When the input voltage (V IN )at any pin exceeds the power supplies (V IN <GND or V IN >V A +or V D +),the current at that pin should be limited to 30mA.The 120mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 30mA to four.Note 4:The maximum power dissipation must be derated at elevated temperatures and is dictated by T J max,θJA and the ambient temperature,T A .The maximum allowable power dissipation at any temperature is P D =(T J max −T A )/θJA or the number given in the Absolute Maximum Ratings,whichever is lower.For this device,T J max =150˚C.The typical thermal resistance (θJA )of these parts when board mounted follow:ThermalPart Number ResistanceθJA ADC12130CIN 53˚C/W ADC12130CIWM 70˚C/W ADC12132CIMSA 134˚C/W ADC12138CIN 40˚C/W ADC12138CIWM 50˚C/W ADC12138CIMSA125˚C/WNote 5:The human body model is a 100pF capacitor discharged through a 1.5k Ωresistor into each pin.Note 6:See AN450“Surface Mounting Methods and Their Effect on Product Reliability”or the section titled “Surface Mount”found in any post 1986National Semi-conductor Linear Data Book for other methods of soldering surface mount devices.A D C 12130/A D C 12132/A D C 12138 10AC Electrical Characteristics(Continued)Note 7:Two on-chip diodes are tied to each analog input through a series resistor as shown below.Input voltage magnitude up to 5V above V A +or 5V below GND will not damage this device.However,errors in the A/D conversion can occur (if these diodes are forward biased by more than 50mV)if the input voltage magnitude of selected or unselected analog input go above V A +or below GND by more than 50mV.As an example,if V A +is 4.5V DC ,full-scale input voltage must be ≤4.55V DC to ensure accurate conversions.Note 8:To guarantee accuracy,it is required that the V A +and V D +be connected together to the same power supply with separate bypass capacitors at each V +pin.Note 9:With the test condition for V REF (V REF +−V REF −)given as +4.096V,the 12-bit LSB is 1.0mV.For V REF =2.5V,the 12-bit LSB is 610µV.Note 10:Typicals are at T J =T A =25˚C and represent most likely parametric norm.Note 11:Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).Note 12:Positive integral linearity error is defined as the deviation of the analog value,expressed in LSBs,from the straight line that passes through positive full-scale and zero.For negative integral linearity error,the straight line passes through negative full-scale and zero (see Figure 2and Figure 3).Note 13:Zero error is a measure of the deviation from the mid-scale voltage (a code of zero),expressed in LSB.It is the average value of the code transitions be-tween −1to 0and 0to +1(see Figure 4).Note 14:Total unadjusted error includes offset,full-scale,linearity and multiplexer errors.Note 15:The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together.Note 16:Channel leakage current is measured after the channel selection.Note 17:Timing specifications are tested at the TTL logic levels,V OL =0.4V for a falling edge and V OL =2.4V for a rising edge.TRI-STATE output voltage is forced to 1.4V.Note 18:The ADC12130family’s self-calibration technique ensures linearity and offset errors as specified,but noise inherent in the self-calibration process will re-sult in a maximum repeatability uncertainty of 0.2LSB.Note 19:If SCLK and CCLK are driven from the same clock source,then t A is 6,10,18or 34clock periods minimum and maximum.Note 20:The “12-Bit Conversion of Offset”and “12-Bit Conversion of Full-Scale”modes are intended to test the functionality of the device.Therefore,the output data from these modes are not an indication of the accuracy of a conversion result.DS012079-4DS012079-5FIGURE 1.Transfer CharacteristicADC12130/ADC12132/ADC12138。
MIL-STD-1275E
METRICMIL-STD-1275E22 MARCH 2013SUPERSEDINGMIL-STD-1275D29 August 2006 DEPARTMENT OF DEFENSEINTERFACE STANDARDCHARACTERISTICS OF28 VOLT DC INPUT POWER TO UTILIZATION EQUIPMENT INMILITARY VEHICLESFOREWORD1.This standard is approved for use by all departments and agencies of the Department of Defense (DOD).2.The intent of this document is to describe the nominal 28 VDC voltage characteristics, common across military ground vehicles, at the input power terminal of the utilizing electrical and electronic assemblies directly connected to the distribution network. This lays the groundwork for commonality across vehicle pla tforms. The vehicle’s design authority is responsible to ensure that the 28 VDC delivered to the input power terminal of the utilization equipment meets these requirements.3.This is neither a power source nor a power system standard. This standard focuses on utilization equipment and the conditions under which it is expected to operate.ments, suggestions, or questions on this document should be addressed to U.S. Army Tank automotive and Armaments Command, ATTN: RDTA-EN/STND/TRANS, MS# 268, 6501 E. 11 Mile Road, Warren, MI 48397 5000 or emailed to usarmy.detroit.rdecom.mbx.tardec-standardization@. Since contact information can change, you may want to verify the currency of this address information using the ASSIST Online database at https://.Table of Contents1 SCOPE (1)1.1 Scope. (1)2 APPLICABLE DOCUMENTS (1)2.1 General. (1)2.2 Government documents (1)2.2.1 Specifications, standards, and handbooks. (1)2.3 Non-Government documents. (1)2.4 Order of precedence. (2)3 DEFINITIONS (2)3.1 Utilization equipment. (2)3.2 Equipment under test. (2)3.3 Operations. (2)3.3.1 Starting operation. (2)3.3.2 Normal operation. (2)3.4 Operational voltage range. (2)3.5 Transient waveform characteristics. (2)3.5.1 Rise time. (2)3.5.2 Fall time. (3)3.5.3 Recovery time. (3)3.5.4 Ripple. (3)3.6 Types of transient waveforms. (3)3.6.1 Starting disturbance. (3)3.6.2 Voltage spike. (4)3.6.3 Voltage surge. (5)3.6.4 Intermittent contact. (6)3.7 Reverse polarity (6)4 GENERAL REQUIREMENTS (6)4.1 Reverse polarity (6)4.2 Electromagnetic compatibility. (7)4.3 Electrostatic discharge (7)5 DETAILED REQUIREMENTS (7)5.1 Voltage compatibility requirements. (7)5.1.1 Steady state operation. (7)5.1.2 Starting operation. (7)5.1.3 Transient disturbances. (8)5.2 Voltage compatibility verification setup. (9)5.2.1 Environmental conditions. (9)5.2.2 Calibration of test equipment. (10)5.2.3 Nominal voltage. (10)5.2.4 Measurement tolerance. (10)5.2.5 Measurement reference point. (11)5.2.6 Power return. (11)5.2.7 Loads. (11)5.2.8 Power supply. (11)5.3 Voltage compatibility verification method. (11)5.3.1 Steady state operation. (11)5.3.2 Starting operation. (12)5.3.3 Transient disturbances. (12)5.3.4 Reverse polarity. (15)5.3.5 Electromagnetic compatibility. (15)5.3.6 Electrostatic discharge. (15)6 NOTES (15)6.1 Intended use (15)6.2 Acronyms. (15)6.3 International interest. (16)6.4 Changes from previous issue (16)6.5 Subject term (key word) listing. (16)Table of FiguresFigure 1. Recovery time. (3)Figure 2. Sample starting disturbance waveform. (4)Figure 3. Voltage spike. (4)Figure 4. Sample alternator load dump waveform. (5)Figure 5. Sample intermittent contact waveform. (6)Figure 6. Starting disturbance limits on 28VDC systems. (8)Figure 7. Envelope of spikes for 28VDC systems. (9)Figure 8. Envelope of surges for 28VDC systems. (10)Figure 9. Sample test setup for immunity to injected voltage spikes. (12)Figure 10. Sample test setup for exported voltage spikes and surges. (13)Figure 11. Sample test circuit for immunity to injected voltage surges. (14)Table of TablesTable I. Positive voltage surge test parameters. (14)1SCOPE1.1Scope.This standard defines the operating voltage limits and transient voltage characteristics of the 28 VDC electrical power at the input power terminals to the utilization equipment connected to the electrical power distribution system on military ground vehicle platforms.2APPLICABLE DOCUMENTS2.1General.The documents listed in this section are cited in sections 3, 4 and 5 of this document. This section does not include documents cited in other sections of this standard or recommended for additional information or as examples. While every effort has been made to ensure the completeness of this list, the users of this standard are cautioned that they must meet all requirements of documents cited in sections 3, 4 and 5 of this standard, whether or not they are listed in this section.2.2Government documents.2.2.1Specifications, standards, and handbooks.The following specifications, standards, and handbooks form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract.DEPARTMENT OF DEFENSEMIL-STD-461 - Requirements for the Control of ElectromagneticInterference Characteristics of Subsystems and Equipment(Copies of these documents are available from https:///quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)2.3Non-Government documents.The following documents form a part of this document to the extent specified herein. Unless otherwise specified, the issues of documents are those cited in the solicitation or contract.SAE INTERNATIONALSAE J1113-42 - Electromagnetic Compatibility—Component TestProcedure—Part 42—Conducted Transient Emissions(Copies of these documents are available from or SAE Customer Service, 400 Commonwealth Drive, Warrendale, PA 15096-0001.)2.4Order of precedence.In the event of a conflict between the text of this document and the references cited herein, the text of this document takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption is obtained in writing from the applicable authority.3DEFINITIONS3.1Utilization equipment.Utilization equipment is defined as the electronic device, equipment, or system subjected to the voltage range(s) indicated in this specification.3.2Equipment under test.The Equipment Under Test (EUT) is defined as the electronic device, equipment, or system undergoing validation and/or verification testing or evaluation.3.3Operations.3.3.1Starting operation.Electrical power during an engine starting event is sufficient for utilization equipment to provide the level of performance specified in the utilization equipment’s detailed specification.3.3.2Normal operation.Electrical power is sufficient for utilization equipment to provide the level of performance specified in the utilization equipment’s detailed specification.3.4Operational voltage range.Voltage characteristics representative of the nominal operating voltage within a pre-defined tolerance or limit. Some variation in voltage is reasonable and expected; however, this variation remains within pre-defined limits of operation.3.5Transient waveform characteristics.A transient waveform represents a time-varying electrical signal defined by characteristics such as rise/fall time, period, frequency of oscillation, pulse width, etc. Transients typically exceed pre-defined steady-state limits, return to and remain within the steady-state limits within a specified time. The transient may have positive or negative polarity and/or be of short or long duration. Transient voltage levels may also exceed the system battery voltage by several hundred volts depending on the source of the transient.3.5.1Rise time.The rise time is the difference between when the rising edge of a voltage or current transient crosses a pre-defined low threshold to when the transient crosses a pre-defined high threshold. As defined in this standard, the low threshold is defined to be the time at when the amplitude of the rising edge is equal to ten percent (10%) of the maximum value of the transient. The highthreshold is defined to be the time when the amplitude is equal to ninety percent (90%) of the maximum value of the transient.3.5.2Fall time.The fall time is the difference between when the falling edge of a voltage or current transient crosses a pre-defined high threshold to when the transient crosses a pre-defined low threshold. As defined in this standard, the high threshold is defined to be the time at when the amplitude of the falling edge is equal to ninety percent (90%) of the maximum value of the transient. The low threshold is defined to be the time when the amplitude is equal to ten percent (10%) of the maximum value of the transient.3.5.3Recovery time.The interval between the time a characteristic deviates from the steady-state limits and the time it returns and remains within the same range. Refer to Figure 1.Figure 1. Recovery time.3.5.4Ripple.The regular and/or irregular variations of voltage about a fixed DC voltage level during normal operation of a DC system.3.6Types of transient waveforms.There are several different types of transient waveforms associated with the vehicle’s power supply system.3.6.1Starting disturbance.A starting disturbance is the variation in system voltage from the normal operating voltage range caused by the initial engagement of the engine starter and subsequent engine cranking. The duration of the Initial Engagement Surge (IES) is measured from the time at which it departs from the normal operating voltage to the time at which it reaches and remains at the crankingvoltage. An example showing “Initial Engagement Surge” (IES) and “Cranking”; i.e., voltage level during active engine cranking is shown in Figure 2.Figure 2. Sample starting disturbance waveform.3.6.2 Voltage spike.A voltage spike is an energy-limited transient waveform having a duration less than or equal to 1 ms. These typically result from the interaction of the power delivery system wiring and switching of reactive loads or a mismatch in impedance between the wiring harness andequipment. Figure 3 shows an example of a spike waveform.Figure 3. Voltage spike.V peak t duration Timef osc0.1 V peak0.9 V peak0 VDC t rise3.6.3 Voltage surge.A surge is a transient waveform having a duration greater than 1 ms and a specific wave shape, typically a rising/falling edge and a slow exponential decay for the falling edge. Surges result from the switching of reactive loads containing a significant level of stored energy or sudden disconnection of a constant load. Surges may also occur due to the application of high-demand loads.3.6.3.1 Positive voltage surge.A positive voltage surge is a positive-going transient, which exceeds the nominal supplied voltage. This may occur when a high current or inductive load is suddenly disconnected. The most common occurrence of a positive voltage surge, or “alternator load dump,” occurs when the alternator is working to charge a partially or fully discharged set of batteries and the connection to the battery positive terminal is suddenly disconnected. The alternator cannot immediately decrease its output to compensate for the sudden loss of load so the energy delivered during this settling period is distributed to the vehicle’s electrical system. A positive surge (V PEAK ) with a short rise time (t RISE ) and long exponential decay is generated above the nominal battery voltage of the system (V NOM ) and last for a given time (t WIDTH ). Figure 4 shows an example of an alternator load dump waveform.Figure 4. Sample alternator load dump waveform.3.6.3.2 Negative voltage surge.This event is similar to an alternator load dump as specified in Section 3.6.3.1 except itrepresents the negative-going transient generated when a sudden load is placed on the alternator. The alternator cannot immediately change its output so the system voltage decreases until the alternator can compensate for the sudden increase in load.VoltV V3.6.4 Intermittent contact.Intermittent contact occurs when electrical contacts in a switch or relay change state. A common way of describing intermittent contacts is the use of t he terms “contact bounce” or “chattering relay.” Mechanical vibration may also affect the operation of mechanical contacts and cause this to occur. The settling period and pulse widths associated may vary depending on theconstruction of the contacts. Figure 5 shows an example of an intermittent contact waveform.Figure 5. Sample intermittent contact waveform.Intermittent contact may affect operation of equipment in one of two ways. First, equipment power feed(s) controlled by the relay/switch may be directly affected with resets, dropouts, etc. Second, the electrical noise generated by the intermittent contact on a directly connected wire may be coupled to nearby wires in the wiring harness through electric/magnetic field coupling.3.7 Reverse polarity.Reverse polarity is d efined as the inverted connection of the EUT’s power terminal(s) to the vehicle’s power system. The positive (+) terminal of the EUT is connected to the negative (-) or “ground” terminal of the vehicle’s power supply system. The negative (-) terminal of the EUT is connected to the positive (+) terminal of the vehicle’s power supply system.4 GENERAL REQUIREMENTS4.1 Reverse polarity.Utilization equipment shall protect itself against damage due to input power with reverse polarity. With reverse polarity voltage applied to the input power terminals of the utilization equipment, the magnitude of the reverse polarity input current shall be equal to or less than the magnitude of the utilization equipment normal operating current.VoltV4.2 Electromagnetic compatibility.Utilization equipment shall be compatible with the applicable performance specificationrequirements for control of electromagnetic interference and voltage spikes induced by lightning, electromagnetic pulses, and power switching. Electromagnetic interference is not covered by this standard.4.3 Electrostatic discharge.Utilization equipment shall be compatible with the applicable performance specificationrequirements for immunity to electrostatic discharge. Electrostatic discharge is not covered by this standard. 5 DETAILED REQUIREMENTS5.1 Voltage compatibility requirements.This section contains detailed requirements regarding the voltage conditions under which the utilization equipment is expected to operate. Verification of compliance shall be in accordance with Sections 5.2 and 5.3 of this document.5.1.1disturbances, and applies to all utilization equipment. Utilization equipment shall operatewithout degradation or damage when subjected to the operational voltage range specified in this section.5.1.1.1 Operational voltage range.The utilization equipment voltage operating range is between 20 VDC and 33 VDC, including ripple.5.1.1.2 Voltage ripple.The maximum peak-to-peak ripple voltage limits are specified in MIL-STD-461 CS101 with the same values used at 150 kHz extended to 250 kHz, as shown in Figure CS101-1.5.1.2 disturbances. Utilization equipment shall operate without degradation or damage when subjected to engine starting disturbances within the limits shown in Figure6.5.1.2.1 Initial engagement surge (IES).The minimum voltage supplied to utilization equipment during an IES is 12 VDC. Themaximum duration of the IES is one (1) second. Consecutive IES events are a minimum of one (1) second apart.5.1.2.2 Cranking surges.The minimum voltage supplied to utilization equipment during cranking surges is 16 VDC. The maximum duration of cranking surges is thirty (30) seconds.Figure 6. Starting disturbance limits on 28VDC systems.5.1.3Transient disturbances.5.1.3.1 Voltage spikes.5.1.3.1.1 Injected voltage spikes.Utilization equipment shall operate without degradation or damage when subjected to voltage spikes within the limits shown in Figure 7. The maximum rise time (t RISE ) of the injected spikes is 50 nanoseconds, and the maximum total energy content of a single spike is 2 Joules.5.1.3.1.2 Emitted voltage spikes.Emitted voltage spikes from utilization equipment shall be within the limits shown in Figure 7. The maximum total energy content of a single emitted spike is 125 millijoules (mJ).5.1.3.2 Voltage surges.5.1.3.2.1 Injected voltage surges.Utilization equipment shall operate without degradation or damage when subjected to voltage surges within the limits shown in Figure 8. The maximum total energy content of a single surge is 60 Joules (J).Time (s)Figure 7. Envelope of spikes for 28VDC systems.5.1.3.2.2 Emitted voltage surges.Emitted voltage surges from utilization equipment shall be within the limits shown in Figure 8.5.2 Voltage compatibility verification setup.5.2.1 Environmental conditions.Testing of the EUT according to this standard shall be performed under the following environmental conditions:Temperature: +23°C ± 5°C (+73°F ± 9°F) Relative Humidity: 0% to 90% humidity Atmospheric Pressure: 80kPa to 102kPa (23.62 inHg to 30.12 inHg)Testing under different environmental conditions (e.g., extremes of operating temperature) shall be conducted at the discretion of the appropriate authority.The electromagnetic environment (e.g., background noise) shall not interfere with the measurement instrumentation setup.1002003004005006007008009001000Time (µs)Volts1 100 200 300 400 500 600 700 800 900 1000Time (ms)Figure 8. Envelope of surges for 28VDC systems.5.2.2Calibration of test equipment.Test equipment used to verify parameters such as current, voltage, rise/fall time, etc. of the test setup shall have traceable calibration to a national standards body, such as NIST, and within the calibration period at the time of the test.5.2.3Nominal voltage.For purposes of verification, the term “nominal” when used to describe voltage shall mean the stated voltage ±1%, unless otherwise stated.5.2.4Measurement tolerance.The default measurement tolerance shall be ±1% unless otherwise stated.5.2.5Measurement reference point.The measurement reference point for EUTs shall be the power input terminals of the EUT. EUTs having multiple power input terminals shall be individually and simultaneously monitored during the test(s). All transient voltage waveforms applied to EUTs shall be verified open circuit; i.e., no load.5.2.6Power return.The test setup shall use a power return for the EUT as required by the applicable performance specification.If a power return is not specified, the EUT power return conductor shall be equivalent to the EUT power source conductor.In cases where the EUT uses the vehicle structure as the power return, a ground plane in accordance with (IAW) MIL-STD-461 shall be used to simulate the vehicle’s metal structure as the return current path. The negative (-) terminal of the EUT as well as the negative (-) terminal of the power source shall be bonded to the ground plane.5.2.7Loads.Loads representative of the actual installation on vehicle shall be used to test the EUT if the EUT is not a standalone device.5.2.8Power supply.Power supplies shall maintain ±1% of specified voltage during testing, as measured at their output.5.3Voltage compatibility verification method.5.3.1Steady state operation.5.3.1.1Operational voltage range.The EUT shall be tested to operate as specified while subjected to the voltages/durations at both the lower and higher limits of the voltage envelope shown in Figure 8. Any deviation from normal operation shall be recognized as a failure of the EUT.5.3.1.2Voltage ripple.Unless otherwise specified in the applicable performance specification, the test method and limits for voltage ripple specified in MIL-STD-461 CS101 shall be used at nominal voltages of 23 VDC and 30 VDC with the same values used at 150 kHz extended to 250 kHz, as shown in Figures CS101-1 and CS101-2.Verify the EUT operates as specified while subjected to the ripple. Any deviation from normal operation shall be recognized as a failure of the EUT.5.3.2Starting operation.When applicable, the EUT shall be tested to operate as specified while subjected to the voltages/durations of the lower limit of the voltage envelope shown in Figure 6. Any deviation from normal operation shall be recognized as a failure of the EUT.5.3.3Transient disturbances.5.3.3.1Voltage spikes.5.3.3.1.1Injected voltage spikes.The EUT shall be supplied power by a voltage source set to the nominal 28 VDC operating voltage through a Line Impedance Stabilization Network (LISN). The test operator shall inject voltage spikes into the EUT using a test setup similar to Figure 9.Figure 9. Sample test setup for immunity to injected voltage spikes.One LISN shall be used when the power return is the vehicle chassis; in this case the ground plane provides the power return current path. Two LISNs shall be used when the EUT has a dedicated power return conductor, such as wires, buss bar, etc. This simulates the additional vehicle wiring harness present in the vehicle.Both positive and negative voltage spikes shall be applied to the EUT. A minimum of fifty (50) 250V spikes of each polarity shall be applied at one (1) second intervals. Each test spike shall have a peak amplitude of 250V, a risetime not exceeding 50 ns, a frequency of oscillation greater than 100 kHz and less than 500 kHz, and a maximum energy content of 2 Joules.Verify the EUT operates as specified while subjected to the voltage spikes. Any deviation from normal operation shall be recognized as a failure of the EUT.5.3.3.1.2Emitted spikes.The EUT shall be supplied power by a source set to the nominal 28 VDC operating voltage. Unless otherwise specified in the applicable performance specification, use the conducted transient emissions test method specified in SAE J1113-42 to measure the spikes emitted by the EUT using a test setup similar to Figure .Figure 10. Sample test setup for exported voltage spikes and surges.One LISN shall be used when the power return is the vehicle chassis; in this case the ground plane provides the power return current path. Two LISNs shall be used when the EUT has a dedicated power return conductor, such as wires, buss bar, etc. This simulates the additional vehicle wiring harness present in the vehicle.The test operator shall exercise switching function(s) of the EUT capable of producing spikes, (e.g., the switching of any inductive loads controlled by the EUT). If the power source to the EUT is controlled by means of a vehicle mounted switch or relay, the test shall be performed using this switch or relay. Each switching function shall be exercised a minimum of thirty-two (32) times in order to give a reasonable probability that the maximum spike voltage is recorded. The test operator shall monitor the operation of the EUT. Voltage spikes emitted by the EUT shall be within the limits shown in Figure 7. Any voltage spike or combination of voltage spikes emitted from a single event shall have an energy content less than 125 mJ.5.3.3.2Voltage surges.5.3.3.2.1Injected voltage surges.The test operator shall inject voltage surges into the EUT using a test setup similar to Figure 11.Figure 11. Sample test circuit for immunity to injected voltage surges.The voltage waveform injected on the power line(s) of the EUT shall simulate the voltage surge shown in Figure 4. The voltage surge parameters are shown in Table I. Energy emitted from the transient surge generator shall be limited to 60 Joules.Prior to connection of the EUT, the test operator shall verify the amplitude and duration of the voltage surge specified in Table I with a non-inductive load whose resistance is matched to the source impedance of the transient generator.Verify the EUT operates as specified while subjected to the voltage surges. Any deviation from normal operation shall be recognized as a failure of the EUT.5.3.3.2.2Emitted voltage surges.The EUT shall be supplied power by a source set to the nominal 28 VDC operating voltage. The test operator shall measure voltage surges emitted by the EUT using a test setup similar to Figure 10. The test operator shall exercise function(s) of the EUT capable of producing surges. Each surge-producing function shall be exercised a minimum of thirty-two (32) times in order to give a reasonable probability that the maximum surge voltage is recorded.The test operator shall monitor the operation of the EUT. Voltage surges emitted by the EUT shall be within the limits shown in Figure 8.5.3.4Reverse polarity.Connect the positive (+) terminal of the EUT to the negative (-) terminal of the power supply system. Connect the negative (-) terminal of the EUT to the positive (+) terminal of the power supply system. Set the voltage on the power supply to 33 VDC and leave connected for five (5) minutes. Connect EUT input terminals to power with the correct polarity and verify device operates as specified. Any deviation from normal operation shall be recognized as a failure of the EUT.5.3.5Electromagnetic compatibility.The EUT shall demonstrate compliance with the applicable performance specification requirements for control of electromagnetic interference and voltage spikes induced by lightning, electromagnetic pulses, and power switching prior to MIL-STD-1275 testing. Electromagnetic interference testing is not covered by this standard.5.3.6Electrostatic discharge.The EUT shall demonstrate compliance with the applicable performance specification requirements for immunity to electrostatic discharge prior to MIL-STD-1275 testing. Electrostatic discharge testing is not covered by this standard.6NOTES(This section contains information of a general or explanatory nature, which may be helpful, but is not mandatory.)6.1Intended use.The intent of this document is to describe the nominal 28 VDC voltage characteristics, common across military ground vehicles, at the input power terminal of the utilizing electrical and electronic assemblies directly connected to the distribution network. This lays the groundwork for commonality across vehicle platforms. The vehicle’s design authority is responsible to ensure that the 28 VDC delivered to the input power terminal of the utilization equipment meets these requirements.6.2Acronyms.6.3International interest.Certain provisions of this standard are the subject of international standardization agreement NATO STANAG 2601. When a change notice, revision, or cancellation of this standard is proposed which will modify the international agreement concerned, the preparing activity will take appropriate action through international standardization channels, including departmental standardization offices, to change the agreement or make other appropriate accommodations. 6.4Changes from previous issue.Marginal notations are not used in this revision to identify changes with respect to the previous issue due to the extent of the changes.6.5Subject term (key word) listing.PolarityRecovery timeRippleRise timeSpikeStarting disturbanceSurgeVoltageCustodian: Preparing Activity: Army – AT Army - ATReview Activities: Project 2920-2013-001 Army - CR, MI, TEDLA - CCNOTE: The activities listed above were interested in this document as of the date of this document. Since organizations and responsibilities can change, you should verify the currency of the information above using the ASSIST Online, database at https://.。
LDEExxxx中文资料
Series Rated voltage (C = 50Vdc) Size code (D = 22.20) Capacitance = 0.47μF Tolerance (J = 5%) Dielectric (A = PEN) Version (5 = standard) Packing (N= Tape) Internal use
28.24
7.1
6.1
1000
40.30
10.2
7.6
1000
50.40
12.7
10.2
500
60.54
15.2
13.7
500
All dimensions are in mm. In accordance with IEC 60286-3. Material used: - Carrier tape: antistatic material - Cover tape: polyester + PE - Reel: recyclable polystyrene All parts in bulk or on reel are packed in hermetically sealed moisture barrier bag (MBB).
L
3.2 3.2 4.5 5.7
W
(mm) 1.6 2.5 3.2 5.1
H max
(mm) 1.1 1.5--2.0 1.7 2.3--2.6 2.3--2.7 3.3 4.2--4.4 3.5 4.5 5.4 3.6 4.5 5.4--5.6 3.6 4--4.5 5.5--5.7 3.6 4.5--4.9 5.5--5.7
东芝芯片资料
0 900Ω 600Ω 19.5K 15K 13K 19K
LA7833引脚功能
引脚
1 2 3 4 4 6 7
功能
接地端 场输出 自举升压电源端 场激励输入 负反馈输入及相位补偿 电源端 场逆程脉冲输出
直流电压
0V 13.6V 25.5V 0.8V 0.8V 26V 1.4V
纹波滤波电路引脚 第二伴音中频输出 调频直流反馈滤波电路引脚
电压
1.8V 0V 1.3V
+2.5V
+5V 2.45V 2.45V
1V 6.4V 0V 0V 2.3V 1.6V 0V +5V 3.6V 4.3V 0V 8V 8.8V 3.5V 5.6V 3.4V 3.5V
RXIK档对地电阻(黑表笔接地)
场AGC 总线时钟端子 总线数据端子
行电源 SECAM识别/载波信号输出
行逆程脉冲输入 复合同步信号输出 行激励信号输出
接地 沙堡脉冲输出 视频信号输出
数字电源
SECAM蓝色差信号输入 SECAM红色差信号输入
亮度信号输入 行AFC滤波
外接视频信号
接地 视频信Leabharlann 输入黑电平检测滤波直流电压（V）
有信号 4.9
800Ω 0
12.5K
12.8K
6K 13K 13K 13K 12.8K 13.2K
0 12.8K 13K 11.5K
1K 12.5K 12K
0 900Ω 600Ω 12.5K 12.2K 11.5K 12K
红笔接地 R×1K档
800Ω 0
19K
27K
5.5K 20K 20K 18K 28K 28K
SLVDA2.8LC中文资料
SL VDA2.8LCUL TRA LOW CAP ACIT ANCE TVS ARRA YOnly One Name Means ProTek’Tion™APPLICA TIONS ✔ Ethernet - 10/100/1000 Base T✔ Cellular Phone Base Stations ✔ Switching Stations ✔ Audio/Video Inputs ✔ H andheld DevicesIEC COMP A TIBILITY (EN61000-4)✔ 61000-4-2 (ESD): Air - 15kV, Contact - 8kV ✔ 61000-4-4 (EFT): 40A - 5/50ns✔ 61000-4-5 (Surge): 24A, 8/20µs - Level 2(Line-Ground) & Level 3(Line-Line)FEA TURES✔ 600 Watts Peak Pulse Power per Line (tp = 8/20µs)✔ Provides Protection for Four (4) Line Pairs ✔ LOW LEAKAGE CURRENT < 1.0µA ✔ ULTRA LOW CAPACITANCE: 1.25pF ✔ RoHS Compliant in Lead-Free VersionsMECHANICAL CHARACTERISTICS✔ Molded JEDEC SO-8✔ Weight 70 milligrams (Approximate)✔ Available in Tin-Lead or Lead-Free Pure-Tin Plating(Annealed)✔ Solder Reflow Temperature:Tin-Lead - Sn/Pb, 85/15: 240-245°C Pure-Tin - Sn, 100: 260-270°C✔ Flammability Rating UL 94V-0✔ 12mm Tape and Reel Per EIA Standard 481✔ Device Marking: Marking Code, Logo, Date Code & Pin One Defined By DOT on Package05143PIN CONFIGURA TIONSO-8SL VDA2.8LCDEVICE CHARACTERISTICSMAXIMUM RATINGS @ 25°C Unless Otherwise SpecifiedPeak Pulse Power (t p = 8/20µs) - See Figure 1Peak Pulse Current (t p = 8/20µs)Lead Soldering T emperature Operating T emperature SYMBOL VALUE °C°C A Watts UNITS 260°C (10 Sec)30600T J I PP P PP T STGPARAMETERStorage T emperatureT II -55°C to 150°C-55°C to 150°C °C ELECTRICAL CHARACTERISTICS PER LINE @ 25°C Unless Otherwise SpecifiedPARTNUMBERDEVICE MARKING CODERATED STAND-OFF VOLTAGEV WM VOLTSMINIMUM BREAKDOWN VOLTAGE @ 1mA V (BR)VOLTS MINIMUM SNAP BACK VOLTAGE@ I SB = 50mAV SB VOLTSSLVDA2.8LCLV2.82.83.02.84.6TYPICAL CAPACITANCE@0V, 1MH zC pF6.25MAXIMUMCLAMPING VOLTAGE (See Fig. 2)@I P = 1AV C VOLTS MAXIMUM CLAMPING VOLTAGE (See Fig. 2)@I P = 5AV C VOLTS MAXIMUM CLAMPING VOLTAGE (See Fig. 42)@8/20µs V C @ I PP MAXIMUM LEAKAGE CURRENT@V WMI D µA 21.0V@30.0A1.0FIGURE 2FIGURE 1PEAK PULSE POWER VS PULSE TIME0.01 1 10 100 1,000 10,000t d - Pulse Duration - µs0 5 10 15 20 25 30t - Time - µs20406080100120I P P - P e a k P u ls e C u r r e n t - % o f I P P101001,00010,000P P P - P e a k P u l s e C u r r e n t - W a t t sSL VDA2.8LCGRAPHST L - Lead Temperature - °C20406080100% O f R a t e d P o w e rFIGURE 3FIGURE 4TYPICAL CLAMPING VOLTAGE VS PEAK PULSE CURRENT0 5 10 15 20 25 30I PP - Peak Pulse Current AV C - C l a m p i n g V o l t a g e - V201612840SL VDA2.8LC APPLICA TION NOTECIRCUIT BOARD LAYOUT RECOMMENDATIONSCircuit board layout is critical for Electromagnetic Compatibility (EMC) protection. The following guidelines are recommended:✔The protection device should be placed near the input terminals or connectors, the device will divert the transient current immediately before it can becoupled into the nearby traces.✔The path length between the TVS device and the protected line should be minimized.✔All conductive loops including power and ground loops should be minimized.✔The transient current return path to ground should be kept as short as possible to reduce parasiticinductance.✔Ground planes should be used whenever possible.For multilayer PCBs, use ground vias.Figure 1: Bidirectional Common-Mode Protection Figure 2: Bidirectional Differential-Mode ProtectionElectronic equipment is susceptible to damage caused by Electrostatic Discharge (ESD), Electrical Fast Transients (EFT), and tertiary lightning effects. Knowing that equipment can be damaged, the SLVDA2.8LC was designed to provide the level of protection required to safe guard sensitive high speed data circuits. This product can be used to provide a level of protection to meet bidirectional requirements either in a common-mode or differential-mode configuration.BIDIRECTIONAL COMMON-MODE CONFIGURATION (Figure 1)The SLVDA2.8LC can provide up to four (4) lines of protection in a common-mode configuration as depicted in Figure 1.Circuit connectivity is as follows:✔Line 1 is connected to pin 8✔Line 2 is connected to pin 7✔Line 3 is connected to pin 6✔Line 4 is connected to pin 5✔Pins 1, 2, 3, and 4 are connected to groundBIDIRECTIONAL DIFFERENTIAL-MODE CONFIGURATION (Figure 2)The SLVDA2.8LC can provide up to four line pairs (4) of protection in a differential-mode configuration as depicted in Figure 2.Circuit connectivity is as follows:✔Line Pair # 1 is connected to pin 8 and 1✔Line Pair # 2 is connected to pin 7 and 2✔Line Pair # 3 is connected to pin 5 and 4✔Line Pair # 4 is connected to pin 6 and 3SL VDA2.8LC P ACKAGE OUTLINE & DIMENSIONSCOPYRIGHT © ProTek Devices 2005SPECIFICATIONS: ProTek reserves the right to change the electrical and or mechanical characteristics described herein without notice (except JEDEC). DESIGN CH ANGES: ProTek reserves the right to discontinue product lines without notice, and that the final judgement concerning selection and specifications is the buyer’s and that in furnishing engineering and technical assistance, ProTek assumes no responsibility with respect to the selection or specifications of such products.ProTek Devices2929 South Fair Lane, T empe, AZ 85282 T el: 602-431-8101 Fax: 602-431-2288 E-Mail: sales@ Web Site: 。
SED1565中文资料
FEATURES
• Direct display of RAM data through the display data RAM. RAM bit data: “1” Non-illuminated “0” Illuminated (during normal display) • RAM capacity 65 × 132 = 8580 bits • Display driver circuits SED1565***: 65 common output and 132 segment outputs SED1566***: 49 common output and 132 segment outputs SED1567***: 33 common outputs and 132 segment outputs SED1568***: 55 common outputs and 132 segment outputs SED1569***: 53 common outputs and 132 segment outputs
–i–
元器件交易网
SED1565 Series
GENERAL DESCRIPTION
The SED1565 Series is a series of single-chip dot matrix liquid crystal display drivers that can be connected directly to a microprocessor bus. 8-bit parallel or serial display data sent from the microprocessor is stored in the internal display data RAM and the chip generates a liquid crystal drive signal independent of the microprocessor. Because the chips in the SED1565 Series contain 65 × 132 bits of display data RAM and there is a 1-to-1 correspondence between the liquid crystal panel pixels and the internal RAM bits, these chips enable displays with a high degree of freedom. The SED1565 Series chips contain 65 common output circuits and 132 segment output circuits, so that a single chip can drive a 65 × 132 dot display (capable of displaying 8 columns × 4 rows of a 16 × 16 dot kanji font). The SED1567 Series chips contain 33 common output circuits and 132 segment output circuits, so that a single chip can drive 33 × 132 dot display (capable of displaying 8 columns × 2 rows of 16 × 16 dot kanji fonts). Thanks to the built-in 55 common output circuits and 132 segment output circuits, the SED1568*** is capable of displaying 55 × 132 dots (11 columns × 4 lines using 11 × 12 dots Kanji font) with a single chip. The SED1569 Series chips contain 53 common output circuits and 132 segment output circuits, so that a single chip can drive 53 × 132 dot display (capable of displaying 11 columns × 4 rows of 11 × 12 dot kanji fonts). Moreover, the capacity of the display can be extended through the use of master/slave structures between chips. The chips are able to minimize power consumption because no external operating clock is necessary for the display data RAM read/write operation. Furthermore, because each chip is equipped internally with a lowpower liquid crystal driver power supply, resistors for liquid crystal driver power voltage adjustment and a display clock CR oscillator circuit, the SED1565 Series chips can be used to create the lowest power display system with the fewest components for highperformance portable devices.
西恩迪放电数据表
C&D 12-7A LBT恒功率放电 - Watts Per Cell @ 25°C (77°F)恒电流放电 - Amps @ 25°C (77°F)C&D 12-9A LBT恒功率放电 - Watts Per Cell @ 25°C (77°F)恒电流放电 - Amps @ 25°C (77°F)C&D 12-12A LBT恒功率放电 - Watts Per Cell @ 25°C (77°F)恒电流放电 - Amps @ 25°C (77°F)C&D 12-18A LBT恒功率放电 - Watts Per Cell @ 25°C (77°F)恒电流放电 - Amps @ 25°C (77°F)C&D 12-26A LBT恒功率放电 - Watts Per Cell @ 25°C (77°F)恒电流放电 - Amps @ 25°C (77°F)C&D 12-40N LBT恒功率放电 - Watts Per Cell @ 25°C (77°F)恒电流放电 - Amps @ 25°C (77°F)C&D 12-54 LBT恒功率放电 - Watts Per Cell @ 25°C (77°F)恒电流放电 - Amps @ 25°C (77°F)C&D 12-65N LBT恒功率放电 - Watts Per Cell @ 25°C (77°F)恒电流放电 - Amps @ 25°C (77°F)C&D 12-76 LBT恒功率放电 - Watts Per Cell @ 25°C (77°F)恒电流放电 - Amps @ 25°C (77°F)C&D 12-88 LBT恒功率放电 - Watts Per Cell @ 25°C (77°F)恒电流放电 - Amps @ 25°C (77°F)C&D 12-100 LBT恒功率放电 - Watts Per Cell @ 25°C (77°F)恒电流放电 @ 25°C (77°F)C&D 12-114 LBT恒功率放电 - Watts Per Cell @ 25°C (77°F)恒电流放电 - Amps @ 25°C (77°F)C&D 12-127A LBT恒功率放电 - Watts Per Cell @ 25°C (77°F)恒电流放电 - Amps @ 25°C (77°F)C&D 12-150A LBT恒功率放电 - Watts Per Cell @ 25°C (77°F)恒电流放电 - Amps @ 25°C (77°F)C&D 12-158A LBT恒功率放电 - Watts Per Cell @ 25°C (77°F)恒电流放电 - Amps @ 25°C (77°F)C&D 12-200A LBT恒功率放电 - Watts Per Cell @ 25°C (77°F)恒电流放电 - Amps @ 25°C (77°F)C&D 12-211A LBT恒功率放电 - Watts Per Cell @ 25°C (77°F)恒电流放电 - Amps @ 25°C (77°F)C&D 12-242A LBT恒功率放电 - Watts Per Cell @ 25°C (77°F)恒电流放电 - Amps @ 25°C (77°F)。
士兰微SL库存型号推荐---赛矽电子何小姐
士兰微SL库存型号推荐SA7527(料管)士兰微SOP-8 1000SA1117BH-1.8TR 士兰微SOT-223 20000/箱 2500/盘SA1117BH-3.3TR 士兰微SOT-223 20000/箱 2500/盘SA1117BH-2.5TR 士兰微SOT-223 20000/箱 2500/盘SA1117BH-5.0TR 士兰微SOT-223 20000/箱 2500/盘SA1117BH-ADJTR 士兰微SOT-223 20000/箱 2500/盘SD4840P67K65 士兰微DIP-8 2000/盒SD4841P67K65 士兰微DIP-8 2000/盒SD4842P67K65 士兰微DIP-8 2000/盒SD4843P67K65 士兰微DIP-8 2000/盒SD45215 士兰微SOP-8 25000/箱 2500/盘SD4844P67K65 士兰微DIP-8 2000/盒SD4870TR 士兰微SOT23-6 3000/盘SC5272 士兰微TO-22OF 1000SC5262 士兰微TO-22OF 1000SD42522 士兰微SOP-8 2500/盘SD42525E 士兰微SOT89 2500/盘SA7527(盘装)士兰微SOP-8 2500/盘SDH6802 士兰微DIP-8 2000/盒SD6863 士兰微DIP-8 2000/盒SD6861P 士兰微DIP-8 2000/盒GB45215 士兰微SOP-8 25000/箱 2500/盘SD6834 士兰微DIP-8 2000/盒SD6832 士兰微DIP-8 2000/盒SD6864 士兰微DIP-8 2000/盒SD6953B 士兰微SOT-6 3000/盘WY0365 士兰微DIP-8 2000/盒SD45216 士兰微SOP-8 25000/箱 2500/盘SA1117BH-1.2TR 士兰微SOT-223 25000/箱 2500/盘SD6834G 士兰微DIP-8 2000/盒SD45214 士兰微SOP-8 25000/箱 2500/盘SD6835 士兰微DIP-8 2000/盒SD42527 士兰微SOP-8 2500/盘SD42560E 士兰微ESOP-8 2500/盘SC8113 士兰微TO-22OF 1000SD6834B 士兰微DIP-8 2000/盒SD7530S 士兰微SOP-8 2500/盘SD45217 士兰微SOP-8 2500SD6900 士兰微SOT-6 3000/盘SD4871 士兰微SOT-23-6 3000/盘SD6800 士兰微SOP-8 盘SD6901S 士兰微SOP-8 盘SD6902S 士兰微SOP-8 盘SA1117BH-1.5TR 士兰微SOT-223 2500/盘SA9801 士兰微SOP-20 100SD6857 士兰微SOP-8 3000SD6954 士兰微DIP-8 2000SD6830 士兰微DIP-8 2000SVD1N60B 士兰微TO-92 2000/盒SVD1N60DB 士兰微TO-92 2000/盒SVD2N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVD2N65F 士兰微TO-22OF 5000/箱/ 1000/盒SVD4N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVD4N65F 士兰微TO-22OF 5000/箱/ 1000/盒SVD7N65AF 士兰微TO-22OF 1000/盒SVD10N65F 士兰微TO-22OF 5000/箱/ 1000/盒SVD10N60F 士兰微TO-22OF 5000/箱/ 1000/盒SBD20C100T 士兰微TO-220T 5000/箱/ 1000/盒SBD20C100F 士兰微TO-22OF 5000/箱/ 1000/盒SVD1N60M 士兰微TO-251 24000/箱 4800/盒SVD1N60M(J)士兰微TO-251 4500/盒SVD12N65F 士兰微TO-22OF 5000/箱/ 1000/盒SVD12N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVD2N60M 士兰微TO-251 24000/箱 4800/盒SVD2N60M(J) 士兰微TO-251 4500/盒SFR16S20T 士兰微TO-220T 5000/箱/ 1000/盒SBD10C100F 士兰微TO-22OF 5000/箱/ 1000/盒SBD10C150T 士兰微TO-220T 5000/箱/ 1000/盒SBD10C100T 士兰微TO-220T 5000/箱/ 1000/盒SVD5N60F 士兰微TO-22OF 5000/箱/ 1000/盒SFR20S20T 士兰微TO-220T 5000/箱/ 1000/盒SVF1N60N 士兰微TO-126 200/包SVF10N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVD8N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVF2N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVF4N60D 士兰微TO-252 2500/盘SVF4N65F 士兰微TO-22OF 5000/箱/ 1000/盒SVF4N65M 士兰微TO-251 24000/箱 4800/盒SVF5N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVF8N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVF7N80F 士兰微TO-22OF 5000/箱/ 1000/盒SVF7N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVF12N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVF840F 士兰微TO-22OF 5000/箱/ 1000/盒SVF7N65F 士兰微TO-22OF 5000/箱/ 1000/盒SVF10N65F 士兰微TO-22OF 5000/箱/ 1000/盒SVF2N60MJ 士兰微TO-251 4500/盒SVF2N70M 士兰微TO-251 24000/箱 4800/盒SVF13N60AF 士兰微TO-22OF 1000/盒SVD2N60MJ 士兰微TO-251 4500/盒SVF12N65F 士兰微TO-22OF 5000/箱/ 1000/盒SVF2N60N 士兰微TO-126 3000/盒 200/包SVF5N60D 士兰微TO-252 2500/盘SVF13N50F 士兰微TO-22OF 5000/箱/ 1000/盒SVF4N70F 士兰微TO-22OF 5000/箱/ 1000/盒SVF2N60M 士兰微TO-251 24000/箱 4800/盒SVF9N90F 士兰微TO-22OF 5000/箱/ 1000/盒SVF4N90F 士兰微TO-, 22OF 5000/箱/ 1000/盒SVF2N65F 士兰微TO-22OF 5000/箱/ 1000/盒SVF4N65D 士兰微TO-252 2500/盘SVF830F 士兰微TO-22OF 5000/箱/ 1000/盒SBD20C45T 士兰微TO-220T 5000/箱/ 1000/盒SVF20N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVF1N60B 士兰微TO-92 2000/盒SVD7N60F 士兰微TO-22OF 5000/箱/ 1000/盒SVF830T 士兰微TO-220F 5000/箱SVD830T 士兰微TO-220T 10SVF2N60D 士兰微TO-252 2500SVF3N80F 士兰微TO-220F 1000/盘SVF4N60F 士兰微TO-220F 1000SBD20C150T 士兰微TO-220T 1000/盒SVF4N65MJ 士兰微TO-251 4500/盒SVF4N65M(S) 士兰微TO-251 4500/盒SVF2N60M(S) 士兰微TO-251 4800PCS/盒SBD20C150F 士兰微TO-220F 1000SVD2N70M 士兰微TO-251 4500/盒SVF1N60D 士兰微TO-252 2500/盒SVF8N80F 士兰微TO-220F 1000/盒SBD10C200F 士兰微TO-220F 1000/盒SBD20C200F 士兰微TO-220F 1000/盒SVF1N60M(S) 士兰微TO-251 80/管SVF4N60EF 士兰微TO-220F 1000/盒SVF5N60MJ 士兰微TO-251 4500/盒SFR10S40T 士兰微TO-220 50 SBD20C45F 士兰微TO-220 1000/盒SA7527STR 士兰微SOP-8 2500/盘。
SX1278data中文手册带书签
SX1278data中文手册带书签一、产品简介SX1278是一款高性能、低功耗的射频收发器，广泛应用于远程无线通信领域。
本手册旨在帮助用户了解SX1278的功能特点、电气特性、封装类型及使用方法，方便用户快速上手并充分发挥其性能。
二、功能特点1. 工作频率范围：137525MHz2. 可编程传输速率：0.018bps 300kbps3. 高灵敏度：低至148dBm4. 高线性输出功率：最高达+20dBm5. 支持多种调制方式：FSK、GFSK、OOK、4FSK、MSK等6. 内置温度传感器和低电压检测功能7. 小尺寸封装：QFN243mm×3mm三、电气特性1. 工作电压：1.83.7V2. 接收电流：10mA（典型值）3. 发送电流：100mA（典型值，+20dBm输出功率）4. 睡眠电流：≤200nA5. 待机电流：≤2.5μA四、封装类型1. GND：地2. VCC：电源正极3. ANT：天线接口4. SCLK：时钟信号输入5. MISO：数据输出6. MOSI：数据输入7. NSS：芯片选择8. NRESET：复位信号9. DIO0DIO5：数字IO口，可配置为中断输出或其他功能10. RXTX：收发控制信号11. BOOT：启动模式选择12. LDIO：低压检测输出13. TEMP：温度传感器输出五、使用方法1.硬件连接（1）将SX1278的GND、VCC、ANT分别连接到电路板的相应位置。
（2）将SCLK、MISO、MOSI、NSS、NRESET、DIO0DIO5、RXTX、BOOT、LDIO、TEMP等引脚按照实际需求连接到单片机或其他控制器。
2.软件配置（1）通过SPI接口向SX1278写入配置参数，包括工作频率、波特率、调制方式等。
（2）配置DIO0DIO5等引脚的功能，如设置为中断输出。
（3）根据实际需求，编写发送和接收程序。
3.发送数据（1）设置SX1278为发送模式。
CFD1275中文资料
NPN SILICON PLANAR DALINGTON POWER TRANSISTORS CFD1275, CFD1275ATO-220FP Fully Isolated Plastic PackageComplementary CFB949, CFB949AABSOLUTE MAXIMUM RATINGS (T a =25ºC)DESCRIPTIONSYMBOL Collector Base Voltage V CBO Collector Emitter Voltage V CEO Emitter Base VoltageV EBO RMS Isolation Voltage (for 1sec, R.H.** V ISOL (a)<30%, T a = 25oC)(b)Collector Current Peak I CPCollector CurrentI CCollector Power Dissipation @T c =25o C P C@T a=25oC Junction Temperature T jStorage Temperature RangeT stg** RMS Isolation Voltage: (a) 3500 V RMS with Package in Clip Mounting Position (b) 1500 V RMS with Package in Screw Mounting Position (for 1sec, R.H.<30%, T a =25oC; Pulse Test: Pulse Width <300µs, Duty Cycle<2%)ELECTRICAL CHARACTERISTICS (T a =25ºC unless specified otherwise)DESCRIPTION SYMBOL TEST CONDITIONMINTYP MAXUNIT Collector Cut Off CurrentI CBO V CB =60V, I E =0, CFD1275 1.0mA V CB =80V, I E =0, CFD1275A1.0mA Collector Cut Off CurrentI CEO V CE =30V, I B =0, CFD1275 2.0mA V CE =40V, I B =0, CFD1275A2.0mA Emitter Cut Off CurrentI EBO V EB =5V, I C =0 2.0mA Collector Emitter Voltage V CEO I C =30mA, I B =0CFD127560V CFD1275A 80VDC Current Gainh FE V CE =4V, I C =1A 1000*h FE V CE =4V, I C =2A 100010000Collector Emitter Saturation Voltage V CE(sat)I C =2A, I B =8mA 2.5V Base Emitter On Voltage V BE V CE =4V, I C =2A 2.8V Turn On Time t on0.5µs Storage Time t stg 4.0µs Fall Timet r1.0µs*h FE ClassificationA CFD1275 CFD1275AW UNIT V V 1500235ºC V V RMS V RMS A W 150460 8060 80535002- 55 to +150ºCI C =2A, I B1 = - I B2=8mAR : 1000 - 2500 Q : 2000 - 5000 P : 4000 - 10000CFD1275, CFD1275ATO-220FP Fully Isolated Plastic PackageTO-220FP Fully Isolated Plastic PackageTO-220 FP Tube PackingTO-220FP200 pcs/polybag 50 pcs/t u b e396 g m /200 pcs135 g m /50 pcs3" x 7.5" x 7.5"3.5" x 3.7" x 21.5"1K 1K17" x 15" x 13.5"19" x 19" x 19"16K 10K36 k g s 28 k g sPACKAG EN e t W e ight/Q t y DetailsSTANDARD PACKI N N E R C A RT O N B O XQ t y O U T E R C A R T O N B O XQ t y G r W t SizeSizePacking DetailDIM MIN MAX All diminsions in mm.A B C D E F G H J 9.962.604.503.107.9016.870.452.562.34K —L—M —10.363.004.903.308.2017.270.502.962.743.0830.050.80Pin Configuration 1. Base 2. Collector3. Emitter321Notes CFD1275, CFD1275ATO-220FP Fully IsolatedPlastic PackageCFD1275_1275ARev190302E DisclaimerThe product information and the selection guides facilitate selection of the CDIL's Discrete Semiconductor Device(s)best suited for application in your product(s)as per your requirement.It is recommended that you completely review our Data Sheet(s)so as to confirm that the Device(s)meet functionality parameters for your application.The information furnished in the Data Sheet and on the CDIL Web Site/CD are believed to be accurate and reliable.CDIL however,does not assume responsibility for inaccuracies or incomplete information.Furthermore,CDIL does not assume liability whatsoever,arising out of the application or use of any CDIL product;neither does it convey any license under its patent rights nor rights of others.These products are not designed for use in life saving/support appliances or systems.CDIL customers selling these products(either as individual Discrete Semiconductor Devices or incorporated in their end products),in any life saving/support appliances or systems or applications do so at their own risk and CDIL will not be responsible for any damages resulting from such sale(s).CDIL strives for continuous improvement and reserves the right to change the specifications of its products without prior notice.CDIL is a registered Trademark ofContinental Device India LimitedC-120 Naraina Industrial Area, New Delhi 110 028, India.Telephone + 91-11-2579 6150, 5141 1112 Fax + 91-11-2579 5290, 5141 1119email@ 。
D127中文资料
150
mV P-P
Ripple & Noise (20 MHz)
5
mV rms
Output Power Protection Temperature Coeffiecient Output Short Circuit
120
!0.01
!0.02 0.5
% %/1C Sec.
General
Parameter
Typ. !1.0 !0.1 !1.2
Max. !3.0 !1.0 !1.5
Units % % %
Load Regulation
See Model Selection Guide
Ripple & Noise (20 MHz)
50
75
mV P-P
Ripple & Noise (20 MHz)
Over Line Load & Temp.
元器件交易网
MicroPower Direct
1W, Miniature SIP Single & Dual Output
DC/DC Converters
D100 Series
Key Features
! 1,000 VDC Isolation ! 1W Output Power ! Wide Model Selection
Conditions
Min. Typ. Max.
Units
Isolation Voltage
60 Seconds 1,000
VDC
Isolation Resistance
500 VDC 1,000
MΩ
Isolation Capacitance
Devicelist_QD77
缓冲存储器地址Un\G■
QD77MS4
QD77MS16
Un\G36 Un\G37 Un\G38 Un\G39 Un\G40 Un\G41 Un\G42 Un\G43 Un\G44 Un\G45 Un\G46 Un\G47 Un\G48 Un\G49 Un\G50 Un\G51 Un\G52 Un\G53 Un\G54 Un\G55 Un\G56 Un\G57 Un\G58 Un\G59 Un\G60 Un\G61 Un\G62 Un\G63 Un\G64 Un\G65 Un\G67 Un\G68.4-7 Un\G68.8-B Un\G68.C-F
Un\G30 Un\G31.0 Un\G31.1 Un\G31.3 Un\G31.4 Un\G31.6 Un\G31.8
Un\G32 Un\G33 Un\G34 Un\G35
-1-
856730851.xls/参数区
详细参数2 Pr.□
项目
Pr.25 加速时间1
Pr.26 加速时间2
Pr.27 加速时间3
-
缓冲存储器地址Un\G■
QD77MS4
QD77MS16
Un\G70
Un\G70
Un\G71
Un\G71
Un\G72
Un\G72
Un\G73
Un\G73
Un\G74
Un\G74
Un\G75
Un\G75
Un\G76
Un\G76
Un\G77 Un\G78
Un\G77 Un\G78
缓冲存储器地址Un\G■
Un\G11
Un\G12
Un\G12
Un\G13
Un\G13
Un\G14 Un\G15
金翰牌工业用缝纫机操作手册说明书
NO : CS 5940N02金翰牌工棠用缝纫械GOLDEN WHEEL INDUSTRIAL SEWING MACHINE Ti t－OL AAτAAI nu nuυ 产气υF气υ／／／／ nU OLA哇AAI nu nU Fhd Fhd 一－P、u nδρlνρEU INSTRUCTION MANUAL 操作手册后欠莉3月支f分手于严良乏〉司CHEE SIANG INDU STRIAL CO., LTD. 2016.02.041. SETTING UP 安裝1. Inserting the Needle裝置機針CAUTION: Switch off the machine! Danger ofinjury by unintentional starting ofthe machine!●Set the needle bar at its highest point.●Loosen screw 1.●Push needle 2 fully into the needle bar (thelong needle groove must face to the front.)●Tighten screw 1.注意：關閉電源！防止無意中啟動機器！◆ 將針棒提升到最高位置◆ 鬆開螺絲1◆ 將機針2插入至針棒底部（機針的長勾槽朝向正前方）◆ 擰緊螺絲12. Threading the Needle Thread and Regulating its Tension 穿針線與調整線張力●Thread the needle thread as shown in theleft figure.●Regulate the needle thread by turningknurled nut 1.◆ 如左圖所示穿針線◆ 旋轉螺帽1調整針線的張力3. Threading the Looper Thread and Regulating its Tension 穿底線與調整線張力●Open the looper cover and swing out thread guide plate 1.●Thread the looper thread as shown in the figure below and pull it under guide plate 2.●Regulate the looper thread by turning knurled nut 4.◆ 打開勾針護蓋及過線導引板1◆ 如上圖所示穿底線並繞過導線板2的下方◆ 旋轉螺帽4調整底線的張力2. CARE AND MAINTENANCE 維護與保養1. Machine Oil Level 油位高度Caution: Check oil level before each use.●The oil level must be between the markingsin the inspection glass.●If required, refill oil through hole 1.Caution: Only use oil with a mean viscosity of22.0mm²/s at 40°C and a density of0.865 g/cm³at 15°C!注意：每次使用前需檢查油位的高度◆ 油位的高度須介於兩個刻度線之間◆ 必要時，由加油孔1補充潤滑油注意：需使用潤滑油黏度約22.0mm²/s（在40°C時）且密度約0.865 g/cm³（在15°C時）2. Lubricating the Top Feed Joints 潤滑上送料連桿●Lubricate the points marked in theillustration with a drop of oil once a weekor after the machine has stood still forlonger periods.Caution: Only use oil with a medium viscosityof 10.0 mm²/s at 40°C and a density of0.847 g/cm³at 15°C.◆ 每週一次或長期不使用時在圖示的箭頭指示部位添加潤滑油注意：需使用潤滑油黏度約10.0mm²/s（在40°C時）且密度約0.847 g/cm³（在15°C時）3. Checking and Adjusting the Air Pressure 檢查與調整空氣壓力●Before operating the machine, always checkthe air pressure on gauge 1.●Gauge 1 must show a pressure of 6 bar.●If necessary adjust to this reading.●To do so, pull knob 2 upwards and turn it sothat the gauge shows a pressure of 6 bar.◆ 在操作機器之前，請檢查壓力表1的空氣壓力◆ 壓力表1的壓力須指示在6 bar◆ 必要時，調整壓力至此值◆ 調整時，將旋鈕2往上拉，轉到指針指示壓力在6 bar位置，再壓下旋鈕23. ADJUSTMENT 機器的調整1. Control and Adjustment Aids 控制與輔助調整設置Note: By inserting the adjustment pin (ø5mm) to the marked holes 1, 2, 3and 4 with, the desired needle barpositions can fixed exactly.備註：利用調整用平行銷(ø 5mm)插入對應1, 2, 3及4的記號孔時，可得到準確的針棒位置●Turn the balance wheel until the needle bar is approximately in the desired position.●Insert the adjustment pin into the appropriate hole and apply pressure.●Turn the balance wheel slightly backwards and forwards, until the pin locks into the rear crankrecess, in this way the main shaft of the machine is locked.Adjustment hole 1 = top dead centre of the needle bar (t.d.c.)Adjustment hole 2 = bottom position of top feed dogAdjustment hole 3 = bottom dead centre of the needle bar (b.d.c.)Adjustment hole 4 = neutral position of main feed dog and differential feed dog◆旋轉手輪使針棒到達所需的大略位置◆將調整用平行銷插入對應的記號孔，並施以適當的推力◆稍微前後轉動手輪使平行銷插入凸輪的溝槽中，以鎖定機器的主軸調整記號孔1 = 針棒上死點調整記號孔2 = 上送料齒下死點調整記號孔3 = 針棒下死點調整記號孔4 = 主送料齒與差動送料齒的中立位置2. Needle to Needle Hole 機針與針孔位置 Requirement1. As seen from the direction of feeding, needle 5 should be in the centre of the needle hole.2. The distance between needle 5 and the front edge of the needle hole should be approximately0.8mm. 調整需求調整需求：：1. 從送料方向觀察，機針5必須對準針孔的中心2. 機針5與針孔前緣的距離需約為0.5mm● Loosen screw 1 and 2.● Adjust needle bar frame 3 according to requirement 1) and tighten screw 1.● Loosen screw 4 and turn needle bar frame 3 according to requirement 2).● Tighten screws 2 and 4.◆ 鬆開螺絲1與2◆ 根據調整需求1) 調整針柱座3的左右位置，然後擰緊螺絲1◆ 鬆開螺絲4，根據調整需求2) 調整針柱座3的前後位置◆ 擰緊螺絲2與43. Preliminary Adjustment of Needle Height 機針高度的初步調整 Requirement調整需求CS-5940 With the needle bar at t.d.c. (adjustment hole 1), the distance X between the needle plate and the needle tip should be 11 mm.當針棒在上死點時（調整記號孔1），針尖端與針板面的距離須等於11 mmCS-5941 With the needle bar at t.d.c. (adjustment hole 1), the distance X between the needle plate and the needle tip should be 14 mm.當針棒在上死點時（調整記號孔1），針尖端與針板面的距離須等於14 mm● Bring needle bar 1 to t.d.c.● Adjust needle bar 1 (screws 2) according to the requirement.◆ 將針棒1提升到上死點◆ 根據調整需求（鬆開螺絲2）設定針棒1的高度4. Neutral Position of Main Feed Dog 主送料齒的中立位置 Requirement調整需求When the stitch length is set at “0”, there should be no feeding motion of the main feed dog 7. 當縫目長度設定在「0」的位置時，主送料齒無前後運動● Unscrew set screw 1 and nut 2 (stitch length limitation disengaged).● Bring stitch length adjustment lever 3 to “0” mark.● Loosen screw 4 to such an extent that crank 5 can be rotated on the shaft with some resistance. ● While turning the balance wheel continuously, adjust crank 5, so that crank 6 does not move. ● Tighten screw 4.Note: Screw 1 and nut 2 remains loosened for further adjustments.(Stitch length limitation is still disengaged).◆ 鬆開螺絲1與螺帽2（解除縫目長度限制）◆ 將縫目長度調整桿推到「0」的刻度位置◆ 鬆開螺絲4至一有限的程度使擺動臂5可在軸上旋轉並具有阻力◆ 連續轉動手輪，並調整擺動臂5，使擺動臂6不轉動◆ 擰緊螺絲4注意：螺絲1與螺帽2仍然保持鬆開狀態，以便做後續的調整（縫目長度限制仍然保持在解除狀態）5. Neutral Position of Differential Feed Dog 差動料齒的中立位置 Requirement調整需求With the stitch length set at “0” and the adjustment gauge 1 fitted, there should be no movement of the differential feed dog 5.當縫目長度設定在「0」的位置且調整治具1裝入時，差動送料齒5無前後運動● Set stitch length at “0”.● Fit adjustment gauge 1.● Loosen screw 2 to such an extent that crank 3 can be moved on the shaft with some resistance. ● While turning the balance wheel continuously, adjust crank 3, so that crank 4 does not move. ● Tighten screw 2.Note: Adjustment gauge 1 remains fitted for further adjustments.◆ 將縫目長度設定在「0」的刻度位置 ◆ 裝入調整治具1◆ 鬆開螺絲2至一有限的程度使擺動臂3可在軸上旋轉並具有阻力 ◆ 連續轉動手輪，並調整擺動臂3，使擺動臂4不轉動 ◆ 擰緊螺絲2注意：調整治具1仍然保持裝入狀態，以便做後續的調整When the stitch length is set at “4” and the needle bar is positioned at neutral position of feed dog (adjustment hole 4) and the adjustment gauge 8 is fitted, the main feed dog and the differential feed dog should not move when roller 5 is operated.當縫目長度設定在「4」的位置，針棒設定在送料齒的中立位置（調整記號孔4），且調整治具8在裝入狀態，當推動滾輪5時，主送料齒與差動送料齒無前後運動● Slightly loosen screws 1 and 2 (4 screws).● Bring needle bar to adjustment hole 4 and adjust stitch length to “4”.● While moving roller 5 up and down continuously, turn eccentrics 6 and 7 so that the cutout is visible and the cranks 3 and 4 do not move. ● Tighten screws 1 and 2.◆ 稍微鬆開螺絲1與2（共4個螺絲）◆ 將針棒移到調整記號孔4的位置，以及將縫目長度設定在「4」的位置◆ 上下推動滾輪5，同時調整偏心輪6與7的位置，使擺臂3與4無運動。
DC1278 快速入门指南说明书
QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 12786-CHANNEL, 14-BIT, 1.5MSPS SIMULTANEOUS SAMPLING ADCLTC2351-14 DESCRIPTIONDemonstration circuit 1278 features the LTC2351-14 6-channel, 14-Bit, simultaneous sampling ADC. Total throughput is 1.5MSPS; 250KSPS per channel, with a typical channel-to-channel aperture skew of 200ps. The board is designed to be used with the DC890B Fast DAACS data collection board to show the AC performance of the LTC2351-14. Alternatively, the board can be directly connected to an application to evaluate the ADC’s performance.Design files for this circuit board are available. Call the LTC factory.LTC is a trademark of Linear Technology CorporationQUICK START PROCEDURE BASIC CONNECTIONSConnect DC1278 to a DC890B USB High Speed Data Collection Board using connector J2. Connect DC890B to a host PC with a standard USB A/B cable. Apply 5-7V DC to the VIN and GND terminals. Apply a 25MHz 3.3Vp-p sine wave or square wave to connec-tor J3. Note that J3 has a 50 ohm termination resistor to ground. CH0-CH5 are provided through connector J1 (See schematic for details.). Run the QuickEval II (Pscope.exe) evaluation software supplied with DC890 or download it from /software.Figure 1. CONNECTION DIAGRAM 40 pin AnalogSignal Connector (Refer to Schematic)To DC890BController Master clock at 98x conversion rate, 3.3Vpp Sine or Square wave (See Hardware Setup Section)5-7VDC SupplyFigure 2.SOFTWARE SCREENSHOTSOFTWARE CONFIGURATIONCONFIGURE DEVICEThe Pscope software should automatically config-ure itself after detecting the demo board. To change from Bipolar to Unipolar mode it will be necessary to manually configure the software. In the CONFIGURE menu (See Figure 3) select Device, which will bring up another window. In this window, select User Configure and adjust the other settings as follows:Bits: 14Alignment: 14Bipolar: Checked if BIP jumper is set high, Un-Checked if BIP jumper is set to low. (Default is checked)Channels: 6Positive Edge Clk: UN-CheckedFPGA: Serial 1408 Class. CONFIGURE SOFTWARE SCREENThe software interface is highly configurable and displays any combination of time domain data, fre-quency domain data, primitive wave and perform-ance parameters (SNR, THD, SINAD, etc.). The screen can be broken into multiple panes as shown in Figure 2. Complete documentation on configur-ing PSCOPE can be found in the help file.Click the COLLECT button to begin acquiring data. Complete software documentation is available from the Help menu item, as features may be added peri-odically.HARDWARE SET-UPJUMPERSJP1, JP2 - Select number of channels to convert and Unipolar / Bipolar selection. NCH2, NCH1, NCH0 are set to 111 which selects all six channels. These switches should be left in this position when running Pscope software. UNI/BIP selection applies to all channels. Refer to Figure 4.JP3 –Enable Oscillator and Oscillator Division. Presently not used. This may be used in the future as serial clock, to allow a convert signal at 1X the conversion rate.JP4 – Digital Interface Header. Provides direct con-nection to the LTC2351-14 CONV, SDO, and SCK pins. This can be used to either monitor signals with a logic analyzer or to drive the LTC2351-14 directly from the customer’s test equipment or pro-totype circuitry. DC890B should be disconnected before driving the LTC2351-14 externally with JP4. Note that R34 should be removed if the CONV sig-nal is being driven externally.JP5 – Currently not used SIGNAL CONNECTIONSJ1 –40 pin connector with CH0-CH5 differential inputs, multiple grounds, a mid-supply bias voltage and Vref. Refer to schematic for pin out. The mid-supply bias voltage can be used to bias the minus ADC inputs for bipolar conversions.J2 – Data connections to DC890B collection board. J3– Conversion Clock Input. This input has a 50 ohm termination resistor, and is intended to be driven by a 3.3Vpp sine or square wave. This clock is divided by 98 in the DC890B collection board to control the serial interface and convert pulse. To run the LTC2351-14 at maximum conversion rate, apply a 25MHz signal to this input.GROUNDING AND POWER CONNECTION Connect a 5V to 7V power supply to the Vin and GND turret posts. For optimum performance, this supply should be floating with respect to any signal generators connected to the analog inputs.Figure 4 – JP1, JP2 CONFIGURATION。
ISIS-7-Professional元件库列表及中英文对照整理版要点
模拟芯片(Analog ICs )放大器(Amplifiers)比较器(Comparators)显示驱动器(Display Drivers)过滤器(Filters)数据选择器(Multiplexers)稳压器(Regulators)定时器(Timers)基准电压(Voltage Referenee) 杂类(Miseellananeous)电容(Capaeitors)可动态显示充放电电容(An imated)音响专用轴线电容(Audio Grade Axial)轴线聚苯烯电容(Axial Lead Polyprope ne)轴线聚苯烯电容(Axial Lead Polystyre ne)陶瓷圆片电容(Ceramic Disc)去耦片状电容(Deeoupling Disc)普通电容(Generic)高温径线电容(High Temp Radial)高温径线电解电容(High Temperature Axial Electrolytic)金属化聚酯膜电容(Metallised Polyester Film) 金属化聚烯电容(Metallised Polypropene)金属化聚烯膜电容( Metallised Polyprope ne Film)小型电解电容(Miniture Electrolytic)多层金属化聚酯膜电容( Multilayer Metallised Polyestern Film) 聚脂膜电容(Mylar Film)镍栅电容(Nickel Barrier)无极性电容(Non Polarised)聚脂层电容(Polyester Layer)径线电解电容(Radial Electrolytic)树脂蚀刻电容(Resin Dipped)钽珠电容(Tantalum Bead)可变电容(Variable)VX 轴线电解电容(VX Axial Electolytic)连接器(Connectors)音频接口( Audio)D 型接口( D-Type)双排插座(DIL)插头(Header Blocks)PCB 转接器(PCB Transfer)带线(Ribbon Cable)单排插座(SIL)连线端子(Terminal Blocks)杂类(Miscellananeous)数据转换器(Data Converter) 模/数转换器(A/D converters) 数/模转换器(D/A converters) 采样保持器(Sample & Hold) 温度传感器(Temperature Sen sore) 调试工具(Debugging Tools) 断点触发器(Breakpoint Triggers) 逻辑探针(Logic Probes) 逻辑激励源(Logic Stimuli) 二极管(Diode) 整流桥(Bridge Rectifiers) 普通二极管(Generic) 整流管(Rectifiers) 肖特基二极管(Schottky) 开关管(Switching) 隧道二极管(Tunnel) 变容二极管(Varicap) 齐纳击穿二极管(Zener)ECL 10000 系列(ECL 10000 Series) 各种常用集成电路机电(Electromechanical)各种直流和步进电机电感(Inductors) 普通电感(Generic) 贴片式电感(SMT In ductors) 变压器(Transformers) 拉普拉斯变换(Laplace Primitives) 一阶模型(1st Order) 二阶模型(2st Order) 控制器(Controllers) 非线性模式(Non-Linear) 算子(Operators) 极点/零点(Poles/Zones) 符号(Symbols) 存储芯片(Memory Ics) 动态数据存储器(Dynamic RAM) 电可擦除可编程存储器(EEPROM) 可擦除可编程存储器(EPROM) I2C 总线存储器(I2C Memories) SPI 总线存储器(SPI Memories) 存储卡(Memory Cards) 静态数据存储器(Static Memories) 微处理器芯片(Microprocess ICs) 6800 系列(6800 Family)8051 系列(8051 Family)ARM 系列(ARM Family)AVR 系列(AVR Family)Parallax 公司微处理器(BASIC Stamp Modules)HCF11 系列(HCF11 Family)PIC10 系列(PIC10 Family )PIC12 系列(PIC12 Family)PIC16 系列(PIC16 Family)PIC18 系列(PIC18 Family)Z80 系列(Z80 Family)CPU 外设(Peripherals)杂项(Miscellaneous)含天线、ATA/IDE硬盘驱动模型、单节与多节电池、串行物理接口模型、晶振、动态与通用保险、模拟电压与流符号、交通信号灯建模源(Modelling Primitives)模拟(仿真分析)(Analogy-SPICE)数字(缓冲器与门电路)(Digital-Buffers&Gates)数字(杂类)(Digital--Miscellaneous)数字(组合电路)(Digital--Combinational)数字(时序电路)(Digital--Sequential)混合模式(Mixed Mode)可编程逻辑器件单元(PLD Eleme nts)实时激励源(Realtime Actuators)实时指示器(Realtime Indictors)运算放大器(Operational Amplifiers)单路运放(Single)二路运放(Dual)三路运放(Triple)四路运放(Quad)八路运放(Octal)理想运放(Ideal)大量使用的运放(Macromodel)光电子类器件(Optoelectronics)七段数码管(7-Segment Displays)英文字符与数字符号液晶显示器(Alpha nu meric LCDs) 条形显示器(Bargraph Displays)点阵显示屏(Dot Matrix Display)图形液晶(Grphical LCDs)灯泡(Lamp)液晶控制器(LCD Controllers)液晶面板显示(LCD Pan els Displays)发光二极管(LEDs)光耦元件(Optocouplers)串行液晶(Serial LCDs)可编程逻辑电路与现场可编程门阵列(PLD&FPGA)无子类电阻(Resistors)0.6W 金属膜电阻(0.6W Metal Film)10W 绕线电阻(10W Wirewound)2W 金属膜电阻(2W Metal Film)3W 金属膜电阻(3W Metal Film)7W 金属膜电阻(7W Metal Film)通用电阻符号(Generic)高压电阻(High Voltage)负温度系数热敏电阻(NTC)排阻(Resisters Packs)滑动变阻器(Variable)可变电阻(Varistors)仿真源(Simulator Primitives)触发器(Flip-Flop)门电路(Gates)电源(Sources)扬声器与音响设备(Speaker&Sou nders)无子分类开关与继电器(Switch&Relays)键盘(Keypads)普通继电器(Generic Relays)专用继电器(Specific Relays)按键与拨码(Switchs)开关器件(Switching Devices)双端交流开关元件(DIACs)普通开关元件(Generic)可控硅(SCRs)三端可控硅(TRIACs)热阴极电子管(Thermionic Valves)二极真空管(Diodes)三极真空管(Triodes)四极真空管(Tetrodes)五极真空管(Pentodes)转换器(Transducers)压力传感器(Pressures)温度传感器(Temperature)晶体管(Transistors)双极性晶体管(Bipolar)普通晶体管(Generic)绝缘栅场效应管(IGBY/Insulated Gate Bipolar Transistors结型场效应晶体管(JFET)金属-氧化物半导体场效应晶体管(MOSFET)射频功率LDMOS晶体管(RF Power LDMOS) 射频功率VDMOS晶体管(RF Power VDMOS) 单结晶体管(Unijunction) CMOS 4000 系列(CMOS 4000 seriesTTL 74 系列(TTL 74 series)TTL 74增强型低功耗肖特基系列(TTL 74ALS Series)TTL 74增强型肖特基系列(TTL 74AS Series)TTL 74 高速系列(TTL 74F Series)TTL 74HC 系列/CMOS 工作电平(TTL 74HC Series)TTL 74HCT 系歹U /TTL 工作电平(TTL 74HCT Series)TTL 74低功耗肖特基系列(TTL 74LS Series)TTL 74 肖特基系列(TTL 74S Series)加法器(Adders)缓冲器/驱动器(Bufers&Drivers)比较器(Comparators)计数器(Counters)解码器(Decoders)编码器(Encoders)存储器(Memory)触发器/锁存器(Flip-Flop&Latches)分频器/定时器(Frequency Dividers & Timers) 门电路/反相器(Gates&lnverters)数据选择器(Multiplexers)多谐振荡器(Multivibrators)振荡器(Oscillators)锁相环(Phrase-Locked-Loop,PLL)寄存器(Registers)信号开关(Signal Switches)收发器(Tranxceivers)杂类逻辑芯片(Misc.Logic)Proteus isis 的元件库中英对照Proteus元件名称对照1元件名称屮文名说明7407 驱动门1N914 二极管74Ls00 与非门74LS04 非门74LS08 与门74LS390 TTL 双十进制计数器7SEG 4 针BCD-LED俞出从0-9对应于4根线的BCD码7SEG 3-8 译码器电路BCD-7SEG[size=+0]转换电路ALTERNATOR 交流发电机AMMETER-MILLI m安培计AND 与门BATTERY 电池/电池组BUS 总线CAP 电容CAPACITOR 电容器CLOCK 时钟信号源CRYSTAL 晶振D-FLIPFLOP D 触发器FUSE 保险丝GROUND 地LAMP 灯LED-RED 红色发光二极管LM016L 2 行16列液晶可显示2行16列英文字符，有8位数据总线D0-D7, RS R/W EN三个控制端口（共14线），工作电压为5V。
UL1278中文版
UL1278 可移动的挂墙式或吊顶式室内电暖器的标准的翻译（ UL1278 2000 年 6 月 21 日）翻译版本：A版目录介绍1．范围2．概述3．术语4．元件5．测试单位6．参考文件结构7 外壳8带电体的可接近性9 运动部件的可接近性10 发热元件的防护11 承受压力的部件12 塑胶材料13 传热的液体14元件的装配15防腐蚀保护16 电源连接17 载流部件18 内部引线19发热元件20 发热元件的支撑21电气绝缘22隔热23 Materials in an air-handling comparment 24马达25马达过载保护26 过电流保护27 次级电流28 限温控制器29 警告装置30灯头31 指示灯32 开关33 自动控制器和控制电路34间隙35接地性能36概述37输入功率测试38泄漏电流39温升测试40 警告装置的耐久性测试41 非正常操作测试42 耐久性测试43 短路测试44 过载测试-高压变压器45 烧毁测试-高压变压器46 元件失效测试47 电气强度测试48 绝缘电阻测试49 喷水测试50 可移动式的电暖器的稳定性测试51 发热元件的支撑器的冲击测试52 跌落测试53 电源线警告标贴的耐久性测试54 人身伤害的防护的测试55 旋钮的紧固性测试5657 静态水压测试58 电源线拉力测试59 标贴的永久性测试生产线上的测试60耐压测试61接地测试62 翻倒测试额定值63概述标识64概述65 说明书附录SA 某些辐射式电暖器(略)附录SB 在浴室，洗衣店工类似的室内使用的电暖器（略）附录SC 用半导体发热元件的可移动式电暖器（略）附录SD 跟进服务（略）附录SE DIRECT PLUG-IN HEATERS （略）1．介绍1．范围1.1这些要求适用于额定电压不超过600V的可移动的且挂墙式或吊顶式的电暖器。
这些电暖器用在普通场所1.2这些要求不适用于固定式电暖器，LOCATION DELICATED HEATER, BASEBOARD HEATERS, 管道式电暖器，中心加热的炉，PANEL OR CABLE-TYPE RADIANT-HEATING EQUIPMENT。
船舶SED电气设计系统操作使用说明书
SSD1289中文手册
SSD12891 概述SSD1289是集成RAM、电源电路、门驱动器、驱动源于一体的TFTLCD驱动控制器。
它最大可驱动分辨率为240×320的26.2万色RGB非晶TFT面板。
SSD1289同样集成了控制功能。
其包括172800字节的图形显示数据区。
因此，通过兼容的并行或串行接口，它可以与像6800及8080系列的8-/9-/16-/18位通用微控制器接口，将数据写入图形显示数据区。
另外，集成辅助的18-/16-/6位的视频接口用于动画图像的显示。
SSD1289嵌入了DC-DC变压器和电压转换器，用于提供芯片驱动所有外部底层元件所必需的电压。
芯片包含的一个通用电压发生电路用于驱动TFT显示器的反电极。
另外还有一个整合的伽马控制电路，用于配合软指令以提供最大的灵活性和最佳的显示效果。
DS1289工作的最低电压能低到1.16V，同时提供不同的节电模式。
它适用于任何需要长时间运行的，用便携式电池驱动的紧凑型设备。
2 特点●工作电压：V DD = 1.65V-1.95V （不规则的逻辑输入）= 1.4V-3.6V （规则的逻辑输入）VDDIO= 2.5V-3.6V （内部模拟电路的电源供应）VCI●最大的门驱动输出电压：30Vp-p●驱动源输出电压：0-5V●低电流睡眠模式和8-color节能显示模式●显示尺寸：240RGB×320●显示颜色支持：26.2万色RGB非晶TFT面板●8/9/16/18位的6800系列/8080系列的并行接口和串行接口●支持动画显示的18位RGB接口（VSYNC, HSYNC, DOTCLK, DEN, and D0-17）●片上172800字节的图形显示数据区●RAM写同步功能●支持线性和帧转换●软件可选中心滚屏、顶部滚屏、底部滚屏和全部滚屏。
●Source and Gate scan direction control●片内电平发生器●片内电压转换器高达6x/-6x●可编程的伽马矫正曲线●对VCOM标准的稳定存储●可编程的公共电极电压幅度和一般结构的Cs水平●支持Cs的门结构●COG包可用3 订购信息4 结构图名字类型功能描述DENinput 显示的时间信号Display enable pin from controller.VSYNC 帧同步信号HSYNC 线性同步信号DOTCLK 点时钟和振荡源SHUTinput 逻辑控制关闭显示引脚，使进入睡眠模式- Connect to V DDIO for sleep mode- Connect to V SS for normal operating modeRLinput 面板映射控制选择源驱动数据的转换方向- Connect to V DDIO for display first RGB data at S0-S2- Connect to V SS for display first RGB data at S719-S717GD 选择第一个输出门- GD = ‘0’, G0 is 1st output Gate, Gate sequence G0, G1, G2, G3, …,G318, G319- GD = ‘1’, G1 is 1st output Gate, Gate sequence G1, G0, G3, G2, …,G319, G318TB 选择驱动门扫描方向- Connect to V DDIO for Gate scan from G0 to G319- Connect to V SS for Gate scan from G319 to G0BGR选择颜色映射- Connect to V DDIO for Blue-Green-Red mapping8 模块功能描述系统接口：系统接口单元由3个功能模块组成，来驱动6800系列的并行接口、8080系列的并行接口、3线串行接口、4线串行接口。
24位高性能模数转换器ADS1274_ADS1278及其应用
６ 结束语
ＡＤＳ１２７４／１２７８ 是基于 Δ－ Σ技术的 ２４ 位高性 能工业模数转换器，内部集成有多个独立的高阶斩 波稳定调制器和 ＦＩＲ 数字滤波器，具有优良的 ＡＣ 和 ＤＣ 性能，可实现 ４／８ 通道同步采样，支持高速、 高精度、低功耗、低速 ４ 种工作模式；数据输出可选 帧同步或 ＳＰＩ 串行接口，每个接口均支持菊花链连 接，可应用于要求严格的多通道信号采集系统，如 振动分析、医疗监控、动态应变测量设备等。 参考文献： ［１］ Ｔｅｘａｓ Ｉｎｓｔｒｕｍｅｎｔｓ Ｉｎｃｏｒｐｏｒａｔｅｄ． ＡＤＳ１２７４／ＡＤＳ－
２４位高性能模数转换器 ＡＤＳ１２７４／ＡＤＳ１２７８ 及其应用
王怀秀 １， ２， 朱国维 ２
（１． 北京建筑工程学院，北京 １０００４４；２． 中国矿业大学（北京）煤炭资源教育部重点实验室，北京 １０００８３）
摘要：介绍了是德州仪器的多通道 ２４ 位工业模数转换器 ＡＤＳ１２７４／ＡＤＳ１２７８ 的性能特点、引脚功
监控、声学／动态应变测量及压力测量设备等。
２ 性能特点
传统的具有较高漂移性能的工业 Δ－ ΣＡＤＣ 采 用导通带宽滑落幅度很大的数字滤波器，来得尽可 能满足 ＤＣ 测量需求的有限信号带宽。针对音频应 用的高分辨率 ＡＤＣ 能够提供更大的可用带宽，但 偏 移 与 漂 移 规 范 远 低 于 工 业 ＡＤＣ。 ＡＤＳ１２７４／ ＡＤＳ１２７８ 将两种类型的转换器相结合，实现最佳 ＤＣ 与 ＡＣ 规范的高精度工业测量。具体特点如下：
图 ２ ＴＤＭ 模式，固定位置数据（通道 １ 和通道 ３ 为掉电状态）输出
－ ５６－
《国外电子元器件》２００８ 年第 ５ 期 ２００８ 年 ５ 月
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Dot Matrix LCD Controller DriverPF282-07q 1/8, 1/11 or 1/16 Duty Dot Matrix Driveq Built-in Character Generator ROM and RAM ( )q Maximum Simultaneous Display of 80 Characters (With extension LCD driver)SED1278F/Ds DESCRIPTIONThe SED1278F/D is a dot matrix LCD controller/driver which is dedicated to character display. It is capable of displaying up to 80 characters under 4-bit/8-bit MPU control.The built-in character generator ROM has an extended capacity of 240 different characters, each being generated in a 5×10 dots font compatible with a 1/11 duty. In addition, the SED1278F/D contains 64 bytes of character generator RAM in which the user can store 8 different characters, each consisting of 558 dots. These memory features offer high flexibility in character display.The guaranteed minimum LCD driving voltage is 3V, and this makes the SED1278F/D suitable for driving low voltage LCDs.s FEATURESq Display RAM ..............................80 bytes (80 characters)q Character generator ROM..........240 characters (Able to 256 characters)q Character generator RAM ..........8 charactersq Built-in CR oscillator, Built-in power-on reset circuitq Maximim display dimension .......40 characters52 lines, 80 characters51 line(When accompanied with SED1181F LA /D LA , SED1681F OA /D OA )q 1/8, 1/11 or 1/16 duty matirx drive (fixed by command)q 2 flame AC wave-form driveq High-speed bus interface with 4-bit/8-bit MPU q Powerful display control instructionsq Character ...................................5!7 dots+Cursor line (5!8 dots also possible)5!10 dots+Cursor lineq 6 Kinds of character fontq Single power supply ...................5V ±10% (Logic)q Low LCD driving voltage ............V DD —V 5≥.0Vq Package .....................................SED1278F: QFP5-80pin (plastic)SED1278D: Die form (Al pad)s BLOCK DIAGRAMROM 240 charactersRAM 8 characterss PIN CONFIGURATIONs PIN DESCRIPTIONs ABSOLUTE MAXIMUM RATINGSRatingSupply voltage (1)Supply voltage (2)Input voltage Output voltage Power dissipationOperating temperature Storage temperatureSoldering temperature and timeSymbol V DD V 1 to V 5V I V O P D T opr T stg T solUnit V V V V mW °C °C —Value –0.3 to 7.0–0.3 to V DD +0.3–0.3 to V DD +0.3–0.3 to V DD +0.3300–20 to 75–65 to 150260°C•10s (at lead)(V SS = 0V, Ta = 25°C)Note: The following condition must always hold true: V DD ≥V 1≥V 2≥V 3≥V 4≥V 5s ELECTRICAL CHARACTERISTICS q DC Characteristicsr Write CycleV IH1V IL1V IH2V IL2V OH1V OL1V OH2V OL2R COM R SEG I IL —I P I OPf EXTCL Duty tr EXTCL tf EXTCL f OSC f OSC V LCDSymbol I OH = –0.205mA I OL = 1.6mA I OH = –0.04mA I OL = 0.04mA V COM —V n =0.5V V SEG —V n =0.5V V I = 0 to V DD V DD = 5VR f = 91K Ω±2%Ceramic filter V DD —V 5Condition2.0V SS V DD —1.0V SS 2.4—0.9V DD ————50—12545——1902453.0Min.DB0~DB7RS, R/W, E OSC1DB0~DB7V DD COM1~16SEG1~40ApplicablePin ————————22.5—12525050——270250—0.5Typ.V DD 0.8V DD 1.0—0.4—0.1V DD 10101250350550.20.2350255V DD0.8Max.V V V V V V V V k Ωk ΩµA µA mAkHz %µS µS kHz kHz VUnit "H" level input voltage (1)"L" level input voltage (1)"H" level input voltage (2)"L" level input voltage (2)"H" level output voltage (1)"L" level output voltage (1)"H" level output voltage (2)"L" level output voltage (2)Driver-on resistor (COM)Driver-on resistor (SEG)I/O leakage current Pull-up MOS current Supply currentExternal clock operation External clock operating frequency External clock duty External clock rise time External clock fall time Internal clock operation (Rf oscillation)Oscillation frequency Internal clock operation (Ceramic filter oscillation)Oscillation frequency LCD driving voltageCharacteristicRf oscillation, from external clockV DD = 5V, fosc = f CP = 270kHz(V DD = 5.0V ±10%, V SS = 0V, Ta = –20 to 75°C)XSCL LP DO q AC Characteristics r Read Cycle(V = 5.0V ±10%, V = 0V, Ta = –20 to 75°C)t cycE t WEH t rE , t fE t AS t AH t DS t DHSymbol 500220—40106010Min.———————Typ.——25————Max.ns ns ns ns ns ns nsUnit ConditionEnable cycle timeEnable "H" level pulse width Enable rise/fall time RS, R/W setup time RS, R/W address hold time Data setup time Write data hold timeCharacteristic(V DD =5.0V ±10%, V SS =0V, Ta=–20 to 75°C)q Timing Charts DISPLAY COMMANDT Don't cares PACKAGE DIMENSIONSs LCD PANEL INTERFACE EXAMPLE (2 lines×20 characters)SED1278F/D is usually connected to 8-bit MPU via I/O ports.s SED1278Dq PAD LAYOUTq PAD COORDINATIONs SED1278D OA CHARACTER FONTs SED1278F OB/D OB CHARACTER FONTs SED1278F OC/D OC CHARACTER FONTs SED1278F OD/D OE CHARACTER FONTs SED1278F OG/D OG CHARACTER FONT11s SED1278F OH/D OH CHARACTER FONTT Character codes (0OH-0FH) of SED1278F are assigned to the area of character generator RAM (CG RAM).The CG ROM of the SED1278F is masked; if you wish to have your own CG ROM, consult Seiko EpsonMarketing Department for conversion of the masked ROM.1213ELECTRONIC DEVICES MARKETING DIVISIONElectronic Device Marketing Department IC Marketing & Engineering Group421-8, Hino, Hino-shi, Tokyo 191-8501, JAPANPhone: +81-(0)42-587-5816Fax: +81-(0)42-587-5624ED International Marketing Department I (Europe & U.S.A.)421-8, Hino, Hino-shi, Tokyo 191-8501, JAPANPhone: +81-(0)42-587-5812Fax: +81-(0)42-587-5564ED International Marketing Department II (Asia)421-8, Hino, Hino-shi, Tokyo 191-8501, JAPANPhone: +81-(0)42-587-5814Fax: +81-(0)42-587-5110NOTICENo part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and,further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency.All product names mentioned herein are trademarks and/or registered trademarks of their respective companies.©Seiko Epson Corporation 1998 All rights reserved.http://www.epson.co.jpElectric Device Information of EPSON WWW server。