Q67000-A8338中文资料

The window discriminator compares an input voltage to a defined voltage window. The digital outputs show whether the input voltage is below, within or above this window.The TCA 965B window discriminator is especially suitable as a tracking or compensating controller with a dead band in control engineering and for the selection of DC voltages within a certain tolerance of the required setpoint value in measurement engineering. When it is used as a Schmitt trigger, switching frequencies up to a typical value of 50kHz are possible.
Type Ordering Code Package s TCA 965 B
Q67000-A8338
P-DIP-14-1
s Not for new design
Window Discriminator Preliminary Bipolar IC
P-DIP-14-1
Features
q
Two window settings
–direct setting of lower and upper edge voltage (window edges)
–indirect setting by window center voltage and half window width q Adjustable hysteresis
q Digital outputs with open collectors for currents up to 50mA
q
Adjustable reference voltage V Stab
TCA 965 B
Functional Description
Amplifier Amp 3 increases the voltage of the reference source R to V Stab = 2x V REF . The amplification factor can be altered by external wiring. With direct setting of the window,the input voltage appears on amplifier Amp 1(V 8), the upper edge voltage on comparator K2(V 6) and the lower edge voltage on comparator K1(V 7).
With indirect setting of the window, the input voltage appears on inputs
V 6 and V 7, while the center voltage is connected to amplifier A1(V 8).
The voltage applied to the input (V 9) of amplifier Amp 2 is subtracted symmetrically from the output voltage of amplifier Amp 1 and added. The comparators switch with hysteresis. The logic gates have open-collector outputs.
If the inhibit input A or B is connected to ground, output A or B will always be high.
Block Diagram Outputs A, B, C, D are open-collector
IEB00091
20k Ω
20k Ω
_
+Amp 3
R
_+
_+
+
_
+_
K1
K2
Amp 1
Amp 2
1
1
1
1
V = 1
V = 1
11
1
5
S
+V V REF
210
4
13
312
14
V Stab
A Inhibit A C D Inhibit
B B
7
8
96
V 7
V 8
V 9V 6
_
<
Pin Configuration
(top view)
Pin Definitions and Functions
Pin Symbol Pin Function in
Direct Setting Indirect Setting
of Window
1 2 3 4 5GND
A
D
Inhibit A
V
REF
GND
Logic output A
Logic output D = A @ B (AND)
Connected to GND: logic output A = HIGH
Internal V REF = 3V
6 7 8 9V
6
V
7
V
8
V
9
Upper edge voltage
Lower edge voltage
Input voltage
GND
Input voltage V6/7
Input voltage V6/7
Center voltage
Half window width
10 11 12 13 14V
Stab
+V S
Inhibit B
C
B
Internal V Stab = 6V
Supply voltage
Connected to GND: logic output B = HIGH
Logic output C = A @ B (NAND)
Logic output B
TCA 965 B
IEP00292
C
D
A
GND
78
69
510
411
312
213
114B
7
V
Inhibit A
6
V
REF
V
Inhibit B
V9
V S
V Stab
V8
+
Absolute Maximum Ratings
Maximum ratings for ambient temperature T A = –25 to 85°C
Parameter Symbol Limit Values Unit
min.max.
Supply voltage (pin 11)
Difference in input voltage between pins 6, 7, 8 Input voltage (pins 6, 7, 8, 9)V
S
V
I
V
I
–
–
–
30
15
30
V
V
V
Output current (pins 2, 3, 13, 14)I Q–50mA Output voltage (pins 2, 3, 13, 14)
independent of V S Voltage on V REF (pin 5)V
Q
V
R
–
–
–
30
8
V
V
Output current of stabilized voltage (pin 10)I10–10mA Inhibit input voltage (pins 4, 12)V IH–7V
Junction temperature Storage temperature T
j
T
stg
–55
150
125
°C
°C
Thermal resistance system - air P-DIP-14-1R th SA–80K/W Operating Range
Supply voltage V S 4.530V Ambient temperature T A–2585°C
Characteristics
V
S
= 10V;T A= 25°C
Parameter Symbol Limit Values Unit Test
Condition Test Circuit
min.typ.max.
Current consumption Input current
(pins 6, 7, 8)
Input current, pin 9I
S
I
I
–I I
–
–
–
5
20
400
7
50
3000
mA
nA
nA
V
2
,V13 =V QH1
1
1
Input offset voltage in
direct setting of window Input offset voltage in indirect setting of window Input-voltage range on pins 6, 7, 8
Input-voltage range on pin 9
Differential input voltage Reference voltage Stabilized voltage on
pin 10
TC of reference voltage Sensitivity of reference voltage to supply-voltage variation V
IO
V
IO
V
I
V
I
V
6
–(V8–V9)
(V8+V9)–V7
V
5
V
10
αV5
∆V5/∆V S
–20
–50
1.5
50
2.8
5.5
3
6
0.4
2
20
50
V
S
–1
V
S
/2
13
13
3.2
6.5
mV
mV
V
mV
V
V
V
V
mV/K
mV/V
∆V I<13V
I
REF
= 0
V
S
>7.9V
1
2
1
2
Output reverse current I QH––10µA––
Output saturation voltage Hysteresis of window edges
Inhibit threshold V
QL
V
U
–V L
V
4, 12
18
1
100
500
22
200
800
35
1.8
mV
mV
mV
V
I
Q
= 10mA
I
Q
= 50mA
1
Inhibit current I4, 12––100–µA––
Switching frequency f dir
f
ind –
–
20
50
–
–
kHz
kHz
–
–
1
2
Test Circuit 1
Direct Setting of Window
IES00086
V 5V 10V QL14V QL13V QL3V QL2
V 6
V 7
V 8
ΙQH14
QH13ΙQH3ΙQH2ΙΙ6
6
23
13
1410
5
7
8Ι7
ΙΙ4
V V 12
Ι9
91412
R L R L R L R L
ΙS1111
V S
TCA 965B
ΙΙ8
Ι=
=
=
=
=
Test Circuit 2
Indirect Setting of Window by Center Voltage and Half Window Width IES00087
V6/7V8V9
6
8
9
1412
7
V5V10V QL14V QL13V QL3V QL2
ΙQH14
QH13
Ι
QH3
Ι
QH2
Ι2
3
13
14
10
5
4
V V12
R L R L R L R L
ΙS11
11
V S
TCA 965B
===
==
Schematic Circuit Diagrams
Inhibit Inputs 4,12
Inputs 6, 7, 8Outputs 2, 3, 13, 14
IES00088
Outputs Input 9
Outputs A, B
GND High Not permitted > 7 V Normal function open Low
> 1.8 V
100 1 k V S
V 4,12
V 6,7,8
1 k V 9
V REF
Q
R
V Stab
V REF V Stab
,V 4,12
Ω
Ω
Ω
Application Circuit 1
Direct Setting of Lower and Upper Edge Voltages
V 6 –V 9 = Upper edge voltage V 7 +V 9 = Lower edge voltage V 8 =Input voltage
TCA 965 B
2
3
13
14
A
D
C
B
C 1
1011
6781
R R 4
7
R R 3
IES00294
1
4
12
C 3
R 6
Ι
V V
6
7
V
8
V
S
V 5
R R 2
2
C 9
V 9To increase the switching frequency, pin 9 may be grounded via R 7(9V approx. 30...40 mV).
Definition of the Offset Voltage V IO IES00296
A
V L V U
V10
V7
t
V10
V L V U
+
2
---------------------V7
–
=
Application Circuit 1
Direct Setting of Lower and Upper Edge Voltages
Upper Edge V 68
V 7
V Edge
Lower t
L
U
t
t
A B C
D
D
C B
A A
B C
D D
C
B A
A B C
D
10
Pin 4 on GND Pin 12 on GND Inhibit A
Inhibit B
110010
11.8 V < Pin 12 < 7 V
IES00295
10
010
11.8 V < Pin 4 < 7 V
t
U
L
t
t
L
U
t
Application Circuit 2
Indirect Setting of Window by Center Voltage and Half-Window Width V
V 6 = V 7 =Input voltage V 8 =Center voltage V 9 =Half window width
TCA 965 B
2
3
13
14
A
D
C
B
C 1
1011
89671R R 3
R 5
6
R 4
R R 2IES00297
1
412
2
C C 3
R 7
Ι
V V
8
9
V
6
V
7
V
S
V
Definition of the Offset Voltage V IO IES00299
B
V L V U
V10
V8
t V9
-
V10=V L-V U
V8-V9 2
-()
V10
V L V U
+
2
---------------------V8V9)
–
(–
=
Application Circuit 2
Indirect Setting of Window by Center Voltage and Half-Window Width V
Upper Edge V 68V 7
V Edge
Lower t
L
U
t
t
A
B C
D
D
C B
A A B
C D
D
C
B A
A
B C
D
10
Inhibit A
Inhibit B
110010
1IED00298
10
010
1t
U
L
t
t
L
U t
Pin 4 on GND 1.8 V < Pin
4 < 7 V
Pin 12 on GND 1.8 V < Pin
12 < 7 V
Application Circuit 3
Symmetrically Enlarged Edge Hysteresis in Direct Setting of Window Calculation of Hysteresis V H
IES00089
V S
V Ι
R 1
R 3
R L
R L R L R 4
6
8
7
10
11
13
142
39
1
TCA 965B
V 3
V 8
V H
R 2
V H
V 7
V 6
P R 5
=V H
V 10R 5
R 4R 5
+-------------------=V 10
R 4R 5+-------------------V 10R 1R 2R 3
++--------------------------------10mA ≤+
Application Circuit 4
Symmetrically Enlarged Edge Hysteresis in Indirect Setting of Window Calculation of Hysteresis V H
V H =V 9/2 –V 9/1IES00090
V S
V Ι
R 1
R 2
R L
R L R L R 3
R 5
R 4
8
67
10
11
2
1413
3
9
1
TCA 965B
V 3
V 8
V V 9/19/2
6/7
V V H =9/1
V V 9/2-V 9/1
V 10R 4R 5
||R 3R 4R 5||+-------------------------------=V 9/2
V 10R 4
R 3R 4
+-------------------=
P-DIP-14-1
(Plastic Dual In-line Package)
G P D 05005
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”.
Dimensions in mm。