Design of a minimum power, low-voltage supply fully-differential transconductance amplifier

focused on multi-stage ampli ers. We developed two designs: one uses a three-stages topology, while the other is a folded-cascode with a second stage. In the three stages approach we maintained the topology as simple as possible. Cascodes are not needed, which makes it more robust to supply changes. On the other hand compensation appears more problematic then the two stage design. For our rst design we used an expression for the calculation of the dynamic range which is not accurate for Miller-compensated multi-stage ampli ers. In this report we derive a more accurate expression for our multistage ampli ers. We still present in Appendix A our three stages ampli er which is a low power solution, designed to meet the speci cations according to the wrong expression of the dynamic range. Modi cations on the two stages approach seemed more feasible based on the time available after deriving the accurate formula for the dynamic range. The two stages folded cascode, in fact, has been redesigned and optimized for low power in order to meet also the dynamic range speci cation according to the new expression.
Assuming the noise power density is given by the expression KT Pnoise = (1 + nf ); (1) C the dynamic range speci cation of 80 dB corresponds to:
vi2
s
2.1 Dynamic Range
1 Introduction
Pipelined analog to Digital (A/D) converters usually require transconductance ampli ers to provide an adding functionality and a gain stageห้องสมุดไป่ตู้ In this project we designed a fully-di erential ampli er to be used as a rst stage of a pipelined 13-Bit A/D converter according to the following speci cations: Supply 3:3V 10% Open-loop gain 10000 Settling time 100ns Accuracy 0.01% Power minimum Dynamic Range 80dB
8 K T (1 + ns )
vi2 Cs
Cs
108;
(2) (3)
which translates into: 8:28 V2pF;
capacitors are chosen as small as possible to minimize the power. Smaller compensation capacitors require smaller currents for a given slew rate and smaller transconductances which means again smaller currents for a given bandwidth. If instead the correct formula is used, the compensation capacitor cannot be made small. Cc has to be chosen of at least the same order of magnitude of Cs implying larger power dissipation. An optimal ratio Cc=Cs with respect to power consumption has been found in the case of the two stage folded cascode and the details of the design are presented in Section 3.
where a noise factor nf = 1:5 has been assumed. A small single-ended input range vi requires a large capacitor Cs The speci cation on the settling time tST determines the unity gain bandwidth !u . In our designs the slew rate and therefore a large current to drive it. (SR) is given by the tail current in the rst stage I0 and by the capacitor determining the bandwidth: vi = 0:1 ! Cs 828pF the compensation capacitor Cc for the two stages vi = 1 ! Cs 8:28pF topology, Due to the square dependence on vi , to minimize power the outer-most compensation capacitor Cc2 in the we minimize Cs making vi as large as possible. This is three stages topology. done avoiding cascodes on the last stage and using small The di erential output slew rate is Vdsat. The noise factor nf should also be minimized for low I SR = 2 0 : (6) power. Small Vdsat in the input transistors and large Vdsat Cc2 in their loads are used to accomplish the task. We also calculations presented in Appendix C designed a high gain in the rst stage to minimize any According to the time is: the total settling additional noise from the later stages. The expression given above for the noise power density t = 2 ( 2vi ? 1 )] ? 1 ln( 2fvi ) fFB !u Vgs ? Vt is a good approximation in the case, for example, of a ST !u Vgs ? Vt fFB (7) single stage ampli er, where the bandwidth is given by the load capacitor Cs . In a Miller compensated multi- where is the speci ed accuracy; fFB = 1=3 is the feedstage approach, the bandwidth is instead given by the back factor. Finally Vgs ? Vt is the maximum input that compensation capacitor Cc . We show in Appendix B the does not cause slewing. This quantity can be chosen derivations of a more accurate expression to estimate the to trade slewing time with linear settling time. We observed that in our design, for low power a minimum value noise power for that case: of Vgs ? Vt is to be chosen to minimize the noise factor nf KT 2nf KT (4) and to achieve high transconductance in the rst stage Pnoise = 2Cs + 3fFB Cc ; with smaller current. gain bandwidth is chosen where fFB is the feedback factor that we calculate in- to The unitysettling time speci cation. as low as needed meet the In our design we cluding also the input capacitance Cin of the ampli er: chose the following parameters: