Lecture_PLL11

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W. Rhee, Institute of Microelectronics, Tsinghua University
PLL-Based CDR: Design Trade-Off
• Main goal is to extract clock information from noisy data and do retiming. (clock recovery + data retiming) • Ultimate goal is to achieve low BER.
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W. Rhee, Institute of Microelectronics, Tsinghua University
SerDes System Overview
Optical Link Example
• Transmitter - Parallel-to-serial (low data rate to high data rate) - Laser + Modulator + MUX + TXPLL • Receiver - Serial-to-parallel (high data rate to low data rate) - Photodiode + TIA + LA + DMUX + RXPLL (CDR)
ΔTcc ,rms ≈ lim
1 (T2 − T1 )2 + (T3 − T2 )2 + ⋅ ⋅ ⋅ + (TN − TN −1 )2 N →∞ N
• Period jitter - For PLL, period jitter = absolute jitter.
ΔTp ,rms = lim
*
1 (T − T1 )2 + (T − T2 )2 + ⋅ ⋅ ⋅ + (T − TN −1 )2 N →∞ N
W. Rhee, Institute of Microelectronics, Tsinghua University
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V. Applications 2. Clock and Data Recovery Systems B. System Design
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W. Rhee, Institute of Microelectronics, Tsinghua University
PLL DESIGN AND CLOCK/FREQUENCY GENERATION (Lecture 11)
Woogeun Rhee Institute of Microelectronics Tsinghua University
Announcement: Invited Lecture/Seminar
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W. Rhee, Institute of Microelectronics, Tsinghua University
Cock Recovery: PLL-Based (Active/Analog)
D Q DFF DAT’
DAT
PD
LPF
VCO
CLK’
• Highly integrated low-cost solution • Tunable frequency with high-Q filtering • Requires frequency acquisition.
Note: Periodic jitter (PJ) is often considered DJ by sinusoidal modulation, which is different from period jitter.
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W. Rhee, Institute of Microelectronics, Tsinghua University
Jitter
• Absolute jitter (long-term jitter) - Phase error w.r.t. ideal reference
ΔTabs ,rms = lim
1 ΔT12 + ΔT22 + ⋅ ⋅ ⋅ + ΔTN2 N →∞ N
• Cycle-to-cycle jitter (short-term jitter) - No need for reference
• LPF and HPF on random data cause intersymbol interference (ISI). • Various nonidealities (PCB trace, impedance mismatch, ..) can cause ISI. • Noise (amplitude/phase) further aggravates data waveform. • Eye diagram often used to observe ISI effect for long sequence data.
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W. Rhee, Institute of Microelectronics, Tsinghua University
Clock Extraction
RZ Data NRZ Data
• NRZ is more bandwidth efficient but contains no clock information. • To prevent dc wandering, max run length is limited (e.g. 8B/10B code).
a
b
m
)dfm [rms deg]
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W. Rhee, Institute of Microelectronics, Tsinghua University
Deterministic Jitter by Modulation
Time Domain
RJpk-pk (14*σ) Pspur DJ DJ dominant (modulation) RJ dominant (noise)
G ain P eaking (for second-order type 2)
= 10 log
8ζ 8ζ
4
4
− 4ζ
2
− 1+
8ζ
2
+1
dB
• Jitter transfer - Ratio of CDR output jitter to input sinusoidal jitter. • Jitter peaking causes jitter accumulation. Æ Serious problem for data repeaters. • Always exists in second-order type 2 PLL. • For OC-192, jitter peaking < 0.1dB within 120kHz frequency band. Æ Requires ζ > 4.4 for type 2 PLL.
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W. Rhee, Institute of Microelectronics, Tsinghua University
Term Project/Final Exam
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W. Rhee, Institute of Microelectronics, Tsinghua University
V. Applications 2. Clock and Data Recovery Systems A. Overview
Jitter Inside
• Total jitter (TJ) - Random jitter (RJ) + deterministic jitter (DJ) • Random jitter (RJ) - Non-systematic jitter - Gaussian distribution • Deterministic jitter (DJ) - Systematic jitter - Coupling, ISI, duty cycle distortion
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W. Rhee, Institute of Microelectronics, Tsinghua University
Jitter Transfer and Jitter Peaking
Repeater PLL
H(s)
0dB
Repeater PLL
Repeater PLL
Jitter peaking
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W. Rhee, Institute of Microelectronics, Tsinghua University
Pattern-Dependent Jitter
• Pattern-dependent jitter can occur with non-periodic input.
Ref: Wolaver’s book
Frequency Domain
fo
DJ pk − pk = 0.01 UI
→ →
Δfpk
fm
Pspur
=
0.01× 2π 2 2 ⎛ Δfpk ⎞ = 10log ⎜ ⎟ ≈ -36dBc f 2 ⎝ m ⎠
• Total jitter = Random jitter (RJ) + Deterministic Jitter (DJ). • Depending on design, total jitter can be dominated by DJ.
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W. Rhee, Institute of Microelectronics, Tsinghua University
Data Retiming with Recovered Clock
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