FPGA可编程逻辑器件芯片XCVU13P-2FHGB2104CE中文规格书
FPGA可编程逻辑器件芯片XCVU11P-2FLGB2104E中文规格书
FPGA (U1) Pin Schematic Net Name I/O Standard C27RLD3_36B_DQ0SSTL12D29RLD3_36B_DQ1SSTL12A29RLD3_36B_DQ2SSTL12B27RLD3_36B_DQ3SSTL12B26RLD3_36B_DQ4SSTL12A28RLD3_36B_DQ5SSTL12C28RLD3_36B_DQ6SSTL12C29RLD3_36B_DQ7SSTL12B28RLD3_36B_DQ8SSTL12K29RLD3_36B_DQ9SSTL12J26RLD3_36B_DQ10SSTL12K28RLD3_36B_DQ11SSTL12N27RLD3_36B_DQ12SSTL12L28RLD3_36B_DQ13SSTL12K26RLD3_36B_DQ14SSTL12GTH Quad 230MGTHTXP0_230 L7 HMC_L0TX_10_P E20 L0RXP_4HMCU160 MGTHTXN0_230 L6 HMC_L0TX_10_N E19L0RXN_4MGTHRXP0_230 L2 HMC_L0RX_10_C_P D25 L0TXP_4MGTHRXN0_230 L1 HMC_L0RX_10_C_N D24 L0TXN_4MGTHTXP1_230 K9 HMC_L0TX_14_P D21 L0RXP_5MGTHTXN1_230 K8 HMC_L0TX_14_N D20L0RXN_5MGTHRXP1_230 K4 HMC_L0RX_14_C_P B27 L0TXP_5MGTHRXN1_230 K3 HMC_L0RX_14_C_N B26 L0TXN_5MGTHTXP2_230 J7 HMC_L0TX_0_P C22L0RXP_6MGTHTXN2_230 J6 HMC_L0TX_0_N C21L0RXN_6MGTHRXP2_230 J2 HMC_L0RX_0_C_P A20L0TXP_6MGTHRXN2_230 J1 HMC_L0RX_0_C_N A19L0TXN_6MGTHTXP3_230 H9 HMC_L0TX_1_P B23L0RXP_7MGTHTXN3_230 H8 HMC_L0TX_1_N B22L0RXN_7MGTHRXP3_230 H4 HMC_L0RX_1_C_P B19L0TXP_7MGTHRXN3_230 H3 HMC_L0RX_1_C_N B18L0TXN_7MGTREFCLK0P_230R11 HMC_SI5328_OUT2_BUF1_C_P35CKOUT2_P SI5328U57 MGTREFCLK0N_230R10 HMC_SI5328_OUT2_BUF1_C_N34CKOUT2_N MGTREFCLK1P_230P13NA NA NANA MGTREFCLK1N_230P12NA NA NATable 1-8:HMC Memory U160 L0 I/F to FPGA U1 GTH Quads 229-232 (Cont’d)MGTBank FPGA (U1) Pin Name FPGA(U1)PinSchematic Net Name(1)ConnectedPinNumberConnectedPin NameConnectedDeviceThe HMC component U160 control bank connections are listed in Table 1-10.For more details about HMC, see the Micron MT43A4G40200NFA data sheet [Ref 21].Micro-SD Card Interface[Figure 1-2, callout 8]The VCU110 board includes a secure digital input/output (SDIO) interface to provide user access to general purpose nonvolatile micro-SD memory cards for configuration. The micro-SD card slot is designed to support 50MHz high speed micro-SD cards. The SDIO signals are connected to U111 XC7Z010 Zynq SoC system controller bank 500, which has its V CCO set to SYS_1V8 1.8V. A MAX13035E level-shifter (U154) is used between the XC7Z010 System Controller (U111) and the micro-SD card connector (J83).Table 1-10:HMC Memory U160 Control I/F Connections HMC U160 Pin NumberHMC U160 PinNameSchematic Net Name (1)I/O StandardConnected Pin NumberConnected DeviceU30P_RST_N HMC_P_RST_B LVCMOS15AW28FPGA U1N1REFCLK_BOOT_0HMC_REFCLK_BOOT_0LVCMOS15BA26U29REFCLK_BOOT_1HMC_REFCLK_BOOT_1LVCMOS15BB26V6REFCLKSEL HMC_REFCLK_SEL LVCMOS15AV30U5FERR_N HMC_FERR_B LVCMOS15AW30P29L1RXPS HMC_L1RXPS LVCMOS15BB27V24L1TXPS HMC_L1TXPS LVCMOS15AY29U28L0RXPS HMC_L0RXPS LVCMOS15AY30N24L0TXPS HMC_L0TXPSLVCMOS15AW27R30REFCLKN HMC_SI5328_OUT1_C_N (1)NA 28SI5328U57T30REFCLKP HMC_SI5328_OUT1_C_P (1)NA 29R28SCL IIC_SCL_HMC_LS (2)NA 16IIC MUX U28T24SDA IIC_SDA_HMC_LS (2)NA 15T5TCK HMC_TCK NA 5JTAG connector J120P7TDI HMC_TDI NA 3T1TDO HMC_TDO NA 2R5TMS HMC_TMS NA 4R7TRST_NHMC_TRST_BNA6Notes:1.Series capacitor coupled.2.IIC is level shifted through U159.USB JTAG Interface[Figure 1-2, callout 9]JTAG configuration is provided through a Digilent onboard USB-to-JTAG configuration logic module (U115) where a host computer accesses the VCU110 board JTAG chain through a type-A (host side) to micro-B (VCU110 board side) USB cable.A 2 mm JTAG header (J3) is also provided in parallel for access by Xilinx download cables such as the Platform Cable USB II and the Parallel Cable IV. JTAG initiated configuration takes priority over the configuration method selected through the FPGA mode pins M[2:0], wired to SW16 positions [1:3].The JTAG chain of the VCU110 board is illustrated in Figure 1-7.For more details about the Digilent USB JTAG module, see [Ref 24].Figure 1-7:JTAG Chain Block Diagram。
FPGA可编程逻辑器件芯片XCVU13P-1FHGC2104I中文规格书
FLGA2577
XCVU9P page 330
XCVU11P page 332
XCVU13P page 334
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FSGA2577
XCVU13P page 334
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FSGA2577
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FSVH2892
VCCAUX_HDIO. These pins can be connected to a
common VCCAUX_IO supply.
VCCIO_HBM_d
N/A
HBM component I/O power supply (VDDQ)
VCC_HBM_[HBM bank number]
XCVU35P page 340
XCVU37P page 342
XCVU45P page 340
XCVU47P page 342
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FSVA3824
XCVU19P page 344
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FSVB3824
XCVU19P page 346
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UltraScale Device Packaging and Pinouts UG575 (v1.14) March 18, 2020
This pin is present on Kintex UltraScale+ and Virtex UltraScale+ devices.
Power/Ground Pins
For more information on voltage specifications see the UltraScale and UltraScale+ device data sheets [Ref 3].
FPGA可编程逻辑器件芯片XCVU11P-3FLGB2104E中文规格书
Alveo 产品详细介绍表 1：Alveo U200/U250 加速器卡产品详细介绍规格U200U250主动散热版被动散热版主动散热版被动散热版产品 SKU A-U200-A64G-PQ-GA-U200-P64G-PQ-GA-U250-A64G-PQ-GA-U250-P64G-PQ-G散热解决方案主动被动主动被动重量1122g1066g1122g1066g外形尺寸全高、全长、双宽度全高、¾ 长、双宽度全高、全长、双宽度全高、¾ 长、双宽度卡总耗电量1225 W 225 W 网络接口2x QSFP282x QSFP28PCIe 接口Gen3 x16Gen3 x16查找表 (LUT)1,182K 1,728K 寄存器2,364K 3,456K DSP slice 6,84012,288UltraRAM 9601,280DDR 总容量64 GB 64 GB DDR 最大数据率2400 MT/s 2400 MT/s DDR 总带宽77 GB/s77 GB/s 注释：1.225W PCIe CEM 卡通过标准连接器 12V 电源获取 65W ，通过 AUX 连接器 12V 电源获取另外 150W 。
此卡上不使用标准连接器提供的 3.3 V 电源。
CEM 卡需将 150W PCIe AUX 电源线缆连接到本卡。
Alveo U200 和 U250 数据中心加速器卡数据手册条款中英文版本如有歧义，概以英文版本为准。
下图显示了 Alveo 加速器卡内的组件。
FPGA 资源信息赛灵思 Alveo U200 和 U250 加速器卡属于定制型 UltraScale+ FPGA，能够在 Alveo 架构上以最佳状态运行，并且只能在该架构上运行。
Alveo U200 卡采用 XCU200 FPGA，而 Alveo U250 卡则使用 XCU250 FPGA，两者均使用赛灵思堆叠硅片互联 (SSI) 技术来实现突破性的 FPGA 容量、带宽和功耗效率。
FPGA可编程逻辑器件芯片XCVU13P-1FHGA2104I中文规格书
Chapter1 Packaging OverviewIntroduction to the UltraScale ArchitectureThe Xilinx® UltraScale™ architecture is the first ASIC-class architecture to enablemulti-hundred gigabit-per-second levels of system performance with smart processing,while efficiently routing and processing data on-chip. UltraScale architecture-based devices address a vast spectrum of high-bandwidth, high-utilization system requirements by using industry-leading technical innovations, including next-generation routing, ASIC-likeclocking, 3D-on-3D ICs, multiprocessor SoC (MPSoC) technologies, and new powerreduction features. The devices share many building blocks, providing scalability acrossprocess nodes and product families to leverage system-level investment across platforms.Virtex® UltraScale+™ devices provide the highest performance and integration capabilities in a FinFET node, including both the highest serial I/O and signal processing bandwidth, as well as the highest on-chip memory density. As the industry's most capable FPGA family, the Virtex UltraScale+ devices are ideal for applications including 1+Tb/s networking and data center and fully integrated radar/early-warning systems.Virtex UltraScale devices provide the greatest performance and integration at 20nm,including serial I/O bandwidth and logic capacity. As the industry's only high-end FPGA at the 20nm process node, this family is ideal for applications including 400G networking, large scale ASIC prototyping, and emulation.Kintex® UltraScale+ devices provide the best price/performance/watt balance in a FinFET node, delivering the most cost-effective solution for high-end capabilities, includingtransceiver and memory interface line rates as well as 100G connectivity cores. Our newest mid-range family is ideal for both packet processing and DSP-intensive functions and is well suited for applications including wireless MIMO technology, Nx100G networking, and data center.Kintex UltraScale devices provide the best price/performance/watt at 20nm and include the highest signal processing bandwidth in a mid-range device, next-generationtransceivers, and low-cost packaging for an optimum blend of capability andcost-effectiveness. The family is ideal for packet processing in 100G networking and data centers applications as well as DSP-intensive processing needed in next-generation medical imaging, 8k4k video, and heterogeneous wireless infrastructure.Device/Package CombinationsTable1-1 shows the size and BGA pitch of the UltraScale and UltraScale+ device packages. The devices with stacked-silicon interconnect (SSI) technology are labeled.Gigabit Transceiver Channels by Device/PackageTable 1-2 lists the quantity of gigabit transceiver channels for the UltraScale andUltraScale+ devices. In all devices, a gigabit transceiver channel is one set of MGTRXP, MGTRXN, MGTTXP, and MGTTXN pins. For transceiver data rate limitations on specific device/package combinations, see the specific UltraScale and UltraScale+ device data sheets [Ref 4].Table 1-2:Serial Transceiver Channels (GTH/GTY) by Device/PackageDevicePackageGTH ChannelsGTY ChannelsKintex UltraScale DevicesXCKU035FBVA676160XCKU040160XCKU035SFVA78480XCKU04080XCKU035FBVA900160XCKU040160XCKU025FFVA1156120XCKU035160XCKU040200XCKU060280XCKU095208XCKU060FFVA1517320XCKU085FLVA1517480XCKU115480XCKU095FFVC15172020XCKU115FLVD1517640XCKU095FFVB17603216Kintex UltraScale+ DevicesXCKU3P FFVA676480208480192XCKU5P 480208480192XCKU3P FFVB676720208720192XCKU5P 720208720192XCKU3P SFVB784960208960192XCKU5P 960208960192XCKU3P FFVD90096020*******XCKU5P 960208960192XCKU11P 960312960288XCKU9P FFVE900960208960192XCKU13P 960208960192XCKU11P FFVA1156480416480384XCKU15P 480468480432XCKU11P FFVE1517960416960384XCKU15P 960416960384XCKU15P FFVA1760960416960384XCKU15P FFVE1760960572960528XQKU5P FFRB676720208720192XQKU5P SFRB784960208960192XQKU15P FFRA1156480468480432XQKU15PFFRE15179641696384Virtex UltraScale+ DevicesXCVU3P FFVC15170052000480XCVU11P FLGF19240062400576XCVU31P FSVH19240020800192XCVU5P FLVA21040083200768XCVU7P 0083200768XCVU9P FLGA21040083200768XCVU13P FHGA21040083200768XCVU5P FLVB21040070200648XCVU7P702648Table 1-4:Available I/O Pins by Device/Package (Cont’d)DevicePackageTotal User I/O Differential I/OHD (1)HR (1)HP (1)HDHRHP。
FPGA可编程逻辑器件芯片XCVU11P-2FLGC2104E中文规格书
The connections between the dual Quad SPI components U182, U183 and XCVU190 banks 0 and 65 are listed in Table 1-7.Hybrid Memory Cube[Figure 1-2, callout 7]The HMC component memory system is comprised of one 16-lane 2GB device (Micron MT43A4G40200NFA) located at U160. This memory system is connected to the XCVU190 MGTH banks 225-232 (8 MGTH Quads).Table 1-7:Dual-QSPI Memory U182, U183 I/F to FPGA U1 Banks 0 and 65FPGA (U1)PinSchematic NetNameI/O StandardQSPI MemoryPin NumberPin NameReference DesignatorAM14QSPI0_IO0(1)D3DQ0U182AK14QSPI0_IO1(1)D2DQ1U182AF16QSPI0_IO2(1)C4DQ2_W_B U182AH14QSPI0_IO3(1)D4DQ3_HOLD_BU182AF14QSPI0_CS_B (1)C2S_B U182AB16FPGA_CCLK (1)B2C U182BE19QSPI1_IO0LVCMOS18D3DQ0U183BF19QSPI1_IO1LVCMOS18D2DQ1U183BD18QSPI1_IO2LVCMOS18C4DQ2_W_B U183BE18QSPI1_IO3LVCMOS18D4DQ3_HOLD_BU183AP20QSPI1_CS_B LVCMOS18C2S_B U183AB16FPGA_CCLK(1)B2CU183Notes:1.Bank 0 V CCO = 1.8V; bank 0 I/O standards are not specified.The connections between the HMC component U160 bank L0 and XCVU190 GTH Quads 229-232 are listed in Table1-8. The nets with _C_P or _C_N in their net names are series capacitor coupled.Table 1-8:HMC Memory U160 L0 I/F to FPGA U1 GTH Quads 229-232MGTBank FPGA (U1) Pin Name FPGA(U1)PinSchematic Net Name(1)ConnectedPinNumberConnectedPin NameConnectedDeviceGTH Quad 229MGTHTXP0_229 R7HMC_L0TX_12_P G18L0RXP_0HMCU160 MGTHTXN0_229 R6HMC_L0TX_12_NG17L0RXN_0MGTHRXP0_229 R2HMC_L0RX_12_C_PE24L0TXP_0MGTHRXN0_229 R1HMC_L0RX_12_C_N E23L0TXN_0MGTHTXP1_229 P9HMC_L0TX_9_P F19L0RXP_1MGTHTXN1_229 P8HMC_L0TX_9_N F18L0RXN_1MGTHRXP1_229 P4HMC_L0RX_9_C_P F23L0TXP_1MGTHRXN1_229 P3HMC_L0RX_9_C_N F22L0TXN_1MGTHTXP2_229 N7HMC_L0TX_13_P A16L0RXP_2MGTHTXN2_229 N6HMC_L0TX_13_N A15L0RXN_2MGTHRXP2_229 N2HMC_L0RX_13_C_PD17L0TXP_2MGTHRXN2_229 N1HMC_L0RX_13_C_N D16L0TXN_2MGTHTXP3_229 M9HMC_L0TX_8_P A24L0RXP_3MGTHTXN3_229 M8HMC_L0TX_8_N A23L0RXN_3MGTHRXP3_229 M4HMC_L0RX_8_C_P C18L0TXP_3MGTHRXN3_229 M3HMC_L0RX_8_C_N C17L0TXN_3MGTREFCLK0P_229U11NA NA NANA MGTREFCLK0N_229U10NA NA NAMGTREFCLK1P_229T13NA NA NAMGTREFCLK1N_229T12NA NA NAThe HMC component U160 control bank connections are listed in Table 1-10.For more details about HMC, see the Micron MT43A4G40200NFA data sheet [Ref 21].Micro-SD Card Interface[Figure 1-2, callout 8]The VCU110 board includes a secure digital input/output (SDIO) interface to provide user access to general purpose nonvolatile micro-SD memory cards for configuration. The micro-SD card slot is designed to support 50MHz high speed micro-SD cards. The SDIO signals are connected to U111 XC7Z010 Zynq SoC system controller bank 500, which has its V CCO set to SYS_1V8 1.8V. A MAX13035E level-shifter (U154) is used between the XC7Z010 System Controller (U111) and the micro-SD card connector (J83).Table 1-10:HMC Memory U160 Control I/F Connections HMC U160 Pin NumberHMC U160 PinNameSchematic Net Name (1)I/O StandardConnected Pin NumberConnected DeviceU30P_RST_N HMC_P_RST_B LVCMOS15AW28FPGA U1N1REFCLK_BOOT_0HMC_REFCLK_BOOT_0LVCMOS15BA26U29REFCLK_BOOT_1HMC_REFCLK_BOOT_1LVCMOS15BB26V6REFCLKSEL HMC_REFCLK_SEL LVCMOS15AV30U5FERR_N HMC_FERR_B LVCMOS15AW30P29L1RXPS HMC_L1RXPS LVCMOS15BB27V24L1TXPS HMC_L1TXPS LVCMOS15AY29U28L0RXPS HMC_L0RXPS LVCMOS15AY30N24L0TXPS HMC_L0TXPSLVCMOS15AW27R30REFCLKN HMC_SI5328_OUT1_C_N (1)NA 28SI5328U57T30REFCLKP HMC_SI5328_OUT1_C_P (1)NA 29R28SCL IIC_SCL_HMC_LS (2)NA 16IIC MUX U28T24SDA IIC_SDA_HMC_LS (2)NA 15T5TCK HMC_TCK NA 5JTAG connector J120P7TDI HMC_TDI NA 3T1TDO HMC_TDO NA 2R5TMS HMC_TMS NA 4R7TRST_NHMC_TRST_BNA6Notes:1.Series capacitor coupled.2.IIC is level shifted through U159.The third SI5328 U181 jitter-attenuated clock multiplier circuit is shown in Figure1-12.。
FPGA可编程逻辑器件芯片XCKU13P-2FFVE900I中文规格书
General DescriptionXilinx® UltraScale™ architecture comprises high-performance FPGA, MPSoC, and RFSoC families that address a vast spectrum of system requirements with a focus on lowering total power consumption through numerous innovative technological advancements.Kintex® UltraScale FPGAs: High-performance FPGAs with a focus on price/performance, using both monolithic andnext-generation stacked silicon interconnect (SSI) technology. High DSP and block RAM-to-logic ratios and next-generation transceivers, combined with low-cost packaging, enable an optimum blend of capability and cost.Kintex UltraScale+™ FPGAs: Increased performance and on-chip UltraRAM memory to reduce BOM cost. The ideal mix of high-performance peripherals and cost-effective system implementation. Kintex UltraScale+ FPGAs have numerous power options that deliver the optimal balance between the required system performance and the smallest power envelope.Virtex® UltraScale FPGAs: High-capacity, high-performance FPGAs enabled using both monolithic and next-generation SSI technology. Virtex UltraScale devices achieve the highest system capacity, bandwidth, and performance to address key market and application requirements through integration of various system-level functions.Virtex UltraScale+ FPGAs: The highest transceiver bandwidth, highest DSP count, and highest on-chip and in-package memory available in the UltraScale architecture. Virtex UltraScale+ FPGAs also provide numerous power options that deliver the optimal balance between the required system performance and the smallest power envelope.Zynq® UltraScale+ MPSoCs : Combine the Arm® v8-based Cortex®-A53 high-performance energy-efficient 64-bit application processor with the Arm Cortex-R5F real-time processor and the UltraScale architecture to create the industry's firstprogrammable MPSoCs. Provide unprecedented power savings, heterogeneous processing, and programmable acceleration.Zynq® UltraScale+ RFSoCs: Combine RF data converter subsystem and forward error correction with industry-leadingprogrammable logic and heterogeneous processing capability. Integrated RF-ADCs, RF-DACs, and soft decision FECs (SD-FEC) provide the key subsystems for multiband, multi-mode cellular radios and cable infrastructure.Family ComparisonsUltraScale Architecture and Product Data Sheet: OverviewDS890 (v3.14) September 14, 2020Product SpecificationTable 1:Device ResourcesKintex UltraScale FPGAKintex UltraScale+FPGA Virtex UltraScale FPGA Virtex UltraScale+FPGA Zynq UltraScale+MPSoCZynq UltraScale+RFSoCMPSoC Processing System ✓✓RF-ADC/DAC ✓SD-FEC✓System Logic Cells (K)318–1,451356–1,843783–5,541862–8,938103–1,143489–930Block Memory (Mb)12.7–75.912.7–60.844.3–132.923.6–94.5 4.5–34.622.8–38.0UltraRAM (Mb)0–8190–3600–3613.5–45.0HBM DRAM (GB)0–16DSP (Slices)768–5,5201,368–3,528600–2,8801,320–12,288240–3,5281,872–4,272DSP Performance (GMAC/s)8,1806,2874,26821,8976,2877,613Transceivers12–6416–7636–12032–1280–728–16Max. Transceiver Speed (Gb/s)16.332.7530.558.032.7532.75Max. Serial Bandwidth (full duplex) (Gb/s)2,0863,2685,6168,3843,2681,048Memory Interface Performance (Mb/s)2,4002,6662,4002,6662,6662,666I/O Pins312–832280–668338–1,456208–2,07282–668152–408Virtex UltraScale+ HBM Device-Package Combinations and Maximum I/Os Table 12:Virtex UltraScale+ HBM Device-Package Combinations and Maximum I/OsPackage (1)(2)(3)(4)PackageDimensions(mm)VU31P VU33P VU35P VU37P VU45P VU47P VU57PHP,GTY HP,GTY HP,GTY HP,GTY HP,GTY HP,GTY HP,GTY,GTMFSVH192445x45208,32FSVH210447.5x47.5208,32416,64416,64FSVH289255x55416,64624,96416,64624,96FSVK289255x55624, 32, 32 Notes:1.Go to Ordering Information for package designation details.2.All packages have 1.0mm ball pitch.3.Packages with the same last letter and number sequence, e.g., A2104, are footprint compatible with all other UltraScalearchitecture-based devices with the same sequence. The footprint compatible devices within this family are outlined. See the UltraScale Architecture Product Selection Guide for details on inter-family migration.4.Consult UG583, UltraScale Architecture PCB Design User Guide for specific migration details.Zynq UltraScale+ MPSoC: CG Device Feature SummaryTable 13:Zynq UltraScale+ MPSoC: CG Device Feature SummaryZU2CG ZU3CG ZU4CG ZU5CG ZU6CG ZU7CG ZU9CGApplication Processing Unit Dual-core Arm Cortex-A53 MPCore with CoreSight; NEON & Single/Double Precision Floating Point;32KB/32KB L1 Cache, 1MB L2 CacheReal-Time Processing Unit Dual-core Arm Cortex-R5F with CoreSight; Single/Double Precision Floating Point;32KB/32KB L1 Cache, and TCMEmbedded and External Memory 256KB On-Chip Memory w/ECC; External DDR4; DDR3; DDR3L; LPDDR4; LPDDR3;External Quad-SPI; NAND; eMMCGeneral Connectivity214 PS I/O; UART; CAN; USB 2.0; I2C; SPI; 32b GPIO; Real Time Clock; WatchDog Timers; TripleTimer CountersHigh-Speed Connectivity 4 PS-GTR; PCIe Gen1/2; Serial ATA 3.1; DisplayPort 1.2a; USB3.0; SGMIISystem Logic Cells103,320154,350192,150256,200469,446504,000599,550 CLB Flip-Flops94,464141,120175,680234,240429,208460,800548,160 CLB LUTs47,23270,56087,840117,120214,604230,400274,080 Distributed RAM (Mb) 1.2 1.8 2.6 3.5 6.9 6.28.8 Block RAM Blocks150216128144714312912 Block RAM (Mb) 5.37.6 4.5 5.125.111.032.1 UltraRAM Blocks0048640960 UltraRAM (Mb)0013.518.0027.00 DSP Slices2403607281,2481,9731,7282,520 CMTs3344484 Max. HP I/O(1)156156156156208416208 Max. HD I/O(2)9696969612048120 System Monitor2222222 GTH Transceiver 16.3Gb/s(3)001616242424 GTY Transceivers32.75Gb/s0000000 Transceiver Fractional PLLs0088121212 PCIE4(PCIe Gen3x16)0022020150G Interlaken0000000100G Ethernet w/RS-FEC0000000 Notes:1.HP = High-performance I/O with support for I/O voltage from 1.0V to 1.8V.2.HD = High-density I/O with support for I/O voltage from 1.2V to3.3V.3.GTH transceivers in the SFVC784 package support data rates up to 12.5Gb/s. See Table14.RF Data Converter SubsystemZynq UltraScale+ RFSoCs contain an RF data converter subsystem consisting of multiple RF-ADCs and RF-DACs.RF-ADCsThe RF-ADCs can be configured individually for real input signals. RF-ADCs in all devices other than the XCZU43DR can also be configured as a pair for I/Q input signals. The RF-ADC tile has one PLL and a clocking instance. Decimation filters in the RF-ADCs can operate in varying decimation modes at 80% of Nyquist bandwidth with 89dB stop-band attenuation. Each RF-ADC contains a 48-bit numerically controlled oscillator (NCO) and a dedicated high-speed, high-performance, differential input buffer with on-chip calibrated 100 termination.RF-DACsThe RF-DACs can be configured individually for real outputs. RF-DACs in all devices other than the XCZU43DR can also be configured as a pair for I/Q output signal generation. The RF-DAC tile has one PLL and a clocking instance. Interpolation filters in the RF-DACs can operate in varying interpolation modes at 80% of Nyquist bandwidth with 89dB stop-band attenuation. Each RF-DAC contains a 48-bit NCO.Kintex UltraScaleKintexUltraScale+VirtexUltraScaleVirtexUltraScale+ZynqUltraScale+MPSoCZynqUltraScale+RFSoCGen1 (2.5GT/s)x8x16x8x16x16x16 Gen2 (5GT/s)x8x16x8x16x16x16 Gen3 (8GT/s)x8x16x8x16x16x16 Gen4 (16GT/s)(1)x8x8x8。
FPGA可编程逻辑器件芯片XCVU13P-2FHGA2104I中文规格书
General DescriptionXilinx® UltraScale™ architecture comprises high-performance FPGA, MPSoC, and RFSoC families that address a vast spectrum of system requirements with a focus on lowering total power consumption through numerous innovative technological advancements.Kintex® UltraScale FPGAs: High-performance FPGAs with a focus on price/performance, using both monolithic andnext-generation stacked silicon interconnect (SSI) technology. High DSP and block RAM-to-logic ratios and next-generation transceivers, combined with low-cost packaging, enable an optimum blend of capability and cost.Kintex UltraScale+™ FPGAs: Increased performance and on-chip UltraRAM memory to reduce BOM cost. The ideal mix of high-performance peripherals and cost-effective system implementation. Kintex UltraScale+ FPGAs have numerous power options that deliver the optimal balance between the required system performance and the smallest power envelope.Virtex® UltraScale FPGAs: High-capacity, high-performance FPGAs enabled using both monolithic and next-generation SSI technology. Virtex UltraScale devices achieve the highest system capacity, bandwidth, and performance to address key market and application requirements through integration of various system-level functions.Virtex UltraScale+ FPGAs: The highest transceiver bandwidth, highest DSP count, and highest on-chip and in-package memory available in the UltraScale architecture. Virtex UltraScale+ FPGAs also provide numerous power options that deliver the optimal balance between the required system performance and the smallest power envelope.Zynq® UltraScale+ MPSoCs: Combine the Arm® v8-based Cortex®-A53 high-performance energy-efficient 64-bit application processor with the Arm Cortex-R5F real-time processor and the UltraScale architecture to create the industry's first programmable MPSoCs. Provide unprecedented power savings, heterogeneous processing, and programmable acceleration. Zynq® UltraScale+ RFSoCs: Combine RF data converter subsystem and forward error correction with industry-leading programmable logic and heterogeneous processing capability. Integrated RF-ADCs, RF-DACs, and soft decision FECs (SD-FEC) provide the key subsystems for multiband, multi-mode cellular radios and cable infrastructure.Family ComparisonsDS890 (v3.14) September 14, 2020Product Specification Table 1:Device ResourcesKintex UltraScale FPGAKintexUltraScale+FPGAVirtexUltraScaleFPGAVirtexUltraScale+FPGAZynqUltraScale+MPSoCZynqUltraScale+RFSoCMPSoC Processing System✓✓RF-ADC/DAC✓SD-FEC✓System Logic Cells (K)318–1,451356–1,843783–5,541862–8,938103–1,143489–930 Block Memory (Mb)12.7–75.912.7–60.844.3–132.923.6–94.5 4.5–34.622.8–38.0 UltraRAM (Mb)0–8190–3600–3613.5–45.0 HBM DRAM (GB)0–16DSP (Slices)768–5,5201,368–3,528600–2,8801,320–12,288240–3,5281,872–4,272 DSP Performance (GMAC/s)8,1806,2874,26821,8976,2877,613 Transceivers12–6416–7636–12032–1280–728–16 Max. Transceiver Speed (Gb/s)16.332.7530.558.032.7532.75 Max. Serial Bandwidth (full duplex) (Gb/s)2,0863,2685,6168,3843,2681,048 Memory Interface Performance (Mb/s)2,4002,6662,4002,6662,6662,666I/O Pins312–832280–668338–1,456208–2,07282–668152–408Cache Coherent Interconnect for Accelerators (CCIX)CCIX is a chip-to-chip interconnect operating at data rates up to 25Gb/s that allows two or more devices to share memory in a cache coherent manner. Using PCIe for the transport layer, CCIX can operate at several standard data rates (2.5, 5, 8, and 16Gb/s) with an additional high-speed 25Gb/s option. The specification employs a subset of full coherency protocols and ensures that FPGAs used as accelerators can coherently share data with processors using different instruction set architectures.PCIE4C blocks support CCIX data rates up to 16Gb/s and contain one CCIX port. Each CCIX port requires the use of one integrated block for PCIe. If not used with a CCIX port, the integrated blocks for PCIe can still be used for PCIe communication.are stored in registers that can be accessed via internal FPGA (DRP), JTAG, PMBus, or I2C interfaces. The I2C interface and PMBus allow the on-chip monitoring to be easily accessed by the System Manager/Host before and after device configuration.The System Monitor in the PS MPSoC and RFSoC uses a 10-bit, 1 mega-sample-per-second (MSPS) ADC to digitize the sensor outputs. The measurements are stored in registers and are accessed via the Advanced Peripheral Bus (APB) interface by the processors and the platform management unit (PMU) in the PS.ConfigurationThe UltraScale architecture-based devices store their customized configuration in SRAM-type internal latches. The configuration storage is volatile and must be reloaded whenever the device is powered up. This storage can also be reloaded at any time. Several methods and data formats for loading configuration are available, determined by the mode pins, with more dedicated configuration datapath pins to simplify the configuration process.UltraScale architecture-based devices support secure and non-secure boot with optional Advanced Encryption Standard - Galois/Counter Mode (AES-GCM) decryption and authentication logic. If only authentication is required, the UltraScale architecture provides an alternative form of authentication in the form of RSA algorithms. For RSA authentication support in the Kintex UltraScale and Virtex UltraScale families, go to UG570, UltraScale Architecture Configuration User Guide.UltraScale architecture-based devices also have the ability to select between multiple configurations, and support robust field-update methodologies. This is especially useful for updates to a design after the end product has been shipped. Designers can release their product with an early version of the design, thus getting their product to market faster. This feature allows designers to keep their customers current with the most up-to-date design while the product is already deployed in the field.Booting MPSoCs and RFSoCsZynq UltraScale+MPSoCs and RFSoCs use a multi-stage boot process that supports both a non-secure and a secure boot. The PS is the master of the boot and configuration process. For a secure boot, the AES-GCM, SHA-3/384 decryption/authentication, and 4096-bit RSA blocks decrypt and authenticate the image.Upon reset, the device mode pins are read to determine the primary boot device to be used: NAND, Quad-SPI, SD, eMMC, or JTAG. JTAG can only be used as a non-secure boot source and is intended for debugging purposes. One of the CPUs, Cortex-A53 or Cortex-R5F, executes code out of on-chip ROM and copies the first stage boot loader (FSBL) from the boot device to the on-chip memory (OCM).After copying the FSBL to OCM, the processor executes the FSBL. Xilinx supplies example FSBLs or users can create their own. The FSBL initiates the boot of the PS and can load and configure the PL, or configuration of the PL can be deferred to a later stage. The FSBL typically loads either a user application or an optional second stage boot loader (SSBL) such as U-Boot. Users obtain example SSBL from Xilinx or a third party, or they can create their own SSBL. The SSBL continues the boot process by loading code from any of the primary boot devices or from other sources such as USB, Ethernet, etc. If the FSBL did not configure the PL, the SSBL can do so, or again, the configuration can be deferred to a later stage.。
FPGA可编程逻辑器件芯片XCVU13P-L2FHGB2104E中文规格书
– 2
VU35P 1,906,800 1,743,360 871,680
24.6 1,344 47.3 640 180.0
8 8 416 5,952 2 64 0 0 32 1
4
2 5
VU37P 2,851,800 2,607,360 1,303,680
36.7 2,016 70.9
960 270.0
48, 416 24, 0
Notes:
1. Go to Ordering Information for package designation details. 2. FB/FF packages have 1.0mm ball pitch. SF packages have 0.8mm ball pitch. 3. All device package combinations bond out 4 PS-GTR transceivers. 4. GTH transceivers in the SFVC784 package support data rates up to 12.5Gb/s. 5. Packages with the same last letter and number sequence, e.g., B900, are footprint compatible with all other UltraScale
35x35
FFVF1517
40x40
ZU4EV
HD, HP GTH, GTY
96, 156 4, 0
48, 156 16, 0
ZU5EV
HD, HP GTH, GTY
96, 156 4, 0
48, 156 16, 0
ZU7EV HD, HP GTH, GTY
FPGA可编程逻辑器件芯片XCVU190-1FLGB2104C中文规格书
DS635 (v2.0) September 9, 2009Product SpecificationDifferential I/O StandardsTable 11: Recommended Operating Conditions for User I/Os Using Differential Signal Standards IOSTANDARD Attribute V CCO for Drivers (1)V IDV ICM Min (V)Nom (V)Max (V)Min(mV)Nom (mV)Max (mV)Min (V)Nom (V)Max (V)LVDS_25 2.375 2.50 2.6251003506000.30 1.25 2.20BLVDS_25 2.375 2.50 2.6251003506000.30 1.25 2.20MINI_LVDS_25 2.375 2.50 2.625200-6000.30- 2.2LVPECL_25(2)Inputs Only 10080010000.5 1.2 2.0RSDS_25 2.375 2.50 2.625100200-0.3 1.20 1.4DIFF_HSTL_I_18 1.7 1.8 1.9100--0.8- 1.1DIFF_HSTL_III_18 1.7 1.8 1.9100--0.8- 1.1DIFF_SSTL18_I 1.7 1.8 1.9100--0.7- 1.1DIFF_SSTL2_I2.3 2.5 2.7100-- 1.0- 1.5Notes:1.The V CCO rails supply only differential output drivers, not input circuits.2.V REF inputs are not used for any of the differential I/O standards.Table 12: DC Characteristics of User I/Os Using Differential Signal Standards IOSTANDARDAttributeV ODΔV OD V OCM ΔV OCM V OH V OL Min (mV)Typ (mV)Max (mV)Min (mV)Max (mV)Min (V)Typ (V)Max (V)Min (mV)Max (mV)Min (V)Max (V)LVDS_25250350450–– 1.125– 1.375––––BLVDS_25250350450––– 1.20–––––MINI_LVDS_25300–600–50 1.0– 1.4–50––RSDS_25100–400–– 1.1– 1.4––––DIFF_HSTL_I_18––––––––––V CCO – 0.40.4DIFF_HSTL_III_18––––––––––V CCO – 0.40.4DIFF_SSTL18_I––––––––––V TT + 0.475V TT – 0.475DIFF_SSTL2_I––––––––––V TT + 0.61V TT – 0.61Notes:1.The numbers in this table are based on the conditions set forth in T able 6, and T able 11.2.Output voltage measurements for all differential standards are made with a termination resistor (R T ) of 100Ω across the N and P pins of the differential signal pair. The exception is for BLVDS, shown in Figure 5 below.3.At any given time, no more than two of the following differential output standards may be assigned to an I/O bank: LVDS_25, RSDS_25,MINI_LVDS_25DS635 (v2.0) September 9, 2009Product Specification Single-Ended I/O StandardsTable 9: Recommended Operating Conditions for User I/Os Using Single-Ended Standards IOSTANDARD AttributeV CCO for Drivers (2)V REF V IL V IH Min (V)Nom (V)Max (V)Min (V)Nom (V)Max (V)Max (V)Min (V)LVTTL3.0 3.3 3.465V REF is not used for these I/O standards 0.8 2.0LVCMOS33(4)3.0 3.3 3.4650.8 2.0LVCMOS25(4,5)2.3 2.5 2.70.7 1.7LVCMOS181.65 1.8 1.950.40.8LVCMOS151.4 1.5 1.60.40.8LVCMOS121.1 1.2 1.30.40.7PCI33_33.0 3.3 3.4650.3 * V CCO 0.5 * V CCO HSTL_I_181.7 1.8 1.90.80.9 1.1V REF - 0.1V REF + 0.1HSTL_III_181.7 1.8 1.9- 1.1-V REF - 0.1V REF + 0.1SSTL18_I1.7 1.8 1.90.8330.9000.969V REF - 0.125V REF + 0.125SSTL2_I2.3 2.5 2.7 1.15 1.25 1.35V REF - 0.125V REF + 0.125Notes:1.Descriptions of the symbols used in this table are as follows:V CCO – the supply voltage for output driversV REF – the reference voltage for setting the input switching thresholdV IL – the input voltage that indicates a Low logic levelV IH – the input voltage that indicates a High logic level2.The V CCO rails supply only output drivers, not input circuits.3.For device operation, the maximum signal voltage (V IH max) may be as high as V IN max. See Table 72 in DS312.4.There is approximately 100 mV of hysteresis on inputs using LVCMOS33 and LVCMOS25 I/O standards.5.All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) use the LVCMOS25 standard and draw power from the V CCAUX rail (2.5V). The Dual-Purpose configuration pins use the LVCMOS standard before the User mode. When using these pins as part of a standard 2.5V configuration interface, apply 2.5V to the V CCO lines of Banks 0, 1, and 2 at power-on as well as throughout configuration.6.For information on PCI IP solutions .。
FPGA可编程逻辑器件芯片XCVU9P-2FLGA2104I中文规格书
Chapter2 Board Setup and ConfigurationBoard Component LocationFigure2-1 shows the VCU118 board component locations. Each numbered componentshown in the figure is keyed to Table2-1. Table2-1 identifies the components, references the respective schematic page numbers, and links to a detailed functional description of the components and board features in Chapter3.Electrostatic Discharge Cautionreplacing components.To prevent ESD damage:•Use an ESD wrist or ankle strap and ensure that it makes skin contact. Connect theequipment end of the strap to an unpainted metal surface on the chassis.•Avoid touching the adapter against your clothing. The wrist strap protects components from ESD on the body only.•Handle the adapter by its bracket or edges only. Avoid touching the printed circuit board or the connectors.•Put the adapter down only on an antistatic surface such as the bag supplied in your kit.FPGA (U1)Pin Schematic Net Name I/O StandardComponent MemoryPin #Pin Name Ref. Des.F11DDR4_C1_DQ0POD12_DCI G2DQL0U60 E11DDR4_C1_DQ1POD12_DCI F7DQL1U60 F10DDR4_C1_DQ2POD12_DCI H3DQL2U60 F9DDR4_C1_DQ3POD12_DCI H7DQL3U60 H12DDR4_C1_DQ4POD12_DCI H2DQL4U60 G12DDR4_C1_DQ5POD12_DCI H8DQL5U60 E9DDR4_C1_DQ6POD12_DCI J3DQL6U60 D9DDR4_C1_DQ7POD12_DCI J7DQL7U60 R19DDR4_C1_DQ8POD12_DCI A3DQU0U60 P19DDR4_C1_DQ9POD12_DCI B8DQU1U60 M18DDR4_C1_DQ10POD12_DCI C3DQU2U60 M17DDR4_C1_DQ11POD12_DCI C7DQU3U60AY28 DDR4_C2_DQ77POD12_DCI C8DQU5U139 BA27 DDR4_C2_DQ78POD12_DCI D3DQU6U139 BB27 DDR4_C2_DQ79POD12_DCI D7DQU7U139 BE25 DDR4_C2_DQS8_T DIFF_POD12_DCI G3DQSL_C U139 BF25 DDR4_C2_DQS8_C DIFF_POD12_DCI F3DQSL_T U139 BA26 DDR4_C2_DQS9_T DIFF_POD12_DCI B7DQSU_C U139 BB26 DDR4_C2_DQS9_C DIFF_POD12_DCI A7DQSU_T U139 BE29 DDR4_C2_DM8POD12_DCI E7DML_B/DBIL_B U139 BA29 DDR4_C2_DM9POD12_DCI E2DMU_B/DBIU_BU139 AM27 DDR4_C2_A0SSTL12_DCI P3A0U135-U139 AL27 DDR4_C2_A1SSTL12_DCI P7A1U135-U139 AP26 DDR4_C2_A2SSTL12_DCI R3A2U135-U139 AP25 DDR4_C2_A3SSTL12_DCI N7A3U135-U139 AN28 DDR4_C2_A4SSTL12_DCI N3A4U135-U139 AM28 DDR4_C2_A5SSTL12_DCI P8A5U135-U139 AP28 DDR4_C2_A6SSTL12_DCI P2A6U135-U139 AP27 DDR4_C2_A7SSTL12_DCI R8A7U135-U139 AN26 DDR4_C2_A8SSTL12_DCI R2A8U135-U139 AM26 DDR4_C2_A9SSTL12_DCI R7A9U135-U139 AR28 DDR4_C2_A10SSTL12_DCI M3A10/AP U135-U139 AR27 DDR4_C2_A11SSTL12_DCI T2A11U135-U139 AV25 DDR4_C2_A12SSTL12_DCI M7A12/BC_B U135-U139 AT25 DDR4_C2_A13SSTL12_DCI T8A13U135-U139 AR25 DDR4_C2_BA0SSTL12_DCI N2BA0U135-U139 AU28 DDR4_C2_BA1SSTL12_DCI N8BA1U135-U139 AU27 DDR4_C2_BG0SSTL12_DCI M2BG0U135-U139 AV28 DDR4_C2_A14_WE_B SSTL12_DCI L2WE_B/A14U135-U139 AU26 DDR4_C2_A15_CAS_B SSTL12_DCI M8CAS_B_A15U135-U139 AV26 DDR4_C2_A16_RAS_B SSTL12_DCI L8RAS_B/A16U135-U139 AT26 DDR4_C2_CK_T DIFF_SSTL12_DCI K7CK_T U135-U139 AT27 DDR4_C2_CK_C DIFF_SSTL12_DCI K8CK_C U135-U139 AW28 DDR4_C2_CKE SSTL12_DCI K2CKE U135-U139 AN25 DDR4_C2_ACT_B SSTL12_DCI L3ACT_B U135-U139 BF29DDR4_C2_PARSSTL12_DCIP9ALERT_BU135-U139FPGA (U1)PinSchematic Net NameI/O StandardComponent MemoryPin #Pin NameRef. Des.BB29 DDR4_C2_ODT SSTL12_DCI T3PAR U135-U139 AY29 DDR4_C2_CS_B SSTL12_DCI K3ODT U135-U139 AR29 DDR4_C2_ALERT_B SSTL12_DCI L7CS_B U135-U139 BD35 DDR4_C2_RESET_B LVCMOS12P1RESET_B U135-U139 AY35DDR4_C2_TENSSTL12_DCIN9TENU135-U139FPGA (U1)PinSchematic Net NameI/O StandardComponent MemoryPin #Pin NameRef. Des.The connections between the dual-QSPI flash memory and the XCVU9P FPGA are listed in Table 3-5.The UltraScale Architecture Configuration User Guide (UG570) [Ref 2] provides FPGA configuration details. For more Quad SPI component information, see the Micron MT25QU01GBB8ESF-0SIT data sheet at the Micron website [Ref 18].System Controller Micro-SD Card Interface[Figure 2-1, callout 7]The VCU118 board includes a secure digital input/output (SDIO) interface allowing the U111 XC7Z010 Zynq-7000 SoC system controller access to general purpose nonvolatile micro-SD memory cards and peripherals. The micro-SD card slot is designed to support 50MHz high speed micro-SD cards. The SD card is not accessible by the U1 XCVU9P FPGA and is not an FPGA configuration option.Table 3-5:Quad-SPI Component Connections to FPGA U1XCVC9P (U1) PinNet NameU133 (QSPI0), U43 (QSPI1)Pin #Pin NameAP11QSPI0_DQ015DQ0AN11QSPI0_DQ18DQ1AM11QSPI0_DQ29DQ2_WP_B AL11QSPI0_DQ31DQ3_RST_HOLD_BAF13QSPI _CLK 16 C AJ11QSPI0_CS_B 7S_B AM19QSPI1_DQ015DQ0AM18QSPI1_DQ18DQ1AN20QSPI1_DQ29DQ2_WP_B AP20QSPI1_DQ31DQ3_RST_HOLD_BAF13QSPI _CLK 16 C BF16QSPI1_CS_B7S_B。
FPGA可编程逻辑器件芯片XCVU13P-2FIGD2104I中文规格书
SummaryMany systems use byte-wide peripheral interface (BPI) flash memory for FPGA configuration and system data storage. Often it is not desirable or even possible to update the flash PROM directly after the system is deployed. One approach to address this issue is to use the FPGA to program the PROM to which it is connected. This methodology is called in-systemprogramming (ISP). An example of ISP is the indirect programming capability supported by iMPACT (a tool featuring batch and GUI operations). In this case, iMPACT uses the JTAG interface port as the communication channel between a host and the FPGA. The iMPACT tool sends the bit file to the FPGA, which in turn programs the PROM attached to it.However, many embedded systems do not have such JTAG interface connections available. The FPGA is often an endpoint device on the PCI Express® bus. Because no JTAG interface channel is available through the standard PCIe® peripheral, the only way to program a PROM on the endpoint is to program across the PCIe system.This application note provides an ISP reference design to demonstrate the methodology and considerations of programming in-system BPI PROM for Virtex®-6, Virtex®-7, and Kintex®-7 FPGAs in a PCIe system.OverviewFigure 1 shows the high-level block diagram of the ISP reference design. The design comprises three major components: an integrated block for PCI Express core, a buffer, and a programming state machine (PSM).The ISP reference design targets the ML605, VC707, and the KC705 evaluation boards. The ML605 board has an XC6VLX240T -1FFG1156 FPGA connected to a 256 Mb BPI PROM.Application Note: Virtex-6, Virtex-7, and Kintex-7 FamilyXAPP518 (v1.3) April 23, 2014In-System Programming of BPI PROM for Virtex-6, Virtex-7, and Kintex-7 FPGAs Using PCI Express TechnologyAuthor: Simon TamFigure 1:High-Level Block DiagramIntegrated Block for PCI ExpressFailsafe PROM Update Problems can occur during the PROM update process. For example, the system power might be interrupted or the PROM data are corrupted while the new configuration bitstream is being updated in the PROM. The result is that the FPGA cannot configure properly from the PROM after such failed PROM update event. A failsafe methodology needs to be in place to ensure the continued operation and recovery of the system.One method to address the potential issue is to use the FPGA configuration fallback feature. Fallback is control logic that ensures the FPGA is always configured with a default PROM image if there is an error during the configuration process. Such user default system has minimal features with the sole purpose to recover from configuration failure.During configuration, these errors can trigger fallback: an IDCODE error, a CRC error, a Watchdog Timer timeout error, or a BPI address wraparound error. After configuration, the Watchdog Timer, enabled in the user monitor mode, can also trigger fallback. If fallback reconfiguration fails a second time, configuration stops and both INIT_B and DONE are held Low. Fallback can also be disabled with BitGen option -g ConfigFallback:Disable. During fallback reconfiguration, the FPGA drives new values on the two dual-mode pinsRS[1:0] (revision select). RS[1:0] are in high-impedance state and weakly pulled up during the first configuration, and weakly pulled down after configuration by default. The user can use external pull-up/pull-down resistors to override the FPGA weak pull-up resistor during first configuration to load the desired bitstream. When a configuration error is detected, the configuration logic generates an internal reset pulse and actively drives RS[1:0] to 00 for loading the fallback bitstream.The ML605 board can demonstrate fallback configuration. For example, let the onboard BPI PROM be divided into two halves of equal size containing two images—a user function image and a fallback image. The user function image has the bitstream of intended normal operation and should be stored in the upper half of the PROM address range. The fallback image has the golden bitstream that is for recovery after an unsuccessful configuration event and should be stored in the lower half of the PROM address range. Figure24 shows the PROM address mapping.One of the FPGA revision select pins, RS[0], is connected to the most significant address bit (A[24] pin) of the PROM shown in Figure 25 (RS[1] is not connected). A[24] is connected to DIP switch S2-6 through a weak pull-up resistor.When the configuration mode is set to master BPI-up mode, the BPI address pin Addr[22:0] is set to logic zero upon power-up. If DIP switch S2-6 is closed, the address presented to the PROM is 0x800000. Therefore, the FPGA begins loading the configuration bitstream from the upper memory region starting from address 0x800000 where the user configuration bitstream is located.If there is any error event during configuration it triggers fallback configuration. The internal configuration logic drives the RS[0] pin and BPI address pins Addr[22:0] to all zeros, effectively pointing the PROM address to 0x0. It then restarts the configuration process starting from 0x0 loading the fallback bitstream.Fallback DemonstrationThese steps demonstrate the fallback feature on the ML605 board:1.Set DIP switch S2 on the ML605 board as follows to enable BPI PROM programming:•S2-1 = ON •S2-2 = ON •S2-3 = OFF •S2-4 = ON •S2-5 = ON •S2-6 = OFF •S1-1 = OFF •S1-2 = OFF •S1-3 = OFF •S1-4 = OFFunch the application <ref_design_dir>\sw\XAPP518_PCIe_ISP.exe .3.Click the Program PROM button. Select a pre-made PROM file available at<ref_design_dir>\config\PROM\XAPP518_corrupted_PROM_img.mcs .4.Click Open .This MCS file is a corrupted image file and causes configuration failure during loading. The start address of this particular image file is 0x800000.Figure 25:ML605 Revision Select Pin Connection。
FPGA可编程逻辑器件芯片XCVU13P-L2FIGD2104E中文规格书
Device DiagramsSummaryThe diagrams in this chapter show a top-view perspective of the package pinout of each UltraScale and UltraScale+ device/package combination. Table3-1 through Table3-4contain cross references to the device diagrams. The I/O-bank diagram shows the location of each user I/O and GTH/GTY transceiver and the respective bank or GT quad. Theconfiguration-power diagram shows the location of every power pin and dedicated as well as multi-function configuration pin in the package. See Package SpecificationsDesignations in Chapter2 for definitions of Evaluation Only, Engineering Sample, andProduction device diagrams.Table 3-1:Cross-Reference to Kintex UltraScale and XQ Kintex UltraScale Device Diagrams by PackagePackage Footprint Compatible Devices Package StatusFBVA676XCKU035page186XCKU040page186ProductionRBA676XQKU040page186ProductionSFVA784XCKU035page188XCKU040page188ProductionFBVA900XCKU035page190XCKU040page190ProductionFFVA1156XCKU025page192XCKU035page194XCKU040page196XCKU060page198XCKU095page200ProductionRFA1156XQKU040page196XQKU060page198XQKU095page200ProductionFFVA1517XCKU060page202ProductionChapter 5:Package MarkingTable 5-1:XC Device Marking Definition—ExampleItem DefinitionXilinx Logo Xilinx logo, Xilinx name with trademark, and trademark-registered status.Family Brand Logo Device family name with trademark and trademark-registered status. This line is optional and could appear blank.1st Line Device name. This line is not marked on some devices. Refer to the bar code for device information. 2nd Line This line is not marked on some devices. Refer to the bar code for device information.•Package code: FF1st digit: F for flip-chip BGA, S for flip-chip BGA with 0.8mm ball pitch.2nd digit: F for lidded, L for lidded SSI, B for bare-die, H for overhang SSI, S for lidless SSIstiffener, and I for overhang lidless SSI stiffener.•3rd digit: Pb-free code: V for RoHS 6/6, G for RoHS 6/6 with exemption 15, or for packages witheutectic BGA balls (R or Q).All commercial (XC) UltraScale Architecture devices have Pb-free RoHS compliant packaging. Formore details on Xilinx Pb-free and RoHS compliant products.•4th digit: This is the pin out (net list) identifier.•5th–8th digits: These are the physical pin count identifiers: A1156 and D1924 are shown in theFigure5-1 and Figure5-2 example marking drawings. Example: A package code of FFVA1517and FFVC1517 means they have a different pinout (net list) but the same physical ball count andphysical dimensions.•Three letter circuit design revision, the location code for the wafer fab, and the geometry code(xxx). Designated as the mask code in some figures.•When marked, the date code: YYWW (two digit year and work week). This code is not markedon some devices. Refer to the bar code for more information.3rd Line When marked, this line describes ten alphanumeric characters for assembly location, 7-digit lot number, and step information. The last digit is usually an A or an M if a stepping version does notexist.This line is not marked on some devices. Refer to the bar code for more information.4th Line When marked, this line describes the device speed grade (1) and temperature operating range (C).When not marked on the package, the product is considered to operate at the extended (E)temperature range.If a bar code is present on the device, the 4th line might be blank or unmarked. In this case, referto the bar code for speed grade and temperature range information. For more information on theordering codes, see the UltraScale Architecture and Product Overview (DS890) [Ref1].Other variations for the 4th line:L1I The L1I indicates a -1LI device. The -1LI speed grade offers reduced maximum powerconsumption. For more information, see the specific device’s data sheet [Ref3].1C xxxx The xxxx indicates a 4-digit SCD device option. An SCD is a special ordering codethat is not always marked in the device top mark.1C ES 2E ES L1I ES The addition of an ES after the operating temperature range code indicates an engineering sample.Bar Code A device-specific bar code is marked on each device. Refer to the FAQ: Top Marking Change for 7 Series, UltraScale, and UltraScale+ Products (XTP424) [Ref12].T e m p e r a t u r e (°C )ug575_c7_02_090919。
FPGA可编程逻辑器件芯片XCVU13P-2FIGD2104E中文规格书
For complete information about Tandem Configuration, including required PCIe block locations, design flow examples, requirements, restrictions and other considerations, see Tandem Configuration in the UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213).Supported DevicesThe DMA/Bridge Subsystem for PCIe® and Vivado® tool flow support implementations targeting Xilinx® reference boards and specific part/package combinations. Tandem configuration supports the configurations found in the following tables.UltraScale DevicesThe following table lists the Tandem PROM/PCIe supported configurations for UltraScale™devices.HDL Verilog OnlyPCIeConfigurationAll configurations (max: X8Gen3)Xilinx Reference Board Support KCU105 Evaluation Board for Kintex® UltraScale™ FPGA VCU108 Evaluation Board for Virtex® UltraScale™ FPGADevice Support Part1PCIe BlockLocationPCIe ResetLocationTandemConfigurationTandem withField UpdatesKintex UltraScale XCKU025PCIE_3_1_X0Y0IOB_X1Y103Production Production XCKU035PCIE_3_1_X0Y0IOB_X1Y103Production Production XCKU040PCIE_3_1_X0Y0IOB_X1Y103Production Production XCKU060PCIE_3_1_X0Y0IOB_X2Y103Production Production XCKU085PCIE_3_1_X0Y0IOB_X2Y103Production Production XCKU095PCIE_3_1_X0Y0IOB_X1Y103Production Production XCKU115PCIE_3_1_X0Y0IOB_X2Y103Production ProductionVirtex UltraScale XCVU065PCIE_3_1_X0Y0IOB_X1Y103Production Production XCVU080PCIE_3_1_X0Y0IOB_X1Y103Production Production XCVU095PCIE_3_1_X0Y0IOB_X1Y103Production Production XCVU125PCIE_3_1_X0Y0IOB_X1Y103Production Production XCVU160PCIE_3_1_X0Y1IOB_X1Y363Production Production XCVU190PCIE_3_1_X0Y2IOB_X1Y363Production Production XCVU440PCIE_3_1_X0Y2IOB_X1Y363Production ProductionNotes:1.Only production silicon is officially supported. Bitstream generation is disabled for all engineering sample silicon(ES2) devices.Chapter 4: Designing with the SubsystemT o achieve consistent implementation results, an XDC containing these original, unmodified constraints must be used when a design is run through the Xilinx tools. For additional details on the definition and use of an XDC or specific constraints, see Vivado Design Suite User Guide: Using Constraints (UG903).Constraints provided with the integrated block solution have been tested in hardware andprovide consistent results. Constraints can be modified, but modifications should only be made with a thorough understanding of the effect of each constraint. Additionally, support is not provided for designs that deviate from the provided constraints.Device, Package, and Speed Grade SelectionsThe device selection portion of the XDC informs the implementation tools which part, package,and speed grade to target for the design.IMPORTANT! Because Gen2 and Gen3 Integrated Block for PCIe cores are designed for specific part and package combinations, this section should not be modified.The device selection section always contains a part selection line, but can also contain part or package-specific options. An example part selection line follows:CONFIG PART = XCKU040-ffva1156-3-e-es1Clock Frequencies, Clock Management, and Clock PlacementFor detailed information about clock requirements, see the respective product guide listed below:•7 Series FPGAs Integrated Block for PCI Express LogiCORE IP Product Guide (PG054)•Virtex-7 FPGA Integrated Block for PCI Express LogiCORE IP Product Guide (PG023)•UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)•UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213)BankingThis section is not applicable for this IP subsystem.Transceiver PlacementThis section is not applicable for this IP subsystem.I/O Standard and PlacementThis section is not applicable for this IP subsystem.Chapter 5: Design Flow Steps。
FPGA可编程逻辑器件芯片XCVU13P-I2FHGB2104E中文规格书
Block RAMSome of the key features of the block RAM include:•Dual-port 36Kb block RAM with port widths of up to 72•Programmable FIFO logic•Built-in optional error correction circuitryEvery 7series FPGA has between 5 and 1,880 dual-port block RAMs, each storing 36Kb. Each block RAM has two completely independent ports that share nothing but the stored data.Synchronous OperationEach memory access, read or write, is controlled by the clock. All inputs, data, address, clock enables, and write enables are registered. Nothing happens without a clock. The input address is always clocked, retaining data until the next operation. An optional output data pipeline register allows higher clock rates at the cost of an extra cycle of latency.During a write operation, the data output can reflect either the previously stored data, the newly written data, or can remain unchanged.Programmable Data WidthEach port can be configured as 32K×1, 16K×2, 8K×4, 4K×9 (or8), 2K×18 (or16), 1K×36 (or32), or 512×72 (or64). The two ports can have different aspect ratios without any constraints.Each block RAM can be divided into two completely independent 18Kb block RAMs that can each be configured to any aspect ratio from 16K×1 to 512×36. Everything described previously for the full 36Kb block RAM also applies to each of the smaller 18Kb block RAMs.Only in simple dual-port (SDP) mode can data widths of greater than 18bits (18Kb RAM) or 36bits (36Kb RAM) be accessed. In this mode, one port is dedicated to read operation, the other to write operation. In SDP mode, one side (read or write) can be variable, while the other is fixed to 32/36 or 64/72.Both sides of the dual-port 36Kb RAM can be of variable width.Two adjacent 36Kb block RAMs can be configured as one cascaded 64K×1 dual-port RAM without any additional logic. Error Detection and CorrectionEach 64-bit-wide block RAM can generate, store, and utilize eight additional Hamming code bits and perform single-bit error correction and double-bit error detection (ECC) during the read process. The ECC logic can also be used when writing to or reading from external 64- to 72-bit-wide memories.FIFO ControllerThe built-in FIFO controller for single-clock (synchronous) or dual-clock (asynchronous or multirate) operation increments the internal addresses and provides four handshaking flags: full, empty, almost full, and almost empty. The almost full and almost empty flags are freely programmable. Similar to the block RAM, the FIFO width and depth are programmable, but the write and read ports always have identical width.First word fall-through mode presents the first-written word on the data output even before the first read operation. After the first word has been read, there is no difference between this mode and the standard mode.I/O Electrical CharacteristicsSingle-ended outputs use a conventional CMOS push/pull output structure driving High towards V CCO or Low towards ground, and can be put into a high-Z state. The system designer can specify the slew rate and the output strength. The input is always active but is usually ignored while the output is active. Each pin can optionally have a weak pull-up or a weak pull-down resistor.Most signal pin pairs can be configured as differential input pairs or output pairs. Differential input pin pairs can optionally be terminated with a 100 internal resistor. All 7series devices support differential standards beyond LVDS: RSDS, BLVDS, differential SSTL, and differential HSTL.Each of the I/Os supports memory I/O standards, such as single-ended and differential HSTL as well as single-ended SSTL and differential SSTL. The SSTL I/O standard can support data rates of up to 1,866Mb/s for DDR3 interfacing applications. 3-State Digitally Controlled Impedance and Low Power I/O FeaturesThe 3-state Digitally Controlled Impedance (T_DCI) can control the output drive impedance (series termination) or can provide parallel termination of an input signal to V CCO or split (Thevenin) termination to V CCO/2. This allows users to eliminate off-chip termination for signals using T_DCI. In addition to board space savings, the termination automatically turns off when in output mode or when 3-stated, saving considerable power compared to off-chip termination. The I/Os also have low power modes for IBUF and IDELAY to provide further power savings, especially when used to implement memory interfaces.I/O LogicInput and Output DelayAll inputs and outputs can be configured as either combinatorial or registered. Double data rate (DDR) is supported by all inputs and outputs. Any input and some outputs can be individually delayed by up to 32 increments of 78ps, 52ps, or 39ps each. Such delays are implemented as IDELAY and ODELAY. The number of delay steps can be set by configuration and can also be incremented or decremented while in use.ISERDES and OSERDESMany applications combine high-speed, bit-serial I/O with slower parallel operation inside the device. This requires a serializer and deserializer (SerDes) inside the I/O structure. Each I/O pin possesses an 8-bit IOSERDES (ISERDES and OSERDES) capable of performing serial-to-parallel or parallel-to-serial conversions with programmable widths of 2, 3, 4, 5, 6, 7, or 8 bits. By cascading two IOSERDES from two adjacent pins (default from differential I/O), wider width conversions of 10 and 14 bits can also be supported. The ISERDES has a special oversampling mode capable of asynchronous data recovery for applications like a 1.25Gb/s LVDS I/O-based SGMII interface.Low-Power Gigabit TransceiversSome highlights of the Low-Power Gigabit Transceivers include:•High-performance transceivers capable of up to 6.6Gb/s (GTP), 12.5Gb/s (GTX), 13.1Gb/s (GTH), or 28.05Gb/s (GTZ) line rates depending on the family, enabling the first single device for 400G implementations.•Low-power mode optimized for chip-to-chip interfaces.•Advanced Transmit pre and post emphasis, receiver linear equalization (CTLE), and decision feedback equalization (DFE) for long reach or backplane applications. Auto-adaption at receiver equalization and on-chip Eye Scan for easy serial link tuning.Ultra-fast serial data transmission to optical modules, between ICs on the same PCB, over the backplane, or over longer distances is becoming increasingly popular and important to enable customer line cards to scale to 100Gb/s and onwards to 400Gb/s. It requires specialized dedicated on-chip circuitry and differential I/O capable of coping with the signal integrity issues at these high data rates.The transceiver count in the 7series FPGAs ranges from up to 16 transceiver circuits in the Artix-7 family, up to 32 transceiver circuits in the Kintex-7 family, and up to 96transceiver circuits in the Virtex-7 family. Each serial transceiver is a combined transmitter and receiver. The various 7series serial transceivers use either a combination of ring oscillators and。
FPGA可编程逻辑器件芯片XCVU13P-2FLGB2104E中文规格书
Chapter 6Example DesignThis chapter contains information about the example designs provided in the Vivado® DesignSuite.Available Example DesignsThe example designs are as follows:•AXI4 Memory Mapped Default Example Design•AXI4 Memory Mapped with PCIe to AXI4-Lite Master and PCIe to DMA Bypass Example Design•AXI4 Memory Mapped with AXI4-Lite Slave Interface Example Design•AXI4-Stream Example Design•AXI4 Memory Mapped with Descriptor Bypass Example•Vivado IP Integrator-Based Example Design•User IRQ Example DesignPG195 (v4.1) April 29, 2021DMA/Bridge Subsystem for PCIe v4.1Chapter 7: Test Bench •By default, post-synthesis simulation is not supported for the example design. T o enable post-synthesis simulation, generate the IP using the following T cl command:set_property -dict [list CONFIG.post_synth_sim_en {true}] [get_ips<ip_name>]Note: With this feature, functional simulation time increases to approximately 2.5 ms.AXI4 Memory Mapped InterfaceFirst, the test case starts the H2C engine. The H2C engine reads data from host memory andwrites to block RAM on user side. Then, the test case starts the C2H engine. The C2H enginereads data from block RAM and writes to host memory. The following are the simulation steps:1.The test case sets up one descriptor for the H2C engine.2.The H2C descriptor is created in the Host memory. The H2C descriptor gives data length 128bytes, source address (host), and destination address (Card).3.The test case writes data (incremental 128 bytes of data) in the source address space.4.The test case also sets up one descriptor for the C2H engine.5.The C2H descriptor gives data length 128 bytes, source address (Card), and destinationaddress (host).6.Write H2C descriptor starting address to register (0x4080 and 0x4084).7.Write to H2C control register to start H2C transfer address (0x0004). Bit 0 is set to 1 to startthe transfer. For details of control register, refer to H2C Channel Control (0x04).8.The DMA transfer takes the data host source address and sends to the block RAMdestination address.9.The test case then starts the C2H transfer.10.Write C2H descriptor starting address to register (0x5080 and0x5084).11.Write to C2H control register to start the C2H transfer (0x1004). Bit 0 is set to 1 to start thetransfer. For details of control the register, see C2H Channel Control (0x04).12.The DMA transfer takes data from the block RAM source address and sends data to the hostdestination address.13.The test case then compares the data for correctness.14.The test case checks for the H2C and C2H descriptor completed count (value of 1).15.The test case then disables transfer by deactivating the Run bit (bit0) in the Control registers(0x0004 and 0x1004) for the H2C and C2H engines.PG195 (v4.1) April 29, 2021DMA/Bridge Subsystem for PCIe v4.1。
FPGA可编程逻辑器件芯片XCVU13P-1FIGD2104C中文规格书
C2H Channel Performance Data Count (0xCC)Table 76: C2H Channel Performance Data Count (0xCC)Bit Index Default Access Type Description 31:032’h0RO pmon_dat_count[31:0]Increments for each valid read data beat while running. Seethe Performance Monitor Control register (0xC0) bits Clearand Auto for clearing.C2H Channel Performance Data Count (0xD0)Table 77: C2H Channel Performance Data Count (0xD0)Bit Index Default Access Type Description161’b0RO pmon_dat_count_maxedData count maximum was hit15:10Reserved9:010’h0RO pmon_dat_count [41:32]Increments for each valid read data beat while running. Seethe Performance Monitor Control register (0xC0) bits Clearand Auto for clearing.IRQ Block Registers (0x2)The IRQ Block registers are described in this section.Table 78: IRQ Block Register SpaceAddress (hex)Register Name0x00IRQ Block Identifier (0x00)0x04IRQ Block User Interrupt Enable Mask (0x04)0x08IRQ Block User Interrupt Enable Mask (0x08)0x0C IRQ Block User Interrupt Enable Mask (0x0C)0x10IRQ Block Channel Interrupt Enable Mask (0x10)0x14IRQ Block Channel Interrupt Enable Mask (0x14)0x18IRQ Block Channel Interrupt Enable Mask (0x18)0x40IRQ Block User Interrupt Request (0x40)0x44IRQ Block Channel Interrupt Request (0x44)0x48IRQ Block User Interrupt Pending (0x48)0x4C IRQ Block Channel Interrupt Pending (0x4C)0x80IRQ Block User Vector Number (0x80)0x84IRQ Block User Vector Number (0x84)0x88IRQ Block User Vector Number (0x88)0x8C IRQ Block User Vector Number (0x8C)Table 97: Config Block Identifier (0x00) (cont'd)Bit Index Default Access Type Description 19:164’h3RO Config identifier15:88’h0RO Reserved7:08'h04RO Version8'h01: 2015.3 and 2015.48'h02: 2016.18'h03: 2016.28'h04: 2016.38'h05: 2016.48'h06: 2017.1 to current releaseConfig Block BusDev (0x04)Table 98: Config Block BusDev (0x04)Bit Index Default Access Type Description[15:0]PCIe IP RO bus_devBus, device, and functionConfig Block PCIE Max Payload Size (0x08)Table 99: Config Block PCIE Max Payload Size (0x08)Bit Index Default Access Type Description[2:0]PCIe IP RO pcie_max_payloadMaximum write payload size. This is the lesser of the PCIe IPMPS and DMA/Bridge Subsystem for PCIe parameters.3'b000: 128 bytes3'b001: 256 bytes3'b010: 512 bytes3'b011: 1024 bytes3'b100: 2048 bytes3'b101: 4096 bytes。
FPGA可编程逻辑器件芯片XCVU3P-2FLGA2104I中文规格书
DS635 (v2.0) September 9, 2009Product SpecificationClock Buffer/Multiplexer Switching Characteristics 18 x 18 Embedded Multiplier TimingTable 23: Clock Distribution Switching Characteristics DescriptionSymbol MaximumUnits -4 Speed Grade Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to O-output delayT GIO 1.46ns Global clock multiplexer (BUFGMUX) select S-input setup to I0 and I1 inputs. Same as BUFGCE enable CE-inputT GSI 0.63ns Frequency of signals distributed on global buffers (all sides)F BUFG 311MHz Table 24: 18 x 18 Embedded Multiplier Timing SymbolDescription -4 Speed GradeUnitsMin Max Combinatorial DelayT MULT Combinatorial multiplier propagation delay from the A and B inputs tothe P outputs, assuming 18-bit inputs and a 36-bit product (AREG, BREG, and PREG registers unused)- 4.88(1)ns Clock-to-Output TimesT MSCKP_PClock-to-output delay from the active transition of the CLK input to valid data appearing on the P outputs when using the PREG register (2)- 1.10ns T MSCKP_AT MSCKP_BClock-to-output delay from the active transition of the CLK input to valid data appearing on the P outputs when using either the AREG or BREG register (3)- 4.97ns Setup TimesT MSDCK_P Data setup time at the A or B input before the active transition at theCLK when using only the PREG output register (AREG, BREG registers unused)(2)3.98-ns T MSDCK_A Data setup time at the A input before the active transition at the CLK when using the AREG input register (3)0.23-ns T MSDCK_BData setup time at the B input before the active transition at the CLK when using the BREG input register (3)0.39-ns Hold TimesT MSCKD_P Data hold time at the A or B input before the active transition at the CLKwhen using only the PREG output register (AREG, BREG registers unused)(2)-0.97T MSCKD_A Data hold time at the A input before the active transition at the CLK when using the AREG input register (3)0.04T MSCKD_B Data hold time at the B input before the active transition at the CLK when using the BREG input register (3)0.05DS635 (v2.0) September 9, 2009Product SpecificationDigital Clock Manager TimingFor specification purposes, the DCM consists of three keycomponents: the Delay-Locked Loop (DLL), the Digital Fre-quency Synthesizer (DFS), and the Phase Shifter (PS).Aspects of D LL operation play a role in all D CM applica-tions. All such applications inevitably use the CLKIN and theCLKFB inputs connected to either the CLK0 or the CLK2Xfeedback, respectively. Thus, specifications in the D LLtables (T able 26 and T able 27) apply to any application thatonly employs the D LL component. When the D FS and/orthe PS components are used together with the DLL, thenthe specifications listed in the DFS and PS tables (Table 28through Table 31) supersede any corresponding ones in theDLL tables. DLL specifications that do not change with theaddition of DFS or PS functions are presented in Table 26and Table 27.Period jitter and cycle-cycle jitter are two of many differentways of specifying clock jitter. Both specifications describestatistical variation from a mean value.Period jitter is the worst-case deviation from the ideal clockperiod over a collection of millions of samples. In a histo-gram of period jitter, the mean value is the clock period.Cycle-cycle jitter is the worst-case difference in clock periodbetween adjacent clock cycles in the collection of clock peri-ods sampled. In a histogram of cycle-cycle jitter, the meanvalue is zero.Spread SpectrumD CMs accept typical spread spectrum clocks as long asthey meet the input requirements. The DLL will track the fre-quency changes created by the spread spectrum clock todrive the global clocks to the FPGA logic. See XAPP469,Spread-Spectrum Clocking Reception for Displaysfor details.Clock TimingT BPWHHigh pulse width of the CLK signal 1.59-ns T BPWL Low pulse width of the CLK signal 1.59-ns Clock FrequencyF BRAM Block RAM clock frequency. RAM read output value written backinto RAM, for shift registers and circular buffers. Write-only orread-only performance is faster.0230MHzNotes:1.The numbers in this table are based on the operating conditions set forth in Table 6.Table 25: Block RAM Timing (Continued)SymbolDescription -4 Speed GradeUnits Min Max。
FPGA可编程逻辑器件芯片XCVU9P-2PLGA2104E中文规格书
DS635 (v2.0) September 9, 2009Product SpecificationPhase ShifterTable 29: Switching Characteristics for the DFS SymbolDescription Device -4 Speed GradeUnitsMin Max Output Frequency RangesCLKOUT_FREQ_FXFrequency for the CLKFX and CLKFX180 outputs All 5311MHz Output Clock Jitter (2,3)CLKOUT_PER_JITT_FX Period jitter at the CLKFX and CLKFX180outputs All Typ Max CLKIN <20 MHzSee Note 4ps CLKIN > 20 MHz ±[1% of CLKFX period +100]±[1% of CLKFX period +200]ps Duty Cycle (5,6)CLKOUT_DUTY_CYCLE_FX Duty cycle precision for the CLKFX and CLKFX180 outputs,including the BUFGMUX and clock tree duty-cycle distortion All -±[1% of CLKFXperiod+400]ps Phase Alignment (6)CLKOUT_PHASE_FX Phase offset between the DFS CLKFX output and the DLL CLK0 output when both the DFS and DLL are used All -±200ps CLKOUT_PHASE_FX180Phase offset between the DFS CLKFX180 output and the DLL CLK0 output when both the DFS and DLL are used All -±[1% ofCLKFXperiod+300]ps Lock Time LOCK_FX (2)The time from deassertion at the DCM’s Reset input to the rising transition at its LOCKED output. The DFS asserts LOCKED when the CLKFX and CLKFX180 signalsare valid. If using both the DLL and the DFS,use the longer locking time. 5 MHz < F CLKIN < 15 MHz All -5ms F CLKIN > 15 MHz -450μsNotes:1.The numbers in this table are based on the operating conditions set forth in Table 6 and T able 28.2.For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.3.Maximum output jitter is characterized within a reasonable noise environment (150 ps input period jitter, 40 SSOs and 25% CLB switching). Output jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB utilization, CLB switching activities, switching frequency, power supply and PCB design. The actual maximum output jitter depends on the system application.e the Spartan-3A Jitter Calculator to estimate DFS output jitter. Use the Clocking Wizard to determine jitter for a specific design.5.The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.6.Some duty-cycle and alignment specifications include 1% of the CLKFX output period or 0.01 UI. Example: The data sheet specifies a maximum jitter of “±[1% of CLKFX period + 300]”. Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 300 ps] = ±400 ps.Table 30: Recommended Operating Conditions for the PS in Variable Phase ModeSymbolDescription -4 Speed GradeUnitsMin Max Operating Frequency RangesPSCLK_FREQ(F PSCLK )Frequency for the PSCLK input 1167MHz Input Pulse RequirementsPSCLK_PULSE PSCLK pulse width as a percentage of the PSCLK period 40%60%-DS635 (v2.0) September 9, 2009Product SpecificationConfiguration and JTAG TimingTable 33: Power-On Timing and the Beginning of Configuration SymbolDescription Device -4 Speed GradeUnits Min Max T POR (2)The time from the application of V CCINT , V CCAUX , and V CCOBank 2 supply voltage ramps (whichever occurs last) to therising transition of the INIT_B pin XA3S100E -5ms XA3S250E-5ms XA3S500E-5ms XA3S1200E-5ms XA3S1600E-7ms T PROGThe width of the low-going pulse on the PROG_B pin All 0.5-μs T PL (2)The time from the rising edge of the PROG_B pin to therising transition on the INIT_B pin XA3S100E -0.5ms XA3S250E-0.5ms XA3S500E-1ms XA3S1200E-2ms XA3S1600E-2ms T INITMinimum Low pulse width on INIT_B output All 250-ns T ICCK (3)The time from the rising edge of the INIT_B pin to thegeneration of the configuration clock signal at the CCLKoutput pin All 0.5 4.0μsNotes:1.The numbers in this table are based on the operating conditions set forth in Table 6. This means power must be applied to all V CCINT , V CCO ,and V CCAUX lines.2.Power-on reset and the clearing of configuration memory occurs during this period.3.This specification applies only to the Master Serial, SPI, BPI-Up, and BPI-Down modes.。
FPGA可编程逻辑器件芯片XCVU160-2FLGB2104E中文规格书
Soldering GuidelinesSoldering GuidelinesTo implement and control the production of surface-mount assemblies, the dynamics of the Pb-free solder reflow process and how each element of the process is related to the end result must be thoroughly understood.The primary phases of the Pb-free reflow process are:•Melting the particles in the solder paste•Wetting the surfaces to be joined•Solidifying the solder into a strong metallurgical bondThe peak reflow temperature of a plastic surface-mount component (PSMC) body should not be more than 250°C maximum (260°C for dry rework only) for Pb-free packages (220°C for eutectic packages), and is package size dependent. For multiple BGAs in a single board and because of surrounding component differences, Xilinx recommends checking all BGA sites for varying temperatures.The infrared reflow (IR) process is strongly dependent on equipment and loading.Components might overheat due to lack of thermal constraints. Unbalanced loading can lead to significant temperature variation on the board. These guidelines are intended to assist users in avoiding damage to the components; the actual profile should bedetermined by those using these guidelines. For complete information on packagemoisture / reflow classification and package reflow conditions, refer to the Joint IPC/JEDEC Standard J-STD-020C.Conformal CoatingXilinx does not have information regarding the reliability of flip-chip BGA packages on a board after exposure to any specific conformal coating process. Therefore, any process using conformal coating should be qualified for the specific use case to cover the materials and process steps.Ruggedized XQ packages are designed to support conformal coating, with vented lids that ensure proper cleaning can occur after the etching process and prior to conformal coating.Solder PasteSolder paste consists of solder alloy and a flux system. A typical solder paste composition by volume is split between about 50% alloy and 50% flux. The metal load mass (solder alloy powder) is around 90%, with the remaining 10% mass a flux system. The primary purpose of the flux system is to remove the contaminations from the solder joints during the soldering process. The capability of removing contaminations is determined by the activation level of the type of solder paste. The preferred solder paste metal alloy has a lead-free composition (SnAgCu where Ag is 3–4% and Cu is 0.5–1%). A no-clean solder paste is preferred to eliminate any risk of improper cleaning that could leave active residue beneath the device and other BTC components. The paste must be suitable for printing the solder stencil aperture dimensions. Type 4 paste is recommended for better paste release performance. When using a solder paste, you must adhere to the handling recommendations of the paste manufacturer.Component PlacementXilinx device packages must be placed accurately according to their geometry outline. Positioning packages manually via hand mounting is not recommended.Typical component placement accuracies of ±50 μm can be achieved using standard pick and placement machine equipment with vision system. The PCB and the components are optically checked and measured and the components are placed on the PCB in specific programmed positions based on the PCB CAD information. The pick and placement machine vision system detects the fiducials on the PCB immediately prior to mounting the FPGA. Recognition of the packages is performed by the vision system, to ensure correct centering of the FPGA placement on the PCB pad array.BGA packages with solder balls can self-align during the reflow process because of the solder high surface tension that enables the pulling and centering of the device, and where a slight offset of the placement is still allowed. For guidance, the maximum tolerable offset of device placement is around 30% of the pad diameter on the PCB for typical non-solder mask defined pads. This means that for device packages the solder ball to PCB pad misalignment must be better than 150μm to assure a robust mounting process. Generally, this is achievable using a wide range of modern pick and placement systems. The following setup conditions are important for the pick and placement systems:•The pick and placement nozzle type should be sized to the dimensions of the Xilinx device. The nozzle needs to firmly hold the device package during the pick andplacement stage. The appropriate nozzle type for the device package can be chosen from the manual provided by the pick and placement equipment company.•The ball recognition capabilities of the placement system should be used and package outline centering should be avoided. This eliminates the solder ball to package edge tolerances of the package. Refer to the specific package outline drawing for details.•To ensure the proper identification of the device package by the vision system, a suitable lighting system and the correct choice of the features of the measuringmethod are essential. The most suitable settings can be chosen from the manualprovided by the pick and placement equipments company.•To avoid solder bridging or solder smear, ensure the proper placement force of the device package during placement on the PCB. Excessive placement force can lead to excess solder paste and cause solder bridging. However, a slight placement force can lead to insufficient solder paste contact between the device package solder balls and the solder paste, causing solder defects including open solder joints, badly centered packages, or even head-in-pillow (HIP) defects.。
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Chapter1 Packaging Overview
Introduction to the UltraScale Architecture
The Xilinx® UltraScale™ architecture is the first ASIC-class architecture to enable
multi-hundred gigabit-per-second levels of system performance with smart processing,
while efficiently routing and processing data on-chip. UltraScale architecture-based devices address a vast spectrum of high-bandwidth, high-utilization system requirements by using industry-leading technical innovations, including next-generation routing, ASIC-like
clocking, 3D-on-3D ICs, multiprocessor SoC (MPSoC) technologies, and new power
reduction features. The devices share many building blocks, providing scalability across
process nodes and product families to leverage system-level investment across platforms.
Virtex® UltraScale+™ devices provide the highest performance and integration capabilities in a FinFET node, including both the highest serial I/O and signal processing bandwidth, as well as the highest on-chip memory density. As the industry's most capable FPGA family, the Virtex UltraScale+ devices are ideal for applications including 1+Tb/s networking and data center and fully integrated radar/early-warning systems.
Virtex UltraScale devices provide the greatest performance and integration at 20nm,
including serial I/O bandwidth and logic capacity. As the industry's only high-end FPGA at the 20nm process node, this family is ideal for applications including 400G networking, large scale ASIC prototyping, and emulation.
Kintex® UltraScale+ devices provide the best price/performance/watt balance in a FinFET node, delivering the most cost-effective solution for high-end capabilities, including
transceiver and memory interface line rates as well as 100G connectivity cores. Our newest mid-range family is ideal for both packet processing and DSP-intensive functions and is well suited for applications including wireless MIMO technology, Nx100G networking, and data center.
Kintex UltraScale devices provide the best price/performance/watt at 20nm and include the highest signal processing bandwidth in a mid-range device, next-generation
transceivers, and low-cost packaging for an optimum blend of capability and
cost-effectiveness. The family is ideal for packet processing in 100G networking and data centers applications as well as DSP-intensive processing needed in next-generation medical imaging, 8k4k video, and heterogeneous wireless infrastructure.
Gigabit Transceiver Channels by Device/Package
Table 1-2 lists the quantity of gigabit transceiver channels for the UltraScale and
UltraScale+ devices. In all devices, a gigabit transceiver channel is one set of MGTRXP, MGTRXN, MGTTXP, and MGTTXN pins. For transceiver data rate limitations on specific device/package combinations, see the specific UltraScale and UltraScale+ device data sheets [Ref 4].FSVA3824SSI, flip-chip, fine-pitch, lidless with stiffener ring BGA 1.065x 65FSVB3824
SSI, flip-chip, fine-pitch, lidless with stiffener ring
BGA
1.0
65x 65
Notes:
1.FFV, FLV, and FLG packages are footprint compatible when the package code letter designator and pin count are identical.See UltraScale Architecture and Product Overview (DS890) [Ref 1] for specific letter codes and ordering code information.
2.These 52.5x 52.5 packages have the same PCB ball footprint as the 47.5x 47.5 packages and are footprint compatible.
Table 1-1:
Package Specifications (Cont’d)
Packages (1)
Description
Package Specifications
Package Type Pitch (mm)
Size (mm)
Table 1-2:
Serial Transceiver Channels (GTH/GTY) by Device/Package
Device
Package
GTH Channels
GTY Channels
Kintex UltraScale Devices
XCKU035FBVA676160XCKU040160XCKU035SFVA78480XCKU04080XCKU035FBVA900
160XCKU040160XCKU025FFVA1156
120XCKU03516
0XCKU040200XCKU060280XCKU09520
8XCKU060FFVA1517320XCKU085FLVA1517480XCKU115480XCKU095FFVC15172020XCKU115FLVD1517640XCKU095
FFVB1760
32
16
XQVU3P FFRC1517040XQVU7P FLRA2104052XQVU7P FLRB2104076XQVU11P
FLRC2104
96
Device
Package GTH Channels GTY Channels GTM Channels
Virtex UltraScale+ Devices
XCVU27P FIGD2104
01630XCVU29P 01630XCVU27P FSGA2577
03248XCVU29P
32
48
Device
Package GTH Channels
GTY Channels。