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10000 MPS 专卖店正品现货
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针对dsPIC33F和PIC24H的开发板Microstick

本设计以切换电路为控制核心，制升压型电路和降压控
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龙晟电子 FORESEE eMMC FSEIASOD-16G 数据手册说明书

FORESEE eMMC FSEIASOD-16G DatasheetVersion: 1.02019.05.31LONGSYS ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATIONAND SPECIFICATIONS WITHOUT NOTICE.Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an “AS IS ” basis, without warranties of any kind.This document and all information discussed herein remain the sole and exclusive property of Longsys Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other-wise.Longsys products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.For updates or additional information about Longsys products, contact your nearest Longsys office.All brand names, trademarks and registered trademarks belong to their respective owners.ⓒ 2018 Shenzhen Longsys Electronics Co., Ltd. All rights reserved.L on gs ysc on fi de nt ia l,F or 宏景on lyL on gs ysc on fi de nt ia l,F or宏景on lyCONTENTS1. Introduction .......................................................................................................................... 1 2. Product List ........................................................................................................................... 1 3. Features ................................................................................................................................ 1 4. Functional Description .. (2)5. Product Specifications (3)5.1 Performance........................................................................................................................ 3 5.2 Power Consumption ............................................................................................................. 3 6. Pin Assignments .................................................................................................................... 4 6.1 Ball Array view .................................................................................................................... 4 6.2 Ball Array view .. (5)7. Usage Overview (6)7.1 General description .............................................................................................................. 6 7.2 Partition Management .......................................................................................................... 6 7.3 Automatic Sleep Mode .......................................................................................................... 8 7.4 Sleep (CMD5) . (8)7.5 H/W Reset operation (9)7.6 High-speed mode selection (9)7.7 Bus width selection .............................................................................................................. 9 7.8 Partition configuration .......................................................................................................... 9 7.9 CID register ........................................................................................................................ 9 7.10 CSD register .. (10)7.11 Extended CSD register (11)7.12 OCR Register ................................................................................................................... 22 7.13 Field firmware update(FFU) ............................................................................................... 23 7.14 S.M.A.R.T. Health Report .. (24)8. Package Dimension .............................................................................................................. 25 9 Connection Guide .................................................................................................................. 25 9.1 Schematic Diagram ............................................................................................................ 25 10. Processing Guide (26)L on gs ysc on fi de nt ia l,F or宏景on lyRev. 1.0FSEIASOD-16G1. IntroductionFORESEE eMMC is an embedded storage solution designed in the BGA package. The FORESEE eMMC consists of NAND flash and eMMC controller. The controller could manage the interface protocols ，wear-leveling ，bad block management and ECC.FORESEE eMMC has high performance at a competitive cost, high quality and low power consumption, and eMMC is compatible with JEDEC standard eMMC 5.1 specifications.3. FeatureseMMC5.1 specification compatibility (Backward compatible to eMMC4.41/4.5/5.0)Bus mode- Data bus width: 1 bit (default), 4 bits, 8 bits- Data transfer rate: up to 400MB/s (HS400)- MMC I/F Clock frequency : 0~200MHzOperating voltage range - Vcc(NAND) : 2.7 - 3.6V- Vccq(Controller) : 1.7 - 1.95V / 2.7 - 3.6VTemperature- Operation (-30℃ ~ +85℃) - Storage without operation (-40℃ ~ +85℃) Sudden-Power-Loss safeguardHardware ECC engineUnique firmware backup mechanism Global-wear-levelingSupported features. -HS400, HS200- Partitioning, RPMB- Boot feature, boot partition - HW Reset/SW Reset- Discard, Trim, Erase, Sanitize - Background operations, HPI - Enhanced reliable write - S.M.A.R.T. Health Report - FFU- Sleep / awakeOthers- Compliance with the RoHS DirectiveL on gs ysc on fi de nt ia l,F or宏y4. Functional DescriptionFORESEE eMMC with powerful L2P (Logical to Physical) NAND Flash management algorithm provides unique functions: Host independence from details of operating NAND flash Internal ECC to correct defect in NAND flashSudden-Power-Loss safeguardTo prevent from data loss, a mechanism named Sudden-Power-Loss safeguard is added in the eMMC. In the case of sudden power-failure, the eMMC would work properly after power cycling.Global-wear-levelingTo achieve the best stability and device endurance, this eMMC equips the Global Wear Leveling algorithm. It ensures that not only normal area, but also the frequently accessed area, such as FAT, would be programmed and erased evenly.IDA(Initial Data Acceleration)The eMMC prevents the pre-burned data from data-loss with IDA, in case of our customer had pre-burned data to eMMC, before the eMMC being SMT.CacheThe eMMC enhanced the data written performance with Cache, with which our customer would getmore endurance and reliability.DEVICE TYPEL on gs ysc F or宏景on ly5. Product Specifications• Test Condition: Bus width x8, 200MHz DDR, 512KB data transfer , w/o file system overhead, measuredon internal board• Test tool: uBOOT (Without O/S) • Chunk size: 1MB• Test area: 100MB/ Full-range of LBA.5.2 Power Consumption5.2.1 Active power consumption during operation• Vcc:3.3V & Vccq ：1.8V .• The measurement for max RMS current is the average RMS current consumption over a period of 100ms.5.2.2 Low power mode (stand-by)• Standby: Nand Vcc & Controller Vccq power supply is switched on.• The measurement for max RMS current is the average RMS current consumption over a period of 100ms.5.2.3 Low power mode (sleep)• Sleep: Nand Vcc power supply is switched off(Controller Vccq on)• The measurement for max RMS current is the average RMS current consumption over a period of 100ms.L on gs ysc oe nt iF oron ly6. Pin Assignments6.1 Ball Array viewFBGA153 - Ball Array (Top View through package)L on gs ysc on fi de nt ia l,F or宏景on lyNote: NC: No Connect, shall be connected to ground or left floating.RFU: Reserved for Future Use, must be left floating for future use. VSF: Vendor Specific Function, must be left floating.L on gs ys7.1 General descriptionThe eMMC can be operated in 1, 4, or 8-bit mode. NAND flash memory is managed by a controller inside, which manages ECC, wear leveling and bad block management. The eMMC provides easy integration with the host process that all flash management hassles are invisible to the host.7.2 Partition ManagementThe embedded device offers also the possibility of configuring by the host additional split local memory partitions with independent addressable space starting from logical address 0x00000000 for differentusage models. Default size of each Boot Area Partition is 4096 KB and can be changed by Vendor Command as multiple of 128KB. Boot area partition size is calculated as ( 128KB * BOOT_SIZE_MULTI ) The size of Boot Area Partition 1 and 2 cannot be set independently and is set as same value Boot area partition which is enhanced partition. Therefore memory block area scan is classified as follows:Factory configuration supplies boot partitions.The RPMB partition is 4MB.The host is free to configure one segment in the User Data Area to be implemented as enhancedstorage media, and to specify its starting location and size in terms of Write Protect Groups. The attributes of this Enhanced User Data Area can be programmed only once during the device life-cycle (one-time programmable).Up to four General Purpose Area Partitions can be configured to store user data or sensitive data, or for other host usage models. The size of these partitions is a multiple of the write protect group. Size and attributes can be programmed once in device life-cycle (one-time programmable). Each of the General Purpose Area Partitions can be implemented with enhanced technological features. L on gs ysc on fi de nt ia l,F or宏景on lyPartitions and user data area configuration(The size of RPMB area partition is 4MB)In boot operation mode, the master can read boot data from the slave (device) by keeping CMD line low or sending CMD0 with argument + 0xFFFFFFFA, before issuing CMD1. The data can be read from either boot area or user area depending on register setting.State diagram (boot mode)State diagram (alternative boot mode)L on gs ysc on fi de nt ia宏景on lyState diagram (boot mode)*7.3 Automatic Sleep ModeIf host does not issue any command during certain duration (1s), after previously issued command is completed, the device enters “Power Saving mode” to reduce power consumption. At this time, commandsarriving at the device while it is in power saving mode will be serviced in normal fashion. The below table explains the condition to enter and exit Auto Power Saving Mode7.4 Sleep (CMD5)A card may be switched between a Sleep state and a Standby state by SLEEP/AWAKE (CMD5). In theSleep state the power consumption of the memory device is minimized. In this state the memory devicereacts only to the commands RESET (CMD0 with argument of either 0x00000000 or 0xF0F0F0F0 or H/W reset) and SLEEP/AWAKE (CMD5). All the other commands are ignored by the memory device. The timeout for state transitions between Standby state and Sleep state is defined in the EXT_CSD register S_A_timeout. The maximum current consumptions during the Sleep state are defined in the EXT_CSD registers S_A_VCC and S_A_VCCQ. Sleep command: The bit 15 as set to 1 in SLEEP/ AWAKE (CMD5) argument. A wake command: The bit 15 as set to 0 in SLEEP/AWAKE (CMD5) argument.L on gs ysc on fi de nt ia l,F or宏景on ly7.5 H/W Reset operationDevice will detect the rising edge of RST_n signal to trigger internal reset sequenceH/W reset waveform7.6 High-speed mode selectionAfter the host verifies that the card complies with version 4.0, or higher, of this standard, it has to enable the high speed mode timing in the card, before changing the clock frequency to a frequency higher than 20MHz. For the host to change to a higher clock frequency, it has to enable the high speed interface timing. The host uses the SWITCH command to write 0x01 to the HS_TIMING byte, in the Modes segmentof the EXT_CSD register.7.7 Bus width selectionAfter the host has verified the functional pins on the bus it should change the bus width configurationaccordingly, using the SWITCH command. The bus width configuration is changed by writing to the BUS_WIDTH byte in the Modes Segment of the EXT_CSD register (using the SWITCH command to do so).After power-on, or software reset, the contents of the BUS_WIDTH byte is 0x00.7.9 CID registerThe Card Identification (CID) register is 128 bits wide. It contains the card identification information used during the card identification phase (protocol). Every individual flash or I/O card shall have an unique identification number. Every type of ROM cards (defined by content) shall have a unique identification L on gi de nt ia l,F or宏景on ly7.10 CSD registerThe Card-Specific Data (CSD) register provides information on how to access the card contents. The CSD defines the data format, error correction type, maximum data access time, data transfer speed, whetherthe DSR register can be used etc. The programmable part of the register (entries marked by W or E, see景on7.11 Extended CSD registerThe Extended CSD register defines the card properties and selected modes. It is 512 bytes long. The most significant 320 bytes are the Properties segment, which defines the card capabilities and cannot be modified by the host. The lower 192 bytes are the Modes segment, which defines the configuration theor宏Notes: 1.R= Read-onlyR/W=One-Time Programmable and readableR/W/E=Multiple writable with value kept after a power cycle, assertion of the RST_n signal, and anyCMD0 reset, and readableTBD=T o Be Defined. 2. Reserved bits should be read as 0.7.12 OCR RegisterThe 32-bit operation conditions register stores the VCCQ voltage profile of the eMMC. In addition, this register includes a status information bit. This status bit is set if the eMMC power up procedure has beenNote*: This bit is set to LOW if the eMMC has not finished the power up routine. The supported voltage range is coded as shown in table.c on fi de nt i7.13 Field firmware update(FFU)To download a new firmware, the controller requires instruction sequence following JEDEC standard. Longsys eMMC only supports Manual mode (MODE_OPERATION_CODES is not supported). For more details, refer to the App note.SUPPORTED_MODE[493] (Read Only)BIT[0] : ‘0’ FFU is not supported by the device.‘1’ FFU is supported by the device.BIT[1] : ‘0’ Vendor specific mode (VSM) is not supported by the device.FFU_FEATURE[492] (Read Only)BIT[0] : ‘0’ Device does not support MODE_OPERATION_CODES field (Manual mode)FFU_ARG[490-487] (Read Only)Using this field the device reports to the host which value the host should set as an argument for read and write commands in FFU mode.n gs i de ntFW_CONFIG[169] (R/W) BIT[0] : Update disable0x0 : FW updates enabled.FFU_STATUS[26] (R/W/E_P)OPERATION_CODES_TIMEOUT[491](Read Only)Maximum timeout for the SWITCH command when setting a value to the MODE_OPERATION_CODESMODE_OPERATION_CODES[29] (W/E_P)The host sets the operation to be performed at the selected mode, in case MODE_CONFIGS is set to7.14 S.M.A.R.T. Health ReportS.M.A.R.T . is a monitoring system that detects and reports on various indicators of eMMCreliability(Including original bad blocks, increased bad blocks, power-up number , power-loss counts and etc), with the intent of enabling the anticipation of hardware failures. We may be able to use recorded S.M.A.R.T . data to discover where the faults lie, ensure how to solve the problems and prevent them from recurring in future eMMC designs (For details, please refer to app note).Lc ot ia on ly8. Package Dimension11.5mm x 13.0mm x 1.0mm Package Dimension9 Connection Guide9.1 Schematic DiagramCoupling capacitor should be connected with VCC/VCCQ and VSS as closely as possible. The resistance on the CLK line is highly recommended (0Ω by default). 0Ω~100Ω is also available.LONGSYS recommends to separate VCC and VCCQ power.VDDi Capacitor is min 0.1uF.LONGSYS recommends lay the VSS between the CLK and the Data lines.The resistance on the CLK line is highly recommended (0Ω by default)L on gs ysc on fi de nt ia l,F or宏景on ly10. Processing GuideIt is recommended to follow the instructions of Moisture Sensitivity Level 3.In the case of Pre-burn before SMT , It is highly recommended to limit the size of data pre-burned to the eMMC ，please contact your agency for more information. The amount of data pre-burned (data written before SMT) is limited, it should be managed properly.L on gs ysc on fi de nt ia l,F or宏景on ly。

MicroChip PIC24FJ256DAXXX宣传资料

更智能，更好，更小使用新的集成MCU和设计工具在将来的设计中添加丰富且用户友好的图形界面__________________________________________________________________________________Lee K. KohAMAD市场部Microchip Technology Inc.现在，无论是机械开关上的图形覆盖物还是触摸传感图形显示屏上的“软”按钮，使用图标和图形菜单均为实现用户界面的首选方法。

简单地说，图形用户界面可以使产品更易于上手、更吸引用户，并有助于OEM提升价值并彰显个性。

有诸多理由可以说明使用图像代替或补充文本很有道理，不仅是因为它可以打破语言障碍或消除对专业知识的要求。

用户现在期待图形界面的进步，不仅改善产品的外观而且便于产品的使用；这也是OEM渴望满足的愿望。

这推动了对以下解决方案的需求，即技术和商业均可行且简单但具有所需功能的图形解决方案。

Microchip为用户开发产品提供咨询，其高质量和完善的软件/硬件实现方案意味着它将不断提供必要的集成和功能水平，以满足市场需求。

例如，为了响应对更直观更吸引人的用户界面日益增长的需求，Microchip已经开发了一系列PIC®单片机，提供一个完全集成的、具有竞争力的解决方案来实现图形用户界面，并支持交付完整的系统解决方案。

市场发展消费、工业和汽车市场均呈现出对显示屏的更大需求，因而电子行业中此类产品也在不断增多，这通常会导致价格迅速下降。

其净效应是技术的快速进步，因而掀起了显示屏在技术价格先前让人望而却步的应用中使用的浪潮。

虽然这将有力地打开现有显示屏技术的新市场，但只有在整体系统解决方案仍能满足目标市场的商业规范时才能抓住这个机会。

就LCD技术而言，显示屏不是惟一要考虑的因素；驱动显示屏需要一个更强大的处理器和其他元件，例如，图形显示控制器和额外的存储器。

除了额外的硬件需求，与显示屏和图形元素相关的软件复杂度也明显上升。

常用电源芯片大全

常用电源芯片大全-CAL-FENGHAI.-(YICAI)-Company One1常用电源芯片大全第1章DC-DC电源转换器/基准电压源DC-DC电源转换器1.低噪声电荷泵DC-DC电源转换器AAT3113/AAT31142.低功耗开关型DC-DC电源转换器ADP30003.高效3A开关稳压器AP15014.高效率无电感DC-DC电源转换器FAN56605.小功率极性反转电源转换器ICL76606.高效率DC-DC电源转换控制器IRU30377.高性能降压式DC-DC电源转换器ISL64208.单片降压式开关稳压器L49609.大功率开关稳压器L4970A降压式开关稳压器L4971高效率单片开关稳压器L4978高效率升压/降压式DC-DC电源转换器L5970降压式DC-DC电源转换器LM157214.高效率1A降压单片开关稳压器LM1575/LM2575/LM2575HV 降压单片开关稳压器LM2576/LM2576HV16.可调升压开关稳压器LM2577降压开关稳压器LM259618.高效率5A开关稳压器LM267819.升压式DC-DC电源转换器LM2703/LM270420.电流模式升压式电源转换器LM273321.低噪声升压式电源转换器LM275022.小型75V降压式稳压器LM500723.低功耗升/降压式DC-DC电源转换器LT107324.升压式DC-DC电源转换器LT161525.隔离式开关稳压器LT172526.低功耗升压电荷泵LT175127.大电流高频降压式DC-DC电源转换器LT176528.大电流升压转换器LT193529.高效升压式电荷泵LT193730.高压输入降压式电源转换器LT1956升压式电源转换器LT196132.高压升/降压式电源转换器LT343333.单片3A升压式DC-DC电源转换器LT343634.通用升压式DC-DC电源转换器LT346035.高效率低功耗升压式电源转换器LT3464升压式DC-DC电源转换器LT346737.大电流高效率升压式DC-DC电源转换器LT378238.微型低功耗电源转换器LTC1754单片同步降压式稳压器LTC187540.低噪声高效率降压式电荷泵LTC191141.低噪声电荷泵LTC3200/LTC3200-542.无电感的降压式DC-DC电源转换器LTC325143.双输出/低噪声/降压式电荷泵LTC325244.同步整流/升压式DC-DC电源转换器LTC340145.低功耗同步整流升压式DC-DC电源转换器LTC340246.同步整流降压式DC-DC电源转换器LTC340547.双路同步降压式DC-DC电源转换器LTC340748.高效率同步降压式DC-DC电源转换器LTC341649.微型2A升压式DC-DC电源转换器LTC3426两相电流升压式DC-DC电源转换器LTC342851.单电感升/降压式DC-DC电源转换器LTC344052.大电流升/降压式DC-DC电源转换器LTC3442同步升压式DC-DC电源转换器LTC345854.直流同步降压式DC-DC电源转换器LTC370355.双输出降压式同步DC-DC电源转换控制器LTC373656.降压式同步DC-DC电源转换控制器LTC377057.双2相DC-DC电源同步控制器LTC380258.高性能升压式DC-DC电源转换器MAX1513/MAX151459.精简型升压式DC-DC电源转换器MAX1522/MAX1523/MAX152460.高效率40V升压式DC-DC电源转换器MAX1553/MAX155461.高效率升压式LED电压调节器MAX1561/MAX159962.高效率5路输出DC-DC电源转换器MAX156563.双输出升压式DC-DC电源转换器MAX1582/MAX1582Y64.驱动白光LED的升压式DC-DC电源转换器MAX158365.高效率升压式DC-DC电源转换器MAX1642/MAX1643降压式开关稳压器MAX164467.高效率升压式DC-DC电源转换器MAX1674/MAX1675/MAX167668.高效率双输出DC-DC电源转换器MAX167769.低噪声1A降压式DC-DC电源转换器MAX1684/MAX168570.高效率升压式DC-DC电源转换器MAX169871.高效率双输出降压式DC-DC电源转换器MAX171572.小体积升压式DC-DC电源转换器MAX1722/MAX1723/MAX172473.输出电流为50mA的降压式电荷泵MAX173074.升/降压式电荷泵MAX175975.高效率多路输出DC-DC电源转换器MAX1800同步整流降压式稳压型MAX1830/MAX183177.双输出开关式LCD电源控制器MAX187878.电流模式升压式DC-DC电源转换器MAX189679.具有复位功能的升压式DC-DC电源转换器MAX194780.高效率PWM降压式稳压器MAX1992/MAX199381.大电流输出升压式DC-DC电源转换器MAX61882.低功耗升压或降压式DC-DC电源转换器MAX629升压式DC-DC电源转换器MAX668/MAX66984.大电流PWM降压式开关稳压器MAX724/MAX72685.高效率升压式DC-DC电源转换器MAX756/MAX75786.高效率大电流DC-DC电源转换器MAX761/MAX76287.隔离式DC-DC电源转换器MAX8515/MAX8515A88.高性能24V升压式DC-DC电源转换器MAX872789.升/降压式DC-DC电源转换器MC33063A/MC34063A升压/降压/反向DC-DC电源转换器MC33167/MC3416791.低噪声无电感电荷泵MCP1252/MCP125392.高频脉宽调制降压稳压器MIC220393.大功率DC-DC升压电源转换器MIC229594.单片微型高压开关稳压器NCP1030/NCP103195.低功耗升压式DC-DC电源转换器NCP1400A96.高压DC-DC电源转换器NCP140397.单片微功率高频升压式DC-DC电源转换器NCP141098.同步整流PFM步进式DC-DC电源转换器NCP142199.高效率大电流开关电压调器NCP1442/NCP1443/NCP1444/NCP1445 100.新型双模式开关稳压器NCP1501101.高效率大电流输出DC-DC电源转换器NCP1550102.同步降压式DC-DC电源转换器NCP1570103.高效率升压式DC-DC电源转换器NCP5008/NCP5009104.大电流高速稳压器RT9173/RT9173A105.高效率升压式DC-DC电源转换器RT9262/RT9262A106.升压式DC-DC电源转换器SP6644/SP6645107.低功耗升压式DC-DC电源转换器SP6691108.新型高效率DC-DC电源转换器TPS54350109.无电感降压式电荷泵TPS6050x110.高效率升压式电源转换器TPS6101x恒流白色LED驱动器TPS61042112.具有LDO输出的升压式DC-DC电源转换器TPS6112x 113.低噪声同步降压式DC-DC电源转换器TPS6200x 114.三路高效率大功率DC-DC电源转换器TPS75003 115.高效率DC-DC电源转换器UCC39421/UCC39422控制升压式DC-DC电源转换器XC6371117.白光LED驱动专用DC-DC电源转换器XC9116同步整流降压式DC-DC电源转换XC9215/XC9216/XC9217 119.稳压输出电荷泵XC9801/XC9802120.高效率升压式电源转换器ZXLB1600线性/低压差稳压器121.具有可关断功能的多端稳压器BAXXX122.高压线性稳压器HIP5600123.多路输出稳压器KA7630/KA7631124.三端低压差稳压器LM2937125.可调输出低压差稳压器LM2991126.三端可调稳压器LM117/LM317127.低压降CMOS500mA线性稳压器LP38691/LP38693128.输入电压从12V到450V的可调线性稳压器LR8非常低压降稳压器（VLDO）LTC3025130.大电流低压差线性稳压器LX8610负输出低压差线性稳压器MAX1735低压差线性稳压器MAX8875133.带开关控制的低压差稳压器MC33375134.带有线性调节器的稳压器MC33998低压差固定及可调正稳压器NCP1117136.低静态电流低压差稳压器NCP562/NCP563137.具有使能控制功能的多端稳压器PQxx138.五端可调稳压器SI-3025B/SI-3157B低压差线性稳压器SPX2975140.五端线性稳压器STR20xx141.五端线性稳压器STR90xx142.具有复位信号输出的双路输出稳压器TDA8133143.具有复位信号输出的双路输出稳压器TDA8138/TDA8138A 144.带线性稳压器的升压式电源转换器TPS6110x145.低功耗50mA低压降线性稳压器TPS760xx146.高输入电压低压差线性稳压器XC6202147.高速低压差线性稳压器XC6204148.高速低压差线性稳压器XC6209F149.双路高速低压差线性稳压器XC6401基准电压源150.新型XFET基准电压源ADR290/ADR291/ADR292/ADR293 151.低功耗低压差大输出电流基准电压源MAX610x152.低功耗基准电压源MAX6120精密基准电压源MC1403基准电压源MCP1525/MCP1541155.低功耗精密低压降基准电压源REF30xx/REF31xx156.精密基准电压源TL431/KA431/TLV431A第2章AC-DC转换器及控制器1.厚膜开关电源控制器DP104C2.厚膜开关电源控制器DP308P系列高电压功率转换控制器DPA423/DPA424/DPA425/DPA4264.电流型开关电源控制器FA13842/FA13843/FA13844/FA138455.开关电源控制器FA5310/FA5311开关电源控制器FAN75567.绿色环保的PWM开关电源控制器FAN7601型开关电源控制器FS6M07652R9.开关电源功率转换器FS6Sxx10.降压型单片AC-DC转换器HV-2405E11.新型反激准谐振变换控制器ICE1QS01电源功率转换器KA1M088013.开关电源功率转换器KA2S0680/KA2S088014.电流型开关电源控制器KA38xx型开关电源功率转换器KA5H0165R型开关电源功率转换器KA5Qxx型开关电源功率转换器KA5Sxx18.电流型高速PWM控制器L499019.具有待机功能的PWM初级控制器L599120.低功耗离线式开关电源控制器L6590SWITCH TN系列电源功率转换器LNK304/LNK305/LNK306 SWITCH系列电源功率转换器LNK500/LNK501/LNK520 23.离线式开关电源控制器M51995A电源控制器M62281P/M62281FP25.高频率电流模式PWM控制器MAX5021/MAX502226.新型PWM开关电源控制器MC4460427.电流模式开关电源控制器MC4460528.低功耗开关电源控制器MC4460829.具有PFC功能的PWM电源控制器ML482430.液晶显示器背光灯电源控制器ML487631.离线式电流模式控制器NCP120032.电流模式脉宽调制控制器NCP120533.准谐振式PWM控制器NCP120734.低成本离线式开关电源控制电路NCP121535.低待机能耗开关电源PWM控制器NCP1230系列自动电压切换控制开关STR8xxxx37.大功率厚膜开关电源功率转换器STR-F665438.大功率厚膜开关电源功率转换器STR-G865639.开关电源功率转换器STR-M6511/STR-M652940.离线式开关电源功率转换器STR-S5703/STR-S5707/STR-S570841.离线式开关电源功率转换器STR-S6401/STR-S6401F/STR-S6411/STR-S6411F42.开关电源功率转换器STR-S651343.离线式开关电源功率转换器TC33369～TC3337444.高性能PFC与PWM组合控制集成电路TDA16846/TDA1684745.新型开关电源控制器TDA1685046.“绿色”电源控制器TEA1504 447.第二代“绿色”电源控制器TEA150748.新型低功耗“绿色”电源控制器TEA153349.开关电源控制器TL494/KA7500/MB3759SwitchⅠ系列功率转换器TNY253、TNY254、TNY255SwitchⅡ系列功率转换器TNY264P～TNY268GSwitch（Ⅱ）系列离线式功率转换器TOP209～TOP227Switch-FX系列功率转换器TOP232/TOP233/TOP234Switch-GX系列功率转换器TOP242～TOP25055.开关电源控制器UCX84X56.离线式开关电源功率转换器VIPer12AS/VIPer12ADIP57.新一代高度集成离线式开关电源功率转换器VIPer53第3章功率因数校正控制/节能灯电源控制器1.电子镇流器专用驱动电路BL83012.零电压开关功率因数控制器FAN48223.功率因数校正控制器FAN75274.高电压型EL背光驱动器HV826场致发光背光驱动器IMP525/IMP5606.高电压型EL背光驱动器/反相器IMP8037.电子镇流器自振荡半桥驱动器IR21568.单片荧光灯镇流器IR21579.调光电子镇流器自振荡半桥驱动器IR215910.卤素灯电子变压器智能控制电路IR216111.具有功率因数校正电路的镇流器电路IR216612.单片荧光灯镇流器IR216713.自适应电子镇流器控制器IR252014.电子镇流器专用控制器KA754115.功率因数校正控制器L656116.过渡模式功率因数校正控制器L656217.集成背景光控制器MAX8709/MAX8709A18.功率因数校正控制器MC33262/MC3426219.固定频率电流模式功率因数校正控制器NCP1653场致发光灯高压驱动器SP440321.功率因数校正控制器TDA4862/TDA486322.有源功率因数校正控制器UC385423.高频自振荡节能灯驱动器电路VK05CFL24.大功率高频自振荡节能灯驱动器电路VK06TL第4章充电控制器1.多功能锂电池线性充电控制器AAT36802.可编程快速电池充电控制器BQ20003.可进行充电速率补偿的锂电池充电管理器BQ20574.锂电池充电管理电路BQ2400x5.单片锂电池线性充电控制器BQ2401x接口单节锂电池充电控制器BQ2402x同步开关模式锂电池充电控制器BQ241008.集成PWM开关控制器的快速充电管理器BQ29549.具有电池电量计量功能的充电控制器DS277010.锂电池充电控制器FAN7563/FAN7564线性锂/锂聚合物电池充电控制器ISL629212.锂电池充电控制器LA5621M/LA5621V通用充电控制器LT1571恒流/恒压电池充电控制器LT176915.线性锂电池充电控制器LTC173216.带热调节功能的1A线性锂电池充电控制器LTC173317.线性锂电池充电控制器LTC173418.新型开关电源充电控制器LTC198019.开关模式锂电池充电控制器LTC4002锂电池充电器LTC400621.多用途恒压/恒流充电控制器LTC4008锂离子/锂聚合物电池充电控制器LTC405223.可由USB端口供电的锂电池充电控制器LTC405324.小型150mA锂电池充电控制器LTC405425.线性锂电池充电控制器LTC405826.单节锂电池线性充电控制器LTC405927.独立线性锂电池充电控制器LTC406128.镍镉/镍氢电池充电控制器M62256FP29.大电流锂/镍镉/镍氢电池充电控制器MAX150130.锂电池线性充电控制器MAX150731.双输入单节锂电池充电控制器MAX1551/MAX155532.单节锂电池充电控制器MAX167933.小体积锂电池充电控制器MAX1736接口单节锂电池充电控制器MAX181135.多节锂电池充电控制器MAX187336.双路输入锂电池充电控制器MAX187437.单节锂电池线性充电控制器MAX189838.低成本/多种电池充电控制器MAX190839.开关模式单节锂电池充电控制器MAX1925/MAX192640.快速镍镉/镍氢充电控制器MAX2003A/MAX200341.可编程快速充电控制器MAX712/MAX71342.开关式锂电池充电控制器MAX74543.多功能低成本充电控制器MAX846A44.具有温度调节功能的单节锂电池充电控制器MAX8600/MAX860145.锂电池充电控制器MCP73826/MCP73827/MCP7382846.高精度恒压/恒流充电器控制器MCP73841/MCP73842/MCP73843/MCP7384447.锂电池充电控制器MCP73861/MCP7386248.单节锂电池充电控制器MIC7905049.单节锂电池充电控制器NCP180050.高精度线性锂电池充电控制器VM7205。

EPM240T100C5中文资料(Altera)中文数据手册「EasyDatasheet - 矽搜」

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芯片中文手册,看全文,戳
MAX II器件采用节省空间FineLine BGA,微型BGAFineLine可用,
和薄型四方扁平封装（TQFP）封装（参见
表1-3 and 表1-4）.
器件支持垂直迁移同一封装内（例如,你可以
特点
EPM240G EPM570G EPM1270G
LEs
240
570
1,270
典型等效宏单元
192
440
980
等效宏单元范围
128至240 240至570 570至1270
UFM大小（位）最大用户I / O引脚
8,192 80
8,192 160
8,192 212
t (ns) (1)
4.7
5.4
6.2
EPM 2210 EPM 2210G
2,210 1,700 1,270 to 2,210 8,192 272
7.0 304 1.2 4.6
EPM 240Z 240 192
128至240 8,192 80 7.5 152 2.3 6.5
EPM 570Z 570 440
240至570 8,192 160 9.0 152 2.2 6.7

MICROCHIP PIC16F627A 628A 648A单片机数据手册

深圳市粤原点科技有限公司(Microchip Authorized Design Partner)指定授权总部地址：深圳市福田区福虹路世贸广场C座1103座Add： Room 1103,Block C,World Trade Plaza,9Fuhong Road,Futian District Shen Zhen City电话(tel) ：86-755-83666321,83666320,83666325传真(fax) ：86-755-83666329Web: E-mail：********************@联系人：马先生,王小姐,汤小姐在线咨询：QQ:42513912MSN:***********************7x24小时在线产品咨询:135******** 137********PIC16F627A/628A/648A数据手册采用纳瓦技术的8位CMOS闪存单片机 2005 Microchip Technology Inc.DS40044D_CNDS40044D_CN 第ii 页 2005 Microchip Technology Inc.提供本文档的中文版本仅为了便于理解。

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SD2400RAMdatasheet

INTAF INTS1 TDS1 F5 TD5
INTDF INTS0 TDS0 F4 TD4
0 FOBAT FS3 F3 TD3
WRTC2 INTDE FS2 F2 TD2
0 INTAE FS1 F1 TD1
RTCF INTFE FS0 F0 TD0
N/A N/A N/A N/A 0-255
0000-0000 0000-0000 0000-0000 0000-0000 0000-0000
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芯片在兴威帆的评估板上可通过 4KV 的群脉冲(EFT)干扰。 CMOS 工艺内置晶振，出厂前已对时钟进行校准，保证精度±5ppm，即时钟年误差小于 2.5 分钟(在 25±1 ℃下)。有工业级型号，其尾缀加“I”以示区分，如“SD2400API”为 SD2400AP 的工业级， “P”标志为直插封装形式。
注意: 当读取小时数据时,要屏蔽掉小时的最高位 12_/24,否则在 24 小时制时会因为 12_/24=1 而显示不对. 分数据[01 地址]（00~59）秒数据[00H 地址]（00~59）例如:设时间为 2006 年 12 月 20 日星期三 18 点 19 分 20 秒(24 小时制),则寄存器 00～07H 的赋值应分别为 20h、19H、98h、03h、20h、12h、06h。要特别注意此处小时位的赋值,因为是 24 小时制式,小时的 12_/24 位=1,所以小时的赋值为 98h(1001 1000B)。注: 1. 在上电复位时，芯片内部不对实时时钟数据寄存器作清零或置位处理。
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24AA128T-EMS资料

© 2007 Microchip Technology Inc.DS21930B-page 124AA00/24LC00/24C00 24AA01/24LC01B 24AA014/24LC01424C01C 24AA02/24LC02B 24C02C24AA024/24LC024 24AA025/24LC02524AA04/24LC04B 24AA08/24LC08B 24AA16/24LC16B 24AA32A/24LC32A 24AA64/24LC64/24FC6424AA128/24LC128/24FC12824AA256/24LC256/24FC256 24AA512/24LC512/24FC512Features:•128-bit through 512 Kbit devices•Single supply with operation down to 1.7V for 24AAXX devices•Low-power CMOS technology:-1mA active current, typical-1μA standby current, typical (I-temp)•2-wire serial interface bus, I 2C™ compatible •Schmitt Trigger inputs for noise suppression •Output slope control to eliminate ground bounce •100kHz (1.7V) and 400kHz (≥ 2.5V) compatibility • 1 MHz for 24FCXX products•Self-timed write cycle (including auto-erase)•Page write buffer•Hardware write-protect available on most devices •Factory programming (QTP) available •ESD protection > 4,000V • 1 million erase/write cycles •Data retention > 200 years•8-lead PDIP , SOIC, TSSOP and MSOP packages •5-lead SOT-23 package (most 1-16 Kbit devices)•8-lead 2x3mm and 5x6mm DFN packages available•Pb-free and RoHS compliant•Available for extended temperature ranges:-Industrial (I): -40°C to +85°C -Automotive (E): -40°C to +125°CDescription:The Microchip Technology Inc. 24CXX, 24LCXX,24AAXX and 24FCXX (24XX*) devices are a family of 128-bit through 512 Kbit Electrically Erased PROMs.The devices are organized in blocks of x8-bit memory with 2-wire serial interfaces. Low-voltage design permits operation down to 1.7V (for 24AAXX devices),with standby and active currents of only 1 μA and 1mA, respectively. Devices 1 Kbit and larger have page write capability. Parts having functional address lines allow connection of up to 8 devices on the same bus.The 24XX family is available in the standard 8-pin PDIP , surface mount SOIC, TSSOP and MSOP pack-ages. Most 128-bit through 16 Kbit devices are also available in the 5-lead SOT-23 package. DFN packages (2x3mm or 5x6mm) are also available. All packages are Pb-free (Matte Tin) finish.*24XX is used in this document as a generic part number for 24 series devices in this data sheet.24XX64, for example, represents all voltages of the 64Kbit device.Package Types (1)A0A1A2V SS12348765V CC WP (3)SCL SDAPDIP/SOICA0A1A2V SS12348765V CC WP (3)SCL SDA TSSOP/MSOP (2)1543SCL V SS SDAV CCNC 2SOT-23-5(24XX00)SOT-23-51543SCL V SS SDAWPV CC 2(all except 24XX00)A0A1A2V SS WP (3)SCL SDA56784321V CC DFNNote 1:Pins A0, A1, A2 and WP are not used by some devices (no internal connections). See Table 1-1,Device Selection Table, for details.2:Pins A0 and A1 are no-connects for the 24XX128and 24XX256 MSOP devices.3:Pin 7 is “not used” for 24XX00, 24XX025 and 24C01C.I 2C ™ Serial EEPROM Family Data Sheet24AAXX/24LCXX/24FCXXDS21930B-page 2© 2007 Microchip Technology Inc.TABLE 1-1:DEVICE SELECTION TABLEPart Number V CC RangeMax. Clock FrequencyPage SizeWrite-Protect SchemeFunctional Address PinsTemp. RangePackages (5)128-bit devices 24AA00 1.7-5.5V 400 kHz (1)—NoneNoneI P , SN, ST, OT, MC24LC00 2.5-5.5V 400 kHz (1)I 24C00 4.5-5.5V400 kHzI, E1 Kb devices 24AA01 1.7-5.5V 400 kHz (2)8 bytes Entire Array None I P , SN, ST, MS, OT, MC24LC01B 2.5-5.5V 400 kHz I, E 24AA014 1.7-5.5V 400 kHz (2)16 bytes Entire Array A0, A1, A2I P , SN, ST, MS, MC 24LC014 2.5-5.5V400 kHzI 24C01C 4.5V-5.5V 400 kHz16 bytesNoneA0, A1, A2I, EP , SN, ST, MC 2 Kb devices 24AA02 1.7-5.5V 400 kHz (2)8 bytes Entire Array None I P , SN, ST, MS, OT, MC24LC02B 2.5-5.5V 400 kHz I, E 24AA024 1.7-5.5V 400 kHz (2)16 bytes Entire Array A0, A1, A2I P , SN, ST, MS, MC 24LC024 2.5-5.5V 400 kHz I 24AA025 1.7-5.5V 400 kHz (2)16 bytes None A0, A1, A2I P , SN, ST,MS, MC 24LC025 2.5-5.5V 400 kHz I 24C02C 4.5-5.5V400 kHz16 bytesUpper Half of ArrayA0, A1, A2I, EP , SN, ST, MC 4 Kb devices 24AA04 1.7-5.5V 400 kHz (2)16 bytesEntire ArrayNoneI P , SN, ST, MS, OT, MC24LC04B 2.5-5.5V400 kHzI, E8 Kb devices 24AA08 1.7-5.5V 400 kHz (2)16 bytesEntire ArrayNoneI P , SN, ST, MS, OT, MC24LC08B 2.5-5.5V400 kHzI, E16 Kb devices 24AA16 1.7-5.5V 400 kHz (2)16 bytesEntire ArrayNoneI P , SN, ST, MS, OT, MC24LC16B 2.5-5.5V400 kHzI, E32 Kb devices 24AA32A 1.7-5.5V 400 kHz (2)32 bytesEntire ArrayA0, A1, A2I P , SN, SM, ST, MS, MC24LC32A 2.5-5.5V400 kHzI, E64 Kb devices 24AA64 1.7-5.5V 400 kHz (2)32 bytesEntire ArrayA0, A1, A2I P , SN, SM, ST, MS, MC24LC64 2.5-5.5V 400 kHz I, E 24FC641.7-5.5V1 MHz (3)INote 1:100 kHz for V CC <4.5V.2:100 kHz for V CC <2.5V.3:400 kHz for V CC <2.5V.4:Pins A0 and A1 are no-connects for the 24XX128 and 24XX256 in the MSOP package.5:P = 8-PDIP , SN = 8-SOIC (3.90 mm JEDEC), ST = 8-TSSOP , OT = 5 or 6-SOT23, MC = 2x3mm DFN,MS = 8-MSOP , SM = 8-SOIC (200 mil EIAJ), MF = 5x6mm DFN.© 2007 Microchip Technology Inc.DS21930B-page 324AAXX/24LCXX/24FCXX128 Kb devices 24AA128 1.7-5.5V 400 kHz (2)64 bytesEntire ArrayA0, A1, A2(4)I P , SN, SM, ST, MS, MF, ST1424LC128 2.5-5.5V 400 kHz I, E 24FC128 1.7-5.5V1 MHz (3)I256 Kb devices 24AA256 1.7-5.5V 400 kHz (2)64 bytesEntire ArrayA0, A1, A2(4)I P , SN, SM, ST, MS, MF, ST1424LC256 2.5-5.5V 400 kHz I, E 24FC256 1.7-5.5V1 MHz (3)I512 Kb devices 24AA512 1.7-5.5V 400 kHz (2)128 bytesEntire ArrayA0, A1, A2IP , SM, MF, ST1424LC512 2.5-5.5V400 kHzI, E 24FC5121.7-5.5V (3) 1 MHzITABLE 1-1:DEVICE SELECTION TABLE (CONTINUED)Part Number V CC RangeMax. Clock FrequencyPage SizeWrite-Protect SchemeFunctional Address PinsTemp. RangePackages (5)Note 1:100 kHz for V CC <4.5V.2:100 kHz for V CC <2.5V.3:400 kHz for V CC <2.5V.4:Pins A0 and A1 are no-connects for the 24XX128 and 24XX256 in the MSOP package.5:P = 8-PDIP , SN = 8-SOIC (3.90 mm JEDEC), ST = 8-TSSOP , OT = 5 or 6-SOT23, MC = 2x3mm DFN,MS = 8-MSOP , SM = 8-SOIC (200 mil EIAJ), MF = 5x6mm DFN.24AAXX/24LCXX/24FCXXDS21930B-page 4© 2007 Microchip Technology Inc.2.0ELECTRICAL CHARACTERISTICSAbsolute Maximum Ratings (†)V CC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. V SS .........................................................................................................-0.6V to V CC +1.0V Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature with power applied................................................................................................-40°C to +125°C ESD protection on all pins ......................................................................................................................................................≥4kVTABLE 2-1:DC CHARACTERISTICS† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.DC CHARACTERISTICS Electrical Characteristics:Industrial (I):V CC = +1.7V to 5.5V T A = -40°C to +85°C Automotive (E):V CC = +2.5V to 5.5V T A = -40°C to 125°CParam.No.Sym.CharacteristicMin.Max.Units ConditionsD1—A0, A1, A2, SCL, SDA and WP pins:————D2V IH High-level input voltage 0.7 V CC—V —D3V IL Low-level input voltage—0.3 V CC 0.2 V CCV V V CC ≥ 2.5V V CC < 2.5V D4V HYS Hysteresis of Schmitt Trigger inputs (SDA, SCL pins)0.05 V CC —V (Note 1)D5V OL Low-level output voltage —0.40V I OL = 3.0mA @ V CC = 2.5V D6I LI Input leakage current —±1μA V IN = V SS or V CC D7I LO Output leakage current —±1μA V OUT = V SS or V CC D8C IN , C OUTPin capacitance (all inputs/outputs)—10pF V CC = 5.0V (Note 1)T A = 25°C, F CLK = 1MHz D9I CC Read Operating current—4001μA mA 24XX128, 256, 512: V CC = 5.5V, SCL = 400 kHzAll except 24XX128, 256, 512: V CC = 5.5V, SCL = 400 kHz I CC Write—35mA mA V CC = 5.5V, All except 24XX512V CC = 5.5V, 24XX512D10I CCSStandby current—1μAT A = -40°C to +85°CSCL = SDA = V CC = 5.5V A0, A1, A2, WP = V SS or V CC —5μAT A = -40°C to 125°CSCL = SDA = V CC = 5.5V A0, A1, A2, WP = V SS or V CC —50μA24C01C and 24C02C only SCL = SDA = V CC = 5.5V A0, A1, A2, WP = V SS or V CCNote 1:This parameter is periodically sampled and not 100% tested.24AAXX/24LCXX/24FCXX TABLE 2-2:AC CHARACTERISTICS – ALL EXCEPT 24XX00, 24C01CAND 24C02CAC CHARACTERISTICS Electrical Characteristics:Industrial (I):V CC = +1.7V to 5.5V T A = -40°C to +85°C Automotive (E):V CC = +2.5V to 5.5V T A = -40°C to 125°CParam.No.Sym.Characteristic Min.Max.Units Conditions1F CLK Clock frequency————1004004001000kHz 1.7V ≤ V CC< 2.5V2.5V ≤ V CC≤ 5.5V1.7V ≤ V CC<2.5V 24FCXXX2.5V ≤ V CC≤ 5.5V 24FCXXX2T HIGH Clock high time4000600600500————ns 1.7V ≤ V CC< 2.5V2.5V ≤ V CC≤ 5.5V1.7V ≤ V CC<2.5V 24FCXXX2.5V ≤ V CC≤ 5.5V 24FCXXX3T LOW Clock low time470013001300500————ns 1.7V ≤ V CC< 2.5V2.5V ≤ V CC≤ 5.5V1.7V ≤ V CC<2.5V 24FCXXX2.5V ≤ V CC≤ 5.5V 24FCXXX4T R SDA and SCL rise time(Note1)———1000300300ns 1.7V ≤ V CC< 2.5V2.5V ≤ V CC≤ 5.5V1.7V ≤ V CC≤ 5.5V 24FCXXX5T F SDA and SCL fall time(Note1)——300100ns All except 24FCXXX1.7V ≤ V CC≤ 5.5V 24FCXXX6T HD:STA Start condition hold time4000600600250————ns 1.7V ≤ V CC< 2.5V2.5V ≤ V CC≤ 5.5V1.7V ≤ V CC<2.5V 24FCXXX2.5V ≤ V CC≤ 5.5V 24FCXXX7T SU:STA Start condition setup time4700600600250————ns 1.7V ≤ V CC< 2.5V2.5V ≤ V CC≤ 5.5V1.7V ≤ V CC<2.5V 24FCXXX2.5V ≤ V CC≤ 5.5V 24FCXXX8T HD:DAT Data input hold time0—ns(Note2)9T SU:DAT Data input setup time250100100———ns 1.7V ≤ V CC< 2.5V2.5V ≤ V CC≤ 5.5V1.7V ≤ V CC≤ 5.5V 24FCXXX10T SU:STO Stop condition setup time4000600600250————ns 1.7V ≤ V CC< 2.5V2.5V ≤ V CC≤ 5.5V1.7V ≤ V CC<2.5V 24FCXXX2.5V ≤ V CC≤ 5.5V 24FCXXX11T SU:WP WP setup time4000600600———ns 1.7V ≤ V CC< 2.5V2.5V ≤ V CC≤ 5.5V1.7V ≤ V CC≤ 5.5V 24FCXXX12T HD:WP WP hold time470013001300———ns 1.7V ≤ V CC< 2.5V2.5V ≤ V CC≤ 5.5V1.7V ≤ V CC≤ 5.5V 24FCXXXNote1:Not 100% tested. C B = total capacitance of one bus line in pF.2:As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.3:This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site:.4:24FCXXX denotes the 24FC64, 24FC128, 24FC256 and 24FC512 devices.© 2007 Microchip Technology Inc.DS21930B-page 524AAXX/24LCXX/24FCXXDS21930B-page 6© 2007 Microchip Technology Inc.13T AAOutput valid from clock (Note 2)————3500900900400ns1.7V ≤ V CC <2.5V 2.5V ≤ V CC ≤ 5.5V1.7V ≤ V CC <2.5V 24FCXXX 2.5V ≤ V CC ≤ 5.5V 24FCXXX 14T BUFBus free time: Time the bus must be free before a new transmission can start 470013001300500————ns1.7V ≤ V CC <2.5V 2.5V ≤ V CC ≤ 5.5V1.7V ≤ V CC <2.5V 24FCXXX 2.5V ≤ V CC ≤ 5.5V 24FCXXX 15T OF Output fall time from V IH minimum to V IL maximum C B ≤ 100pF10 + 0.1C B250250nsAll except 24FCXXX (Note 1)24FCXXX (Note 1)16T SP Input filter spike suppression (SDA and SCL pins)—50ns All except 24FCXXX (Note 1)17T WC Write cycle time (byte or page)—5ms18—Endurance1,000,000—cycles 25°C (Note 3)TABLE 2-2:AC CHARACTERISTICS – ALL EXCEPT 24XX00, 24C01C AND 24C02C (CONTINUED)AC CHARACTERISTICS Electrical Characteristics:Industrial (I):V CC = +1.7V to 5.5V T A = -40°C to +85°C Automotive (E):V CC = +2.5V to 5.5V T A = -40°C to 125°CParam.No.Sym.CharacteristicMin.Max.Units ConditionsNote 1:Not 100% tested. C B = total capacitance of one bus line in pF.2:As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.3:This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site:.4:24FCXXX denotes the 24FC64, 24FC128, 24FC256 and 24FC512 devices.24AAXX/24LCXX/24FCXX TABLE 2-3:AC CHARACTERISTICS – 24XX00, 24C01C AND 24C02CAll Parameters apply across all recommended operating ranges unless otherwise noted Industrial (I):T A = -40°C to +85°C, V CC = 1.7V to 5.5V Automotive (E):T A = -40°C to +125°C, V CC = 4.5V to 5.5VParameter Symbol Min.Max.Units ConditionsClock frequency F CLK———100100400kHz 4.5V ≤ Vcc ≤ 5.5V (E Temp range)1.7V ≤ Vcc ≤ 4.5V4.5V ≤ Vcc ≤5.5VClock high time T HIGH40004000600———ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)1.7V ≤ Vcc ≤ 4.5V4.5V ≤ Vcc ≤5.5VClock low time T LOW470047001300———ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)1.7V ≤ Vcc ≤ 4.5V4.5V ≤ Vcc ≤5.5VSDA and SCL rise time (Note1)T R———10001000300ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)1.7V ≤ Vcc ≤ 4.5V4.5V ≤ Vcc ≤5.5VSDA and SCL fall time T F—300ns(Note1)Start condition hold time T HD:STA40004000600———ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)1.7V ≤ Vcc ≤ 4.5V4.5V ≤ Vcc ≤5.5VStart condition setup time T SU:STA47004700600———ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)1.7V ≤ Vcc ≤ 4.5V4.5V ≤ Vcc ≤5.5VData input hold time T HD:DAT0—ns(Note2)Data input setup time T SU:DAT250250100———ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)1.7V ≤ Vcc ≤ 4.5V4.5V ≤ Vcc ≤5.5VStop condition setup time T SU:STO40004000600———ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)1.7V ≤ Vcc ≤ 4.5V4.5V ≤ Vcc ≤5.5VOutput valid from clock (Note2)T AA———35003500900ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)1.7V ≤ Vcc ≤ 4.5V4.5V ≤ Vcc ≤5.5VBus free time: Time the bus must be free before a new transmis-sion can start T BUF470047001300———ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)1.7V ≤ Vcc ≤ 4.5V4.5V ≤ Vcc ≤5.5VOutput fall time from V IH minimum to V IL maximum T OF20+0.1CB250ns(Note1), CB ≤ 100 pFInput filter spike suppression(SDA and SCL pins)T SP—50ns(Note1)Write cycle time T WC—41.5ms24XX0024C01C, 24C02CEndurance1,000,000—cycles(Note3)Note1:Not 100% tested. C B = total capacitance of one bus line in pF.2:As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.3:This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained at .© 2007 Microchip Technology Inc.DS21930B-page 724AAXX/24LCXX/24FCXXDS21930B-page 8© 2007 Microchip Technology Inc.FIGURE 2-1:BUS TIMING DATA(unprotected)(protected)SCL SDA INSDA OUTWP 57616328913D441011121424AAXX/24LCXX/24FCXX3.0PIN DESCRIPTIONSThe descriptions of the pins are listed in Table3-1.TABLE 3-1:PIN FUNCTION TABLE3.1A0, A1, A2 Chip Address Inputs The A0, A1 and A2 pins are not used by the 24XX01 through 24XX16 devices.The A0, A1 and A2 inputs are used by the 24C01C, 24C02C, 24XX014, 24XX024, 24XX025 and the 24XX32 through 24XX512 for multiple device opera-tions. The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true.For the 24XX128 and 24XX256 in the MSOP package only, pins A0 and A1 are not connected.Up to eight devices (two for the 24XX128 and 24XX256 MSOP package) may be connected to the same bus by using different Chip Select bit combinations.In most applications, the chip address inputs A0, A1 and A2 are hard-wired to logic ‘0’ or logic ‘1’. For applications in which these pins are controlled by a microcontroller or other programmable device, the chip address pins must be driven to logic ‘0’ or logic ‘1’before normal device operation can proceed.3.2Serial Data (SDA)This is a bidirectional pin used to transfer addresses and data into and out of the device. It is an open drain terminal. Therefore, the SDA bus requires a pull-up resistor to V CC (typical 10kΩ for 100kHz, 2kΩ for 400kHz and1MHz).For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions.3.3Serial Clock (SCL)This input is used to synchronize the data transfer to and from the device.3.4Write-Protect (WP)This pin must be connected to either V SS or V CC. If tied to V SS, write operations are enabled. If tied to V CC, write operations are inhibited but read operations are not affected. See Table1-1 for the write-protect scheme of each device.3.5Power Supply (V CC)A V CC threshold detect circuit is employed which disables the internal erase/write logic if V CC is below 1.5V at nominal conditions. For the 24C00, 24C01C and 24C02C devices, the erase/write logic is disabled below 3.8V at nominal conditions.Pin Name8-PinPDIP andSOIC8-PinTSSOP andMSOP5-Pin SOT-2324XX005-Pin SOT-23All except24XX0014-PinTSSOP8-Pin5x6 DFN and2x3 DFNFunctionA011(1)——11User configurable Chip Select(3) A122(1)——22User configurable Chip Select(3) A233——63User configurable Chip Select(3) V SS442274GroundSDA553385Serial DataSCL661196Serial Clock(NC)——4—3, 4, 5,10, 11, 12—Not ConnectedWP7(2)7(2)—5137Write-Protect InputV CC8854148Power SupplyNote1:Pins 1 and 2 are not connected for the 24XX128 and 24XX256 MSOP packages.2:Pin 7 is not used for 24XX00, 24XX025 and 24C01C.3:Pins A0, A1 and A2 are not used by some devices (no internal connections). See Table1-1 for details.© 2007 Microchip Technology Inc.DS21930B-page 924AAXX/24LCXX/24FCXXDS21930B-page 10© 2007 Microchip Technology Inc.4.0FUNCTIONAL DESCRIPTIONEach 24XX device supports a bidirectional, 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter, while a device receiving data is defined as a receiver. The bus has to be controlled by a master device which gener-ates the Serial Clock (SCL), controls the bus access and generates the Start and Stop conditions, while the 24XX works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated.Block DiagramHV GeneratorEEPROM Array Page Latches*YDECXDECSense Amp.R/W ControlM emory C ontrol L ogicI/O C ontrol L ogic I/OA0*A1*A2*SDASCLV CC V SSWP** A0, A1, A2, WP and page latches are not used by some devices.See Table 1-1, Device Selection Table, for details.5.0BUS CHARACTERISTICSThe following bus protocol has been defined:•Data transfer may be initiated only when the busis not busy.•During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure5-1).5.1Bus Not Busy (A)Both data and clock lines remain high.5.2Start Data Transfer (B)A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition.5.3Stop Data Transfer (C)A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition.5.4Data Valid (D)The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal.The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data.Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of data bytes transferred between Start and Stop conditions is determined by the master device.5.5AcknowledgeEach receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit.The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end-of-data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave.In this case, the slave (24XX) will leave the data line high to enable the master to generate the Stop condition (Figure 5-2).FIGURE 5-1:DATA TRANSFER SEQUENCE ON THE SERIAL BUSFIGURE 5-2:ACKNOWLEDGE TIMINGNote:During a write cycle, the 24XX will not acknowledge commands.SCLSDA(A)(B)(D)(D)(A)(C)Start ConditionAddress or AcknowledgeValid Data Allowed to ChangeStop ConditionSCL 987654321123Transmitter must release the SDA line at this point,allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data.Receiver must release the SDA line at this point so the Transmitter can continue sending data.Data from transmitterSDA AcknowledgebitData from transmitter5.6Device Addressing For Devices Without Functional Address PinsA control byte is the first byte received following the Start condition from the master device (Figure 5-3).The control byte begins with a four-bit control code. For the 24XX, this is set as ‘1010’ binary for read and write operations. The next three bits of the control byte are the block-select bits (B2, B1, B0). They are used by the master device to select which of the 256-word blocks of memory are to be accessed. These bits are in effect the three Most Significant bits of the word address. Note that B2, B1 and B0 are “don’t care” for the 24XX00, the 24XX01 and 24XX02. B2 and B1 are “don’t care” for the 24XX04. B2 is “don’t care” for the 24XX08.The last bit of the control byte defines the operation to be performed. When set to ‘1’, a read operation is selected. When set to ‘0’ a write operation is selected.Following the Start condition, the 24XX monitors the SDA bus. Upon receiving a ‘1010’ code, the block Acknowledge signal on the SDA line. The address byte follows the acknowledge.FIGURE 5-3:CONTROL AND ADDRESS BYTE ASSIGNMENTS FOR DEVICES WITHOUT ADDRESS PINSS 1010x x x R/W ACK S 1010x x x R/W ACK S 1010x x x R/W ACK S 1010x xB0R/W ACK S 1010xB1B0R/W ACK S11B2B1B0R/WACK24XX0124XX0224XX0424XX0824XX016x = “don’t care” bitAcknowledge Control CodeStart bitControl ByteBlock Select bitsAddress Byte24XX00Read/Write bit (read = 1, write = 0)x x x x A3..A0x A6.....A0A7......A0A7......A0A7......A0A7......A0bit5.7Device Addressing For Devices With Functional Address PinsA control byte is the first byte received following the Start condition from the master device (Figure 5-4).The control byte begins with a 4-bit control code. For the 24XX, this is set as ‘1010’ binary for read and write operations. The next three bits of the control byte are the Chip Select bits (A2, A1, A0). The Chip Select bits allow the use of up to eight 24XX devices on the same bus and are used to select which device is accessed.The Chip Select bits in the control byte must corre-spond to the logic levels on the corresponding A2, A1and A0 pins for the device to respond. These bits are,in effect, the three Most Significant bits of the word address.For 24XX128 and 24XX256 in the MSOP package, the A0 and A1 pins are not connected. During device addressing, the A0 and A1 Chip Select bits (Figure 5-4)should be set to ‘0’. Only two 24XX128 or 24XX256MSOP packages can be connected to the same bus.The last bit of the control byte defines the operation to be performed. When set to a ‘1’, a read operation is selected. When set to a ‘0’, a write operation is selected.For higher density devices (24XX32 through 24XX512), the next two bytes received define the address of the first data byte. Depending on the prod-uct density, not all bits in the address high byte are used. A15, A14, A13 and A12 are “don’t care” for 24XX32. A15, A14 and A13 are “don’t care” for 24XX64. A15 and A14 are “don’t care” for 24XX128.A15 is “don’t care” for 24XX256. All address bits are used for the 24XX512. The upper address bits are transferred first, followed by the Less Significant bits.Following the Start condition, the 24XX monitors the SDA bus. Upon receiving a ‘1010’ code, appropriate device select bits and the R/W bit, the slave device out-puts an Acknowledge signal on the SDA line. The address byte(s) follow the acknowledge.FIGURE 5-4:CONTROL AND ADDRESS BYTE ASSIGNMENTS FOR DEVICES WITH ADDRESS PINSS 1010A2A1A0R/W ACK S 1010A2A1A0R/W ACK S 1010A2A1A0R/W ACK S 1010A2A1A0R/W ACK S110A2A1A0R/W ACK24XX6424XX12824XX25624XX512x = “don’t care” bitAcknowledgeControl Code Start bitControl ByteChip Select bits*Address High Byte24XX32Read/Write bitx x x x A11A10A9A8x x xA12A11A10A9A8x xA13A12A11A10A9A8xA14A13A12A11A10A9A8A15A14A13A12A11A10A9A8bitS 1010A2A1A0R/W ACK S 1010A2A1A0R/W ACK S11A2A1A0R/WACKx A6.....A0A7......A0A7......A024XX024/02524C02C 24C01C Address ByteA7......A0A7......A0A7......A0A7......A0A7......A0Address Low Byte* Chip Select bits A1 and A0 must be set to ‘0’ for 24XX128/256 devices in the MSOP package.Control Byte(Read = 1, Write = 0)。

CAT24AC128_06资料

1V SSA1A2V CC WP SCL SDAA0DESCRIPTIONThe CAT24AC128 is a 128kbit Serial CMOS EEPROM internally organized as 16,384 words of 8 bits each.Catalyst’s advanced CMOS technology substantially reduces device power requirements. The CAT24AC128features a 64-byte page write buffer. The device operates* Catalyst Semiconductor is licensed by Philips Corporation to carry the I 2C Bus Protocol.I Commercial, industrial and extendedautomotive temperature rangesI Write protect feature– Entire array protected when WP at V IHI 1,000,000 program/erase cycles I 100 year data retentionI 8-Pin DIP, 8-Pin SOIC (JEDEC/EIAJ) or14-pin TSSOPvia the I 2C bus serial interface and is available in 8-pin DIP, 8-pin SOIC or 14-pin TSSOP packages. Three device address inputs allows up to 8 devices to share a common 2-wire I 2C bus.PIN CONFIGURATIONBLOCK DIAGRAMI 400kHz (2.5V) and 100kHz (1.8V) I 2C buscompatibility I 1.8 to 5.5 volt operation I Low power CMOS technologyI Schmitt trigger filtered inputs for noisesuppressionI 64-Byte page write bufferI Self-timed write cycle with auto-clearFEATURESDIP Package (P, L)SOIC Package (J, K, W, X)© Catalyst Semiconductor, Inc.Characteristics subject to change without noticeVEXTERNAL LOADVDoc. No. 1028, Rev. JTSSOP Package (U14, Y14)A1A2A0SDAWP NC NC NC SCL V SSV CC PIN FUNCTIONSPin Name FunctionSDA Serial Data/Address SCL Serial Clock WP Write ProtectV CC +1.8V to +5.5V Power Supply V SS GroundA0 - A2Device Address Inputs2Doc. No. 1028, Rev. JSymbol ParameterTest Conditions MinTypMax Units I CC1Power Supply Current - Read f SCL = 100 KHz 1mA V CC = 5V I CC2Power Supply Current - Writef SCL = 100 KHz 3mA V CC = 5V I SB (5)Standby Current V IN = GND or V CC1µA V CC = 5V I LI Input Leakage Current V IN = GND to V CC 3µA I LO Output Leakage Current V OUT = GND to V CC3µA V IL Input Low Voltage –1V CC x 0.3V V IH Input High VoltageV CC x 0.7V CC + 0.5V V OL1Output Low Voltage (V CC = +3.0V)I OL = 3.0 mA 0.4V V OL2Output Low Voltage (V CC = +1.8V)I OL = 1.5 mA 0.5VABSOLUTE MAXIMUM RATINGS*Temperature Under Bias .................–55°C to +125°C Storage Temperature.......................–65°C to +150°C Voltage on Any Pin withRespect to Ground (1)...........–2.0V to +V CC + 2.0V V CC with Respect to Ground ...............–2.0V to +7.0V Package Power DissipationCapability (T A = 25°C)...................................1.0W Lead Soldering Temperature (10 secs)............300°C Output Short Circuit Current (2)........................100mA *COMMENTStresses above those listed under “Absolute Maximum Ratings ” may cause permanent damage to the device.These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.CAPACITANCE T A = 25°C, f = 1.0 MHz, V CC = 5V Symbol TestConditions MinTypMax Units C I/O (3)Input/Output Capacitance (SDA)V I/O = 0V 8pF C IN (3)Input Capacitance (SCL, WP, A0, A1, A2)V IN = 0V6pFNote:(1)The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DCvoltage on output pins is V CC +0.5V, which may overshoot to V CC + 2.0V for periods of less than 20ns.(2)Output shorted for no more than one second. No more than one output shorted at a time.(3)These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100and JEDEC test methods.(4)Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V CC +1V.(5)Maximum standby current (I SB ) = 10µA for the Extended Automotive temperature range.D.C. OPERATING CHARACTERISTICSV CC = +1.8V to +5.5V, unless otherwise specified.RELIABILITY CHARACTERISTICS Symbol ParameterMin.Typ.Max.Units N END (3)Endurance 1,000,000Cycles/Byte T DR (3)Data Retention 100Years V ZAP (3)ESD Susceptibility 2000Volts I LTH (3)(4)Latch-up100mACAT24AC1283Doc. No. 1028, Rev. JPower-Up Timing (1)(2)Symbol ParameterMinTypMax Units t PUR Power-Up to Read Operation 1ms t PUWPower-Up to Write Operation1msThe write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.Note:(1)This parameter is tested initially and after a design or process change that affects the parameter.(2)t PUR and t PUW are the delays required from the time V CC is stable until the specified operation can be initiated.FUNCTIONAL DESCRIPTIONThe CAT24AC128 supports the I 2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START andSTOP conditions for bus access. The CAT24AC128operates as a Slave device. Both the Master device and Slave device can operate as either transmitter or receiver,but the Master device controls which mode is activated.A.C. CHARACTERISTICSV CC = +1.8V to +5.5V, unless otherwise specified Output Load is 1 TTL Gate and 100pF Read & Write Cycle Limits SymbolParameterV CC = 1.8 V - 5.5 V V CC = 2.5 V - 5.5 V MinMax MinMax Units F SCL Clock Frequency100400kHz t AA SCL Low to SDA Data Out 0.1 3.50.050.9µs and ACK Outt BUF (1)Time the Bus Must be Free Before 4.7 1.2µs a New Transmission Can Start t HD:STA Start Condition Hold Time 4.00.6µs t LOW Clock Low Period 4.7 1.2µs t HIGH Clock High Period4.00.6µs t SU:STA Start Condition Setup Time4.00.6µs (for a Repeated Start Condition)t HD:DAT Data In Hold Time 00ns t SU:DAT Data In Setup Time 100100nst R (1)SDA and SCL Rise Time 1.00.3µs t F (1)SDA and SCL Fall Time 300300ns t SU:STO Stop Condition Setup Time 4.70.6µs t DH Data Out Hold Time 10050nst WR Write Cycle Time55ms t SPInput Suppression (SDA, SCL)100100nsNot Recommended for New Design, Replace with CAT24C128元器件交易网CAT24AC1284Doc. No. 1028, Rev. JI 2C BUS PROTOCOLThe features of the I 2C bus protocol are defined as follows:(1)Data transfer may be initiated only when the bus isnot busy.(2)During a data transfer, the data line must remainstable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition.START ConditionThe START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT24AC128 monitors the SDA and SCL lines and will not respond until this condition is met.STOP ConditionA LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition.PIN DESCRIPTIONSSCL: Serial ClockThe serial clock input clocks all data transferred into or out of the device.SDA: Serial Data/AddressThe bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs.WP: Write ProtectThis input, when tied to GND, allows write operations to the entire memory. When this pin is tied to Vcc, the entire memory is write protected. When left floating,memory is unprotected.A0, A1, A2: Device Address InputsThese inputs set the device address when cascading multiple devices. When these pins are left floating the default values are zeroes. A maximum of eight devices can be cascaded.START BITSDASTOP BITSCLNot Recommended for New Design, Replace with CAT24C128元器件交易网CAT24AC1285Doc. No. 1028, Rev. JDEVICE ADDRESSINGThe bus Master begins a transmission by sending a START condition. The Master sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 1010 (Fig. 5). The next three significant bits (A2, A1, A0)are the device address bits and define which device the master is accessing. Up to eight CAT24AC128 devices may be individually addressed by the system. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected.After the Master sends a START condition and the slave address byte, the CAT24AC128 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT24AC128 then performs a Read or Write operation depending on the state of the R/W bit.AcknowledgeAfter a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data.The CAT24AC128 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation,it responds with an acknowledge after receiving each 8-bit byte.Figure 5. Slave Address BitsWhen the CAT24AC128 begins a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT24AC128 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition.WRITE OPERATIONSByte WriteIn the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends two 8-bit address words that are to be written into the address pointers of the CAT24AC128. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the addressed memory location. The CAT24AC128 acknowledges once more and the Master generates the STOP condition. At this time, the device begins an internal programming cycle to nonvolatile memory. While the cycle is in progress, the device will not respond to any request from the Master device.Page WriteThe CAT24AC128 writes up to 64 bytes of data, in a single write cycle, using the Page Write operation. The page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed*A0, A1 and A2 must compare to its corresonding hard wired inputs (pins 1, 2 and 3).Not Recommended for New Design, Replace with CAT24C128元器件交易网CAT24AC1286Doc. No. 1028, Rev. Jto send up to 63 additional bytes. After each byte has been transmitted, CAT24AC128 will respond with an acknowledge, and internally increment the six low order address bits by one. The high order bits remain unchanged.If the Master transmits more than 64 bytes before sending the STOP condition, the address counter ‘wraps around ’,and previously transmitted data will be overwritten.When all 64 bytes are received, and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the CAT24AC128 in a single write cycle.Acknowledge PollingDisabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation,CAT24AC128 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issu-ing the start condition followed by the slave address for a write operation. If CAT24AC128 is still busy with the write operation, no ACK will be returned. If CAT24AC128 has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation.WRITE PROTECTIONThe Write Protection feature allows the user to protect against inadvertent programming of the memory array.If the WP pin is tied to V CC , the entire memory array is protected and becomes read only. The CAT24AC128will accept both slave and byte addresses, but the memory location accessed is protected from programming by the device ’s failure to send an acknowledge after the first byte of data is received.READ OPERATIONSThe READ operation for the CAT24AC128 is initiated in the same manner as the write operation with one exception, that R/W bit is set to one. Three different READ operations are possible: Immediate/Current Address READ, Selective/Random READ and Sequential READ.Immediate/Current Address ReadThe CAT24AC128’s address counter contains the address of the last byte accessed, incremented by one.In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N+1. If N=E (where E=16383),then the counter will ‘wrap around ’ to address 0 and continue to clock out data. After the CAT24AC128receives its slave address information (with the R/W bit set to one), it issues an acknowledge, then transmits the 8 bit byte requested. The master device does not send an acknowledge, but will generate a STOP condition.Selective/Random Address ReadSelective/Random READ operations allow the MasterFigure 7. Page Write TimingFigure 6. Byte Write TimingA 15–A 8SLAVE ADDRESSSA C KA C KDATAA C KST O P PBUS ACTIVITY:MASTERSDA LINES T A R T A 7–A 0BYTE ADDRESS A C K**SLAVE C KC KC KBUS ACTIVITY:MASTERSDA LINES T A R BYTE ADDRESS C KST O C KC KC K*=Don't Care Bit*=Don't Care BitNot Recommended for New Design, Replace with CAT24C128元器件交易网CAT24AC1287Doc. No. 1028, Rev. Jdevice to select at random any memory location for a READ operation. The Master device first performs a ‘dummy ’ write operation by sending the START condition,slave address and byte addresses of the location it wishes to read. After CAT24AC128 acknowledges, the Master device sends the START condition and the slave address again, this time with the R/W bit set to one. The CAT24AC128 then responds with its acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition.Sequential ReadThe Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT24AC128 sends the initial 8-bit byte requested, the Master will respond with an acknowledge which tells the device it requires more Figure 8. Current Address Read Timingdata. The CAT24AC128 will continue to output an 8-bit byte for each acknowledge sent by the Master. The operation will terminate when the Master fails to respond with an acknowledge, thus sending the STOP condition.The data being transmitted from CAT24AC128 is outputted sequentially with data from address N followed by data from address N+1. The READ operation address counter increments all of the CAT24AC128 address bits so that the entire memory array can be read during one operation. If more than E (where E=16383) bytes are read out, the counter will ‘wrap around ’ and continue to clock out data bytes.Figure 9. Random Address Read Timing*=Don't Care Bit24AC128 F08SCL SDA 8TH BIT STOPNO ACKDATA OUT89SLAVE ADDRESSSA C KBUS ACTIVITY:MASTERSDA LINES T A R T N O A C K DATAS T O P PA 15–A 8SLAVE ADDRESSSA C KA C KA C KBUS ACTIVITY:MASTERSDA LINES T A R T A 7–A 0BYTE ADDRESS SLAVEADDRESSSA C KN O A C K S T A R T DATAPS T O P **Not Recommended for New Design, Replace with CAT24C128元器件交易网CAT24AC1288Doc. No. 1028, Rev. JORDERING INFORMATIONNotes:(1)The device used in the above example is a CAT24AC128KI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 VoltOperating Voltage, Tape & Reel)(2)Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWA). For additionalinformation, please contact your Catalyst sales office.Figure 10. Sequential Current Address Read TimingC KC KS T O O A C K C KSLAVE C KBUS ACTIVITY:MASTERSDA LINES T A RSLAVE C KC KC KBUS ACTIVITY:MASTERSDA LINES T A R BYTE ADDRESS SLAVES T A R C KC KC KS T O O A C K C KFigure 11. Sequential Random Address Read TimingNot Recommended for New Design, Replace with CAT24C128元器件交易网CAT24AC1289Doc. No. 1028, Rev. JNotes:plies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent.2.All linear dimensions are in inches and parenthetically in millimeters.0.100 (2.54)BSC8-LEAD 300 MIL WIDE PLASTIC DIP (P, L)8-LEAD 150 MIL WIDE SOIC (J, W)Notes:plies with JEDEC publication 95 MS-012 dimensions; however, some dimensions may be more stringent.2.All linear dimensions are in inches and parenthetically in millimeters.Not Recommended for New Design, Replace with CAT24C128元器件交易网CAT24AC12810Doc. No. 1028, Rev. JNote:1.All linear dimensions are in inches and parenthetically in millimeters.8-LEAD 210 MIL WIDE SOIC (K, X)14-LEAD TSSOP (U14, Y14)LAND P A TTERN RECOMMENDATION0.250o - 8DETAIL ADimension D Pkg Min Max 144.95.1Not Recommended for New Design, Replace with CAT24C128元器件交易网Catalyst Semiconductor, Inc.Corporate Headquarters2975 Stender WaySanta Clara, CA 95054Phone: 408.542.1000Fax: Publication #:1028Revison:J Issue date:01/16/06REVISION HISTORY DateRev.Reason 07/7/2004G Added Die Revision to Ordering Information Started revision history 07/27/2004H Updated DC Operating Characteristics table and notes 06/23/2005I Update FeaturesUpdate Pin FunctionsUpdate Reliability Characteristics Update D.C. Operating CharacteristicsUpdate A.C. CharacteristicsUpdate Read OperationsUpdate Figures 8, 9, 10Add Figure 11Update Ordering Information01/16/2006JUpdate Ordering Information Copyrights, Trademarks and Patents© Catalyst Semiconductor, Inc.Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:Beyond Memory ™, DPP ™, EZDim ™, LDD ™, MiniPot™ and Quad-Mode™Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur.Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete.Not Recommended for New Design, Replace with CAT24C128元器件交易网。

WTC-G2LS 数据手册说明书

G2L核心板数据手册Rev. 1.62022-05-05版本记录版本号修改说明修改人修改日期V1.0 初始文档yuge 2021-12-01 V1.3 修正引脚定义yuge 2021-12-11 V1.4 更新实物图yuge 2021-12-30 V1.5 修正内容描述yuge 2022-01-05 V1.6 更新实物图，QSPI1改成QSPI0 yuge 2022-05-05目录第1章产品简介 (5)1.1 CPU性能 (5)1.2 外观图 (6)1.3 系统框图 (7)第2章硬件参数 (7)2.1 核心板配置资源 (7)2.2 工作环境 (9)2.3 结构尺寸 (10)第3章引脚定义 (12)3.1 管脚位置 (12)3.2 管脚定义 (12)第4章核心板说明 (24)4.1 硬件设计 (24)4.1.1 DDR4内存 (24)4.1.2 Flash存储 (24)4.1.3 电源 (25)4.1.4 以太网 (25)4.1.5 启动引脚 (25)4.2 核心板引脚默认功能 (26)4.2.1 一路MAC控制器 (26)4.2.2 一路MIPI (27)4.2.3 一路RGB接口 (27)第5章软件参数 (29)第6章订货型号 (31)第7章联系我们 (32)第8章声明 (33)第1章产品简介WTC-G2LS核心板是杭州维芯科电子有限公司推出的一款采用日本瑞萨Renesas G2L系列为核心的嵌入式核心板。

该系列器件基于ARM Cortex-A55 内核，具有高性能、低功耗、多接口、低成本等特性，同时提供3D 图形加速和关键外设的集成，可满足各种应用需要，支持主流DDR4 内存，同时提供双路千兆以太网，多路串口来满足工业产品的需求。

1.1 CPU性能RZ/G2L系列处理器是日本瑞萨推出的通用处理器，集成Cortex-M33实时硬核，支持2路千兆网、2路CAN-FD、高清显示接口、摄像头接口、3D、H.264视频硬件编解码、USB接口、多路串口、PWM、ADC，是当前市场上接口最全面的MPU之一，而且长达10年+生命周期让您选择之后没有后顾之忧。

潘启panchip 2.4ghz无线收发soc芯片pan2416av产品说明书

PAN2416AV产品说明书2.4GHz无线收发SOC芯片V1.0PAN2416AV产品说明书2.4GHz单片高速无线收发SOC芯片概述PAN2416AV芯片是工作在2.400~2.483GHz世界通用ISM频段的单片无线收发芯片。

该芯片集成射频收发机、频率发生器、晶体振荡器、调制解调器和低功耗MCU等功能模块，并且支持一对多组网和带ACK的通信模式。

用户通过MCU的I/O口向芯片发出指令，芯片自动完成收发配置进行通信，并根据应答信息自动判断数据发送/接收是否成功，从而进行重发，丢包，继续发送和等待等操作，简化了用户程序。

发射输出功率、工作频道以及通信数据率均可配置。

PAN2416AV需要少量的外围器件，支持单层/双层印制电路板的方案。

主要特性1、功耗较低发射模式（2dBm）工作电流19mA；接收模式工作电流15mA；休眠电流2uA。

2、节省外围器件支持外围5个元器件，包括1颗晶振和少量电容；支持双层或单层印制板设计，可以使用印制板微带天线或者导线天线；芯片自带部分链路层的通信协议；配置少量的参数寄存器，使用方便。

3、性能优异250K/1M/2M bps模式的接收灵敏度为-91/-87/-83dBm；发射输出功率最大可达8dBm；抗干扰性好，接收滤波器的邻道抑制度高，接收机选择性较好。

4、集成MCU功能OTP：4K×16Bit；通用RAM：176×8Bit；MCU集成高精度12位ADC，内置WDT定时器、PWM输出、低压侦测电路等模块。

其它特性四线SPI 接口通信带自动扰码和CRC校验功能支持最大数据长度为32字节（两级FIFO）或者64字节（单级FIFO）SOP16封装1M / 2Mbps模式，需要晶振精度±40ppm 250kbps模式，需要晶振精度±20ppm 工作电压支持2.2~3.3V 工作温度支持-40~+85℃GFSK通信方式支持自动应答及自动重传支持RSSI检测功能10个GPIO中断源三路定时器应用方案无线鼠标电视和机顶盒遥控器无线游戏手柄遥控玩具常用遥控器智能家居版本修订时间更新内容相关文档V0.4 2016. 12 文字勘误V1.0 2017.09 文字修改目录1. 命名规则 (8)1.1 PAN2416AV命名规则 (8)1.2 PAN2416系列产品选择 (8)2. 主要电特性 (8)3. 极限最大额定值 (10)4. 系统结构方框图 (10)5. 引脚定义 (11)6. 芯片工作状态 (13)6.1 休眠模式 (14)6.2 待机模式-I（STB1） (14)6.3 待机模式-III（STB3） (14)6.4 待机模式-II（STB2） (14)6.5 接收模式 (14)6.6 发射模式 (14)7. 数据通信模式 (15)7.1 普通模式 (15)7.2 增强模式 (15)7.3增强发送模式 (16)7.4 增强接收模式 (16)7.5 增强模式下的数据包识别 (17)7.6 增强模式下的PTX和PRX的时序图 (17)7.7 增强模式下的接收端一对多通信 (17)7.8 DATA FIFO (19)7.9 中断引脚 (19)8. SPI控制接口 (19)8.1 SPI指令格式 (20)8.2 SPI 时序 (21)9. 控制寄存器 (22)10. 数据包格式描述 (32)10.1 普通模式的数据包形式 (32)10.2 增强模式的数据包形式 (33)10.3 增强模式的ACK包形式 (33)11. MCU寄存器 (34)11.1性能特性 (33)11.2系统结构框图 (34)11.3系统配置寄存器 (35)11.4在线串行编程 (36)12. 中央处理器(CPU) (37)12.1内存 (37)12.1.1程序内存 (37)12.1.2数据存储器 (41)12.2寻址方式 (43)12.2.1直接寻址 (43)12.2.2立即寻址 (43)12.2.3间接寻址 (43)12.3堆栈 (44)12.4工作寄存器（ACC） (45)12.4.1概述 (45)12.4.2 ACC应用 (45)12.5 程序状态寄存器(STATUS) (45)12.6 预分频器(OPTION_REG) (47)12.7程序计数器（PC） (48)12.8 看门狗计数器(WDT) (48)12.8.1 WDT周期 (48)12.8.2 看门狗定时器控制寄存器WDTCON (49)13. 系统时钟 (50)13.1 概述 (50)13.2 系统振荡器 (51)13.2.1 内部RC振荡 (51)13.3起振时间 (51)13.4振荡器控制寄存器 (51)14. 复位 (52)14.1上电复位 (52)14.2 掉电复位 (53)14.2.1掉电复位概述 (53)14.2.2掉电复位的改进办法 (54)14.3 看门狗复位 (54)15. 休眠模式 (55)15.1 进入休眠模式 (55)15.2 从休眠状态唤醒 (55)15.3 使用中断唤醒 (55)15.4 休眠模式应用举例 (56)15.5 休眠模式唤醒时间 (56)16. I/O端口 (57)16.1 PORTA (58)16.1.1 PORTA数据及方向控制 (58)16.1.2 PORTA模拟选择控制 (60)16.2 PORTB (60)16.2.1 PORTB数据及方向 (60)16.2.2 PORTB上拉电阻 (61)16.2.3 PORTB电平变化中断 (61)16.3 PORTC (62)16.3.1 PORTC数据及方向 (62)16.3.2 PORTC上拉电阻 (63)16.4 PORTE (63)16.4.1 PORTE数据及方向 (63)16.5 I/O使用 (64)16.5.1 写I/O口 (64)16.5.2 读I/O口 (64)16.6 I/O口使用注意事项 (65)17. 中断 (66)17.1 中断概述 (66)17.2 中断控制寄存器 (67)17.2.1 中断控制寄存器 (67)17.2.2 外设中断允许寄存器 (68)17.2.3 外设中断请求寄存器 (69)17.3 中断现场的保护方法 (70)17.4 中断的优先级，及多中断嵌套 (70)18. 定时计数器TIMER0 (71)18.1 定时计数器TIMER0概述 (71)18.2 TIMER0的工作原理 (72)18.2.1 8 位定时器模式 (72)18.2.2 8 位计数器模式 (72)18.2.3 软件可编程预分频器 (72)18.2.4 在TIMER0和WDT模块间切换预分频器 (72)18.2.5 TIMER0中断 (73)18.3 与TIMER0相关寄存器 (73)19. 定时计数器TIMER1 (74)19.1 TIMER1概述 (74)19.2 TIMER1 的工作原理 (74)19.3 TIMER1 预分频器 (74)19.4 TIMER1 中断 (74)19.5 TIMER1相关寄存器 (75)20. 定时计数器TIMER2 (75)20.1 TIMER2概述 (75)20.2 TIMER2的工作原理 (77)20.3 TIMER2相关的寄存器 (77)21. 模数转换（ADC） (79)21.1 ADC概述 (79)21.2 ADC配置 (79)21.2.1 端口配置 (79)21.2.2 通道选择 (80)21.2.3 ADC参考电压 (80)21.2.4 转换时钟 (80)21.2.5 ADC中断 (80)21.2.6 结果格式化 (80)21.3 ADC工作原理 (81)21.3.1 启动转换 (81)21.3.2 完成转换 (81)21.3.3 终止转换 (81)21.3.4 ADC在休眠模式下的工作原理 (81)21.3.5 A/D转换步骤 (81)21.4 ADC相关RAM (83)22. PWM模块 (85)22.1 PWM1 (85)22.2 PWM2 (86)22.3 PWM模式 (87)22.3.1 PWM周期 (88)22.3.2 PWM占空比 (88)22.3.3 PWM分辨率 (89)22.3.4 休眠模式下的操作 (89)22.3.5 系统时钟频率的改变 (89)22.3.6 复位的影响 (89)22.3.7 设置PWM操作 (89)23. MCU电气参数 (90)23.1 MCU DC特性 (90)23.2 MCU AC特性 (90)23.3指令一览表 (91)23.4 指令说明 (93)24. 典型应用电路（参考） (104)25. 封装尺寸 (105)26. 联系方式 (106)1. 命名规则1.1 PAN2416AV 命名规则图1.1 PAN2416系列产品命名规则1.2 PAN2416系列产品选择表1-1 PAN2416系列产品选择产品型号芯片版本封装形式 PAN2416AV A V ：SOP16 PAN2416AF A F ：SOP142. 主要电特性表2-1 PAN2416AV 的RF 部分主要电特性参数值特性测试条件(VCC = 3V±5%，TA=25℃)最小典型最大单位休眠模式 2 uA 待机模式1 30 uA 待机模式3 650 uA 待机模式2 780 uA 发射模式 (-35dBm) 9 mA 发射模式 (-20dBm) 9.5 mA 发射模式 (0dBm) 16 mA 发射模式 (2dBm) 19 mA 发射模式 (8dBm) 30 mA 发射模式 (13dBm) 66 mA 接收模式 (250Kbps) 15 mA 接收模式 (1Mbps) 15.5 mA ICC接收模式 (2Mbps)16.5 mA 系统指标ƒOP 工作频率24002483MHzPLL res锁相环频率步径 1 MHz ƒXTAL晶振频率16 MHz DR码率0.25 2 Mbps ∆ƒ250K调制频偏@250Kbps 125 150 KHz ∆ƒ1M调制频偏@1Mbps 160 300 KHz ∆ƒ2M调制频偏@2Mbps 320 550 KHz FCH250K频道间隔@250Kbps 1 MHz FCH1M频道间隔@1Mbps 1 MHz FCH2M频道间隔@2Mbps 2 MHz发射模式指标PRF 典型输出功率 2 8 8 dBm PRFC 输出功率范围-35 8 dBmPBW1发射带数据调制的20dB带宽（250Kbps）500 KHzPBW2发射带数据调制的20dB带宽（1Mbps）1 MHzPBW3发射带数据调制的20dB带宽（2Mbps）2 MHz接收模式指标（注1）RX max误码率<0.1%时的最大接收幅度0 dBm RXSENS1 接收灵敏度（0.1%BER）@250Kbps-91 dBmRXSENS2 接收灵敏度（0.1%BER）@1Mbps-87 dBmRXSENS3 接收灵敏度（0.1%BER）@2Mbps-83 dBm接收模式邻道选择性C/I CO同频的通道选择性@250kbps 2 dBc C/I1ST第1相邻道选择性@250kbps -8 dBc C/I2ND第2相邻道选择性@250kbps -18 dBc C/I3RD第3相邻道选择性@250kbps -24 dBc C/I4TH第4相邻道选择性@250kbps -28 dBc C/I5TH第5相邻道选择性@250kbps -32 dBc C/I6TH第6相邻道选择性@250kbps -35 dBc C/I CO同频的通道选择性@1Mbps 10 dBc C/I1ST第1相邻道选择性@1Mbps 1 dBc C/I2ND第2相邻道选择性@1Mbps -18 dBc C/I3RD第3相邻道选择性@1Mbps -23 dBc C/I4TH第4相邻道选择性@1Mbps -28 dBc C/I5TH第5相邻道选择性@1Mbps -32 dBc C/I6TH第6相邻道选择性@1Mbps -35 dBc C/I CO同频的通道选择性@2Mbps 10 dBcC/I1ST第1相邻道选择性@2Mbps -6 dBcC/I2ND第2相邻道选择性@2Mbps -10 dBcC/I3RD第3相邻道选择性@2Mbps -22 dBcC/I4TH第4相邻道选择性@2Mbps -28 dBcC/I5TH第5相邻道选择性@2Mbps -34 dBc操作条件VDD 供电电压 2.2 3 3.3 VVSS 芯片地0 VV OH高电平输出电压VDD-0.3 VDD VV OL低电平输出电压VSS VSS+0.3 VV IH高电平输入电压VDD-0.3 VDD VV IL低电平输入电压VSS VSS+0.3 V*注1：在晶振16MHz的整数倍（如2416、2432MHz等）的频道及相邻正负1MHz的频道的接收灵敏度退化2dB；发射信号调制精度（EVM）退化10%。

常见IC卡型号

常见IC卡型号来源：迈德金卡作者：青青禾更新时间：2010-04-12IC卡（INTEGRATED CIRCUITCARD）又称集成电路卡，它是一个塑料卡片，其大小与磁卡一样，但比磁卡要厚且硬。

在卡片的正面可以看到一块小金属片，在金属片的下面是一块半导体芯片。

这种芯片可以是存储器或是一微处理器（CPU）。

带着存储器的IC卡又称存储卡，带着CPU的IC卡又称智能卡或CPU。

1、ATMEL 24CO1A存储容量：1Kbit,无密码，只有读写两种操作制作标准：ISO 7816应用范围：数据存储2、ATMEL 24C16存储容量：16Kbit，无密码，只有读写两种操作制作标准：ISO 7816应用范围：数据存储3、ATMEL 24C64存储容量：64Kbit，无密码，只有读写两种操作制作标准：ISO 7816应用范围：数据存储4、AT88SC102存储容量：加密存储卡，1Kbit特点：2个应用区，容量均为512Kbit，密码计数器值为4，卡片总密码2字节，一区擦除密码6字节，二区擦除密码4字节制作标准：ISO 7816应用范围：医疗保险、数据存储、网吧收费、身份认证、电子钱包5、AT88SC1604A存储容量：加密存储卡，16Kbit特点：1个公用区和4个应用区，四个应用区中，各个分区都有各自的密码和擦除密码，且各个分区中均有各自的密码计数器，密码均为2字节，密码计数器值为8制作标准：ISO 7816应用范围：医疗保险、数据存储、网吧收费、身份认证、电子钱包6、SLE 4428存储容量：加密存储卡，1K字节特点：卡始终可读，写卡必须通过密码校验，2字节可编程密码，密码错误计数值为8，可对整张卡片写保护制作标准：ISO 7816应用范围：医疗保险、数据存储、网吧收费、高速公路收费、电子钱包7、SLE 5542（SLE4442升级）存储容量：加密存储卡，256字节特点：卡始终可读，写卡必须通过密码校验，3字节可编程密码，密码错误计数值为3，可对卡片前32字节写保护制作标准：ISO 7816应用范围：医疗保险、数据存储、网吧收费、高速公路收费、电子钱包8、Philips Mifare 1 S50存储容量：8Kbit,16个扇区，每区4块，每块16字节，以块为存取单位，每个扇区有独立的一组密码及访问控制，有32位全球唯一序列号工作频率：13.56MHZ通讯速度：106kbps读写距离：2.5-10CM制作标准：ISO 14443应用范围：企业/校园一卡通、公交一卡通、高速公路收费、停车场、小区管理、电子钱包9、Philips Mifare S70存储容量：32Kbit,40个扇区，其中32个扇区每扇区64个字节容量，分为4块，每块16字节；8个扇每扇区256个字节，分为16块，每块16个字节，以块为存取单位，每个扇区有独立的一组密码及访问控制，有32位全球唯一序列号码工作频率：13.56MHZ通讯速度：106Kbps读写距离：2.5-10CM制作标准：ISO 14443应用范围：高容量要求的校园一卡通、城市一卡通、电子钱包10、Mifare Ultra Light存储容量：512bit,16块，每块4字节，唯一的7字节序列号，32位用户可定义的一次性编程区域，384位用户读、写区域工作频率：13.56MHZ通讯速度：106Kbps读写距离：在100MM以内（与天线有关）制作标准：ISO 14443应用范围：一次性票卡，如地铁、城际高铁11、Ti 2048存储容量：2Kbit,分为64×32个区段，唯一64位序列号工作频率：13.56MHZ通讯速度：106Kbps制作标准：ISO 15693应用范围：公交，泊车，身份认证，考勤管理，门票，一卡通付费，产品标识12、ATMEL T5567（原T5557升级版）存储容量：330bit, 10分区,每个分区33bit,8位密码工作频率:125KHZ读写距离:3-10CM制作标准：应用范围:感应式智能门锁、企业一卡通系统、门禁、通道系统13、EM4001 ID卡工作频率：125KHZ读写距离：2—15CM应用范围：身份识别、考勤系统、门禁系统、财物标识14、SLE 4442存储容量：加密存储卡，256bit,特点：卡始终可读，写卡必须通过密码校验，3字节可编程密码，密码错误计数值为3，可对卡片前32字节写保护制作标准：ISO 7816应用范围：医疗保险、数据存储、网吧收费、高速公路收费、电子钱包15、CPU卡存储容量：8K、16K、32K等特点：自带芯片操作系统（COS），安全性能高，可自定义卡片文件结构、容量大、速度快、支持一卡多用。

MICROCHIP PIC24F 系列说明书

在 FCKSM1 配置位置 1 时，将 CLKLOCK 位（OSCCON<7>）置 1 可防止发生时钟切换。如果 FCKSM1 位清零，则 CLKLOCK 位状态会被忽略，器件可以发生时钟切换。 LOCK 状态位（OSCCON<5>）是只读位，指示 PLL 电路的状态。在 PLL 实现频率锁定时该位置 1，在产生有效的时钟切换序列时该位复位。每当 PLL 不与振荡器配合用作当前时钟源时，它读为 0。 CF 状态位（OSCCON<3>）是可读 / 可清零状态位，指示发生时钟故障。每当发生有效的时钟切换时，该位复位。 SOSCEN 控制位（OSCCON<1>）用于使能或禁止 32 kHz SOSC 晶体振荡器。 OSWEN 控制位（OSCCON<0>）用于启动时钟切换操作。OSWEN 在成功进行时钟切换或任何冗余时钟切换后自动清零，并在切换到 FRC 后由 FSCM 清零。
超前信息
© 2007 Microchip Technology Inc.
第 6 章振荡器
6.2 CPU 时钟分配
系统时钟源可以由以下 4 种之一提供：
6
振荡器
• • • •
OSC1 和 OSC2 引脚上的主振荡器（POSC） SOSCI 和 SOSCO 引脚上的辅助振荡器内部快速 RC 振荡器（FRC）内部低功耗 RC 振荡器（LPRC）
DS39700A_CN 第 6-4 页
超前信息
© 2007 Microchip Technology Inc.
第 6 章振荡器
6.4 控制寄存器
振荡器的操作由 3 个特殊功能寄存器控制：
6
振荡器
• OSCCON • CLKDIV • OSCTUN

24C02资料

概述：
美国微芯科技公司（Microchip Technology Inc.）生产的电擦写式只读存储器系列 24CXX、 24LCXX、 24AAXX 和 24FCXX （24XX*）容量范围为 128 位到 512 千位。该系列器件支持 2 线串行接口，以 x8 位存储器块进行组合。低电压设计允许工作电压最低可至 1.8V（适用 24AAXX 器件），待机电流和工作电流分别为 1 µA 和 1 mA。容量为 1 千位以及超过 1 千位的器件具有页写入能力。功能性地址线允许连接到同一条总线上的器件数目最多可达 8 个。整个 24XX 系列产品提供标准的 8 引脚 PDIP、表面贴片 SOIC、 TSSOP 和 MSOP 封装。大部分容量为 128 位到 16 千位的器件还提供 5 引脚 SOT-23 封装。另外还提供 DFN 封装（2x3mm 或 5x6mm）。所有封装皆为无铅（雾锡）封装。
24AA00/24LC00/24C00 24AA014/24LC014 24AA02/24LC02B 24AA024/24LC024 24AA04/24LC04B 24AA16/24LC16B 24AA64/24LC64 24AA256/24LC256/24FC256
24AA01/24LC01B 24C01C 24C02C 24AA025/24LC025 24AA08/24LC08B 24AA32A/24LC32A 24AA128/24LC128/24FC128 24AA512/24LC512/24FC512
封装类型（1）
PDIP/SOIC
A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP(3) SCL SDA A0 A1 A2 VSS
（2） TSSOP/MSOP

MEMORY存储芯片PC28F128G18AE中文规格书

READ PAGE MULTI-PLANE (00h-32h)The READ PAGE MULTI-PLANE (00h-32h) command queues a plane to transfer datafrom the NAND flash array to its cache register. This command can be issued one ormore times. Each time a new plane address is specified, that plane is also queued fordata transfer. The READ PAGE (00h-30h) command is issued to select the final planeand to begin the read operation for all previously queued planes. All queued planes willtransfer data from the NAND Flash array to their cache registers.To issue the READ PAGE MULTI-PLANE (00h-32h) command, write 00h to the com-mand register, then write five address cycles to the address register, and conclude bywriting 32h to the command register. The column address in the address specified isignored.After this command is issued, R/B# goes LOW and the die (LUN) is busy(RDY = 0, ARDY = 0) for t DBSY. After t DBSY, R/B# goes HIGH and the die (LUN) is ready(RDY = 1, ARDY = 1). At this point, the die (LUN) and block are queued for data transferfrom the array to the cache register for the addressed plane. During t DBSY, the only val-id commands are status operations (70h, 78h) and reset commands (FFh, FCh). Follow-ing t DBSY, to continue the MULTI-PLANE READ operation, the only valid commandsare status operations (70h, 78h), READ PAGE MULTI-PLANE (00h-32h), READ PAGE(00h-30h), and READ PAGE CACHE RANDOM (00h-31h).Additional READ PAGE MULTI-PLANE (00h-32h) commands can be issued to queueadditional planes for data transfer.If the READ PAGE (00h-30h) command is used as the final command of a MULTI-PLANE READ operation, data is transferred from the NAND Flash array for all of theaddressed planes to their respective cache registers. When the die (LUN) is ready(RDY = 1, ARDY = 1), data output is enabled for the cache register linked to the planeaddressed in the READ PAGE (00h-30h) command. When the host requests data output,it begins at the column address specified in the READ PAGE (00h-30h) command. Toenable data output in the other cache registers, use the CHANGE READ COLUMN EN-HANCED (06h-E0h) command. Additionally, the CHANGE READ COLUMN (05h-E0h)command can be used to change the column address within the currently selected plane.If the READ PAGE CACHE SEQUENTIAL (31h) is used as the final command of a MULTI-PLANE READ CACHE operation, data is copied from the previously read operation fromeach plane to each cache register and then data is transferred from the NAND Flasharray for all previously addressed planes to their respective data registers. When the die(LUN) is ready (RDY = 1, ARDY = 0), data output is enabled. The CHANGE READ COL-UMN ENHANCED (06h-E0h) command is used to determine which cache registeroutputs data first. To enable data output in the other cache registers, use the CHANGEREAD COLUMN ENHANCED (06h-E0h) command. Additionally, the CHANGE READCOLUMN (05h-E0h) command can be used to change the column address within thecurrently selected plane.If the READ PAGE CACHE RANDOM (00h-31h) command is used as the final commandof a MULTI-PLANE READ CACHE operation, data is copied from the previously readoperation from the data register to the cache register and then data is transferred fromthe NAND Flash array for all of the addressed planes to their respective data registers.When the die (LUN) is ready (RDY = 1, ARDY = 0), data output is enabled. The CHANGEREAD COLUMN ENHANCED (06h-E0h) command is used to determine which cacheregister outputs data first. To enable data output in the other cache registers, use theCHANGE READ COLUMN ENHANCED (06h-E0h) command. Additionally, the16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Read Operations16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NANDSynchronous Interface Timing DiagramsCOPYBACK PROGRAM (85h–10h)The COPYBACK PROGRAM (85h-10h) command is functionally identical to the PRO-GRAM PAGE (80h-10h) command, except that when 85h is written to the commandregister, cache register contents are not cleared. See PROGRAM PAGE (80h-10h)(page 89) for further details.Figure 64: COPYBACK PROGRAM (85h–10h) OperationCycle type DQ[7:0]RDYFigure 65: COPYBACK PROGRAM (85h-10h) with CHANGE WRITE COLUMN (85h) OperationCycle type DQ[7:0]RDYCycle type DQ[7:0]RDY COPYBACK READ MULTI-PLANE (00h-32h)The COPYBACK READ MULTI-PLANE (00h-32h) command is functionally identical tothe READ PAGE MULTI-PLANE (00h-32h) command, except that the 35h command iswritten as the final command. The complete command sequence for the COPYBACKREAD PAGE MULTI-PLANE is 00h-32h-00h-35h. See READ PAGE MULTI-PLANE(00h-32h) (page 87) for further details.16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Copyback Operations。

24LC128

TABLE 1-1 PIN FUNCTION TABLE
Name
Function
A0, A1, A2 User Conﬁgurable Chip Selects VSS Ground SDA Serial Data SCL Serial Clock WP Write Protect Input VCC +1.8 to 5.5V (24AA128) +2.5 to 5.5V (24LC128) +4.5 to 5.5V (24C128)
© 1997 Microchip Technology Inc.
Preliminary
DS21191A-page 1
24xx128
1.0 ELECTRICAL CHARACTERISTICS
1.1 Maximum Ratings*
VCC.................................................................................................7.0V All inputs and outputs w.r.t. VSS ............................. -0.6V to VCC +1.0V Storage temperature ...................................................-65°C to +150°C Ambient temp. with power applied...............................-65°C to +125°C Soldering temperature of leads (10 seconds) ........................... +300°C ESD protection on all pins...........................................................≥ 4 kV

金属化聚丙烯薄膜介质电容器商品说明书

规格承认书SPECIFICATION FOR APPROV AL产品名称:金属化聚丙烯薄膜介质电容器Product Name:Metallized polypropylene film dielectric capacitor产品型号:MPBHProduct Type:MPBH产品编码:Product Code:客户名称:深圳华秋电子有限公司Customers Name:客户编码:Customers Code:日期:2019.07.31Issue Date:2019.07.31浙江七星电子股份有限公司Zhejiang Qixing Electronics Corp.,Ltd.地址：中国浙江省长兴县煤山镇发展大道50号No.50,Development Avenue，Meishan Town,Changxing County,Zhejiang Province,P.R.ChinaTel：************Fax：************CBB21/22CBB21/22金属化聚丙烯薄膜介质电容器CBB21/22Metallized polypropylene film dielectric capacitor■特点●金属化聚丙烯膜■Characteristic:●Metallized polypropylene film.●高频损耗小●内部温升小●Low loss at high frequency.●Internal temperature rise ■主要用途●广泛用于高频、直流、交流和脉冲电流中●适用于大屏幕显示器的S 校正电路●适用于各种高频、大电流场合■Main purpose●Widely used in high frequency,dc,ac and pulsecurrent.●S correction circuit for large screen display.●Suitable for high frequency and large currentmotor suppression interference■技术要求Technical requirements 引用标准Reference criteriaGB/T 10190〔IEC 60384-16〕气候类别Climate category 40/105/21额定温度Rated temperature 85℃工作温度Operating temperature -40℃~105℃〔+85℃to+105℃：decreasing factor 1.25%per ℃for Ur(dc)〕额定电压Rated voltage100V ；250v ；400v ；630v ；1000V ；1250V 电容量范围Electricity capacity range 0.001μF~3.3μF电容量偏差Capacitance deviation ±5%〔J 〕,±10%〔K 〕,±20%〔M 〕耐电压Voltage resistance 1.6Ur 〔5s 〕损耗角正切值Loss angle tangent≤8×10-4（+20℃±5℃,1kH z ）≤15×10-4（+20℃±5℃,10kH z ）绝缘电阻Insulation resistanceR ≥30000M Ω，C N ≤0.33μF（20℃，100V,1min ）RC N ≥10000S ，C N ＞0.33μF最大脉冲爬升：Maximum Pulse Climbing Rate ：若实际工作电压U 比额定电压Ur 低，电容器可工作在更高的dv/dt 场合，这样dv/dt 允许值应为右表值乘以Ur/UIf the actual working voltage U is lower than the rated voltage Or,the capacitor can work in a higher dv/dt case so that the dv/dt allowed value should be multiplied by the right table value Ur/UPattern IIUr 〔V 〕dV/dt 〔V/μs 〕P=7.5P=10P=15P=22.5250V 660560310130400V 900780600300630V 150012009004001250V25002200--■电容器外形尺寸Capacitor dimensionsMPBH系列100VDC100VDC〔63VAC〕/250VDC〔160VAC〕电容量CAP电容器外形尺寸Capacitordimensions电容器代码Part number电容量CAP电容器外形尺寸Capacitordimensions电容器代码Part number T H W PΦd T H W PΦd0.2 3.58.09.57.50.5MPB0100V204J*0.010 4.07.79.87.50.6B210***V103*** 0.25 4.07.89.57.50.5MPB0100V254J*0.015 4.27.89.87.50.6B210***V153*** 0.3 3.78.49.77.50.5MPB0100V304J*0.022 4.88.49.87.50.6B210***V223*** 0.33 3.79.79.77.50.5MPB0100V334J*0.033 4.27.99.87.50.6B210***V333*** 0.35 3.79.49.57.50.5MPB0100V354J*0.047 4.88.59.87.50.6B210***V473*** 0.39 4.310.39.57.50.5MPB0100V394J*0.068 4.88.512.5100.6B210***V683*** 0.4 4.010.610.57.50.5MPB0100V404J*0.10 4.78.312.5100.6B210***V104*** 0.42 4.010.59.57.50.5MPB0100V424J*0.15 5.28.912.5100.6B210***V154*** 0.4 3.51012.5100.5MPB0100V404J*0.22 6.19.812.5100.6B210***V224***0.33 5.81117.5150.6B210***V334***0.47 6.61217.5150.6B210***V474***0.567.212.417.5150.6B210***V564***0.687.813.517.5150.8B210***V684***0.828.514.217.5150.8B210***V824***1.09.315.017.5150.8B210***V105***1.27.514.825.222.50.8B210***V125***1.58.315.625.222.50.8B210***V155***2.29.918.325.222.50.8B210***V225***3.312.120.525.222.50.8B210***V335***400VDC〔200VAC〕630VDC〔220VAC〕电容量CAP电容器外形尺寸Capacitor dimensions电容器代码Part number电容量CAP电容器外形尺寸Capacitor dimensions电容器代码Part number T H W PΦd T H W PΦd0.010 4.17.89.87.50.6B210400V103***0.001 4.37.9107.50.6B210630V102*** 0.015 4.78.49.87.50.6B210400V153***0.01 4.17.812.5100.6B210630V103*** 0.022 5.59.19.87.50.6B210400V223***0.015 4.78.312.5100.6B210630V153*** 0.033 4.88.512.3100.6B210400V333***0.022 5.38.912.5100.6B210630V223*** 0.047 5.49.012.5100.6B210400V473***0.033 6.29.912.5100.6B210630V333*** 0.068 5.49.112.5100.6B210400V683***0.047 5.610.817.5150.6B210630V473*** 0.10 6.41012.5100.6B210400V104***0.068 6.511.717.5150.6B210630V683*** 0.15 6.011.217.5150.6B210400V154***0.107.612.817.5150.8B210630V104*** 0.227.012.217.5150.6B210400V224***0.159.014.717.5150.8B210630V154*** 0.338.414.117.5150.8B210400V334***0.227.915.225.222.50.8B210630V224*** 0.479.815.517.5150.8B210400V474***0.331016.825.222.50.8B210630V334*** 0.567.915.225.222.50.8B210400V564***0.4711.818.625.222.50.8B210630V474*** 0.689.115.925.222.50.8B210400V684***0.5612.819.625.222.50.8B210630V564***0.821016.725.222.50.8B210400V824***1.010.917.725.222.50.8B210400V105***■承认规格登记表Size and specification●尺寸（mm）（T*H*W）max---最大宽度Hmax---最大高度Tmax---最大厚度P-----脚距±0.5L-----脚长±2.0●.规格Specification:序号NO客户料号CustomerNO 七星料号Spec NO规格型号Specification尺寸SizeT*H*W*P线径Line脚长Length备注Note1-MPB0100V204J7ABLTY**MPBH-100V204J 3.8*8.0*9.8*7.50.524镀锡铜线2-MPB0100V204J10BLTY**MPBH-100V204J 3.6*6.8*12.5*100.524镀锡铜线-MPB0100V334J7ABLTY**MPBH-100V334J 3.7*9.7*9.8*7.50.524镀锡铜线-MPB0100V334J10BLTY**MPBH-100V334J 3.6*9.0*12.5*100.524镀锡铜线-MPB0100V404J7ABLTY**MPBH-100V404J 4.0*10.6*9.8*7.50.524镀锡铜线-MPB0100V404J10BLTY**MPBH-100V404J 3.5*10*12.5*100.524镀锡铜线■电容器编码说明Capacitor coding specification●20位电容器代码如下：The code of the20-bit capacitor at the center is as follows:CBB21/22■特性曲线图Characteristic curve电容量随温度变化的曲线﹝1KHz ﹞电容量随频率变化的曲线Is the temperature curve of the capacitance Capacitance may vary in frequency损耗角正切值随温度变化的曲线﹝1KHz ﹞损耗角正切值随频率变化的曲线The curve of the tangent of loss Angle with temperatureCurve of the change of the tangent value of the loss angle with frequency绝缘电阻随温度变化的曲线﹝1KHz ﹞The curve of insulation resistance totemperature电容量随温度变化的曲线(1KHz)电容量随频率变化的曲线损耗角正切值随温度变化的曲线(1KHz)损耗角正切值随频率变化的曲线绝缘电阻随温度变化的曲线(1KHz)■性能及测试方法Performance and test methodsNo项目Item性能与判据Performance and criteria测试方法Test method(IEC60384-2)1电容量允许偏差Capacitance tolerance±5%〔J〕,±10%〔K〕,±20%〔M〕2损耗角的正切Tangent of the loss angle tgδ≤0.0008〔1KHz〕tgδ≤0.0015〔10KHz〕典型测量频率：1KHzTypical measuringfrequency:1KHz3耐电压Dielectric strength无飞弧或击穿There shall be no breakdown or flashover1.4Ur2sec4绝缘电阻Insulation resistance R≥30000MΩ,Cn≤0.33μFIR≥10000S Cn＞0.33μF充电电压Ur＜500V Charging voltage100v环境温度20℃，测量时间60S充电电压Ur＞500V Charging voltage500v环境温度20℃，测量时间60S5可焊性Solder ability Good quality of tinning镀锡良好锡炉温度Soldre temperature245℃±5℃浸渍时间Immersion time2.S±0.5S6初始测量Initialmeasurement电容量与损耗Capacitance&tgδ〔10KHz〕引线抗拉强度强度Terminal strength外观无可见损伤There shall be no visible damage拉力试验Tension Ual:拉力Pull：φd=0.5mm5Nφd=0.6mm10N弯曲试验bend Ub:弯力The qull of bendφd=0.5mm2.5Nφd=0.6mm5N端子应向每个方向弯曲2次The terminals shall be bent2times in each direction耐焊接热Resistance to solder heat无可见损伤There shall be no visible damage锡炉温度Soldre temperature260℃±5℃浸渍时间Immersion time10.S±1S最后的测量Final measurementΔC/C≤±2%相对于初始值Relative to the initialvalue.tgδ≤0.0015〔10KHz〕7初始测量Initial measurement电容量与损耗Capacitance&tgδ〔10KHz〕温度快速变化Rapid change of temperature外观无可见损伤There shall be no visible damageΘa=-55℃Θb=+125℃持续的时间=30分钟■最大电压﹝Vr.m.s〕/频率表〔正弦波形/环境温度≤40°C﹞MAX.VOLTAGE(Vr.m.s.)VERSUS FREQUENCY(sinusoidal wave-form/Th≤40°C)●径向编带包装箱尺寸Box sizes for Ammo-packA=48±3;B=260±3;C=330±3■波峰焊接Wave soldering电容器的内部温度必须保持如下:聚酯:预热温度+125°C 聚丙烯:预热温度+100°C 单波峰焊接焊接浴温度:T=260°C停留时间:5秒双波峰焊接焊接浴温度:T=260°C停留时间:5秒由于不同的焊接工艺和热量要求图形仅作为推荐Internal temperature of the capacitor mustbe kept as follows:Polyester:preheating:T max.T125°CPolypropylene:preheating:T max.T100°CSingle wave solderingSoldering bath temperature:T260°CDwell time:t5secDouble wave solderingSoldering bath temperature:T260°CDwell time:St5secDue to different soldering processes andheat requirements the graphs are to beregarded as a recommendation only.双波焊接的典型温度/时间图Typical temperature/time graph for double wave soldering。

微芯,DSPIC30F系列,规格书,Datasheet 资料

© 2010 Microchip Technology Inc.DS70102K-page1dsPIC30F1.0OVERVIEW AND SCOPEThis document defines the programming specification for the dsPIC30F family of Digital Signal Controllers (DSCs). The programming specification is required only for the developers of third-party tools that are used to program dsPIC30F devices. Customers using dsPIC30F devices should use development tools that already provide support for device programming.This document includes programming specifications for the following devices:•dsPIC30F2010/2011/2012•dsPIC30F3010/3011/3012/3013/ 3014•dsPIC30F4011/4012/4013•dsPIC30F5011/5013/5015/5016•dsPIC30F6010/6011/6012/6013/6014/6015•dsPIC30F6010A/6011A/6012A/6013A/6014A2.0PROGRAMMING OVERVIEW OF THE dsPIC30FThe dsPIC30F family of DSCs contains a region of on-chip memory used to simplify device programming. This region of memory can store a programming executive, which allows the dsPIC30F to be programmed faster than the traditional means. Once the programming executive is stored to memory by an external programmer (such as Microchip’s MPLAB ®ICD 2, MPLAB PM3, PRO MATE ® II, or MPLAB REAL ICE™), it can then interact with the external programmer to efficiently program devices.The programmer and programming executive have a master-slave relationship, where the programmer is the master programming device and the programming executive is the slave, as illustrated in Figure 2-1.FIGURE 2-1:OVERVIEW OF dsPIC30F PROGRAMMINGTwo different methods are used to program the chip in the user’s system. One method uses the Enhanced In-Circuit Serial Programming™ (Enhanced ICSP™) protocol and works with the programming executive. The other method uses In-Circuit Serial Programming (ICSP) protocol and does not use the programming executive.The Enhanced ICSP protocol uses the faster, high-voltage method that takes advantage of the programming executive. The programming executive provides all the necessary functionality to erase, program and verify the chip through a small command set. The command set allows the programmer to program the dsPIC30F without having to deal with the low-level programming protocols of the chip.The ICSP programming method does not use the programming executive. It provides native, low-level programming capability to erase, program and verify the chip. This method is significantly slower because it uses control codes to serially execute instructions on the dsPIC30F device.This specification describes the ICSP and Enhanced ICSP programming methods. Section 3.0 “Programming Executive Application” describes the programming executive application and Section 5.0 “Device Programming” describes its application programmer’s interface for the hostprogrammer.Section 11.0 “ICSP™ Mode”describes the ICSP programming method.2.1 Hardware RequirementsIn ICSP or Enhanced ICSP mode, the dsPIC30F requires two programmable power supplies: one for V DD and one for MCLR. For Bulk Erase programming, which is required for erasing code protection bits, V DD must be greater than 4.5 volts. Refer to Section 13.0 “AC/DC Characteristics and Timing Requirements”for additional hardware parameters.Programmer dsPIC30F DeviceProgramming Executive On-chip Memory 2dsPIC30F Flash Programming SpecificationdsPIC30F Flash Programming SpecificationDS70102K-page 2© 2010 Microchip Technology Inc.2.2Pins Used During ProgrammingThe pins identified in Table 2-1 are used for device programming. Refer to the appropriate device data sheet for complete pin descriptions.TABLE 2-1:dsPIC30F PIN DESCRIPTIONS DURING PROGRAMMINGPin Name Pin TypePin Description MCLR/V PP P Programming Enable V DD P Power Supply V SS P Ground PGC I Serial Clock PGDI/OSerial Data2.3Program Memory MapThe program memory space extends from 0x0 to 0xFFFFFE. Code storage is located at the base of the memory map and supports up to 144 Kbytes (48K instruction words). Code is stored in three, 48 Kbyte memory panels that reside on-chip. Table 2-2 shows the location and program memory size of each device.Locations 0x800000 through 0x8005BE are reserved for executive code memory. This region stores either the programming executive or debugging executive. The programming executive is used for device programming, while the debug executive is used for in-circuit debugging. This region of memory cannot be used to store user code.Locations 0xF80000 through 0xF8000E are reserved for the Configuration registers. The bits in these registers may be set to select various device options, and are described in Section 5.7 “Configuration Bits Programming”.Locations 0xFF0000 and 0xFF0002 are reserved for the Device ID registers. These bits can be used by the programmer to identify what device type is being programmed and are described in Section 10.0 “Device ID”. The device ID reads out normally, even after code protection is applied.Figure 2-2 illustrates the memory map for the dsPIC30F devices.2.4Data EEPROM MemoryThe Data EEPROM array supports up to 4 Kbytes of data and is located in one memory panel. It is mapped in program memory space, residing at the end of User Memory Space (see Figure 2-2). Table 2-2 shows the location and size of data EEPROM in each device.TABLE 2-2:CODE MEMORY AND DATA EEPROM MAP AND SIZE DeviceCode Memory map (Size in Instruction Words)Data EEPROM Memory Map(Size in Bytes)dsPIC30F20100x000000-0x001FFE (4K)0x7FFC00-0x7FFFFE (1K)dsPIC30F20110x000000-0x001FFE (4K)None (0K)dsPIC30F20120x000000-0x001FFE (4K)None (0K)dsPIC30F30100x000000-0x003FFE (8K)0x7FFC00-0x7FFFFE (1K)dsPIC30F30110x000000-0x003FFE (8K)0x7FFC00-0x7FFFFE (1K)dsPIC30F30120x000000-0x003FFE (8K)0x7FFC00-0x7FFFFE (1K)dsPIC30F30130x000000-0x003FFE (8K)0x7FFC00-0x7FFFFE (1K)dsPIC30F30140x000000-0x003FFE (8K)0x7FFC00-0x7FFFFE (1K)dsPIC30F40110x000000-0x007FFE (16K)0x7FFC00-0x7FFFFE (1K)dsPIC30F40120x000000-0x007FFE (16K)0x7FFC00-0x7FFFFE (1K)dsPIC30F40130x000000-0x007FFE (16K)0x7FFC00-0x7FFFFE (1K)dsPIC30F50110x000000-0x00AFFE (22K)0x7FFC00-0x7FFFFE (1K)dsPIC30F50130x000000-0x00AFFE (22K)0x7FFC00-0x7FFFFE (1K)dsPIC30F50150x000000-0x00AFFE (22K)0x7FFC00-0x7FFFFE (1K)dsPIC30F50160x000000-0x00AFFE (22K)0x7FFC00-0x7FFFFE (1K)dsPIC30F60100x000000-0x017FFE (48K)0x7FF000-0x7FFFFE (4K)dsPIC30F6010A 0x000000-0x017FFE (48K)0x7FF000-0x7FFFFF (4K)dsPIC30F60110x000000-0x015FFE (44K)0x7FF800-0x7FFFFE (2K)dsPIC30F6011A 0x000000-0x015FFE (44K)0x7FF800-0x7FFFFE (2K)dsPIC30F60120x000000-0x017FFE (48K)0x7FF000-0x7FFFFE (4K)dsPIC30F6012A 0x000000-0x017FFE (48K)0x7FF000-0x7FFFFE (4K)dsPIC30F60130x000000-0x015FFE (44K)0x7FF800-0x7FFFFE (2K)dsPIC30F6013A 0x000000-0x015FFE (44K)0x7FF800-0x7FFFFE (2K)dsPIC30F60140x000000-0x017FFE (48K)0x7FF000-0x7FFFFE (4K)dsPIC30F6014A 0x000000-0x017FFE (48K)0x7FF000-0x7FFFFE (4K)dsPIC30F60150x000000-0x017FFE (48K)0x7FF000-0x7FFFFE (4K)Legend:I = Input, O = Output, P = Power© 2010 Microchip Technology Inc.DS70102K-page 3dsPIC30F Flash Programming SpecificationFIGURE 2-2:PROGRAM MEMORY MAPU s e r M e m o r y S p a c e000000Configuration RegistersUser Flash Code Memory 018000017FFE C o n f i g u r a t i o n M e m o r y S p a c eData EEPROM (48K x 24-bit)(2K x 16-bit)800000F80000(8 x 16-bit)F8000E F80010Device ID FEFFFE FF0000FFFFFEReservedF7FFFE Reserved7FF0007FEFFE 8005BE 8005C0Executive Code Memory7FFFFE ReservedFF0002FF0004Reserved(2 x 16-bit)(Reserved)Note:The address boundaries for user Flash code memory and data EEPROM are device-dependent.Unit ID (32 x 24-bit)8005FE 800600dsPIC30F Flash Programming SpecificationDS70102K-page 4© 2010 Microchip Technology Inc.3.0PROGRAMMING EXECUTIVE APPLICATION3.1Programming Executive OverviewThe programming executive resides in executive memory and is executed when Enhanced ICSP Programming mode is entered. The programming exec-utive provides the mechanism for the programmer (host device) to program and verify the dsPIC30F, using a simple command set and communication protocol.The following capabilities are provided by the programming executive:•Read memory-Code memory and data EEPROM -Configuration registers -Device ID •Erase memory-Bulk Erase by segment -Code memory (by row)-Data EEPROM (by row)•Program memory -Code memory-Data EEPROM-Configuration registers •Query-Blank Device-Programming executive software versionThe programming executive performs the low-level tasks required for erasing and programming. This allows the programmer to program the device by issuing the appropriate commands and data.The programming procedure is outlined in Section 5.0 “Device Programming”.3.2Programming Executive Code MemoryThe programming executive is stored in executive code memory and executes from this reserved region of memory. It requires no resources from user code memory or data EEPROM.3.3Programming Executive Data RAMThe programming executive uses the device’s data RAM for variable storage and program execution. Once the programming executive has run, no assumptions should be made about the contents of data RAM.4.0CONFIRMING THE CONTENTS OF EXECUTIVE MEMORYBefore programming can begin, the programmer must confirm that the programming executive is stored in exec-utive memory. The procedure for this task is illustrated in Figure 4-1.First, ICSP mode is entered. The unique application ID word stored in executive memory is then read. If the programming executive is resident, the application ID word is 0xBB, which means programming can resume as normal. However, if the application ID word is not 0xBB, the programming executive must be programmed to Executive Code memory using the method described in Section 12.0 “Programming the Programming Executive to Memory”.Section 11.0 “ICSP™ Mode” describes the process for the ICSP programming method. Section 11.13 “Reading the Application ID Word” describes the procedure for reading the application ID word in ICSP mode.FIGURE 4-1:CONFIRMING PRESENCE OF THE PROGRAMMING EXECUTIVEIsStartEnter ICSP™ ModeApplication ID0xBB?Resident in MemoryYesNoProg. Executive is Application ID Read the be ProgrammedProg. Executive must from Address 0x8005BEFinishdsPIC30F Flash Programming Specification5.0DEVICE PROGRAMMING5.1Overview of the ProgrammingProcessOnce the programming executive has been verified in memory (or loaded if not present), the dsPIC30F can be programmed using the command set shown in Table 5-1. A detailed description for each command is provided in Section 8.0 “Programming Executive Commands”.TABLE 5-1:COMMAND SET SUMMARY Command DescriptionSCHECK Sanity checkREADD Read data EEPROM, Configurationregisters and device IDREADP Read code memoryPROGD Program one row of data EEPROMand verifyPROGP Program one row of code memory andverifyPROGC Program Configuration bits and verify ERASEB Bulk Erase, or erase by segment ERASED Erase data EEPROMERASEP Erase code memoryQBLANK Query if the code memory and dataEEPROM are blankQVER Query the software versionA high-level overview of the programming process is illustrated in Figure 5-1. The process begins by enter-ing Enhanced ICSP mode. The chip is then bulk erased, which clears all memory to ‘1’ and allows the device to be programmed. The Chip Erase is verified before programming begins. Next, the code memory, data Flash and Configuration bits are programmed. As these memories are programmed, they are each verified to ensure that programming was successful. If no errors are detected, the programming is complete and Enhanced ICSP mode is exited. If any of the verifications fail, the procedure should be repeated, starting from the Chip Erase.If Advanced Security features are enabled, then individual Segment Erase operations need to be performed, based on user selections (i.e., based on the specific needs of the user application). The specific operations that are used typically depend on the order in which various segments need to be programmed for a given application or system.Section 5.2 “Entering Enhanced ICSP Mode”through Section 5.8 “Exiting Enhanced ICSP Mode”describe the programming process in detail.FIGURE 5-1:PROGRAMMING FLOWStartProgram andProgram andProgram and verifyConfiguration bitsFinishverify codeverify dataEnter EnhancedExit Enhanced ICSPModePerform ChipEraseProgramConfigurationregisters toICSP™ modedefault value© 2010 Microchip Technology Inc.DS70102K-page 5dsPIC30F Flash Programming SpecificationDS70102K-page 6© 2010 Microchip Technology Inc.5.2Entering Enhanced ICSP ModeThe Enhanced ICSP mode is entered by holding PGC and PGD high, and then raising MCLR/V PP to V IHH (high voltage), as illustrated in Figure 5-2. In this mode, the code memory, data EEPROM and Configuration bits can be efficiently programmed using the program-ming executive commands that are serially transferred using PGC and PGD.FIGURE 5-2:ENTERING ENHANCED5.3Chip EraseBefore a chip can be programmed, it must be erased. The Bulk Erase command (ERASEB ) is used to perform this task. Executing this command with the MS command field set to 0x3 erases all code memory, data EEPROM and code-protect Configuration bits. The Chip Erase process sets all bits in these three memory regions to ‘1’.Since non-code-protect Configuration bits cannot be erased, they must be manually set to ‘1’ using multiple PROGC commands. One PROGC command must be sent for each Configuration register (see Section 5.7 “Configuration Bits Programming”).If Advanced Security features are enabled, then indi-vidual Segment Erase operations would need to be performed, depending on which segment needs to be programmed at a given stage of system programming. The user should have the flexibility to select specific segments for programming.Note:The Device ID registers cannot be erased. These registers remain intact after a Chip Erase is performed.5.4Blank CheckThe term “Blank Check” means to verify that the device has been successfully erased and has no programmed memory cells. A blank or erased memory cell reads as ‘1’. The following memories must be blank checked: •All implemented code memory •All implemented data EEPROM•All Configuration bits (for their default value)The Device ID registers (0xFF0000:0xFF0002) can be ignored by the Blank Check since this region stores device information that cannot be erased. Additionally, all unimplemented memory space should be ignored from the Blank Check.The QBLANK command is used for the Blank Check. It determines if the code memory and data EEPROM are erased by testing these memory regions. A ‘BLANK’ or ‘NOT BLANK’ response is returned. The READD command is used to read the Configuration registers. If it is determined that the device is not blank, it must be erased (see Section 5.3 “Chip Erase”) before attempting to program the chip.Note 1:The sequence that places the device intoEnhanced ICSP mode places all unused I/Os in the high-impedance state.2:Before entering Enhanced ICSP mode,clock switching must be disabled using ICSP , by programming the FCKSM<1:0> bits in the FOSC Configuration register to ‘11’ or ‘10’.3:When in Enhanced ICSP mode, the SPIoutput pin (SDO1) will toggle while the device is being programmed.dsPIC30F Flash Programming Specification5.5Code Memory Programming5.5.1OVERVIEWThe Flash code memory array consists of 512 rows ofthirty-two, 24-bit instructions. Each panel stores 16Kinstruction words, and each dsPIC30F device haseither 1, 2 or 3 memory panels (see Table 5-2).TABLE 5-2:DEVICE CODE MEMORY SIZEDevice Code Size(24-bitWords)NumberofRowsNumberofPanelsdsPIC30F20104K1281 dsPIC30F20114K1281 dsPIC30F20124K1281 dsPIC30F30108K2561 dsPIC30F30118K2561 dsPIC30F30128K2561 dsPIC30F30138K2561 dsPIC30F30148K2561 dsPIC30F401116K5121 dsPIC30F401216K5121 dsPIC30F401316K5121 dsPIC30F501122K7042 dsPIC30F501322K7042 dsPIC30F501522K7042 dsPIC30F501622K7042 dsPIC30F601048K15363 dsPIC30F6010A48K15363 dsPIC30F601144K14083 dsPIC30F6011A44K14083 dsPIC30F601248K15363 dsPIC30F6012A48K15363 dsPIC30F601344K14083 dsPIC30F6013A44K14083 dsPIC30F601448K15363 dsPIC30F6014A48K15363 dsPIC30F601548K153635.5.2PROGRAMMING METHODOLOGY Code memory is programmed with the PROGP command. PROGP programs one row of code memory to the memory address specified in the command. The number of PROGP commands required to program a device depends on the number of rows that must be programmed in the device.A flowchart for programming of code memory is illus-trated in Figure 5-3. In this example, all 48K instruction words of a dsPIC30F6014A device are programmed. First, the number of commands to send (called ‘RemainingCmds’ in the flowchart) is set to 1536 and the destination address (called ‘BaseAddress’) is set to ‘0’. Next, one row in the device is programmed with a PROGP command. Each PROGP command contains data for one row of code memory of the dsPIC30F6014A. After the first command is processed successfully, ‘RemainingCmds’ is decremented by 1 and compared to 0. Since there are more PROGP commands to send, ‘BaseAddress’ is incremented by 0x40 to point to the next row of memory.On the second PROGP command, the second row of each memory panel is programmed. This process is repeated until the entire device is programmed. No special handling must be performed when a panel boundary is crossed.FIGURE 5-3:FLOWCHART FORPROGRAMMINGdsPIC30F6014A CODEMEMORYIsPROGP responsePASS?IsRemainingCmds0?BaseAddress = 0x0RemainingCmds = 1536RemainingCmds =RemainingCmds – 1FinishBaseAddress =BaseAddressNoNoYesYes+ 0x40StartFailureReport ErrorSend PROGPCommand to ProgramBaseAddress© 2010 Microchip Technology Inc.DS70102K-page 7dsPIC30F Flash Programming SpecificationDS70102K-page 8© 2010 Microchip Technology Inc.5.5.3PROGRAMMING VERIFICATIONOnce code memory is programmed, the contents of memory can be verified to ensure that programming was successful. Verification requires code memory to be read back and compared against the copy held in the programmer’s buffer.The READP command can be used to read back all the programmed code memory.Alternatively, you can have the programmer perform the verification once the entire device is programmed using a checksum computation, as described in Section 6.8 “Checksum Computation”.5.6Data EEPROM Programming5.6.1OVERVIEWThe panel architecture for the data EEPROM memory array consists of 128 rows of sixteen 16-bit data words. Each panel stores 2K words. All devices have either one or no memory panels. Devices with data EEPROM provide either 512 words, 1024 words or 2048 words of memory on the one panel (see Table 5-3).TABLE 5-3:DATA EEPROM SIZEDevice Data EEPROM Size (Words)Number of RowsdsPIC30F201051232dsPIC30F201100dsPIC30F201200dsPIC30F301051232dsPIC30F301151232dsPIC30F301251232dsPIC30F301351232dsPIC30F301451232dsPIC30F401151232dsPIC30F401251232dsPIC30F401351232dsPIC30F501151232dsPIC30F501351232dsPIC30F501551232dsPIC30F501651232dsPIC30F60102048128dsPIC30F6010A 2048128dsPIC30F6011102464dsPIC30F6011A 102464dsPIC30F60122048128dsPIC30F6012A 2048128dsPIC30F6013102464dsPIC30F6013A 102464dsPIC30F60142048128dsPIC30F6014A 2048128dsPIC30F601520481285.6.2PROGRAMMING METHODOLOGYThe programming executive uses the PROGD command to program the data EEPROM. Figure 5-4 illustrates the flowchart of the process. Firstly, the number of rows to program (RemainingRows) is based on the device size, and the destination address (DestAddress) is set to ‘0’. In this example, 128 rows (2048 words) of data EEPROM will be programmed.The first PROGD command programs the first row of data EEPROM. Once the command completes successfully, ‘RemainingRows’ is decremented by 1 and compared with 0. Since there are 127 more rows to program, ‘BaseAddress’ is incremented by 0x20 to point to the next row of data EEPROM. This process is then repeated until all 128 rows of data EEPROM are programmed.FIGURE 5-4:FLOWCHART FOR PROGRAMMINGdsPIC30F6014A DATA EEPROMIsPROGD responsePASS?IsRemainingRows0?Remaining Rows = 128BaseAddress = 0RemainingRows =RemainingRows – 1FinishBaseAddress =BaseAddress NoNoYes Yes+ 0x20StartSend PROGD Command with BaseAddressFailure Report ErrordsPIC30F Flash Programming Specification5.6.3PROGRAMMING VERIFICATIONOnce the data EEPROM is programmed, the contents of memory can be verified to ensure that the programming was successful. Verification requires the data EEPROM to be read back and compared against the copy held in the programmer’s buffer. The READD command reads back the programmed data EEPROM. Alternatively, the programmer can perform the verification once the entire device is programmed using a checksum computation, as described in Section 6.8 “Checksum Computation”.Note:TBLRDL instructions executed within a REPEAT loop must not be used to readfrom Data EEPROM. Instead, it isrecommended to use PSV access.5.7Configuration Bits Programming5.7.1OVERVIEWThe dsPIC30F has Configuration bits stored in seven 16-bit registers. These bits can be set or cleared to select various device configurations. There are two types of Configuration bits: system-operation bits and code-protect bits. The system-operation bits determine the power-on settings for system-level components such as the oscillator and Watchdog Timer. The code- protect bits prevent program memory from being read and written. The FOSC Configuration register has three different register descriptions, based on the device. The FOSC Configuration register description for the dsPIC30F2010 and dsPIC30F6010/6011/6012/6013/ 6014 devices are shown in Table 5-4.Note:If user software performs an erase opera-tion on the configuration fuse, it must befollowed by a write operation to this fusewith the desired value, even if the desiredvalue is the same as the state of theerased fuse.The FOSC Configuration register description for the dsPIC30F4011/4012 and dsPIC30F5011/5013 devicesis shown in Table 5-5.The FOSC Configuration register description forall remaining devices (dsPIC30F2011/2012, dsPIC30F3010/3011/3012/3013, dsPIC30F3014/ 4013, dsPIC30F5015 and dsPIC30F6011A/6012A/ 6013A/ 6014A) is shown in Table 5-6. Always use the correct register descriptions for your target processor.The FWDT, FBORPOR, FBS, FSS, FGS and FICD Configuration registers are not device-dependent. The register descriptions for these Configuration registersare shown in Table 5-7.The Device Configuration register maps are shown in Table 5-8 through Table 5-11.TABLE 5-4:FOSC CONFIGURATION BITS DESCRIPTION FOR dsPIC30F2010 ANDdsPIC30F6010/6011/6012/6013/6014Bit Field Register DescriptionFCKSM<1:0>FOSC Clock Switching Mode1x =Clock switching is disabled, Fail-Safe Clock Monitor is disabled01 =Clock switching is enabled, Fail-Safe Clock Monitor is disabled00 =Clock switching is enabled, Fail-Safe Clock Monitor is enabledFOS<1:0>FOSC Oscillator Source Selection on POR11 =Primary Oscillator10 =Internal Low-Power RC Oscillator01 =Internal Fast RC Oscillator00 =Low-Power 32 kHz Oscillator (Timer1 Oscillator)FPR<3:0>FOSC Primary Oscillator Mode1111 = ECIO w/PLL 16X – External Clock mode with 16X PLL. OSC2 pin is I/O1110 = ECIO w/PLL 8X – External Clock mode with 8X PLL. OSC2 pin is I/O1101 = ECIO w/PLL 4X – External Clock mode with 4X PLL. OSC2 pin is I/O1100 = ECIO – External Clock mode. OSC2 pin is I/O1011 = EC – External Clock mode. OSC2 pin is system clock output (F OSC/4)1010 = Reserved (do not use)1001 = ERC – External RC Oscillator mode. OSC2 pin is system clock output(F OSC/4)1000 = ERCIO – External RC Oscillator mode. OSC2 pin is I/O0111 = XT w/PLL 16X – XT Crystal Oscillator mode with 16X PLL0110 = XT w/PLL 8X – XT Crystal Oscillator mode with 8X PLL0101 = XT w/PLL 4X – XT Crystal Oscillator mode with 4X PLL0100 = XT – XT Crystal Oscillator mode (4 MHz-10 MHz crystal)001x = HS – HS Crystal Oscillator mode (10 MHz-25 MHz crystal)000x = XTL – XTL Crystal Oscillator mode (200 kHz-4 MHz crystal)© 2010 Microchip Technology Inc.DS70102K-page 9dsPIC30F Flash Programming SpecificationTABLE 5-5:FOSC CONFIGURATION BITS DESCRIPTION FOR dsPIC30F4011/4012 AND dsPIC30F5011/5013Bit Field Register DescriptionFCKSM<1:0>FOSC Clock Switching Mode1x =Clock switching is disabled, Fail-Safe Clock Monitor is disabled01 =Clock switching is enabled, Fail-Safe Clock Monitor is disabled00 =Clock switching is enabled, Fail-Safe Clock Monitor is enabledFOS<1:0>FOSC Oscillator Source Selection on POR11 =Primary Oscillator10 =Internal Low-Power RC Oscillator01 =Internal Fast RC Oscillator00 =Low-Power 32 kHz Oscillator (Timer1 Oscillator)FPR<3:0>FOSC Primary Oscillator Mode1111 =ECIO w/PLL 16X – External Clock mode with 16X PLL. OSC2 pin is I/O1110 =ECIO w/PLL 8X – External Clock mode with 8X PLL. OSC2 pin is I/O1101 =ECIO w/PLL 4X – External Clock mode with 4X PLL. OSC2 pin is I/O1100 =ECIO – External Clock mode. OSC2 pin is I/O1011 =EC – External Clock mode. OSC2 pin is system clock output (F OSC/4)1010 =FRC w/PLL 8x – Internal fast RC oscillator with 8x PLL. OSC2 pin is I/O1001 =ERC – External RC Oscillator mode. OSC2 pin is system clock output(F OSC/4)1000 =ERCIO – External RC Oscillator mode. OSC2 pin is I/O0111 =XT w/PLL 16X – XT Crystal Oscillator mode with 16X PLL0110 =XT w/PLL 8X – XT Crystal Oscillator mode with 8X PLL0101 =XT w/PLL 4X – XT Crystal Oscillator mode with 4X PLL0100=XT – XT Crystal Oscillator mode (4 MHz-10 MHz crystal)0011 =FRC w/PLL 16x – Internal fast RC oscillator with 16x PLL. OSC2 pin is I/O0010=HS – HS Crystal Oscillator mode (10 MHz-25 MHz crystal)0001 =FRC w/PLL 4x – Internal fast RC oscillator with 4x PLL. OSC2 pin is I/O0000=XTL – XTL Crystal Oscillator mode (200 kHz-4 MHz crystal)DS70102K-page 10© 2010 Microchip Technology Inc.dsPIC30F Flash Programming Specification TABLE 5-6:FOSC CONFIGURATION BITS DESCRIPTION FOR dsPIC30F2011/2012,dsPIC30F3010/3011/3012/3013/3014, dsPIC30F4013, dsPIC30F5015/5016,dsPIC30F6010A/6011A/6012A/6013A/6014A AND dsPIC30F6015 Bit Field Register DescriptionFCKSM<1:0>FOSC Clock Switching Mode1x =Clock switching is disabled, Fail-Safe Clock Monitor is disabled01 =Clock switching is enabled, Fail-Safe Clock Monitor is disabled00 =Clock switching is enabled, Fail-Safe Clock Monitor is enabledFOS<2:0>FOSC Oscillator Source Selection on POR111 = Primary Oscillator110 = Reserved101 = Reserved100 = Reserved011 = Reserved010 = Internal Low-Power RC Oscillator001 = Internal Fast RC Oscillator (no PLL)000 = Low-Power 32 kHz Oscillator (Timer1 Oscillator)FPR<4:0>FOSC Primary Oscillator Mode (when FOS<2:0> = 111b)11xxx = Reserved (do not use)10111 = HS/3 w/PLL 16X – HS/3 crystal oscillator with 16X PLL(10 MHz-25 MHz crystal)10110 = HS/3 w/PLL 8X – HS/3 crystal oscillator with 8X PLL(10 MHz-25 MHz crystal)10101 = HS/3 w/PLL 4X – HS/3 crystal oscillator with 4X PLL(10 MHz-25 MHz crystal)10100 = Reserved (do not use)10011 = HS/2 w/PLL 16X – HS/2 crystal oscillator with 16X PLL(10 MHz-25 MHz crystal)10010 = HS/2 w/PLL 8X – HS/2 crystal oscillator with 8X PLL(10 MHz-25 MHz crystal10001 = HS/2 w/PLL 4X – HS/2 crystal oscillator with 4X PLL(10 MHz-25 MHz crystal)10000 = Reserved (do not use)01111 = ECIO w/PLL 16x – External clock with 16x PLL. OSC2 pin is I/O01110 = ECIO w/PLL 8x – External clock with 8x PLL. OSC2 pin is I/O01101 = ECIO w/PLL 4x – External clock with 4x PLL. OSC2 pin is I/O01100 = Reserved (do not use)01011 = Reserved (do not use)01010 = FRC w/PLL 8x – Internal fast RC oscillator with 8x PLL. OSC2 pin is I/O01001 = Reserved (do not use)01000 = Reserved (do not use)00111 = XT w/PLL 16X – XT crystal oscillator with 16X PLL00110 = XT w/PLL 8X – XT crystal oscillator with 8X PLL00101 = XT w/PLL 4X – XT crystal oscillator with 4X PLL00100 = Reserved (do not use)00011 = FRC w/PLL 16x – Internal fast RC oscillator with 8x PLL. OSC2 pin is I/O00010 = Reserved (do not use)00001 = FRC w/PLL 4x – Internal fast RC oscillator with 4x PLL. OSC2 pin is I/O00000 = Reserved (do not use)© 2010 Microchip Technology Inc.DS70102K-page 11。

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PIC24HJXXXGPX06/X08/X10Data SheetHigh-Performance,16-Bit Microcontrollers © 2009 Microchip Technology Inc.DS70175HDS70175H-page ii © 2009 Microchip Technology Inc.Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY , PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE . Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.TrademarksThe Microchip name and logo, the Microchip logo, Accuron, dsPIC, K EE L OQ , K EE L OQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.FilterLab, Linear Active Thermistor, MXDEV, MXLAB,SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, , dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit SerialProgramming, ICSP , ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP , PICkit, PICDEM, , PICtail, PIC 32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.All other trademarks mentioned herein are property of their respective companies.© 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.Printed on recycled paper.Note the following details of the code protection feature on Microchip devices:•Microchip products meet the specification contained in their particular Microchip Data Sheet.•Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to ourknowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.•Microchip is willing to work with the customer who is concerned about the integrity of their code.•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC ® MCUs and dsPIC ® DSCs, K EE L OQ ® code hoppingdevices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.PIC24HJXXXGPX06/X08/X10Operating Range:•Up to 40 MIPS operation (at 3.0-3.6V):-Industrial temperature range(-40°C to +85°C)High-Performance CPU:•Modified Harvard architecture• C compiler optimized instruction set•16-bit wide data path•24-bit wide instructions•Linear program memory addressing up to 4M instruction words•Linear data memory addressing up to 64 Kbytes •71 base instructions: mostly 1 word/1 cycle •Sixteen 16-bit General Purpose Registers •Flexible and powerful Indirect Addressing modes •Software stack•16 x 16 multiply operations•32/16 and 16/16 divide operations•Up to ±16-bit data shiftsDirect Memory Access (DMA):•8-channel hardware DMA• 2 Kbytes dual ported DMA buffer area(DMA RAM) to store data transferred via DMA: -Allows data transfer between RAM and aperipheral while CPU is executing code(no cycle stealing)•Most peripherals support DMAInterrupt Controller:•5-cycle latency•Up to 61 available interrupt sources•Up to five external interrupts•Seven programmable priority levels•FIve processor exceptionsDigital I/O:•Up to 85 programmable digital I/O pins•Wake-up/Interrupt-on-Change on up to 24 pins •Output pins can drive from 3.0V to 3.6V•All digital input pins are 5V tolerant• 4 mA sink on all I/O pins On-Chip Flash and SRAM:•Flash program memory, up to 256 Kbytes •Data SRAM, up to 16 Kbytes (includes 2 Kbytes of DMA RAM)System Management:•Flexible clock options:-External, crystal, resonator, internal RC-Fully integrated PLL-Extremely low jitter PLL•Power-up Timer•Oscillator Start-up Timer/Stabilizer •Watchdog Timer with its own RC oscillator •Fail-Safe Clock Monitor•Reset by multiple sourcesPower Management:•On-chip 2.5V voltage regulator•Switch between clock sources in real time •Idle, Sleep and Doze modes with fast wake-upTimers/Capture/Compare/PWM:•Timer/Counters, up to nine 16-bit timers:-Can pair up to make four 32-bit timers-One timer runs as Real-Time Clock withexternal 32.768 kHz oscillator-Programmable prescaler•Input Capture (up to eight channels):-Capture on up, down or both edges-16-bit capture input functions-4-deep FIFO on each capture•Output Compare (up to eight channels):-Single or Dual 16-Bit Compare mode-16-bit Glitchless PWM modeHigh-Performance, 16-Bit Microcontrollers© 2009 Microchip Technology Inc.DS70175H-page 1PIC24HJXXXGPX06/X08/X10DS70175H-page 2© 2009 Microchip Technology Inc.Communication Modules:•3-wire SPI (up to two modules):-Framing supports I/O interface to simple codecs-Supports 8-bit and 16-bit data-Supports all serial clock formats and sampling modes •I 2C™ (up to two modules):-Full Multi-Master Slave mode support -7-bit and 10-bit addressing-Bus collision detection and arbitration -Integrated signal conditioning -Slave address masking •UART (up to two modules):-Interrupt on address bit detect -Interrupt on UART error-Wake-up on Start bit from Sleep mode -4-character TX and RX FIFO buffers -LIN bus support-IrDA ® encoding and decoding in hardware -High-Speed Baud mode-Hardware Flow Control with CTS and RTS •Enhanced CAN (ECAN™ module) 2.0B active (up to two modules):-Up to eight transmit and up to 32 receive buffers -16 receive filters and 3 masks-Loopback, Listen Only and Listen AllMessages modes for diagnostics and bus monitoring-Wake-up on CAN message-Automatic processing of Remote Transmission Requests -FIFO mode using DMA-DeviceNet™ addressing supportAnalog-to-Digital Converters:•Up to two Analog-to-Digital Converter (ADC) modules in a device•10-bit, 1.1 Msps or 12-bit, 500 ksps conversion:-Two, four, or eight simultaneous samples -Up to 32 input channels with auto-scanning -Conversion start can be manual orsynchronized with one of four trigger sources -Conversion possible in Sleep mode -±1 LSb max integral nonlinearity -±1 LSb max differential nonlinearityCMOS Flash Technology:•Low-power, high-speed Flash technology •Fully static design• 3.3V (±10%) operating voltage •Industrial temperature •Low-power consumptionPackaging:•100-pin TQFP (14x14x1 mm and 12x12x1 mm)•64-pin TQFP (10x10x1 mm)Note:See the device variant tables for exact peripheral features per device.PIC24HJXXXGPX06/X08/X10PIC24H PRODUCT FAMILIESThe PIC24H Family of devices is ideal for a wide vari-ety of 16-bit MCU embedded applications. The devicenames, pin counts, memory sizes and peripheral avail-ability of each device are listed below, followed by theirpinout diagrams.PIC24H Family ControllersDevice PinsProgramFlashMemory (KB)RAM(1)(KB)DMAChannelsTimer16-bitInputCaptureOutputCompareStd.PWMCodecInterfaceADCUARTSPII2C™CANI/OPins(Max)(2)PackagesPIC24HJ64GP2066464889880 1 ADC,18 ch221053PTPIC24HJ64GP21010064889880 1 ADC,32 ch222085PF, PTPIC24HJ64GP5066464889880 1 ADC,18 ch222153PTPIC24HJ64GP51010064889880 1 ADC,32 ch222185PF, PTPIC24HJ128GP20664128889880 1 ADC,18 ch222053PTPIC24HJ128GP210100128889880 1 ADC,32 ch222085PF, PTPIC24HJ128GP50664128889880 1 ADC,18 ch222153PTPIC24HJ128GP510100128889880 1 ADC,32 ch222185PF, PTPIC24HJ128GP306641281689880 1 ADC,18 ch222053PTPIC24HJ128GP3101001281689880 1 ADC,32 ch222085PF, PTPIC24HJ256GP206642561689880 1 ADC,18 ch222053PTPIC24HJ256GP2101002561689880 1 ADC,32 ch222085PF, PTPIC24HJ256GP6101002561689880 2 ADC,32 ch222285PF, PTNote1:RAM size is inclusive of 2 Kbytes DMA RAM.2:Maximum I/O pin count includes pins shared by the peripheral functions.© 2009 Microchip Technology Inc.DS70175H-page 3PIC24HJXXXGPX06/X08/X10DS70175H-page 4© 2009 Microchip Technology Inc.Pin Diagrams64-Pin TQFP123456789101112133635343332313029282726646362616059585756141516171819202122232425PGEC2/SOSCO/T1CK/CN0/RC14PGED2/SOSCI/T4CK/CN1/RC13OC1/RD0IC4/INT4/RD11IC2/U1CTS/INT2/RD9IC1/INT1/RD8V SSOSC2/CLKO/RC15OSC1/CLKIN/RC12V DDSCL1/RG2U1RTS/SCK1/INT0/RF6U1RX/SDI1/RF2U1TX/SDO1/RF3RG15AN16/T2CK/T7CK/RC1AN17/T3CK/T6CK/RC2SCK2/CN8/RG6SDI2/CN9/RG7SDO2/CN10/RG8MCLRV SS V DDAN3/CN5/RB3AN2/SS1/CN4/RB2PGEC3/AN1/V REF -/CN3/RB1PGED3/AN0/V REF +/CN2/RB0O C 8/C N 16/R D 7R G 13R G 12R G 14V C A P /V D D C O R ER G 1R F 1R G 0O C 2/R D 1O C 3/R D 2P G E C 1/A N 6/O C F A /R B 6P G E D 1/A N 7/R B 7A V D DA V S SU 2C T S /A N 8/R B 8A N 9/R B 9T M S /A N 10/R B 10T D O /A N 11/R B 11V S SV D DT C K /A N 12/R B 12T D I /A N 13/R B 13U 2R T S /A N 14/R B 14A N 15/O C F B /C N 12/R B 15U 2T X /S C L 2/C N 18/R F 5U 2R X /S D A 2/C N 17/R F 4SDA1/RG343424140393837444847465049515453525545SS2/CN11/RG9AN5/IC8/CN7/RB5AN4/IC7/CN6/RB4IC3/INT3/RD10V D DR F 0O C 4/R D 3O C 7/C N 15/R D 6O C 6/I C 6/C N 14/R D 5O C 5/I C 5/C N 13/R D 4PIC24HJ64GP206PIC24HJ128GP206PIC24HJ256GP206Note:The PIC24HJ64GP206 device does not have the SCL2 and SDA2 pins.= Pins are up to 5V tolerant© 2009 Microchip Technology Inc.DS70175H-page 5PIC24HJXXXGPX06/X08/X10Pin Diagrams (Continued)64-Pin TQFP123456789101112133635343332313029282726646362616059585756141516171819202122232425PGEC2/SOSCO/T1CK/CN0/RC14PGED2/SOSCI/T4CK/CN1/RC13OC1/RD0IC4/INT4/RD11IC2/U1CTS/INT2/RD9IC1/INT1/RD8V SSOSC2/CLKO/RC15OSC1/CLKIN/RC12V DDSCL1/RG2U1RTS/SCK1/INT0/RF6U1RX/SDI1/RF2U1TX/SDO1/RF3RG15AN16/T2CK/T7CK/RC1AN17/T3CK/T6CK/RC2SCK2/CN8/RG6SDI2/CN9/RG7SDO2/CN10/RG8MCLRV SS V DDAN3/CN5/RB3AN2/SS1/CN4/RB2PGEC3/AN1/V REF -/CN3/RB1PGED3/AN0/V REF +/CN2/RB0O C 8/C N 16/R D 7R G 13R G 12R G 14V C A P /V D D C O R ER G 1R F 1R G 0O C 2/R D 1O C 3/R D 2P G E C 1/A N 6/O C F A /R B 6P G E D 1/A N 7/R B 7A V D DA V S SU 2C T S /A N 8/R B 8A N 9/R B 9T M S /A N 10/R B 10T D O /A N 11/R B 11V S SV D DT C K /A N 12/R B 12T D I /A N 13/R B 13U 2R T S /A N 14/R B 14A N 15/O C F B /C N 12/R B 15U 2T X /S C L 2/C N 18/R F 5U 2R X /S D A 2/C N 17/R F 4SDA1/RG343424140393837444847465049515453525545SS2/CN11/RG9AN5/IC8/CN7/RB5AN4/IC7/CN6/RB4IC3/INT3/RD10V D DR F 0O C 4/R D 3O C 7/C N 15/R D 6O C 6/I C 6/C N 14/R D 5O C 5/I C 5/C N 13/R D 4PIC24HJ128GP306= Pins are up to 5V tolerantPIC24HJXXXGPX06/X08/X10DS70175H-page 6© 2009 Microchip Technology Inc.Pin Diagrams (Continued)64-Pin TQFP123456789101112133635343332313029282726646362616059585756141516171819202122232425PGEC2/SOSCO/T1CK/CN0/RC14PGED2/SOSCI/T4CK/CN1/RC13OC1/RD0IC4/INT4/RD11IC2/U1CTS/INT2/RD9IC1/INT1/RD8V SSOSC2/CLKO/RC15OSC1/CLKIN/RC12V DDSCL1/RG2U1RTS/SCK1/INT0/RF6U1RX/SDI1/RF2U1TX/SDO1/RF3RG15AN16/T2CK/T7CK/RC1AN17/T3CK/T6CK/RC2SCK2/CN8/RG6SDI2/CN9/RG7SDO2/CN10/RG8MCLRV SS V DDAN3/CN5/RB3AN2/SS1/CN4/RB2PGEC3/AN1/V REF -/CN3/RB1PGED3/AN0/V REF +/CN2/RB0O C 8/C N 16/R D 7R G 13R G 12R G 14V C A P /V D D C O R ER G 1C 1T X /R F 1R G 0O C 2/R D 1O C 3/R D 2P G E C 1/A N 6/O C F A /R B 6P G E D 1/A N 7/R B 7A V D DA V S SU 2C T S /A N 8/R B 8A N 9/R B 9T M S /A N 10/R B 10T D O /A N 11/R B 11V S SV D DT C K /A N 12/R B 12T D I /A N 13/R B 13U 2R T S /A N 14/R B 14A N 15/O C F B /C N 12/R B 15U 2T X /S C L 2/C N 18/R F 5U 2R X /S D A 2/C N 17/R F 4SDA1/RG343424140393837444847465049515453525545SS2/CN11/RG9AN5/IC8/CN7/RB5AN4/IC7/CN6/RB4IC3/INT3/RD10V D DC 1R X /R F 0O C 4/RD 3O C 7/C N 15/R D 6O C 6/I C 6/C N 14/R D 5O C 5/I C 5/C N 13/R D 4PIC24HJ64GP506PIC24HJ128GP506= Pins are up to 5V tolerant© 2009 Microchip Technology Inc.DS70175H-page 7PIC24HJXXXGPX06/X08/X10Pin Diagrams (Continued)929493919089888786858483828180797820234567891011121314151665646362616059265645444342414039282930313233343536373817181921229517677727170696867667574735857242325969897992746474849505554535251O C 6/C N 14/R D 5O C 5/C N 13/R D 4I C 6/C N 19/R D 13I C 5/R D 12O C 4/R D 3O C 3/R D 2O C 2/R D 1A N 23/C N 23/R A 7A N 22/C N 22/R A 6A N 26/R E 2R G 13R G 12R G 14A N 25/R E 1A N 24/R E 0R G 0A N 28/R E 4A N 27/R E 3R F 0V C A P /V D D C O R EPGED2/SOSCI/CN1/RC13OC1/RD0IC3/RD10IC2/RD9IC1/RD8IC4/RD11SDA2/RA3SCL2/RA2OSC2/CLKO/RC15OSC1/CLKIN/RC12V DD SCL1/RG2SCK1/INT0/RF6SDI1/RF7SDO1/RF8SDA1/RG3U1RX/RF2U1TX/RF3V SSPGEC2/SOSCO/T1CK/CN0/RC14V R E F +/R A 10V R E F -/R A 9A V D DA V S SA N 8/RB 8A N 9/R B 9A N 10/R B 10A N 11/R B 11V D D U 2C T S /R F 12U 2R T S /R F 13I C 7/U 1C T S /C N 20/RD 14I C 8/U 1R T S /C N 21/R D 15V D DV S SP G E C 1/A N 6/O C F A /R B 6P G E D 1P G E D 1/A N 7/R B 7U 2T X /C N 18/R F 5U 2R X /C N 17/R F 4AN29/RE5AN30/RE6AN31/RE7AN16/T2CK/T7CK/RC1AN17/T3CK/T6CK/RC2AN18/T4CK/T9CK/RC3AN19/T5CK/T8CK/RC4SCK2/CN8/RG6V DD TMS/RA0AN20/INT1/RA12AN21/INT2/RA13AN5/CN7/RB5AN4/CN6/RB4AN3/CN5/RB3AN2/SS1/CN4/RB2SDI2/CN9/RG7SDO2/CN10/RG8PGEC3/AN1/CN3/RB1PGED3/AN0/CN2/RB0RG15V DDSS2/CN11/RG9MCLRA N 12/RB 12A N 13/R B 13A N 14/R B 14A N 15/OC F B /C N 12/R B 15R G 1R F 1O C 8/C N 16/RD 7O C 7/C N 15/R D 6TDO/RA5INT4/RA15INT3/RA14V SS V S SV SSV D DTDI/RA4T C K /R A 1 100-Pin TQFPPIC24HJ64GP210PIC24HJ128GP210100PIC24HJ128GP310PIC24HJ256GP210= Pins are up to 5V tolerantPIC24HJXXXGPX06/X08/X10DS70175H-page 8© 2009 Microchip Technology Inc.Pin Diagrams (Continued)929493919089888786858483828180797820234567891011121314151665646362616059265645444342414039282930313233343536373817181921229517677727170696867667574735857242325969897992746474849505554535251O C 6/C N 14/R D 5O C 5/C N 13/R D 4I C 6/C N 19/R D 13I C 5/R D 12O C 4/R D 3O C 3/R D 2O C 2/R D 1A N 23/C N 23/R A 7A N 22/C N 22/R A 6A N 26/R E 2R G 13R G 12R G 14A N 25/R E 1A N 24/R E 0R G 0A N 28/R E 4A N 27/R E 3C 1R X /R F 0V C A P /V D D C O R EPGED2/SOSCI/CN1/RC13OC1/RD0IC3/RD10IC2/RD9IC1/RD8IC4/RD11SDA2/RA3SCL2/RA2OSC2/CLKO/RC15OSC1/CLKIN/RC12V DD SCL1/RG2SCK1/INT0/RF6SDI1/RF7SDO1/RF8SDA1/RG3U1RX/RF2U1TX/RF3V SSPGEC2/SOSCO/T1CK/CN0/RC14V R E F +/R A 10V R E F -/R A 9A V D DA V S SA N 8/RB 8A N 9/R B 9A N 10/R B 10A N 11/R B 11V D DU 2C T S /R F 12U 2R T S /R F 13I C 7/U 1C T S /C N 20/R D 14I C 8/U 1R T S /C N 21/R D 15V D DV S SP G E C 1/A N 6/O C F A /R B 6P G E D 1/A N 7/R B 7U 2T X /C N 18/R F 5U 2R X /C N 17/R F 4AN29/RE5AN30/RE6AN31/RE7AN16/T2CK/T7CK/RC1AN17/T3CK/T6CK/RC2AN18/T4CK/T9CK/RC3AN19/T5CK/T8CK/RC4SCK2/CN8/RG6V DD TMS/RA0AN20/INT1/RA12AN21/INT2/RA13AN5/CN7/RB5AN4/CN6/RB4AN3/CN5/RB3AN2/SS1/CN4/RB2SDI2/CN9/RG7SDO2/CN10/RG8PGEC3/AN1/CN3/RB1PGED3/AN0/CN2/RB0RG15V DDSS2/CN11/RG9MCLRA N 12/RB 12A N 13/R B 13A N 14/R B 14A N 15/OC F B /C N 12/R B 15R G 1C 1T X /R F 1O C 8/C N 16/RD 7O C 7/C N 15/R D 6TDO/RA5INT4/RA15INT3/RA14V SS V S SV SSV D DTDI/RA4T C K /R A 1 100-Pin TQFPPIC24HJ64GP510100PIC24HJ128GP510= Pins are up to 5V tolerantPin Diagrams (Continued)929493919089888786858483828180797820234567891011121314151665646362616059265645444342414039282930313233343536373817181921229517677727170696867667574735857242325969897992746474849505554535251O C 6/C N 14/R D 5O C 5/C N 13/R D 4I C 6/C N 19/R D 13I C 5/R D 12O C 4/R D 3O C 3/R D 2O C 2/R D 1A N 23/C N 23/R A 7A N 22/C N 22/R A 6A N 26/R E 2R G 13R G 12R G 14A N 25/R E 1A N 24/R E 0C 2R X /R G 0A N 28/R E 4A N 27/R E 3C 1R X /R F 0V C A P /V D D C O R EPGED2/SOSCI/CN1/RC13OC1/RD0IC3/RD10IC2/RD9IC1/RD8IC4/RD11SDA2/RA3SCL2/RA2OSC2/CLKO/RC15OSC1/CLKIN/RC12V DD SCL1/RG2SCK1/INT0/RF6SDI1/RF7SDO1/RF8SDA1/RG3U1RX/RF2U1TX/RF3V SSPGEC2/SOSCO/T1CK/CN0/RC14V R E F +/R A 10V R E F -/R A 9A V D DA V S SA N 8/RB 8A N 9/R B 9A N 10/R B 10A N 11/R B 11V D DU 2C T S /R F 12U 2R T S /R F 13I C 7/U 1C T S /C N 20/R D 14I C 8/U 1R T S /C N 21/R D 15V D DV S SP G E C 1/A N 6/O C F A /R B 6P G E D 1/A N 7/R B 7U 2T X /C N 18/R F 5U 2R X /C N 17/R F 4AN29/RE5AN30/RE6AN31/RE7AN16/T2CK/T7CK/RC1AN17/T3CK/T6CK/RC2AN18/T4CK/T9CK/RC3AN19/T5CK/T8CK/RC4SCK2/CN8/RG6V DD TMS/RA0AN20/INT1/RA12AN21/INT2/RA13AN5/CN7/RB5AN4/CN6/RB4AN3/CN5/RB3AN2/SS1/CN4/RB2SDI2/CN9/RG7SDO2/CN10/RG8PGEC3/AN1/CN3/RB1PGED3/AN0/CN2/RB0RG15V DDSS2/CN11/RG9MCLRA N 12/RB 12A N 13/R B 13A N 14/R B 14A N 15/OC F B /C N 12/R B 15C 2T X /R G 1C 1T X /R F 1O C 8/C N 16/RD 7O C 7/C N 15/R D 6TDO/RA5INT4/RA15INT3/RA14V SS V S SV SSV D DTDI/RA4T C K /R A 1 100-Pin TQFP100PIC24HJ256GP610= Pins are up to 5V tolerantTable of ContentsPIC24H Product Families (3)1.0Device Overview (11)2.0Guidelines for Getting Started with 16-Bit Microcontrollers (15)3.0CPU (19)4.0Memory Organization (25)5.0Flash Program Memory (55)6.0Reset (61)7.0Interrupt Controller (65)8.0Direct Memory Access (DMA) (109)9.0Oscillator Configuration (119)10.0Power-Saving Features (129)11.0I/O Ports (137)12.0Timer1 (139)13.0Timer2/3, Timer4/5, Timer6/7 and Timer8/9 (141)14.0Input Capture (147)15.0Output Compare (149)16.0Serial Peripheral Interface (SPI) (153)17.0Inter-Integrated Circuit™ (I2C™) (159)18.0Universal Asynchronous Receiver Transmitter (UART) (167)19.0Enhanced CAN (ECAN™) Module (173)20.010-Bit/12-Bit Analog-to-Digital Converter (ADC) (199)21.0Special Features (211)22.0Instruction Set Summary (219)23.0Development Support (227)24.0Electrical Characteristics (231)25.0Packaging Information (267)Appendix A: Revision History (275)Index (281)The Microchip Web Site (285)Customer Change Notification Service (285)Customer Support (285)Reader Response (286)Product Identification System (287)TO OUR VALUED CUSTOMERSIt is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@ or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.Most Current Data SheetTo obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).ErrataAn errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.To determine if an errata sheet exists for a particular device, please check with one of the following:•Microchip’s Worldwide Web site; •Your local Microchip sales office (see last page)When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using.Customer Notification SystemRegister on our web site at to receive the most current information on all of our products.1.0DEVICE OVERVIEWThis document contains device specific information for the following devices:•PIC24HJ64GP206•PIC24HJ64GP210•PIC24HJ64GP506•PIC24HJ64GP510•PIC24HJ128GP206•PIC24HJ128GP210•PIC24HJ128GP506•PIC24HJ128GP510•PIC24HJ128GP306•PIC24HJ128GP310•PIC24HJ256GP206•PIC24HJ256GP210•PIC24HJ256GP610The PIC24HJXXXGPX06/X08/X10 device family includes devices with different pin counts (64 and 100 pins), different program memory sizes (64 Kbytes, 128 Kbytes and 256 Kbytes) and different RAM sizes (8 Kbytes and 16 Kbytes).This makes these families suitable for a wide variety of high-performance digital signal control applications. The devices are pin compatible with the dsPIC33F fam-ily of devices, and also share a very high degree of compatibility with the dsPIC30F family devices. This allows easy migration between device families as may be necessitated by the specific functionality, computa-tional resource and system cost requirements of the application.The PIC24HJXXXGPX06/X08/X10 device family employs a powerful 16-bit architecture, ideal for applications that rely on high-speed, repetitive computations, as well as control.The 17 x 17 multiplier, hardware support for division operations, multi-bit data shifter, a large array of 16-bit working registers and a wide variety of data addressing modes, together provide the PIC24HJXXXGPX06/X08/X10 Central Processing Unit (CPU) with extensive mathematical processing capability. Flexible and deterministic interrupt handling, coupled with a powerful array of peripherals, renders the PIC24HJXXXGPX06/X08/X10 devices suitable for control applications. Further, Direct Memory Access (DMA) enables overhead-free transfer of data between several peripherals and a dedicated DMA RAM. Reliable, field programmable Flash program memory ensures scalability of applications that use PIC24HJXXXGPX06/X08/X10 devices.Figure1-1 shows a general block diagram of the various core and peripheral modules in the PIC24HJXXXGPX06/X08/X10 family of devices, while Table1-1 lists the functions of the various pins shown in the pinout diagrams.Note:This data sheet summarizes the features of the PIC24HJXXXGPX06/X08/X10 fam-ily of devices. However, it is not intendedto be a comprehensive reference source.To complement the information in this datasheet, refer to the latest family referencesections of the “PIC24H Family ReferenceManual”, which is available from theMicrochip web site ().FIGURE 1-1:PIC24HJXXXGPX06/X08/X10 GENERAL BLOCK DIAGRAM16OSC1/CLKIOSC2/CLKO V DD , V SS Timing Generation MCLRPower-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out ResetPrecision Reference Band Gap FRC/LPRC Oscillators RegulatorVoltage V CAP /V DDCORE UART1,2ECAN1,2IC1-8OC/SPI1,2I2C1,2PORTANote:Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features present on each device.PWM1-8CN1-23Instruction Decode and Control PCH PCL 16Program Counter16-bit ALU23232423Instruction RegPCU16 x 16W Register ArrayROM Latch16EA MUX168Interrupt ControllerPSV and Table Data Access Control BlockStackControlLogic Loop Control LogicAddress LatchProgram MemoryData LatchL i t e r a l D a t a16161616Data LatchAddressLatch16X RAMData Bus17 x 17 MultiplierDivide Support16DMARAMDMAControllerControl Signals to Various BlocksADC1,2Timers PORTBPORTCPORTDPORTEPORTFPORTGAddress Generator Units1-9TABLE 1-1:PINOUT I/O DESCRIPTIONSPin NamePinTypeBufferTypeDescriptionAN0-AN31I Analog Analog input channels.AV DD P P Positive supply for analog modules. This pin must be connected at all times. AV SS P P Ground reference for analog modules.CLKI CLKO IOST/CMOS—External clock source input. Always associated with OSC1 pin function.Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillatormode. Optionally functions as CLKO in RC and EC modes. Always associatedwith OSC2 pin function.CN0-CN23I ST Input change notification inputs.Can be software programmed for internal weak pull-ups on all inputs.C1RX C1TX C2RX C2TX IOIOST—ST—ECAN1 bus receive pin.ECAN1 bus transmit pin.ECAN2 bus receive pin.ECAN2 bus transmit pin.PGED1 PGEC1 PGED2 PGEC2 PGED3 PGEC3I/OII/OII/OISTSTSTSTSTSTData I/O pin for programming/debugging communication channel 1.Clock input pin for programming/debugging communication channel 1.Data I/O pin for programming/debugging communication channel 2.Clock input pin for programming/debugging communication channel 2.Data I/O pin for programming/debugging communication channel 3.Clock input pin for programming/debugging communication channel 3.IC1-IC8I ST Capture inputs 1 through 8.INT0 INT1 INT2 INT3 INT4IIIIISTSTSTSTSTExternal interrupt 0.External interrupt 1.External interrupt 2.External interrupt 3.External interrupt 4.MCLR I/P ST Master Clear (Reset) input. This pin is an active-low Reset to the device.OCFA OCFB OC1-OC8IIOSTST—Compare Fault A input (for Compare Channels 1, 2, 3 and 4).Compare Fault B input (for Compare Channels 5, 6, 7 and 8).Compare outputs 1 through 8.OSC1 OSC2II/OST/CMOS—Oscillator crystal input. ST buffer when configured in RC mode; CMOSotherwise.Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillatormode. Optionally functions as CLKO in RC and EC modes.RA0-RA7 RA9-RA10 RA12-RA15I/OI/OI/OSTSTSTPORTA is a bidirectional I/O port.RB0-RB15I/O ST PORTB is a bidirectional I/O port.RC1-RC4 RC12-RC15I/OI/OSTSTPORTC is a bidirectional I/O port.RD0-RD15I/O ST PORTD is a bidirectional I/O port. RE0-RE7I/O ST PORTE is a bidirectional I/O port. RF0-RF8RF12-RF13I/O ST PORTF is a bidirectional I/O port.RG0-RG3 RG6-RG9 RG12-RG15I/OI/OI/OSTSTSTPORTG is a bidirectional I/O port.Legend:CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input。