PCF8574中文手册
847PET手操器中文使用说明
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3.7 EN-prefix...............................................................................................................................................10 3.8 键盘超时 ...............................................................................................................................................10
3 设置模式 ..........................................................................................................................................................7 3.1 综述 .........................................................................................................................................................7 3.2 显示对比度 .............................................................................................................................................8 3.3 模式选择 .................................................................................................................................................8 3.4 IR 波特率选择 ........................................................................................................................................8 3.5 EN 波特率选择.......................................................................................................................................9 3.6 RS-232 波特率选择 ................................................................................................................................9
PCF8574中文资料_数据手册_参数
PCF8534AUDA1,026;PCF8534AHL1,518;中文规格书,Datasheet资料
PCF8534A-1
SCL CLK
2 3 10 11 12 VLCD F 13 14 15 16 17 18 19 20 21 22 23 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 4 5 6 7 8 A1 9 A2
SYNC
OSC
A0
VDD
SA0
Top view
VSS
001aai648
Viewed from active side. For mechanical details, see Figure 26.
Fig 3.
Pin configuration for the wire bond die (PCF8534AU)
S31 S32 S33 S34 S35 S36 S37 S38 S39
1 2 3 4 5 6 7 8 9
60 S10 59 S9 58 S8 57 S7 56 S6 55 S5 54 S4 53 S3 52 S2 51 S1 50 S0 49 VLCD 48 VSS 47 SA0 46 A2 45 A1 44 A0 43 OSC 42 SYNC 41 VDD S51 21 S52 22 S53 23 S54 24 S55 25 S56 26 S57 27 S58 28 S59 29 BP0 30 BP1 31 BP2 32 BP3 33 n.c. 34 n.c. 35 n.c. 36 n.c. 37 SDA 38 SCL 39 CLK 40
S40 10 S41 11 S42 12 S43 13 S44 14 S45 15 S46 16 S47 17 S48 18 S49 19 S50 20
PCF8534AHL
013aaa158
Top view. For mechanical details, see Figure 25.
PCA8574中文资料
PCA8574中⽂资料1.General descriptionThe PCA8574/74A provide general purpose remote I/O expansion for mostmicrocontroller families via the two-line bidirectional I 2C-bus (serial clock (SCL), serial data (SDA)).The devices consist of an 8-bit quasi-bidirectional port and an I 2C-bus interface. ThePCA8574/74A have low current consumption and include latched outputs with 25mA high current drive capability for directly driving LEDs.The PCA8574/74A also possess an interrupt line (INT) that can be connected to theinterrupt logic of the microcontroller.By sending an interrupt signal on this line,the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I 2C-bus.The internal Power-On Reset (POR) initializes the I/Os as inputs.2.FeaturesI 400kHz I 2C-bus interfaceI 2.3V to 5.5V operation with 5.5V tolerant I/OsI 8-bit remote I/O pins that default to inputs at power-upI Latched outputs with 25mA sink capability for directly driving LEDs I T otal package sink capability of 200mA I Active LOW open-drain interrupt outputI 8 programmable slave addresses using 3 address pinsI Readable device ID (manufacturer, device type, and revision)I Low standby current (10µA max.)I ?40°C to +85°C operation IESD protection exceeds 2000V HBM per JESD22-A114, 200V MM per JESD22-A115, and 1000V CDM per JESD22-C101 I Latch-up testing is done to JEDEC standard JESD78 which exceeds 100mA I Packages offered: DIP16, SO16, TSSOP16, SSOP203.ApplicationsI LED signs and displays I ServersI Industrial control I Medical equipment IPLCsPCA8574/74ARemote 8-bit I/O expander for I 2C-bus with interruptRev. 02 — 14 May 2007Product data sheetI Cellular telephones I Gaming machinesI Instrumentation and test measurement4.Ordering information5.Block diagramTable 1.Ordering informationType number Topside mark Package Name DescriptionVersion PCA8574D PCA8574D SO16plastic small outline package; 16 leads; body width 7.5mmSOT162-1PCA8574AD PCA8574AD PCA8574N PCA8574N DIP16plastic dual in-line package; 16 leads (300mil); long bodySOT38-1PCA8574AN PCA8574AN PCA8574PW PCA8574TSSOP16plastic thin shrink small outline package; 16 leads;body width 4.4mmSOT403-1PCA8574APW PA8574A PCA8574TS PCA8574SSOP20plastic shrink small outline package; 20 leads;body width 4.4mmSOT266-1PCA8574A TSPCA8574AFig 1.Block diagram of PCA8574/74A002aac677INT I 2C-BUS CONTROLINTERRUPT LOGICPCA8574PCA8574ALP FILTERAD0AD1AD2INPUT FILTERSHIFT REGISTERSDASCL 8 BITSwrite pulse read pulsePOWER-ON RESETV DD V SSI/O PORTP0 to P76.Pinning information6.1PinningFig 2.Simpli?ed schematic diagram of P0 to P7002aac109write pulseread pulseD CI SFF Qpower-on resetdata from Shift RegisterI trt(pu)100 µAI OHI OLV DDP0 to P7V SSD CI S FFQdata to Shift Registerto interrupt logicFig 3.Pin con?guration for DIP16Fig 4.Pin con?guration for SO16 PCA8574N PCA8574ANAD0V DD AD1SDA AD2SCLP0INT P1P7P2P6P3P5V SSP4002aac67912345678109121114131615PCA8574D PCA8574ADAD0V DD AD1SDA AD2SCLP0INT P1P7P2P6P3P5V SSP4002aac678123456781091211141316156.2Pin descriptionFig 5.Pin con?guration for TSSOP16Fig 6.Pin con?guration for SSOP20PCA8574PW PCA8574APWAD0V DD AD1SDA AD2SCLP0INT P1P7P2P6P3P5V SSP4002aac94112345678109121114131615PCA8574TS PCA8574ATSINT P7SCLP6n.c.n.c.SDA P5V DD P4AD0V SS AD1P3n.c.n.c.AD2P2P0P1002aac6801234567891012111413161518172019Table 2.Pin description for DIP16, SO16, TSSOP16Symbol Pin Description AD01address input 0AD12address input 1AD23address input 2P04quasi-bidirectional I/O0P15quasi-bidirectional I/O 1P26quasi-bidirectional I/O 2P37quasi-bidirectional I/O 3V SS 8supply groundP49quasi-bidirectional I/O 4P510quasi-bidirectional I/O 5P611quasi-bidirectional I/O 6P712quasi-bidirectional I/O 7INT 13interrupt output (active LOW)SCL 14serial clock line SDA 15serial data line V DD16supply voltageTable 3.Pin description for SSOP20Symbol Pin DescriptionINT1interrupt output (active LOW) SCL2serial clock linen.c.3not connectedSDA4serial data lineV DD5supply voltageAD06address input 0AD17address input 1n.c.8not connectedAD29address input 2P010quasi-bidirectional I/O0P111quasi-bidirectional I/O1P212quasi-bidirectional I/O2n.c.13not connectedP314quasi-bidirectional I/O3V SS15supply groundP416quasi-bidirectional I/O4P517quasi-bidirectional I/O5n.c.18not connectedP619quasi-bidirectional I/O6P720quasi-bidirectional I/O77.Functional descriptionRefer to Figure 1 “Block diagram of PCA8574/74A”.7.1Device addressFollowing a START condition, the bus master must send the address of the slave it is accessing and the operation it wants to perform (read or write). The address of thePCA8574/74A is shown in Figure 7. Slave address pins AD2, AD1, and AD0 choose 1 of 8slave addresses. T o conserve power, no internal pull-up resistors are incorporated on AD2, AD1, and AD0. Address values depending on AD2, AD1, and AD0 can be found in Table 4 “PCA8574 address map” and T able 5 “PCA8574A address map”.Remark:When using the PCA8574A, the General Call address (00000000b) and the Device ID address (1111100Xb) are reserved and cannot be used as device address.Failure to follow this requirement will cause the PCA8574A not to acknowledge.The last bit of the ?rst byte de?nes the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation.When AD2, AD1 and AD0 are held to V DD or V SS , the same address as the PCF8574 or PCF8574A is applied.7.1.1Address mapsFig 7.PCA8574/74A addressR/W002aab636A6A5A4A3A2A1A0programmableslave addressTable 4.PCA8574 address map A6A5A4A3A2A1A0Address 010000020h 010000121h 010001022h 010001123h 010010024h 010010125h 010011026h 0111127hTable 5.PCA8574A address mapA6A5A4A3A2A1A0Address011100038h011100139h01110103Ah01110113Bh01111003Ch01111013Dh01111103Eh01111113Fh8.I/O programming8.1Quasi-bidirectional I/O architectureThe PCA8574/74A’s 8ports (see Figure2) are entirely independent and can be usedeither as input or output ports. Input data is transferred from the ports to the microcontroller in the Read mode(see Figure9).Output data is transmitted to the ports inthe Write mode (see Figure8).This quasi-bidirectional I/O can be used as an input or output without the use of a control signal for data directions. At power-on the I/Os are HIGH. In this mode only a currentsource (I OH) to V DD is active. An additional strong pull-up to V DD (I trt(pu)) allows fast rising edges into heavily loaded outputs.These devices turn on when an output is written HIGH, and are switched off by the negative edge of SCL.The I/Os should be HIGH before being used as inputs. After power-on, as all the I/Os are set HIGH, all of them can be used as inputs. Any change in setting of the I/Os as either inputs or outputs can be done with the write mode.Remark:If a HIGH is applied to an I/O which has been written earlier to LOW, a largecurrent (I OL) will ?ow to V SS.8.2Writing to the port (Output mode)To write, the master (microcontroller) ?rst addresses the slave device. By setting the lastbit of the byte containing the slave address to logic0 the write mode is entered. ThePCA8574/74A acknowledges and the master sends the data byte for P7 to P0 and is acknowledged by the PCA8574/74A. The 8-bit data is presented on the port lines after ithas been acknowledged by the PCA8574/74A.The number of data bytes that can be sent successively is not limited. The previous datais overwritten every time a data byte has been sent.8.3Reading from a port (Input mode)All ports programmed as input should be set to logic 1. To read, the master(microcontroller) ?rst addresses the slave device after it receives the interrupt. By setting the last bit of the byte containing the slave address to logic 1 the Read mode is entered.The data bytes that follow on the SDA are the values on the ports.If the data on the input port changes faster than the master can read, this data may be lost.Fig 8.Write mode (output)A5A4A3A2A1A00A S A6slave addressSTART conditionR/Wacknowledge from slave002aac120P61P7data 1A acknowledge from slave12345678SCL 9SDA A acknowledge from slavewrite to portdata output from port t v(Q)P5data 2DATA 2 VALIDP4P3P2P1P0P7P4P3P2P1P00P5P5t v(Q)DATA 1 VALIDP5 output voltageI trt(pu)I OHP5 pull-up output current t d(rst)INTA LOW-to-HIGH transition of SDA while SCL is HIGH is de?ned as the STOP condition (P).T ransfer of data can be stopped at any moment by a STOP condition.When this occurs,data present at the last acknowledge phase is valid (Output mode).Input data is lost.Fig 9.Read input port registerA5A4A3A2A1A01AS A6slave addressSTART conditionR/Wacknowledge from slave 002aac121data from port Aacknowledge from masterSDA 1no acknowledge from master read fromportdata intoportdata from port DATA 1DATA 4INTDATA 4DATA 2DATA 3P STOP conditiont v(Q)t d(rst)t h(D)t su(D)t d(rst)8.4Power-on resetWhen power is applied to V DD, an internal Power-On Reset (POR) holds thePCA8574/74A in a reset condition until V DD has reached V POR. At that point, the reset condition is released and the PCA8574/74A registers and I2C-bus/SMBus state machine will initialize to their default states. Thereafter V DD must be lowered below 0.2V to reset the device.8.5Interrupt output (INT)The PCA8574/74A provides an open-drain interrupt (INT) which can be fed to acorresponding input of the microcontroller (see Figure8,Figure9, and Figure10). This gives these chips a kind of master function which can initiate an action elsewhere in the system.An interrupt is generated by any rising or falling edge of the port inputs.After time t v(D)the signal INT is valid.The interrupt disappears when data on the port is changed to the original setting or data is read from or written to the device which has generated the interrupt.In the write mode,the interrupt may become deactivated(HIGH)on the rising edge of the write to port pulse. On the falling edge of the write to port pulse the interrupt is de?nitely deactivated (HIGH).The interrupt is reset in the read mode on the rising edge of the read from port pulse.During the resetting of the interrupt itself, any changes on the I/Os may not generate an interrupt.After the interrupt is reset any change in I/Os will be detected and transmitted as an INT.Fig 10.Application of multiple PCA8574s with interrupt 002aac682V DDMICROCOMPUTERINT PCA8574INTPCA8574INTdevice 1device 2PCA8574INTdevice 89.Characteristics of the I 2C-busThe I 2C-bus is for 2-way,2-line communication between different ICs or modules.The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must beconnected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.9.1Bit transferOne data bit is transferred during each clock pulse.The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 11).9.1.1START and STOP conditionsBoth data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOWtransition of the data line while the clock is HIGH is de?ned as the START condition (S).A LOW-to-HIGH transition of the data line while the clock is HIGH is de?ned as the STOP condition (P) (see Figure 12.)9.2System con?gurationA device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 13).Fig 11.Bit transfermba607data line stable;data validchange of data allowedSDASCLFig 12.De?nition of START and STOP conditionsmba608SDA SCLPSTOP conditionSDASCLSSTART condition9.3AcknowledgeThe number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by oneacknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,whereas the master generates an extra acknowledge related clock pulse.A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse,so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold times must be taken into account.A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.Fig 13.System con?guration002aaa966MASTER TRANSMITTER/RECEIVERSLAVE RECEIVERSLAVETRANSMITTER/RECEIVERMASTER TRANSMITTERMASTER TRANSMITTER/RECEIVERSDA SCLI 2C-BUS MULTIPLEXERSLAVEFig 14.Acknowledgement on the I 2C-bus002aaa987S START condition9821clock pulse for acknowledgementnot acknowledgeacknowledgedata output by transmitterdata output by receiverSCL from master10.Application design-in information10.1Bidirectional I/O expander applicationsIn the 8-bit I/O expander application shown in Figure 15,P0and P1are inputs,and P2to P7 are outputs. When used in this con?guration, during a write, the input (P0 and P1)must be written as HIGH so the external devices fully control the input ports. The desired HIGH or LOW logic levels may be written to the I/Os used as outputs (P2to P7).During a read, the logic levels of the external devices driving the input ports (P0 and P1) and the previous written logic level to the output ports (P2 to P7) will be read.The GPIO also has an interrupt line (INT) that can be connected to the interrupt logic of the microprocessor.By sending an interrupt signal on this line,the remote I/O informs the microprocessor that there is incoming data or a change of data on its ports without having to communicate via the I 2C-bus.10.2High current-drive load applicationsThe GPIO has a maximum sinking current of 25mA per bit. In applications requiring additional drive, two port pins in the same octal may be connected together to sink up to 50mA current. Both bits must then always be turned on or off together. Up to 8 pins (one octal) can be connected together to drive 200mA.Fig 15.Bidirectional I/O expander application002aac123V DDtemperature sensor battery status control for latch control for switch control for audio control for camera control for MP3P0P1P2P3P4P5P6P7V DDSDA SCL INTAD0AD1AD2CORE PROCESSORV DDFig 16.High current-drive load application002aac124V DDP0P1P2P3P4P5P6P7V DD SDA SCL INTAD0AD1AD2CORE PROCESSORV DDLOADIn accordance with the Absolute Maximum Rating System (IEC 60134).Symbol Parameter Conditions Min Max UnitV DD supply voltage?0.5+6VI DD supply current-±100mAI SS ground supply current-±400mAV I input voltage V SS?0.5 5.5VI I input current-±20mAI O output current[1]-±50mAP tot total power dissipation-400mWP/out power dissipation per output-100mWT stg storage temperature?65+150°CT amb ambient temperature operating?40+85°C[1]Total package (maximum) output current is 400mA.12.Static characteristics[1]The power-on reset circuit resets the I 2C-bus logic with V DDThe value is not tested, but veri?ed on sampling basis.Table 7.Static characteristicsV DD =2.3V to 5.5V; V SS =0V; T amb =?40°C to +85°C; unless otherwise speci?ed.Symbol Parameter Conditions Min Typ Max Unit Supplies V DD supply voltage 2.3- 5.5V I DDsupply currentOperating mode; no load;V I =V DD or V SS ;f SCL =400kHz;AD0, AD1, AD2=static H or L -200500µAI stb standby current Standby mode; no load;V I =V DD or V SS ; f SCL =0kHz- 4.510µA V POR power-on reset voltage [1]- 1.8 2.0V Input SCL; input/output SDAV IL LOW-level input voltage ?0.5-+0.3V DD V V IH HIGH-level input voltage 0.7V DD- 5.5V I OLLOW-level output currentV OL =0.4V; V DD =2.3V 2035-mA V OL =0.4V; V DD =3.0V 2544-mA V OL =0.4V; V DD =4.5V3057-mA I L leakage current V I =V DD or V SS ?1-+1µA C i input capacitance V I =V SSLOW-level output currentV OL =0.5V; V DD =2.3V [2]1226-mA V OL =0.5V; V DD =3.0V [2]1733-mA V OL =0.5V; V DD =4.5V[2]2540-mA I OL(tot)total LOW-level output current V OL =0.5V; V DD =4.5V [2]--200mA I OH HIGH-level output current V OH =V SS30138300µA I trt(pu)transient boosted pull-up current V OH =V SS ; see Figure 80.51.0-mA C i input capacitance [3]-2.110pF C o output capacitance [3]- 2.110pF Interrupt INT (see Figure 8 and Figure 9)I OL LOW-level output current V OL =0.4V3.0--mA C o output capacitance -35pF Inputs AD0, AD1, AD2V IL LOW-level input voltage ?0.5-+0.3V DD V V IH HIGH-level input voltage 0.7V DD - 5.5V I LI input leakage current ?1-+1µA C iinput capacitance-3.55pF13.Dynamic characteristics[1]t VD;ACK =time for Acknowledgement signal from SCL LOW to SDA (out) LOW.[2]t VD;DA T =minimum time for SDA data out to be valid following SCL LOW.[3] A master device must internally provide a hold time of at least 300ns for the SDA signal (refer to the V IL of the SCL signal) in order to bridge the unde?ned region SCL ’s falling edge.[4]The maximum t f for the SDA and SCL bus lines is speci?ed at 300ns. The maximum fall time for the SDA output stage t f is speci?ed at 250ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum speci?ed t f .[5]C b =total capacitance of one bus line in pF .[6]Input ?lters on the SDA and SCL inputs suppress noise spikes less than 50ns.Table 8.Dynamic characteristicsV DD =2.3V to 5.5V; V SS =0V; T amb =?40°C to +85°C; unless otherwise speci?ed. Limits are for Fast-mode I 2C-bus.Symbol ParameterConditions Min Typ Max Unit f SCL SCL clock frequency0-400kHz t BUF bus free time between a STOP and START condition1.3--µs t HD;STA hold time (repeated) ST ART condition 0.6--µs t SU;ST A set-up time for a repeated ST ART condition 0.6--µs t SU;STO set-up time for STOP condition 0.6--µs t HD;DA T data hold time0--ns t VD;ACK data valid acknowledge time [1]0.1-0.9µs t VD;DA T data valid time [2]50--ns t SU;DA T data set-up time20+0.1C b [5]-300ns t r rise time of both SDA and SCL signals 20+0.1C b [5]-300ns t SPpulse width of spikes that must be suppressed by the input ?lter [6]--50nsPort timing; C L ≤100pF (see Figure 8 and Figure 9)t v(Q)data output valid time --4µs t su(D)data input set-up time 0--µs t h(D)data input hold time 4--µs Interrupt timing; C L ≤100pF (see Figure 8 and Figure 9)t v(D)data input valid time --4µs t d(rst)reset delay time--4µsRise and fall times refer to V IL and V IH .Fig 17.I 2C-bus timing diagramSCLSDAt HD;STA t SU;DA T t HD;DA T t ft BUFt SU;ST At LOWt HIGHt VD;ACK 002aab175t SU;STOprotocolST ART condition (S)bit 7MSB (A7)bit 6(A6)bit 0(R/W)acknowledge(A)STOP condition (P)1/fSCLt rt VD;DA T14.Package outlineFig 18.Package outline SOT38-1 (DIP16)OUTLINE VERSION EUROPEAN PROJECTIONISSUE DATE IEC JEDEC JEITA mm inchesDIMENSIONS (inch dimensions are derived from the original mm dimensions)SOT38-1 99-12-2703-02-13A min. A max.b max.w M E e 11.401.140.0550.0450.530.380.320.2321.821.40.860.846.486.200.260.243.93.40.150.130.2542.547.620.38.257.800.320.319.58.30.370.332.20.0874.70.51 3.70.150.0210.0150.0130.0090.010.10.020.19050G09MO-001SC-503-16M Hc(e )1M EALs e a t i n g p l a n eA 1w Mb 1eDbEpin 1 index0510 mmscaleNote1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.(1)(1)D (1)Z DIP16: plastic dual in-line package; 16 leads (300 mil); long bodySOT38-1UNITAmax.A1A2A3b p c D(1)E(1)(1)e H E L L p Q ZywvθREFERENCESOUTLINE VERSIONEUROPEANPROJECTIONISSUE DATE IEC JEDEC JEITAmm inches 2.650.30.12.452.250.490.360.320.2310.6510.001.11.00.90.48oo0.250.1DIMENSIONS (inch dimensions are derived from the original mm dimensions)Note1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 SOT162-1816w Mb pDdetail X Ze91y0.25075E03 MS-013pin 1 index0.10.0120.0040.0960.0890.0190.300.290.051.40.055 0.419 0.394 0.043 0.039 0.035 0.016 0.010.250.010.004 0.043 0.016 0.01XθAA1A2H EL pQEcLv M A (A )3SO16: plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 99-12-2703-02-19Fig 19.Package outline SOT162-1 (SO16)Fig 20.Package outline SOT403-1 (TSSOP16)UNIT A 1A 2A 3b p c D (1)E (2)(1)e H E L L p Q Z y w v θ REFERENCES OUTLINE VERSION EUROPEAN PROJECTIONISSUE DATE IECJEDEC JEITAmm0.150.050.950.800.300.190.20.15.14.94.54.30.656.66.20.40.30.400.0680oo 0.130.10.21DIMENSIONS (mm are the original dimensions)Notes1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.0.750.50SOT403-1MO-153D Ze0.2518169θAA 1A 2L p Qdetail XL(A )3H EE cv M AXAy0 2.5 5 mmscaleTSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 Amax.1.1pin 1 index。
PCF8574APW中文资料
FEATURES
• Low Standby-Current Consumption of 10 µA Max
• I2C to Parallel-Port Expander • Open-Drain Interrupt Output
DW OR N PACKAGE (TOP VIEW)
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
RGY PACKAGE (TOP VIEW)
DGV OR PW PACKAGE (TOP VIEW)
P7
INT
A0 1 A1 2 A2 3 P0 4 P1 5 P2 6 P3 7 GND 8
Copyright © 2001–2005, Texas Instruments Incorporated
元器件交易网
PCF8574A REMOTE 8-BIT I/O EXPANDER FOR I2C BUS
SCPS069D – JULY 2001 – REVISED OCTOBER 2005
TA –40°C to 85°C
ORDERING INFORMATION
PACKAGE (1)
ORDERABLE PART NUMBER
QFN – RGY
Tape and reel
PCF8574ARGYR
PDIP – N
Tube
PCF8574AN
SOIC – DW
Tube Tape and reel
By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C bus. Therefore, the PCF8574A can remain a simple slave device.
PCF8574调试的沉痛经历
PCF8574调试的沉痛经历最近一个超声项目需要用到端口扩展功能，经过一番调研，决定选用PCF8574这款I2C总线的芯片，然后开始看数据手册，组实验板，经过一番忙碌，材料齐全，准备开始调试，之前已经做好了I2C的程序，烧入单片机，运行，状态不对？诧异，很是诧异，然后我就开始了我那冤屈的、痛苦的苦难之旅，为什么这么说，看官您请往下看。
开始我以为是程序中时序匹配的问题，于是开始用示波器查看，经过一番查找，最后确定时序没问题，开始郁闷——。
然后我以为是硬件损坏，然后检查PCF8574，型号是PCF8574T，没错，然后在数据手册中曾看到中断是自动响应的，然后我就在输出管脚上加逻辑电平，高低，高低，高高低低，反复测试后，最后确认，芯片的中断脚是有输出的，说明芯片应该或者说基本是好的，没坏，然后对程序进行了简单修改，测试，当满怀信心的测试后发现，芯片还是没响应，情绪开始低落，很是郁闷——。
为了确认芯片的好坏，我在这之后还是决定不管三七二十几，换芯片！！！然后准备烙铁、工具等，焊下原有芯片（在焊下的一瞬间，脑子里飞快的闪过一念头，坏的扔了得了，但是抬头一看老板在，马上作出了违背我良心的决定，保存！！！鄙视我一次），装上新的芯片，清理工作台，重新测试，老状况，老现象，崩溃！！！！于是我就开始疯狂的修改程序，加延时，测试，不行；加逻辑，测试、不行；加协议代码，测试，不行；单字节通信，测试，不行；多字节通信，不行；只读，测试，不行；只写，测试，不行，这时候我感觉我自己要崩溃了，程序作了这么多年，硬件调了那么多次，难不成今天我黑腿哥要将一世英名丢在此吗？不行，重来，将上面的过程重复一便，还是不行，崩溃了，感觉被打败了——！！！于是将手册打出来，重新翻看了几遍，没想法？再看，还是没发现，情绪开始低落，资料扔在一边，上网，聊大天——，经过一阵休整，刚要准备重新来过，却发现天色已晚，算了，下老子的班，让老板瞪眼去吧！！！！！！！转过天来，本将军经过一夜休整，精神抖擞，豪气万丈，上班第一件决定就是管他他奶奶的，再战江湖，于是第一天的情景又重新演义了一遍，到下班时，调试结果还是涛声依旧，一如既往，没有任何反映，PCF8574就好象死了一样，怎么都没反映，就好象是哑巴聋子一样，不管你怎么招呼，他就是没有反映，已经彻底崩溃，于是决定再次休战，明日再来！！！！！！又是迷乱的一夜，晚上做梦时，看到PCF8574就象一座大山，横在心上，太他*的堵心了，老子今天不调了，你不是不理我吗？老子也不理你，看谁吊！！！！！于是收拾，洗梳，上班。
FT857说明书
FT857说明书FT 857快速菜单一览表菜单a A/B VFO A/B频率交换 A=B 置VFO A/B同频 SPL VFO A/B收发异频菜单b MW 存储信道检查，存储信道等 SKIP 从扫描列表中删除信道 TAG 选择存储信道的显示类型（频率显示/字符显示）菜单c STO 存储当前VFO数据到快速存储区信道 RCL 调出快速存储区信道 PROC 激活语音压缩功能，调整语音压缩等级菜单d RPT 设置中继差频（+/-/单频） REV 激活反频功能 VOX 发射声控设定，调整声控增益等级菜单e TON/ENC 激活哑音功能 DEC 哑音译码方式选择 TDCH 哑音搜索功能菜单f ARTS 自动应答系统使能 SRCH 智能搜索功能 PMS 存储器扫描菜单g SCN 频率扫描 PRI 激活优先扫描 DW 激活双段守候菜单h SCOP 激活周边频谱监视功能 WID 设定频谱监视宽度 STEP 设定频谱监视信道步长菜单i MTR 发射机信号表类型选择，信号表峰值保持功能设定 PWR 发射机信号表类型选择（功率表、自动电平控制表、驻波表、调制度表） DISP 屏幕显示模式切换，显示屏对比度设定菜单j SPOT BK 激活CW插入操作，CW侧音音量调节 KYR 激活机器内置电子键，设定电子键发码速度菜单k TUNE 激活天调、自适应天线模式，初始化天调、自适应天线 DOWN 下调节 UP 上调节菜单l NB 中频白噪声调整 AGC 自动增益控制模式选择 AUTO 自动增益控制模式：自动、慢速、快速菜单m IPO 跳过接收机前置信号放大器直通/UV段无效 ATT 天线衰减（10dB）/UV段无效 NAR 在29兆FM操作模式下选择低检波模式菜单n CFIL 选择2.4kHz中频滤波器 N/A N/A菜单o PLY1 CW预存储文本自动发射 PLY2 CW预存储文本自动发射 PLY3 CW预存储文本自动发射菜单p DNR 激活DSP数字降噪功能 DNF 激活DSP数字陷波滤波器功能 DBF 激活DSP数字带通滤波器功能菜单q MONI 打开静噪，本键可自定义 QSPL 激活快速异频工作功能，本键可自定义ATC 产生一个1750Hz音频信号用以打开欧洲的中继设备，本键可自定义--------------------------------------------------------------------------------No 菜单选项功能01 EXTMENU 扩展菜单开启02 144MHz ARS 144 MHz自动频偏功能开启03 430MHz ARS 430MHz自动频偏功能开启04 AM&FM DIAL AM/FM模式主旋钮开启05 AM MIC GAIN AM模式话筒增益06 AM STEP AM模式频率步进设定07 APO TIME 自动电源关闭时间设定08 ARTS BEEP 自动应答系统告警音设定09 ARTS ID 自动应答系统呼号发送设定10 ARTS IDW 自动应答系统呼号编程11 BEACON TEXT 1 CW字符串存储（自动发射）12 BEACON TIME CW自定义字符串发射间隔13 BEEP TONE 设备操作音音调设定14 BEEP VOL 设备操作音音量设定15 CAR LSB R LSB模式接收微调设定16 CAR LSB T LSB模式发射微调设定17 CAR USB R USB模式接收微调设定18 CAR USB T USB模式发射微调设定19 CAT RATE CAT端口波特率设定20 CAT/LIN/TUN 外接端子类型设定21 CLAR DIAL SET 频率微调旋钮选择22 CW AUTO MODE CW自动模式设定23 CW BFO CW拍频模式设定24 CW DELAY CW发射接收转换延迟时间25 CW KEY REV CW自动键点划翻转设置26 CW PADDLE 使用话筒UP/DWN做自动键27 CW PITCH CW侧音频率设定28 CW QSK 选择PTT松开后转换时间29 CW SIDE TONE CW侧音音量设定30 CW SPEED CW自动键发码速度31 CW TRAINING 摩尔斯码自训练功能32 CW WEIGHT CW点划宽度比例设定33 DCS CODE 数字哑音编码设定34 DCS INV 数字哑音翻转控制模式设定35 DIAL STEP 主旋钮选择精度设定36 DIG DISP 数据传输频率偏移显示设定37 DIG GAIN 数据传输增益设定38 DIG MODE 数据传输方式设定39 DIG SHIFT 数据传输频率偏移设定40 DIG VOX 数据传输声控等级设定41 DISP COLOR 显示屏背光颜色设定42 DISP CONTRAST 显示屏对比度设定43 DISP INTENSITY 显示屏背光亮度设定44 DISP MODE 显示屏背光控制模式设定45 DSP BPF WIDTH CW DSP音频带宽设定46 DSP HPF CUTOFF SSB/AM/FM高通滤波截止点47 DSP LPF CUTOFF SSB/AM/FM低通滤波截止点48 DSP MIC EQ DSP数字话筒均衡器设定49 DSP NR LEVEL DSP数字降噪设定50 EMERGENCY 仅美国版有效51 FM MIC GAIN FM话筒增益设定52 FM STEP FM模式频率步进设定53 HOME=>VFO HOME频道转存设定54 LOCK MODE 设备锁定模式选择55 MEM GROUP 存储器组开启设定56 MEM TAG 存储器标示设定57 MEM/VFO DIAL MODE SELECT旋钮第二功能设定58 MIC SCAN 手麦扫描功能设定59 MIC SEL 话筒接口外接设备选择60 MTR ARX SET 接收模式下强度计类型选择61 MTR ATX SET 发射模式下强度计类型选择62 MTR PEAK HOLD 信号表数据保持功能设定63 NB LEVEL NB 控制强度设定64 OP FILTER 165 PG A 多功能键A编程设定66 PG B 多功能键B编程设定67 PG C 多功能键C编程设定68 PG ACC 远程控制话筒ACC键设定69 PG P1 远程控制话筒P1键设定70 PG P2 远程控制话筒P2键设定71 PKT 1200 1200bps音频输入强度设定72 PKT 9600 9600bps音频输入强度设定73 PKT RATE Packet 波特率设定74 PROC LEVEL SSB/AM语音压缩强度设定75 RF POWER SET 当前模式下射频功率调节76 PRT SHIFT 中转台差频设定77 SCAN MODE 扫描模式选择78 SCAN RESUME 扫描恢复时间设定79 SPLIT TONE 音频起控模式组合设定80 SQL/RF GAIN SQL/RF旋钮功能设定81 SSB MIC GAIN SSB话筒增益设定82 SSB STEP SSB模式频率步进设定83 TONE FREQ 哑音频率选择设置84 TOT TIME 发射超时定时器时间设定85 TUNER/ATAS 天调/自适应天线设定86 TX IF FILTER 发射中频滤波器选择87 VOX DELAY 声控延时时间设定88 VOX GAIN 声控增益设定89 XVTR A FREQ 频率显示A设定90 XVTR B FREQ 频率显示B设定91 XVTR SET XVTR功能开启设定-------------------------------------------------------------------------------- 897和857说明：A.本文是针对实际使用，其中按钮的编号及位置按照原厂说明书第12页图示B.FT897的两个旋钮，MAIN DIAL和MEM/VFO，本文中分别称为“大旋钮”“小旋钮”一.按键和旋钮说明1. A，B，C，功能键，有十七组，5. POWER 键，开机后短暂地按这个按键，可以在正常和“快速调谐”之间切换，“快速调谐”启动时屏幕上有一个跑步的人的图标6. F，短暂的按一下，可以用MEM/VFO CH旋钮（以下称“小旋钮”）改变功能键ABC对应的内容按住不放（长按），可以启动菜单模式10. SQL/RF旋钮，静噪/射频（增益），美国版中这个旋钮此旋钮用于调整射频和中频增益，在80号菜单（SQL/RF GAIN）中可以更改为静噪控制；其它（国家）版本中，这个旋钮缺省为静噪控制。
756PC 754N 754 说明书
756PC/754N/754使用说明书本说明书详细阐述了仪器的使用方法、故障排除及维护与保养等内容。
请在使用前仔细阅读本说明，并请妥善保管以备日后查阅。
制造计量器具许可证编号: 沪制********号章节标题页码1 性能指标 (1)2.安装 (2)2.1电源需求 (2)2.1.1供电电压 (2)2.1.2供电频率 (2)2.1.3供电容量 (2)2.2安装条件 (2)2.2.1安装空间 (2)2.2.2安装平面 (2)2.2.3安装场所的环境要求 (2)2.3安装光盘 (2)2.4检查内容 (2)2.4.1检查包装 (2)2.4.2按照装箱单进行检查 (2)2.5电源线的连接 (2)2.6安装后检查 (3)2.7加电 (3)3部件功能 (3)3.1主机左前视图 (3)3.2主机后视图 (4)3.3操作面板 (5)4仪器操作 (6)4.1仪器功能结构图 (7)4.2 仪器启动和系统自检 (7)4.2.1 仪器启动 (7)4.2.2 系统自检 (7)4.2.3 进入系统主界面 (8)4.3 光度测量功能 (9)4.3.1进入光度测量主界面 (9)4.3.2设定测量模式 (9)4.3.3设定工作波长 (9)4.3.4校空白 (10)4.3.5数据记录测量 (10)4.3.6删除数据 (10)4.3.7打印数据 (10)4.4定量测量功能 (10)4.4.1 首先设定工作波长 (11)4.4.2进入定量测量界面 (11)4.4.3标准曲线法 (11)4.4.3.1 进入标准曲线法界面 (12)4.4.3.2 新建曲线 (12)4.4.3.3 输入标样个数 (12)4.4.3.4 输入标样浓度 (13)（续）4.4.3.5 显示曲线信息 (13)4.4.3.6 进入测量结果显示界面 (13)4.4.3.7 可以重新设定工作波长 (13)4.4.3.8 校空白 (14)4.4.3.9 数据记录测量 (14)4.4.3.10 删除数据 (14)4.4.3.11 打印数据 (14)4.4.4 打开曲线 (15)4.4.5 删除曲线 (15)4.4.6 系数法 (16)4.4.6.1 进入系数法 (16)4.4.6.2 进入设定曲线参数界面 (16)4.4.6.3 设定曲线参数K (17)4.4.6.4 设定曲线参数B (17)4.4.6.5 进入测量结果显示界面 (17)4.4.6.6 可以重新设定工作波长 (17)4.4.6.7 校空白 (18)4.4.6.8 数据记录测量 (18)4.4.6.9 删除数据 (18)4.4.6.10 打印数据 (18)4.4.7 选择浓度单位 (19)4.5 系统设定 (19)4.5.1 氘灯 (19)4.5.2 钨灯 (20)4.5.3 时间设置 (20)4.5.4 暗电流校正 (20)4.5.5 波长校正 (21)4.5.6 输入换灯波长 (21)4.5.7 恢复出厂设置 (21)4.5.8 版本信息 (21)5 周期检查和贮藏 (22)5.1 周期检查 (22)5.1.1 清扫样品室 (22)5.1.2 清扫聚焦镜 (22)5.2 贮藏 (22)5.2.1 完成测量以后 (22)5.2.2 长时间不使用 (22)1. 性能指标型号 756PC 754N / 754单色器 C-T 式单色器，1200线全息光栅 C-T 式单色器，1200线全息光栅 检测器 硅光二极管 硅光二极管显示器 128*64大屏幕液晶显示 128*64大屏幕液晶显示 光源 卤钨灯20W/12V （2000小时），氘灯（1000小时） 卤钨灯20W/12V （2000小时），氘灯（1000小时） 光源切换范围可在300nm-400nm 范围内设定光源切换点 可在300nm-400nm 范围设定光源切换点 波长范围 190~1100nm （步进间隔0.1nm ） 190~1100nm （步进间隔0.1nm ） 光谱带宽 2 nm 4 nm 波长准确度 ±1.0 nm （开机自动校准） ±1.0 nm （开机自动校准） 波长重复性 0.5 nm 0.5 nm 光度范围 -1.0 ~ 200.0%T -0.5 ~ 3.000Abs 0 ~ 9999 C 0 ~ 9999 F -1.0 ~ 200.0%T-0.5 ~ 3.000Abs 0 ~ 9999 C 0 ~ 9999 F透射比准确度±0.5 %T （0 – 100%T ） ±0.5 %T （0 – 100%T ） 透射比重复性±0.2 %T ±0.2 %T 杂散光 0.15 %T (在 220, 340 nm 处) 0.3 %T (在 220, 340 nm 处) 亮电流 / ±0.5 %T 暗电流 / ±0.2 %T 基线平直度 ±0.004A / 基线漂移 ±0.002A / 数据输出 USB 端口，LPT 并行打印口 USB 端口，LPT 并行打印口 软件支持 UV-Solution 工作站软件 UV-Solution 工作站软件（选配） 电源 220V ±±10% 50Hz 150VA 220V 10% 50Hz 150VA 标准样品架 四槽位标准样品架 四槽位标准样品架 仪器尺寸 465长 X 375宽 X 220高 毫米 456长 X 375宽 X 220高 毫米 仪器净重 14.0公斤 14.0公斤 包装尺寸 625长 X 520宽 X 348高 毫米 625长 X 520宽 X 348高 毫米 仪器毛重 17.5 公斤 17.5 公斤12. 安装2.1 电源需求2.1.1 供电电压供电电压(220V和110V)标记在供电电压选择开关的侧面（左面和右面）供电电压的波动范围在额定电压的±10%以内。
VSC8574芯片评估板用户指南说明书
VSC8574User Guide VSC8574 Evaluation BoardContents1Revision History (1)1.1Revision 2.0 (1)1.2Revision 1.0 (1)2Introduction (2)2.1References (2)3General Description (3)3.1Key Features (3)3.1.1Copper Port RJ45 Connections (3)3.1.2SGMII/QSGMII MAC SMA (3)3.1.3Switch Block Control (3)3.1.4Zarlink ZL30143 SyncE G.8262/SETS (3)3.1.5External 1588 Clock Option (3)3.1.6External RefClk Option (3)3.1.7Network Interface Microcontroller Card (4)4Quick Start (5)4.1Connecting the Power Supply (5)4.2PC Software Installation (5)4.3Connecting the Board to the PC (5)4.3.1Changing the IP Address of the Board (5)4.4Using the Control Software (6)4.4.1Copper Media Operation (1000BASE-T) (7)4.4.2Fiber Media Operation (100BASE-FX) (7)4.4.3Fiber Media Operation (1000BASE-X) (8)4.5Useful Registers (8)4.5.1Ethernet Packet Generator (8)4.5.2Copper PHY Error Counters (8)4.5.3Fiber PHY Error Counters (8)5Additional Information (9)1Revision HistoryThe revision history describes the changes that were implemented in the document. The changes arelisted by revision, starting with the most current publication.1.1Revision2.0Revision 2.0 was published in April 2014. This revision includes changes regarding ZL30143 output drivecompatibility and hyperlinks.1.2Revision 1.0Revision 1.0 was the first release of this document. It was published in June 2012.2IntroductionThe VSC8574 device is a low-power, quad-port Gigabit Ethernet transceiver with four SerDes interfacesfor quad-port dual media capability. It also includes an integrated quad port I C multiplexer (MUX) to2control SFPs or PoE modules. The VSC8574 device also includes Vitesse’s unique IEEE 1588 time-stamping engine with dual encapsulation support. It also includes dual recovered clock outputs tosupport Synchronous Ethernet applications.This document describes the architecture and usage of the VSC8574 Evaluation Board (VSC8574EV). TheVSC8574EV may be used to evaluate a family of devices which include the VSC8504, VSC8552, VSC8572,and VSC8574. These devices vary with respect to the number of ports, supported interfaces, andavailable features. This document specifically addresses the VSC8574 device. The Quick Start sectiondescribes how to bring-up the evaluation board along with install and run the graphical user interface(GUI), used to control the evaluation board.Figure 1 • VSC8574EV Evaluation Board2.1ReferencesThe following reference documents provide additional information about the operation of the VSC8574evaluation board.VSC8504 DatasheetVSC8552 DatasheetVSC8572 DatasheetVSC8574 DatasheetIEEE1588v2 and SyncE – Applications and Operation Using Vitesse’s Synchronization SolutionVSC8475 GUIVSC8574 Evaluation Board Schematic3General DescriptionThe evaluation board (Figure 1) provides the user a way to evaluate the VSC8574 device in multipleconfigurations. Four RJ-45 connectors are provided for copper media interfaces. The four SFP cagesallow for evaluation of the fiber media interconnects. The MAC interface is provided via SMA connectorsor alternatively through SFP ports.For access to all of the features of the device, an external microcontroller is used to configure the on-board clock chip via a two wire serial bus and the VSC8574 via the MDIO bus. The graphical userinterface (GUI) enables the user to access the registers.The evaluation board uses a Zarlink device to synthesize a 125MHz reference clock signal from a 20MHzcrystal which serves as the REFCLK input.3.1Key Features3.1.1Copper Port RJ45 ConnectionsPHY Ports 2 and 3 use UDE RTA 1648BAK1A with integrated magnetic while PHY Ports 0 and 1 usegeneric RJ45 connectors with discrete Pulse H5008 magnetics.3.1.2SGMII/QSGMII MAC SMASGMII SMA connections are provided for all PHYs while the QSGMII SMA connection is available only onPHY0. Optional MAC side SFP port connections are provided for PHY0 and 3. To use these, 0 Ω resistorsmust be removed and re-installed on the board.3.1.3Switch Block ControlSet the SW1 switch as shown in the figure below.Figure 2 • SW1 Switch Control3.1.4Zarlink ZL30143 SyncE G.8262/SETSThe Zarlink ZL30143 is initialized by default to provide a 125MHz differential LVPECL clock to theVSC8574 REFCLK inputs. The ZL30143 can be programmed to provide an LVDS differential clock inconjunction with an LVDS termination provided for REFCLK. See the Zarlink manual for output driveprogramming details. The ZL30143 can support synchronization with the VSC8574 PHY recovered clockfor SyncE operation.3.1.5External 1588 Clock OptionThe user may choose to provide an external 1588 REFCLK via SMA connections to J65 and J66. Zero ohmjumpers may need to be removed and or installed to connect via these clock inputs.3.1.6External RefClk OptionThe user may choose to provide an external PHY REFCLK via SMA connections to J21 and J23. Zero Ohmjumpers may need to be removed and or installed to connect via these clock inputs.3.1.7Network Interface Microcontroller CardA “Rabbit” microcontroller card is included to facilitate a software interface to the registers on theVSC8574. The controller card has a hard coded static IP address. See the label on the card for the value.This address is required by the user to initiate communications via the board and the GUI.Note: The factory programmed Rabbit board IP address is 10.9.70.193.1. 2. 3. 1. 2. 3. 4. 5. 6. 7. a. b. 8. 9. 10. 11. 4Quick Start 4.1Connecting the Power SupplyThe evaluation board uses +5VDC to power the on-board regulators creating the +3.3V, +2.5V, and +1.0V rails which drive the devices as well as modules. The evaluation board can be powered up using the power pack which provides the +5VDC. Simply plug the AC adaptor into a wall socket and the barrel end into J67 (see the upper right corner of Figure 1). Immediately the user should see several LEDs turn on.The user may alternately connect the board to a bench style power supply by connecting the red banana plug to +5VDC and the black banana plug to ground. If the supply provides 3A the board should come alive as described above.4.2PC Software InstallationDownload the ZIP file to the PC’s root directory, normally C:\.Extract to C:\Double click the icon to launch the GUI (It is acceptable to drag the icon to the desktop)4.3Connecting the Board to the PCThe Rabbit board can interface with a PC either through a direct connection to the PC or if configured properly through a local area network. The latter option requires the user to configure the Rabbit’s IP address so as to properly reside on the user’s network.The IP address of the board should be written on the Rabbit network interface daughter board card. The default value should be 10.9.70.193. You will need to use this IP address to initially access the board for operation or to change its IP address.4.3.1Changing the IP Address of the BoardDetermine and write down the new unique IP address you wish to change the board to.Directly connect an Ethernet cable from a PC to the Rabbit board.Note : Some older PCs do not support auto-crossover on the Ethernet connection so a cross-over cable may be unch a DOS command window by clicking on the Start->Run button and typing “cmd”.Within the DOS command window type “Telnet”In Telnet, connect to the Rabbit board’s address using the open command by typing “open 10.9.70.^XXX”.10.9.70.xxx where xxx is the value on your board from the factory (typically 193).You should have a prompt and be able to type help to get a list of commands available on the Rabbit.If you are unable to connect, then most likely you will need to change the IP address of the connected PC to have the first 3 octets similar to the board by following the subsequent steps.On the PC under Windows -> Control Panel → Network Connections → Local Area Connection, right mouse click for Properties. Under the General tab highlight Internet Protocol (TCP/IP) and click on Properties. From there enter the new PC IP address such as 10.9.70.yyy where yyy is a unique value and NOT the same as the Rabbit board. Once complete, return to step 4.Command the board to change its IP address to the new one by typing into Telnet now connected to the board the command: set ip <new IP address> <Enter> where <new IP address> is in the form xxx.xxx.xxx.xxx. Once you hit <Enter> the IP address will be changed and the Rabbit will save the value and reboot which may take approximately 1 minute. The Telnet session will disconnect from the board.Change your PC IP address to the same IP network as the Rabbit board.Telnet to the Rabbit board.Use the following commands to complete configuration of the Rabbit board:11. a. b. c. 12. 13. Use the following commands to complete configuration of the Rabbit board:Set netmask xxx.xxx.xxx.xxx Set gateway xxx.xxx.xxx.xxx Save envPlease record and inform Vitesse of the new IP address of the board when you return so that Vitesse can connect to and reconfigure the board.Re-label the Rabbit board with the new IP.4.4Using the Control SoftwareConnect the VSC8574EV Rabbit microcontroller RJ-45 directly to the PC or through a network switch if properly configured. Apply +5VDC to the EVB.Launch the GUI by double-clicking the GUI shortcut located in C:\TeslaGUI_4_65 or on the desktop if it has been moved there. The GUI Connection window shown in Figure 3 should appear.Figure 3 • GUI Connection WindowTo make a connection to the EVB, click “Rabbit” and enter the IP address of the EVB, then click on1. 2. 3. 4. 5. 6. 1. 2. 3. 4. 5. To make a connection to the EVB, click “Rabbit” and enter the IP address of the EVB, then click on “Connect”. The display next to the IP address window should change to “Connected”. If it does not, check the IP address, or your network configuration until connection with the EVB can be successfully established.Double-click on “MII Registers” and the window shown in Figure 4 should appear:Figure 4 • MII Registers GUI WindowVerify the device is up and running by reading MII Register 0. It should read back 0x1040. Reading back all 0’s or all 1’s indicates a problem. A checked box means the bit is set to “1”, if unchecked it is “0”.4.4.1Copper Media Operation (1000BASE-T)A single register write and some external coax cables enables 1G Ethernet traffic to be received by the VSC8574 RJ-45 port, routed through the VSC8574 and externally via coax loopback cables through the SGMII interface and transmitted back to the traffic source on the same copper port. First configure the SerDes in SGMII mode by writing to Micro page 18’d. This is a global setting and does not need to be applied per port.Set up the Copper traffic source (ie: IXIA or Smartbits)Connect an Ethernet cable to an RJ-45 Port 0.Connect two matched coax cables, J1 – J4 and J2 – J3.Write using the “Micro Page Registers” window: 18’d 0x80F0.When “Micro Page” 18’d is read back, bit 15 will clear.Linkup bit is in MII Reg 1, bit 2 (MII 1.2), read twice to updateTraffic should be flowing.4.4.2Fiber Media Operation (100BASE-FX)Follow all steps in section 2.53 with fiber media connection to (IXIA) and add the following steps.Write using the “Micro Page Registers” window: 18’d 0x8FD1. (Global)When “Micro Page” 18’d is read back, bit 15 will clear.Write “MII Register” (PHY 0) 23’d 0x0304 (Sets Media Mode)Write “MII Register” (PHY0) 0’d 0x9040 (SW Reset for media mode setting to have effect)Write “Extended MII Register” (PHY0) 19’d 0x0001 (Flip SIGDET polarity if necessary)5. 6. 1. 2. 3. 4. 5. 6. Write “Extended MII Register” (PHY0) 19’d 0x0001 (Flip SIGDET polarity if necessary)Write “MII Register” (PHY0) 0’d 0x0004 (Disable Auto Neg if necessary)4.4.3Fiber Media Operation (1000BASE-X)Follow all steps in section 3.4.1 with fiber media connection to (IXIA) and add the following steps.Write using the “Micro Page Registers” window: 18’d 0x8FC1. (Global)When “Micro Page” 18’d is read back, bit 15 will clear.Write “MII Register” (PHY 0) 23’d 0x0204 (Sets Media Mode)Write “MII Register” (PHY0) 0’d 0x9040 (SW Reset for media mode setting to have effect)Write “Extended MII Register” (PHY0) 19’d 0x0001 (Flip SIGDET polarity if necessary)Write “MII Register” (PHY0) 0’d 0x0004 (Disable Auto Neg if necessary)Traffic should be flowing.4.5Useful Registers 4.5.1Ethernet Packet GeneratorExtMII 29E is the Ethernet Packet Generator register. Refer to the datasheet for configuration options.A Good CRC packet counter is in ExtMII 18.13:0. A read of the register reads back the good CRC packets and then clears the register so the subsequent reads will be 0 if no traffic has been received. If traffic has been received since the last read, bit 15 will be set.4.5.2Copper PHY Error CountersIdle errors = MII 10.7:0RX errors = MII 19.7:0False carrier = MII 20.7:0Disconnects = MII 21.7:0CRC errors = ExtMII 23.7:04.5.3Fiber PHY Error CountersGood RX CRC packets = Ext3MII 28.13:0Bad RX CRC packets = Ext3MII 29.7:0Good TX CRC packets = Ext3MII 21.13:0Bad TX CRC packets = Ext3MII 22.7:05Additional InformationFor any additional information or questions regarding the device(s) mentioned in this document, contactyour local sales representative.Microsemi HeadquartersOne Enterprise, Aliso Viejo,CA 92656 USAWithin the USA: +1 (800) 713-4113Outside the USA: +1 (949) 380-6100Sales: +1 (949) 380-6136Fax: +1 (949) 215-4996Email:***************************© 2014 Microsemi. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided "as is, where is" and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice.Microsemi, a wholly owned subsidiary of Microchip Technology Inc. (Nasdaq: MCHP), offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication solutions; security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, California, and has approximately 4,800 employees globally. Learn more at www. .VPPD-03067。
PCF8574中文资料
15
16
FEATURES
GENERAL DESCRIPTION
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING CHARACTERISTICS OF THE I2C-BUS
Bit transfer Start and stop conditions System configuration Acknowledge
The PCF8574 and PCF8574A versions differ only in their slave address as shown in Fig.9.
3 ORDERING INFORMATION
TYPE NUMBER
PCF8574P; PCF8574AP PCF8574T; PCF8574AT PCF8574TS
1997 Apr 02
元器件交易网
Philips Semiconductors
Remote 8-bit I/O expander for I2C-bus
CONTENTS
1
2
3
4
5
6
6.1 6.2 6.3 6.4
7
7.1 7.2 7.3
8
9
10
11
12
13
13.1 13.2 13.2.1 13.2.2 13.3 13.3.1 13.3.2 13.3.3
handbook, halfpage
INT 1
20 P7
SCL 2 n.c. 3
19 P6 18 n.c.
SDA 4
17 P5
VDD 5 A0 6
16 P4
PCF8574TS 15 VSS
I2C接口地输入与输出驱动地PCF8574-
I2C接口的输入与输出驱动的PCF8574-pcf8574采用I2C接口，有8个准双向口，可以和外部电路连接，来实现输入输出功能，可以用来对口线进行扩展有几点需要注意1.某位作为输入的时候，必须首先置为高电平2.地址是0100 A2 A1 A0 R/W3.最多可以扩展8片4.低电流损耗，静态电流10uA,驱动电流比较大，而且有索存功能，能够驱动LED 发光管5.带有外部中断输出，低电平有效我作了一个电路，其中P7-P4作为输入检测开关状态，P3-P0作为输出来驱动LED灯程序如下#include "reg51.h"#define SETBIT(VAR,Place) (VAR|=(1<<Place))#define CLRBIT(VAR,Place) (VAR&=((1<<Place)^255))sbit IC_SCL=P3^6;sbit IC_SDA=P3^7;unsigned char IC_Re_Time;unsigned char IC_Err_Flag;void Timer0_Init(void){TMOD=0x00; //timer0工作定时器方式0，13位技术TH0=0x1e; //5msTL0=0x0c; //5msTR0=1; //启动时钟0ET0=1; //允许时钟0进行中断EA=1; //开放所有中断}void Delay(void){unsigned char i;for(i=0;i<=10;i++){}}unsigned char VALBIT(unsigned int Val,unsigned char Bit) {unsigned int Buf;Buf=0x0001;if(Bit)Buf<<=Bit;Val&=Buf;if(Val)return(0xff);elsereturn(0x00);}/**********************************************下面是PCF8574的操作程序1.通信方式:I2C2.通信端口:IC_SCL(P3.6),IC_SDA(P3.7)3.通信地址:0x0101000x***********************************************/void IC_Start(void) //启动IC通信IC_SDA=1;Delay();IC_SCL=1;Delay();IC_SDA=0;Delay();IC_SCL=0;Delay();}void IC_Stop(void) //停止IC通信{IC_SDA=0;Delay();IC_SCL=1;Delay();IC_SDA=1;Delay();}void IC_Receive_Ack(void) //接受ACK {IC_SDA=1;IC_SCL=1;Delay();IC_Re_Time=0;while(IC_Re_Time<=30){if(IC_SDA==0){IC_Err_Flag=0;break;}else{IC_Err_Flag=1;}}IC_SCL=0;Delay();}//void IC_Send_ACK(void) //发送ACK//{ //if read many datas at a time,this can be used // IC_SDA=0;// Delay();// IC_SCL=1;// Delay();// IC_SCL=0;// Delay();// IC_SDA=1;//}void IC_Send_NAck(void) //发送NACK{IC_SDA=1;Delay();IC_SCL=1;Delay();IC_SCL=0;Delay();}void IC_Write_Byte(unsigned char Data) //写数据到8574{unsigned char i;for(i=0;i<=7;i++){if(VALBIT(Data,(7-i))) //data out msbIC_SDA=1;elseIC_SDA=0;IC_SCL=1;Delay();IC_SCL=0;Delay();}}unsigned char IC_Read_Byte(void) //从8574读取一个数据{unsigned char i;unsigned char Data;for(i=0;i<=7;i++){IC_SCL=1;Delay();IC_SDA=1;Delay();if(IC_SDA)SETBIT(Data,(7-i)); //data in msb tooCLRBIT(Data,(7-i));IC_SCL=0;Delay();}return(Data);}void IC_Write_Data(unsigned char Data){unsigned char write_time;unsigned char write_data;write_data=Data;for(write_time=0;write_time<=2;write_time++) {IC_Start();IC_Write_Byte(0x40);IC_Receive_Ack();IC_Write_Byte(write_data);IC_Receive_Ack();IC_Stop();if(IC_Err_Flag==0)break;}unsigned char IC_Read_Data(void){unsigned char Return_Data;unsigned char read_time;for(read_time=0;read_time<=2;read_time++) {IC_Start();IC_Write_Byte(0x41);IC_Receive_Ack();Return_Data=IC_Read_Byte();IC_Send_NAck();IC_Stop();if(IC_Err_Flag==0){return(Return_Data);break;}}}void PCF8574_Init(void)IC_Write_Data(0xf0); //输入状态的必须开始的时候置为1，输出为0 }void main(void){unsigned char temp3;Timer0_Init();PCF8574_Init();while(1){temp3=IC_Read_Data();IC_Write_Data(0x0f);Delay();；中间可以添加你需要的模块，比如显示或者其他的操作等}}/********************************************************** 中断服务子程序**********************************************************/extern void external0_rt(void)interrupt 0//INT0{extern void eit0_rt(void)interrupt 1//T0，标准，定时中断{TH0=0x1e;TL0=0x0c;IC_Re_Time++;}void external1_rt(void)interrupt 2 using 1//INT1{}void eit1_rt(void)interrupt 3 using 1//T1，标准{}void sci_rt(void)interrupt 4 using 1//UART{}void eit2_rt(void)interrupt 5 using 1//T2 3种工作模式，输入捕捉、自动重载和波形发生器{void PCA_rt(void)interrupt 6 using 1//PCA{}void KBDIT_rt(void)interrupt 7 using 1//keyboard {}void spi_rt(void)interrupt 9 using 1//SPI{}。
用两片I_2C总线接口通用器件PCF8574扩展的8_8键盘
SIDA T (DA H)
D7 D6 D5 D4 D3 D2 D1 D0 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
它为串行输入输出结构的核心部分 ,用来存放一
个发送的数据字节或刚收到的一个数据字节 。
的编址方法 ,避免了片选线的连接方法 。 5. 所有带 I2C 总线接口的外围器件都具有应答功
(单片机 、微处理器等) 、外围器件等都连到同名端的
SIADR (DB H)
D7 D6 D5 D4 D3 D2 D1 D0 × × × × × × × GC
自己从地址
SDA (串行数据线) 、SCL (串行时钟线) 上 ,并通过这两 根线在器件之间传送信息 。
2. 系统中 有 多 个 主 器 件 时 , 任 何 一 个 主 器 件 在 I2C 上工作时都可成为主控制器 (无中心主机) 。
RET
;状态处理程序高、低位地址进入 PC
( 三) I2C 总线初始化及通用读写子程序
D7 D6 D5 D4 D3 D2 D1 D0
一般情况下 ,可把 I2C 总线的初始化和通用读写
0100 器件地址
× × × R/ W 引脚地址
子程序合写为一个包括 I2C 总线初始化的通用读写子 程序 。使用时只需满足通用读写子程序的入口条件 , 直接调用通用读写子程序 ,就可完成包括启动 I2C 总
I2C 总线 的 状 态 产 生 开 始 信 号 或 重 复 开 始 信 号 ; 当 STA = 0 时 ,SIO1 不产生开始信号或重复开始信号 。
[教学设计]I2C总线8位远程IO扩展口芯片PCF8574的驱动程序
![[教学设计]I2C总线8位远程IO扩展口芯片PCF8574的驱动程序](https://img.taocdn.com/s3/m/f9e72edc02020740bf1e9ba6.png)
[教学设计]I2C总线8位远程IO扩展口芯片PCF8574的驱动程序I2C总线8位远程IO扩展口芯片PCF8574的驱动程序//...................................... //名称: PCF8574(A).c I2C扩展8位I/O芯片的接口程序//编程: 不详//日期: 20111025////发现问题请指点，谢谢～//...................................... //CPU: 89C55 11.0592MHz //环境: Keil C51 V8.01//引脚定义:// CPU_P2.0 --- PCF8574X_SCL 时钟// CPU_P2.1 --- PCF8574X_SDA 数据 // CPU_P2.2 --- PCF8574X_INT 中断//...................................... #include <Public.h> #include <Intrins.h>#include "delay_s.h"#include "pcf8574.h"//PCF8574(A)芯片指令的定义#define PCF8574_WRITE 0x40 //器件地址= 0111 A2 A1 A0r/w#define PCF8574_READ 0x41 //器件地址= 0111 A2 A1 A0 r/w#define PCF8574A_WRITE 0x70 //器件地址= 0111 A2 A1 A0r/w#define PCF8574A_READ 0x71 //器件地址= 0111 A2 A1 A0r/w#define PCF8574X_REGISTER_ADDR_MAX 7 //器件内部寄存器地址的最大值//内部函数static void i2c_start_cond(void);static void i2c_stop_cond(void);static uchar i2c_read_byte(void);static uchar i2c_read_byte_nack(void);static void i2c_write_byte(uchar da);//========================================================= ====================//接口调用函数部分//******************************************************* //序号:// HD_PCF8574X_S01//功能:// 读出芯片的复位状态//输入:// is_pcf8574a =1 是A芯片// add_of_part 器件的子地址 0~3//输出:// 端口的数据//******************************************************** uchar PCF8574X_read_io(uchar is_pcf8574a, uchar add_of_part) {uchar i;i2c_start_cond();if(is_pcf8574a !=0){i2c_write_byte(PCF8574A_READ |((add_of_part <<1)&0x0E));//器件地址=0111 A2 A1 A0 r/w}else{i2c_write_byte(PCF8574_READ |((add_of_part <<1)&0x0E));//器件地址=0100 A2 A1 A0 r/w}i =i2c_read_byte_nack(); //顺序读的方式读出一个字节i2c_stop_cond();return(i);}//*******************************************************//序号:// HD_PCF8574X_S02//功能:// 写数据到I/O端口//输入:// is_pcf8574a =1 是A芯片 // add_of_part: 器件的子地址 0~7 // dat: 写入的字节//输出:// 无//********************************************************void PCF8574X_write_io(uchar is_pcf8574a, uchar add_of_part,uchar dat){i2c_start_cond();if(is_pcf8574a !=0){i2c_write_byte(PCF8574A_WRITE |((add_of_part <<1) &0x0E)); //器件地址=0111 A2 A1 A0 r/w}else{i2c_write_byte(PCF8574_WRITE |((add_of_part <<1)&0x0E)); //器件地址=0100 A2 A1 A0 r/w}i2c_write_byte(dat);i2c_stop_cond();}//==============//内部调用函数部分//==============//----------------------------------------------//I2C 发启始条件:时钟线为高时数据线发生下降沿跳变//----------------------------------------------static void i2c_start_cond(void){CODE_SCL_LOW;_DELAY_NOP3;CODE_SDA_HIGH;_DELAY_NOP3;CODE_SCL_HIGH;_DELAY_NOP3;CODE_SDA_LOW;_DELAY_NOP3;}//---------------------------------------- //I2C 发结束条件:时钟线为高时数据线发生上升沿跳变//----------------------------------------static void i2c_stop_cond(void) {CODE_SCL_LOW;_DELAY_NOP3;CODE_SDA_LOW;_DELAY_NOP3;CODE_SCL_HIGH;_DELAY_NOP3;CODE_SDA_HIGH;_DELAY_NOP3;}//---------------------------------------- // I2C 读取一个中间字节的数据 //---------------------------------------- /*static uchar i2c_read_byte(void) {uchar i;uchar da=0;for(i =0; i<8; i++){da <<=1; //传输的数据高位在前CODE_SCL_LOW;_DELAY_NOP3;CODE_SCL_HIGH; //时钟为高时读数据//NOP3;if (JUDGE_PCF8574X_SDA) da++;}CODE_SCL_LOW;_DELAY_NOP3;CODE_SDA_LOW; //发送应答位_DELAY_NOP3;CODE_SCL_HIGH;_DELAY_NOP3;CODE_SCL_LOW;_DELAY_NOP3;CODE_SDA_HIGH;return(da);}*///---------------------------------------- // I2C 读取一个结尾字节的数据 //---------------------------------------- static uchari2c_read_byte_nack(void) {uchar i;uchar da =0;for (i =0; i<8; i++){da <<=1;CODE_SCL_LOW;_DELAY_NOP3;CODE_SCL_HIGH;//NOP3;if(JUDGE_PCF8574X_SDA) da++;}CODE_SCL_LOW;_DELAY_NOP3;CODE_SDA_HIGH;_DELAY_NOP3;CODE_SCL_HIGH;_DELAY_NOP3;CODE_SCL_LOW;return( da );}//----------------------------------------// I2C 写入一个字节的数据 //---------------------------------------- static void i2c_write_byte(uchar da ){uchar i;for(i =0; i<8; i++){CODE_SCL_LOW;if(da&0x80){CODE_SDA_HIGH;}else{CODE_SDA_LOW;}CODE_SCL_HIGH;da <<=1;}CODE_SCL_LOW; //第8个SCL下降沿,写入8位数据_DELAY_NOP3;CODE_SDA_HIGH;_DELAY_NOP3;CODE_SCL_HIGH; }//========================================================= ====================//End Of File。
PCA8574中文资料
1.General descriptionThe PCA8574/74A provide general purpose remote I/O expansion for mostmicrocontroller families via the two-line bidirectional I 2C-bus (serial clock (SCL), serial data (SDA)).The devices consist of an 8-bit quasi-bidirectional port and an I 2C-bus interface. ThePCA8574/74A have low current consumption and include latched outputs with 25mA high current drive capability for directly driving LEDs.The PCA8574/74A also possess an interrupt line (INT) that can be connected to theinterrupt logic of the microcontroller.By sending an interrupt signal on this line,the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I 2C-bus.The internal Power-On Reset (POR) initializes the I/Os as inputs.2.FeaturesI 400kHz I 2C-bus interfaceI 2.3V to 5.5V operation with 5.5V tolerant I/OsI 8-bit remote I/O pins that default to inputs at power-upI Latched outputs with 25mA sink capability for directly driving LEDs I T otal package sink capability of 200mA I Active LOW open-drain interrupt outputI 8 programmable slave addresses using 3 address pinsI Readable device ID (manufacturer, device type, and revision)I Low standby current (10µA max.)I −40°C to +85°C operationIESD protection exceeds 2000V HBM per JESD22-A114, 200V MM per JESD22-A115, and 1000V CDM per JESD22-C101I Latch-up testing is done to JEDEC standard JESD78 which exceeds 100mA I Packages offered: DIP16, SO16, TSSOP16, SSOP203.ApplicationsI LED signs and displays I ServersI Industrial control I Medical equipment IPLCsPCA8574/74ARemote 8-bit I/O expander for I 2C-bus with interruptRev. 02 — 14 May 2007Product data sheetI Cellular telephones I Gaming machinesI Instrumentation and test measurement4.Ordering information5.Block diagramTable 1.Ordering informationType number Topside mark Package Name DescriptionVersion PCA8574D PCA8574D SO16plastic small outline package; 16 leads; body width 7.5mmSOT162-1PCA8574AD PCA8574AD PCA8574N PCA8574N DIP16plastic dual in-line package; 16 leads (300mil); long bodySOT38-1PCA8574AN PCA8574AN PCA8574PW PCA8574TSSOP16plastic thin shrink small outline package; 16 leads;body width 4.4mmSOT403-1PCA8574APW PA8574A PCA8574TS PCA8574SSOP20plastic shrink small outline package; 20 leads;body width 4.4mmSOT266-1PCA8574A TSPCA8574AFig 1.Block diagram of PCA8574/74A002aac677INT I 2C-BUS CONTROLINTERRUPT LOGICPCA8574PCA8574ALP FILTERAD0AD1AD2INPUT FILTERSHIFT REGISTERSDASCL 8 BITSwrite pulse read pulsePOWER-ON RESETV DD V SSI/O PORTP0 to P76.Pinning information6.1PinningFig 2.Simplified schematic diagram of P0 to P7002aac109write pulseread pulseD CI SFF Qpower-on resetdata from Shift RegisterI trt(pu)100 µAI OHI OLV DDP0 to P7V SSD CI S FFQdata to Shift Registerto interrupt logicFig 3.Pin configuration for DIP16Fig 4.Pin configuration for SO16PCA8574N PCA8574ANAD0V DD AD1SDA AD2SCLP0INT P1P7P2P6P3P5V SSP4002aac67912345678109121114131615PCA8574D PCA8574ADAD0V DD AD1SDA AD2SCLP0INT P1P7P2P6P3P5V SSP4002aac678123456781091211141316156.2Pin descriptionFig 5.Pin configuration for TSSOP16Fig 6.Pin configuration for SSOP20PCA8574PW PCA8574APWAD0V DD AD1SDA AD2SCLP0INT P1P7P2P6P3P5V SSP4002aac94112345678109121114131615PCA8574TS PCA8574ATSINT P7SCLP6n.c.n.c.SDA P5V DD P4AD0V SS AD1P3n.c.n.c.AD2P2P0P1002aac6801234567891012111413161518172019Table 2.Pin description for DIP16, SO16, TSSOP16Symbol Pin Description AD01address input 0AD12address input 1AD23address input 2P04quasi-bidirectional I/O 0P15quasi-bidirectional I/O 1P26quasi-bidirectional I/O 2P37quasi-bidirectional I/O 3V SS 8supply groundP49quasi-bidirectional I/O 4P510quasi-bidirectional I/O 5P611quasi-bidirectional I/O 6P712quasi-bidirectional I/O 7INT 13interrupt output (active LOW)SCL 14serial clock line SDA 15serial data line V DD16supply voltageTable 3.Pin description for SSOP20Symbol Pin DescriptionINT1interrupt output (active LOW) SCL2serial clock linen.c.3not connectedSDA4serial data lineV DD5supply voltageAD06address input 0AD17address input 1n.c.8not connectedAD29address input 2P010quasi-bidirectional I/O0P111quasi-bidirectional I/O1P212quasi-bidirectional I/O2n.c.13not connectedP314quasi-bidirectional I/O3V SS15supply groundP416quasi-bidirectional I/O4P517quasi-bidirectional I/O5n.c.18not connectedP619quasi-bidirectional I/O6P720quasi-bidirectional I/O77.Functional descriptionRefer to Figure 1 “Block diagram of PCA8574/74A”.7.1Device addressFollowing a START condition, the bus master must send the address of the slave it is accessing and the operation it wants to perform (read or write). The address of thePCA8574/74A is shown in Figure 7. Slave address pins AD2, AD1, and AD0 choose 1 of 8slave addresses. T o conserve power, no internal pull-up resistors are incorporated on AD2, AD1, and AD0. Address values depending on AD2, AD1, and AD0 can be found in Table 4 “PCA8574 address map” and T able 5 “PCA8574A address map”.Remark:When using the PCA8574A, the General Call address (00000000b) and the Device ID address (1111100Xb) are reserved and cannot be used as device address.Failure to follow this requirement will cause the PCA8574A not to acknowledge.The last bit of the first byte defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation.When AD2, AD1 and AD0 are held to V DD or V SS , the same address as the PCF8574 or PCF8574A is applied.7.1.1Address mapsFig 7.PCA8574/74A addressR/W002aab636A6A5A4A3A2A1A0programmableslave addressTable 4.PCA8574 address map A6A5A4A3A2A1A0Address 010000020h 010000121h 010001022h 010001123h 010010024h 010010125h 010011026h 0111127hTable 5.PCA8574A address mapA6A5A4A3A2A1A0Address011100038h011100139h01110103Ah01110113Bh01111003Ch01111013Dh01111103Eh01111113Fh8.I/O programming8.1Quasi-bidirectional I/O architectureThe PCA8574/74A’s 8ports (see Figure2) are entirely independent and can be usedeither as input or output ports. Input data is transferred from the ports to themicrocontroller in the Read mode(see Figure9).Output data is transmitted to the ports inthe Write mode (see Figure8).This quasi-bidirectional I/O can be used as an input or output without the use of a controlsignal for data directions. At power-on the I/Os are HIGH. In this mode only a currentsource (I OH) to V DD is active. An additional strong pull-up to V DD (I trt(pu)) allows fast risingedges into heavily loaded outputs.These devices turn on when an output is written HIGH,and are switched off by the negative edge of SCL.The I/Os should be HIGH before beingused as inputs. After power-on, as all the I/Os are set HIGH, all of them can be used asinputs. Any change in setting of the I/Os as either inputs or outputs can be done with thewrite mode.Remark:If a HIGH is applied to an I/O which has been written earlier to LOW, a largecurrent (I OL) will flow to V SS.8.2Writing to the port (Output mode)To write, the master (microcontroller) first addresses the slave device. By setting the lastbit of the byte containing the slave address to logic0 the write mode is entered. ThePCA8574/74A acknowledges and the master sends the data byte for P7 to P0 and isacknowledged by the PCA8574/74A. The 8-bit data is presented on the port lines after ithas been acknowledged by the PCA8574/74A.The number of data bytes that can be sent successively is not limited. The previous datais overwritten every time a data byte has been sent.8.3Reading from a port (Input mode)All ports programmed as input should be set to logic 1. To read, the master(microcontroller) first addresses the slave device after it receives the interrupt. By setting the last bit of the byte containing the slave address to logic 1 the Read mode is entered.The data bytes that follow on the SDA are the values on the ports.If the data on the input port changes faster than the master can read, this data may be lost.Fig 8.Write mode (output)A5A4A3A2A1A00A S A6slave addressSTART conditionR/Wacknowledge from slave002aac120P61P7data 1A acknowledge from slave12345678SCL 9SDA A acknowledge from slavewrite to portdata output from port t v(Q)P5data 2DATA 2 VALIDP4P3P2P1P0P7P4P3P2P1P00P5P5t v(Q)DATA 1 VALIDP5 output voltageI trt(pu)I OHP5 pull-up output current t d(rst)INTA LOW-to-HIGH transition of SDA while SCL is HIGH is defined as the STOP condition (P).T ransfer of data can be stopped at any moment by a STOP condition.When this occurs,data present at the last acknowledge phase is valid (Output mode).Input data is lost.Fig 9.Read input port registerA5A4A3A2A1A01AS A6slave addressSTART conditionR/Wacknowledge from slave 002aac121data from port Aacknowledge from masterSDA 1no acknowledge from master read fromportdata intoportdata from port DATA 1DATA 4INTDATA 4DATA 2DATA 3P STOP conditiont v(Q)t d(rst)t h(D)t su(D)t d(rst)8.4Power-on resetWhen power is applied to V DD, an internal Power-On Reset (POR) holds thePCA8574/74A in a reset condition until V DD has reached V POR. At that point, the reset condition is released and the PCA8574/74A registers and I2C-bus/SMBus state machine will initialize to their default states. Thereafter V DD must be lowered below 0.2V to reset the device.8.5Interrupt output (INT)The PCA8574/74A provides an open-drain interrupt (INT) which can be fed to acorresponding input of the microcontroller (see Figure8,Figure9, and Figure10). This gives these chips a kind of master function which can initiate an action elsewhere in the system.An interrupt is generated by any rising or falling edge of the port inputs.After time t v(D)the signal INT is valid.The interrupt disappears when data on the port is changed to the original setting or data is read from or written to the device which has generated the interrupt.In the write mode,the interrupt may become deactivated(HIGH)on the rising edge of the write to port pulse. On the falling edge of the write to port pulse the interrupt is definitely deactivated (HIGH).The interrupt is reset in the read mode on the rising edge of the read from port pulse.During the resetting of the interrupt itself, any changes on the I/Os may not generate an interrupt.After the interrupt is reset any change in I/Os will be detected and transmitted as an INT.Fig 10.Application of multiple PCA8574s with interrupt 002aac682V DDMICROCOMPUTERINT PCA8574INTPCA8574INTdevice 1device 2PCA8574INTdevice 89.Characteristics of the I 2C-busThe I 2C-bus is for 2-way,2-line communication between different ICs or modules.The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must beconnected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.9.1Bit transferOne data bit is transferred during each clock pulse.The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 11).9.1.1START and STOP conditionsBoth data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOWtransition of the data line while the clock is HIGH is defined as the START condition (S).A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 12.)9.2System configurationA device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 13).Fig 11.Bit transfermba607data line stable;data validchange of data allowedSDASCLFig 12.Definition of START and STOP conditionsmba608SDA SCLPSTOP conditionSDASCLSSTART condition9.3AcknowledgeThe number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by oneacknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,whereas the master generates an extra acknowledge related clock pulse.A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse,so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold times must be taken into account.A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.Fig 13.System configuration002aaa966MASTER TRANSMITTER/RECEIVERSLAVE RECEIVERSLAVETRANSMITTER/RECEIVERMASTER TRANSMITTERMASTER TRANSMITTER/RECEIVERSDA SCLI 2C-BUS MULTIPLEXERSLAVEFig 14.Acknowledgement on the I 2C-bus002aaa987S START condition9821clock pulse for acknowledgementnot acknowledgeacknowledgedata output by transmitterdata output by receiverSCL from master10.Application design-in information10.1Bidirectional I/O expander applicationsIn the 8-bit I/O expander application shown in Figure 15,P0and P1are inputs,and P2to P7 are outputs. When used in this configuration, during a write, the input (P0 and P1)must be written as HIGH so the external devices fully control the input ports. The desired HIGH or LOW logic levels may be written to the I/Os used as outputs (P2to P7).During a read, the logic levels of the external devices driving the input ports (P0 and P1) and the previous written logic level to the output ports (P2 to P7) will be read.The GPIO also has an interrupt line (INT) that can be connected to the interrupt logic of the microprocessor.By sending an interrupt signal on this line,the remote I/O informs the microprocessor that there is incoming data or a change of data on its ports without having to communicate via the I 2C-bus.10.2High current-drive load applicationsThe GPIO has a maximum sinking current of 25mA per bit. In applications requiring additional drive, two port pins in the same octal may be connected together to sink up to 50mA current. Both bits must then always be turned on or off together. Up to 8 pins (one octal) can be connected together to drive 200mA.Fig 15.Bidirectional I/O expander application002aac123V DDtemperature sensor battery status control for latch control for switch control for audio control for camera control for MP3P0P1P2P3P4P5P6P7V DDSDA SCL INTAD0AD1AD2CORE PROCESSORV DDFig 16.High current-drive load application002aac124V DDP0P1P2P3P4P5P6P7V DD SDA SCL INTAD0AD1AD2CORE PROCESSORV DDLOAD11.Limiting valuesTable 6.Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).Symbol Parameter Conditions Min Max UnitV DD supply voltage−0.5+6VI DD supply current-±100mAI SS ground supply current-±400mAV I input voltage V SS−0.5 5.5VI I input current-±20mAI O output current[1]-±50mAP tot total power dissipation-400mWP/out power dissipation per output-100mWT stg storage temperature−65+150°CT amb ambient temperature operating−40+85°C[1]Total package (maximum) output current is 400mA.12.Static characteristics[1]The power-on reset circuit resets the I 2C-bus logic with V DD <V POR and sets all I/Os to logic 1 (with current source to V DD ).[2]Each bit must be limited to a maximum of 25mA and the total package limited to 200mA due to internal busing limits.[3]The value is not tested, but verified on sampling basis.Table 7.Static characteristicsV DD =2.3V to 5.5V; V SS =0V; T amb =−40°C to +85°C; unless otherwise specified.Symbol Parameter Conditions Min Typ Max Unit Supplies V DD supply voltage 2.3- 5.5V I DDsupply currentOperating mode; no load;V I =V DD or V SS ;f SCL =400kHz;AD0, AD1, AD2=static H or L -200500µAI stb standby current Standby mode; no load;V I =V DD or V SS ; f SCL =0kHz- 4.510µA V POR power-on reset voltage [1]- 1.8 2.0V Input SCL; input/output SDAV IL LOW-level input voltage −0.5-+0.3V DD V V IH HIGH-level input voltage 0.7V DD- 5.5V I OLLOW-level output currentV OL =0.4V; V DD =2.3V 2035-mA V OL =0.4V; V DD =3.0V 2544-mA V OL =0.4V; V DD =4.5V3057-mA I L leakage current V I =V DD or V SS −1-+1µA C i input capacitance V I =V SS-510pF I/Os; P0 to P7I OLLOW-level output currentV OL =0.5V; V DD =2.3V [2]1226-mA V OL =0.5V; V DD =3.0V [2]1733-mA V OL =0.5V; V DD =4.5V[2]2540-mA I OL(tot)total LOW-level output current V OL =0.5V; V DD =4.5V [2]--200mA I OH HIGH-level output current V OH =V SS−30−138−300µA I trt(pu)transient boosted pull-up current V OH =V SS ; see Figure 8−0.5−1.0-mA C i input capacitance [3]- 2.110pF C o output capacitance [3]- 2.110pF Interrupt INT (see Figure 8 and Figure 9)I OL LOW-level output current V OL =0.4V3.0--mA C o output capacitance -35pF Inputs AD0, AD1, AD2V IL LOW-level input voltage −0.5-+0.3V DD V V IH HIGH-level input voltage 0.7V DD - 5.5V I LI input leakage current −1-+1µA C iinput capacitance-3.55pF13.Dynamic characteristics[1]t VD;ACK =time for Acknowledgement signal from SCL LOW to SDA (out) LOW.[2]t VD;DA T =minimum time for SDA data out to be valid following SCL LOW.[3] A master device must internally provide a hold time of at least 300ns for the SDA signal (refer to the V IL of the SCL signal) in order to bridge the undefined region SCL ’s falling edge.[4]The maximum t f for the SDA and SCL bus lines is specified at 300ns. The maximum fall time for the SDA output stage t f is specified at 250ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t f .[5]C b =total capacitance of one bus line in pF .[6]Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.Table 8.Dynamic characteristicsV DD =2.3V to 5.5V; V SS =0V; T amb =−40°C to +85°C; unless otherwise specified. Limits are for Fast-mode I 2C-bus.Symbol ParameterConditions Min Typ Max Unit f SCL SCL clock frequency0-400kHz t BUF bus free time between a STOP and START condition1.3--µs t HD;STA hold time (repeated) ST ART condition 0.6--µs t SU;ST A set-up time for a repeated ST ART condition 0.6--µs t SU;STO set-up time for STOP condition 0.6--µs t HD;DA T data hold time0--ns t VD;ACK data valid acknowledge time [1]0.1-0.9µs t VD;DA T data valid time [2]50--ns t SU;DA T data set-up time100--ns t LOW LOW period of the SCL clock 1.3--µs t HIGH HIGH period of the SCL clock 0.6--µs t f fall time of both SDA and SCL signals [3][4]20+0.1C b [5]-300ns t r rise time of both SDA and SCL signals 20+0.1C b [5]-300ns t SPpulse width of spikes that must be suppressed by the input filter [6]--50nsPort timing; C L ≤100pF (see Figure 8 and Figure 9)t v(Q)data output valid time --4µs t su(D)data input set-up time 0--µs t h(D)data input hold time 4--µs Interrupt timing; C L ≤100pF (see Figure 8 and Figure 9)t v(D)data input valid time --4µs t d(rst)reset delay time--4µsRise and fall times refer to V IL and V IH .Fig 17.I 2C-bus timing diagramSCLSDAt HD;STA t SU;DA T t HD;DA T t ft BUFt SU;ST At LOWt HIGHt VD;ACK 002aab175t SU;STOprotocolST ART condition (S)bit 7MSB (A7)bit 6(A6)bit 0(R/W)acknowledge(A)STOP condition (P)1/fSCLt rt VD;DA T14.Package outlineFig 18.Package outline SOT38-1 (DIP16)UNIT Amax.12b 1c E e M H L REFERENCESOUTLINE VERSION EUROPEAN PROJECTIONISSUE DATE IEC JEDEC JEITA mm inchesDIMENSIONS (inch dimensions are derived from the original mm dimensions)SOT38-199-12-2703-02-13A min. A max.b max.w M E e 11.401.140.0550.0450.530.380.320.2321.821.40.860.846.486.200.260.243.93.40.150.130.2542.547.620.38.257.800.320.319.58.30.370.332.20.0874.70.51 3.70.150.0210.0150.0130.0090.010.10.020.19050G09MO-001SC-503-16M Hc(e )1M EALs e a t i n g p l a n eA 1w Mb 1eDA 2Z16198bEpin 1 index0510 mmscaleNote1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.(1)(1)D (1)Z DIP16: plastic dual in-line package; 16 leads (300 mil); long bodySOT38-1UNITAmax.A1A2A3b p c D(1)E(1)(1)e H E L L p Q ZywvθREFERENCESOUTLINE VERSIONEUROPEANPROJECTIONISSUE DATE IEC JEDEC JEITAmm inches 2.650.30.12.452.250.490.360.320.2310.510.17.67.41.2710.6510.001.11.00.90.48oo0.250.1DIMENSIONS (inch dimensions are derived from the original mm dimensions)Note1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4SOT162-1816w Mb pDdetail X Ze91y0.25075E03 MS-013pin 1 index0.10.0120.0040.0960.0890.0190.0140.0130.0090.410.400.300.290.051.40.0550.4190.3940.0430.0390.0350.0160.010.250.010.0040.0430.0160.01XθAA1A2H EL pQEcLv M A(A )3A0510 mmscaleSO16: plastic small outline package; 16 leads; body width 7.5 mm SOT162-199-12-2703-02-19Fig 19.Package outline SOT162-1 (SO16)Fig 20.Package outline SOT403-1 (TSSOP16)UNIT A 1A 2A 3b p c D (1)E (2)(1)e H E L L p Q Z y w v θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTIONISSUE DATE IECJEDEC JEITAmm0.150.050.950.800.300.190.20.15.14.94.54.30.656.66.20.40.30.400.0680oo 0.130.10.21DIMENSIONS (mm are the original dimensions)Notes1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.0.750.50SOT403-1MO-15399-12-2703-02-18w Mb pD Ze0.2518169θAA 1A 2L p Qdetail XL(A )3H EE cv M AXAy0 2.5 5 mmscaleTSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1Amax.1.1pin 1 indexFig 21.Package outline SOT266-1 (SSOP20)UNIT A 1A 2A 3b p c D (1)E (1)(1)e H E L L p Q Z y w v θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTIONISSUE DATE IECJEDEC JEITAmm0.1501.41.20.320.200.200.136.66.44.54.30.6510.26.66.20.650.450.480.18100oo 0.130.1DIMENSIONS (mm are the original dimensions)Note1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.0.750.45SOT266-1MO-15299-12-2703-02-19w MθAA 1A 2b pD H EL p Qdetail XE ZecLv M AX(A )3Ay0.251102011pin 1 index0 2.5 5 mmscaleSSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1Amax.1.515.Handling informationInputs and outputs are protected against electrostatic discharge in normal handling.However,to be completely safe you must take normal precautions appropriate to handlingintegrated circuits.16.Soldering16.1IntroductionThere is no soldering method that is ideal for all surface mount IC packages. Wavesoldering can still be used for certain surface mount ICs,but it is not suitable forfine pitchSMDs. In these situations reflow soldering is recommended.16.2Through-hole mount packages16.2.1Soldering by dipping or by solder waveTypical dwell time of the leads in the wave ranges from3seconds to4seconds at250°Cor 265°C, depending on solder material applied, SnPb or Pb-free respectively.The total contact time of successive solder waves must not exceed 5seconds.The device may be mounted up to the seating plane, but the temperature of the plasticbody must not exceed the specified maximum storage temperature (T stg(max)). If theprinted-circuit board has been pre-heated, forced cooling may be necessary immediatelyafter soldering to keep the temperature within the permissible limit.16.2.2Manual solderingApply the soldering iron (24V or less) to the lead(s) of the package, either below theseating plane or not more than2mm above it.If the temperature of the soldering iron bit isless than 300°C it may remain in contact for up to 10seconds. If the bit temperature isbetween 300°C and400°C, contact may be up to 5seconds.16.3Surface mount packages16.3.1Reflow solderingKey characteristics in reflow soldering are:•Lead-free versus SnPb soldering;note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure22) than a PbSn process, thusreducing the process window•Solder paste printing issues including smearing, release, and adjusting the processwindow for a mix of large and small components on one board•Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peaktemperature is high enough for the solder to make reliable solder joints(a solder pastecharacteristic). In addition, the peak temperature must be low enough that thepackages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 9 and 10Moisture sensitivity precautions, as indicated on the packing, must be respected at all times.Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 22.For further information on temperature profiles, refer to Application Note AN10365“Surface mount reflow soldering description”.Table 9.SnPb eutectic process (from J-STD-020C)Package thickness (mm)Package reflow temperature (°C)Volume (mm 3)< 350≥ 350< 2.5235220≥ 2.5220220Table 10.Lead-free process (from J-STD-020C)Package thickness (mm)Package reflow temperature (°C)Volume (mm 3)< 350350 to 2000> 2000< 1.62602602601.6 to 2.5260250245> 2.5250245245MSL: Moisture Sensitivity LevelFig 22.Temperature profiles for large and small components001aac844temperaturetimeminimum peak temperature = minimum soldering temperaturemaximum peak temperature = MSL limit, damage levelpeak temperature。
Bloomfield 8574 模块酿造系统用户手册说明书
Use & CareServicing InstructionsModel 8574 Brewerwith optional8900-Series Glass Decantersp/n 2M-75804 Rev. L M611 140425WARRANTY STATEMENTAll equipment manufactured by Bloomfield is warranted against defectsin materials and workmanship for the time periods listed in the chartEquipmentPartsLabor2M -75804-611 K o f f e e -K i n g 8900 S e r i e s B r e w e rTABLE OF CONTENTSThank You for purchasing thisensure its optimum performance.WARRANTY STATEMENT xi SPECIFICATIONS2M -75804-611 K o f f e e -K i n g 8900 S e r i e s B r e w e rMODELTYPEWARMERS FAUCETVOLTS 1øAMPS WATTS POWER CORDFEATURES AND OPERATING CONTROLS2M -75804-611 K o f f e e -K i n g 8900 S e r i e s B r e w e rPRECAUTIONS AND GENERAL INFORMATIONWARNING: ELECTRIC SHOCK HAZARDAll servicing requiring access to non-insulated components must be performed by qualified service personnel. Do not open any access panels which require the use of tools. Failure to heed this warning can result in electrical shock.WARNING: All installation procedures must be performed by qualified personnel with full knowledge of all applicable electrical and plumbing codes. Failure could result in property damage and personal injury.WARNING: Brewer must be properly grounded to prevent possible shock hazard. DO NOT assume a plumbing line will provide such a ground. Electrical shock will cause death or serious Injury.WARNING: This appliance dispenses very hot liquid. Serious bodily injury from scalding can occur from contact with dispensed liquids.This appliance is intended for commercial use only.This appliance is intended for use to brew beverage products for USA and has American sizes on hardware. All metric conversions are These brewer are listed under UL file E9253, andlisted under LR21315.This brewer meets Standard 4 only when installed,operated and maintained in accordance with the enclosed CAUTION:EQUIPMENT DAMAGEDO NOT plug in or energize this appliance until all Instructions are read and followed. these instructions are not followed.CAUTION:BURN HAZARDExposed surfaces of the appliance, brew chamber and decanter may be HOT to the AGENCY APPROVAL INFORMATIONWARNINGWARNINGWARNINGWARNINGLR21315STD 4E92532M -75804-611 K o f f e e -K i n g 8900 S e r i e s B r e w e rINSTALLATION INSTRUCTIONSREAD THIS CAREFULLY BEFORE STARTING THE INSTALLATIONCAUTION:EQUIPMENT DAMAGEDO NOT plug in or energize this appliance until all Installation Instructions are read and CAUTION:UNSTABLEEQUIPMENT HAZARDIt is very important for safety and for proper operation that the 2M -75804-611 K o f f e e -K i n g 8900 S e r i e s B r e w e rINSTALLATION INSTRUCTIONS (continued)NOTE: This equipment must be installed to comply with WARNING:SHOCK HAZARD Brewer must be properlygrounded to prevent possible shock hazard. DO NOT NSF requires that the brewer be able to be moved for cleaning WARNING2M -75804-611 K o f f e e -K i n g 8900 S e r i e s B r e w e rOPERATION2M -75804-611 K o f f e e -K i n g 8900 S e r i e s B r e w e rOPERATION (continued)WATER HEATERHI-LIMIT2M -75804-611 K o f f e e -K i n g 8900 S e r i e s B r e w e rBREWING COFFEECAUTION:BURN HAZARDExposed surfaces of the brewer, brew chamber and decanter may be HOT to CAUTION:BURN HAZARDTo avoid splashing or overflowing hot liquids,CAUTION:BURN HAZARDAfter a brew cycle, brew chamber contents are HOT. Remove the brew A. PREPARATION2M -75804-611 K o f f e e -K i n g 8900 S e r i e s B r e w e rCLEANING INSTRUCTIONSPROCEDURE: Clean Coffee BrewerCAUTION:BURN HAZARDBrewing and servingtemperatures of coffee are extremely hot.CAUTION:SHOCK HAZARDDo not submerge or immerse brewer in water.2M -75804-611 K o f f e e -K i n g 8900 S e r i e s B r e w e rTROUBLESHOOTING SUGGESTIONSSERVICING INSTRUCTIONS ACCESS PANELSCAUTION:SHOCK HAZARDOpening access panels or removing warmer plates on this brew may expose uninsulated 2M -75804-611 K o f f e e -K i n g 8900 S e r i e s B r e w e rSERVICING INSTRUCTIONS (continued)TEMPERATURE ADJUSTMENTCAUTION:SHOCK HAZARDThese procedures involve 2M -75804-611 K o f f e e -K i n g 8900 S e r i e s B r e w e rSERVICING INSTRUCTIONS (continued)IMPORTANT: Water pressure TIMER ADJUSTMENT2M -75804-611 K o f f e e -K i n g 8900 S e r i e s B r e w e rSERVICING INSTRUCTIONS (continued)REPLACE HEATING ELEMENTIMPORTANT: When replacing heating element, also replace 2M -75804-611 K o f f e e -K i n g 8900 S e r i e s B r e w e rSERVICING INSTRUCTIONS (continued)IMPORTANT: When replacing REPLACE TIMER ASSEMBLY2M -75804-611 K o f f e e -K i n g 8900 S e r i e s B r e w e rCAUTION:CHEMICAL BURNHAZARDDeliming chemicals are caustic. Wear appropriate protective gloves and goggles during this PROCEDURE: Delime the Water TankSERVICING INSTRUCTIONS (continued)Koffee-King™ EXPLODED VIEW & PARTS LIST2M -75804-611 K o f f e e -K i n g 8900 S e r i e s B r e w e rKoffee-King™ EXPLODED VIEW & PARTS LIST (continued)2M -75804-611 K o f f e e -K i n g 8900 S e r i e s B r e w e rKoffee-King™ EXPLODED VIEW & PARTS LIST (continued)2M -75804-611 K o f f e e -K i n g 8900 S e r i e s B r e w e rINTERNAL PLUMBING COMPONENTS2M -75804-611 K o f f e e -K i n g 8900 S e r i e s B r e w e rKoffee-King™ EXPLODED VIEW & PARTS LIST (continued)Koffee-King™ EXPLODED VIEW & PARTS LIST (continued)ELECTRICAL COMPONENTS2M -75804-611 K o f f e e -K i n g 8900 S e r i e s B r e w e rKoffee-King™ WIRING DIAGRAMS2M -75804-611 K o f f e e -K i n g 8900 S e r i e s B r e w e rKoffee-King™ WIRING DIAGRAMS (continued)2M -75804-611 K o f f e e -K i n g 8900 S e r i e s B r e w e rNOTES:2M -75804-611 K o f f e e -K i n g 8900 S e r i e s B r e w e rNOTES:2M -75804-611 K o f f e e -K i n g 8900 S e r i e s B r e w e r。
PCF8574中文手册
PCF8574T I 2C 并行口扩展电路1. 特性操作电压2.5~6.0V低备用电流（≤10μA ） I 2C 并行口扩展电路 开漏中断输出I 2C 总线 实现8位远程I/O 口 与大多数MCU 兼容口输出锁存，具有大电流驱动能力，可直接驱动LED通过3个硬件地址引脚可寻址8个器件（PCF8574A 可多达16个）DIP16，SO16或SSOP20形式封装2. 概述PCF8574是CMOS 电路。
它通过两条双向总线（I 2C ）可使大多数MCU 实现远程I/O 口扩展。
该 器件包含一个8位准双向口和一个I 2C 总线接口。
PCF8574电流消耗很低，且口输出锁存具有大电流驱动能力，可直接驱动LED 。
它还带有一条中断接线（INT ）可与MCU 的中断逻辑相连。
通过INT 发送中断信号，远端I/O 口不必经过I 2C 总线通信就可通知MCU 是否有数据从端口输入。
这意味着PCF8574可以作为一个单被控器。
PCF8574 和PCF8574A 的唯一区别仅在于器件地址不相同。
3. 订单信息封装型号 名称 描述PCF8574TPCF8574ATSO16塑料小型表面封装4. 功能框图P7P6P5P4P3P2P1P0V DD V SSSDASCL A2A1A0INT管脚配置(SO16)12345678161514131211109INT A0A1A2P0P1P2P3SDA V SSSCL P7P6P5P4V DD PCF8574PCF8574A6. I 2C 总线特性I 2C 总线用于不同的IC 或模块之间的双线通信。
两条线其中之一为串行数据线（SDA ），另一条为串行时钟线（SCL ）。
当与器件的输出级相连时，这两条线都必须接上拉电阻。
数据的传送只有在总线空闲时才能进行。
位传送 在每个时钟脉冲出现时，总线传送一个数据位。
在时钟信号高电平期间，SDA 线上的数据位应保持稳定，如果此时改变SDA 线数据则被认为是总线的控制信号（见图1）。
PCF8574指南
distinguished by the value of the DIR bit. This must also be given the correct value in the USER module.Then the status register of PCF8584 must be read to check if theI2C bus is free. First the status register must be addressed by giving ES0-ES2 of the control register the correct value (lines 47-48). Then the Bus Busy bit is tested until the bus is free (lines 49-50). If this is the case, the slave address is sent to data register S0 and theI2C_END bit is cleared (lines 51-53). The slave address is set by the user program in variable USER. The LSB of the slave address is the R/W bit. I2C_END can be tested by the user program whether anI2C reception/transmission is in progress or not.Next the START condition will be generated and interrupt generation enabled by setting the appropriate bits in control register S1 (lines 54-55).Now the routine will return back to the user program and other tasks may be performed. When the START condition, slave address and R/W bit are sent, and the ACK is received, the PCF8584 will generate an interrupt. The interrupt routine will determine if more bytes have to be received or transmitted.Routine Stop (Lines 59-62) —Calling this routine, a STOP condition will be sent to the I2C bus. This is done by sending the correct value to control register S1 (lines 59-61). After this the I2C_END bit is set, to indicate to the user program that a complete I2C sequence has been received or transmitted.Routine I2C_Init (Lines 65-76)—This routine initializes the PCF8584. This must be done directly after reset. Lines 67-70 write data to ’own address’ register S0’. First the correct address of S0’ is set in control register S1 (lines 67-68), then the correct value is written to it (lines 69-70). The value for S0’ is in variable SLAVE_ADR and set by the user program. As noted previously, register S0’ must always be the first register to be accessed after reset, because the PCF8584 now determines whether an 80Cxxx or 68xxx microcontroller is connected. Lines72-76 set the clock register S2. The variable I2C_CLOCK is also set by the user program.Module INTERRThis module contains the I2C interrupt routine. This routine is called every time a byte is received or transmitted on the I2C bus. In lines 12-15 RAM space for variables is reserved.BASE is the start address in the internal 80C51 RAM where the data is stored that is received, or where the data is stored that has to be transmitted.NR_BYTES, IIC_CNT and SLAVE were explained earlier. I2C_END and DIR are flags that are used in the program. I2C_END indicates whether an I2C transmission or reception is in progress. DIR indicates whether the PCF8584 has to receive or transmit bytes. The interrupt routine makes use of register bank 1.The transmission part of the routine starts at line 42. In lines 42-43, a check is made whether IIC_CNT = NR_BYTES. If true, all bytes are sent and a STOP condition may be generated (lines 44-45). Next the pointer for the internal RAM is restored (line 46) and the byte to be transmitted is fetched from the internal RAM (line 47). Then this byte is sent to the PCF8584 and the variables are updated (lines 47-49). The interrupt routine is left and the user program may proceed. The receive part starts from line 55. First a check is made if the next byte to be received is the last byte (lines 56-59). If true the ACK must be disabled when the last byte is received. This is accomplished by resetting the ACK bit in the control register S1 (lines 60-61).Next the received byte may be read (line 62) from data register S0. The byte will be temporary stored in R4 (line 63). Then a check is made if this interrupt was the first after a START condition. If so, the byte read has no meaning and the interrupt routine will be left (lines 68-70). However by reading the data register S0 the next read cycle is started.If valid data is received, it will be stored in the internal RAM addressed by the value of BASE (lines 71-73). Finally a check is made if all bytes are received. If true, a STOP condition will be sent (lines 75-78).EXAMPLESIn the listing section (starting on page 10), some examples are shown that make use of the routines described before. The examples are transmission of a sequence, reception of I2C data and an example that combines both.The first example sends bytes to the PCD8577 LCD driver on the OM1016 demonstration board. Lines 7 to 10 define the interface with the other modules and should be included in every user program. Lines 14 to 16 define the segments in the user module. It is completely up to the user how to organize this.Lines 24 and 28 are the reset and interrupt vectors. The actual user program starts at line 33. Here three variables are defined that are used in the I2C driver routines. Note that PCF8584 must be an even address, otherwise the wrong internal registers will be accessed! Lines 37-42 initialize the interrupt logic of the microcontroller. Next the PCF8584 will be initialized (line 45).The PCF8584 is now ready to transmit data. A table is made in the routine at line 61. For the PCD8577, the data is a control byte and the segment data. Note that the table does not contain the slave address of the LCD driver. In lines 51-54, variables are made ready to start the transmission. This consists of defining the direction of the transmission (DIR), the address where the data table starts (BASE), the number of bytes to transmit (NR_BYTES, without slave address!) and the slave address (SLAVE) of the I2C peripheral that has to be accessed.In line 55 the transmission is started. Once the I2C transmission is started, the user program can do other tasks because the transmission works on interrupts. In this example a loop is performed (line 58). The user can check the end of the transmission during the other tasks, by testing the I2C_END bit regularly.The second example program receives 2 bytes from the PCF8574P I/O expander on the OM1016 demonstration board. Until line 45 the program is identical to the transmit routine because it consists of initialization and variable definition. From line 48, the variables are set for I2C reception. The received bytes are stored in RAM area from label TABLE. During reception, the user program can do other tasks. By testing the I2C_END bit the user can determine when to start processing the data in the TABLE.The third example program displays time from the PCF8583Pclock/calendar/RAM on the LCD display driven by the PCD8577. The LED display (driven by SAA1064) shows the value of the analog inputs of the A/D converter PCF8591. The four analog inputs are scanned consecutively.In this example, both transmit and receive sequences are implemented as shown in the previous examples. The main clock part is from lines 62-128. This contains the calls to the I2C routines. From lines 135-160, routines are shown that prepare the data to be transmitted. Lines 171 to 232 are the main program for the AD converter and LED display. Lines 239 to 340 contain routines used by the main program. This demo program can also be used with the I2C peripherals on the OM1016 demonstration board.ASM51 TSW ASSEMBLER Routines for PCF8584 LOC OBJ LINE SOURCE1 $TITLE (Routines for PCF8584)2 $PAGELENGTH(40)3 ;Program written for PCF8584 as master4 ;5 PUBLIC READBYTE,READCONTR,SENDBYTEPUBLIC SENDCONTR,START,STOP6 PUBLIC I2C_INIT7 EXTRN BIT(I2C_END,DIR)8 EXTRN DATA(SLAVE,IIC_CNT,NR_BYTES)9 EXTRN NUMBER(SLAVE_ADR,I2C_CLOCK,PCF8584)10 ;11 ;Define code segment12 ROUTINE SEGMENT CODE–––– 13 RSEG ROUTINE14 ;15 ;SENDBYTE sends a byte to PCF8584 with A0=016 ;Byte to be send must be in accu0000: R 17 SENDBYTE:0000: 900000 R 18 MOV DPTR,#PCF8584 ;Register address0003: F0 19 SEND: MOVX @DPTR,A ;Send byte0004: 22 20 RET21 ;22 ;SENDCONTR sends a byte to PCF8584 with A0=123 ;Byte to be send must be in accu0005: 24 SENDCONTR:0005: 900001 R 25 MOV DPTR,#PCF8584+01H ;Register address 0008: 80F9 26 JMP SEND27 ;28 ;READBYTE reads a byte from PCF8584 with A0=029 ;Received byte is stored in accu000A: 30 READBYTE:000A: 900000 R 31 MOV DPTR,#PCF8584 ;Register address000D: E0 32 REC: MOVX A,@DPTR ;Receive byte000E: 22 33 RET34 ;35 ;READCONTR reads a byte from PCF8584 with A0=136 ;Received byte is stored in accu000F: 37 READCONTR:000F: 900001 R 38 MOV DPTR,#PCF8584+01H ;Register address 0012: 80F9 39 JMP REC40 ;41 ;START tests if the I2C bus is ready. If ready a42 ;START–condition will be sent, interrupt generation43 ;and acknowledge will be enabled.0014: 750000 R 44 START: MOV IIC_CNT,#00 ;Clear I2C byte counter 0017: 200002 R 45 JB DIR,PROCEED ;If DIR is ’receive’ then 001A: 0500 R 46 INC NR_BYTES ;increment NR_BYTES001C: 7440 47 PROCEED:MOV A,#40H ; Read STATUS register of; 8584001E: 120005 R 48 CALL SENDCONTR0021: 12000F R 49 TESTBB: CALL READCONTR0024: 30E0FA 50 JNB ACC.0,TESTBB; Test BB/ bit0027: E500 R 51 MOV A,SLAVE0029: C200 R 52 CLR I2C_END ;Reset I2C ready bit002B: 120000 R 53 CALL SENDBYTE ;Send slave address002E: 744D 54 MOV A,#01001101B;Generate START, set ENI,;set ACK0030: 120005 R 55 CALL SENDCONTR0033: 22 56 RET57 ;58 ;STOP will generate a STOP condition and set the;I2C_END bit0034: 74C3 59 STOP: MOV A,#11000011B0036: 120005 R 60 CALL SENDCONTR ;Send STOP condition 0039: D200 R 61 SETB I2C_END ;Set I2C_END bit003B: 22 62 RET63 ;64 ;I2C_init does the initialization of the PCF8584 003C: 65 I2C_INIT:66 ;Write own slave address003C: E4 67 CLR A003D: 120005 R 68 CALL SENDCONTR ;Write to control register 0040: 7400 R 69 MOV A,#SLAVE_ADR0042: 120000 R 70 CALL SENDBYTE ;Write to own slave;register71 ;Write clock register0045: 7420 72 MOV A,#20H0047: 120005 R 73 CALL SENDCONTR ;Write to control register 004A: 7400 R 74 MOV A,#I2C_CLOCK004C: 120000 R 75 CALL SENDBYTE ;Write to clock register 004F: 22 76 RET77 ;0050: 78 ENDASM51 TSW ASSEMBLER I2C INTERRUPT ROUTINELOC OBJ LINE SOURCE1 $TITLE (I2C INTERRUPT ROUTINE)2 $PAGELENGTH(40)3 ;4 PUBLIC INT0_SRV5 PUBLIC DIR,I2C_END6 PUBLIC BASE,NR_BYTES,IIC_CNT,SLAVE7 EXTRN CODE(SENDBYTE,SENDCONTR,STOP)EXTRN CODE(READBYTE,READCONTR)8 ;9 ;Define variables in RAM10 IIC_VAR SEGMENT DATA–––– 11 RSEG IIC_VAR0000: R 12 BASE: DS 1 ;Pointer to I2C table (till ;256)0001: 13 NR_BYTES: DS 1 ;Number of bytes to rcv/trm 0002: 14 IIC_CNT:DS 1 ;I2C byte counter0003: 15 SLAVE: DS 1 ;Slave address after START16 ;17 ;Define variable segment18 BIT_VAR SEGMENT DATA BITADDRESSABLE–––– 19 RSEG BIT_VAR0000: R 20 STATUS: DS 1 ;Byte with flags0000 R 21 I2C_END BIT STATUS.0 ;Defines if a I2C;transmission is finished22 ;’1’ is finished23 ;’0’ is not ready0000 R 24 DIR BIT STATUS.3 ;Defines direction of I2C;transmission25 ;’1’:Transmit ’0’:Receive26 ;27 ;Define code segment for routine28 IIC_INT SEGMENT CODE PAGE–––– 29 RSEG IIC_INT30 ;31 ;Program uses registers in RB132 USING 133 ;0000: R 34 INT0_SRV:0000: C0E0 35 PUSH ACC ;Save acc. en psw on stack 0002: C0D0 36 PUSH PSW0004: 75D008 37 MOV PSW,#08H ;Select register bank 1 0007: 300016 R 38 JNB DIR,RECEIVE ;Test direction bit39 ;8584 is MST/TRM4041 ;Program part to transmit bytes to IIC bus000A: E502 R 42 MOV A,IIC_CNT ;Compare IIC_CNT and;NR_BYTES000C: B50105 R 43 CJNE A,NR_BYTES,PROCEED000F: 120000 R 44 CALL STOP ;All bytes transmitted 0012: 8032 45 JMP EXIT0014: A800 R 46 PROCEED:MOV R0,BASE ;RAM pointer0016: E6 47 MOV A,@R0 ;Source is internal RAM 0017: 0500 R 48 INC BASE ;Update pointer of table 0019: 120000 R 49 CALL SENDBYTE ;Send byte to IIC bus001C: 0502 R 50 INC IIC_CNT ;Update byte counter001E: 8026 51 JMP EXIT52 ;53 ;54 ;Program to receive byte from IIC bus0020: 55 RECEIVE:0020: E502 R 56 MOV A,IIC_CNT ;Test if last byte is to be ;received0022: 04 57 INC A0023: 04 58 INC A0024: B50105 R 59 CJNE A,NR_BYTES,PROC_RD0027: 7448 60 MOV A,#01001000B;Last byte to be received.;Disable ACK0029: 120000 R 61 CALL SENDCONTR ;Write control word to;PCF8584002C: 120000 R 62 PROC_RD:CALL READBYTE ;Read I2C byte002F: FC 63 MOV R4,A ;Save accu64 ;If RECEIVE is entered after the transmission of65 ;START+address then the result of READBYTE is not66 ;relevant. READBYTE is used to start the generation ;of the clock pulses for the next byte to read.67 ;This situation occurs when IIC_CNT is 00030: E4 68 CLR A ;Test IIC_CNT0031: B50202 R 69 CJNE A,IIC_CNT,SAVE0034: 8006 70 JMP END_TEST ;START is send. No relevant ;data in data reg. of 8584 0036: A800 R 71 SAVE: MOV R0,BASE0038: EC 72 MOV A,R4 ;Destination is internal RAM 0039: F6 73 MOV @R0,A003A: 0500 R 74 INC BASE003C: 0502 R 75 END_TEST:INC IIC_CNT ;Test if all bytes are;received003E: E501 R 76 MOV A,NR_BYTES0040: B50203 R 77 CJNE A,IIC_CNT,EXIT0043: 120000 R 78 CALL STOP ;All bytes received79 ;0046: D0D0 80 EXIT: POP PSW ;Restore PSW and accu0048: D0E0 81 POP ACC004A: 32 82 RETI83 ;004B: 84 ENDASM51 TSW ASSEMBLER Send a string of bytes to the PCD8577 on OM1016 LOC OBJ LINE SOURCE1 $TITLE (Send a string of bytes to the PCD8577 onOM1016)2 $PAGELENGTH(40)3 ;4 ;This program is an example to transmit bytes via;PCF85845 ;to the I2C–bus6 ;7 PUBLIC SLAVE_ADR,I2C_CLOCK,PCF85848 EXTRN CODE(I2C_INIT,INT0_SRV,START)9 EXTRN BIT(I2C_END,DIR)10 EXTRN DATA(BASE,NR_BYTES,IIC_CNT,SLAVE)11 ;12 ;13 ;Define used segments14 USER SEGMENT CODE ;Segment for user program15 RAMTAB SEGMENT DATA ;Segment for table in;internal RAM16 RAMVAR SEGMENT DATA ;Segment for RAM variables ;in RAM17 ;18 ;–––– 19 RSEG RAMVAR0000: R 20 STACK: DS 20 ;Reserve stack area21 ;22 ;–––– 23 CSEG AT 00H0000: 020000 R 24 JMP MAIN ;Reset vector25 ;26 ;–––– 27 CSEG AT 03H0003: 020000 R 28 JMP INT0_SRV ;I2C interrupt vector;(INT0/)29 ;30 ;–––– 31 RSEG USER32 ;Define I2C clock, own slave address and PCF8584;hardware address0055 33 SLAVE_ADR EQU 55H ;Own slave address is 55H 001C 34 I2C_CLOCK EQU 00011100B ;12.00MHz/90kHz0000 35 PCF8584 EQU 0000H ;PCF8584 address with A0=0 36 ;0000: 7581FF R 37 MAIN: MOV SP,#STACK–1 ;Initialize stack pointer38 ;Initialize 8031 interrupt registers for I2C;interrupt0003: D2A8 39 SETB EX0 ;Enable interrupt INT0/ 0005: D2AF 40 SETB EA ;Set global enable0007: D2B8 41 SETB PX0 ;Priority level ’1’0009: D288 42 SETB IT0 ;INT0/ on falling edge43 ;44 ;Initialize PCF8584000B: 120000 R 45 CALL I2C_INIT46 ;47 ;Make a table in RAM with data to be transmitted. 000E: 120021 R 48 CALL MAKE_TAB49 ;50 ;Set variables to control PCF85840011: D200 R 51 SETB DIR ;DIR=’transmission’0013: 750000 R 52 MOV BASE,#TABLE ;Start address of I2C–data 0016: 750005 R 53 MOV NR_BYTES,#05H ;5 bytes must be;transferred0019: 750074 R 54 MOV SLAVE,#01110100B ;Slave address PCD8577 ; + WR/001C: 120000 R 55 CALL START ;Start I2C transmission56 ;57 ;001F: 80FE 58 LOOP: JMP LOOP ;Endless loop when program ;is finished59 ;60 ;0021: 61 MAKE_TAB:0021: 7800 R 62 MOV R0,#TABLE ;Make data ready for I2C;transmission0023: 7600 63 MOV @R0,#00 ;Controlword PCD8577 0025: 08 64 INC R00026: 76FC 65 MOV @R0,#0FCH ;’0’0028: 08 66 INC R00029: 7660 67 MOV @R0,#60H ;’1’002B: 08 68 INC R0002C: 76DA 69 MOV @R0,#0DAH ;’2’002E: 08 70 INC R0002F: 76F2 71 MOV @R0,#0F2H ;’3’0031: 22 72 RET73 ;74 ;–––– 75 RSEG RAMTAB0000: R 76 TABLE: DS 10 ;Reserve space in internal ;data RAM77 ;for I2C data to transmit78 ;79 ;000A: 80 ENDASM51 TSW ASSEMBLER Receive 2 bytes from the PCF8574P on OM1016LOC OBJ LINE SOURCE1 $TITLE (Receive2 bytes from the PCF8574P on OM1016)2 $PAGELENGTH(40)3 ;4 ;This program is an example to receive bytes via;PCF85845 ;from the I2C–bus6 ;7 PUBLIC SLAVE_ADR,I2C_CLOCK,PCF85848 EXTRN CODE(I2C_INIT,INT0_SRV,START)9 EXTRN BIT(I2C_END,DIR)10 EXTRN DATA(BASE,NR_BYTES,IIC_CNT,SLAVE)11 ;12 ;13 ;Define used segments14 USER SEGMENT CODE ;Segment for user program15 RAMTAB SEGMENT DATA ;Segment for table in;internal RAM16 RAMVAR SEGMENT DATA ;Segment for RAM variables;in RAM17 ;18 ;–––– 19 RSEG RAMVAR0000: R 20 STACK: DS 20 ;Reserve stack area21 ;22 ;–––– 23 CSEG AT 00H0000: 020000 R 24 JMP MAIN ;Reset vector25 ;26 ;–––– 27 CSEG AT 03H0003: 020000 R 28 JMP INT0_SRV ;I2C interrupt vector;(INT0/)29 ;30 ;–––– 31 RSEG USER32 ;Define I2C clock, own slave address and PCF8584;hardware address0055 33 SLAVE_ADR EQU 55H ;Own slave address is 55H 001C 34 I2C_CLOCK EQU 00011100B ;12.00MHz/90kHz0000 35 PCF8584 EQU 0000H ;PCF8584 address with A0=0 36 ;0000: 7581FF R 37 MAIN: MOV SP,#STACK–1 ;Initialize stack pointer38 ;Initialize 8031 interrupt registers for I2C;interrupt0003: D2A8 39 SETB EX0 ;Enable interrupt INT0/ 0005: D2AF 40 SETB EA ;Set global enable0007: D2B8 41 SETB PX0 ;Priority level ’1’0009: D288 42 SETB IT0 ;INT0/ on falling edge43 ;44 ;Initialize PCF8584000B: 120000 R 45 CALL I2C_INIT46 ;47 ;Set variables to control PCF8584000E: C200 R 48 CLR DIR ;DIR=’receive’0010: 750000 R 49 MOV BASE,#TABLE ;Start address of I2C–data 0013: 750002 R 50 MOV NR_BYTES,#02H ;2 bytes must be received 0016: 75004F R 51 MOV SLAVE,#01001111B ;Slave address PCF8574 ; + RD0019: 120000 R 52 CALL START ;Start I2C transmission53 ;54 ;001C: 80FE 55 LOOP: JMP LOOP ;Endless loop when program;is finished56 ;57 ;–––– 58 RSEG RAMTAB0000: R 59 TABLE: DS 10 ;Reserve space in internal ;data RAM60 ;for received I2C data61 ;62 ;000A: 63 ENDASM51 TSW ASSEMBLER Demo program for PCF8584 I2C–routines LOC OBJ LINE SOURCE1 $TITLE (Demo program for PCF8584 I2C–routines)2 $PAGELENGTH(40)3 ;Program displays on the LCD display the time (with ;PCF8583). Dots on LCD display blink every second.5 ;On the LED display the values of the successive;analog input channels are shown.7 ;Program reads analog channels of PCF8591P.8 ;Channel number and channel value are displayed;successively.9 ;Values are displayed on LCD and LED display on I2C ;demo board.10 ;11 PUBLIC SLAVE_ADR,I2C_CLOCK,PCF858412 EXTRN CODE(I2C_INIT,INT0_SRV,START)13 EXTRN BIT(I2C_END,DIR)14 EXTRN DATA(BASE,NR_BYTES,IIC_CNT,SLAVE)15 ;16 ;17 ;Define used segments18 USER SEGMENT CODE ;Segment for user program19 RAMTAB SEGMENT DATA ;Segment for table in;internal RAM20 RAMVAR SEGMENT DATA ;Segment for variables21 ;–––– 22 RSEG RAMVAR0000: R 23 STACK: DS 20 ;Stack area (20 bytes) 0014: 24 PREVIOUS: DS 1 ;Store for previous seconds 0015: 25 CHANNEL:DS 1 ;Channel number to be;sampled0016: 26 AN_VAL: DS 1 ;Analog value sampled;channel0017: 27 CONVAL: DS 3 ;Converted BCD value sampled ;channel28 ;–––– 29 CSEG AT 00H0000: 020000 R 30 LJMP MAIN ;Reset vector31 ;–––– 32 CSEG AT 03H ;INT0/0003: 020000 R 33 LJMP INT0_SRV ;Vector I2C–interrupt34 ;35 ;–––– 36 RSEG USER37 ;Define I2C clock, own slave address and address for ;main processor0055 38 SLAVE_ADR EQU 55H ;Own slaveaddress is 55h 001C 39 I2C_CLOCK EQU 00011100B ;12.00MHz/90kHz0000 40 PCF8584 EQU 0000H ;Address of PCF8584. This;must be an EVEN number!!41 ;Define addresses of I2C peripherals00A3 42 PCF8583R EQU 10100011B ;Address PCF8583 with Read;active00A2 43 PCF8583W EQU 10100010B ;Address PCF8583 with Write ;active009F 44 PCF8591R EQU 10011111B ;Address PCF8591 with Read;active009E 45 PCF8591W EQU 10011110B ;Address PCF8591 with Write ;active0074 46 PCD8577W EQU 01110100B ;Address PCD8577 with Write ;active0076 47 SAA1064W EQU 01110110B ;Address SAA1064 with Write ;active48 ;0000: 7581FF R 49 MAIN: MOV SP,#STACK–1 ;Define stack pointerASM51 TSW ASSEMBLER Demo program for PCF8584 I2C–routinesLOC OBJ LINE SOURCE50 ;Initialize 80C31 interrupt registers for I2C;interrupt (INT0/)0003: D2A8 51 SETB EX0 ;Enable interrupt INT0/ 0005: D2AF 52 SETB EA ;Set global enable0007: D2B8 53 SETB PX0 ;Priority level is ’1’ 0009: D288 54 SETB IT0 ;INT0/ on falling edge55 ;Initialize PCF8584000B: 120000 R 56 CALL I2C_INIT57 ;000E: 751500 R 58 MOV CHANNEL,#00 ;Set AD–channel59 ;60 ;Time must be read from PCF8583.61 ;First write word address and control register of;PCF8583.0011: D200 R 62 SETB DIR ;DIR=’transmission’0013: 750000 R 63 MOV BASE,#TABLE ;Start address I2C data 0016: 750002 R 64 MOV NR_BYTES,#02H ;Send 2 bytes0019: 7500A2 R 65 MOV SLAVE,#PCF8583W001C: E4 66 CLR A001D: F500 R 67 MOV TABLE,A ;Data to be sent (word;address).001F: F501 R 68 MOV TABLE+1,A ; ” (control;byte)0021: 120000 R 69 CALL START ;Start transmission.0024: 3000FD R 70 FIN_1: JNB I2C_END,FIN_1 ;Wait till transmission;finished71 ;Send word address before reading time0027: D200 R 72 REPEAT: SETB DIR ;’transmission0029: 750000 R 73 MOV BASE,#TABLE ;I2C data002C: 7500A2 R 74 MOV SLAVE,#PCF8583W002F: 7401 75 MOV A,#010031: F500 R 76 MOV NR_BYTES,A ;Send 1 byte0033: F500 R 77 MOV TABLE,A ;Data to be sent is ’1’ 0035: 120000 R 78 CALL START ;Start I2C transmission 0038: 3000FD R 79 FIN_2: JNB I2C_END,FIN_2 ;Wait till transmission;finished80 ;81 ;Time can now be read from PCF8583. Data read is82 ;hundredths of sec’s, sec’s, min’s and hr’s003B: C200 R 83 CLR DIR ;DIR=’receive’003D: 750000 R 84 MOV BASE,#TABLE ;I2C table0040: 750004 R 85 MOV NR_BYTES,#04; 4 bytes to receive0043: 7500A3 R 86 MOV SLAVE,#PCF8583R0046: 120000 R 87 CALL START ;Start I2C reception0049: 3000FD R 88 FIN_3: JNB I2C_END,FIN_3 ;Wait till finished89 ;90 ;Transfer data to R2...R5004C: 7800 R 91 MOV R0,#TABLE ;Set pointers004E: 7902 92 MOV R1,#02H ;Pointer R20050: E6 93 TRANSFER:MOV A,@R00051: F7 94 MOV @R1,A0052: 08 95 INC R00053: 09 96 INC R10054: D500F9 R 97 DJNZ NR_BYTES,TRANSFER0057: ED 98 MOV A,R5 ;Mask of hour counter0058: 543F 99 ANL A,#3FH005A: FD 100 MOV R5,A101 ;102 ;Data must now be displayed on LCD display.103 ;First minutes and hours (in R4 and R5) must be104 ;converted from BCD to LCD segment data.The segment;data105 ;will be transferred to TABLE. R0 is pointer to tableASM51 TSW ASSEMBLER Demo program for PCF8584 I2C–routinesLOC OBJ LINE SOURCE005B: 7800 R 106 MOV R0,#TABLE005D: 7600 107 MOV @R0,#00H ;Control word for PCD8577005F: 08 108 INC R0 0060: 120080 R 109 CALL CONV110 ;111 ;Switch on dp between hours and minutes0063: 430301 R 112 ORL TABLE+3,#01H113 ;If lsb of seconds is ’0’ then switch on dp.0066: EB 114 MOV A,R3 ;Get seconds0067: 13 115 RRC A ;lsb in carry0068: 4003 116 JC PROCEED006A: 430101 R 117 ORL TABLE+1,#01H;switch on dp118 ;119 ;Now the time (hours,minutes) can be displayed on;the LCD006D: 120 PROCEED:006D: D200 R 121 SETB DIR ;Direction ’transmit’006F: 750000 R 122 MOV BASE,#TABLE0072: 750005 R 123 MOV NR_BYTES,#05H0075: 750074 R 124 MOV SLAVE,#PCD8577W0078: 120000 R 125 CALL START ;Start transmission126 ;007B: 3000FD R 127 FIN_4: JNB I2C_END,FIN_4007E: 8026 128 JMP ADCON ;Proceed with AD–conversion;part129 ;130 ;***************************************************************** 131 ;Routines used by clock part of demo132 ;133 ;CONV converts hour and minute data to LCD data and stores134 ;it in TABLE.0080: 90009C R 135 CONV: MOV DPTR,#LCD_TAB ;Base for LCD segment table0083: ED 136 MOV A,R5 ;Hours to accu0084: C4 137 SWAP A ;Swap nibbles0085: 120096 R 138 CALL LCD_DATA ;Convert 10’s hours to LCD;data in table0088: ED 139 MOV A,R5 ;Get hours0089: 120096 R 140 CALL LCD_DATA008C: EC 141 MOV A,R4 ;Get minutes008D: C4 142 SWAP A008E: 120096 R 143 CALL LCD_DATA ;Convert 10’s minutes0091: EC 144 MOV A,R40092: 120096 R 145 CALL LCD_DATA ;Convert minutes0095: 22 146 RET147 ;148 ;LCD_DATA gets data from segment table and stores it in TABLE 0096: 540F 149 LCD_DATA:ANL A,#0FH ;Mask off LS–nibble0098: 93 150 MOVC A,@A+DPTR ;Get LCD segment data0099: F6 151 MOV @R0,A ;Save data in table009A: 08 152 INC R0009B: 22 153 RET154 ;155 ;LCD_TAB is conversion table for LCD009C: 156 LCD_TAB:009C: FC60DA 157 DB 0FCH,60H,0DAH; ’0’,’1’,’2’009F: F266B6 158 DB 0F2H,66H,0B6H; ’3’,’4’,’5’00A2: 3EE0FE 159 DB 3EH,0E0H,0FEH; ’6’,’7’,’8’00A5: E6 160 DB 0E6H ; ’9’161 ;ASM51 TSW ASSEMBLER Demo program for PCF8584 I2C–routinesLOC OBJ LINE SOURCE162 ;******************************************************************* 163 ;164 ;165 ;These part of the program reads an analog input–channel.166 ;Displaying is done on the LED–display167 ;On odd–seconds the channel number will be displayed.168 ;On even–seconds the analog value of this channel is displayed169 ;Then the next channel is displayed.170 ;00A6: EB 171 ADCON: MOV A,R3 ;Get seconds00A7: 13 172 RRC A ;lsb to carry00A8: 503C 173 JNC NEW_MEAS ;Even seconds; do a;measurement on the current channel174 ;175 ;Display and/or update channel00AA: 33 176 RLC A ;Restore accu00AB: B51402 R 177 CJNE A,PREVIOUS,NEW_CH ;If new seconds,;update channel number00AE: 800A 178 JMP DISP_CH00B0: 0515 R 179 NEW_CH: INC CHANNEL00B2: E515 R 180 MOV A,CHANNEL ;If channel=4 then;channel:=000B4: B40403 181 CJNE A,#04,DISP_CH00B7: 751500 R 182 MOV CHANNEL,#0000BA: 8B14 R 183 DISP_CH:MOV PREVIOUS,R3 ;Update previous seconds00BC: E515 R 184 MOV A,CHANNEL ;Get segment value of;channel00BE: 900193 R 185 MOV DPTR,#LED_TAB00C1: 93 186 MOVC A,@A+DPTR187 ;00C2: 7800 R 188 MOV R0,#TABLE ;Fill table with I2C data00C4: 7600 189 MOV @R0,#00 ;SAA1064 instruction byte00C6: 08 190 INC R000C7: 7677 191 MOV @R0,#77H ;SAA1064 control byte00C9: 08 192 INC R000CA: F6 193 MOV @R0,A ;Channel number00CB: E4 194 CLR A00CC: 08 195 INC R000CD: F6 196 MOV @R0,A ;Second digit00CE: 08 197 INC R000CF: F6 198 MOV @R0,A ;Third digit00D0: 08 199 INC R000D1: F6 200 MOV @R0,A ;Fourth byte201 ;00D2: D200 R 202 SETB DIR ;I2C transmission of channel;number00D4: 750000 R 203 MOV BASE,#TABLE00D7: 750006 R 204 MOV NR_BYTES,#06H00DA: 750076 R 205 MOV SLAVE,#SAA1064W00DD: 120000 R 206 CALL START207 ;00E0: 3000FD R 208 FIN_5: JNB I2C_END,FIN_500E3: 020027 R 209 JMP REPEAT ; Repeat clock and AD cycle; again210 ;211 ;ASM51 TSW ASSEMBLER Demo program for PCF8584 I2C–routinesLOC OBJ LINE SOURCE212 ;Measure and display the value of an AD–channel00E6: 120108 R 213 NEW_MEAS: CALL AD_VAL ;Do measurement214 ;Wait till values are available00E9: 3000FD R 215 FIN_6: JNB I2C_END,FIN_6216 ;Relevant byte in TABLE+1. Transfer to AN_VAL00EC: 7801 R 217 MOV R0,#TABLE+100EE: 8616 R 218 MOV AN_VAL,@R000F0: E516 R 219 MOV A,AN_VAL ;Channel value in accu for;conversion220 ;AN_VAL is converted to BCD value of the measured;voltage.221 ;Input value for CONVERT in accu222 ;Address for MSByte in R100F2: 7917 R 223 MOV R1,#CONVAL00F4: 120154 R 224 CALL CONVERT225 ;Convert 3 bytes of CONVAL to LED–segments00F7: 900193 R 226 MOV DPTR,#LED_TAB ;Base of segment table00FA: 7817 R 227 MOV R0,#CONVAL00FC: 12018A R 228 CALL SEG_LOOP229 ;Display value of channel to LED display00FF: 12012C R 230 CALL LED_DISP0102: 3000FD R 231 FIN_8: JNB I2C_END,FIN_8 ;Wait till I2C;transmission is ended0105: 020027 R 232 JMP REPEAT ;Repeat clock and AD cycle233 ;234 ;**************************************************************** 235 ;Routines used for AD converter.236 ;237 ;AIN reads an analog values from channel denoted by;CHANNEL.238 ;Send controlbyte:0108: D200 R 239 AD_VAL: SETB DIR ;I2C transmission010A: 7800 R 240 MOV R0,#TABLE ;Define control word010C: A615 R 241 MOV @R0,CHANNEL010E: 750000 R 242 MOV BASE,#TABLE ;Set base at table0111: 750001 R 243 MOV NR_BYTES,#01H ;Number of bytes to be;send0114: 75009E R 244 MOV SLAVE,#PCF8591W ;Slave address PCF85910117: 120000 R 245 CALL START ;Start transmission of;controlword011A: 3000FD R 246 FIN_7: JNB I2C_END,FIN_7 ;Wait until transmission is;finished247 ;Read 2 data bytes from AD–converter248 ;First data byte is from previous conversion and not249 ;relevant011D: C200 R 250 CLR DIR ;I2C reception011F: 750000 R 251 MOV BASE,#TABLE ;Bytes must be stored in;TABLE0122: 750002 R 252 MOV NR_BYTES,#02H; Receive 3 bytes0125: 75009F R 253 MOV SLAVE,#PCF8591R ;Slave address PCF85910128: 120000 R 254 CALL START012B: 22 255 RET256 ;257 ;LED_DISP displays the data of 3 bytes from address;CONVAL012C: 258 LED_DISP:012C: 431780 R 259 ORL CONVAL,#80H ;Set decimal point012F: 7800 R 260 MOV R0,#TABLE0131: 7917 R 261 MOV R1,#CONVAL0133: 7600 262 MOV @R0,#00 ;SAA1064 instruction byte0135: 08 263 INC R0。
ATmega16单片读取PCF8574键盘扩展并串行在12864液晶显示
ATmega16单片机扩展键盘输入口，使用PCF8574芯片，在调试过程中一定要注意读取和写入的寄存器，不管买的是PCF8574A还是PCF8574,都试下0x70、0x71和0x40、0x41，我买的这个是PCF8574,按照厂商给的资料应该是访问0x40、0x41的，但是最后用的时候访问的是0X70和0X71，所以大家注意了，参考的时候，如果读取不对，立马进行更换。
#define F_CPU 1000000UL#include <avr/io.h>#include <util/delay.h>#include <avr/interrupt.h>#define scl PC0#define scl_out DDRC|=_BV(scl)#define scl_in DDRC&=_~BV(scl)#define scl_1 PORTC|=_BV(scl)#define scl_0 PORTC&=~_BV(scl)#define sda PC1#define sda_out DDRC|=_BV(sda)#define sda_in DDRC&=~_BV(sda)#define sda_1 PORTC|=_BV(sda)#define sda_0 PORTC&=~_BV(sda)#define sda_read PINC&_BV(sda)unsigned int key_value=255;const unsigned char tabn[]={"0123456789"};/*串行写液晶12864*//*PB0,PB1,PB2分别对应CS,SID,和SCLK*//*对CS引脚进行定义与设置*/#define cs_out DDRB|=_BV(PB0)#define cs_in DDRB&=~_BV(PB0)#define cs_1 PORTB|=_BV(PB0)#define cs_0 PORTB&=~_BV(PB0)/*对sid引脚进行定义与设置*/#define sid_out DDRB|=_BV(PB1)#define sid_in DDRB&=~_BV(PB1)#define sid_1 PORTB|=_BV(PB1)#define sid_0 PORTB&=~_BV(PB1)#define sid_read PINB&_BV(PB1)/*对使能sclk引脚进行定义与设置*/#define sclk_out DDRB|=_BV(PB2)#define sclk_in DDRB&=~_BV(PB2)#define sclk_1 PORTB|=_BV(PB2)#define sclk_0 PORTB&=~_BV(PB2)/*向液晶写入一个字节的数据*/void write_byte(unsigned char byte){unsigned char i;sid_out; //数据引脚为输出模式for(i=0;i<8;i++){sclk_0;if(byte&0x80) //从高位开始往液晶中写入一个8位数据sid_1;elsesid_0;sclk_1;_delay_us(2); //出现一个下降沿sclk_0;byte=byte<<1;}}/*从12864液晶中读取一个字节的数据*/unsigned char read_byte(){unsigned char i,temp1=0,temp2=0;unsigned char date;sid_in; //数据引脚为输入模式for(i=0;i<8;i++) //从12864中读取高四位数据{sclk_0;sclk_1;_delay_us(2);sclk_0;temp1=temp1<<1;if(sid_read)temp1|=0x01;}for(i=0;i<8;i++) //从12864中读取低四位数据{sclk_0;sclk_1;_delay_us(2);sclk_0;temp2=temp2<<1;if(sid_read)temp2|=0x01;}sid_out; //数据引脚转为输出模式date=(temp1&0xf0)+((temp2&0xf0)>>4);return date;}/*液晶忙检测函数*/void check_busy(){do{write_byte(0xfc);}while(0x80&read_byte());}/*向液晶写命令*/void write_com(unsigned char addr){cs_1; //片选check_busy(); //检验是否忙write_byte(0xf8); //写入写命令_delay_us(1);write_byte(addr&0xf0); //写入命令的高四位_delay_us(1);write_byte((addr&0x0f)<<4); //写入命令的低四位cs_0; //片选关闭}/*向液晶写数据*/void write_date(unsigned char date){cs_1; //片选check_busy(); //检验是否忙write_byte(0xfa); //写入写数据_delay_us(1);write_byte(date&0xf0);//写入数据的高四位_delay_us(1);write_byte((date&0x0f)<<4); //写入数据的低四位cs_0; //片选关闭}/*初始化液晶函数*/void init_lcd(){DDRB|=0x07;PORTB&=0xf8;write_com(0x30);_delay_us(20);write_com(0x0c);_delay_us(10);write_com(0x01);_delay_us(10);write_com(0x06);_delay_us(10);}/*向LCD写入一个字符串*/void write_string(const unsigned char *s){while(*s>0) //写入一串字符{write_date(*s);s++;_delay_us(1);}_delay_ms(1);}/*向LCD某个地址写入一个字符串*/void write_addstr(unsigned char add,const unsigned char *s ) {write_com(add); //找到地址while(*s>0) //写入一串字符{write_date(*s);s++;_delay_us(1);}}/*pcf8674开始信号*/void PCF8574_start(){sda_out;sda_1;scl_1;_delay_us(5);sda_0;_delay_us(5);scl_0;}/*PCF8574停止信号*/void PCF8574_stop(){sda_out;sda_0;scl_1;_delay_us(5);sda_1;_delay_us(5);}/*初始化PCF8574*/void init_8574(){scl_out;sda_out;scl_0;sda_0;}/*PCF8574发送应答信息*/ void send_ack(unsigned char ack) {sda_out;if(ack==1)sda_1;elsesda_0;scl_1;_delay_us(5);scl_0;_delay_us(5);}/*接收应答信息*/unsigned char revieve_ack() {unsigned char i;scl_1;_delay_us(5);sda_in;if(sda_read)i=1;elsei=0;scl_0;_delay_us(5);return i;}/*向PCF8574写一个字节的数据*/void write_iic(unsigned char date){unsigned char i;sda_out;for(i=0x80;i>0;i>>=1){if(i&date)sda_1;elsesda_0;scl_1;_delay_us(5);scl_0;}revieve_ack();}/*接收来自PCF8574中的一个字节数据*/ unsigned char receive_iic(){unsigned char i,date=0;sda_out;sda_1;sda_in;for(i=0x80;i>0;i>>=1){scl_1;if(sda_read)date|=i;scl_0;}return date;}/*向pcf8574输出一个八位数据*/void write_pcf8574(unsigned char reg_add) {PCF8574_start();write_iic(0x70);write_iic(reg_add);PCF8574_stop();}/*读取PCF8574读取八位数据*/unsigned char recieve_pcf8574(){unsigned int temp;PCF8574_start();write_iic(0x71);temp=receive_iic();PCF8574_stop();_delay_ms(10);return temp;}void display_keyscan(unsigned int key){write_com(0x82);write_date(tabn[((key%1000)/100)%10]);write_date(tabn[((key%100)/10)%10]);write_date(tabn[key%10]);}void init_interrupt(){MCUCR=0x02;GICR=0x40;SREG=0x80;}int main(){init_8574(); //初始化键盘扩展8574init_lcd(); //初始化液晶显示_delay_ms(100);write_com(0x01);init_interrupt(); //初始化中断变量，并开启外部中断_delay_ms(100);while(1){display_keyscan(key_value);_delay_ms(50); //延时}}//中断服务程序ISR(INT0_vect){unsigned int key_no;SREG=0x00; //关中断key_no=recieve_pcf8574(); //获取键盘值if(key_no!=255) //如果按下键盘，key_value=key_no; //获得按键值SREG=0x80; //重新开中断}。
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PCF8574T I 2C 并行口扩展电路1. 特性操作电压2.5~6.0V低备用电流（≤10μA ） I 2C 并行口扩展电路 开漏中断输出I 2C 总线 实现8位远程I/O 口 与大多数MCU 兼容口输出锁存，具有大电流驱动能力，可直接驱动LED通过3个硬件地址引脚可寻址8个器件（PCF8574A 可多达16个）DIP16，SO16或SSOP20形式封装2. 概述PCF8574是CMOS 电路。
它通过两条双向总线（I 2C ）可使大多数MCU 实现远程I/O 口扩展。
该 器件包含一个8位准双向口和一个I 2C 总线接口。
PCF8574电流消耗很低，且口输出锁存具有大电流驱动能力，可直接驱动LED 。
它还带有一条中断接线（INT ）可与MCU 的中断逻辑相连。
通过INT 发送中断信号，远端I/O 口不必经过I 2C 总线通信就可通知MCU 是否有数据从端口输入。
这意味着PCF8574可以作为一个单被控器。
PCF8574 和PCF8574A 的唯一区别仅在于器件地址不相同。
3. 订单信息封装型号 名称 描述PCF8574TPCF8574ATSO16塑料小型表面封装4. 功能框图P7P6P5P4P3P2P1P0V DD V SSSDASCL A2A1A0INT管脚配置(SO16)12345678161514131211109INT A0A1A2P0P1P2P3SDA V SSSCL P7P6P5P4V DD PCF8574PCF8574A6. I 2C 总线特性I 2C 总线用于不同的IC 或模块之间的双线通信。
两条线其中之一为串行数据线（SDA ），另一条为串行时钟线（SCL ）。
当与器件的输出级相连时，这两条线都必须接上拉电阻。
数据的传送只有在总线空闲时才能进行。
位传送 在每个时钟脉冲出现时，总线传送一个数据位。
在时钟信号高电平期间，SDA 线上的数据位应保持稳定，如果此时改变SDA 线数据则被认为是总线的控制信号（见图1）。
起始和停止信号当总线空闲时，数据和时钟线保持高电平。
SCL 线为高电平时，SDA 线电平由高至低的变化定义为总线的起始信号（S ）；SCL 线为高电平时，SDA 线电平由低至高的变化定义为总线的停止信号（S ）（见图2）。
系统配置产生信息的器件称为‘发送器’，接收信息的器件称为‘接收器’。
控制信息的器件称为‘主控器’，而由主控器控制的器件称为‘被控器’（见图3）。
data line stable;data validchange of data allowedSDASCL图1 I 2C 总线上的位传送SDASCLPSTOP conditionSDASCLSSTART condition图2 起始信号和停止信号定义SDA SCL图3 系统配置应答在起动和停止信号之间所传送的数据数量不受限制。
每个8位字节之后跟随一个应答位。
应答位的时钟脉冲由主控器产生。
被控接收器在接收到每一个字节数据之后必须发送一个应答信号；而主控器在接收到被控发送器发送的数据后，也必须发送一个应答信号。
在出现与应答位对应的时钟脉冲时，产生应答位的器件将拉低SDA 线，这样在应答位对应的时钟脉冲高电平期间，SDA 保持低电平状态。
建立和保持时间必须纳入考虑。
当主控器作为接收器时，它必须在被控器发送完最后一个字节数据后产生非应答信号，此时发送器必须将数据线释放为高电平，以使主控器能够产生一个停止信号。
START CONDITIONacknowledgementDATA OUTPUT BY TRANSMITTERDATA OUTPUT BY RECEIVERSCL FROM MASTER图4 I 2C 总线上的应答7. 功能描述to interrupt logicV SSP0 to P7V DDwrite pulsedata from shift registerpower-on resetread pulse data toshift register图5 I/O 口的简化结构图寻址PCF8574的每个I/O 口都可单独用作输入或输出。
输入通过读模式将数据传送到MCU （见图8），输出通过写模式将数据发送到端口（见图7）。
S 0100A2A1A00A 10slave addressslave addressAS 011A2A1A0a.b.(a) PCF8574.(b) PCF8574A.图6 PCF8574和PCF8574A 的从地址SDA SCLWRITE TO PORTDATA OUT FROM PORT图7 写模式（输出）READ FROMPORTDATA INTO PORTslave address (PCF8574)data from portdata from portINT图8 读模式（输入）中断（见图9，10）PCF8574提供一个可以连接到MCU 对应输入端的开漏输出口（INT ）。
这样可使PCF8574能够启动系统中另外一处的动作。
在输入模式中，口输入信号的上升或下降沿产生中断。
在时间t iv 之后INT 有效。
当口数据变为初始值或产生中断端口的数据写入/读出时，中断电路复位并重新激活。
在下列条件下发生复位：读模式中，SCL 信号上升沿之后的应答位 写模式中，SCL 信号从高到低的跳变之后的应答位 应答时钟脉冲期间的中断复位可能会导致中断的丢失中断复位后I/O 口的每个变化都会被检测，并在下一个时钟上升沿作为INT 发送。
对另一个器件的读写不影响中断电路。
PCF8574(1)PCF8574(2)V DDINTPCF8574(16)图9 多个PCF8574的中断应用slave address (PCF8574)data from port图10 I/O 口P5的输入变化产生中断准双向I/O口(见图11)准双向I/O口可用作输入和输出而不需要通过控制寄存器定义数据的方向。
上电时I/O口为高电平。
该模式中只有V DD提供的电流有效。
在大负载输出时提供额外的强上拉以使电平迅速上升。
当输出写为高电平时打开强上拉，在SCL的下降沿关闭。
I/O口用作输入之前应当为高电平。
slave address (PCF8574A)data to port data to portSCLP3OUTPUTVOLTAGEP3PULL-UPOUTPUTCURRENT图11 P3从低变为高再变为低时的瞬时上拉电流极限参数标号参数最小值最大值单位V DD电源电压－0.5 +7.0 V V I输入电压V－0.5 V DD +0.5 VSSI I DC输入电流- ±20 mAI O DC输出电流- ±25 mAI DD电源电流- ±100 mAI SS电源电流- ±100 mAP tot总功率损耗- 400mWP O每个输出的功率损耗- 100mWT stg储存温度－60 150℃T amb工作环境温度－40 +85 ℃DC电气特性V DD=2.5~6.0V; V SS=0V; T amb= -40~85℃标号参数条件最小值典型值最大值单位电源V DD电源电压 2.5－ 6.0 VI DD电源电流工作模式; V=6V;－40 100 ∝ADD无负载; V I= V DD或V SSf SCL=100KHzI stb备用电流备用模式; V=6V;－ 2.5 10 ∝ADD无负载; V I= V DD或V SSV POR上电复位电压V=6V;无负载;－ 1.3 2.4 VDDV I= V DD或V SS ; 注1输入SCL；输入/输出SDAV IL低电平输入电压－0.5 －+0.3 V DD VV DD－V DD+0.5 V V IH高电平输入电压 0.7=0.4V 3I OL低电平输出电流V OL－－mAI L漏电流V=V DD或V SS－1 －+1 ∝AIC i输入电容V I=V SS－－7 pFI/O口V IL低电平输入电压－0.5 －+0.3V DD VV DD－V DD+0.5 V V IH高电平输入电压 0.7I IHL通过保护二极管的最V I≥V DD或V I≤V SS－－±400∝A 大允许电流=5V 10 25 －mAI OL低电平输出电流V OL=1V; V DD注1：上电复位电路复位I C总线逻辑，并将所有I/O口都置位为1。
I2C总线时序特性标号参数最小值典型值最大值单位I2C总线时序（见图12；）f SCL SCL时钟频率 － － 100 kHzt SW总线容许的尖峰信号宽度 － － 100 nst BUF总线空闲时间 4.7 － － ∝st SU;STA起始信号的建立时间 4.7 － － ∝st HD;STA起始信号的保持时间 4.0 － － ∝st LOW SCL低电平时间 4.7 － － ∝st HIGH SCL高电平时间 4.0 － － ∝st r SCL和SDA上升时间 － － 1.0 ∝st f SCL和SDA下降时间 － － 0.3 ∝st SU;DA T数据建立时间 250 － － ∝st HD;DA T数据保持时间 0 － － ∝st VD;DA T SCL低电平到数据输出有效 － － 3.4 ∝st SU;STO停止信号建立时间 4.0 － － ∝sPROTOCOL SCLSDABIT 0LSB(R/W)HD;STA SU;DAT HD;DAT VD;DAT SU;STO t t t HIGHSTARTCONDITION(S)BIT 7MSB(A7)BIT 6(A6)ACKNOWLEDGE(A)STOPCONDITION(P)图12 I2C总线时序SO16：塑料小型表面封装；16脚；本体宽7.5mmUNIT A max.A 1A 2A 3b p c D (1)E (1)(1)e H E L L p Q Zy w v θREFERENCESOUTLINE VERSION EUROPEAN PROJECTIONISSUE DATE IEC JEDEC EIAJmm inches 2.650.300.10 2.452.250.490.360.320.2310.510.17.67.4 1.2710.6510.00 1.11.00.90.480oo0.250.1DIMENSIONS (inch dimensions are derived from the original mm dimensions)Note1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.1.10.4 SOT162-10.25 075E03MS-013AA0.100.0120.0040.0960.0890.0190.0140.0130.0090.410.400.300.290.0501.40.0550.4190.3940.0430.0390.0350.0160.010.250.010.0040.0430.0160.010510 mmscale95-01-2497-05-22。