sgmii_specification

使用altera FPGA soft-CDR模式的SGMII接口实现

使用 Altera FPGA Soft-CDR 模式的 SGMII 接口实现
AN-518-2.0 应用笔记
本应用笔记讨论了使用 Stratix® V、Stratix IV、Stratix III，和 Arria® II FPGA 中的 soft- CDR 模式，实现串行千兆位介质无关接口 (SGMII) 的不同方面。 1 本文档中的信息专门适用于 Stratix® V、Stratix IV、Stratix III，和 Arria® II FPGA。所支持的 Altera FPGA 包含了支持差分标准 ( 例如包括 1.25 Gbps 的各种速度的 LVDS) 的专用电路。这些器件的高速 LVDS I/O 支持许多高速网络、通信 I/O 互联标准，以及包括 SGMII 的应用程序。在 LVDS I/O 上支持 SGMII 可以实现高端口数量、低功耗和低成本的多点以太网 (GbE) 系统。您可以利用所支持的 FPGA 的 soft- CDR 模式实现 SGMII 系统。 Altera 通过 soft- CDR 模式和 TSE MegaCore® 中的 Altera® FPGA LVDS 硬宏，提供了完整的 SGMII 解决方案 — 实现了物理编码子层 (PCS) 和介质访问控制器 (MAC) 的功能。本应用笔记包含如下几方面内容：
LINE CARDS
f 要了解关于 SFP 的详细信息，请参阅 Small Form- factor Pluggable (SFP) Transceiver MultiSource Agreement (MSA) 文档。
Soft- CDR 连接钢缆 SFP 收发器
图 3 显示使用一个 Altera FPGA 连接到铜缆 SFP 模块的一个典型的 SGMII 系统连接。

GE电口速率自协商问题(SGMII SERDES)

GE电口速率自协商问题1、问题描述在某上行扣板的调试过程中，发现上行GE电口与其它GE电口设备对接时，速率都为1000M时，电口可以正常link；但是当与速率强制为100/10M设备对接时，电口不能正确协商，端口link不上。

2、原因分析电口使用已比较成熟，与以前使用过的单板设计架构也没有太大差异，但是为何会出现此问题呢？开始的时候，大家一致认为是软件配置将速率强制成了1000M，但是经过核对，排除了“软件配置问题”。

难道是硬件问题？首先对比一下上个版本的硬件设计，硬件连接如下图：硬件连接图（1）出现问题版本硬件设计，硬件连接如下图：硬件连接图（2）上面的这些接口，都是大家比较熟悉的，硬件设计为了兼容前一版本的上行扣板，在底板上增加了SerDes芯片，使底板出SerDes接口上行。

考虑降成本因素，采用了价格较低TLK1201芯片。

分别分析TLK1201的对外接口。

首先分析SerDes接口，SerDes接口是大家所较熟悉的，“SerDes”接口自协商大家看来是没有任何问题，但是学习了一下“SerDes”接口，却发现和我们平时的理解有些差异。

查阅bcm5464芯片资料，描述如下：SerDes: 1000 Mbps operation。

The SerDes interface shares the same differential data pin as the SGMII interface. The BCM5464S can act as a 1-GHz。

media converter by both supporting SerDes fiber and copper line interfaces simultaneously.很显然SerDes接口仅仅具备1000Mbps数据收发功能，不支持速率的自适应，那么上一版本我们认为的“SerDes”接口是如何进行速率协商的呢？结果发现是我们没有正确的区分速率自协商的。

GE电口速率自协商问题-经典问题解析

GE电口速率自协商问题案例来源：单板调试关键词：GE电口、自协商1、问题描述在某上行扣板的调试过程中，发现上行GE电口与其它GE电口设备对接时，速率都为1000M时，电口可以正常link；但是当与速率强制为100/10M设备对接时，电口不能正确协商，端口link不上。

2、原因分析电口使用已比较成熟，与以前使用过的单板设计架构也没有太大差异，但是为何会出现此问题呢？开始的时候，大家一致认为是软件配置将速率强制成了1000M，但是经过核对，排除了“软件配置问题”。

难道是硬件问题？首先对比一下上个版本的硬件设计，硬件连接如下图：硬件连接图（1）出现问题版本硬件设计，硬件连接如下图：硬件连接图（2）上面的这些接口，都是大家比较熟悉的，硬件设计为了兼容前一版本的上行扣板，在底板上增加了SerDes芯片，使底板出SerDes接口上行。

考虑降成本因素，采用了价格较低TLK1201芯片。

分别分析TLK1201的对外接口。

首先分析SerDes接口，SerDes接口是大家所较熟悉的，“SerDes”接口自协商大家看来是没有任何问题，但是学习了一下“SerDes”接口，却发现和我们平时的理解有些差异。

查阅bcm5464芯片资料，描述如下：SerDes: 1000 Mbps operation。

The SerDes interface shares the same differential data pin as the SGMII interface. The BCM5464S can act as a 1-GHz。

media converter by both supporting SerDes fiber and copper line interfaces simultaneously.很显然SerDes接口仅仅具备1000Mbps数据收发功能，不支持速率的自适应，那么上一版本我们认为的“SerDes”接口是如何进行速率协商的呢？结果发现是我们没有正确的区分SerDes和SGMII，SGMII接口才是支持10/100/1000M速率自协商的。

QSGMII

QSGMII Specification The Quad Serial Gigabit Media Independent Interface (QSGMII) is designed to satisfy thefollowing requirements:•Convey 4 ports of network data and port speed between a 10/100/1000 PHY and a MAC with significantly less signal pins than required for GMII & SGMII.•Operate in both half and full duplex and at all port speeds.•This implementation can be extended to other port to channel ratios. However, this is outside the scope of this document.QSGMII Specification: EDCS-540123Revision 1.2Change HistoryDefinitionsMII – Media Independent Interface: A digital interface that provides a 4-bit wide datapath between a 10/100 Mbit/s PHY and a MAC sublayer. Since MII is a subset of GMII, in this document, we will use the term “GMII” to cover all of the specification regarding the MII interface.GMII – Gigabit Media Independent Interface: A digital interface that provides an 8-bit wide datapath between a 1000 Mbit/s PHY and a MAC sublayer. It also supports the 4-bit wide MII interface as defined in the IEEE 802.3z specification. In this document, the term “GMII” covers all 10/100/1000 Mbit/s interface operations.SGMII – Serial Gigabit Media Independent Interface: A digital interface that provides a 1.25 Gbps serial dual-data-rate datapath between a 1000 Mbit/s PHY and a MAC sublayer. Refer to ENG-46158 or ftp:///smii/smii.html for details.Revision DateDescriptionAuthor1.2Spetember 7,2007Updated Bit[13] and Bit[0] on Table3 and added a statement of possibleremoval of the first byte of frame in 10/100Mbit/s operation to match SGMII spec.Akin Koyuncuoglu1.1June 20, 2007Reword Note1, Added a requirement to disable running disparity check at receiver.Akin Koyuncuoglu1.0April 17, 2007Updated Interconnect Loss Template-Figure 11 and Channel Loss Budget-Table 9. Updated Differential and com-mon mode return loss parameters and differential voltage values in electrical section.Akin Koyuncuoglu, Warren Meggitt0.5January 4, 2007Updated PCS Receive for carrier_detect function. Updated /I/ Idle Code Group Selection for Transmission. Added a note for running disparity support by Framers. Updated Figure2, Figure4,Figure5,Figure6, Table1 and Table2Akin Koyuncuoglu0.4December 4, 2006Updated legal section in the end of the documentAkin Koyuncuoglu 0.3September 1, 2006Updated Electrical Specification Akin Koyuncuoglu, Warren Meggitt 0.2Nov. 3, 2005Initial ReleaseJeff ProvostOverviewQSGMII uses two data signals in each direction to convey frame data and link rate information between a multi-port 10/100/1000 PHY and Ethernet MAC. The data signals operate at 5.0Gbps using CDR technology to recover the clock at the MAC and PHY interfaces. Due to the high speed of operation, each of these signal pairs are realized as differential pairs thus optimizing signal integrity while minimizing system noise.Figure 1 compares the IEEE 802.3 PCS reference diagram before and after the QSGMII modification.Figure 1“Standard” and Modified Transmit Path Diagrams per IEEE 802.3 PCS/PMATXD<7:0>GMII tx_Config_Reg<D7:D0>tx_Config_Reg<D15:D8>7 6 5 4 3 2 1 0(125 million octets/s)8 + controlH G F E D C B AInput to ENCODE function8B/10B Encodera b c d e i f g h j100 1 2 3 4 5 6 7 8 9Management RegistersPMA Service Interface tx_code-group<9:0>PCS ENCODE functionPMD Service Interface (1250 million tx_bits/s)bit 0 is transmitted firstIEEE 802.3 Figure 36-3-PCS reference diagramTXD<7:0>GMII tx_Config_Reg<D7:D0>tx_Config_Reg<D15:D8>7 6 5 4 3 2 1 0(125 million octets/s)8 + controlH G F E D C B AInput to ENCODE function8B/10B Encoder a b c d e i f g h j100 1 2 3 4 5 6 7 8 9Management RegistersPMA Service Interface (500 million code-groups/s)tx_code-group<9:0>PCS ENCODE functionOutput of ENCODE functionPMD Service Interface (5000 million tx_bits/s)bit 0 is transmitted firstQSGMII Modified Figure 36-3-PCS reference diagramPort 0123no swapper “K28.5”SwapperSwapper operates on8 + controlports 1, 2, 32-bit free-running counter(changes are shown with italicized text)octets + control 8 + controlOutput of ENCODE function (125 million code-groups/s)QSGMII Specification: EDCS-540123Revision 1.2The IEEE 802.3 reference diagrams in Figure 2 shows where the modification to the receive PCS function occurs.The transmit and receive data paths leverage the 1000BASE-X PCS defined in the IEEE 802.3z specification (clause 36). Four ports of traditional GMII data signals (TXD/RXD), data valid signals (TX_EN/RX_DV), and error signals (TX_ER/RX_ER) are muxed, encoded, and serialized. Carrier Sense (CRS) is derived/inferred from RX_DV , and collision (COL) is logically derived in the MAC when RX_DV and TX_EN are simultaneously asserted. There is a small block in the PHY transmit path to suppress TX_ER in full duplex mode when TX_EN is not asserted. Since four 1.25Gbps SGMII ports are interleaved onto a single link, the data-rate becomes 5.0 Gbps.Figure 2“Standard” and Modified Receive Path Diagram per IEEE 802.3 PCS/PMARXD<7:0>GMII 7 6 5 4 3 2 1 0(125 million octets/s)8 + controlH G F E D C B A Output of DECODE function8B/10B Decodera b c d e i f g h j 100 1 2 3 4 5 6 7 8 9PMA Service Interface (125 million code-groups/s)rx_code-group<9:0>PCS DECODE functionInput to DECODE functionPMD Service Interface (1250 million rx_bits/s)bit 0 is received firstIEEE 802.3 Figure 36-3-PCS reference diagram0 0 1 1 1 1 1 x x x Properly aligned comma+symbolRXD<7:0>GMII rx_Config_Reg<D7:D0>rx_Config_Reg<D15:D8>7 6 5 4 3 2 1 0(500 million octets/s)8 + control + carrier_detectH G F E D C B A Output of DECODE function a b c d e i f g h j100 1 2 3 4 5 6 7 8 9Management RegistersPMA Service Interface (500 million code-groups/s)rx_code-group<9:0>PCS DECODE & carrier_detect Input to DECODE function PMD Service Interface (5000 million rx_bits/s)bit 0 is received first0 0 1 1 1 1 1 x x x Properly aligned comma+symbolSwapperports 1, 2, 3“K28.1”K28.1 detect123QSGMII Modified Figure 36-3-PCS reference diagram(changes are shown with italicized text)rx_Config_Reg<D7:D0>rx_Config_Reg<D15:D8>Management Registers8B/10B Decoder &carrier_detect functionclear8 + control +carrier detect 2-bit counterfunction*See Note1disparityENFigure 3 illustrates the resulting bit times on the QSGMII 5.0 Gbps link.In order to determine the port number based time slots the port 0 transmit side incorporates a “K28.5” swapper function that modifies the IDLE /I/ and Configuration /C/ ordered_sets by replacing /K28.5/ with /K28.1/ every time /K28.5/ occurs as shown in table 1. Note that the swapper operates on the GMII octets (8 + control), not on the 10B code-group directly. The data will appear on the QSGMII link in the order: port 0 first, then port 1,then port 2, and lastly port 3. Port 0 data then appears on the link again, and so on.802.3z Section 36.2.4.12 explains the rules for running disparity by sending out one of the two IDLE /I/ ordered_sets whenever the GMII is idle. However, since 8B/10B encoder is detached from PCS Transmit Function, it is no longer feasible to use /I1/ and /I2/ ordered_sets to force the disparity. Therefore, the transmitter may be simplified to only generate /I1/ ordered_sets. This change requires more functionality from the framer as documented in Note1.Note1: QSGMII Receivers should not rely upon receipt of /I2/ ordered_sets for proper operation.Code Ordered_Set Number of Code GroupsPort 0 ”pre-swapper” Encoding Port 0 “post-swapper” Encoding /C /Configuration Alternating /C1/ and /C2/Alternating /C1/ and /C2//C1/Configuration 14/K28.5/D21.5/Config_Reg /K28.1/D21.5/Config_Reg /C2/Configuration 24/K28.5/D2.2/Config_Reg /K28.1/D2.2/Config_Reg /I /IDLE Correcting /I1/Correcting /I1//I1/IDLE 12/K28.5/D5.6//K28.1/D5.6/table 1 Port 0 “K28.5” Swapper DefinitionSGMII TX Figure 310B Encoded Data on the 5.0 Gbps QSGMII Link vs. SGMII 1.25 Gbps876543210800ps9bit-time tx_code-group<9:0>(1 port)QSGMII TX 876543210200ps9tx_code-group<9:0>(1 port)bit-time 800ps (1UI) x 10bits = 8000ps per 10B code-group1UI1UI200ps (1UI) x 10bits = 2000ps per 10B code-groupQSGMII = 4-ports x [2000ps 10B code-group per port] = 8000ps for 4-ports of 10B code-groupsQSGMII Specification: EDCS-540123Revision 1.2The receive 10B code-groups pass through a “K28.1” swapper that undoes the modification of the IDLE /I/ and Configuration /C/ ordered_sets by replacing /K28.1/ with /K28.5/ for every occurrence. The K28.1 swapper also clears the de-mux (sets the counter to 2’b00) in order to determine the port 0 data according to table 2. Note that the swapper operates on the GMII octets (8 + control + carrier_detect), not on the 10B code-group directly.On the receive side, carrier_detect function is done on 10B code-groups and this is shown in Figure 2. Please note that, there is a new carrier_detect function that needs to operate on K28.1 for Port0. K28.1 can be locally converted to K28.5 to generate the carrier_detect function. Please refer to 802.3z Section 36.2.5.1.4 for the carrier_detect function that operates on K28.5.Due to the nature of QSGMII, bit errors on the link may cause a running disparity error to propogate across ports. A software register bit that would enable/disable running disparity checking at the receiver is required. Disabling running disparity checking at the receiver prevents error propogation to other ports. It is not necessary to disable ALL disparity checking in the decoder to prevent error propogation to other ports. It is only necessary to disable the disparity checks that rely on the running disparity value from the previous symbol. Note that code violations due to invalid code-words (and current symbol running disparity errors) should continue to be detected regardless of the state of running disparity checking. Please also note that, 802.3z Section 36.2.4.6 and DECODE([/x/]) function in Section 36.2.5.1.4 will be affected by this requirement.Ports 1-3 are unchanged from SGMII specification.Control information, as specified in table 3, is transferred from the PHY to the MAC to signal the change of the link status. This is achieved by using the Auto-Negotiation functionality defined in Clause 37 of the IEEE Specification 802.3z. Instead of the ability advertisement, the PHY sends the control information via its tx_config_Reg[15:0] as specified in table 3whenever the link status changes. Upon receiving control information, the MAC acknowledges the update of link status by asserting bit 14 of its tx_config_reg{15:0] as specified in table 3.The link_timer inside the Auto-Negotiation block has been changed from 10 msec to 1.6 msec to ensure a prompt update of the link status.Code Ordered_Set Number of Code GroupsPort 0 ”pre-swapper” Encoding Port 0 “post-swapper” Encoding /C /Configuration Alternating /C1/ and /C2/Alternating /C1/ and /C2//C1/Configuration 14/K28.1/D21.5/Config_Reg /K28.5/D21.5/Config_Reg /C2/Configuration 24/K28.1/D2.2/Config_Reg /K28.5/D2.2/Config_Reg /I /IDLE Correcting /I1/Correcting /I1//I1/IDLE 12/K28.1/D5.6//K28.5/D5.6/table 2 Port 0 “K28.1” Swapper DefinitionBit Number tx_config_Reg[15:0] sent from the PHY to the MACtx_config_Reg[15:0] sent from the MAC to the PHY 15Link: 1 = link up, 0 = link down0: Reserved for future use 14Reserved for Auto-Negotiation acknowledge as specified in 802.3z 1130: Reserved for future use0: Reserved for future use 12Duplex mode: 1 = full duplex, 0 = half duplex0: Reserved for future usetable 3 Definition of Control Information passed between links via tx_config_Reg[15:0]QSGMII’s 5.0 Gbps transfer rate is excessive for PHYs operating at 10 or 100 Mbit/s. When these situations occur, the interface “elongates” the frame by replicating each frame byte 10 times for 100 Mbit/s and 100 times for 10 Mbit/s. This frame elongation takes place “above” the 802.3z PCS layer, thus the start frame delimiter only appears once per frame. The 802.3z PCS layer may remove the first byte of the “elongated” frame.11:10Speed: Bit 11, 10:1 1 = Reserved1 0 = 1000 Mbps: 1000BASE-TX, 1000BASE-X 0 1 = 100 Mbps: 100BASE-TX, 100BASE-FX 0 0 = 10 Mbps: 10BASET, 10BASE2, 10BASE50: Reserved for future use9:10: Reserved for future use 0: Reserved for future use 011Bit Number tx_config_Reg[15:0] sent from the PHY to the MACtx_config_Reg[15:0] sent from the MAC to the PHY table 3 Definition of Control Information passed between links via tx_config_Reg[15:0]QSGMII Specification: EDCS-540123Revision 1.2 Implementation SpecificationThis section discusses how this QSGMII interface shall be implemented by incorporating andmodifying the PCS layer of the IEEE Specification 802.3z. Figure 4 illustrates the connectionsbetween the MAC and the PHY in a system utilizing QSGMII, as well as the overall scheme ofmuxing, demuxing 4 ports into a single QSGMII channel.Figure 4QSGMII ConnectivitySignal Mapping at the PHY sideFigure 5 shows the PHY functional block diagram. It illustrates that the PCS layer shall beFigure 5PHY Functional Block For One PortAt the receive side, GMII signals come in at 10/100/1000 Mbit/s clocked at 2.5/25/125 MHz.The PHY passes these signals through the PHY Receive Rate Adaptation to output the 8-bitdata RXD[7:0] in Reference Clock domain. Please note that since 4 ports are multiplexed,recovered RX_CLK can not be used to output the 8-bit data RXD[7:0]. RXD is sent to the PCSTransmit State Machine to generate an encoded 10-bit segment ENC_RXD[0:9]. The PHYserializes ENC_RXD[0:9] to create RX and sends it to the MAC at 5.0 Gbps.802.3z Section 36.2.4.12 explains the rules for running disparity by sending out one of the twoIDLE /I/ ordered_sets whenever the GMII is idle. However, since 8B/10B encoder is detachedfrom PCS Transmit Function, it is no longer feasible to use /I1/ and /I2/ ordered_sets to forcethe disparity. Therefore, the transmitter may be simplified to only generate /I1/ ordered_sets.This change requires more functionality from the framer as documented in Note1.Due to the nature of QSGMII, bit errors on the link may cause a running disparity error topropogate across ports. A software register bit that would enable/disable running disparitychecking at the receiver is required. Disabling running disparity checking at the receiverprevents error propogation to other ports. It is not necessary to disable ALL disparity checkingin the decoder to prevent error propogation to other ports. It is only necessary to disable thedisparity checks that rely on the running disparity value from the previous symbol. Note thatQSGMII Specification: EDCS-540123Revision 1.2 code violations due to invalid code-words (and current symbol running disparity errors) shouldcontinue to be detected regardless of the state of running disparity checking. Please also notethat, 802.3z Section 36.2.4.6 and DECODE([/x/]) function in Section 36.2.5.1.4 will beaffected by this requirement.At the transmit side, the PHY deserializes TX to recover encoded ENC_TXD[0:9]. The PHYpasses ENC_TXD[0:9] through the PCS Receive State Machine to recover the GMII signals.In the mean time, Synchronization block checks ENC_TXD[0:9] to determine thesynchronization status between links, and to realign if it detects the loss of synchronization.The decoded GMII signals have to pass the PHY Transmit Rate Adaptation block to outputdata segments according to the PHY port speed.To make the PCS layer from 802.3z work properly, the PHY must provide a frame beginningwith at least two preamble symbols followed by a SFD symbol. To be more specific, at thebeginning of a frame, RXD[7:0] in Figure 5 shall be {8’h55, 8’h55, (8’h55...), 8’h55} followedby valid frame data.Some legacy end points will drop frames when RX_ER asserts during the first clock after aframe ends. The receive PCS state machine generates this signalling at the end of certainframes. To avoid this problem, there is a small block in the PHY transmit path to suppressTX_ER in full duplex mode when RX_DV (from the PHY receive PCS state machine) is notasserted.Signal Mapping at the MAC SideFigure 6 shows the MAC functional block diagram. It illustrates that the PCS layer shall bemodified and incorporated at the MAC side in the QSGMII interface.Figure 6MAC Functional Block for One PortAt the receive side, the MAC deserializes RX to recover encoded ENC_RXD[0:9]. The MACpasses ENC_RXD[0:9] through the PCS Receive State Machine to recover the GMII signals.In the mean time, Synchronization block checks ENC_RXD[0:9] to determine thesynchronization status between links, and to realign once it detects the loss of synchronization.The decoded GMII signals have to pass the MAC Receive Rate Adaptation block to outputdata segments according to the PHY port speed, passed from the PHY to MAC via Auto-Negotiation process.At the transmit side, GMII signals come in at 10/100/1000 Mbit/s data clocked at 2.5/25/125MHz. The MAC passes these signals through the MAC Transmit Rate Adaptation to output the8-bit data TXD[7:0] in 125MHz clock domain. TXD is sent to the PCS Transmit StateMachine to generate an encoded 10-bit segment ENC_TXD[0:9]. The MAC serializesENC_TXD[0:9] to create TX and sends it to the PHY at 5.0 GbpsQSGMII Specification: EDCS-540123Revision 1.2Control Information Exchanged Between LinksAs described in Overview, it is necessary for the PHY to pass control information to the MACto notify the change of the link status. QSGMII interface uses Auto-Negotiation block to passthe control information via tx_config_Reg[15:0].If the PHY detects the link change, it starts its Auto-Negotiation process, switching itsTransmit block from “data” to “configuration” state and sending out the updated controlinformation via tx_config_Reg[15:0]. The Receive block in the MAC receives and decodescontrol information, and starts the MAC’s Auto-Negotiation process. The Transmit block inthe MAC acknowledges the update of link status via tx_config_Reg[15:0] with bit 14 asserted,as specified in table 3. Upon receiving the acknowledgement from the MAC, the PHYcompletes the auto-negotiation process and returns to the normal data process.As specified in Overview, inside the QSGMII interface the Auto-Negotiation link_timer hasbeen changed from 10 msec to 1.6 msec, ensuring a prompt update of the link status. Theexpected latency for the update of link is 3.4 msec (two link_timer time + an acknowledgementprocess).Data Information Transferred Between LinksBelow we briefly describe at receive side how GMII signals get transferred across from thePHY and recovered at the MAC by using the 8B/10B transmission code. The same methodapplies to the transmit side.According to the assertion and deassertion of RX_DV, the PHY encodes the Start_of_Packetdelimiter (SPD /S/) and the End_Of_Packet delimiter (EPD) to signal the beginning and end ofeach packet. The MAC recovers RX_DV signal by detecting these two delimiters.The PHY encodes the Error_Propagation(/V/) ordered_set to indicate a data transmission error.The MAC asserts RX_ER signal whenever it detects this ordered_set.CRS is not directly encoded and passed to the MAC. To regenerate CRS, the MAC shall usessignal RX_DV before it is being passed to the MAC Receive Rate Adaptation block as shownin Figure 6.The MAC decodes ENC_RXD[0:9] to recover RXD[7:0].Figure 7 illustrates how the MAC samples data in 100 Mbit/s mode. The GMII data in 100Mbit/s mode get replicated ten times after passing through the PHY Receive Rate Adaptationto generate RXD[7:0]. The modified PCS Transmit State Machine encodes RXD[7:0] to createENC_RXD[0:9]. As noted in the Overview, the SPD (/S/) only appears once per frame.SAMPLE_EN is a MAC internal signal to enable the MAC sampling of data starting at thefirst data segment (/S/) once every ten data segments in 100 Mbit/s mode.Electrical SpecificationCML, (Current Mode Logic) is by far the most common serdes IO standard in use today. The signal swing provided by the CML output is small, resulting in low power consumption. The driver and receiver are often self-terminated, eliminating external components and minimizing transmission line impedance discontinuity effects on timing and signal integrity.The following section details the requirements for the high speed electrical interface that will operate at 5Gsym/s using NRZ coding (hence 1 bit per symbol at electrical level). Connections are point to point balanced differential pair with 100 Ohm nominal differential impedance and signalling is unidirectional. Clock and data are embedded hence CDR is required in the receiver. The link should operate with a BER of 10-15. It supports both AC and DC coupled operation. However, DC coupling of PHY to MAC is required since it optimizes system cost, complexity, and signal integrity.This section is based on the Optical Internetworking Forum’s(OIF) Common Electrical I/O CEI-6G-SR Short Reach Standard IA#OIF-CEI-02.0 with some modifications listed in below sections.Characteristic Load Type 0(AC Coupling)Load Type 1(DC Coupling)Units R_Zvtt >1K <30Ohms Nominal VttUndefined1.2Vtable 4 Definition of Load TypesParameter Symbol MinTyp MaxUnits NotesBaud RateT_Baud 5.000Gsym/s a Output Differential V oltage (into floating Load Rload=100Ohm)T_Vdiff 400900mVppd bDifferential ResistanceT_Rd 80100120Ohms Recommended Output Rise and Fall Times (20% to 80%)T_tr,T_tf 30ps Differential Output Return Loss (100Mhz to 2.5 GHz )T_SDD22-8dBctable 5 Transmitter Output Electrical Specification125 MHz ClockData in 100 Mbit/sRXD[7:0] after Figure 7Data Sampling in 100 Mbit/s modeD0D0D0D0D0D0D0D0D0D0D1D1D1D1D1D1D1D1D1D1D2D2D2D2D2D2D2D2D2Data0Data1Data2ENC_RXD[0:9]/S/d0d0d0d0d0d0d0d0d0d1d1d1d1d1d1d1d1d1d1d2d2d2d2d2d2d2d2d2SAMPLE_ENRX_DVDomain Rate AdaptationQSGMII Specification: EDCS-540123Revision 1.2Differential Output Return Loss (2.5 GHz to 5 GHz)T_SDD22dBdCommon Mode Return Loss (100Mhz to 2.5 GHz )T_SCC22-6dB eTransmitter Common Mode Noise T_Ncm5% of T-Vdiff mVppd Output current into or out of driver pins when either SHORT to GND or each other100mAfOutput Common Mode V oltage See Note g , See Note h , See Note iT_Vcm 0.0735 1.81135VmVj LoadType0Load Type 1a.CEI-6G-SR is defined to operate between baud rates of 4.976 and 6.375 Gsym/s, However QSGMII will operate at 5 Gsym/s with a tolerance of +/-100ppm.b.Absolute driver output voltage shall be between -0.1V and 1.9V with respect to local ground.See Figure 10 for details.c.See Figure 9d.See Figure 9e.See Figure 9f.+/- 100 mAg.For both Load Types: R_Rdin=100 Ohms+/- 20 Ohms.For Vcm definition, see Figure 10.h.For Load Type 1: R_ZVtt <30Ohms; Vtt is defined follows: Load Type 1: R_Vtt =1.2V +5%/-8%i.DC Coupling compliance is Type 1. It is acceptable for a Transmitter to restrict the range of T_Vdiff in order to comply with the specified T_Vcm range. For a transmitter which supports multiple T_Vdiff levels, it is acceptable for a Trans-mitter to claim DC Compliance if it meets the T_Vcm ranges for at least one of its T_Vdiff setting as long as those settings that are compliant are indicated.j.Load Type 0 with min T_Vdiff, AC Coupling or floating load.ParameterSymbol MinTypMax Units NotesUncorrelated High Probability JitterT_UHPJ 0.15UIpp aDuty Cycle Distortion T_DCD 0.05UIpp Total Jitter T_TJ 0.30UIpp b Eye Mask T_X10.15UI c Eye Mask T_X20.40UI d Eye Mask T_Y1200mV e Eye MaskT_Y2450mVftable 6 Transmitter Output Jitter Specificationsa.This parameter is defined as: Jitter distribution where the value of the jitter show no correlation to any signal level being transmitted. Formally defined as deter-ministic jitter, T_DJb.The link will operate with a BER of 10-15c.See Figure 8d.See Figure 8e.See Figure 8ParameterSymbol Min Typ Max Units Notestable 5 Transmitter Output Electrical Specificationf.See Figure 8Parameter Symbol Min Typ Max Units NotesRX Baud rateR_Baud 5.000GSym/sa a.CEI-6G-SR is defined to operate between baud rates of 4.976 and 6.375 Gsym/s, However QSGMII will operate at 5 Gsym/s with a tolerance of +/-100ppm.Input Differential V oltage R_Vdiff 100900mVppd bb.Min Value is changed from the standard and reduced to 100 mV .Differential Resistance R_Rdin 80100120Ohms Bias V oltage Source Impedance (Load Type 1)R_Zvtt 30Ohms cc.Load Type 1 is with DC Coupling.Differential Input Return Loss (100MHz to 2.5 GHz )R_SDD1-8dB dd.See Figure 9Differential Input Return Loss (2.5 GHz to 5 GHz)R_SDD1dBee.See Figure 9Common Mode Input Return Loss (100MHz to 2.5 GHz )R_SCC1-6dB ff.See Figure 9Termination V oltageR_VttNot spec-ified1.2 -8%Not spec-ifiedNot spec-ified1.2 +5%VVg R_Vttfloating, Load Type0R_Vtt=1.2V Nominal, Load Type1g.For floating load, input resistance must be > 1K Ohms.Input Common Mode V oltage See Note hh.For Vcm definition, see Figure 10.R_Vrcm -0.05720 1.85R_Vtt-10VmViR_Vtt floating, Load Type0R_Vtt=1.2V Nominal, Load Type1i.Input Common Mode voltage for AC-Coupled or floating load input with min T_VdiffWander divider n 10jj.See Figure 2-27 & Figure 2-28 in CEI-6G-SR document for detailstable 7 Receiver Electrical Input SpecificationsParameter Symbol Min Typ Max Units NotesBounded High Probability Jitter R_BHPJ 0.45UIpp aSinusoidal Jit-ter,maximumR_SJ-max5UIpptable 8 Receiver Input Jitter Tolerance SpecificationsQSGMII Specification: EDCS-540123Revision 1.2Sinusodial Jitter, High Frequency R_SJ-hf 0.05UIpp Total Jitter(Does not include Sinu-sodial Jitter)R_TJ0.60UIppbEye Mask R_X10.30UI c Eye Mask R_Y150mV d Eye MaskR_Y2450mVea.This is the sum of Uncorrelated Bounded High Probability Jitter (0.15 UI) and Correlated Bounded High Probability Jitter (0.30 UI).Uncorrelated Bounded High Probability Jitter: Jitter distribution where the value of the jitter show no correlation to any signal level being transmit-ted. Formally defined as deterministic jitter, T_DJCorrelated Bounded High Probability Jitter: Jitter distribution where the value of the jitter shows a strong correlation to the signal level being transmitted. This jitter may considered as being equalisable due to its correlation to the signal levelb.The link will operate with a BER of 10-15c.See Figure 8d.See Figure 8.e.See Figure 8.Parameter Symbol Min Typ Max Units Notestable 8 Receiver Input Jitter Tolerance SpecificationsFigure 8Driver and Receiver Eye MaskAmplitude mVTime UI 0.0T_X1T_X21-T_X21-T_X11.0Transmit Eye MaskT_Y1-T_Y1-T_Y2T_Y2Time UIReceiver Eye Mask0.01.01-R_X10.50R_Y1-R_Y1R_Y2-R_Y2R_X1。

SGMII

Serial-GMII Specification The Serial Gigabit Media Independent Interface (SGMII) is designed to satisfy the followingrequirements:•Convey network data and port speed between a 10/100/1000 PHY and a MAC withsignificantly less signal pins than required for GMII.•Operate in both half and full duplex and at all port speeds. Change HistoryRevision Date Description1.8April 27, 2005Add shim to the PHY transmit datapath to suppress TX_ER when TX_ENis not asserted1.7July 20, 20001Clarify data sampling and also the possible loss of the first byte of pream-ble.1.6Jan 4, 20001Added specifications for Cisco Systems Intellectual Property.1.5Aug 4, 2000Specified the data pattern for the beginning of the frame (preamble, SFD)for the frames sent from the PHY to make the PCS layer work properly.1.4June 30, 2000Took out Jabber info, changed tx_Config_Reg[0] from 0 to 1 to make Auto-Negotiation work1.3April 17, 2000Increased allowable input and output common mode range. The output highand low voltages were also increased appropriately. Added specification foroutput over/undershoot. Added note about AC coupling and clock recovery.1.2Feb 8, 2000Added timing budget analysis and reduced LVDS input threshold to +/- 50mV.1.1Nov 10, 1999Incoporated Auto-Negotiation Process for update of link status1.0Oct. 14, 1999Initial Releaseef initionsMII – Media Independent Interface: A digital interface that provides a 4-bit wide datapathbetween a 10/100 Mbit/s PHY and a MAC sublayer. Since MII is a subset of GMII, in thisdocument, we will use the term “GMII” to cover all of the specification regarding the MIIinterface.S fi on E15on 1.GMII – Gigabit Media Independent Interface: A digital interface that provides an 8-bit wide datapath between a 1000 Mbit/s PHY and a MAC sublayer. It also supports the 4-bit wide MII interface as defined in the IEEE 802.3z specification. In this document, the term “GMII”covers all 10/100/1000 Mbit/s interface operations.Ov erv iewSGMII uses two data signals and two clock signals to convey frame data and link rate information between a 10/100/1000 PHY and an Ethernet MAC. The data signals operate at 1.25 Gbaud and the clocks operate at 625 MHz (a DDR interface). Due to the speed of operation, each of these signals is realized as a differential pair thus providing signal integrity while minimizing system noise.Figure 1 illustrates the simple connections in a system utilizing SGMII.The transmit and receive data paths leverage the 1000BASE-SX PCS defined in the IEEE 802.3z specification (clause 36). The traditional GMII data signals (TXD/RXD), data valid signals (TX_EN/RX_DV), and error signals (TX_ER/RX_ER) are encoded, serialized and output with the appropriate DDR clocking. Thus it is a 1.25 Gbaud interface with a 625 MHz clock. Carrier Sense (CRS) is derived/inferred from RX_DV, and collision (COL) is logically derived in the MAC when RX_DV and TX_EN are simultaneously asserted. There is a small block in the PHY transmit path to suppress TX_ER in full duplex mode when TX_EN is not asserted.Control information, as specified in Table 1, is transferred from the PHY to the MAC to signal the change of the control information. This is achieved by using the Auto-Negotiation functionality defined in Clause 37 of the IEEE Specification 802.3z. Instead of the ability advertisement, the PHY sends the control information via its tx_config_Reg[15:0] as specified in Table 1 whenever the control information changes. Upon receiving control information, the MAC acknowledges the update of the control information by asserting bit 14 of its tx_config_reg{15:0] as specified in Table 1.SGMII details source synchronous clocking; however, specific implementations may desire to recover clock from the data rather than use the supplied clock. This operation is allowed;however, all sources of data must generate the appropriate clock regardless of how they clock receive data.1S fi on E 15on 1.The link_timer inside the Auto-Negotiation has been changed from 10 msec to 1.6 msec to ensure a prompt update of the link status.Clearly, SGMII’s 1.25 Gbaud transfer rate is excessive for interfaces operating at 10 or 100Mbps. When these situations occur, the interface “elongates” the frame by replicating each frame byte 10 times for 100 Mbps and 100 types for 10 Mbps. This frame elongation takes place “above” the 802.3z PCS layer, thus the start frame delimiter only appears once per frame.The 802.3z PCS layer may remove the first byte of the “elongated” frame.Bit Number tx_config_Reg[15:0] sent from the PHY to the MACtx_config_Reg[15:0] sent from the MAC to the PHY 15Link: 1 = link up, 0 = link down0: Reserved for future use 14Reserved for Auto-Negotiation acknowledge as specified in 802.3z 1130: Reserved for future use0: Reserved for future use 12Duplex mode: 1 = full duplex, 0 = half duplex 0: Reserved for future use 11:10Speed: Bit 11, 10:1 1 = Reserved1 0 = 1000 Mbps: 1000BASE-TX, 1000BASE-X 0 1 = 100 Mbps: 100BASE-TX, 100BASE-FX 0 0 = 10 Mbps: 10BASET, 10BASE2, 10BASE50: Reserved for future use9:10: Reserved for future use 0: Reserved for future use 0111 D fi on of C on ol I for on p b l v t on fi 15em entation S ec if ic ationThis section discusses how this SGMII interface shall be implemented by incorporating and modifying the PCS layer of the IEEE Specification 802.3z.Signal Mapping at the PHY sideFigure 2 shows the PHY functional block diagram. It illustrates how the PCS layer shall be modified and incorporated at the PHY side in the SGMII interface.At the receive side, GMII signals come in at 10/100/1000 Mbps clocked at 2.5/25/125 MHz.The PHY passes these signals through the PHY Receive Rate Adaptation to output the 8-bit data RXD[7:0] in 125MHz clock domain. RXD is sent to the PCS Transmit State Machine to generate an encoded 10-bit segment ENC_RXD[0:9]. The PHY serializes ENC_RXD[0:9] to create RX and sends it to the MAC at 1.25 Gbit/s data rate along with the 625 MHz DDR RXCLK.At the transmit side, the PHY deserializes TX to recover encoded ENC_TXD[0:9]. The PHY passes ENC_TXD[0:9] through the PCS Receive State Machine to recover the GMII signals.In the mean time, Synchronization block checks ENC_TXD[0:9] to determine the synchronization status between links, and to realign if it detects the loss of synchronization.S fi on E15on 1.The decoded GMII signals have to pass the PHY Transmit Rate Adaptation block to output data segments according to the PHY port speed.To make the PCS layer from 802.3z work properly, the PHY must provide a frame beginning with at least two preamble symbols followed by a SFD symbol. To be more specific, at the beginning of a frame, RXD[7:0] in Figure 2 shall be {8’h55, 8’h55, (8’h55.....), 8’hD5} followed by valid frame data.Some legacy end points have drop frames when RX_ER asserts during the first clock after a frame ends. The Receive PCS state machine generates this signalling at the end of certain frames. To avoid this problem, there is a small block in the PHY transmit path to surppress TX_ER in full duplex mode when RX_DV (from the Receive PCS state machine) is not asserted.Signal Mapping at the MA SideFigure 3 shows the MAC functional block diagram. It illustrates how the PCS layer shall be modified and incorporated at the MAC side in the SGMII interface.At the receive side, the MAC deserializes RX to recover encoded ENC_RXD[0:9]. The MAC passes ENC_RXD[0:9] through the PCS Receive State Machine to recover the GMII signals.In the mean time, Synchronization block checks ENC_RXD[0:9] to determine the synchronization status between links, and to realign once it detects the loss of synchronization.The decoded GMII signals have to pass the MAC Receive Rate Adaptation block to output data segments according to the PHY port speed, passed from the PHY to MAC via Auto-Negotiation process.At the transmit side, GMII signals come in at 10/100/1000 Mbps data clocked at 2.5/25/125 MHz. The MAC passes these signals through the MAC Transmit Rate Adaptation to output the 8-bit data TXD[7:0] in 125MHz clock domain. TXD is sent to the PCS Transmit State Machine to generate an encoded 10-bit segment ENC_TXD[0:9]. The MAC serializes ENC_TXD[0:9] to create TX and sends it to the PHY at 1.25 Gbit/s data rate along with the 625 MHz DDR TXCLK.ntr l I nf atio n E hanged B etw een L ink sAs described in Overview, it is necessary for the PHY to pass control information to the MAC to notify the change of the link status. SGMII interface uses Auto-Negotiation block to pass the control information via tx_config_Reg[15:0].If the PHY detects the control information change, it starts its Auto-Negotiation process, switching its Transmit block from “data” to “configuration” state and sending out the updated control information via tx_config_Reg[15:0]. The Receive block in the MAC receives and decodes control information, and starts the MAC’s Auto-Negotiation process. The Transmit block in the MAC acknowledges the update of link status via tx_config_Reg[15:0] with bit 14 asserted, as specified in Table 1. Upon receiving the acknowledgement from the MAC, the PHY completes the auto-negotiation process and returns to the normal data process.As specified in Overview, inside the SGMII interface, the Auto-Negotiation link_timer has been changed from 10 msec to 1.6 msec, ensuring a prompt update of the link status. The expected latency for the update of link is 3.4 msec (two link_timer time + an acknowledgement process).ata I nf atio n T ansf er ed B etw een L ink sBelow we briefly describe at receive side how GMII signals get transferred across from the PHY and recovered at the MAC by using the 8B/10B transmission code. The same method applies to the transmit side.According to the assertion and deassertion of RX_DV, the PHY encodes the Start_of_Packet delimiter (SPD /S/) and the End_Of_Packet delimiter (EPD) to signal the beginning and end of each packet. The MAC recovers RX_DV signal by detecting these two delimiters.The PHY encodes the Error_Propagation(/V/) ordered_set to indicate a data transmission error. The MAC asserts RX_ER signal whenever it detects this ordered_set.CRS is not directly encoded and passed to the MAC. To regenerate CRS, the MAC shall uses signal RX_DV before it is being passed to the MAC Receive Rate Adaptation block as shown in Figure 3.The MAC decodes ENC_RXD[0:9] to recover RXD[7:0].Figure 4 illustrates how the MAC samples data in 100 Mbit/s mode. As signals shown in Figure 2, the GMII data in 100 Mbit/s mode get replicated ten times after passing through the PHY Receive Rate Adaptation to generate RXD[7:0]. The modified PCS Transmit State Machine encodes RXD[7:0] to create ENC_RXD[0:9]. As noted in the Overview, the SPD(/S/ ) only appears once per frame. SAMPLE_EN is a MAC internal signal to enable the MAC sampling of data starting at the first data segment (/S/) once every ten data segments in 100 Mbit/s mode.S fi on E 15on 1.A note to Figure 4: there is no fixed boundary for the data sampling. Also the first byte of preamble might be only repeated 9/99 instead of 10/100 times due to the algorithm of the 802.3z PCS Transmit State Machine.LV A C/ C S ec if ic ationThe basis of the LVDS and termination scheme can be found in IEEE1596.3-1996. Some parameters have been modified to accommodate the 1.25Gb/s requirements. SGMII consists of the most lenient DC parameters between the general purpose and reduced range LVDS.Both the data and clock signals are DC balanced; therefore, implementations that meet the AC parameters but fail to meet the DC parameters may be AC coupled.125 MHz ClockData in 100 Mbit/sRXD[7:0] after 4 S i 10 M m od D0D0D0D0D0D0D0D0D0D0D1D1D1D1D1D1D1D1D1D1D2D2D2D2D2D2D2D2D2Data0Data1Data2ENC_RXD[0:9]/S/d0d0d0d0d0d0d0d0d0d1d1d1d1d1d1d1d1d1d1d2d2d2d2d2d2d2d2d2SAMPLE_ENRX_DVDomain Rate AdaptationFigure 5 shows the DDR circuit at the source of the LVDS. The circuit passes data and clock with a 90 degree phase difference. The receiver samples data on both edges of the clock.Symbol a a.For a detailed description of the symbols please refer to the IEEE1596.3-1996 standardParameter bb.All parameters measured at R load = 100ohms +-1% loadMinMax Units V oh Output voltage high, 1525mV V ol Output voltage low 875mV Vring Output ringing10%|Vod|Output Differential V oltage 150400mV V os Output Offset V oltage 10751325mV Ro Output impedance (single ended)40140ohms ∆Ro Mismatch in a pair10%∆|V od|Change in Vod between “0” and “1”25mV ∆V os Change in V os between “0” and “1”25mV Isa, Isb Output current on Short to GND 40mA Isab Output current when a, b are shorted12mA Ixa, IxbPower off leakage current10mA2 D D s fi on5fe 6 C oc a D A RXRXRXCLK RXCLK (single ended)(differential)(single ended)(differential)tclock2q (min)tclock2q (max)S fi on E 15on 1.ep resentativ e T im ing B getA transmit and receive path timing budget provided in the table below. The exact allocation of the budget is implementation specific; however, verification of overall requirements are tested against the specifications in the tables external to the packaged integrated circuit.Symbol ParameterMin Max Units Vi Input Voltage range a or b 6751725mV Vidth Input differential threshold -50+50mV Vhyst Input differential hysteresis 25mv RinReceiver differential input impedance80120ohms3 R D s fi onSymbol a ParameterMin Max Units clock Clock signal duty cycle @ 625MHz4852%t fall V od fall time (20%-80%)100200pSec t rise V od rise time (20%-80%)100200pSec t skew1bSkew between two members of a differential pair - |tp HLA -tp LHB | or |tp LHA - tp HLB |20pSect clock2q cClock to Data relationship: from either edges of the clock to valid data250550pSec4 D A s fi ona.For a detailed description of the symbols please refer to the IEEE1596.3-1996 standardb.Skew measured at 50% of the transitionc.Skew measured at 0v differentialSymbol Parameter Min MaxUnits t setup a setup time 100pSec t holdhold time100pSec5 R A s fi ona.Measured at 50% of the transitionElementValue Units Effective clock period 800 psCycle to cycle clock jitter 100 ps peak-peak Imperfect duty cycle 30 ps peak-peak Data dependent jitter 70 ps peak-peak Static package skew 100ps peak-peak Remaining window500 (250 ps clock2q)ps peak-peak6 T b for d rElement Value UnitsDriver window500ps peak-peakStatic package skew100ps peak-peakReceiver setup time100ps peak-peakRemaining window300ps peak-peak7 T b for r rThis budget shows the driver generating a data signal with a 500 ps eye centered around thesampling clock edge (see Figure 6 “Driver Clock and Data Alignment” on page 9). Thereceiver will add additional skew, leaving 300 ps of margin.Cisc o S ystem s I ntel ec tu al P rop ertyCisco Systems has released its proprietary rights to information contained in this document forthe express purpose of implementation of this specification to encourage others to adopt thisinterface as an industry standard. Any company wishing to use this specification may do so ifthey will in turn relinquish their proprietary rights to information contained or referencedherein. Any questions concerning this release should be directed to the Robert Barr, WorldWide Patent Counsel, Cisco Systems, 300 East Tasman Drive, San Jose, CA.11 of 11ov 2 2。

SGM常用缩略语解释(May 2003)

Acronym Definition Departmentm Meter TechCtrM Magnetic Field Strength VTSM Mega (1,000,000 times) or Million MLBSM, TechCtrM&E Machinery & Equipment TechCtrM/C Model Code.MLBSMM/T Manual Transmission PSEO, TechCtrM2VA Mule 2 Virtual Assessment TechCtrM4Manual Four Speed Transmission.MLBSMM85Mixture of 85% Methanol, 15% unleaded gasoline.mA Milli-Amp TechCtrMAC Management Assessment Center.MLBSMMAC Manufacturers Advisory Correspondence.MLBSMMAC Master Aperture Cards TechCtrMAC Media Access Controller TechCtrMAC Multiple ACcumulate TechCtrMACOS Material Composition System GEDOC, TechCtr, GEBFWC MACRO Macroinstruction.MLBSMMACS Material Alignment & Counting System MLBSMMADYMO MAthematical DYnamic Models (A dynamical modeling CAE package used to simulate thedynamic behavior of mechanical systems, such as automotive crashes for the purpose ofassessing structural behavior and occupant safety.)MAF Mass Air Flow.PSEO, MLBSM, TechCtr MAFS Mass Air Flow Sensor.MLBSMMAG CARD Magnetic Card.MLBSMMAI Manifold Air Injection.MLBSMMAIR Manifold Air Injection Reactor.MLBSMMalf Malfunction (an abbreviation)PSEOMALL Multifunction Alarm Lighting and Locking.PSEOVSSMMAM Market Area Manager. In charge of a specific market area and head of that specificMarketing Area Team.MAM Modular Air Meter TechCtrMAM Multilayer Alumina Substrate Module MLBSMMan Manual (abbreviation)PSEO, GMPTManufact Manufactures (an abbreviation)PSEOQVRManVal Manufacturing Validation. Manufacturing Validation is the critical build that makes thetransition from non-salable to salable vehicles.MAO Market Area OfficeMAP Manifold Absolute Pressure PSEO, MLBSM, TechCtr,GMPTMAP Manufacturing Action Permit.MLBSMMAP Manufacturing Automation Protocol.MLBSM, TechCtrMAP Market Area PlanningMAP Material Archive Program (CARS Section: MAP is a database of more than 90 steel materialcombinations [hot- or cold-rolled, strength level, and coatings]. It provides easy access to themost frequently used automotive steels and includes a full section on material properties.)MAP Military Assistance Program.MLBSMMAPI Messaging Application Programming InterfaceMAPICS Manufacturing Accounting & Production Information Control System.MLBSMMAPS Manifold Absolute Pressure Sensor MLBSMMar March (an abbreviation)PSEOMARCO Microelectronics Advanced Research Corporation [not-for-profit research managementorganization that funds and operates a number of microelectronics technology oriented,university-based research centers. MARCO is a wholly owned, but separately managed,subsidiary of the Semiconductor Research Corporation (SRC). The SRC is a researchmanagement consortium that was established in 1982 as the university research arm of theSemiconductor Industry Association (SIA).]MARS Material Accumulative Requirement Summary MLBSMMARS Measurement, Analysis, & Reporting SystemMAS Material Arrival System MLBSMMASER Microwave Amplification by the Stimulated Emission of Radiation TechCtrMASH MultistAge Noise Shaping TechCtrMAT Manifold Absolute Temperature.MLBSMMAT Manifold Air Temperature PSEO, TechCtrVSSMMAT Market Area Team. This includes a Market Area Manager, Area Parts Manager, FieldSupport Manager, Area Service Manager, Area Sales Manager and a GMACRepresentative.MAT Metropolitan Area Trunk TechCtrMATE Modular Automated Test Equipment TechCtrMATS Manifold Absolute Temperature SensorMATS Manifold Air Temperature Sensor.MLBSMMATS Material Analytical Template System.MATV Master Antenna TeleVision TechCtrMAU Media Access Unit (communications adapter)TechCtrMax Maximum (an abbreviation)PSEOMB MegaByte.MLBSMMBD Master Build DocumentMBD Million Barrels Per Day.MLBSMMBD Model Based Diagnostics.MBE Minority Business EnterprisesMBL Master Bidder List.MLBSMMBM Marketing Budget ModelsMBO Management By Objectives.MLBSMMBO Miscellaneous Blanket OrderMBOM Manufacturing Bill Of Materials TechCtrMbps Megabits per second.MLBSM, TechCtrMBps Mega Bytes per SecondMBT Minimum (spark advance) for Best Torque TechCtrMC Manufacturing Change TechCtrMC Match Check.MC Math Check MLBSMMCA Micro Channel ArchitectureMCAE Mechanical Computer Aided Engineering.MLBSMMCARS Motor Carrier Accident Reporting SystemMCAS Medical Committee on Automotive Safety TechCtrMCBF Mean Cycles Between Failures (in terms of job cycles. The average number of jobs thestation/cell produces between equipment failures. Includes over-cycles, run time failures.Jobs produced / Failures [downtime] [Simulation & Throughput Definitions])MCD Material Completion Date MLBSMMCD Midsize Car Division (no longer used).MLBSM, TechCtrMCE Mid Cycle Enhancement.GVDP, ENG, GEBFWC,TechCtr, GMPTMCE1Mid-Cycle Enhancement level 1. Minor changes from previous model GEBFWCMCE2Mid-Cycle Enhancement level 2. Significant changes except sheet metal GEBFWCMCE3Mid-Cycle Enhancement level 3. Significant changes with sheet metal.GEBFWCMCFC Molten Carbonate Fuel Cell TechCtrMCM Multi Chip ModuleMCN Material Complaint Notice.MLBSMMCNS Multimedia Cable Network System TechCtrMCR Material Cost Reduction.MLBSMMCR Maximum Capacity Rate (The planned maximum capacity requirement including overtime,GMPTalternative work arrangements, etc.)MCREGIS Motor Carrier Regulations Information SystemMCRL Material Cost Reduction List.MLBSMMCS Manufacturing Content Sheet (provides a high level directional capital forecast based on the"change impact" of a new entry allocation.)MCSE Microsoft Certified Systems EngineerMCU Memory Combo Unit.MLBSMMCU Microprocessor Control Unit.PSEO, TechCtrMCXO Microprocessor Controlled Crystal Oscillator TechCtrMd MendeleviumMD Manual Disconnect TechCtrMD Manufacturing Development.MLBSMMD Medium Duty.MLBSM, TechCtrMD Mini Disk PSEOMD Module Duct. (Air Distribution )MLBSMMD Music Disk.MDA Multiple Dealer Area MLBSMMDAI Multi Disciplinary Accident InvestigationMDB Moving (or Movable) Deformable BarrierMDBS Mobile Data Base StationMDC Model Code.MDD Master Datum Drawing GVDP, TechCtrMDDA Modulated Displacement Driver Assembly.MLBSMMDH Major Department Head.MLBSMMDI Motor Drive Interface.TechCtrMDM Market Dynamics Model TechCtrMDOT Michigan Department Of TransportationMDRAM Multibank Dynamic Random Access Memory TechCtrMDRE Mfg. Design Responsible Engineer TechCtrMDX Mini Disk Changer.PSEOME Manufacturing Engineer(ing)GEDOC, GMPT, GEBFWC,TechCtrME Mechanical Engineer(ing).ME&D Manufacturing Engineering & Development.MLBSMMEA Membrane Electrode Assembly TechCtrMEC Manufacturing Engineering ControlMECE Mutually Exclusive, Collectively Exhaustive TechCtrMed Medium (an abbreviation)PSEOMEEL Master Engineering Events ListMEGR[vacuum] Modulated Exhaust Gas Recirculation (Diesel)MLBSMMEGR/EPR Vacuum Modulated EGR w/EPR (Diesel).MLBSMMem Memory (an abbreviation)PSEOMEMA Motor & Equipment Manufacturers Association.MLBSM, TechCtrMEMS Micro Electro Mechanical Systems (Chip level electromechanical devices - currentautomotive accelerometers and yaw-rate sensors are manufactured using MEMStechnology.)MEO Mutually Exclusive Option MLBSMMEO&I Manufacturing Engineering Operations & Integration GEDOC, GEBFWC, TechCtr MeOH Methanol TechCtrFIN, ILMMERS Management Evaluation and Representation Statement. An annual document which fulfillstwo functions: (1) an attestation by local management as to the status of the internal controlenvironment at the unit, and (2) a confirmation by management that the trial balance andsupporting schedules have been prepared in conformance with U. S. Generally AcceptedAccounting Principles (U.S. GAAP) and all accounting policies and procedures established inthe Financial Policies Series, Corporate Policy Manual and Comptroller's Circular Letters.MES Marketing Education Services.MLBSMMESFET MEtal Semiconductor Field Effect Transistor TechCtrMESI Modified Exclusive Shared Invalid TechCtrMESS Modulated EGR Spark Signal.MLBSMMetrics.The six categories used to measure a process: quality, cost, timing, throughput, workload,MLBSMand environment.METT Manufacturing Engineering Task Team TechCtrMF Medium Frequency TechCtrMFAD Material Final Approval DateMFC Material Flow CoordinatorMFD Metal Fabrication Division.GVDP, MFD, EAG, GEBFWC,TechCtrMFD Micro Farad (capacitance)MFG Manufacturing OperationsMFG Manufacturing/Manufacturer.GVDP, MLBSM, TechCtrMFI Micro Fuel Injector TechCtrMFI Multiport Fuel Injection.PSEO, MLBSM, GMPTMFLOPS Millions of Floating Operations Per SecondMFMEA Machinery Failure Mode and Effects Analysis GMPTMFN Most Favored Nation TechCtrMFS Material Flow SupportMg MagnesiumMg milligrams TechCtrMG Morris Garages. A British manufacturer of vehicles.MGM Motors, Generators, Mangnequench TechCtrMgmt Management (an abbreviation)PSEOMGO Material Global Optimization (assembly plant scheduling system)GEDOC, FIN, GMPT, EAG,GEBFWC, TechCtrMGO Asm.NAO GM Assembly (formerly ISP)GMPT, EAGMGO Cmpnt NAO GM Component (formerly MSS)GMPTMGR Mobile Ground RadarMGVMR Maximum Gross Vehicle Mass Rating.MH10See ASC MH10.AIAGMHC Medium Heavy Coach MLBSMMHD Magneto Hydro DynamicMHD Motors Holding Division TechCtrMHDID Motors Holding Dealer Information Database MLBSMMHE Material Handling Engineering.MLBSMMHI Material Handling Institute.AIAGMHS Manifold Heat ShieldMHz Megahertz (1,000,000 Cycles per second)MLBSM, TechCtrmi Miles.TechCtrMIA Missing In ActionMIB Medical Information Bus TechCtrMIC Marketing Information Center.GVDP, TechCtrMLBSMMIC Material & Inventory Control system. A centralized computer system for orderingexperimental parts and maintaining stockroom inventory. (Being replaced by EMS andEMBASSY.).MIC Motorcycle Industry Council.MLBSMMIC Motors Insurance Corporation.MLBSM, TechCtrMICR Magnetic Ink Character Recognition.MLBSMMICRO Microcomputer.MLBSMMid Midrange (an abbreviation)PSEOMID / LUX Midsize and Luxury Car Group. Obsolete; now VEC.MLBSMMIDAS Management Information Disbursement Analysis System.MLBSMMIDB Manufacturing Information Database MLBSMMIDI Musical Instrument Digital Interface (Also a sound file used on web pages to providebackground sound or links to MIDI sound files.)MIE Manufacturing Integration Engineer.GVDP, TechCtrMIFF MADYMO Input File FormatMIG Magnesium Inert Gas.MLBSMMIG Metal Inert GasMII Motorists Information, Inc.MLBSMMIL Malfunction Indicator Lamp.PSEO, TechCtr, GMPT MIMD Multiple Instruction stream, Multiple Data streamMIME Multipurpose Internet Mail Extensions (The standard for attaching non-text files to standardInternet mail messages. Non-text files include graphics, spreadsheets, formatted word-processor documents, sound files, etc.)MIMIC MIcrowave/millimeter wave Monolithic Integrated Circuit (Directed by the U.S. Department ofDefense, the MIMIC program was established to enhance producibility and reduce theproduction cost of gallium arsenide (GaAs) microwave integrated circuits.)Min Minute (an abbreviation)PSEOMIN Mobile Identification Number.PSEOMINLODE Minimize Load Delay. System to align car orders for delivery.MLBSMMIOSHA Michigan Occupational Safety & Health AdministrationMIPS Million Instructions per second MLBSM, TechCtr MIRA Motor Industry Research Association.MLBSMMIRS Material Inventory Record System.MLBSMMIS Manufacturing Information System GMPTMIS Management Information System.MLBSMMIS Months In Service GMPTMISAR Micro-Processed Sensing & Automatic Recognition MLBSMMISC Mechanical Idle Speed Control.MLBSMMISS Monolithic Integrated Smart SensorMIT Manufacturing Integration Team.MIT Marketing Integration TeamMIT Massachusetts Institute of Technology.MLBSMMITI Ministry for International Trade & Industry (Japan)TechCtrMIW Manufacturing Integration Wall.GVDP, TechCtr, GMPT MKT Marketing TechCtrMLBS Material Labor Balance System.GVDP, TechCtrMLCG Mid/Lux Car Group (no longer used).MLPS Machine Loading & Planning System MLBSMMLS Material Location System.MLBSMMLSA Management Leadership Systems Approval GMPTmm Millimeters.MLBSMMM Material Management.MLBSMmm3cubic millimeter PSEOMMC Manufacturing Managers Council.MLBSM, TechCtrMMC Metal Matrix Composites TechCtrMLBSM, TechCtr, GMPT MMDB Material Management Database (is a corporate-wide computer system that processes thelatest engineering intent data from GPDS as well as, tooling and scheduling forecast datafrom POMS.)MMES Martin Marietta Energy Systems - Oak Ridge TechCtrMMF Make Money Fast (Generic name for any of the useless, futile, and often illegal pyramidschemes that promise to "make $5 into $50,000" or "GET RICH QUICK")mmhg millimeters of Mercury PSEOMMI Man Machine InterfaceMMIC Monolithic Microwave Integrated Circuit [Combining active elements (diodes and transistors)TechCtrwith passive elements (resistors, capacitors, inductors and transmission lines) on a singleGaAs (gallium arsenide) substrate.]MMIS Maintenance Management Information System.MLBSMMMM Memory Mirror Module.PSEOMMQC Material Management Quality Council.MLBSMMMQIT Material Management Quality Improvement Team.MLBSMMMR Minimum Mandatory Requirements GEDOC, GEBFWC, TechCtr MMS Maintenance Management SystemMMSTS Manufacturing Major Subsystem Technical Specifications.GVDP, TechCtr, GMU, GMPT MMT Methyl_cyclo_penta_diethyl_Manganese_Tricarbonyl.TechCtrMMTC Michigan Manufacturing Technology Center - A not-for-profit organization in Ann Arbor,AIAGMichigan dedicated to determining how to use technology to help improve industrialmanufacturers their operations.MMTF Mean Miles To Failure.TechCtrMMTS Materials Management Technical Specifications TechCtrMMU Memory Management Unit TechCtrMMUCC Model Minimum Uniform Crash Criteria (A voluntary set of guidelines that help states collectconsistent, reliable crash data that are more effective for identifying traffic safety problems,establishing goals and performance measures, and monitoring the progress of programs.)MMX Multi Media eXtensionsMn ManganeseMLBSM, TechCtr MNG A functional designation that represents Manufacturing Engineering. Statements of Work(SOW's) with this designation describe the manufacturing functions of tool and equipmentrequirements, design, construction, and installation.MNOS Metal Nitride Oxide Semiconductor TechCtrMNP Microcom Network Protocol. A data compression standard for modems.Mo MolybdenumMO Magneto OpticalMO Model Office TechCtrMOC Method of Control.MLBSMMod Module (an abbreviation)PSEOMOD Modulator (abbreviation)GMPTMODE Mission Objective Design Elements.MLBSM MODEM Modulator-Demodulator.MLBSM, TechCtr MOE Measure of EffectivenessMOEMS Micro Optical Electro Mechanical SystemMOFTEC China's Ministry of Foreign Trade and Economic Cooperation TechCtrMon Monitor (an abbreviation)PSEOMON Motor Octane Number.MLBSMMOO Mud, Object Oriented (One of several kinds of multi-user role-playing environments, so faronly text-based.)MOOSE Method for Object-Oriented Software EngineeringMOP Model Option PlanningMOPB Metallic Organic Petroleum Base (Anti-Corrosion).MLBSMMOPS Mega (million) Operations Per Second TechCtrMOS Manufacturing Operations Staff TechCtrMOS Metal Oxide Semiconductor.MLBSM MOSES Model Option Statement Expert System.MLBSM MOSFET Metal Oxide Semiconductor Field Effect Transistor.MLBSM, TechCtr MOSIGT Metal Oxide Semiconductor Insulated Gate Transistor TechCtrMOT Ministry Of Transport TechCtrMOU Memorandum Of Understanding.TechCtrMOV Metal Oxide Varistor TechCtrMOV Minimum Operating Voltage TechCtrMOV Multi Occupant VehicleMOVE Movement of Vehicular Equipment.MLBSMMOW Maintenance Operation Window. Mutually agreed on daily contiguous period during whichEDS may perform backups and other system administration services.MOWAG Motorwagenfabrik AG. In Kreuzlingen, Switzerland.MP Manufacturing Plan TechCtrMPa Mega Pascals MLBSMMPCE Material Production Control Europe GMPTMPCF Manufacturing Process Changes Frozen. To mark that point in time at which allmanufacturing process changes are frozen and after which no new changes will beaccepted.GVDP, TechCtr, GMPTMPEG Moving Pictures Expert Group. An international standard for video compression and desktopmovie presentation. Special viewing application is needed to run MPEG files on computer.TechCtrMPFI Multi-Port Fuel Injection.MLBSM, TechCtrMPG Miles Per Gallon. (VTS signifies small case, ie, mpg, to differeniate from Milford Proving Grounds)PSEO, VTS, GMPT, MLBSM, TechCtrMPG Milford Proving Ground.VTS, GVDP, GEBFWC,MLBSM, TechCtrMPG EFEO Milford Proving Grounds Emissions and Fuel Economy Operations GMPTMPH Miles Per Hour.PSEO, MLBSM, TechCtr MPH Monthly People Hours (We "Go Fast" by reducing MPH.)MPI Master Process Index.GVDP, TechCtrMPI Multi-Point (or Port) Injection.MLBSMMPL Master Parts List.GVDP, MLBSM, TechCtr,GMPTMPMP Manufacturing Portfolio Management ProcessMPO Modular Power Options.MLBSMMPP Market & Product PlanningMPR Manufacturing Planning Release.MLBSMMPR Minimum Performance Requirement.MLBSMMPS Manifold Pressure Sensor.MLBSMMPS Manufacturing Planning Staff.MLBSMMPS Master Planning System GVDPMPS Material Planning System.TechCtrMPS Material Pull System TechCtrMPS Metal Parts Specifications.MLBSMMPSC Manufacturing Portfolio Strategy CouncilMPSDC Master Publication Structure Definition CoordinatorMPTT Marketing Planning Task Team TechCtrMPU Micro Processor Unit MLBSM, TechCtrMPV Multi-Purpose Vehicle.VTS, MLBSM, TechCtrMQ Machine Qualification TechCtrMQ Magnequench TechCtrMQFP Metal Quad Flat Pack (IC package type)TechCtrMQM Manufacturing Quality MeasurementsMR Magneto Resistive TechCtrMR Material Release.MLBSMMR Material Requisition.MLBSMMR Material Return. The material returned to the PDC to be charged against dealers returnreserve.MRA Modular Reservoir Assembly TechCtrMRD Magnetic Rotation Device.TechCtrMRD Mandatory Required DateMRD Manual Release DateMRD Material Required Date (s).GMPT, GVDP, MLBSM,TechCtr, GMUMRD Model Release DateMRE Manufacturing Responsible Engineer GMPTMRF Manufacture Response Form.VSSMMRG Micro Ring Gyro (MEMS tuning fork gyro from Micro Sensors)MRI Magnetic Resonance Interferometer.MLBSMMRI Midwest Research Institute TechCtrAIAG, TechCtrMRO Maintenance, Repair, and Operation supplies. Purchased items not included into the finishedproduct.MROS Maintenance Repair Operating SuppliesMRP Material Requirement Planning.MLBSM, TechCtrMRP Mechanical Repair Protection.MRPS Metal Removal Process Simulation GEDOC, GEBFWC, TechCtr MRR Materials Reservation Report (EMS System).MLBSMMRT Material Requirement Transfer TechCtrMRT Material Routing Tag.MLBSMms Milliseconds.MLBSMMS Manufacturing Sales.MLBSMMS Memo Supplement.MLBSMMS MicrosoftMS Military Standard.MLBSMMS Multi-Skilled TechCtrMS/SE Major Subsystem Engineer. The person on the vehicle platform team managing therequirements of a major subsystem.MSA Measurement Systems Analysis. A procedure for assessing the quality of a measurementAIAG, MFD, MLBSM, GMPT system as agreed to by DaimlerChrysler, Ford and GM.MSAP Measurement System Analysis Plan TechCtrMSAPC Mobile Source Air Pollution Control.MLBSMMSB Most Significant Bit TechCtrMSB Most Significant ByteMSC Management Steering Committee GMPTMSDS Material Safety Data Sheet GVDP, TechCtrMSE Manufacturing Systems Engineer GVDP, TechCtrMSEC,ms Millisecond.MLBSMMSED Mobile Sources Enforcement Division (EPA).MLBSMMSF Motorcycle Safety Foundation.MLBSMMsg Message (an abbreviation)PSEOMSI Medium Scale Integration.MLBSM, TechCtrMSK Minimum Shift Keying.MLBSMMSL Mean Sea Level.VTSMSL Medium speed Serial data Link TechCtrMSM Memory Seat Module.PSEOMSNF Multi System Network Facility.MLBSMMSO Manufacturing Stop Order TechCtrMSO Mixed Signal Oscilloscope TechCtrMSOP Micro Small Outline Package (IC package type)TechCtrMSP Mixed Signal Processing TechCtrMSPC Manufacturers Standard Paint Color.MLBSMMSRP Manufacturer’s Suggested Retail Price.MLBSM, TechCtr, VSSMMSS Market Segment Specifications. A marketing division’s description of a specific market segment as defined by the Corporate Market Needs Segmentation Analysis. Providesinformation on the voice of the customer, prioritization of customer needs, competitors andbusiness conditions for the segment. MSS is a statement of the program problem andconstraints. VTS provides the definition of the vehicle as a solution to this problem.VTS, GVDP, MLBSM, TechCtr, GMU, GMPTMSS Marketing Support ServicesMSS Materials Scheduling System. The predominant material scheduling system in use by NAO. .TechCtr, GMPTMSS Minimum Steering Sensitivity.VTSMSS Mortality Surveillance System.MLBSMMSSE Major Subsystem Systems EngineerMSSE Manager Sub System Engineer.MLBSMMSSE Mechanical Sub Systems Engineering.MSTS Major Subsystem Technical Specifications.MLBSMMSU Model Start Up.MLBSMMSV Measurement Systems Variation.MLBSMMSVA Magnetic Speed Variable Assist steering (Magna Steer).MLBSMMSVA Magnetic Steering Variable Assist.PSEOMSW Multi-sheet Scorecard Workbook TechCtrMSZH1Magyar SZabvanyugi Hivatal TechCtrMT Manual Transmission. (Normally written as M/T)MLBSM, GMPTMT Military Trucks GM DefenseMTA Manual Transmission Autoshift (Europe)GMPTMTA Message Transfer Agent. An MTA transfers mail between two dissimilar mail systems suchas Internet mail and Notes mail.MTBE Methyl Tertiary-Butyl Ether.TechCtrMTBF Mean Time Between Failure.GVDP, MLBSM, TechCtr MTC Manufacturing Technical Council.MLBSM, TechCtrMTC Manufacturing Technology CenterMTC Merchandising Transmission Condition.MLBSMMTC Motors Trading Corporation.MLBSMMTD Machine & Tool Design (DFM [Design for Manufacturability] software tool that is used duringthe design and development of equipment to help reduce parts and simplify designs. MTDfocuses on simplifying machine and tool design without compromising functionalrequirements.)MTD Month To Date FIN, TechCtrMTE Measurement & Test Equipment TechCtrMTL Master Test List. The corporate listing of test procedures used within NAO.VTS, A/D/V MTO Master Terminal Operator.MLBSM MTO Microelectronics Technology OfficeMTP Manufacturing Test Plan TechCtr MTP Master Test Plan.MTPI Multi-Phase Test Point Insertion TechCtr Mtr Motor (an abbreviation)PSEO MTR Manually Tuned Radio.MLBSMMTS Manufacturing Technical Specification. Defines requirements for a manufacturing system, the validation methods, major subsystems and subsystem interfaces.GEDOC, GVDP, GMPT, MLBSM, GEBFWC, TechCtr, GMUMTSO Mobile Telephone Switching OfficeMTT Manufacturing Task Team TechCtrMTTF Mean Time To Failure.MLBSMMTTR Mean Time To Repair.MLBSMMTV Message Translation & ValidationMU Mock-Up. Mock-ups can be actual functioning parts, sub-assemblies or assemblies or non-functional wood, expanded polystyrene, plastic or metal representations of parts,subassemblies or assemblies. The design source can be responsible for providing mock-ups.MLBSM, MLBSMMUD Multi User Dungeon / Dimension (A multi-user simulation environment.)Mult Multiple (an abbreviation)PSEO MULTICS MULTiplexed Information and Computing Systems TechCtr MUMPS Multi User MEMS ProcessMUSE Multi User Simulation Environment (One kind of MUD)MUST Management and Union Serving Together.GMUMUTCD Manual on Uniform Traffic Control DevicesMux Multiplex(-ing, -or) (an abbreviation)PSEO, TechCtr MVA Master Vehicle AssemblyMVA Modulated Vacuum Advance.MLBSMMVDP Motor Vehicle Dimensions Procedures.VTSMVEG Motor Vehicle Emissions Group TechCtrMVEL Milford Vehicle Emissions Laboratory MLBSM, TechCtr MVMA Motor Vehicle Manufacturers Association.MLBSM, TechCtr MVNS Manufacturing Validation Non-Saleable TechCtrMVO Military Vehicle Operations.MVP Master Validation Plan. A system designed to report a list of standardized validation tests ofproduction intent vehicles/systems prior to start of production. .MLBSMMVS Manufacturing Validation Saleable TechCtrMVS Multiple Virtual Storage.MLBSMMVS TCP/IP TCP/IP for MVS.MLBSMMVS/XA Multiple Virtual Storage / Extended Architecture MLBSMMVSA Manufacturing Vehicle Section Advisor GEDOC, GEBFWC, TechCtr MVSR Math-based Vehicle Sections Repository (GM's corporate repository for sharing andpreserving vehicle sections throughout the corporation.)MVSR Motor Vehicle Safety Regulation VTSMVSS Motor Vehicle Safety Standards (of Transport Canada), a.k.a. CMVSS or NSVAC in French.MLBSMMVSS Motor Vehicle Safety Standards. Specific requirements regarding the US. MVSS and Regulations, and Information and Cost Saving Act that relate to vehicles GM manufactures.VTS, GVDP, GMPT, MLBSM, TechCtrMVTT Message Verification Test Tool (C2C)MVZ Manifold Vacuum Zone.MXI Multiplatform eXtensions for Instrumentation TechCtrMY May.MLBSMMY Model Year.MLBSM, TechCtr MYM Model Year Manager.MLBSMMYTD Model-Year-To-Date FIN, TechCtr。

以太网链路连接

2.2.4 100Base-FX(Fiber Interface) to RGMII
2.2.5 10/100/1000Base-T to SGMII
2.2.6 100Base-FX(Copper Interface) to SGMII
2.2.7 1000Base-T to 1000Base-X(SerDes) (GBIC)
0参考文档1规范标准11接口接口名称位置速率规范备注miiswitchmac100rmiiswitchmac100rvmiiswitchmac100gmiiswitchmac1000rgmiiswitchmac1000tbiswitchmac1000rtbiswitchmac1000sgmiiswitchmac1000serdesswitchmac1000serdespassthroughswitchmac1000101001000basetmedia101001000copper100basefxmedia100serdesmedia1000fiber1000basetmedia10001000basexmedia10001000basecxmedia10001000basecxoverspeciallyshielded150balancedcopperjumpercableassembliesieee8023clause391000basekxmedia1000ieee8023apphysicallayerspecificationgbsusing1000basexencodingoverelectricalbackplaneieee8023clause701000basebxmedia1000picmg31electricalspecificationgbsethernetgbsfibrechannelencodeddataoverbackplane10gbasexmedia10000ieee8023physicalcodingsublayer10gbsoperationoverxauifourlanepmdsperieee8023clause4810gbasecx4media10000ieee8023physicallayerspecification10gbsusing10gbaseencodingoverfourlanes100shieldedbalancedcoppercablingieee8023clause5410gbasekx4media10000ieee8023apphysicallayerspecification10gbsusing10gbasexencodingoverelectricalbackplaneieee8023clause7110gbasebx4media10000picm

QSGMII协议详解ppt课件

19
自协商过程
20
有序集/I/
当GMII上没有数据传输的时候，链路也不能空闲，而是传输一些不代表任何实际意义的比特位，这样可以保持两端时钟的同步，并使链路保持在激活状态。组成这些空闲比特位的为有序集/I/，链路两端的设备在接收到/I/后，仅仅忽略，但如果一段时间内没有接收到数据，同时接收不到/I/有序集，则认为链路故障。
8B/10B编码避免了5个连续的“0”或者“1”出现。并且还可以使接收端从数据中有效地提取时钟。
4
编码原理
8bit原始数据会分成两部分，其低5位会进行5B/6B编码，高3位则进行 3B/4B编码，这两种映射关系有一个标准化的表格。对于8bit信号作为一个数据群码时用Dx.y表示，作为特殊群码时用Kx.y表示，其中x是EDCBA 的十进制值，y是HGF的十进制值。例如，一个8bit数据码 110 11101 表示为D29.6。
13
有序集
14
有序集/C/
有序集/C/是用作自协商寄存器配置的标识码，在有序集后的 16比特数即为寄存器值。有序集/C/分为/C1/和/C2/；/C1/定义为/K28.5/D21.5/，/C2/定义为/K28.5/D2.2/。/C1/的前后极性翻转，/C2/的前后极性保持。
15
有序集/C/
5
5B/6B编码表
input EDCBA
D.00 00000 D.01 00001 D.02 00010 D.03 00011 D.04 00100 D.05 00101 D.06 00110 D.07 00111 D.08 01000 D.09 01001 D.10 01010 D.11 01011 D.12 01100 D.13 01101 D.14 01110 D.15 01111

gig_eth_mac模块的说明

© 2004-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. Allother trademarks are the property of their respective owners.IntroductionThe LogiCORE™IP 1-Gigabit Ethernet Media Access Controller (GEMAC) core supports full-duplex opera-tion at 1 Gigabit per second (Gbps), and can be used with all Gigabit Ethernet Physical Coding standards.Features•Designed to IEEE 802.3-2002 specification •Single-speed 1-Gbps Ethernet Media Access Controller (MAC)•Full-duplex operation•Internal GMII physical-side interface (PHY) that can be connected to -An embedded PHY core, such as the Xilinx Ethernet 1000BASE-X PCS/PMA or SGMII core or other custom logic -IOBs to provide an external GMII-A shim that includes DDRs and DCMs to provide an external RGMII•Configured and monitored through an optional independent microprocessor-neutral interface •Interfaces directly to the Xilinx Ethernet Statistics core for powerful statistics gathering •Configurable flow control through MAC control pause frames; symmetrically or asymmetrically enabled •Optional MDIO interface to managed objects in PHY layers (MII Management)•Optional Address Filter with a selectable number of Address Table entries •Support of VLAN frames to specification IEEE 802.3-2002•Configurable support for jumbo frames of any length •Configurable in-band FCS field passing on both transmit and receive paths •Available under the terms of the SignOnce IP License1-Gigabit Ethernet MAC v8.4DS200 March 24, 2008Product SpecificationLogiCORE IP FactsCore SpecificsSupported FPGA FamilyVirtex™-5,Virtex-4,Virtex-II Pro,Virtex-II,Spartan™-3,Spartan-3E,Spartan-3A/3AN/3A DSP 1Speed Grade• -1 for Virtex-5•-4 for Virtex-II, Spartan-3,Spartan-3E,Spartan-3A/3AN/3A DSP• -5 for Virtex-II Pro • -10 for Virtex-4Performance1 GbpsCore ResourcesSlices 372-6082 or 585-10233LUTs 623-9552 or 763-12493FFs 651-10232 or 646-10653DCM 0-23BUFG2-73Core HighlightsDesigned to IEEE 802.3Simulation Only EvaluationHardware VerifiedHardware Evaluation Provided with CoreDocumentation Product Specification Getting Started GuideUser GuideDesign File Formats NGC Netlist,HDL Example Design,Demonstration Test Bench,ScriptsConstraints File User Constraints File (.ucf)Demo Example Designs1-Gigabit Ethernet MAC with GMII 1-Gigabit Ethernet MAC with RGMIIDesign Tool RequirementsSupported HDL VHDL and/or VerilogSynthesis XST 10.1Xilinx T ools ISE™10.1Simulation T oolsModelSim®v6.3c Cadence® IUS v6.1Synopsys® vcs_mxY-2006.06-SP141.See Table 19 for supported family configurations.2.Virtex-5 FPGA slices and LUTs are different from previous families.See Tables 20 and 21.3.See Tables 20 and 21; the precise number depends on user configu-ration.4.Scripts provided for listed simulators only.ApplicationsTypical applications for the GEMAC core include:•Ethernet 1000BASE-X Port•Ethernet 1000BASE-T PortEthernet 1000BASE-X PortFigure1 illustrates a typical GEMAC application. The PHY side of the core is connected to internallyintegrated 1000BASE-X logic using the Virtex-II Pro RocketIO™ Multi-Gigabit Transceiver (MGT) toconnect to an external off-the-shelf GBIC or SFP optical transceiver. The 1000BASE-X logic can be pro-vided by the Ethernet 1000BASE-X PCS/PMA or SGMII cores.The client side of the core is shown connected to the 10Mbps, 100 Mbps, 1 Gbps Ethernet FIFO, deliv-ered with the GEMAC core to complete a single Gigabit Ethernet port. This port is shown connected toa Switch or Routing matrix, which may contain several ports.Figure 1: Typical GEMAC 1000BASE-X Application DS200 March 24, 20081-Gigabit Ethernet MAC v8.4Ethernet 1000BASE-T PortFigure2 illustrates a typical application for the GEMAC core. The PHY side of the core is implementing an external GMII by connecting it to IOBs. The external GMII is connected to an off-the-shelf Ethernet PHY device, which performs the 1000BASE-T standard. Alternatively, the external GMII may be replaced with an RGMII using a small logic shim. HDL example designs are provided with the core to demonstrate external GMII or RGMII.The client side of the core is shown connected to the 10 Mbps, 100 Mbps, 1 Gbps Ethernet FIFO, deliv-ered with the GEMAC core, to complete a single Gigabit Ethernet port. This port is shown connected to a Switch or Routing matrix, which may contain several ports.Figure 2: Typical GEMAC 1000BASE-T ApplicationEthernet Architecture OverviewThe GEMAC sublayer provided by this core is part of the Ethernet architecture illustrated in Figure3.The part of this architecture from the MAC to the right is defined in IEEE 802.3 specification. Figure3also illustrates where supported interfaces fit into the architecture.Figure 3: Typical Ethernet ArchitectureMACThe Ethernet Media Access Controller (MAC) is defined in the IEEE 802.3 specification, in clauses 2, 3,and 4. A MAC is responsible for the Ethernet framing protocols and error detection of these frames. TheMAC is independent of, and can connect to, any type of physical layer device (PHY).GMIIThe Gigabit Media Independent Interface (GMII) is defined in IEEE 802.3, clause 35. This is a parallelinterface connecting a 1 Gigabit-capable MAC to the physical sublayers (PCS, PMA, and PMD).RGMIIThe Reduced Gigabit Media Independent Interface (RGMII) is an alternative to the GMII. RGMIIachieves a 50% reduction in the pin count compared with GMII, and is therefore favored over GMII byPCB designers. This is achieved with the use of double-data-rate (DDR) flip-flops.No change in the operation of the core is required to select GMII or RGMII. However, the clock man-agement logic and IOB logic around the core does change. HDL example designs are provided with thecore to implement either the GMII or RGMII protocols.SGMIIThe Serial-GMII (SGMII) is an alternative interface to the GMII that converts the parallel interface of theGMII into a serial format. This radically reduces the I/O count and is therefore often favored by PCBdesigners.The GEMAC core can be extended to include SGMII functionality by internally connecting its PHY-sideGMII to the Ethernet 1000BASE-X PCS/PMA or SGMII core. See the 1-Gigabit Ethernet MAC User Guidefor more information.PCS, PMA, and PMDThe combination of the Physical Coding sublayer (PCS), the Physical Medium Attachment (PMA), andthe Physical Medium Dependent (PMD) sublayer constitute the physical layers for the protocol. Twomain physical standards are specified for Gigabit Ethernet:•1000BASE-X (defined in IEEE 802.3, clauses 36 to 39), provides short and long wavelength laser and short haul copper interfaces•1000BASE-T, (defined in IEEE 802.3 clause 40), provides twisted-pair cabling systems DS200 March 24, 20081-Gigabit Ethernet MAC v8.4The 1000BASE-X architecture illustrated in Figure 1 can be provided by connecting the GEMAC core to the Ethernet 1000BASE-X PCS/PMA or SGMII core. See the 1-Gi gabi t Ethernet MAC User Gui de for details . The 1000BASE-T architecture illustrated in Figure 2 can be provided with the use of an external 1000BASE-T capable PHY device.Core OverviewFigure 4 shows the major functional blocks and interfaces of the GEMAC core. Descriptions of these functional block and interfaces, along with associated signals are provided in the sections that follow.Transmit EngineThe Transmit Engine accepts Ethernet frame data from the Client Transmitter Interface, adds the pre-amble field to the start of the frame, adds padding bytes if required (to ensure that the frame meets the minimum frame length requirements), and then adds the frame check sequence (when configured to do so). In addition, the transmitter is responsible for ensuring that the interframe spacing between suc-cessive frames always meets the minimum specified. The frame is then converted into a format com-patible with the GMII and sent to the GMII Block.Figure 4: GEMAC Functional Block DiagramDS200 March 24, 2008Client Transmitter Interface SignalsTable 1 defines the GEMAC core client-side transmitter signals. These signals are used to transmit data from the client logic into the GEMAC core. See the 1-Gigabit Ethernet MAC User Guide for more infor-mation.Client Transmitter Interface OperationFigure 5 illustrates the timing of a normal outbound frame transfer. When the client initiates a frame transmission, it places the first column of data onto the tx_data port and asserts a logic 1 onto tx_data_valid .After the GEMAC core reads the first byte of data, it asserts the tx_ack signal. On the next and subse-quent rising clock edges, the client must provide the remainder of the data for the frame. The end of frame is signaled to the GEMAC core by taking tx_data_valid to logic 0.T able 1: Transmitter Client Interface Signal PinsSignal DirectionClock DomainDescriptiongtx_clk Input n/aClock signal provided to the core at 125 MHz. T olerance must be within IEEE 802.3-2002specification. This clock signal is used by all of the transmitter logic.tx_data[7:0]Input gtx_clk Frame data to be transmitted is supplied on this port.tx_data_valid Input gtx_clk Control signal for tx_data port.tx_ifg_delay[7:0]Input gtx_clk Control signal for configurable Inter Frame Gap adjustment.tx_ack Output gtx_clk Handshaking signal asserted when the current data on tx_data has been accepted.tx_underrunInput gtx_clk Asserted by client to force MAC core to corrupt the current frame.tx_statistics_vector[21:0]Output gtx_clk Provides statistical information on the last frame transmitted.tx_statistics_validOutputgtx_clkAsserted at end of frame transmission, indicating that the tx_statistics_vector is valid.1-Gigabit Ethernet MAC v8.4Receive EngineThe Receive Engine accepts Ethernet frame data from the GMII Block, removes the preamble field at the start of the frame, and removes padding bytes and frame check sequence (if required and when configured to do so). In addition, the receiver is responsible for performing error detection on the received frame using information that includes the frame check sequence field, received GMII error codes, and legal frame size boundaries.Client Receiver Interface SignalsTable2 defines the GEMAC core client-side receiver signals. These signals are used by the GEMAC core to transfer data to the client. For a complete description, see the 1-Gigabit Ethernet MAC User Guide.Figure 5: Normal Frame Transmission Across Client InterfaceTable 2: Receive Client Interface Signal PinsSignal DirectionClockDomainDescriptionrx_data[7:0]Output gmii_rx_clk Frame data received is supplied on this port. rx_data_valid Output gmii_rx_clk Control signal for the rx_data port.rx_good_frame Output gmii_rx_clk Asserted at end of frame reception to indicate that the frame should be processed by the MAC client.rx_bad_frame Output gmii_rx_clk Asserted at end of frame reception to indicate that the frame should be discarded by the MAC client.rx_statistics_vector[26:0]Output gmii_rx_clk This provides statistical information on the last frame received.rx_statistics_valid Output gmii_rx_clk Asserted at end of frame reception, indicating thatthe rx_statistics_vector is valid.DS200 March 24, 2008Client Receiver Interface OperationFigure 6 illustrates the timing of a normal inbound frame transfer. The client must be prepared to accept data at any time; there is no buffering within the GEMAC to allow for latency in the receive cli-ent. After frame reception begins, data is transferred on consecutive clock cycles to the receive client until the frame is complete. The GEMAC asserts the rx_good_frame signal to indicate that the frame was successfully received and that the frame should be analyzed by the client.Flow ControlThe Flow Control block is designed to clause 31 of the IEEE 802.3-2002 standard. The GEMAC may be configured to send pause frames and to act upon their reception. These two behaviors can be config-ured asymmetrically. See the 1-Gigabit Ethernet MAC User Guide for more information . Flow Control Interface SignalsTable 3 defines the signals used by the client to request a flow-control action from the transmit engine.Transmitting a PAUSE Control FrameThe client initiates a Flow Control frame by asserting pause_req for a single clock period while the pause value is on the pause_val[15:0] bus. If the GEMAC core is configured to support transmit flow control, this action causes the core to transmit a PAUSE control frame on the link, with the PAUSE parameter set to the value on pause_val[15:0] in the cycle when pause_req was asserted. This does not disrupt any frame transmission in progress, but takes priority over any pending frame trans-mission. This frame will be transmitted even if the transmitter is in a paused state.Figure 6: Normal Frame ReceptionT able 3: Flow Control Interface Signal PinoutSignalDirectionClock DomainDescriptionpause_req Input gtx_clk Pause request Sends a pause frame down the link.pause_val[15:0]Inputgtx_clkPause value Inserted into the parameter field of the transmitted pause frame.1-Gigabit Ethernet MAC v8.4Receiving a Pause Control FrameWhen an error-free frame is received by the GEMAC core, it is evaluated in the following way:1.The destination address field is matched against the MAC Control multicast address or theconfigured source address for the MAC.2.The length/type field is matched against the MAC Control Type code.3.If number 2 is true, the opcode field contents are matched against the PAUSE opcode.If any of the previously listed conditions are false, or the MAC Flow Control logic for the receiver is dis-abled, the frame is ignored by the Flow Control logic and passed to the client with rx_good_frame asserted for interpretation.If the frame passes all of the previously listed conditions, is of minimum legal size, and the MAC Flow Control logic for the receiver is enabled, the pause value parameter in the frame is used to inhibit trans-mitter operation after successful completion of the current packet transmission for the time defined in the IEEE 802.3-2002 specification. Because the received pause frame has been acted on, it is passed to the client with rx_bad_frame asserted to indicate that it should be dropped.Reception of any frame for which condition number 2 is true and is not of legal minimum length is con-sidered an invalid control frame. This will be ignored by the Flow Control logic and passed to the client with rx_bad_frame asserted.Optional Address FilterThe GEMAC core can be implemented with an Address Filter. If the Address Filter is enabled, the device does not pass frames that do not contain one of a set of known addresses to the client.The Address Filter can be programmed to respond to up to five user-defined addresses when the Man-agement Interface is present in the core. These can be stored in a dedicated unicast address register and in a n-address deep table, where n is in the range 0 to 4. If the core is implemented with an Address Fil-ter but the Management Interface is omitted from the core, only the unicast address register can be accessed. Access to the unicast address register is through the input signal unicast_address[47:0] when the Management Interface is not present.In addition to the user-defined addresses, the broadcast and pause multicast addresses defined in the IEEE 802.3-2002 and the pause frame MAC source address are also recognized. For a detailed descrip-tion, see the 1-Gigabit Ethernet MAC User Guide.Optional Management InterfaceThe Management Interface is an optional processor-independent interface with standard address, data, and control signals. It can be used as is, or a wrapper can be applied (not supplied) to interface to com-mon bus architectures such as the CoreConnect bus interfacing to MicroBlaze or the Virtex-II Pro device embedded IBM PowerPC™. For a detailed description, see the 1-Gigabit Ethernet MAC User Guide. This interface is used for the following:•Configuration of the GEMAC core•Access through the MDIO interface to the Management Registers located in the PHY connected to the GEMAC coreDS200 March 24, 2008Client Management Interface SignalsTable 4 defines the optional signals used by the client to access the management features of the GEMAC core.Configuration RegistersAfter a power up or reset, the client can reconfigure the core parameters from the defaults. Configura-tion changes can be written at any time. Both the receiver and transmitter logic will only respond to configuration changes during interframe gaps. The exceptions are the configurable resets, which take effect immediately.Configuration of the GEMAC core is performed through a register bank that is accessed through the Management interface. Table 5 describes the available Configuration Registers. As described, the addresses have some implicit don’t care bits; any access to an address in these performs a 32-bit read or write from the same configuration word.T able 4: Optional Management Interface Signal PinoutSignalDirectionClock DomainDescriptionhost_clkInputn/aClock for the Management Interface; this must in the range of 10 MHz or abovehost_opcode[1:0]Input host_clk Defines operation to be performed over MDIO interface. Bit 1 is also used as a read/write control signal for configuration register access host_addr[9:0]Input host_clk Address of register to be accessed host_wr_data[31:0]Input host_clk Data to write to register host_rd_data[31:0]Output host_clk Data read from registerhost_miim_sel Input host_clk When asserted, the MDIO interface is accessed. When not asserted, the configuration registers are accessed host_req Input host_clk Used to signal a transaction on the MDIO interface host_miim_rdyOutputhost_clkWhen high, the MDIO interface has completed any pending transaction and is ready for a new transactionT able 5: Configuration RegistersAddressDescription0x200-0x23F Receiver Configuration (Word 0)0x240-0x27F Receiver Configuration (Word 1)0x280-0x2BF Transmitter Configuration 0x2C0-0x2FF Flow Control Configuration 0x300-0x33F Reserved0x340-0x37F Management Configuration0x380-0x383Unicast Address (Word 0) (if address filter is present)0x384-0x387Unicast Address (Word 1) (if address filter is present)Tables 6 and 7 define the register contents for the two receiver configuration words.Table 8 defines the register contents for the Transmitter Configuration Word.0x388-0x38B Address T able Configuration (Word 0) (if address filter is present)0x38C-0x38F Address T able Configuration (Word 1) (if address filter is present)0x390-0x393Address Filter Mode (if address filter is present)T able 6: Receiver Configuration Word 0BitDefault ValueDescription31-0All 0sPause frame MAC Source Address[31:0]T able 7: Receiver Configuration Word 1BitDefault ValueDescription15-0All 0s Pause frame MAC Source Address[47:32]23-16n/a Reserved240Control Frame Length Check Disable 250Length/Type Error Check Disable 26n/a Reserved 270VLAN Enable 281Receiver Enable 290In-band FCS Enable 300Jumbo Frame Enable 31Receiver ResetT able 8: Transmitter Configuration WordBitDefault ValueDescription24-0n/a Reserved250Interframe Gap Adjust Enable 26n/a Reserved 270VLAN Enable 281T ransmit Enable 290In-band FCS Enable 300Jumbo Frame Enable 31T ransmitter ResetT able 5: Configuration Registers (Continued)AddressDescriptionDS200 March 24, 2008Table 9 defines the register contents for the Flow Control Configuration Word.Table 10 defines the register contents for the Management Configuration Word.When the GEMAC core is implemented with an Address Filter, registers described in Tables 11 through 15 are used to access the Address Filter configuration. The register contents for the two unicast address registers are described in Tables 11 and 12.Tables 13 and 14 show how the contents of the Address Table are set.T able 9: Flow Control Configuration WordBitDefault ValueDescription28-0n/a Reserved291Receiver Flow Control Enable301T ransmitter Flow Control Enable 31n/aReservedT able 10: Management Configuration WordBitsDefault ValueDescription4-0All 0s Clock Divide[4:0]: This value enters a logical equation which enables the MDC frequency to be set as a divided down ratio of the HOST_CLK frequency.50MDIO Enable 31-6n/aReservedT able 11: Unicast Address (Word 0)BitsDefault ValueDescription31-0All 0sAddress filter unicast address[31:0]T able 12: Unicast Address (Word 1)BitsDefault ValueDescription15-0All 0s Address filter unicast address[47:32]31- 16N/AReservedT able 13: Address Table Configuration (Word 0)BitsDefault ValueDescription31-0All 0sMAC Address[31:0]The contents of the Address Filter mode register are described in Table 15. If Promiscuous mode is set to 1, the Address Filter does not check the addresses of receive frames.MDIO InterfaceThe Management Interface is also used to access the MDIO interface of the GEMAC core; this interface is typically connected to the MDIO port of a PHY to access its configuration and status registers. The MDIO format is defined in IEEE 802.3 clause 22.MDIO Interface SignalsTable 16 defines the MDIO interface signals.T able 14: Address Table Configuration (Word 1)BitsDefault ValueDescription15-0All 0s MAC Address[47:32]17-16All 0s The location in the address table that MAC address is to be read from or written to 22-18N/A Reserved 230Read not write 31-24N/AReservedT able 15: Address Filter ModeBitsDefault ValueDescription30-0N/A Reserved31Promiscuous ModeTable 16: MDIO Interface Signal Pinout SignalDirectionClock DomainDescriptionmdc Output host_clk Management Clock: derived from host_clk on the basis of the Clock Divide[4:0] value in the Management Configuration Word .mdio_in Input host_clk Input data signal for communication with PHY configuration and status. Tie high if unused.mdio_out Output host_clk Output data signal for communication with PHY configuration and status.mdio_triOutputhost_clkT ristate control for MDIO signals; 0 signals that the value on mdio_out should be asserted onto the MDIO bus.Note: mdio_in,mdio_out ,and mdio_tri can be connected to a Tri-state buffer to create a bi-directional mdio signal suitable for connection to an external PHY.DS200 March 24, 2008Configuration VectorIf the optional Management Interface is omitted from the GEMAC core, all relevant configuration set-tings described in Tables 6 through 9 and Table 15 are extracted as signals and bundled into the configuration_vector[67:0] signal. These signals can be permanently set by connecting to logic 0 or 1, or can be driven dynamically by control logic. See the 1-Gigabit Ethernet MAC User Guide .Reset OperationThe optional Management Interface provides independent configurable software driven resets for the receiver and transmitter paths (as defined in Tables 7 and 8.) When the Management interface is omit-ted, these resets are replaced as inputs of the configuration_vector[64:0] signal. In addition, a hardware reset port is provided to the core, described in Table 17.GMII BlockThis implements GMII-style signaling for the physical interface of the core and is typically attached to a PHY, either off-chip or internally integrated. The HDL example design delivered with the core when the GMII is selected connects these signals to IOBs to provide an external GMII. The HDL example design delivered with the core when the RGMII is selected connects these signals to a logic shim that uses double-data-rate (DDR) registers and DCMs to provide an external RGMII.GMII SignalsTable 18 defines the GMII-side interface signals of the core.T able 17: Reset Interface Signal PinoutSignalDirectionClock DomainDescriptionresetInputn/aAsynchronous reset for the entire core. Active High.T able 18: GMII Interface Signal PinoutSignalDirectionClock DomainDescriptiongmii_txd[7:0]Output gtx_clk GMII Transmit data from MAC gmii_tx_en Output gtx_clk GMII Transmit control signal from MAC gmii_tx_er Output gtx_clk GMII Transmit control signal from MACgmii_rx_clk Input n/a GMII Receive clock from an external PHY (125MHz) gmii_rxd[7:0]Input gmii_rx_clk GMII Received data to MAC gmii_rx_dv Input gmii_rx_clk GMII Received control signal to MAC gmii_rx_erInputgmii_rx_clkGMII Received control signal to MACVerificationThe GEMAC core has been verified with extensive simulation and hardware testing, as detailed in this section.SimulationA highly parameterizable transaction-based test bench was used to test the core. Tests include:•Register Access•MDIO Access•Frame Transmission and Error Handling•Frame Reception and Error Handling•Address FilteringHardware VerificationThe GEMAC core has been tested in a variety of hardware test platforms at Xilinx to address specific parameterizations, including the following:•The core has been tested with the Ethernet 1000BASE-X PCS/PMA or SGMII core, which follows the architecture illustrated in Figure1. A test platform was built around these cores, including a back-end FIFO capable of performing a simple ping function and a test pattern generator. Software running on the embedded PowerPC was used to provide access to all configuration, status, and statistical counter registers. Version 3.0 of this core was taken to the University of New Hampshire Interoperability Lab (UNH IOL) where conformance and interoperability testing was performed.•The core has been tested with an external 1000BASE-T PHY device, which follows the architecture illustrated in Figure2. The GEMAC core was connected to the external PHY device using GMII, RGMII and SGMII (in conjunction with the Ethernet 1000BASE-X PCS/PMA or SGMII core). Family SupportT able 19: Family Support for the 1-Gigabit Ethernet MAC CoreDevice FamilyPHY Interface ManagementInterfaceAddress Filter with GMII with RGMIIVirtex-5Supported Supported Supported Supported Virtex-4Supported Supported Supported Supported Virtex-II Pro Supported Supported Supported Supported Virtex-II Supported Supported Supported Supported Spartan-3Supported Supported Supported Supported Spartan-3E Supported Not Supported Supported Supported Spartan-3A/3AN/3ADSPSupported Supported Supported SupportedDS200 March 24, 2008The Virtex-5 device family contains six input LUTs; all other families contain four input LUTs. For this reason, the device utilization for Virtex-5 devices is listed separately. Please refer to either of the follow-ing:•Virtex-5 Devices •Other Device FamiliesVirtex-5 DevicesTable 20 provides approximate utilization figures for various core options when a single instance of the core is instantiated in a Virtex-5 device.Utilization figures are obtained by implementing the block level wrapper for the core. This wrapper is part of the example design and connects the core to the selected physical interface. BUFG usage:•does not consider multiple instantiations of the core, where clock resources can often be shared •does not include the reference clock required for IDELAYCTRL. This clock source can be shared across the entire device and is not core specific Table 20: Device Utilization for Virtex-5 Device FamiliesParameter ValuesDevice ResourcesPhysical InterfaceManagement InterfaceAddress FilterAddr Table EntriesSlice sLUT sFFs18K Block RAMsBUFGsDCMsGMII Y es Y es 4608953102303011.No core-specific DCMs are required if a reference clock for the IDELAYCTRL component is available on-chip.GMII Y es Y es 05618559670301GMII Y es No N/A 4777328330301GMII No Y es N/A 3926727130201GMII No No N/A 3806236610201RGMII Y es Y es 459895*********RGMII Y es Y es 05368589570301RGMII Y es No N/A 4987358230301RGMII No Y es N/A 4016767030201RGMIINoNoN/A372626651201。

SP1000A芯片规格说明书

SP1000A Datasheet2021.5Revision History目录第1章SP1000A简介 (1)1.1主要技术特征 (2)1.1.1以太网 (2)1.1.2数据中心 (2)1.1.3卸载 (2)1.1.4主机接口 (3)1.1.5虚拟化 (3)1.1.6接口 (3)1.2引脚描述 (4)1.3电气规格 (12)1.3.1极限工作条件 (12)1.3.2建议工作条件 (12)1.3.3工作电流 (13)1.3.4模式配置说明 (13)1.3.5ETH时钟输入 (14)1.3.6电源设计 (15)1.3.7复位时间 (15)1.3.8NCSI AC S PECIFICATION (15)1.3.9FLASH推荐 (16)1.3.10光模块推荐 (16)1.3.11PCI_E XPRESS 布线建议 (17)1.3.12SFP+布线建议 (17)第2章芯片封装尺寸说明 (18)第1章SP1000A简介SP1000A处理器是北京网迅自主设计的，拥有自主知识产权，它能满足企业数据中心对网络最新需求，应用在服务器上，支持管理程序分流数据排序功能，通过有效地平衡网络负载在CPU核上，提高数据吞吐量和CPU使用率，在多CPU处理器系统中表现出极佳的性能。

SP1000A处理器具有优良的噪声抗扰性，同时还支持300米距离光纤连接，适用于服务器和高端设备，它可轻松将任何PCI Express X8集成到万兆网络中，并且对性能进行了优化，使系统I/O不再是高端网络应用的瓶颈。

SP1000A处理器带有两个完全集成的万兆以太网媒体存取控制（MAC）和SFP+端口，它是部署多个网络以及在高性能服务器上部署关键网络应用环境的理想解决方案。

SP1000A产品应用框图如下：1.1主要技术特征1.1.1 以太网➢10G SFI/KR/XAUI/SGMII接口➢支持最大9.5 KB的巨型帧➢支持模式下自动匹配第73条➢控制支持：发送/接收暂停帧和接收FIFO阈值➢支持802.1q VLAN➢休眠唤醒➢流量整形1.1.2数据中心➢支持PFC(802.1Qbb)➢支持ETS(802.1Qaz)➢支持QCN(802.1Qau)➢支持VEPA➢支持ETAG➢支持MIB和RMON➢VXLAN/Geneve/NVGRE卸载1.1.3卸载➢IPv4 TCP RSC卸载➢FCOE卸载➢发送端TCP报文切片：最高支持256KB➢Linksec卸载➢更规范的IPSec➢IP/TCP/UDP/STCP校验和卸载➢用于数据包重组的分段UDP校验和卸载➢以太网CRC剥离卸载➢VLAN Tag发送端插入和接收端剥离卸载➢支持传输数据包的MAC源地址/ VLAN防欺骗功能➢支持接收数据包头拆分1.1.4主机接口➢消息信号中断（MSI / MSI-X）➢中断节流控制，用于限制最大中断速率➢TCP定时器中断➢支持TPH/FLR/IDO/ARI/VPD/ECRC➢256B最大有效载荷/ 2KB最大请求➢PCIE乱序发送➢功能性支持D0和D3状态的ACPI寄存器设置和掉电1.1.5虚拟化➢支持SR-IOV➢128个传输队列◼每个队列有32个条目数据描述符缓存◼每个队列都有2个条目上下文描述符缓存➢128个接收队列◼LLI队列的描述符缓存➢支持每个端口64个虚拟机（64个虚拟机x 2个队列）注：驱动软件支持每个端口63个虚拟网口。

VSC8211 链接 CPU 与 R GMII 接口的 SGMII 基础交换机说明书

VSC8211 Linking CPUs with R/GMII Interfaces to SGMII-BasedSwitches1Revision History (1)1.1Revision 1.0 (1)2Introduction (2)2.1Audience (2)2.2References (2)2.2.1Vitesse Documents (2)2.2.2IEEE Standards (2)2.2.3External Documents (2)3 A Managed Switch System (3)4System Considerations (4)4.1How Many Interface Ports? (4)4.2Packet Traffic Shaping (4)4.3RGMII-SGMII PHY Device Link Monitoring (4)5Hardware Considerations (5)5.1Connecting GMII (5)5.2Connecting RGMII (6)5.3Connecting SGMII (7)5.4Control and Status Connections (7)6Software Considerations (9)6.1VSC8211 Register Configuration (9)6.2SGMII Switch Register Configuration (9)1Revision HistoryThe revision history describes the changes that were implemented in the document. The changes arelisted by revision, starting with the most current publication.1.1Revision 1.0Revision 1.0 was the first release of this document. It was published in April 2005.2IntroductionThis Application Note will describe design considerations for connecting an embedded microprocessorthat contains a GMII or RGMII MAC interface to an SGMII-based Gigabit Ethernet Switch. This documentwill cover system, hardware, and software considerations as well as advantages and limitations for each.Systems such as IP DSLAMs, wireless platforms, and enterprise routers often require enhanced securityprotocol processors to help to perform switching and parsing of packets. However, packet processors’Ethernet interfaces are a generation behind the latest Ethernet switch devices. The latest GigabitEthernet switch devices with high port counts of 16-24 ports per chip have migrated towards SGMIIinterfaces, while processors are only now offering both GMII and RGMII interfaces. For a packetprocessor to connect to the latest gigabit switch, there will need to be an interface conversion device toget an RGMII processor to link to an SGMII-based Ethernet switch. This document will cover variousdesign considerations for connecting an embedded microprocessor with a GMII or RGMII MAC interfaceto an SGMII-based Gigabit Ethernet switch. This document will address system, hardware, and softwareconsiderations as well as advantages and limitations for each.2.1AudienceThis document is geared toward system, hardware, and software designers.2.2References2.2.1Vitesse DocumentsVSC8211 Datasheet (VMDS-10105)VSC8224 Datasheet (VMDS-10107)VSC7372 Datasheet (PD0031)VSC7374 Datasheet (PD0028)VSC7376 Datasheet (PD0032)VSC8211 Design and Layout Guide (VPPD-01173)VSC8224 Design and Layout Guide (VPPD-01145)2.2.2IEEE StandardsCSMA/CD Access Method and Physical Layer Specification (IEEE802.3)2.2.3External DocumentsFreescale MPC8548E Fact Sheet (MPC8548FS)Intel IXP2325 Product Brief (30367902)AMCC PowerPC 440GX Product Brief (PB2000)Mindspeed M27481 Product Brief (27481-BRF)3 A Managed Switch SystemA managed switch system is composed of at least an Ethernet switch chip, several physical layer devices(PHYs) that can interface to copper or fiber links, and at least one embedded processor. The system willgenerally be responsible for managing packets at a level of up to Layer 3 or higher.Figure 1 • Managed Switch Block Diagram4.1How Many Interface Ports?One factor to consider is how many interface ports from the switch will be connected to the embeddedprocessor. For example, the MPC8548E PowerQuicc III has four-gigabit Ethernet MAC interfaces. All fourof these ports could be linked to the Ethernet switch.4.2Packet Traffic ShapingGenerally a gigabit Ethernet connection requires at least 1 GHz of dedicated CPU processing power.Most embedded processors cannot handle a large continuous burst of packet data of this magnitude. Toprevent a processor from being overrun, it is important to consider if traffic shaping will be required.Traffic shaping is useful in that it can limit the amount of egress traffic from being sent out of a switchport into a bandwidth-limited device, such as a CPU.4.3RGMII-SGMII PHY Device Link MonitoringTo ensure the link between the processor and switch is active, there are several monitoring methods toconsider.The PHY’s link status register bit can be continuously polled.The PHY’s interrupt pin is connected to the interrupt controller to monitor change in link status.The LINK LED can be connected to a GPIO pin on the processor and then this pin is monitored.5Hardware ConsiderationsOnce the number of ports is established, the RGMII-SGMII conversion device must be selected. For 1-2ports, the VSC8211 single gigabit PHY can be used. For higher ports, the VSC8224 quad gigabit PHY is abetter choice due to its compact footprint size and low power.The following information in this section is a general description. Please consult both the PHY’sdatasheet or design and layout guide for more specific design information.Figure 2 • RGMII-to-SGMII Hardware Connectivity5.1Connecting GMIIGMII is a 25-pin per port interface. It has a clock speed of 125 MHz and 8 data bits in both directions.The interface clock is sourced by the PHY.Figure 3 • GMII Connection Diagram5.2Connecting RGMIIRGMII is a reduced pin count version of GMII as it only has 12 pins per port. While it uses the same 125MHz clock speed, the data pin count is reduced to 4 bits and the data is clocked in on both edges of theclock in a double-data rate manner.Figure 4 • RGMII Connection DiagramAnother aspect of RGMII that is different from GMII is that it requires a clock delay skew of 1.5 ns–1.9 nsAnother aspect of RGMII that is different from GMII is that it requires a clock delay skew of 1.5 ns–1.9 nsto either be placed on the board with a delay trace or the delay is created internally in the MAC and/orPHY. The VSC8211 offers this clock delay skew feature on both TX and RX pairs thereby removing theneed for a board trace delay. See the VSC8211 or VSC8224 Design and Layout Guide for moreinformation.5.3Connecting SGMIISGMII is a further pin reduction of GMII as it is only a 4-pin interface. The data and clock are embeddedand transmitted on a two pin differential interface in both directions. The latest switch will operate itsport interface using the SGMII interface. Both the VSC8211 and VSC8224 cannot perform a full RGMII-to-SGMII conversion. These devices however, can operate as an RGMII-to-1000BASE-X SerDes mediaconverter. 1000BASE-X SerDes is compliant electrically and functionally to SGMII’s 1000 Mbps setting.From a permanent link perspective, 1000 Mbps is the only speed that is required in an SGMII-basedEthernet switch system. Therefore the RGMII-to-1000BASE-X mode can be used to link the processor tothe SGMII-based Ethernet switch.For the VSC8211/VSC8224, AC coupling capacitors are needed from the processor to the PHY. The SGMIIswitches such as the VSC7372/74/76 have a register setting to allow the PHY-to-Switch portion to beelectrically compatible. To allow the SerDes on the PHY to link, the SIGDET pin must also be asserted bytying it high.Figure 5 • SGMII Connection Diagram5.4Control and Status ConnectionsIn order to setup the PHY the MDC and the MDIO must be connected to the host processor to setup theoperating mode and other PHY register settings. Also depending on how the processor will monitor thePHY during normal operation, other pins such as the interrupt pin (MDINT) or the LINK LED pin will needto be connected.Figure 6 • Control and Status Diagram6.1VSC8211 Register ConfigurationFor the VSC8211, the following registers must be configured.Set the operating mode (see the following table).If using RGMII, then set the delay skew setting (register 23[11:8]).Set Auto-negotiation Disabled (Register 0.12 = 0).Set Speed Selection (Register 0.[6,13] = 10).Set Duplex to Full (Register 0.8 = 1).If using MDINT pin as a link indication, set Register 25.15 = 1 and Register 25.13 = 1 (Link statechange indication).Table 1 • Setting the VSC8211 Operating Mode (Register 23[15:12, 2:1])Register Setting Description0011 01GMII-Fiber (1000BASE-X SerDes)0001 01RGMII-Fiber (1000BASE-X SerDes)6.2SGMII Switch Register ConfigurationFor the VSC7372/74/76 switch, the following registers must be configured in order to link to theVSC8211. This is in addition to the settings that are required for initialization of the switch. Thesesettings can be found in the Minimum Software Requirements section of the VSC7372/74/76datasheets.Set the SGMII_MACRO_CFGx.TX_ENA (Block 1, 0x1A bit 28 = 1)Set the SGMII_MACRO_CFGx.TX_OUTPUT_LEVEL (Block 1, 0x1A bit 26 = 1)Set the SGMII_MACRO_CFGx.TX_RESET (Block 1, 0x1A bit 25 = 1)Set the SGMII_MACRO_CFGx.RX_IB_AUTO_SQUELCH (Block 1, 0x1A bit 24 = 1)Set the SGMII_MACRO_CFGx.TX_COMMONMODE_TERM_ENA (Block 1, 0x1A bit 23 = 1)Set the SGMII_MACRO_CFGx.CDR_DISABLE (Block 1, 0x1A bit 22 = 0)Set the SGMII_MACRO_CFGx.RX_ENA (Block 1, 0x1A bit 8 = 1)Set the SGMII_MACRO_CFGx.RX_RESET (Block 1, 0x1A bit 0 = 1)Set the SGMII_INPUT_COMMONMODE_SELx.IB_B (Block 1, 0x1B bit 9 = 1)Set the SGMII_INPUT_COMMONMODE_SELx.IB_A (Block 1, 0x1B bit 0 = 1)Also, if traffic shaping is being employed, this can be found in the following table.Table 2 • Switch Egress Port Traffic Shaping ControlRegister Setting Register DescriptionWS_CONFx.ENABLE Block 1, 0x28 bit 6Enables/Disables ShapingWS_CONFx Block 1, 0x28 bits 12:7, 5:0Configures the ShapingWS_BUCK0Block 1, 0x29 bits 20:0Configures Queue 0 BucketWS_BUCK1Block 1, 0x2A bits 20:0Configures Queue 1 BucketWS_BUCK2Block 1, 0x2B bits 20:0Configures Queue 2 BucketWS_BUCK3Block 1, 0x2C bits 20:0Configures Queue 3 BucketMicrosemi HeadquartersOne Enterprise, Aliso Viejo,CA 92656 USAWithin the USA: +1 (800) 713-4113Outside the USA: +1 (949) 380-6100Sales: +1 (949) 380-6136Fax: +1 (949) 215-4996Email:***************************© 2005 Microsemi. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided "as is, where is" and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice.Microsemi, a wholly owned subsidiary of Microchip Technology Inc. (Nasdaq: MCHP), offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication solutions; security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, California, and has approximately 4,800 employees globally. Learn more at www. .VPPD-01208。

SGMII Specification

Document Number ENG-46158Revision Revision 1.7AuthorYi-Chin Chu Project ManagerJR RiversSerial-GMII SpeciﬁcationThe Serial Gigabit Media Independent Interface (SGMII)is designed to satisfy the following requirements:•Convey network data and port speed between a 10/100/1000 PHY and a MAC with signiﬁcantly less signal pins than required for GMII.•Operate in both half and full duplex and at all port speeds.Change HistoryDeﬁnitionsMII –Media Independent Interface:A digital interface that provides a 4-bit wide datapath between a 10/100Mbit/s PHY and a MAC sublayer.Since MII is a subset of GMII,in this document,we will use the term “GMII”to cover all of the speciﬁcation regarding the MII interface.GMII –Gigabit Media Independent Interface:A digital interface that provides an 8-bit wide datapath between a 1000Mbit/s PHY and a MAC sublayer.It also supports the 4-bit wide MIIRevision Date Description1.7July 20, 20001Clarify data sampling and also the possible loss of the ﬁrst byte of pream-ble.1.6Jan 4, 20001Added speciﬁcations for Cisco Systems Intellectual Property.1.5Aug 4, 2000Speciﬁed the data pattern for the beginning of the frame (preamble, SFD)for the frames sent from the PHY to make the PCS layer work properly.1.4June 30, 2000Took out Jabber info,changed tx_Conﬁg_Reg[0]from 0to 1to make Auto-Negotiation work1.3April 17, 2000Increased allowable input and output common mode range.The output high and low voltages were also increased appropriately.Added speciﬁcation for output over/undershoot.Added note about AC coupling and clock recovery.1.2Feb 8, 2000Added timing budget analysis and reduced LVDS input threshold to +/- 50mV .1.1Nov 10, 1999Incoporated Auto-Negotiation Process for update of link status 1.0Oct. 14, 1999Initial ReleaseSerial-GMII Specification: ENG-46158Revision 1.7 interface as deﬁned in the IEEE802.3z speciﬁcation.In this document,the term“GMII”covers all 10/100/1000 Mbit/s interface operations.OverviewSGMII uses two data signals and two clock signals to convey frame data and link rate information between a 10/100/1000PHY and an Ethernet MAC.The data signals operate at 1.25Gbaud and the clocks operate at 625MHz (a DDR interface).Due to the speed of operation,each of these signals is realized as a differential pair thus providing signal integrity while minimizing system noise.Figure 1 illustrates the simple connections in a system utilizing SGMII.The transmit and receive data paths leverage the 1000BASE-SX PCS deﬁned in the IEEE 802.3z speciﬁcation (clause 36).The traditional GMII data signals (TXD/RXD),data valid signals (TX_EN/RX_DV),and error signals (TX_ER/RX_ER)are encoded,serialized and output with the appropriate DDR clocking.Thus it is a 1.25Gbaud interface with a 625MHz clock.Carrier Sense (CRS)is derived/inferred from RX_DV ,and collision (COL)is logically derived in the MAC when RX_DV and TX_EN are simultaneously asserted.Control information,as speciﬁed in Table 1,is transferred from the PHY to the MAC to signal the change of the control information.This is achieved by using the Auto-Negotiation functionality deﬁned in Clause 37of the IEEE Speciﬁcation 802.3z.Instead of the ability advertisement,the PHY sends the control information via its tx_conﬁg_Reg[15:0]as speciﬁed in Table 1whenever the control information changes.Upon receiving control information,the MAC acknowledges the update of the control information by asserting bit 14of its tx_conﬁg_reg{15:0] as speciﬁed in Table 1.SGMII details source synchronous clocking;however,speciﬁc implementations may desire to recover clock from the data rather than use the supplied clock.This operation is allowed;however,all sources of data must generate the appropriate clock regardless of how they clock receive data.RXRXCLKTXTXCLKPHYMACCRSCOL RX_CKRX_DV RX_ERRXD[7:0]GTX_CLKTX_CLK TX_ENTX_ER88TXD[7:0]802.3z Transmit PCS802.3z Receive PCS802.3z SynchCOL RX_CLKRX_DV RX_ER RXD[7:0]GTX_CLKTX_CLK TX_EN TX_ER TXD[7:0]CRS 8802.3z Synch802.3z Transmit PCS8802.3z Receive PCSFigure 1SGMII Connectivity802.3z Auto-Negotiation 802.3z Auto-NegotiationSerial-GMII Specification: ENG-46158Revision 1.7The link_timer inside the Auto-Negotiation has been changed from 10msec to 1.6msec to ensure a prompt update of the link status.Clearly,SGMII’s 1.25Gbaud transfer rate is excessive for interfaces operating at 10or 100Mbps.When these situations occur,the interface “elongates”the frame by replicating each frame byte 10times for 100Mbps and 100types for 10Mbps.This frame elongation takes place “above”the 802.3z PCS layer,thus the start frame delimiter only appears once per frame.The 802.3z PCS layer may remove the ﬁrst byte of the “elongated” frame.Bit Number tx_conﬁg_Reg[15:0] sent from the PHY to the MACtx_conﬁg_Reg[15:0] sent from the MAC to the PHY 15Link: 1 = link up, 0 = link down0: Reserved for future use 14Reserved for Auto-Negotiation acknowledge as speciﬁed in 802.3z 1130: Reserved for future use0: Reserved for future use 12Duplex mode: 1 = full duplex, 0 = half duplex 0: Reserved for future use 11:10Speed: Bit 11, 10:1 1 = Reserved1 0 = 1000 Mbps: 1000BASE-TX, 1000BASE-X 0 1 = 100 Mbps: 100BASE-TX, 100BASE-FX 0 0 = 10 Mbps: 10BASET, 10BASE2, 10BASE50: Reserved for future use9:10: Reserved for future use 0: Reserved for future use 011table 1 Deﬁnition of Control Information passed between links via tx_conﬁg_Reg[15:0]Implementation SpeciﬁcationThis section discusses how this SGMII interface shall be implemented by incorporating and modifying the PCS layer of the IEEE Speciﬁcation 802.3z.Signal Mapping at the PHY sideFigure 2shows the PHY functional block diagram.It illustrates how the PCS layer shall be modiﬁed and incorporated at the PHY side in the SGMII interface.At the receive side,GMII signals come in at 10/100/1000Mbps clocked at 2.5/25/125MHz.The PHY passes these signals through the PHY Receive Rate Adaptation to output the 8-bit data RXD[7:0]in 125MHz clock domain.RXD is sent to the PCS Transmit State Machine to generate an encoded 10-bit segment ENC_RXD[0:9].The PHY serializes ENC_RXD[0:9]to create RX and sends it to the MAC at 1.25Gbit/s data rate along with the 625MHz DDR RXCLK.At the transmit side,the PHY deserializes TX to recover encoded ENC_TXD[0:9].The PHY passes ENC_TXD[0:9]through the PCS Receive State Machine to recover the GMII signals.In the mean time,Synchronization block checks ENC_TXD[0:9]to determine the synchronization status between links,and to realign if it detects the loss of synchronization.RXRXCLK CRSRX_CLK @RX_DV RX_ER RXD[7:0]TX_CLKTX_EN TX_ER TXD[7:0]GMII Signals from 10/100/1000PHYPHY Receive Rate AdaptationRX_CLK @2.5/25/125 MHzMACRX RXCLKPCS TransmitState Machine10from 802.3zSeri-ENC_RXD[0:9]alizerRX_CLKRX_DV RX_ER RXD[7:0]PCS ReceiveState Machinefrom 802.3zTX_CLK @TX_EN TX_ER TXD[7:0]Synchronization Figure 36-9Figure 36-7Figure 36-5,Figure 36-6Deseri-alizer10ENC_TXD[0:9]Auto-Negotiation Figure 37-6TX TXCLK PCS Layer from 802.3z Figure 36-2GMII Signals to 10/100/1000PHYPHY Transmit Rate AdaptationTX_CLK @2.5/25/125 MHzPHYCOL125 MHz125 MHzFigure 2PHY Functional BlockSerial-GMII Specification: ENG-46158Revision 1.7The decoded GMII signals have to pass the PHY Transmit Rate Adaptation block to output data segments according to the PHY port speed.To make the PCS layer from 802.3z work properly,the PHY must provide a frame started with at least two preamble symbols followed by a SFD symbol.To be more speciﬁc,at the beginning of a frame,RXD[7:0]in Figure 2shall be {8’h55,8’h55,(8’h55.....),8’hD5}followed by valid frame data.Signal Mapping at the MAC SideFigure 3shows the MAC functional block diagram.It illustrates how the PCS layer shall be modiﬁed and incorporated at the MAC side in the SGMII interface.At the receive side,the MAC deserializes RX to recover encoded ENC_RXD[0:9].The MAC passes ENC_RXD[0:9]through the PCS Receive State Machine to recover the GMII signals.In the mean time,Synchronization block checks ENC_RXD[0:9]to determine the synchronization status between links,and to realign once it detects the loss of synchronization.The decoded GMII signals have to pass the MAC Receive Rate Adaptation block to output data segments according to the PHY port speed,passed from the PHY to MAC via Auto-Negotiation process.At the transmit side,GMII signals come in at 10/100/1000Mbps data clocked at 2.5/25/125MHz.The MAC passes these signals through the MAC Transmit Rate Adaptation to output theRX RXCLKTXTXCLKPCS Layer from 802.3z Figure 36-2PHY10Seri-ENC_TXD[0:9]alizer Deseri-alizer 10ENC_RXD[0:9]RX_CLKRX_DVRX_ER RXD[7:0]PCS Receive State Machinefrom 802.3z RX_CLK @RX_DV RX_ER RXD[7:0]Synchronization Figure 36-7TX_CLK @TX_EN TX_ER TXD[7:0]TX_CLKTX_ENTX_ER TXD[7:0]PCS Transmit State Machinefrom 802.3z Auto-NegotiationMACGMII Signals to 10/100/1000PHYMAC Transmit Rate AdaptationSpeed InformationGMII Signals from 10/100/1000PHYMAC Receive Rate AdaptationSpeed InformationFigure 3MAC Functional BlockCRSFigure 37-6Figure 36-5Figure 36-6Figure 36-9COL 125 MHz125 MHzAND8-bit data TXD[7:0]in125MHz clock domain.TXD is sent to the PCS Transmit State Machine to generate an encoded10-bit segment ENC_TXD[0:9].The MAC serializes ENC_TXD[0:9]to create TX and sends it to the PHY at1.25Gbit/s data rate along with the 625 MHz DDR TXCLK.Control Information Exchanged Between LinksAs described in Overview,it is necessary for the PHY to pass control information to the MAC to notify the change of the link status.SGMII interface uses Auto-Negotiation block to pass the control information via tx_conﬁg_Reg[15:0].If the PHY detects the control information change,it starts its Auto-Negotiation process, switching its Transmit block from“data”to“conﬁguration”state and sending out the updated control information via tx_conﬁg_Reg[15:0].The Receive block in the MAC receives and decodes control information,and starts the MAC’s Auto-Negotiation process.The Transmit block in the MAC acknowledges the update of link status via tx_conﬁg_Reg[15:0]with bit14 asserted,as speciﬁed in Table1.Upon receiving the acknowledgement from the MAC,the PHY completes the auto-negotiation process and returns to the normal data process.As speciﬁed in Overview,inside the SGMII interface,the Auto-Negotiation link_timer has been changed from10msec to1.6msec,ensuring a prompt update of the link status.The expected latency for the update of link is3.4msec(two link_timer time+an acknowledgement process).Data Information T ransferred Between LinksBelow we brieﬂy describe at receive side how GMII signals get transferred across from the PHY and recovered at the MAC by using the8B/10B transmission code.The same method applies to the transmit side.According to the assertion and deassertion of RX_DV,the PHY encodes the Start_of_Packet delimiter(SPD/S/)and the End_Of_Packet delimiter(EPD)to signal the beginning and end of each packet. The MAC recovers RX_DV signal by detecting these two delimiters.The PHY encodes the Error_Propagation(/V/)ordered_set to indicate a data transmission error. The MAC asserts RX_ER signal whenever it detects this ordered_set.CRS is not directly encoded and passed to the MAC.To regenerate CRS,the MAC shall uses signal RX_DV before it is being passed to the MAC Receive Rate Adaptation block as shown in Figure 3.The MAC decodes ENC_RXD[0:9] to recover RXD[7:0].Bellow Figure4illustrates how the MAC samples data in100Mbit/s mode.As signals shown in Figure2,the GMII data in100Mbit/s mode get replicated ten times after passing through the PHY Receive Rate Adaptation to generate RXD[7:0].The modiﬁed PCS Transmit State Machine encodes RXD[7:0]to create ENC_RXD[0:9].As noted in the Overview,the SPD(/S/ )only appears once per frame.SAMPLE_EN is a MAC internal signal to enable the MAC sampling of data starting at theﬁrst data segment(/S/)once every ten data segments in100 Mbit/s mode.A note to Figure4:there is noﬁxed boundary for the data sampling.Also theﬁrst byte of preamble might be only repeated9/99instead of10/100times due to the algorithm of the 802.3z PCS Transmit State Machine.Serial-GMII Specification: ENG-46158Revision 1.7LVDS AC/DC SpeciﬁcationThe basis of the LVDS and termination scheme can be found in IEEE1596.3-1996.Some parameters have been modiﬁed to accommodate the 1.25Gb/s requirements.SGMII consists of the most lenient DC parameters between the general purpose and reduced range LVDS.Both the data and clock signals are DC balanced;therefore,implementations that meet the AC parameters but fail to meet the DC parameters may be AC coupled.Figure 5shows the DDR circuit at the source of the LVDS.The circuit passes data and clock with a 90 degree phase difference. The receiver samples data on both edges of the clock.125 MHz ClockData in 100Mbit/sRXD[7:0] after Figure 4Data Sampling in 100 Mbit/s modeD0D0D0D0D0D0D0D0D0D0D1D1D1D1D1D1D1D1D1D1D2D2D2D2D2D2D2D2D2Data0Data1Data2ENC_RXD[0:9]/S/d0d0d0d0d0d0d0d0d0d1d1d1d1d1d1d1d1d1d1d2d2d2d2d2d2d2d2d2SAMPLE_ENRX_DVDomain Rate Adaptation D Q QND Q QNDataRX1.25 GHz Clock625 MHz DDR ClockFigure 5Reference data and clock circuitRXCLK Figure 6Driver Clock and Data AlignmentRXRXRXCLK RXCLK (single ended)(differential)(single ended)(differential)tclock2q (min)tclock2q (max)Symbol a a.For a detailed description of the symbols please refer to the IEEE1596.3-1996 standardParameter bb.All parameters measured at R load = 100ohms +-1% loadMin Max Units V oh Output voltage high,1525mV V ol Output voltage low 875mV Vring Output ringing10%|V od|Output Differential V oltage 150400mV V os Output Offset V oltage 10751325mV Ro Output impedance (single ended)40140ohms ∆Ro Mismatch in a pair10%∆|V od|Change in V od between “0”and “1”25mV ∆V os Change in V os between “0”and “1”25mV Isa, Isb Output current on Short to GND 40mA Isab Output current when a, b are shorted12mA Ixa, IxbPower off leakage current10mAtable 2 Driver DC speciﬁcationSymbol ParameterMin Max Units Vi Input V oltage range a or b 6751725mV Vidth Input differential threshold -50+50mV Vhyst Input differential hysteresis 25mv RinReceiver differential input impedance80120ohmstable 3 Receiver DC speciﬁcationSymbol a a.For a detailed description of the symbols please refer to the IEEE1596.3-1996 standardParameterMin Max Units clock Clock signal duty cycle @625MHz4852%t fall V od fall time (20%-80%)100200pSec t rise V od rise time (20%-80%)100200pSec t skew1bb.Skew measured at 50% of the transition Skew between two members of a differential pair - |tp HLA -tp LHB | or |tp LHA - tp HLB |20pSect clock2q cc.Skew measured at 0v differentialClock to Data relationship:from either edges of the clock to valid data250550pSectable 4 Driver AC speciﬁcationSerial-GMII Specification: ENG-46158Revision 1.7Symbol Parameter Min Max Unitst setup a setup time100pSect hold hold time100pSectable 5 Receiver AC speciﬁcationa.Measured at 50% of the transitionRepresentative Timing BudgetA transmit and receive path timing budget provided in the table below.The exact allocation ofthe budget is implementation speciﬁc;however,veriﬁcation of overall requirements are testedagainst the speciﬁcations in the tables external to the packaged integrated circuit.Element Value UnitsEffective clock period800psCycle to cycle clock jitter100 ps peak-peakImperfect duty cycle30 ps peak-peakData dependent jitter70 ps peak-peakStatic package skew100 ps peak-peakRemaining window500 (250 ps clock2q)ps peak-peaktable 6 Timing budget for driver requirementsElement Value UnitsDriver window500ps peak-peakStatic package skew100ps peak-peakReceiver setup time100ps peak-peakRemaining window300ps peak-peaktable 7 Timing budget for receiver requirementsThis budget shows the driver generating a data signal with a500ps eye centered around thesampling clock edge(see Figure6“Driver Clock and Data Alignment”on page8).Thereceiver will add additional skew, leaving 300 ps of margin.Cisco Systems Intellectual PropertyCisco Systems has released its proprietary rights to information contained in this document forthe express purpose of implementation of this speciﬁcation to encourage others to adopt thisinterface as an industry standard.Any company wishing to use this speciﬁcation may do so ifthey will in turn relinquish their proprietary rights to information contained or referencedherein.Any questions concerning this release should be directed to the Robert Barr,WorldWide Patent Counsel, Cisco Systems, 300 East Tasman Drive, San Jose, CA.。

世界各国认证详细版

世界各国认证简介新加坡PSB认证新加坡消费品保护法规1991指定新加坡标准，生产力和创新委员作为产品安全职能机构，负责对消费者保护（安全要求）注册方案（CPS）涉及的产品进行许可和注册。

只有带“SAFETY”标志的注册产品才能在新加坡销售。

目前新加坡只要求安全而对EMC只是自愿原则。

安全要求：在IEC标准要求下，产品还要符合热带条件测试。

新加坡电压：AC 230V\ 50Hz验厂：一般需要（如果通过莱茵CB去申请有莱茵的工厂检查报告可以不再工厂检查）。

说明书：要求英文证书有效期：证书有效期为一年。

申请周期：一般3-4周。

瑞士SEV为非欧盟国家，在产品认证方面未加入欧盟的CE制度。

因此瑞士的产品法规有自己的要求，瑞士的SEV低电压产品法规规定：进入瑞士市场的电子电气产品需要取得S-PLUS标志。

此标志包含了产品的安全性也涵盖了电磁兼容（EMC）的要求。

电压：AC 23厂说明书：法语0V/50Hz验厂：无需验、意大利语或徳语认证周期：如用CB申请需2-3周。

无CB需4-6周。

波兰(Poland)认证B标志认证是波兰目前的强制性认证。

出口到波兰的电子电气产品都必须通过B标志认证。

B标志涵盖产品安全、电磁兼容和卫生要求。

认证机构：PCBC，BBJ电压：AC 230V/50Hz验厂：需要或指定机构的验厂报告说明书：波兰文认证周期：4-5周申请方式：CB报告或GS报告+EMC报告的基础上申请。

匈牙利（Hungary）匈牙利的电工产品实验是依据关于人身、健康、财产安全的有关规定，按照匈牙利的电气标准而进行的强制实验。

认证机构：Magyar Elektrotechnikai Ellenorzo Intezet-MEEI认证标志：S-Mark MEEI Mark认证要求：安全及EMC都要求电压：AC 230V/50Hz验厂：需要或指定机构的验厂报告说明书：匈牙利文认证周期：S-Mark 1-2 周 (有CB的时间)MEEI 2-3 周 (有CB的时间)申请方式：CB报告或GS报告+EMC报告的基础上申请。

SGM 上海通用汽车对供应商质量要求的规定概要

上海通用汽车对供应商质量要求的规定-SGM供应商质量、项目经理必备手册上海通用汽车采购部供应商质量及开发科2004年10月18日第一版SGM-供应商质量、项目经理必备手册目录一、 GM供应商质量声明二、 APQP三、 FE四、 PPAP五、 GP12六、 PTR/断点七、控制计划审核八、 PRR九、受控发运十、产品与体系审核十一、持续改进十二、供应商易地生产十三、年度优秀供应商评选十四、说明十五、附件SGM-供应商质量、项目经理必备手册一、供应商质量声明:1. Supplier Quality Base Requirements:供应商质量基本要求:•(From General Terms and Conditions Seller agrees to participate in Buyer’s supplier quality and development program(s and to comply with all quality requirements and procedures specified by Buyer, as revised from time to time, including those applicable to Seller as set forth in Quality System Requirements QS-9000. In addition, Buyer shall have the right to enter Seller’s facility at reasonable times to inspect the facility, goods, mat erials and any property of Buyer covered by this contract. Buyer’s inspection of the goods, whether during manufacture, prior to delivery or within a reasonable time after delivery, shall not constitute acceptance of any work-in-process or finished goods.(一般条款和条件供应商应同意买方制定的供应商质量和开发程序并遵守买方列出的所有质量要求和程序(有时会修订,以及QS9000质量体系提出的对供应商适用的要求. 除此之外,买方有权随时进入供应商的设施来检查设备,产品,材料和合同规定的SGM所有物. 无论在制造期间,发运之前还是在发运后的某段时间,买方对产品的检查,不能够免除供应商对在制品或成品检查的责任。

gig_eth_pcs_pma_ds264

- Virtex-5 FPGA RocketIO™ GTP or GTX Transceiver
- Virtex-4 FPGA RocketIO Multi-Gigabit Transceiver (MGT)
- Spartan®-6 FPGA GTP Transceiver
• Parallel Ten-Bit-Interface (TBI) for connection to external SERDES4
© Copyright 2004-2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries. The PowerPC name and logo are registered trademarks of IBM Corp. and used under license. All other trademarks are the property of their respective owners.
Transceiver
TXP/TXN
GBIC or
SFP
Optical Transceiver
Optical Fiber
RXP/RXN
Figure 1: Typical 1000BASE-X Application
DS264 July 23, 2010

2
Product Specification
Supported HDL Xilinx® Tools Simulation Tools3

常用接口介绍

7、编码方式 XAUI接口基于XGMII接口，将32位并行数据转换为4通道的8位数据。XAUI接口与XGMII 接口均采用8B/10B编码方式，IEEE 802.3-2012针对XGMII接口对8B/10B的编码原理作了介绍，如下图所示
8B/10B编码方式介绍
8、测试指标驱动端电气指标：
XAUI接口驱动端电气标准
8
7、编码方式 MII接口传输帧格式：
数据流收发方式：
9
发送端时序图：
发送端数据编解码对应表
10
接收端时序图：
接收端数据编解码对应表
11
管理接口传输帧格式
12
8、测试指标发送端指标
高电平时间是指信号电平大于或等于Vih(min)的持续时间．低电平时间是指信号电平小于或等于Vil(max)的持续时间．与TX_CLK信号同步的信号包括TX_EN；TXD<3:0>；TX_ER．这些信号均需由PHY 端在TX_CLK信号的上升沿进行采样
XAUI接口通道速率及UI指标
带宽为3.125×4＝12.5 Gbps，但由于XAUI接口采用8B/10编码，即每传输一个字节需占用10位，因此纯数据带宽占有率为80%，即12.5×80%＝10Gbps。
5、信号电平 1）驱动电平要求：驱动器差分信号振幅取决于多个因素，如发送器预加重与发送通路线路损耗等。IEEE802.3-2012规范指标：
7、编码方式 GMII 接口是基于MII接口的，在数据传输中不对数据进行编码，TXD、RXD数据线直接传送原始数据。控制信息由TXEN、TXER、RXDV、RXER、COL、CRS 信号线传送。
GMII传输帧格式
GMII接口发送和接收数据位都为8位宽度，故一个时钟周期可以传输和接收一个字节的数据，每个数据位对应的数据如下图

Document Number ENG-46158Revision Revision 1.7AuthorYi-Chin Chu Project ManagerJR RiversSerial-GMII SpeciﬁcationThe Serial Gigabit Media Independent Interface (SGMII)is designed to satisfy the following requirements:•Convey network data and port speed between a 10/100/1000 PHY and a MAC with signiﬁcantly less signal pins than required for GMII.•Operate in both half and full duplex and at all port speeds.Change HistoryDeﬁnitionsMII –Media Independent Interface:A digital interface that provides a 4-bit wide datapath between a 10/100Mbit/s PHY and a MAC sublayer.Since MII is a subset of GMII,in this document,we will use the term “GMII”to cover all of the speciﬁcation regarding the MII interface.GMII –Gigabit Media Independent Interface:A digital interface that provides an 8-bit wide datapath between a 1000Mbit/s PHY and a MAC sublayer.It also supports the 4-bit wide MIIRevision Date Description1.7July 20, 20001Clarify data sampling and also the possible loss of the ﬁrst byte of pream-ble.1.6Jan 4, 20001Added speciﬁcations for Cisco Systems Intellectual Property.1.5Aug 4, 2000Speciﬁed the data pattern for the beginning of the frame (preamble, SFD)for the frames sent from the PHY to make the PCS layer work properly.1.4June 30, 2000Took out Jabber info,changed tx_Conﬁg_Reg[0]from 0to 1to make Auto-Negotiation work1.3April 17, 2000Increased allowable input and output common mode range.The output high and low voltages were also increased appropriately.Added speciﬁcation for output over/undershoot.Added note about AC coupling and clock recovery.1.2Feb 8, 2000Added timing budget analysis and reduced LVDS input threshold to +/- 50mV .1.1Nov 10, 1999Incoporated Auto-Negotiation Process for update of link status 1.0Oct. 14, 1999Initial ReleaseSerial-GMII Specification: ENG-46158Revision 1.7 interface as deﬁned in the IEEE802.3z speciﬁcation.In this document,the term“GMII”covers all 10/100/1000 Mbit/s interface operations.OverviewSGMII uses two data signals and two clock signals to convey frame data and link rate information between a 10/100/1000PHY and an Ethernet MAC.The data signals operate at 1.25Gbaud and the clocks operate at 625MHz (a DDR interface).Due to the speed of operation,each of these signals is realized as a differential pair thus providing signal integrity while minimizing system noise.Figure 1 illustrates the simple connections in a system utilizing SGMII.The transmit and receive data paths leverage the 1000BASE-SX PCS deﬁned in the IEEE 802.3z speciﬁcation (clause 36).The traditional GMII data signals (TXD/RXD),data valid signals (TX_EN/RX_DV),and error signals (TX_ER/RX_ER)are encoded,serialized and output with the appropriate DDR clocking.Thus it is a 1.25Gbaud interface with a 625MHz clock.Carrier Sense (CRS)is derived/inferred from RX_DV ,and collision (COL)is logically derived in the MAC when RX_DV and TX_EN are simultaneously asserted.Control information,as speciﬁed in Table 1,is transferred from the PHY to the MAC to signal the change of the control information.This is achieved by using the Auto-Negotiation functionality deﬁned in Clause 37of the IEEE Speciﬁcation 802.3z.Instead of the ability advertisement,the PHY sends the control information via its tx_conﬁg_Reg[15:0]as speciﬁed in Table 1whenever the control information changes.Upon receiving control information,the MAC acknowledges the update of the control information by asserting bit 14of its tx_conﬁg_reg{15:0] as speciﬁed in Table 1.SGMII details source synchronous clocking;however,speciﬁc implementations may desire to recover clock from the data rather than use the supplied clock.This operation is allowed;however,all sources of data must generate the appropriate clock regardless of how they clock receive data.RXRXCLKTXTXCLKPHYMACCRSCOL RX_CKRX_DV RX_ERRXD[7:0]GTX_CLKTX_CLK TX_ENTX_ER88TXD[7:0]802.3z Transmit PCS802.3z Receive PCS802.3z SynchCOL RX_CLKRX_DV RX_ER RXD[7:0]GTX_CLKTX_CLK TX_EN TX_ER TXD[7:0]CRS 8802.3z Synch802.3z Transmit PCS8802.3z Receive PCSFigure 1SGMII Connectivity802.3z Auto-Negotiation 802.3z Auto-NegotiationSerial-GMII Specification: ENG-46158Revision 1.7The link_timer inside the Auto-Negotiation has been changed from 10msec to 1.6msec to ensure a prompt update of the link status.Clearly,SGMII’s 1.25Gbaud transfer rate is excessive for interfaces operating at 10or 100Mbps.When these situations occur,the interface “elongates”the frame by replicating each frame byte 10times for 100Mbps and 100types for 10Mbps.This frame elongation takes place “above”the 802.3z PCS layer,thus the start frame delimiter only appears once per frame.The 802.3z PCS layer may remove the ﬁrst byte of the “elongated” frame.Bit Number tx_conﬁg_Reg[15:0] sent from the PHY to the MACtx_conﬁg_Reg[15:0] sent from the MAC to the PHY 15Link: 1 = link up, 0 = link down0: Reserved for future use 14Reserved for Auto-Negotiation acknowledge as speciﬁed in 802.3z 1130: Reserved for future use0: Reserved for future use 12Duplex mode: 1 = full duplex, 0 = half duplex 0: Reserved for future use 11:10Speed: Bit 11, 10:1 1 = Reserved1 0 = 1000 Mbps: 1000BASE-TX, 1000BASE-X 0 1 = 100 Mbps: 100BASE-TX, 100BASE-FX 0 0 = 10 Mbps: 10BASET, 10BASE2, 10BASE50: Reserved for future use9:10: Reserved for future use 0: Reserved for future use 011table 1 Deﬁnition of Control Information passed between links via tx_conﬁg_Reg[15:0]Implementation SpeciﬁcationThis section discusses how this SGMII interface shall be implemented by incorporating and modifying the PCS layer of the IEEE Speciﬁcation 802.3z.Signal Mapping at the PHY sideFigure 2shows the PHY functional block diagram.It illustrates how the PCS layer shall be modiﬁed and incorporated at the PHY side in the SGMII interface.At the receive side,GMII signals come in at 10/100/1000Mbps clocked at 2.5/25/125MHz.The PHY passes these signals through the PHY Receive Rate Adaptation to output the 8-bit data RXD[7:0]in 125MHz clock domain.RXD is sent to the PCS Transmit State Machine to generate an encoded 10-bit segment ENC_RXD[0:9].The PHY serializes ENC_RXD[0:9]to create RX and sends it to the MAC at 1.25Gbit/s data rate along with the 625MHz DDR RXCLK.At the transmit side,the PHY deserializes TX to recover encoded ENC_TXD[0:9].The PHY passes ENC_TXD[0:9]through the PCS Receive State Machine to recover the GMII signals.In the mean time,Synchronization block checks ENC_TXD[0:9]to determine the synchronization status between links,and to realign if it detects the loss of synchronization.RXRXCLK CRSRX_CLK @RX_DV RX_ER RXD[7:0]TX_CLKTX_EN TX_ER TXD[7:0]GMII Signals from 10/100/1000PHYPHY Receive Rate AdaptationRX_CLK @2.5/25/125 MHzMACRX RXCLKPCS TransmitState Machine10from 802.3zSeri-ENC_RXD[0:9]alizerRX_CLKRX_DV RX_ER RXD[7:0]PCS ReceiveState Machinefrom 802.3zTX_CLK @TX_EN TX_ER TXD[7:0]Synchronization Figure 36-9Figure 36-7Figure 36-5,Figure 36-6Deseri-alizer10ENC_TXD[0:9]Auto-Negotiation Figure 37-6TX TXCLK PCS Layer from 802.3z Figure 36-2GMII Signals to 10/100/1000PHYPHY Transmit Rate AdaptationTX_CLK @2.5/25/125 MHzPHYCOL125 MHz125 MHzFigure 2PHY Functional BlockSerial-GMII Specification: ENG-46158Revision 1.7The decoded GMII signals have to pass the PHY Transmit Rate Adaptation block to output data segments according to the PHY port speed.To make the PCS layer from 802.3z work properly,the PHY must provide a frame started with at least two preamble symbols followed by a SFD symbol.To be more speciﬁc,at the beginning of a frame,RXD[7:0]in Figure 2shall be {8’h55,8’h55,(8’h55.....),8’hD5}followed by valid frame data.Signal Mapping at the MAC SideFigure 3shows the MAC functional block diagram.It illustrates how the PCS layer shall be modiﬁed and incorporated at the MAC side in the SGMII interface.At the receive side,the MAC deserializes RX to recover encoded ENC_RXD[0:9].The MAC passes ENC_RXD[0:9]through the PCS Receive State Machine to recover the GMII signals.In the mean time,Synchronization block checks ENC_RXD[0:9]to determine the synchronization status between links,and to realign once it detects the loss of synchronization.The decoded GMII signals have to pass the MAC Receive Rate Adaptation block to output data segments according to the PHY port speed,passed from the PHY to MAC via Auto-Negotiation process.At the transmit side,GMII signals come in at 10/100/1000Mbps data clocked at 2.5/25/125MHz.The MAC passes these signals through the MAC Transmit Rate Adaptation to output theRX RXCLKTXTXCLKPCS Layer from 802.3z Figure 36-2PHY10Seri-ENC_TXD[0:9]alizer Deseri-alizer 10ENC_RXD[0:9]RX_CLKRX_DVRX_ER RXD[7:0]PCS Receive State Machinefrom 802.3z RX_CLK @RX_DV RX_ER RXD[7:0]Synchronization Figure 36-7TX_CLK @TX_EN TX_ER TXD[7:0]TX_CLKTX_ENTX_ER TXD[7:0]PCS Transmit State Machinefrom 802.3z Auto-NegotiationMACGMII Signals to 10/100/1000PHYMAC Transmit Rate AdaptationSpeed InformationGMII Signals from 10/100/1000PHYMAC Receive Rate AdaptationSpeed InformationFigure 3MAC Functional BlockCRSFigure 37-6Figure 36-5Figure 36-6Figure 36-9COL 125 MHz125 MHzAND8-bit data TXD[7:0]in125MHz clock domain.TXD is sent to the PCS Transmit State Machine to generate an encoded10-bit segment ENC_TXD[0:9].The MAC serializes ENC_TXD[0:9]to create TX and sends it to the PHY at1.25Gbit/s data rate along with the 625 MHz DDR TXCLK.Control Information Exchanged Between LinksAs described in Overview,it is necessary for the PHY to pass control information to the MAC to notify the change of the link status.SGMII interface uses Auto-Negotiation block to pass the control information via tx_conﬁg_Reg[15:0].If the PHY detects the control information change,it starts its Auto-Negotiation process, switching its Transmit block from“data”to“conﬁguration”state and sending out the updated control information via tx_conﬁg_Reg[15:0].The Receive block in the MAC receives and decodes control information,and starts the MAC’s Auto-Negotiation process.The Transmit block in the MAC acknowledges the update of link status via tx_conﬁg_Reg[15:0]with bit14 asserted,as speciﬁed in Table1.Upon receiving the acknowledgement from the MAC,the PHY completes the auto-negotiation process and returns to the normal data process.As speciﬁed in Overview,inside the SGMII interface,the Auto-Negotiation link_timer has been changed from10msec to1.6msec,ensuring a prompt update of the link status.The expected latency for the update of link is3.4msec(two link_timer time+an acknowledgement process).Data Information T ransferred Between LinksBelow we brieﬂy describe at receive side how GMII signals get transferred across from the PHY and recovered at the MAC by using the8B/10B transmission code.The same method applies to the transmit side.According to the assertion and deassertion of RX_DV,the PHY encodes the Start_of_Packet delimiter(SPD/S/)and the End_Of_Packet delimiter(EPD)to signal the beginning and end of each packet. The MAC recovers RX_DV signal by detecting these two delimiters.The PHY encodes the Error_Propagation(/V/)ordered_set to indicate a data transmission error. The MAC asserts RX_ER signal whenever it detects this ordered_set.CRS is not directly encoded and passed to the MAC.To regenerate CRS,the MAC shall uses signal RX_DV before it is being passed to the MAC Receive Rate Adaptation block as shown in Figure 3.The MAC decodes ENC_RXD[0:9] to recover RXD[7:0].Bellow Figure4illustrates how the MAC samples data in100Mbit/s mode.As signals shown in Figure2,the GMII data in100Mbit/s mode get replicated ten times after passing through the PHY Receive Rate Adaptation to generate RXD[7:0].The modiﬁed PCS Transmit State Machine encodes RXD[7:0]to create ENC_RXD[0:9].As noted in the Overview,the SPD(/S/ )only appears once per frame.SAMPLE_EN is a MAC internal signal to enable the MAC sampling of data starting at theﬁrst data segment(/S/)once every ten data segments in100 Mbit/s mode.A note to Figure4:there is noﬁxed boundary for the data sampling.Also theﬁrst byte of preamble might be only repeated9/99instead of10/100times due to the algorithm of the 802.3z PCS Transmit State Machine.Serial-GMII Specification: ENG-46158Revision 1.7LVDS AC/DC SpeciﬁcationThe basis of the LVDS and termination scheme can be found in IEEE1596.3-1996.Some parameters have been modiﬁed to accommodate the 1.25Gb/s requirements.SGMII consists of the most lenient DC parameters between the general purpose and reduced range LVDS.Both the data and clock signals are DC balanced;therefore,implementations that meet the AC parameters but fail to meet the DC parameters may be AC coupled.Figure 5shows the DDR circuit at the source of the LVDS.The circuit passes data and clock with a 90 degree phase difference. The receiver samples data on both edges of the clock.125 MHz ClockData in 100Mbit/sRXD[7:0] after Figure 4Data Sampling in 100 Mbit/s modeD0D0D0D0D0D0D0D0D0D0D1D1D1D1D1D1D1D1D1D1D2D2D2D2D2D2D2D2D2Data0Data1Data2ENC_RXD[0:9]/S/d0d0d0d0d0d0d0d0d0d1d1d1d1d1d1d1d1d1d1d2d2d2d2d2d2d2d2d2SAMPLE_ENRX_DVDomain Rate Adaptation D Q QND Q QNDataRX1.25 GHz Clock625 MHz DDR ClockFigure 5Reference data and clock circuitRXCLK Figure 6Driver Clock and Data AlignmentRXRXRXCLK RXCLK (single ended)(differential)(single ended)(differential)tclock2q (min)tclock2q (max)Symbol a a.For a detailed description of the symbols please refer to the IEEE1596.3-1996 standardParameter bb.All parameters measured at R load = 100ohms +-1% loadMin Max Units V oh Output voltage high,1525mV V ol Output voltage low 875mV Vring Output ringing10%|V od|Output Differential V oltage 150400mV V os Output Offset V oltage 10751325mV Ro Output impedance (single ended)40140ohms ∆Ro Mismatch in a pair10%∆|V od|Change in V od between “0”and “1”25mV ∆V os Change in V os between “0”and “1”25mV Isa, Isb Output current on Short to GND 40mA Isab Output current when a, b are shorted12mA Ixa, IxbPower off leakage current10mAtable 2 Driver DC speciﬁcationSymbol ParameterMin Max Units Vi Input V oltage range a or b 6751725mV Vidth Input differential threshold -50+50mV Vhyst Input differential hysteresis 25mv RinReceiver differential input impedance80120ohmstable 3 Receiver DC speciﬁcationSymbol a a.For a detailed description of the symbols please refer to the IEEE1596.3-1996 standardParameterMin Max Units clock Clock signal duty cycle @625MHz4852%t fall V od fall time (20%-80%)100200pSec t rise V od rise time (20%-80%)100200pSec t skew1bb.Skew measured at 50% of the transition Skew between two members of a differential pair - |tp HLA -tp LHB | or |tp LHA - tp HLB |20pSect clock2q cc.Skew measured at 0v differentialClock to Data relationship:from either edges of the clock to valid data250550pSectable 4 Driver AC speciﬁcationSerial-GMII Specification: ENG-46158Revision 1.7Symbol Parameter Min Max Unitst setup a setup time100pSect hold hold time100pSectable 5 Receiver AC speciﬁcationa.Measured at 50% of the transitionRepresentative Timing BudgetA transmit and receive path timing budget provided in the table below.The exact allocation ofthe budget is implementation speciﬁc;however,veriﬁcation of overall requirements are testedagainst the speciﬁcations in the tables external to the packaged integrated circuit.Element Value UnitsEffective clock period800psCycle to cycle clock jitter100 ps peak-peakImperfect duty cycle30 ps peak-peakData dependent jitter70 ps peak-peakStatic package skew100 ps peak-peakRemaining window500 (250 ps clock2q)ps peak-peaktable 6 Timing budget for driver requirementsElement Value UnitsDriver window500ps peak-peakStatic package skew100ps peak-peakReceiver setup time100ps peak-peakRemaining window300ps peak-peaktable 7 Timing budget for receiver requirementsThis budget shows the driver generating a data signal with a500ps eye centered around thesampling clock edge(see Figure6“Driver Clock and Data Alignment”on page8).Thereceiver will add additional skew, leaving 300 ps of margin.Cisco Systems Intellectual PropertyCisco Systems has released its proprietary rights to information contained in this document forthe express purpose of implementation of this speciﬁcation to encourage others to adopt thisinterface as an industry standard.Any company wishing to use this speciﬁcation may do so ifthey will in turn relinquish their proprietary rights to information contained or referencedherein.Any questions concerning this release should be directed to the Robert Barr,WorldWide Patent Counsel, Cisco Systems, 300 East Tasman Drive, San Jose, CA.。

标准通用标记语言

标准通用标记语言（SGML）的相关标准和规范1. 引言标准通用标记语言（Standard Generalized Markup Language，简称SGML）是一种面向文档结构化的标记语言，它提供了一种通用的方法来定义文档结构和内容。

SGML的发展和应用对于现代信息交流和文档管理起到了重要的推动作用。

本文将详细描述SGML的相关标准和规范，包括标准的制定、执行和效果等。

2. SGML的发展与背景SGML最早由IBM公司在1969年提出，并于1986年被国际标准化组织（ISO）正式批准为国际标准。

在此之前，各个领域使用不同的方式来描述文档结构和内容，导致了信息交流困难、数据共享复杂等问题。

SGML的出现解决了这些问题，成为一种公认的通用标记语言。

3. SGML相关标准与规范3.1 SGML ISO 8879 标准ISO 8879是SGML最基本、最重要的国际标准，定义了SGML的语法、基本概念、处理模型等方面内容。

该标准确立了SGML作为一种通用标记语言的地位，为后续标准和规范的制定提供了基础。

3.2 SGML DTDSGML文档类型定义（Document Type Definition，简称DTD）是SGML的一个重要组成部分，用于定义文档结构和内容。

DTD描述了文档中可以使用的元素、属性、实体等，并规定了它们之间的关系。

DTD使得不同应用领域可以共享和交换文档结构。

3.3 SGML样式表SGML样式表是一种用于描述如何将SGML文档转换为可视化形式（如网页、打印版等）的标准和规范。

样式表定义了元素在可视化输出中的呈现方式，包括字体、颜色、布局等方面。

常见的SGML样式表包括DSSSL（Document Style Semantics and Specification Language）和XSL（Extensible Stylesheet Language）。

3.4 SGML应用规范除了上述基本标准外，还有一些针对特定应用领域制定的SGML应用规范。

sgmii_specification

使用altera FPGA soft-CDR模式的SGMII接口实现

GE电口速率自协商问题(SGMII SERDES)

GE电口速率自协商问题-经典问题解析

QSGMII

SGMII

SGM常用缩略语解释(May 2003)

以太网链路连接

QSGMII协议详解ppt课件

gig_eth_mac模块的说明

SP1000A芯片规格说明书

VSC8211 链接 CPU 与 R GMII 接口的 SGMII 基础交换机说明书

SGMII Specification

世界各国认证详细版

SGM 上海通用汽车 对供应商质量要求的规定概要

gig_eth_pcs_pma_ds264

常用接口介绍

sgmii_specification

标准通用标记语言

SGM 上海通用汽车对供应商质量要求的规定概要