MEMORY存储芯片MT41K128M16JT-107中文规格书

Table 92: DQ Input Receiver Specifications (Continued)
Notes: 1.All Rx mask specifications must be satisfied for each UI. For example, if the minimum in-
put pulse width is violated when satisfying TdiVW (MIN), V diVW,max , and minimum slew
rate limits, then either TdiVW (MIN) or minimum slew rates would have to be increased
to the point where the minimum input pulse width would no longer be violated.
2.Data Rx mask voltage and timing total input valid window where V diVW is centered
around V CENTDQ,midpoint after V REFDQ training is completed. The data Rx mask is applied
per bit and should include voltage and temperature drift terms. The input buffer design
specification is to achieve at least a BER =1e- 16 when the Rx mask is not violated.
3.Defined over the DQ internal V REF range 1.
4.Overshoot and undershoot specifications apply.
5.DQ input pulse signal swing into the receiver must meet or exceed V IHL(AC)min . V IHL(AC)min
is to be achieved on an UI basis when a rising and falling edge occur in the same UI (a
valid TdiPW).
6.DQ minimum input pulse width defined at the V CENTDQ,midpoint .
7.DQS-to-DQ Rx mask offset is skew between DQS and DQ within a nibble (x4) or word
(x8, x16 [for x16, the upper and lower bytes are treated as separate x8s]) at the SDRAM
balls over process, voltage, and temperature.
8.DQ-to-DQ Rx mask offset is skew between DQs within a nibble (x4) or word (x8, x16) at
the SDRAM balls for a given component over process, voltage, and temperature.
9.Input slew rate over V diVW mask centered at V CENTDQ,midpoint . Slowest DQ slew rate to
fastest DQ slew rate per transition edge must be within 1.7V/ns of each other.
10.Input slew rate between V diVW mask edge and V IHL(AC)min points.
The following figure shows the Rx mask relationship to the input timing specifications
relative to system t DS and t DH. The classical definition for t DS/t DH required a DQ rising
8Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Single-Ended Input Measurement Levels
Table 14: MR2 Register Definition (Continued)
Note: 1.Not allowed when 1/4 rate gear-down mode is enabled.8Gb: x4, x8, x16 DDR4 SDRAM Mode Register 2。