vivado区域约束语法

vivado区域约束语法
## Vivado Region Constraints Syntax.
Vivado region constraints are used to define the
physical location of specific elements of the design within the programmable logic of the target device. This can be useful for optimizing performance and meeting timing requirements.
The syntax for region constraints in Vivado is as follows:
create_pblock [<hierarchical_name>] <block_name>
[<type>]
set_property <property_name> <property_value> [<object>]
<hierarchical_name> specifies the hierarchical path to the block that you want to constrain. This can be a single block, or a group of blocks.
<block_name> specifies the name of the block that you want to constrain.
<type> specifies the type of block that you want to constrain. This can be a logic block, a memory block, or a I/O block.
<property_name> specifies the name of the property that you want to set. This can be any of the properties that are supported by the block that you are constraining.
<property_value> specifies the value that you want to set for the property.
The following are some examples of region constraints:
create_pblock i_top io_clk IO.
set_property LOC CLK_IO IOBUFDS_GTE3[0] [get_ports
i_top/io_clk]
This constraint will create a physical block named
`io_clk` and will place it in the `CLK_IO` region of the device. The `IOBUFDS_GTE3[0]` port of the `i_top` block
will be connected to the `io_clk` block.
create_pblock i_top u_reg FF.
set_property LOC L6 [get_cells i_top/u_reg]
This constraint will create a physical block named
`u_reg` and will place it in the `L6` region of the device. All of the cells in the `i_top/u_reg` block will be placed within the `u_reg` physical block.
create_pblock i_top mmcm_inst MMCME2。

set_property LOC I2 [get_cells i_top/mmcm_inst]
set_property BEL URAM [get_cells i_top/mmcm_inst]
This constraint will create a physical block named
`mmcm_inst` and will place it in the `I2` region of the
device. The cells in the `i_top/mmcm_inst` block will be placed in the `URAM` memory resource.
## Vivado 区域约束语法。

Vivado 区域约束用于定义目标器件可编程逻辑中设计特定元素
的物理位置。

这对于优化性能和满足时序要求很有用。

Vivado 中区域约束的语法如下：
create_pblock [<hierarchical_name>] <block_name>
[<type>]
set_property <property_name> <property_value> [<object>]
<hierarchical_name> 指定要约束的模块的分层路径。

这可以
是单个模块或一组模块。

<block_name> 指定要约束的模块的名称。

<type> 指定要约束的模块类型。

这可以是逻辑模块、存储器模
块或 I/O 模块。

<property_name> 指定要设置的属性的名称。

这可以是受要约束模块支持的任何属性。

<property_value> 指定要为属性设置的值。

以下是区域约束的一些示例：
create_pblock i_top io_clk IO.
set_property LOC CLK_IO IOBUFDS_GTE3[0] [get_ports
i_top/io_clk]
此约束将创建一个名为 `io_clk` 的物理模块，并将其放置在器件的 `CLK_IO` 区域中。

`i_top` 模块的 `IOBUFDS_GTE3[0]` 端口将连接到 `io_clk` 模块。

create_pblock i_top u_reg FF.
set_property LOC L6 [get_cells i_top/u_reg]
此约束将创建一个名为 `u_reg` 的物理模块，并将其放置在器
件的 `L6` 区域中。

`i_top/u_reg` 模块中的所有单元格都将放置在 `u_reg` 物理模块中。

create_pblock i_top mmcm_inst MMCME2。

set_property LOC I2 [get_cells i_top/mmcm_inst]
set_property BEL URAM [get_cells i_top/mmcm_inst]
此约束将创建一个名为 `mmcm_inst` 的物理模块，并将其放置在器件的 `I2` 区域中。

`i_top/mmcm_inst` 模块中的单元格将放置在 `URAM` 存储器资源中。