用FPGA实现的七段数码管vhdl代码
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Output(7 downto 0)
具体设计:
Vhd代码:
library IEEE;
use Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code.
--library UNISIM;
--use sevenled_vhd is
Port (
input : in STD_LOGIC_VECTOR (3 downto 0);
led : out STD_LOGIC_VECTOR (7 downto 0)); end sevenled_vhd;
architecture Behavioral of sevenled_vhd is
begin
led<= "" when input="0000" else -- 0
"" when input="0001" else -- 1
"" when input="0010" else -- 2
"" when input="0011" else -- 3
"" when input="0100" else -- 4
"" when input="0101" else -- 5
"" when input="0110" else -- 6
"" when input="0111" else -- 7
"" when input="1000" else -- 8
"" when input="1001" else -- 9
"" when input="1010" else -- A
"" when input="1011" else -- b
"" when input="1100" else -- c
"" when input="1101" else -- d
"" when input="1110" else -- E
""; -- F
end Behavioral;
管脚约束:
Net "led<7>" LOC=N19;
Net "led<6>" LOC=N15;
Net "led<5>" LOC=R20;
Net "led<4>" LOC=R18;
Net "led<3>" LOC=U20;
Net "led<2>" LOC=T18;
Net "led<1>" LOC=U18;
Net "led<0>" LOC=W20;
Net "input<3>" LOC=F18;
Net "input<2>" LOC=G20;
Net "input<1>" LOC=J18;
Net "input<0>" LOC=L18;
综合结果:
仿真:
wait for 100ms; --0
input<="0000";
wait for 100ms; --1
input<="0001";
wait for 100ms; --2
input<="0010";
wait for 100ms; --3
input<="0011";
wait for 100ms; --4
input<="0100";
wait for 100ms; --5
input<="0101";
wait for 100ms; --6
input<="0110";
wait for 100ms; --7
input<="0111";
wait for 100ms; --8
input<="1000";
wait for 100ms; --9
input<="1001";
wait for 100ms; --A
input<="1010";
wait for 100ms; --B
input<="1011";
wait for 100ms; --C
input<="1100";
wait for 100ms; --D
input<="1101";
wait for 100ms; --E
input<="1110";
wait for 100ms; --F
input<="1111";
烧录程序结果
扩展板由8个数码管,选择其中一个显示。将5V电源连接到其中一个数码管。