FDLL4150_NL中文资料

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士兰微电子LED照明驱动产品及方案-FC

R22 U3 R23
D5
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Silan 士兰微电子
AC-DC LED Lighting Solutions AC-DC LED 照明驱动产品及方案
SD7530 功率因数校正控制器
关键参数列表
典型参数 VCC极限电压值 VCC工作电压最大值 VCC开启电压值 VCC关闭电压值 VCC过压保护值 IC启动电流原边OCP比较点输入UVLO 输入OVP GATE钳位电压短路保护
Silan 士兰微电子
DC-DC LED 照明驱动产品及方案
Company Confidential, don’t copy
Silan 士兰微电子
DC-DC LED 照明驱动产品及方案
型号 SD42522 SD42524 SD42525 SD42527 SD42560 SD42565 SD42566 SD42567
SD7530
40V 32V 17V 9V 33.5V 5uA 1.7V 0.95V 4.5V 15V 专利
Company Confidential, don’t copy
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Silan 士兰微电子
VCC特性描述
AC-DC LED Lighting Solutions AC-DC LED 照明驱动产品及方案

SILAN LED 照明驱动产品及解决方案
Find what we can do……
Up d 201 ate 2.3
Silan 士兰微电子
LED 照明驱动产品及方案
DC-DC LED 照明驱动产品
◆ SD4252X 系列 -降压型(BUCK) ◆ SD42560 - 升-降压型(BUCK-BOOST) ◆ 80V高压系列（升压SD42566，降压SD42565，升/降压SD42567）

雷达液位计规格书

1REV234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950罐旁安装LCD 1/2"NPT 外壳材质 Case Mat'l 铝外壳带涂层指示仪T a n k I n d i c a t o r型号 Model形式 Type显示内容 Display Content 电气接口 Elec. Conn.电源 Power Supply电气接口 Elec. Conn.24VDC 1/2"NPT 防护等级 Enclosure Protection 防爆等级 Explosion ProofIP65ExdIICT4接点形式 Contact Form 接点数量 Contact Quantity 接点容量 Cont. Current Rating 接点作用形式 Contact Action压力输入信号 Input Pressure Signal 油水界面输入信号 Input Interface Signal 辅助输出Auxiliary　Output 负载阻抗 Load Resistance 4～20mA DC温度输入信号 Input Temp. Signal Type温度点数Cell Quantity变送单元T r a n s m i t t e r U n i t型号 Model安装形式 Mounting Type 输出信号 Output Signal 总线标准Field Bus Standard法兰材质 Flange Mat'l 法兰密封面 Facing 碳钢RF计量认证Measure　Proof 延伸管长度 Extend Length 过程连接形式 Proce.Conn.连接规格 Conn.Size 法兰8"法兰标准 Flange STD 法兰等级 Flange Rating ANSI B16.5ANSI CL150天线形式 Antenna Type 天线材质 Antenna Mat'l 喇叭口316SS 导波管尺寸 Still Pipe Size 导波管材质 Still Pipe Mat'l 316SS 辅助测量Auxiliary　Measure 罐底水位量程Interface Range工作温度 Process Temp.(℃)压力等级 Press. Rating ANSI CL150液位±3mm测量范围 Meas. Range0～18m设备法兰高度 Nozzle Height (mm)250mm液位计L e v e l G a u g e型号 Model型式 Type测量功能Function 精度 Level Accuracy法兰面距测量基准点 Distance from Flange Face to Measure Base Point (mm)设备高度 Vessle Height (mm)设备直径 Vessle Diameter (mm)16.5m11m操作温度 Operation Temp.(℃)设计温度 Design Temp.(℃)55雷达与设备壁距离 Distance from Instrument to Vessle Wall(mm)1500mm下部介质 Lower Fluid 介电常数 Dielectric Constant操作压力 Oper. Press. MPa(G)设计压力 Des. Press. MPa(G)0.165工艺条件P r o c e s s C o n d i t i o n s环境温度 Environment Temp.(℃)介质表面状态 Fluid Surface State上部介质 Upper Fluid介电常数 Dielectric Constant 水检测位置 Service 冷焦水储水罐D-132设备材质 Vessle Mat'l 设备等级 Vessle Class(RADAR LEVEL TRANSMITTER )页数 PAGE ：第1页共3页概况G e n e r a l仪表位号 Tag NumberLT-7002流程图号 P&ID No.A10400WS-DW02-0001仪表规格书（雷达液位计）档案号 DOCUMENT No ：A10400IN-SP01-1001(16)INSTRUMENT SPECIFICATION 设计阶段 STAGE ：详细工程设计版本:AFC IP65ExdIICT4外壳材质 Case Mat'l 供电电源 Power Supply铝外壳带涂层防护等级 Enclosure Protection 防爆等级 Explosion Proof 带隔离阀尺寸 Isolated Valve Size 隔离阀材质 Isolated Valve Mat'l清洗和吹扫接管Clean & Flush Conn.Pipe防护罩 Enclosure Shield安装支架 Bracket其他M i s c e l l推荐制造商 Manufacturer 附件A c c e s s o r i e s浪涌保护器 Surge Protection Device本表数据未经SEI书面允许不得扩散至第三方1REV2345678910111213141516171819202122232425262728293031323334353637383940414243444546说明 NOTES ：带20m连接电缆。

1N4148、1N4150、1N4448 开关二极管

Appendix1-Rev1.0
“电子爱好者”网站是一个面向广大电子爱好者、大专院校学生、中小型企业工程技术人员的电子技术应用、推广专业网站。主要内容有：电子技术应用交流，器件资料、电子设计软件下载，电子技术支持服务，电子产品发布、转让和引进等信息。
本资料由＂电子爱好者＂网站收集整理，版权属原作者
The products listed in this document are designed to be used with ordinary electronic equipment or devices (such as audio visual equipment, office-automation equipment, communications devices, electrical appliances and electronic toys). Should you intend to use these products with equipment or devices which require an extremely high level of reliability and the malfunction of with would directly endanger human life (such as medical instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers and other safety devices), please be sure to consult with our sales representative in advance.

NS4150 用户手册说明书

NS4150用户手册V1.0深圳市纳芯威科技有限公司2011年05月修改历史目录1功能说明 (5)2主要特性 (5)3应用领域 (5)4典型应用电路 (5)5极限参数 (6)6电气特性 (6)7芯片管脚描述 (7)7.1MSOP8和SOP8管脚分配图 (7)7.2管脚功能描述..............................................................................................................................77.3芯片印章说明 (8)8NS4150典型参考特性 (8)9NS4150应用说明 (10)9.1原理框图 (10)9.2工作原理 (11)9.3无需输出滤波器 (11)9.4上电,掉电噪声抑制 (11)9.5EMI增强技术 (11)9.6CTRL引脚设置 (11)9.7效率 (12)9.8保护电路....................................................................................................................................129.9应用信息 (12)10芯片的封装 (13)10.1MSOP-8封装尺寸图 (13)10.2SOP-8封装尺寸图 (14)图目录图1NS4150典型应用图 (5)图2MSOP8和SOP8管脚分配图(top view) (7)图3印章说明 (8)图4NS4150功能框图 (10)图5EMI测试频谱图 (11)图6差分和单端输入方式 (12)图7磁珠与电容 (12)图8MSOP-8封装尺寸图 (13)图9SOP-8封装尺寸图 (14)表目录表1芯片最大物理极限值 (6)表2NS4150电气特性表 (6)表3NS4150管脚描述 (7)表4工作模式 (11)1功能说明NS4150是一款超低EMI、无需滤波器3W单声道D类音频功率放大器。

管网运行状态监测设备

管网运行状态监测设备一体式管网监测设备---产品概述---自来水公司的管网监测点多布设在地下表井内，通常无电源且环境潮湿，这给管网监测工作带来了很大困难。

为此设计了低功耗、防水性能好的管网运行状态监测设备（一体式管网监测设备）。

---产品特点---◆防水性能好：采用密封防水外壳、防水天线和防水接线盒，防水等级IP68。

◆超低功耗：待机电流≤50uA/14.4V；采集电流≤5mA/14.4V；发送平均电流≤10mA/14.4V。

◆电池寿命长：电池寿命1~5年，可内置1组或外置4组锂电池，每组电池支持1万次的数据发送。

◆存储容量大：可存储不少于1年的历史数据。

◆维护方便：可远程设置工作参数、远程升级程序。

◆接入灵活：可接入平升公司配套的上位机系统，也可接入组态软件或用户自行开发的监控软件。

---产品功能---◆采集功能：实时采集压力、流量、水质等数据；采集电池电压。

◆通信功能：采用GPRS或短消息上报数据；支持定时上报、越限报警；支持多中心上报。

◆存储功能：本机循环存储监测数据。

◆显示功能：LCD液晶面板显示当前监测数据和工作参数（DATA-6216型）。

◆对外供电功能：可对外提供5V、12V直流电源，为压力变送器供电。

◆报警功能：压力超限、设备连线中断或电池电压过低时，立即上报告警信息。

---现场安装图片---沈阳市管网监测现场呼和浩特市管网监测现场兰州市管网监测现场唐山市管网监测现场压力变送器防水接线盒一体式管网监测设备DATA-6218 一体式管网监测设备DATA-6216管网运行状态监测设备分体式管网监测设备---产品概述---管网监测现场通常为窨井，存在无电源、环境潮湿、GPRS信号弱等诸多问题，给管网监测带来了很多困难。

分体式管网监测设备采用井下、井上分体安装，433MHZ和GPRS通信互补的方式有效解决了上述难题。

分体式管网监测设备由433M微功耗测控终端和无线数传网关两部分组成，可精确采集安装在地下表井内的流量计/脉冲水表、压力变送器、水位变送器等仪表数据。

slf系列贴片电感datasheet

SLF 系列 SLF6025
特点 ●是最适用于电源系统的低直流电阻，大电流，节能型产品。 ●因采用磁力屏蔽结构，所以可实现高密度安装。 ●底面为平直的低背型 , 可稳定地安装在电路板上。 ●采用卷带仕样，支持自动插入机。用途手机，计算机，硬盘驱动器，其他各种电子设备仕样
工作温度范围保存温度范围 –20 to +85°C ［包括自身温度上升］ –40 to +85°C ［产品单体］
电气特性
电感 (H) 4.7 6.8 10 15 22 33 47 68 100 150 220 电感容差 ±20% ±20% ±20% ±20% ±20% ±20% ±20% ±20% ±20% ±20% ±20% L 测定频率 (kHz) 100 100 100 100 100 100 100 100 100 100 100 直流电阻 ( )±20% 0.0284 0.0354 0.0532 0.0745 0.104 0.148 0.21 0.29 0.43 0.65 0.98 额定电流 (A) 基于电感变化率时 1.6max. 1.5max. 1.3max. 1max. 0.77max. 0.69max. 0.59max. 0.5max. 0.42max. 0.34max. 0.26max. 基于温度上升时 2.5typ. 2.2typ. 1.8typ. 1.4typ. 1.3typ. 1.1typ. 0.92typ. 0.78typ. 0.64typ. 0.5typ. 0.38typ. 品名 SLF6028T-4R7M1R6-PF SLF6028T-6R8M1R5-PF SLF6028T-100M1R3-PF SLF6028T-150M1R0-PF SLF6028T-220MR77-PF SLF6028T-330MR69-PF SLF6028T-470MR59-PF SLF6028T-680MR50-PF SLF6028T-101MR42-PF SLF6028T-151MR34-PF SLF6028T-221MR26-PF

TELLIS-24

TELLIS-24 RADIO REMOTE COTROLSYSTEM OPERATION MANUAL抚顺铝厂出铝设备无线遥控系统操作手册Grand Industrial Group Company Ltd.CANADA录1安全提示 (4)2系统概述 (5)2.1 RC2012A手持遥控器（发射机） (6)2.2 BD2124接收驱动装置 (6)2.3 RBD2124系统 (6)3RC2012A手持遥控器（发射机） (6)3.1 RC2012A的控制元件 (6)3.2 操作信息 (7)4BD2124 接收驱动装置 (8)4.1 BD2124的控制输出 (8)4.2 操作信息 (10)4.3 供电电源 (12)5系统安装 (12)5.1 RC2012A电池的安装 (12)5.2 BD2124接收驱动装置的安装 (13)5.3 BD2124接收驱动装置的接线 (13)5.4 BD2124电源连接 (14)5.5 典型电源及输出接线 (14)6系统操作 (15)6.1 安全操作 (15)6.2 RC2012A手持遥控器的使用 (15)6.3 操作信息 (17)7故障诊断和排除 (17)8维护和保养 (18)9技术指标 (19)10相关标准 (20)此页为空白1 安全提示使用前请仔细阅读以下安全提示注意：未经许可，任何非指定的人员对设备进行改动或修改都有可能造成该遥控系统和所控设备无法工作！如果不严格遵守此安全警告有可能导致所遥控设备和本系统的非正常运行，并可能造成人员伤亡！安装1．提供安全电源开关：设备维修时该装置必须与主电源断开。

2．使用正确的导线接线：松动或破损的导线有可能导致系统失灵、操作中断、设备损坏、或带来人身安全隐患。

3．不要在高温环境下安装：温度超过摄氏70度下安装有可能损坏设备。

操作人员安全须知1. 开机操作前，操作人员必须确认所控设备周围无障碍，并选择好自己做站位置可以全方位观察到所要控制的设备。

FCL 系列产品说明书

Free Chlorine Amperometric SensorsProduct InstructionsParts covered by this product data sheet include:FCL502, FCL505, FCL510, FC72, FCLA-5015, FCLA-5016, FCLA-5017, FCLA-50182.0 pHFree Chlorine (FCL) exists as hypochlorous acid and hypochlorite anion. The acid-base dissociation of FCL has a pKa of approximately 7.5. The FCL sensor responds to hypochlorous acid and hypochlorite anion with different sensitivity. In combination, an increase in pH reduces themea-sured FCL and decrease in pH increases the measured FCL. For the most accurate free chlorine measurement, keep system pH at <6.5.2.1 Chemical InterferencesThe sensor should not be used in water containing surfactants. Monochloramine and ozone are interferences.2.2 FlowTo acheive reproducible measurements, the (FCL) free chlorine require a specified constant flow rate. To avoid complications (such as bubbles), it is best to operate the sensors at a flow rate of 0.2 - 0.6 gpm if using flow cell FC72 or FC70 (old version). Use of a flowmeter is recommended (FM001- See Section 4.1)2.3 PressurePressure is relieved via a small vent hole covered with a silicone sleeve (FIG1). DO NOT REMOVE THE SLEEVE, even when refilling the sensor.Section 1.0Theory of Operation1.0 Free Chlorine DefinedFree Chlorine or "freely active chlorine" is defined as the sum of molecu-lar chlorine (Cl 2), hypochlorous acid (HOCl) and hypochlorite ions (OCl -). Molecular chlorine occurs at pH values <pH4. Hypochlorus acid and hypochlorite ions are in pH dependent equilibrium with one another. Hypochlorous acid is a much stronger disinfecting agent (oxidizer) as compared to hypochlorite ions.1.1 Sensor Operating PrincipleOnly hypochlorous acid (HOCl) diffuses through the membrane be-tween the cathode and sample solution. At the applied potential, only hyphochlorous acid is electrochemically reduced. HOCl is reduced to chloride ion at the gold cathode. At the same time, the silver anode is oxidized to form silver chloride (AgCl). When the concentration of HOCl at the cathode is dramatically decreased by electrochemical reduction, hypochlorite ion will be transformed into hypochlorous acid, and to some extent, by proton transfer. The release of electrons at the cathode and acceptance at the anode creates a current flow, which under constant conditions, is proportional to the free chlorine concen-tration in the medium outside the sensor. The resulting low currentoutput is then conditioned to 4-20mA current or Modbus 485 output by the sensor's onboard electronic circuitry.Section 2.0Factors Influencing the SensorpH CorrectionIf your system is >6.5 pH compensation should be applied to the measured output as follows:K(pH) = a 1 *pH 4 + a 2 *pH 3 + a 3 *pH 2 + a 4 *pH + a 5Where a 1= 0.006817 a 2= -0.000764468 a 3= -2.406291a 4= -23.75 a 5= -63.0508i corrected = [i measured - 4.2mA/k(pH), FCL(ppm) = i corrected /slopeFC72 Flow cellEnsure flow cell is mounted at 45 deg or higher above horizon-tal as shown in FIG 2B.4.1 Flow MeterTo control flow to the flow cell, a flow meter is recommended.Sensorex supplies model FM001 for this purpose. The FM001provides flow control from 0.1 to 1.0 GPM (0.5 to 4.0 LPM) with94% accuracy.FIG. 3SECTION 5.0Sensor Installation5.0 Sensor Installation into Flow Cella)First install threaded fitting onto sensor body (remove fitting if pre-installed in flow cell) FIG 2d b)Install snap-ring into groove on sensor bodyc)Next, slide o-ring onto body of sensor until it reaches bottom of threaded fitting.d) Thread sensor assembly into top of flow cell as shown in FIG 2c.e) Turn on flow and verify the flow through the Flow Cell is at least 0.2 gpm (45 liters/hour and no more than 0.6gpm (135 liters/hour).6.0 Electrical InstallationThe sensor is supplied in 2 output types, 4-20mA or Modbus 485.Ou tput of 4 mA in air and 20 mA at the top range of free chlorine output (0-2ppm, 0-5ppm and 0-10ppm) or Modbus 485.NOTE: The supply voltage to the Sensor must be 12-24 V DC with minimum of 250 mA. Maximum load is 1 Watt. The sensor has 2 wires, red (+), black (-). Attach the red wire to the power supply positive ter-minal (+) and the black wire to the PLC or DVM positive (+) terminal. Connect a wire (customer supplied) from the power suppy negative (-) and the PLC or DVM (-). See FIG 3. See FIG3A for Modbus connections.SECTION 6.0Electrical InstallationSECTION 7.0Sensor Conditioning7.0 Sensor ConditioningThe sensor requires conditioning prior to generating stable values.a) For new Sensors, connect the sensor to power and allow to run overnight (at least 12 hours) before calibration.b) If the Sensor will be un-powered for two hours or more, run for two hours prior to use.c) If the Sensor's flow will be off for one hour or less, run the sensor for at least one hour prior to recalibration.d) After membrane/electrolyte replacement, allow the Sensor to run powered overnight (at least 12 hours) before calibration .4.1.1 Install the flow meter and flow cell as shown in FIG 2C.Follow the diagram so that the incoming water is attached to the bottom of the flow meter (where flow adjustment knob is located).FIG. 7FIG. 6c) Adjust span/slope at PLC/4-20mA devic e for 4-20mA models only.d) Repeat this slope calibration one day after sensor is initially installed.e) Repeat the slope calibration weekly.Section 9.0Sensor Storage9.0 StorageStore sensor at 5o C - 50o C only and maximum humidity of 95% non-condensing.a) Short Term Storage (one week or less): Store in Flow cell with water to prevent the probe from drying out.b) Intermediate Term (one week to one month): Store with cap on sen-sor in a beaker with water to keep membrane wet.c) Long Term (one month or longer): Remove Membrane Cap and store cap completely immersed in tap water. Remove fill solution and pour down drain.Note: Electrolyte shelf life is one year from date of mfg (see bottle).Section 10.0Sensor Maintenance10.0 Membrane Cap ReplacementIf membrane replacement is required, a new cap with preinstalled mem-brane must be used. Two caps and 2 bottles of refill solution are shipped with each sensor. Additional caps are ordered as FCLA-5016, and refill solution as FCLA-5015.To change membrane cap:a) Turn sensor upside down with cap facing upward.b) Rotate cap counter-clockwise to remove (SEE FIG 5).c) Place needle tip on syringe as shown in FIG 6d) Remove solution from bottle with needle and syringe (FIG 7)e) Fill sensor body with electrolyte using needle and bottle of refill solution until it flows out of the holes near the cathode(SEE FIG 8).f) Add a few drops of electrolyte to the membrane cap (FIG 9)g) Install new membrane cap by threading cap onto sensor rotating cap clockwise (Opposite of FIG 5).DO NOT TOUCH THE CATHODE DURING THIS PROCESS SINCE IT CAN BE DAMAGED.F C LA -7000F C L A -7000FIG. 3A3. Pressure fluctuation in sample lineFCLA-7000Free Chlorine /Chlorine Dioxide Colorimeter-eXact 7+, requires CLDA-7001 strips5.58"(142mm)3.82"(97mm)2.25"(57mm)2.25"(57mm)4.61"(117mm)10.19"(259mm)3.78"(96mm)GPM LPMstay this way – do not put a flat on the cathode.7))Check tbrighter and shinier than before (FIG. 5) the operation using the abrasive paper. 8))as the gold surface can be easily damaged.membrane pocket (FIG. 7)the sensor.cap with a towel.10.0DAMAGE TO THE GOLD ELECTRODE.* *。

ADF4150

Fractional-N/Integer-N PLL SynthesizerData SheetADF4150Rev. ADocument FeedbackInformation furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners.O ne Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2011–2013 Analog Devices, Inc. All rights reserved. Technical Support FEATURESFractional-N synthesizer and integer-N synthesizer Programmable divide-by-1/-2/-4/-8/-16 output 5.0 GHz RF bandwidth3.0 V to 3.6 V power supply 1.8 V logic compatibilitySeparate charge pump supply (V P ) allows extended tuning voltage in 3 V systemsProgrammable dual-modulus prescaler of 4/5 or 8/9 Programmable output power level RF output mute function 3-wire serial interfaceAnalog and digital lock detectSwitched bandwidth fast-lock mode Cycle slip reductionAPPLICATIONSWireless infrastructure (W-CDMA, TD-SCDMA, WiMax, GSM, PCS, DCS, DECT) Test equipmentWireless LANs, CATV equipment Clock generationGENERAL DESCRIPTIONThe ADF4150 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers if used with an external voltage-controlled oscillator (VCO), loop filter, and external reference frequency.The ADF4150 is for use with external VCO parts and issoftware compatible with the ADF4350. The VCO frequency can be divided by 1/2/4/8/16 to allow the user to generate RF output frequencies as low as 31.25 MHz. For applications that require isolation the RF output stage can be muted. The mute function is both pin and software controllable.Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V and can be powered down when not in use. The ADF4150 is available in a 4 mm × 4 mm package.FUNCTIONAL BLOCK DIAGRAMFigure 1.CP OUTLDSW REF CLK DATA LEAV SDV DV V GND GND GNDR RF OUT +RF OUT –RF IN +RF IN –PDB RF08226-001ADF4150Data SheetRev. A | Page 2 of 28TABLE OF CONTENTSFeatures .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Characteristics ................................................................ 5 Absolute Maximum Ratings ............................................................ 6 Transistor Count ........................................................................... 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 9 Circuit Description ......................................................................... 11 Reference Input Section ............................................................. 11 RF N Divider ............................................................................... 11 INT, FRAC, MOD, and R Counter Relationship.................... 11 INT N Mode ................................................................................ 11 R Counter .................................................................................... 11 Phase Frequency Detector (PFD) and Charge Pump ............ 11 MUXOUT and Lock Detect ...................................................... 12 Input Shift Registers ................................................................... 12 Program Modes .......................................................................... 12 Output Stage ................................................................................ 12 Register Maps .................................................................................. 13 Register 0 ..................................................................................... 18 Register 1 ..................................................................................... 18 Register 2 ..................................................................................... 18 Register 3 ..................................................................................... 20 Register 4 ..................................................................................... 20 Register 5 ..................................................................................... 20 Initialization Sequence .............................................................. 20 RF Synthesizer—A Worked Example ...................................... 21 Modulus ....................................................................................... 21 Reference Doubler and Reference Divider ............................. 21 12-Bit Programmable Modulus ................................................ 21 Cycle Slip Reduction for Faster Lock Times ........................... 22 Spurious Optimization and Fast lock ...................................... 22 Fast Lock Timer and Register Sequences ................................ 22 Fast Lock—An Example ............................................................ 23 Fast Lock—Loop Filter Topology............................................. 23 Spur Mechanisms ....................................................................... 23 Spur Consistency and Fractional Spur Optimization ........... 24 Phase Resync ............................................................................... 24 Applications Information .............................................................. 25 Direct Conversion Modulator .................................................. 25 Interfacing ................................................................................... 26 PCB Design Guidelines for Chip Scale Package .................... 26 Output Matching ........................................................................ 27 Outline Dimensions ....................................................................... 28 Ordering Guide .. (28)REVISION HISTORY11/13—Rev. 0 to Rev. AChanges to Pin 24, Table 4................................................................ 8 7/11—Revision 0: Initial VersionData SheetADF4150Rev. A | Page 3 of 28SPECIFICATIONSAV DD = DV DD = SD VDD = 3.3 V ± 10%; V P = AV DD to 5.5 V; AGND = DGND = 0 V; T A = T MIN to T MAX , unless otherwise noted. The operating temperature range is −40°C to +85°C. Table 1.ParameterB VersionUnit Conditions/Comments Min Typ Max REF IN CHARACTERISTICSInput Frequency 10 250 MHz For f < 10 MHz ensure slew rate > 21 V/µs Input Sensitivity 0.7 AV DD V p-p Biased at AV DD /21 Input Capacitance 5.0 pF Input Current±60 µA RF INPUT CHARACTERISTICSRF Input Frequency (RF IN ), RF Output Buffer Disabled0.54.0 GHz −10 dBm ≤ RF input power ≤ +5 dBm RF Input Frequency (RF IN ), RF Output Buffer Disabled0.5 5.0 GHz −5 dBm ≤ RF input power ≤ +5 dBm RF Input Frequency (RF IN ) RF Output Buffer Enabled0.5 3.5 GHz −10 dBm ≤ RF input power ≤ +5 dBm RF Input Frequency (RF IN ) RF Output Buffer and Dividers Enabled 0.5 3.0 GHz −10 dBm ≤ RF input power ≤ +5 dBm Prescaler Output Frequency 750 MHz MAXIMUM PFD FREQUENCY Fractional-N (Low Spur Mode)26 MHz Fractional-N Mode (Low Noise Mode) 32 MHz Integer-N Mode 32 MHz CHARGE PUMPI CP Sink/Source R SET = 5.1 kΩ High Value 4.65 mA Low Value 0.29 mA R SET Range 2.7 10 kΩI CP Leakage1 nA V CP = V P /2Sink and Source Current Matching 2 % 0.5 V ≤ V CP ≤ V P − 0.5 V I CP vs. V CP1 % 0.5 V ≤ V CP ≤ V P − 0.5 V I CP vs. Temperature2 % V CP = V P /2 LOGIC INPUTSInput High Voltage, V INH 1.5 V Input Low Voltage, V INL 0.6 V Input Current, I INH /I INL ±1 µA Input Capacitance, C IN 3.0 pF LOGIC OUTPUTSOutput High Voltage, V OH DV DD − 0.4 V CMOS output chosen Output High Current, I OH 500 µAOutput Low Voltage, V O 0.4 V I OL = 500 µA POWER SUPPLIES AV DD3.0 3.6 V DV DD , SD VDD AV DD V PAV DD 5.5 V DI DD + AI DD 2 5060 mAOutput Dividers 6 to 24 mA Each output divide by two consumes 6 mA I RFOUT 224 32 mA RF output stage is programmable Low Power Sleep Mode1µAADF4150Data SheetRev. A | Page 4 of 28ParameterB VersionUnit Conditions/Comments Min Typ Max RF OUTPUT CHARACTERISTICSMinimum Output Frequency Using RF Output Dividers31.25MHz 500 MHz VCO input and divide-by-16 selected Maximum RF IN Frequency Using RF Output Dividers4400 MHzHarmonic Content (Second) −19 dBc Fundamental VCO output Harmonic Content (Third) −13 dBc Fundamental VCO output Harmonic Content (Second) −20 dBc Divided VCO output Harmonic Content (Third) −10 dBc Divided VCO output Output Power 3 −4 dBm Maximum setting+5 dBm Minimum setting Output Power Variation±1 dB Level of Signal With RF Mute Enabled −40 dBm NOISE CHARACTERISTICSNormalized Phase Noise Floor (PN SYNTH )4−223dBc/Hz PLL loop BW = 500 kHz (ABP = 3 ns)Normalized 1/f Noise (PN 1_f )5 −123dBc/Hz 10 kHz offset. Normalized to 1 GHz. (ABP = 3 ns) Normalized Phase Noise Floor (PN SYNTH )4−222dBc/Hz PLL loop BW = 500 kHz (ABP = 6 ns); low noise mode selectedNormalized 1/f Noise (PN 1_f )5 −119dBc/Hz 10 kHz offset; normalized to 1 GHz; (ABP = 6 ns); low noise mode selectedSpurious Signals Due to PFD Frequency 6 −90 dBc VCO output−75dBcRF output buffers1 AC coupling ensures AV DD /2 bias.2T A = 25°C; AV DD = DV DD = 3.3 V; prescaler = 8/9; f REFIN = 100 MHz; f PFD = 26 MHz; f RF = 1.7422 GHz. 3Using a tuned load. 4The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value) and 10 log F PFD . PN SYNTH = PN TOT − 10logF PFD − 20logN. 5The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (F RF ) and at a frequency offset (f) is given by PN = P 1_f + 10log(10 kHz/f) + 20log(F RF /1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL. 6Spurious measured on EVAL-ADF4150EB1Z, using a Rohde & Schwarz FSUP signal source analyzer.Data SheetADF4150Rev. A | Page 5 of 28TIMING CHARACTERISTICSAV DD = DV DD = SD VDD = 3.3 V ± 10%; V P = AV DD to 5.5 V; AGND = DGND = 0 V; T A = T MIN to T MAX , unless otherwise noted. Operating temperature range is −40°C to +85°C. Table 2.Parameter Limit (B Version) Unit Test Conditions/Comments t 1 20 ns min LE setup timet 2 10 ns min DATA to CLK setup time t 3 10 ns min DATA to CLK hold time t 4 25 ns min CLK high duration t 5 25 ns min CLK low duration t 6 10 ns min CLK to LE setup time t 720ns minLE pulse widthFigure 2. Timing DiagramCLKDATALELE08226-002ADF4150Data SheetRev. A | Page 6 of 28ABSOLUTE MAXIMUM RATINGST A = 25°C, unless otherwise noted. Table 3.Parameter RatingAV DD to GND 1 −0.3 V to +3.9 V AV DD to DV DD −0.3 V to +0.3 V V P to AV DD−0.3 V to +5.8 V Digital I/O Voltage to GND 1 −0.3 V to V DD + 0.3 V Analog I/O Voltage to GND 1 −0.3 V to V DD + 0.3 V REF IN to GND 1−0.3 V to V DD + 0.3 V Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +125°C Maximum Junction Temperature 150°C LFCSP θJA Thermal Impedance(Paddle-Soldered) 27.3°C/W Reflow SolderingPeak Temperature260°C Time at Peak Temperature40 sec1GND = AGND = DGND = 0 V.Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.TRANSISTOR COUNT23380 (CMOS) and 809 (bipolar)Data SheetADF4150Rev. A | Page 7 of 28PIN CONFIGURATION AND FUNCTION DESCRIPTIONSFigure 3. Pin ConfigurationTable 4. Pin Function DescriptionsPin No. Mnemonic Description1 CLK Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.2 DATA Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high impedance CMOS input.3 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register that is selected by the three LSBs.4 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode. Taking the pin high powers up the device depending on the status of the power-down bits.5 SW Fastlock Switch. Make a connection to this pin from the loop filter when using the fastlock mode.6 V P Charge Pump Power Supply. This pin should be greater than or equal to AV DD . In systems where AV DD is 3 V, it can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.7 CP OUT Charge Pump Output. When enabled, this provides ±I CP to the external loop filter. The output of the loop filter is connected to V TUNE to drive the external VCO.8 CP GND Charge Pump Ground. This is the ground return pin for CP OUT .9 AV DD 1 Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane are to be placed as close as possible to this pin. AV DD must have the same value as DV DD . 10 RF IN + Input to the RF Input. This small signal input is ac-coupled to the external VCO.11 RF IN − Complementary Input to the RF Input. This point must be decoupled to the ground plane with a small bypass capacitor, typically 100 pF.12, 13 A GND Analog Ground. This is a ground return pin for AV DD 1 and AV DD 2.14 RF OUT − Complementary RF Output. The output level is programmable. The VCO fundamental output or a divided down version is available.15 RF OUT + RF Output. The output level is programmable. The VCO fundamental output or a divided down version is available.16 AV DD 2 Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane are to be placed as close as possible to this pin. AV DD 2 must have the same value as DV DD .17 PDBRF RF Power-Down. A logic low on this pin mutes the RF outputs. This function is also software controllable.18 DV DD Digital Power Supply. This pin should be the same voltage as AV DD . Place decoupling capacitors to the ground plane as close as possible to this pin.19 REF IN Reference Input. This is a CMOS input with a nominal threshold of V DD /2 and a dc equivalent input resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.20 LD Lock Detect Output Pin. This pin outputs a logic high to indicate PLL lock; a logic low output indicates loss of PLL lock.21MUXOUTMultiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be accessed externally.A GNDAV DD 2DV DD R E F I NS D V D DS D G N D M U X O U T R S E T RF OUT +RF OUT −PDB RF L D NOTES1. THE LFCSP HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED TO GND.1CLK 2DATA 3LE 4CE 5SW 6V P1516171814137C P O U T 8C P G N D 9A V D D 111R F I N –12A G N D10R F I N +12340908226-003ADF4150 Data SheetRev. A | Page 8 of 28Data SheetADF4150Rev. A | Page 9 of 28TYPICAL PERFORMANCE CHARACTERISTICSFigure 4. RF Input Sensitivity; RF Output Enabled; Output Divide-by-1SelectedFigure 5. RF Input Sensitivity; RF Output DisabledFigure 6. RF Sensitivity; RF Output Enabled (RF Dividers-by-2/-4/-8/-16Enabled)Figure 7. Integer-N Phase Noise and Spur Performance; Low Noise Mode; VCOOUT = 1750 MHz, REF IN = 100 MHz, PFD = 25 MHz, Loop FilterBandwidth= 50 kHzFigure 8. Fractional-N Phase Noise and Spur Performance; Low Noise Mode;VCOOUT = 1750 MHz, REF IN = 100 MHz, PFD = 25 MHz, Loop Filter Bandwidth= 15 kHz, Channel Spacing = 200 kHz. FRAC = 26, MOD = 125Figure 9. Fractional-N Phase Noise and Spur Performance; Low Spur Mode;VCOOUT = 1750 MHz, REF IN = 100 MHz, PFD = 25 MHz, Loop Filter Bandwidth= 50 kHz, Channel Spacing = 200 kHz. FRAC = 26, MOD = 1250–505.0P O W E R (d B m )FREQUENCY (GHz)08226-042–45–40–35–30–25–20–15–10–50.51.01.52.02.53.03.54.04.510–5006P O W E R (d B m )FREQUENCY (MHz)08226-043–40–30–20–10123450–404.0P O W E R (d B m )FREQUENCY (GHz)08226-044–35–30–25–20–15–10–50.51.01.52.03.02.53.5–180–160–140–120–100–80–60P O WE R (d B c )08226-0451k 10k 100k1M 10MFREQUENCY (Hz)1M10M 100M1G 10GFREQUENCY (Hz)–180–160–140–120–100–80–60P O W ER (d B c )08226-0461k10k 100k1M 10MFREQUENCY (Hz)–180–160–140–120–100–80–60P O WE R (d B c )08226-047ADF4150Data SheetRev. A | Page 10 of 28Figure 10. RF Output Phase Noise RF Dividers Used; Integer-N; Low Noise Mode; VCOOUT = 1750 MHz, REF IN = 100 MHz, PFD = 25 MHz, Loop FilterBandwidth = 50 kHzFigure 11. RF Buffer Output Fractional-N Phase Noise and Spur Performance; Low Noise Mode; VCOOUT = 1750 MHz, REF IN = 100 MHz, PFD = 25 MHz, Loop Filter Bandwidth = 15 kHz, Channel Spacing = 200 kHz; FRAC = 1,MOD = 5; Output Divider = 1Figure 12. RF Buffer Output Fractional-N Phase Noise and Spur Performance; Low Noise Mode; VCOOUT = 1750 MHz, REF IN = 100 MHz, PFD = 25 MHz, Loop Filter Bandwidth = 15 kHz, Channel Spacing = 200 kHz; FRAC = 1,MOD = 5; Output Divider = 2Figure 13. RF Buffer Output Fractional-N Phase Noise and Spur Performance; Low Noise Mode; VCOOUT = 1750 MHz, REF IN = 100 MHz, PFD = 25 MHz, Loop Filter Bandwidth = 15 kHz, Channel Spacing = 200 kHz. FRAC = 1,MOD = 5. Output divider = 4–180–160–140–120–100–80–601k 10k 100k1M 10MP O W E R (d B c )FREQUENCY (Hz)08226-0381k 10k 100k1M 10M FREQUENCY (Hz)–180–160–140–120–100–80–60P O W E R (d B c )08226-0391k10k 100k1M 10MFREQUENCY (Hz)–180–160–140–120–100–80–60P O W E R (d B c )08226-041k10k 100k1M 10MFREQUENCY (Hz)–180–160–140–120–100–80–60P O W E R (d B c )08226-041CIRCUIT DESCRIPTIONREFERENCE INPUT SECTIONThe reference input stage is shown in Figure 14. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REF IN pin on power-down.Figure 14. Reference Input StageRF N DIVIDERThe RF N divider allows a division ratio in the PLL feedback path. Division ratio is determined by INT, FRAC, and MOD values, which build up this divider.INT, FRAC, MOD, AND R COUNTER RELATIONSHIPThe INT, FRAC, and MOD values, in conjunction with the R counter, make it possible to generate output frequencies that are spaced by fractions of the PFD frequency. See the RF Synthesizer—A Worked Example section for more informa- tion. The RF VCO frequency (RF OUT ) equation isRF OUT = f PFD × (INT + (FRAC /MOD ))(1)where:RF OUT is the output frequency of external voltage controlled oscillator (VCO).INT is the preset divide ratio of the binary 16–bit counter (23 to 65535 for 4/5 prescaler, 75 to 65535 for 8/9 prescaler). MOD is the preset fractional modulus (2 to 4095).FRAC is the numerator of the fractional division (0 to MOD − 1).f PFD = REF IN × [(1 + D )/(R × (1 + T ))](2)where:REF IN is the reference input frequency. D is the REF IN doubler bit.T is the REF IN divide-by-2 bit (0 or 1).R is the preset divide ratio of the binary 10-bit programmable reference counter (1 to 1023).Figure 15. RF INT DividerINT N MODEIf the FRAC = 0 and DB8 in Register 2 (LDF) is set to 1, the synthesizer operates in integer-N mode. The DB8 in Register 2 (LDF) should be set to 1 to get integer-N digital lock detect. Additionally, lower phase noise is possible if the anti-backlash pulse width is reduced to 3 ns. This mode is not valid for fractional-N applications.R COUNTERThe 10–bit R counter allows the input reference frequency (REF IN ) to be divided down to produce the reference clock to the PFD. Division ratios from 1 to 1023 are allowed.PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMPThe phase frequency detector (PFD) takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure 16 is a simplified schematic of the phase frequency detector. The PFD includes a programmable delay element that sets the width of the antibacklash pulse, which can be either 6 ns (default, for fractional-N applications) or 3 ns (for integer-N mode). This pulse ensures there is no dead zone in the PFD transfer function, and gives a consistent reference spur level.Figure 16. PFD Simplified SchematicPOWER-DOWN 08226-0108226-011CP–IN+IN08226-012MUXOUT AND LOCK DETECTThe output multiplexer on the ADF4150 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 (for details, see Figure 22). Figure 17 shows the MUXOUT section in block diagram form.Figure 17. MUXOUT SchematicINPUT SHIFT REGISTERSThe ADF4150 digital section includes a 10-bit RF R counter, a 16-bit RF N counter, a 12-bit FRAC counter, and a 12-bit modulus counter. Data is clocked into the 32-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of six latches on the rising edge of LE. The destination latch is determined by the state of the three control bits (C3, C2, and C1) in the shift register. These are the 3 LSBs, DB2, DB1, and DB0, as shown in Figure 2. The truth table for these bits is shown in Table 5. Figure 19 shows a summary of how the latches are programmed.Table 5. C3, C2, and C1 Truth TableControl BitsC3 C2 C1 Register0 0 0 Register 0 (R0) 0 0 1 Register 1 (R1) 0 1 0 Register 2 (R2) 0 1 1 Register 3 (R3) 1 0 0 Register 4 (R4) 11Register 5 (R5)PROGRAM MODESFigure 20 through Figure 25 show how the program modes are to be set up in the ADF4150.A number of settings in the ADF4150 are double buffered. These include the modulus value, phase value, R counter value, reference doubler, reference divide-by-2, and current setting. This means that two events have to occur before the part uses a new value of any of the double-buffered settings. First, the new value is latched into the device by writing to the appropriate register. Second, a new write must be performed on Register R0. For example, any time the modulus value is updated, Register R0 must be written to, thus ensuring the modulus value is loaded correctly. Divider select in Register 4 (R4) is also double buffered, but only if DB13 of Register 2 (R2) is high.OUTPUT STAGEThe RF OUT + and RF OUT − pins of the ADF4150 are connected to the collectors of an NPN differential pair driven by bufferedoutputs of the VCO, as shown in Figure 18. To allow the user to optimize the power dissipation vs. the output power require-ments, the tail current of the differential pair is programmable by Bit D2 and Bit D1 in Register 4 (R4). Four current levels may be set. These levels give output power levels of −4 dBm, −1 dBm, +2 dBm, and +5 dBm, respectively, using a 50 Ω resistor to AV DD and ac coupling into a 50 Ω load. Alternatively, both outputs can be combined in a 1 + 1:1 transformer or a 180° microstrip coupler (see the Output Matching section). If the outputs are used individually, the optimum output stage consists of a shunt inductor to AV DD .Another feature of the ADF4150 is that the supply current to the RF output stage can be shut down until the partachieves lock as measured by the digital lock detect circuitry. This is enabled by the mute-till-lock detect (MTLD) bit in Register 4 (R4).Figure 18. Output StageGNDDVANALOG LOCK DETECT DIGITAL LOCK DETECTR COUNTER OUTPUT N COUNTER OUTPUT DGNDRESERVEDTHREE-STATE-OUTPUTDV DD R COUNTER INPUT08226-013RF OUT +RF OUT –08226-014REGISTER MAPSFigure 19. Register Summary1DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.2DBB = DOUBLE BUFFERED BITS—BUFFERED BY THE WRITE TO REGISTER 0, IF AND ONLY IF DB13 OF REGISTER 2 IS HIGH.REGISTER 4REGISTER 0REGISTER 1REGISTER 2REGISTER 3REGISTER 508226-015Figure 20. Register 0 (R0)Figure 21. Register 1 (R1)INTmin = 75 with prescaler = 8/908226-01608226-017Figure 22. Register 2 (R2)08226-018Figure 23. Register 3 (R3)Figure 24. Register 4 (R4)08226-019Figure 25. Register 5 (R5)08226-021REGISTER 0Control BitsWith Bits[C3:C1] set to 0, 0, 0, Register 0 is programmed. Figure 20 shows the input data format for programming this register.16-Bit Integer Value (INT)These 16 bits set the INT value, which determines the integer part of the feedback division factor. They are used in Equation 1 (see the INT, FRAC, MOD, and R Counter Relationship section). All integer values from 23 to 65,535 are allowed for 4/5 prescaler. For 8/9 prescaler, the minimum integer value is 75.12-Bit Fractional Value(FRAC)The 12 FRAC bits set the numerator of the fraction that is input to the Σ-Δ modulator. This, along with INT, specifies the new frequency channel that the synthesizer locks to, as shown in the RF Synthesizer—A Worked Example section. FRAC values from 0 to MOD − 1 cover channels over a frequency range equal to the PFD reference frequency.REGISTER 1Control BitsWith Bits[C3:C1] set to 0, 0, 1, Register 1 is programmed. Figure 21 shows the input data format for programmingthis register.Prescaler ValueThe dual modulus prescaler (P/P + 1), along with the INT, FRAC, and MOD counters, determines the overall division ratio from the VCO output to the PFD input.Operating at CML levels, it takes the clock from the VCO output and divides it down for the counters. It is based on a synchronous 4/5 core. When set to 4/5, the maximum RF frequency allowed is 3 GHz. Therefore, when operating the ADF4150 above 3 GHz, this must be set to 8/9. The prescaler limits the INT value, where:P = 4/5, N MIN = 23P = 8/9, N MIN = 75In the ADF4150, P1 in Register 1 sets the prescaler values. 12-Bit Phase Value (Phase)These bits control what is loaded as the phase word. The word must be less than the MOD value programmed in Register 1. The word is used to program the RF output phase from 0° to 360° with a resolution of 360°/MOD. See the Phase Resync section for more information. In most applications, the phase relationship between the RF signal and the reference is not important. In such applications, the PHASE value can be used to optimize the fractional and subfractional spur levels. See the Spur Consistency and Fractional Spur Optimization section for more information.If neither the PHASE resync nor the spurious optimization functions are being used, it is recommended that the PHASE word be set to 1.12-Bit Modulus Value (MOD)This programmable register sets the fractional modulus. This is the ratio of the PFD frequency to the channel step resolution on the RF output. See the RF Synthesizer—A Worked Example section for more information.REGISTER 2Control BitsWith Bits[C3:C1] set to 0, 1, 0, Register 2 is programmed. Figure 22 shows the input data format for programmingthis register.Low Noise and Spur ModesThe noise modes on the ADF4150 are controlled by DB30 and DB29 in Register 2 (see Figure 22). The noise modes allow the user to optimize a design either for improved spurious perfor-mance or for improved phase noise performance.When the lowest spur setting is chosen, dither is enabled. This randomizes the fractional quantization noise so it resembles white noise rather than spurious noise. As a result, the part is optimized for improved spurious performance. This operation would normally be used when the PLL closed-loop bandwidth is wide, for fast-locking applications. (Wide loop bandwidth is seen as a loop bandwidth greater than 1/10 of the RF OUT channel step resolution (f RES)). A wide loop filter does not attenuate the spurs to the same level as a narrow loop bandwidth.For best noise performance, use the lowest noise setting option. As well as disabling the dither, it also ensures that the charge pump is operating in an optimum region for noise performance. This setting is extremely useful where a narrow loop filter band-width is available. The synthesizer ensures extremely low noise and the filter attenuates the spurs. The typical performance characteristics give the user an idea of the trade-off in a typical W-CDMA setup for the different noise and spur settings.。

ADF4158_cn

直接调制/波形产生 6.1 GHz小数N分频频率合成器
ADF4158
特性
RF带宽达6.1 GHz 25位固定模数可提供次赫兹频率分辨率频率与相位调制能力频域中的锯齿波和三角波抛物线斜坡斜坡与FSK叠加具有2种不同扫描速率的斜坡斜坡延迟斜坡频率回读斜坡中断 2.7 V至3.3 V电源供电独立的电荷泵电源VP可提供扩展的调谐电压可编程电荷泵电流三线式串行接口数字锁定检测关断模式减少周跳以缩短锁定时间在宽带宽内快速锁定模式通过汽车应用认证
概述
ADF4158是一款具有调制和波形产生能力的6.1 GHz小数N分频频率合成器，包含25位固定模数，可在6.1 GHz下提供次赫兹频率分辨率。它由低噪声数字鉴频鉴相器 (PFD)、精密电荷泵和可编程参考分频器组成。该器件内置一个 Σ-Δ 型小数插值器，能够实现可编程模数小数 N分频。 INT和 FRAC寄存器可构成一个总N分频器(N = INT + (FRAC/225))。 ADF4158 可用于实现频移键控 (FSK) 和相移键控 (PSK) 调制。可用的频率扫描模式也有很多，可在频域内产生各种波形，例如锯齿波和三角波。 ADF4158 具有周跳减少电路，可进一步缩短锁定时间，而无需修改环路滤波器。所有片内寄存器均通过简单的三线式接口进行控制。该器件采用2.7 V至3.3 V电源供电，不用时可以关断。
ADI中文版数据手册是英文版数据手册的译文，敬请谅解翻译中可能存在的语言组织或翻译错误，ADI不对翻译中存在的差异或由此产生的错误负责。如需确认任何词语的准确性，请参考ADI提供的最新英文版数据手册。
08728-001
ADF4158 目录
特性 ...............................................

湖南艾华集团股份有限公司产品说明书：金属电容器

PREPARED BY CHECKED BY APPROVED BYCustomer: TRANSFER MUL TISORT ELEKTRONIK SP .Z 0.0 Date: August 26, 2015SPECIFICATIONDescription: Aluminum Electrolytic Capacitors AISHI P/N: EPF2QM101W35OC SERIES: PFITEM: 330V100uF (Φ12.5X35) Customer P/N:No.: CRS-J-1508175APPROVED BYPlease Return One Copy with Your Approval承认后请寄回一份湖南艾华集团股份有限公司HUNAN AIHUA GROUP CO., L TDTel: (0737)6184466 Fax : (0737)6180493版本更改原因更改内容生效日期CRS-J-1508175新建新建2015-8-26CustomerTRANSFER MUL TISORT ELEKTRONIK SP .Z 0.0SERIESPF DATE 2015-8-26FIG-1TABLE-1No.Customer Part No.Aishi Part No.Capacitance(uF)Tolerance on Rated Capacitance(%)Rated V oltage (Vdc)Operating Temp. Range(℃)tan δ (120Hz)(Max)Leakage Current (uA) (5min.)Endurance at 55℃(Hours)Dimensions (mm)Appearance Drawing No. D ΦL αd F F11 EPF2QM101W35OC 100 ±20 330 -25~+55 0.06 100 5000 12.53520.6 5.0/FIG-1F ±0.5PVCL+ α MAX 15 MIN4MIN￠d±0.05D+0.5 MAX1．概述SCOPE本承认书规定了PF 系列径向引线引出铝电解电容器的技术规范，本技术规范条文解释权归本公司所有。

Z87L00中文资料(zilog)中文数据手册「EasyDatasheet - 矽搜」

Z87C33®CMOS MCU消费者Z8控制器处理器产品规格PS015601-1003©2003 ZiLOG公司防护留所有权利.本出版物中关于设备信息,应用程序,或者有技术描述意在暗示可能用途,并且可以被替代. Zilog公司,INC.不承担责任或提供精度表示资料,设备或技术描述这份文件. ZiLOG公司也没有承担起知识产权侵权责任相关以任何方式使用信息,设备或技术此处或本.除非ZiLOG公司,利用信息,设备或技术作为生命支持系统中关键部件明确书面许可,没有被授权.转让任何许可证,暗示或以其他方式,通过在本文档中任何知识产权.PS015601-1003iii 目录结构概述. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1特征 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2功能框图. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3引脚说明. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4引脚功能. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .五控制寄存器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32扩展寄存器文件,单元0H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32定时器模式寄存器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32扩展寄存器文件,单元Fh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42电气特性 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47绝对最大额定值 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47直流电气特性. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49AC电气特性. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56标准测试条件. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61电容 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61包装. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61订购信息 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63型号说明. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64文档信息. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65文件编号描述. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65顾客意见调查表. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65Z87C33产品规格. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65产品信息 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66返回信息. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66PS015601-1003目录iv 图一览图1.图2.图3.图4.图5.图6.图7.图8.图9.图10.图11.图12.图13.图14.图15.图16.图17.图18.图19.功能框图. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328引脚DIP / SOIC引脚配置. . . . . . . . . . . . . . . . . . . . . . . . . 4P0口配置. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6端口2配置. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7端口3配置. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9端口3配置,电源控制寄存器详细信息. . . . . . . . . . . . . . . . . 10程序存储器映射. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12寄存器指针细节. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14扩展寄存器文件架构. . . . . . . . . . . . . . . . . . . . . . . . 16计数器/定时器框图. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17中断框图. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18振荡器配置. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20停止模式恢复源. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25复位和看门狗定时器为例. . . . . . . . . . . . . . . . . . . . . .三十典型低电压防护护与温度关系. . . . . . . . . . . . . . 31额外时序. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56测试负载图. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 28引脚DIP封装图. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6228引脚SOIC封装图. . . . . . . . . . . . . . . . . . . . . . . . . . . . 63PS015601-1003图一览v 表一览表1.家族特征. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2表2. 28引脚DIP / SOIC引脚配置. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4表3.端口3引脚分配. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8表4.寄存器指针寄存器-RP FDH / R253单元0H：读/写. . 13表5.中断类型,来源,和载体. . . . . . . . . . . . . . . . . . . . . . . . . 18表6. IRQ寄存器*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19表7.端口配置寄存器,PCON 00H / R0单元Fh：只写. 22表8.停止模式恢复寄存器1 SMR1值0Bh / R11单元FH：有关WRITEONLY,除D7位,这是只读. . . . . . . . . . . . . . . . . . 23表9.停止模式恢复源. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26表10.停止模式恢复寄存器2. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26表11.停止模式恢复寄存器2 SMR20DH / R13单元FH：有关WRITE只要 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27表12.看门狗定时器模式寄存器-WDTMR0Fh / R15：写只要 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28表13. WDT时间选择. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28表14.最大（V LV）条件： . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31表15.扩展寄存器文件寄存器,复位状态. . . . . . . . . . . . . . . 32表16.定时器模式寄存器,TMR为Fih / R241单元0H：读/写. . . . 33表17.计数器/定时器1寄存器-T1 F2H / R242单元0H：读/写. . 33表18.预分频器1注册-PRE1 F3H / R243单元0H：只写. . . 34表19.计数器/定时器0寄存器-T0 F4H / R244单元0H：读/写. . 35表20.预分频器0注册-PRE0 F5H / R245单元0H：只写. . . 35表21.端口2模式寄存器,P2M F6H / R246单元0H：只写. . . . 36表22.端口3模式寄存器-P3M F7H / R247单元0H：只写. . . . 36表23.端口0和1模式寄存器-P01M F8H / R248单元0H：写只要 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37表24.中断优先级寄存器,IPR F9H / R249单元0H：只写. 37表25.中断请求寄存器,IRQ FAH / R250单元0H：读/写38表26.中断屏蔽寄存器,IMR FBH / R251单元0H：读/写. . 39表27.标志寄存器,标志位FCH / R252单元0H：读/写. . . . . . . 40表28.寄存器指针-RP FDH / R253单元0H：读/写. . . . . . . . . 41表29.通用-GPR FEH / R254单元0H：读/写. . . . . . . 41表30.堆栈指针低SPL FFH / R255单元0H：读/写. . . . . . 42表31.扩展寄存器文件寄存器,复位状态. . . . . . . . . . . . . . . 42PS015601-1003表一览。

超高效液相色谱串联四极杆质谱联用仪质谱部分技术参数

超高效液相色谱串联四极杆质谱联用仪(质谱部分)技术参数1应用范围：系统主要用于食品中农药残留、兽药残留、非法添加物等有机化合物的定量/定性分析和鉴定。

2.工作环境条件：2.1电源：220Vac,±10%,50∕60Hz,30A o2.2环境温度：15~30℃o2.3相对湿度：20~80%o3.总体要求：3.2仪器主体部分包括串联四极杆复合型质谱仪主机，仪器由计算机控制、配有独立的ESI和APCI离子源。

软件包括仪器调节、数据采集、数据处理、定量分析和报告。

*3.2仪器灵敏度高，性能稳定，重复性好；同一台仪器要同时满足串联四极杆质谱仪的定量功能和超高分辨质谱仪的高分辨功能；4.质谱性能指标：4.2离子源：配有电喷雾离子源(ESI)、大气压化学电离源(APCI),离子源切换方便、快速，清洗、维护方便。

*4.11离子源加热温度：≥650o C,雾化气流速可调。

4.1.1插拔式可互换ES1及APCI喷针，可实现ESI源及APCI源的快速更换。

1.1.1气压离子源采用锥孔结构，以同时保持高灵敏度和优异的抗污染能力，（提供结构示意图）而非毛细管或离子传输管结构设计。

4.1.3电喷雾离子源流速范围：在确保灵敏度不损失的前提下，实现高流速，无需分流，即可达到3m1∕min;加快样品的分析速度同时，还可避免分流对样品造成损失。

4.1.4大气压化学电离源流速范围：在确保灵敏度不损失的前提下，实现高流速，无需分流，即可达到3m1∕min;加快样品的分析速度同时，还可避免分流对样品造成损失。

4.1.5离子源内废气排放：有废气排放装置，防止气体在密闭的离子源腔体中的回流，降低离子源的记忆效应和污染，降低机械泵的负荷延长机械泵泵油使用时间，维护试验环境,保障工作人员健康。

4.1.6QO聚焦技术：离子引入部分拥有高压离子聚焦技术，压力至少达7.5mtorr,以确保最佳的离子聚焦效果和离子传输效率，有效消除“记忆效应”和“交叉污染”。

LTC4150中文资料

12344150faPI FU CTIO SU U USENSE + (Pin 1): Positive Sense Input. This is the noninverting current sense input. Connect SENSE + to the load and charger side of the sense resistor. Full-scale current sense input is 50mV. SE NSE + must be within 60mV of V DD for proper operation.SENSE – (Pin 2): Negative Sense Input. This is the inverting current sense input. Connect SE NSE – to the positive battery terminal side of the sense resistor. Full-scale current sense input is 50mV. SE NSE – must be within 60mV of V DD for proper operation.C F + (Pin 3): Filter Capacitor Positive Input. A capacitor connected between C F + and C F – filters and averages noise and fast battery current variations. A 4.7µF value is recom-mended. If filtering is not desired, leave C F + and C F –unconnected.C F – (Pin 4): Filter Capacitor Negative Input. A capacitor connected between C F + and C F – filters and averages noise and fast battery current variations. A 4.7µF value is recom-mended. If filtering is not desired, leave C F + and C F –unconnected.SHDN (Pin 5): Shutdown Digital Input. When asserted low, SHDN forces the LTC4150 into its low current con-sumption power-down mode and resets the part. In appli-cations with logic supply V CC > V DD , a resistive divider must be used between SHDN and the logic which drives it.See the Applications Information section.POL (Pin 6): Battery Current Polarity Open-Drain Output.POL indicates the most recent battery current polarity when INT is high. A low state indicates the current is flowing out of the battery while high impedance means the current is going into the battery. POL latches its state when INT is asserted low. POL is an open-drain output and can be pulled up to any logic supply up to 9V. In shutdown,POL is high impedance.GND (Pin 7): Ground. Connect directly to the negative battery terminal.V DD (Pin 8): Positive Power Supply. Connect to the load and charger side of the sense resistor. SE NSE + also connects to V DD . V DD operating range is 2.7V to 8.5V.Bypass V DD with 4.7µF capacitor.CLR (Pin 9): Clear Interrupt Digital Input. When asserted low for more than 20µs, CLR resets INT high. Charge counting is unaffected . INT may be directly connected to CLR. In this case the LTC4150 will capture each assertion of INT and wait at least 1µs before resetting it. This ensures that INT pulses low for at least 1µs but gives automatic INT reset. In applications with a logic supply V CC > V DD , a resistive divider must be used between INT and CLR. See the Applications Information section.INT (Pin 10): Charge Count Interrupt Open-Drain Output.INT latches low every 1/(V SENSE • G VF ) seconds and is reset by a low pulse at CLR. INT is an open-drain output and can be pulled up to any logic supply of up to 9V. In shutdown INT is high impedance.5OPERATIOUCharge is the time integral of current. The LTC4150 measures battery current by monitoring the voltage devel-oped across a sense resistor and then integrates this information in several stages to infer charge. The Block Diagram shows the stages described below. As each unit of charge passes into or out of the battery, the LTC4150 INT pin interrupts an external microcontroller and the POL pin reports the polarity of the charge unit. The external microcontroller then resets INT with the CLR input in preparation for the next interrupt issued by the LTC4150. The value of each charge unit is determined by the sense resistor value and the sense voltage to interupt frequency gain G VF of the LTC4150.Power-On and Start-Up InitializationWhen power is first applied to the LTC4150, all internal circuitry is reset. After an initialization interval, the LTC4150 begins counting charge. This interval depends on V DD and the voltage across the sense resistor but will be at least 5ms. It may take an additional 80ms for the LTC4150 to accurately track the sense voltage. An internal undervolt-age lockout circuit monitors V DD and resets all circuitry when V DD falls below 2.5V.Asserting SHDN low also resets the LTC4150’s internal circuitry and reduces the supply current to 1.5µA. In this condition, POL and INT outputs are high impedance. The LTC4150 resumes counting after another initialization interval. Shutdown minimizes battery drain when both the charger and load are off.CHARGE COUNTINGFirst, the current measurement is filtered by capacitor C F connected across pins C F+ and C F–. This averages fast changes in current arising from ripple, noise and spikes in the load or charging current.Second, the filter’s output is applied to an integrator with the amplifier and 100pF capacitor at its core. When the integrator output ramps to RE FHI or RE FLO levels, switches S1 and S2 reverse the ramp direction. By observing the condition of S1 and S2 and the ramp direction, polarity is determined. The integrating interval is trimmed to 600µs at 50mV full-scale sense voltage.Third, a counter is incremented or decremented every time the integrator changes ramp direction. The counter effec-tively increases integration time by a factor of 1024, greatly reducing microcontroller overhead required to service interrupts from the LTC4150.At each counter under or overflow, the INT output latches low, flagging a microcontroller. Simultaneously, the POL output is latched to indicate the polarity of the observed charge. With this information, the microcontroller can total the charge over long periods of time, developing an accurate estimate of the battery’s condition. Once the interrupt is recognized, the microcontroller resets INT with a low going pulse on CLR and awaits the next interrupt. Alternatively, INT can drive CLR.64150fa74150faSENSE VOLTAGE INPUT AND FILTERSSince the overall integration time is set by internally trimming the LTC4150, no external timing capacitor or trimming is necessary. The only external component that affects the transfer function of interrupts per coulomb of charge is the sense resistor, R SENSE . The common mode range for the SENSE + and SENSE – pins is V DD ±60mV, with a maximum differential voltage range of ±50mV. SENSE +is normally tied to V DD , so there is no common mode issue when SENSE – operates within the 50mV differential limit relative to SENSE +.Choose R SENSE to provide 50mV drop at maximum charge or discharge current, whichever is greater. Calculate R SENSE from:R mV I SENSE MAX=50(1)The sense input range is small (±50mV) to minimize the loss across R SENSE . To preserve accuracy, use Kelvin connections at R SENSE .The external filter capacitor C F operates against a total on-chip resistance of 4k to form a lowpass filter that averages battery current and improves accuracy in the presence of noise, spikes and ripple. 4.7µF is recommended for gen-eral applications but can be extended to higher values as long as the capacitor’s leakage is low. A 10nA leakage is roughly equivalent to the input offset error of the integra-tor. Ceramic capacitors are suitable for this use.Switching regulators are a particular concern because they generate high levels of current ripple which may flow through the battery. The V DD and SENSE + connection to the charger and load should be bypassed by at least 4.7µF at the LTC4150 if a switching regulator is present.The LTC4150 maintains high accuracy even when Burst Mode ® switching regulators are used. Burst pulse “on”levels must be within the specified differential input volt-age range of 50mV as measured at C F + and C F –. To retain accurate charge information, the LTC4150 must remain enabled during Burst Mode operation. If the LTC4150shuts down or V DD drops below 2.5V, the part resets and charge information is lost.APPLICATIO S I FOR ATIOW UUU Coulomb CountingThe LTC4150’s transfer function is quantified as a voltage to frequency gain G VF , where output frequency is the number of interrupts per second and input voltage is the differential drive V SENSE across SENSE + and SENSE –. The number of interrupts per second will be:f = G VF • ⏐V SENSE ⏐(2)whereV SENSE = I BATTERY • R SENSE (3)Therefore,f = G VF • ⏐I BATTERY • R SENSE ⏐(4)Since I • t = Q, coulombs of battery charge per INT pulse can be derived from Equation 4:One INT G R CoulombsVF SENSE=1•(5)Battery capacity is most often expressed in ampere-hours.1Ah = 3600 Coulombs (6)Combining Equations 5 and 6:One INT G R VF SENSE=13600•• [Ah](7)or1Ah = 3600 • G VF • R SENSE Interrupts(8)The charge measurement may be further scaled within the microcontroller. However, the number of interrupts, cou-lombs or Ah all represent battery charge.The LTC4150’s transfer function is set only by the value of the sense resistor and the gain G VF . Once R SENSE is selected using Equation 1, the charge per interrupt can be determined from Equation 5 or 7.Note that R SENSE is not chosen to set the relationship between ampere-hours of battery charge and number of interrupts issued by the LTC4150. Rather, R SENSE is chosen to keep the maximum sense voltage equal to or less than the LTC4150’s 50mV full-scale sense input.Burst Mode is registered trademark of Linear Technology Corporation.891011Information furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.121630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 ● FAX: (408) 434-0507 ● © LINEAR TECHNOLOGY CORPORA TION 2003LT/TP 1004 1K REV A • PRINTED IN USA。

广州爱普电子技术有限公司产品说明书

Typical Features◆Wide input voltage range:85-265VAC/120-380VDC◆No-load power consumption≤≤0.5W◆Transfer efficiency（typ.87%）◆Switching frequency:65KHz◆Protection:Short Circuit,Over Current◆Isolation voltage:2500Vac◆Plastic case,conform to UL94V-0Class◆PCB mountingApplication FieldFA24-220SXXG3N3Series-----a compact size,high efficient power converter offered by Aipu.It features universal input voltage,DC and AC dual-use,low ripple,low temperature rise,low power consumption, high efficiency,high reliability,safer isolation,with good EMC performance.EMC and Safety standard meet international EN55032,IEC/EN61000.It widely used in power,industrial,instrument,smart home applications.For harsh EMC environment,the application circuit in the datasheet is strongly recommended.Typical Product ListPart No.Output SpecificationMax.Capacitive LoadRipple&Noise20MHz（Max）Efficiency@Full Load220Vac(Typical) Power Voltage1Current1Voltage2Current2（W）Vo1（V）Io1（m A）Vo2（V）Io2（m A）u F mVp-p%FA24-220S12G3N32412.02000--200015085 FA24-220S15G3N32415.01600--20008086 FA24-220S24G3N324241000--80010087 Note1:Ripple&Noise of FA24-220S15G3N3,FA24-220S24G3N3should be tested with EMC solution recommended circuit,please see photo1at back.Note2:Due to space limitations,above is only a part of our product list,please contact our sales team for more items.Note3:.”*”is model under developing.Note4:The typical output efficiency is based on that product is full loaded and burned-in after half an hour.Note5:The fluctuation range of full load efficiency(%,TYP)is±2%,full load output efficiency=total output power/module’s input power.Input SpecificationItem Operating Condition Min.Typ.Max.UnitInput Voltage Range AC Input85220265VAC DC Input120310380VDCInput Frequency Range-475063HzInput Current 115VAC//250mA 220VAC//150Surge Current 115VAC//10 220VAC//20Leakage Current-0.5mA TYP/230VAC/50HzExternal fuserecommended value-2A-5A/250VAC slow-fusing Hot plug-UnavailableRemote control terminal-UnavailableOutput SpecificationItem Operating Condition Min.Typ.Max.UnitVoltage Accuracy Full input voltagerangeAny loadVo1--±2.0%Vo2---%Line Regulation Nominal Load Vo1--±2.0% Vo2---%Load RegulationNominal inputVoltage20%~100%loadVo1--±2.0%Vo2---%No load power consumption Input115VAC--0.5W Input220VAC--Minimum loadSingle Output0--% Positive Negative Dualoutput commongrounded---% Positive Negative Dualoutput isolated---Turn-on Delay Time Nominal input voltage,fullload-300-mSPower-off Holding Time Input115VAC(full load)-65-mS Input220VAC(full load)--Output Overshooting Full input voltage range(full load)--10%Dynamic Response 25%~50%~25%50%~75%~50%Overshoot range（%）：≤±5%%Recovery time（mS）：≤5.0mS mSShort Circuit Protection Input full voltage range Continuous,Self-recovery Hiccup Drift Coefficient--±0.03%-%/℃Over Current Protection Input220VAC≥120%Io,Self-recovery HiccupRipple&Noise Vo=12.0V≤150mV Vo=15.0V≤80mVVo=24.0V≤100Note:Ripple&Noise is tested by Twisted Pair Method,details please see Ripple&Noise Test at back. General SpecificationsItem Operating Condition Min.Typ.Max.Unit Switching Frequency-606570KHz Operating Temperature--40-+75℃Storage Temperature--40-+85Relative Humidity-10-90%RHIsolation Voltage Input-Output,Test1min,leakage current≤5mA2500--VACInsulation Resistance Input-Output@DC500V100--MΩMTBF-≥300,000H@25℃Vibration-10-55Hz,10G,30Min,alongX,Y,ZClass of Case Material-UL94V-0EMC CharacteristicsTotal Item Sub Item Test Standard ClassEMC EMICE CISPR22/EN55032CLASS B（see recommended circuit Photo2）RE CISPR22/EN55032CLASS B（see recommended circuit Photo2）EMSRS IEC/EN61000-4-310V/m Perf.Criteria BCS IEC/EN61000-4-63Vr.m.s Perf.Criteria BESD IEC/EN61000-4-2Contact±4KV/Air±8KV Perf.Criteria BSurge IEC/EN61000-4-5±1KV Perf.Criteria B（see recommendedcircuit Photo2）EFT IEC/EN61000-4-4±2KV Perf.Criteria BVoltage dips,shortinterruptions and voltagevariations immunityIEC/EN61000-4-110%~70%Perf.Criteria BPacking DimensionPacking Code L x W x HG339.0x25.0x22.0mmPin DefinitionPin-out12345Single（S）AC(N)AC(L)GND NP+VoNote:If the definition of pin is not in accordance with the model selection manual,please refer to the label on actual item. Ripple&Noise Test:(Twisted Pair Method20MHZ bandwidth)Test Method:(1)12#twisted pair to connect,Oscilloscope bandwidth set as20MHz,100M bandwidth probe,terminated with0.1uFpolypropylene capacitor and10uF high frequency lowresistance electrolytic capacitor in parallel,oscilloscope set asSample pattern.(2)Input terminal connect to power supply,output terminalconnect to electronic load through jig plate,Use30cm±2cmsampling line.Power line selected from correspondingdiameter wire with insulation according to the flow of outputcurrent.Product Characteristic CurveNote1:Input Voltage should be derated base on Input Voltage Derating Curve when it is85~100VAC/240~265VAC/120~140VDC/340~380VDC.2:Our product is suitable to use under natural air cooling environment,if use it under closed condition,please contact with us. Typical EMC Circuit and Recommended Spec1.Typical Application CircuitPart No.CE1L1CE2TVS1FA24-220S12G3N3NC2uH470uF/16V SMBJ14.0AFA24-220S15G3N3220uF/25V5uH220uF/25V SMBJ17.0A*FA24-220S24G3N3220uF/35V5uH220uF/35V SMBJ26.0ANote:Output filter capacitor C2is electrolytic capacitor,recommend high frequency low resistor electrolytic capacitor,for capacity and current low,please refer to the technical specifications provided by each manufacturer.C2capacitor withstand voltage should derate to80%,capacitor C1is ceramic capacitor,to filter high frequency noise,recommended0.1uF/50V/1206.TVS1tube is a recommend component to protect post-circuit if converter fails.Recommend to external FUSE,Model:3.15A/250V, slow fusing.2.EMC solution recommended circuitPhoto2,EMC for higher requirement circuitComponent Products Module ValueFUSE 3.15A/250Vac 3.15A/250Vac,slow-fusing,necessaryNTC5D-95D-9MOV10D561K10D561KCX10.47uF/275Vac0.47uF/275VacL1 6.8uH/3.0A 6.8uH/3.0A H inductorLF2UU9.830mH min30mH/3.0ANote:1.The product should be used under the specification range,otherwise it will cause permanent damage to it.2.Product’s input terminal should connect to fuse;3.If the product is not worked under the load range(below the minimum load or beyond the load range),we cannot ensure that the performance of product is in accordance with all the indexes in this manual;4.Unless otherwise specified,data in this datasheet are tested under conditions of Ta=25℃,humidity<75%when inputting nominal voltage and outputting rated load(pure resistance load);5.All index testing methods in this datasheet are based on our Company’s corporate standards6.The performance indexes of the product models listed in this manual are as above,but some indexes of non-standard model products will exceed the above-mentioned requirements,please directly contact our technician for specific information;7.We can provide customized product service;8.The product specification may be changed at any time without prior notice.。

常用三极管参数大全

玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理。

蓝色贴片式发光二极管 XL-1005UBC 商品说明书

产品承认书产品名称：0402-T0.4蓝色贴片式发光二极管产品型号：XL-1005UBC客户名称：客户料号：承认日期：深圳市成兴光电子科技有限公司制定审核核准客户承认栏确认审核核准一、产品描述：●外观尺寸(L/W/H): 1.0x0.5x0.4mm●颜色:高亮度蓝色●胶体:透明胶体●EIA规范标准包装●环保产品，符合ROHS要求●适用于自动贴片机●适用于红外线回流焊制程二、外形尺寸及建议焊盘尺寸：Cathode AnodeC athode m arkG reen m ark建议焊盘尺寸备注：1.单位:毫米（mm）2.公差：如无特别标注则为±0.10mm三、建议焊接温度曲线：有铅制程无铅制程四、最大绝对额定值（Ta=25℃）：参数符号最大额定值单位消耗功率Pd80mW最大脉冲电流(1/10占空比,0.1ms脉宽)I FP100mA正向直流工作电流I F25mA 反向电压V R5V 工作环境温度Topr-30°C~+85°C存储环境温度Tstg-40°C~+90°C焊接条件Tsol 回流焊:260°C,10s 手动焊:300°C,3s五、光电参数（Ta=25℃）：参数符号最小值代表值最大值单位测试条件光强IV 35---72mcd IF =5mA 半光强视角2θ1/2---120---deg IF =5mA 主波长λD 460---469nm IF =5mA 正向电压VF 2.7--- 3.1V IF=5mA 反向电流IR------1uAVR=5V亮度分档代码最小值最大值单位测试条件D03542mcdIF=5mAD14250D25060D36072电压分档代码最小值最大值单位测试条件W11 2.7 2.8VIF=5mAW12 2.8 2.9W13 2.9 3.0W143.03.1波长分档代码最小值最大值单位测试条件B1460463nmIF=5mAB2463466B3466469六、光电参数代表值特征曲线：φ60七、标签标识：CAT ：光强（mcd ）HUE ：波长（nm ）REF ：电压（V ）误差范围a.Luminous Intensity:±15%b.HUE:±1nmc.Forward Voltage:±0.1V八、包装载带与圆盘尺寸：φ13.0AAA-A剖面图U ser Feed D irection备注:1.尺寸单位为毫米(mm)；2.尺寸公差如无标注，为±0.15mm ；九、圆盘及载带卷出方向及空穴规格：尾端空壳载带的组合开始端空壳载带的组合盖带与空壳载带的组合十、内包装及外包装：内标签圆盘干燥剂防潮防静电袋5cartons/box外标签抽真空、热封10bags/carton至少160mm盖带和装有零件部分至少160mm盖带和至少160mm独立盖带或十一、信赖性实验：测试项目测试条件测试次数参考标准失效判定标准失效LED数量（PCS）防潮等级1.回流焊最高温度=260℃,10秒，2次回流焊；2.回流焊之前存储条件：30℃，相对湿度=70%，168H；-JEITAED-4701300.301﹟10/22焊接信赖性（无铅回流焊）回流焊最高温度=245±5℃，5秒（无铅回流焊）-JEITAED-4701303303A﹟20/22冷热循环-40℃30分钟~25℃5分钟~100℃30分钟~25℃5分钟300个循环JESD22-A104﹟10/22冷热冲击-35℃15分钟转换时间3分钟85℃15分钟300个循环JESD22-A106﹟10/22高温存储Ta=100℃1000小时JESD22-A103﹟10/22低温存储Ta=-40℃1000小时JESD22-A119﹟10/22常温老化Ta=25℃IF=20mA1000小时JESD22-A108﹟10/22（2）失效标准标准﹟项目测试条件失效标准﹟1正向电压(V F)I F=20mA＞U.S.L*1.1光强（IV）I F=20mA＜L.S.L*0.7反向电流(I R)V R=5V＞U.S.L*2.0﹟2焊接可靠性/锡膏覆盖焊盘比例小于95%★U.S.L:规格上限L.S.L:规格下限十二、使用注意事项：◆使用：1.过高的温度会影响LED的亮度以及其他性能，所以为使LED有较好的性能表现，应将LED远离热源。

D4DL中文资料

Compact Guard-locking Interlock Safety Door SwitchD4DLPolymer housing, IP65, and slow-action contacts with positive opening →.2 versions•Mechanical lock/Solenoid release •Solenoid lock/Mechanical releaseRotatable operating head provides four possible key entry slots.Incorporates an indicator that shows operation status at a glance.Double-insulation structure requires no grounding terminals. (with mark)Three types of Operation Key are available:•Horizontal mounting •Vertical mounting•Angle-adjustable vertical mounting Safety StandardsConformity:Machinery Directive, Low-voltage Directive, EN1088, SUV A Approval:Note:Approval for CSA C22.2 No. 14 is authorized by c mark.ESwitchesD4DL-jjjj -j123451.Conduit Size (2-conduit)1:Pg13.52:G 1/22.Built-in Switch (with Safety Switch and Lock Monitor Switch Contacts)C:1NC/1NO slow-action contacts plus 1NC slow-actioncontactD:2NC slow-action contacts plus 1NC slow-action contact 3.Head Mounting Direction F:Front4.Door Lock and ReleaseA:Mechanical lock / 24-VDC solenoid release (see note)B:Mechanical lock / 110-V AC solenoid release C:Mechanical lock / 230-V AC solenoid releaseG:24-VDC solenoid lock / mechanical release (see note)H:110-V AC solenoid lock / mechanical release J:230-V AC solenoid lock / mechanical release 5.IndicatorB:10 to 115 V AC/VDC (with orange LED indicator)E:100 to 250 V AC (with orange neon lamp indicator)Operation KeysD4DS-K j11.Key T ype1:Horizontal mounting 2:V ertical mounting3:Horizontal-adjustable vertical mounting5:V ertical/Horizontal-adjustable vertical mountingNote:Models marked with “∗” are recommendedHorizontal mountingTÜV (EN60947-5-1)Note:Use a 10-A fuse type gI or gG as a short-circuit protection device that conforms to IEC269.UL/CSA (UL508, CSA C22.2 No. 14)A300CharacteristicsNote: 1.The above values are initial values.2.Although the switch box is protected from dust or water penetration, do not use the D4DL in places where foreign material maypenetrate through the key hole on the head, otherwise switch damage or malfunctioning may occur.3.The above mechanical or electrical life is ensured at an ambient temperature of 5°C to 35°C and an ambient humidity of 40% to 70%.4.These values must be satisfied to ensure safe operation.Solenoid CharacteristicsIndicatorOperation key hole Terminal E3Terminal E4Operation key holeCamTerminal 11Terminal 12Terminal 23Terminal 24Main switchIndicator Release key Conduit opening SolenoidLock monitor switch Terminal E1 ( ) Terminal E2 ( ) Conduit openingTerminal 32 Terminal 31+~–~GuardInside equipmentLock spring112324123132Door closedAccess to machine is not allowed.Lock spring locks the door .Power to solenoid Door can be opened.Lock releasing springIndicates conditions where the Key is inserted and the lock is applied. Connect the terminals 12 to 31 to conform to BIA GS-ET-19.ONTravelKey fullyinserted.Key fullyextracted.Lock positionONTravelKey fullyinserted.Key fullyextracted.Internal Circuit DiagramLED T ype (10 to 115 V AC/DC)Constant-current diodeLED (orange)Neon Lamp T ype (100 to 250 V AC)R=130 KΩNeon lamp (orange)Circuit Connection ExampleCircuit is to be connected by user.•Connect terminals 12 to 31. (T o conform to BIA GS-ET-19.)•Do not connect the indicator in parallel to the contacts.Doing so may allow short-circuit current to flow while theindicator is damaged, causing equipment malfunction.•The 24-VDC solenoid has polarity. Be sure not to make wiringmistakes.•In the following connection example, the indicator will be lit whenthe door is open. (D4DL-1CF A-B)Power supply sideSolenoidAuxiliarycircuitSafetycircuit Ground+~–~(Orange)G9S-321-T j (24 VDC)+D4DL-j CFA-j /-j CFB-j /-CFC-j (Mechanical Lock T ype)+D4D-j 520N T 11T 12T 22T 21G9SINPCS1:Safety Switch (D4D-j 520N)S2:Safety Door Switch with solenoid lock (D4DL-j CFA-B)S3:Pushbutton switch for solenoid E S SW:Emergency-stop switch (A22E)KM1, KM2:Magnet Contactor (LC1-D)M:3-phase motorFeed back loop(Operation instruction) Emergency stop or standbyMotor control systemOff delay timerOUTc 12C 12G9S-301 (24 VDC)+D4DL-j CFG-j/-j CFH-j/-j CFJ-j (Solenoid Lock T ype)+D4D-j520 NINPCOUT c12C1SwitchD4DL-jjjj -jPre-travel distanceThree, 4.3-dia. holesIndicatorThree, cover counting screwsConduit capRelease keyConduit openingOperation KeyD4DS-K1Horizontal MountingFour, R2.15D4DS-K2Vertical MountingFour, R2.15D4DS-K3Horizontal-adjustable V ertical Mounting9 dia.4.5 dia.8 dia.Note:Each dimension has a tolerance of ±0.4 mm unless otherwise specified.D4DS-K5Horizontal/V ertical-adjustable V ertical MountingOperation Key InsertedD4DL + D4DS-K1D4DL + D4DS-K2D4DL + D4DS-K3NOTICEIf the D4DL is applied to an emergency stop circuit or safety circuit for prevention of injury, use the NC contact, which incorporates a positive opening mechanism, and make sure that the D4DL oper-ates in positive mode. Furthermore, secure the D4DL with screws or equivalent parts that are tightened in a single direction so that the D4DL or operation key cannot be easily removed or provide a protection cover to the D4DL and post a warning label near the D4DL.To protect the D4DL from damage due to short-circuits, connect the D4DL in parallel to a fuse that has a breaking current 1.5 to 2 times the rated current of the D4DL. If the D4DL is used under EN-ap-proved rating conditions, use a 10 A fuse, type gI or gG conforming to IEC 269.Do not supply power to the D4DL while wiring the D4DL.In order to prevent the D4DL from burning due to overvoltage, inser -tion of a protection fuse into the solenoid circuits is recommended.Do not use the D4DL in locations subject to explosive or flammable gases.Makesure that the load current does not exceed the rated current and that the load terminals are wired correctly .Pay utmost attention to correctly wire each terminal.After mounting and adjusting the D4DL, make sure that the D4DL operates properly .If the D4DL is imposed with force exceeding the lock strength, the D4DL may break and the equipment may continue operating.Do not drop or disassemble the D4DL.Release KeyThe release key is used to unlock the D4DL in case of emergency or if the power supply to the D4DL fails.Use an appropriate tool to set the release key to UNLOCK so that the lock will be released and the door can be opened.The release key is set at the UNLOCK position. Set the release key to the LOCK position before use.Mechanical Lock T ypeRelease keyThe release key applied to the door of a machine room ensures the safety of people adjusting the equipment in the machine room. If therelease key is set to UNLOCK, the door will not be locked when the door is closed and no power will be supplied to the equipment.Do not use the release key to start or stop machines.To prevent the release key from being used carelessly by unautho -rized people, set the release key of the D4DL in normal operation to UNLOCK and seal the release key with seal wax.MountingBe sure to mount the D4DL with a stopper as shown in the following illustration. Do not use the D4DL Switch as a stopper .Door StopperOperation keySwitchSet zone (0.5 to 3 mm)Solenoid Lock T ypeThe solenoid lock locks the door only when power is supplied to the solenoid. Therefore, the door will be unlocked if the power supply to the solenoid fails. Therefore, do not use the solenoid lock type for machines that may be operating and dangerous even after the ma -chine stops operating because of inertia.Life ExpectancyThe life of the D4DL will vary with the switching conditions. Before applying the D4DL, test the D4DL under actual operating conditions and be sure to use the D4DL in actual operation within switching times that will not lower the performance of the D4DL.Operating EnvironmentThe D4DL is for indoor use only. Do not use the D4DL outdoors.Otherwise, the D4DL may malfunction.Do not use the D4DL in the following locations:Locations with severe changes in temperatureLocations with excessive humidity that may cause condensation Locations with excessive vibrationLocations where metal dust, oil, or chemical may be sprayed onto the D4DLOperation KeyBe sure to use the dedicated Operation Key only .Do not operate the D4DL with anything other than the dedicated Operation Key. Otherwise, the safety of the system may not be maintained.Do not impose excessive force on the Operation Key inserted into the D4DL or drop the D4DL with the Operation Key inserted. Other -wise, the Operation Key may be deformed or broken.Force imposedDropSecure the Operation Key with a one-way screw , or an equivalent,so that the Operation Key cannot be easily removed.Locking the DoorThe D4DL may eventually break if the door opens accidentally due to the weight of the door , the vibration of the machine, or the bounc -ing of the door against the rubber bumper .Furthermore, the door may not unlocked if force is imposed on the operation key.Do not use the casing of the D4DL as a locking mechanism for the doorin such cases and be sure to prepare a special lock within the lock range of the D4DL (i.e., 0.5 to 3 mm).MountingReferto page 10 for the mounting dimensions of the Operation Key .Be sure that the Operation Key can be inserted properly with a toler -ance of ±1 mm in the upward, downward, left, or right direction,otherwise the D4DL may be damaged.±1 min.±1 min.Tightening T orqueBe sure to tighten each screw of the D4DL properly , otherwise the D4DL may malfunction.(3)(5)(1)(7)(6)(2)(4)Note:Tighten each screw together with a washer to the specified torque.MountingBe sure the that D4DL operates properly after mounting and adjust -ing the D4DL.Use M4 screws (one-way screws, etc.) and washers to mount the D4DL and Operation Key securely .Switch Mounting HolesThree, M4Operation Key Mounting Holes •Horizontal/V ertical Mounting D4DSK1/D4DS-K2OMRON CorporationIndustrial Control Components Division 28th Fl., Crystal T ower Bldg.,1-2-27, Shiromi, Chuo-ku,Osaka 540-6028 JapanPhone: (81)6-949-6025 Fax: (81)6-949-6029ALL DIMENSIONS SHOWN ARE IN MILLIMETERS.To convert millimeters into inches, multiply by 0.03937. T o convert grams into ounces, multiply by 0.03527.Cat. No. C107-E1-2In the interest of product improvement, specifications are subject to change without notice.Printed in Japan 1198-1M (0497) a。