BL-S41LL8中文资料

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IB-LCD240使用手册

“安理工电子”在矿用 PLC、矿用本安-非安隔离安全栅、组态软件、通讯设备、专用控制电路开发及工业自动化控制系统等方面拥有雄厚的技术研发实力和丰富的工程实践经验。本公司研发生产的 IB 系列工业级 PLC 拥有多项专利技术，性能达到煤矿级与军工级要求；KC01 系列矿用本安型 PLC 已通过“本安”认证，防爆证号：1094029U，在煤尘、瓦斯等危险环境中使用不需要采用隔爆措施，技术处于国内领先水平。
置该动态元件。在“屏幕”中选中某个动态元件，点该栏的“删除”按钮可删除该元件。可使用的动态元件如下： ① 数据显示用来显示 PLC 中的某个变量（数据存储器）的值。 ② 数据设定用来设定 PLC 中的某个变量（数据存储器）的值。 ③ 指示灯以指示灯的形式显示 PLC 中的某个位变量（继电器）的值。 ④ 棒图以棒图的形式显示 PLC 中的某个变量（数据存储器）的值。 ⑤ 位控文本用 PLC 中的某个位变量（继电器）来控制所显示的文本，即该变量为 ON 时显示什么文本，为 OFF 时显示什么文本（两者文本的长度应一致）。 ⑥ 字控文本用 PLC 中的某个变量（数据存储器）中的值来控制所显示的文本（文本的长度应一致）。 ⑦ 位控图片用 PLC 中的某个位变量（继电器）来控制所显示的图片，即该变量为 ON 时显示什么图片，为 OFF 时显示什么图片（两者图片的长度应一致）。 ⑧ 字控图片用 PLC 中的某个变量（数据存储器）中的值来控制所显示的图片（图片的长度应一致）。
“安理工电子”的目标：研发、生产工矿领域高端自动化产品，提供煤矿自动化全系列解决方案，打造成煤矿行业的“西门子”，最终实现矿用电子产品生产厂转变为自动化系统集成商。
声明
本说明书之著作权属于安徽理工大学电子设备厂。未经本公司书面同意，不得就本手册增删、改编、改造、或仿制。关于本手册所述之内容，本公司不负任何明示或暗示之保证或担保责任。本手册虽然经过了仔细的检查和核对，但是仍不排除文字拼写及技术描述错误的可能，此种错误或疏漏将于新版时予以更正。本手册的全部内容本公司享有随时修改的权利，且不另行通知。真诚感谢您购买和使用本公司产品，如果您在实际使用中遇到无法在本手册中得到解答的问题，或者您对我们的产品有好的意见和建议，请您及时与我们联系，我们会根据您的问题及时给予答复。

L78L12中文资料

L78L00SERIESPOSITIVE VOLTAGE REGULATORS®November 1998s OUTPUT CURRENT UP TO 100mAsOUTPUT VOLTAGESOF 3.3;5;6;8;9;12;15;18;24Vs THERMAL OVERLOAD PROTECTION s SHORT CIRCUIT PROTECTIONsNO EXTERNAL COMPONENTS ARE REQUIREDsAVAILABLEIN EITHER ±5%(AC)OR ±10%(C)SELECTIONDESCRIPTIONThe L78L00series of three-terminal positive regulators employ internal current limiting and thermal shutdown,making them essentially indestructible.If adequate heatsink is provided,they can deliver up to 100mA output current.They are intended as fixed voltage regulators in a wide range of applications including local or on-card regulation for elimination of noise and distribution problems associated with single-point regulation.In addition,they can be used with power pass elements to make high-current voltage regulators.The L78L00series used as Zener diode/resistor combination replacement,offers an effectiveBLOCK DIAGRAMSO-8TO-92output impedance improvement of typically two orders of magnetude,along with lower quiescent current and lower noise.SOT-891/19ABSOLUTE MAXIMUM RATINGSymbol ParameterValue Unit V iDC Input VoltageV o =3.3V to 9V 30V V o =12V to 15V 35V V o =18V to 24V40V I o Output Current 100mA P tot Power DissipationInternally limited (*)T st g Storage Temperature Range-40to 150o C T opOperating Junction Temperature RangeFor L78L00C,L78L00AC For L78L00AB0to 125-40to 125o C oC(*)Our SO-8package used for Voltage Regulators is modified internally to have pins 2,3,6and 7electrically commoned to the die attach flag.This particular frame decreases the total thermal resistance of the package and increases its ability to dissipate power when an appropriate area of copper on the printed circuit board is available for heatsinking.The external dimensions are the same as for the standard SO-8TEST CIRCUITSTHERMAL DATASymbolParameterSO-8TO-92SOT-89UnitR thj-ca se R thj-amb Thermal Resistance Junction-case Max Thermal Resistance Junction-ambientMax2055(*)20012o C/W oC/W(*)Considering 6cm 2of copper Board heat-sinkL78L002/19CONNECTION DIAGRAM AND ORDERING NUMBERS(top view)ORDERING NUMBERSType SO-8TO-92SOT-89Output VoltageL78L33AC L78L33AB L78L05C L78L05AC L78L05AB L78L06C L78L06AC L78L06AB L78L08C L78L08AC L78L08AB L78L09C L78L09AC L78L09AB L78L12C L78L12AC L78L12AB L78L15C L78L15AC L78L15AB L78L18C L78L18AC L78L18AB L78L24C L78L24AC L78L24ABL78L33ACDL78L33ABDL78L05CDL78L05ACDL78L05ABDL78L06CDL78L06ACDL78L06ABDL78L08CDL78L08ACDL78L08ABDL78L09CDL78L09ACDL78L09ABDL78L12CDL78L12ACDL78L12ABDL78L15CDL78L15ACDL78L15ABDL78L18CDL78L18ACDL78L18ABDL78L24CDL78L24ACDL78L24ABDL78L33ACZL78L33ABZL78L05CZL78L05ACZL78L05ABZL78L06CZL78L06ACZL78L06ABZL78L08CZL78L08ACZL78L08ABZL78L09CZL78L09ACZL78L09ABZL78L12CZL78L12ACZL78L12ABZL78L15CZL78L15ACZL78L15ABZL78L18CZL78L18ACZL78L18ABZL78L24CZL78L24ACZL78L24ABZL78L33ACUL78L33ABUL78L05ACUL78L05ABUL78L06ACUL78L06ABUL78L08ACUL78L08ABUL78L09ACUL78L09ABUL78L12ACUL78L12ABUL78L15ACUL78L15ABUL78L18ACUL78L18ABUL78L24ACUL78L24ABU3.3V3.3V5V5V5V6V6V6V8V8V8V9V9V9V12V12V12V15V15V15V18V18V18V24V24V24VSO-8TO-92pin1=V OUTpin2=GNDpin3=V INBOTTOM VIEWSOT-89L78L003/19ELECTRICAL CHARACTERISTICS FOR L78L05(refer to the test circuits,T j=0to125o C,V i=10V,I o=40mA,C i=0.33µF,C o=0.1µF unless otherwise specified)Symbol Parameter Test Conditions Min.Typ.Max.Unit V o Output Voltage T j=25o C 4.65 5.4VV o Output Voltage I o=1to40mA V i=7to20VI o=1to70mA V i=10V 4.54.55.55.5VV∆V o Line Regulation V i=7to20V T j=25o CV i=8to20V T j=25o C 200150mVmV∆V o Load Regulation I o=1to100mA T j=25o CI o=1to40mA T j=25o C 6030mVmVI d Quiescent Current T j=25o CT j=125o C65.5mAmA∆I d Quiescent Current Change I o=1to40mA0.2mA ∆I d Quiescent Current Change V i=8to20V 1.5mA eN Output Noise Voltage B=10Hz to100KHz T j=25o C40µV SVR Supply Voltage Rejection I o=40mA f=120Hz T j=25o CV i=8to18V4049dB V d Dropout Voltage 1.7VELECTRICAL CHARACTERISTICS FOR L78L06(refer to the test circuits,T j=0to125o C,V i=12V,I o=40mA,C i=0.33µF,C o=0.1µF unless otherwise specified)Symbol Parameter Test Conditions Min.Typ.Max.Unit V o Output Voltage T j=25o C 5.526 6.48VV o Output Voltage I o=1to40mA V i=8.5to20VI o=1to70mA V i=12V 5.45.46.66.6VV∆V o Line Regulation V i=8.5to20V T j=25o CV i=9to20V T j=25o C 200150mVmV∆V o Load Regulation I o=1to100mA T j=25o CI o=1to40mA T j=25o C 6030mVmVI d Quiescent Current T j=25o CT j=125o C65.5mAmA∆I d Quiescent Current Change I o=1to40mA0.2mA ∆I d Quiescent Current Change V i=8to20V 1.5mA eN Output Noise Voltage B=10Hz to100KHz T j=25o C50µV SVR Supply Voltage Rejection I o=40mA f=120Hz T j=25o CV i=9to20V3846dB V d Dropout Voltage 1.7V L78L004/19ELECTRICAL CHARACTERISTICS FOR L78L08(refer to the test circuits,T j=0to125o C,V i=14V,I o=40mA,C i=0.33µF,C o=0.1µF unless otherwise specified)Symbol Parameter Test Conditions Min.Typ.Max.Unit V o Output Voltage T j=25o C7.3688.64VV o Output Voltage I o=1to40mA V i=10.5to23VI o=1to70mA V i=14V 7.27.28.88.8VV∆V o Line Regulation V i=10.5to23V T j=25o CV i=11to23V T j=25o C 200150mVmV∆V o Load Regulation I o=1to100mA T j=25o CI o=1to40mA T j=25o C 8040mVmVI d Quiescent Current T j=25o CT j=125o C65.5mAmA∆I d Quiescent Current Change I o=1to40mA0.2mA ∆I d Quiescent Current Change V i=11to23V 1.5mA eN Output Noise Voltage B=10Hz to100KHz T j=25o C60µV SVR Supply Voltage Rejection I o=40mA f=120Hz T j=25o CV i=12to23V3645dB V d Dropout Voltage 1.7VELECTRICAL CHARACTERISTICS FOR L78L09(refer to the test circuits,T j=0to125o C,V i=15V,I o=40mA,C i=0.33µF,C o=0.1µF unless otherwise specified)Symbol Parameter Test Conditions Min.Typ.Max.Unit V o Output Voltage T j=25o C8.2899.72VV o Output Voltage I o=1to40mA V i=11.5to23VI o=1to70mA V i=15V 8.18.19.99.9VV∆V o Line Regulation V i=11.5to23V T j=25o CV i=12to23V T j=25o C 250200mVmV∆V o Load Regulation I o=1to100mA T j=25o CI o=1to40mA T j=25o C 8040mVmVI d Quiescent Current T j=25o CT j=125o C65.5mAmA∆I d Quiescent Current Change I o=1to40mA0.2mA∆I d Quiescent Current Change V i=12to23V 1.5mA eN Output Noise Voltage B=10Hz to100KHz T j=25o C70µV SVR Supply Voltage Rejection I o=40mA f=120Hz T j=25o CV i=12to23V3644dBV d Dropout Voltage 1.7VL78L005/19ELECTRICAL CHARACTERISTICS FOR L78L12(refer to the test circuits,T j=0to125o C,V i=19V,I o=40mA,C i=0.33µF,C o=0.1µF unless otherwise specified)Symbol Parameter Test Conditions Min.Typ.Max.Unit V o Output Voltage T j=25o C11.11212.9VV o Output Voltage I o=1to40mA V i=14.5to27VI o=1to70mA V i=19V 10.810.813.213.2VV∆V o Line Regulation V i=14.5to27V T j=25o CV i=16to27V T j=25o C 250200mVmV∆V o Load Regulation I o=1to100mA T j=25o CI o=1to40mA T j=25o C 10050mVmVI d Quiescent Current T j=25o CT j=125o C 6.56mAmA∆I d Quiescent Current Change I o=1to40mA0.2mA ∆I d Quiescent Current Change V i=16to27V 1.5mA eN Output Noise Voltage B=10Hz to100KHz T j=25o C80µV SVR Supply Voltage Rejection I o=40mA f=120Hz T j=25o CV i=15to25V3642dB V d Dropout Voltage 1.7VELECTRICAL CHARACTERISTICS FOR L78L15(refer to the test circuits,T j=0to125o C,V i=23V,I o=40mA,C i=0.33µF,C o=0.1µF unless otherwise specified)Symbol Parameter Test Conditions Min.Typ.Max.Unit V o Output Voltage T j=25o C13.81516.2VV o Output Voltage I o=1to40mA V i=17.5to30VI o=1to70mA V i=23V 13.513.516.516.5VV∆V o Line Regulation V i=17.5to30V T j=25o CV i=20to30V T j=25o C 300250mVmV∆V o Load Regulation I o=1to100mA T j=25o CI o=1to40mA T j=25o C 15075mVmVI d Quiescent Current T j=25o CT j=125o C 6.56mAmA∆I d Quiescent Current Change I o=1to40mA0.2mA ∆I d Quiescent Current Change V i=20to30V 1.5mA eN Output Noise Voltage B=10Hz to100KHz T j=25o C90µV SVR Supply Voltage Rejection I o=40mA f=120Hz T j=25o CV i=18.5to28.5V3339dB V d Dropout Voltage 1.7V L78L006/19ELECTRICAL CHARACTERISTICS FOR L78L18(refer to the test circuits,T j=0to125o C,V i=27V,I o=40mA,C i=0.33µF,C o=0.1µF unless otherwise specified)Symbol Parameter Test Conditions Min.Typ.Max.Unit V o Output Voltage T j=25o C16.61819.4VV o Output Voltage I o=1to40mA V i=22to33VI o=1to70mA V i=27V 16.216.219.819.8VV∆V o Line Regulation V i=22to33V T j=25o CV i=22to33V T j=25o C 320270mVmV∆V o Load Regulation I o=1to100mA T j=25o CI o=1to40mA T j=25o C 17085mVmVI d Quiescent Current T j=25o CT j=125o C 6.56mAmA∆I d Quiescent Current Change I o=1to40mA0.2mA ∆I d Quiescent Current Change V i=23to33V 1.5mA eN Output Noise Voltage B=10Hz to100KHz T j=25o C120µV SVR Supply Voltage Rejection I o=40mA f=120Hz T j=25o CV i=23to33V3238dB V d Dropout Voltage 1.7VELECTRICAL CHARACTERISTICS FOR L78L24(refer to the test circuits,T j=0to125o C,V i=33V,I o=40mA,C i=0.33µF,C o=0.1µF unless otherwise specified)Symbol Parameter Test Conditions Min.Typ.Max.Unit V o Output Voltage T j=25o C22.12425.9VV o Output Voltage I o=1to40mA V i=27to38VI o=1to70mA V i=33V 21.621.626.426.4VV∆V o Line Regulation V i=27to38V T j=25o CV i=28to38V T j=25o C 350300mVmV∆V o Load Regulation I o=1to100mA T j=25o CI o=1to40mA T j=25o C 200100mVmVI d Quiescent Current T j=25o CT j=125o C 6.56mAmA∆I d Quiescent Current Change I o=1to40mA0.2mA∆I d Quiescent Current Change V i=28to38V 1.5mA eN Output Noise Voltage B=10Hz to100KHz T j=25o C200µV SVR Supply Voltage Rejection I o=40mA f=120Hz T j=25o CV i=29to35V3037dBV d Dropout Voltage 1.7VL78L007/19ELECTRICAL CHARACTERISTICS FOR L78L33AB AND L78L33AC(refer to the test circuits,V i=8.3V,I o=40mA,C i=0.33µF,C o=0.1µF,T j=0to125o C for L78L33AC,T j=-40to125o C for L78L33AB,unless otherwise specified)Symbol Parameter Test Conditions Min.Typ.Max.Unit V o Output Voltage T j=25o C 3.168 3.3 3.432VV o Output Voltage I o=1to40mA V i=5.3to20VI o=1to70mA V i=8.3V 3.1353.1353.4653.465VV∆V o Line Regulation V i=5.3to20V T j=25o CV i=6.3to20V T j=25o C 150100mVmV∆V o Load Regulation I o=1to100mA T j=25o CI o=1to40mA T j=25o C 6030mVmVI d Quiescent Current T j=25o CT j=125o C65.5mAmA∆I d Quiescent Current Change I o=1to40mA0.1mA ∆I d Quiescent Current Change V i=6.3to20V 1.5mA eN Output Noise Voltage B=10Hz to100KHz T j=25o C40µV SVR Supply Voltage Rejection I o=40mA f=120Hz T j=25o CV i=6.3to16.3V4149dB V d Dropout Voltage 1.7VELECTRICAL CHARACTERISTICS FOR L78L05AB AND L78L05AC(refer to the test circuits,V i=10V,I o=40mA,C i=0.33µF,C o=0.1µF,T j=0to125o C for L78L05AC,T j=-40to125o C for L78L05AB,unless otherwise specified)Symbol Parameter Test Conditions Min.Typ.Max.Unit V o Output Voltage T j=25o C 4.85 5.2VV o Output Voltage I o=1to40mA V i=7to20VI o=1to70mA V i=10V 4.754.755.255.25VV∆V o Line Regulation V i=7to20V T j=25o CV i=8to20V T j=25o C 150100mVmV∆V o Load Regulation I o=1to100mA T j=25o CI o=1to40mA T j=25o C 6030mVmVI d Quiescent Current T j=25o CT j=125o C65.5mAmA∆I d Quiescent Current Change I o=1to40mA0.1mA ∆I d Quiescent Current Change V i=8to20V 1.5mA eN Output Noise Voltage B=10Hz to100KHz T j=25o C40µV SVR Supply Voltage Rejection I o=40mA f=120Hz T j=25o CV i=8to18V4149dB V d Dropout Voltage 1.7V L78L008/19ELECTRICAL CHARACTERISTICS FOR L78L06AB AND L78L06AC(refer to the test circuits,V i=12V,I o=40mA,C i=0.33µF,C o=0.1µF,T j=0to125o C for L78L06AC,T j=-40to125o C for L78L06AB,unless otherwise specified)Symbol Parameter Test Conditions Min.Typ.Max.Unit V o Output Voltage T j=25o C 5.766 6.24VV o Output Voltage I o=1to40mA V i=8.5to20VI o=1to70mA V i=12V 5.75.76.36.3VV∆V o Line Regulation V i=8.5to20V T j=25o CV i=9to20V T j=25o C 150100mVmV∆V o Load Regulation I o=1to100mA T j=25o CI o=1to40mA T j=25o C 6030mVmVI d Quiescent Current T j=25o CT j=125o C65.5mAmA∆I d Quiescent Current Change I o=1to40mA0.1mA ∆I d Quiescent Current Change V i=9to20V 1.5mA eN Output Noise Voltage B=10Hz to100KHz T j=25o C50µV SVR Supply Voltage Rejection I o=40mA f=120Hz T j=25o CV i=9to20V3946dB V d Dropout Voltage 1.7VELECTRICAL CHARACTERISTICS FOR L78L08AB AND L78L08AC(refer to the test circuits,V i=14V,I o=40mA,C i=0.33µF,C o=0.1µF,T j=0to125o C for L78L08AC,T j=-40to125o C for L78L08AB,unless otherwise specified)Symbol Parameter Test Conditions Min.Typ.Max.Unit V o Output Voltage T j=25o C7.6888.32VV o Output Voltage I o=1to40mA V i=10.5to23VI o=1to70mA V i=14V 7.67.68.48.4VV∆V o Line Regulation V i=10.5to23V T j=25o CV i=11to23V T j=25o C 175125mVmV∆V o Load Regulation I o=1to100mA T j=25o CI o=1to40mA T j=25o C 8040mVmVI d Quiescent Current T j=25o CT j=125o C65.5mAmA∆I d Quiescent Current Change I o=1to40mA0.1mA∆I d Quiescent Current Change V i=11to23V 1.5mA eN Output Noise Voltage B=10Hz to100KHz T j=25o C60µV SVR Supply Voltage Rejection I o=40mA f=120Hz T j=25o CV i=12to23V3745dBV d Dropout Voltage 1.7VL78L009/19ELECTRICAL CHARACTERISTICS FOR L78L09AB AND L78L09AC(refer to the test circuits,V i=15V,I o=40mA,C i=0.33µF,C o=0.1µF,T j=0to125o C for L78L09AC,T j=-40to125o C for L78L09AB,unless otherwise specified)Symbol Parameter Test Conditions Min.Typ.Max.Unit V o Output Voltage T j=25o C8.6499.36VV o Output Voltage I o=1to40mA V i=11.5to23VI o=1to70mA V i=15V 8.558.559.459.45VV∆V o Line Regulation V i=11.5to23V T j=25o CV i=12to23V T j=25o C 225150mVmV∆V o Load Regulation I o=1to100mA T j=25o CI o=1to40mA T j=25o C 8040mVmVI d Quiescent Current T j=25o CT j=125o C65.5mAmA∆I d Quiescent Current Change I o=1to40mA0.1mA ∆I d Quiescent Current Change V i=12to23V 1.5mA eN Output Noise Voltage B=10Hz to100KHz T j=25o C70µV SVR Supply Voltage Rejection I o=40mA f=120Hz T j=25o CV i=12to23V3744dB V d Dropout Voltage 1.7VELECTRICAL CHARACTERISTICS FOR L78L12AB AND L78L12AC(refer to the test circuits,V i=19V,I o=40mA,C i=0.33µF,C o=0.1µF,T j=0to125o C for L78L12AC,T j=-40to125o C for L78L12AB,unless otherwise specified)Symbol Parameter Test Conditions Min.Typ.Max.Unit V o Output Voltage T j=25o C11.51212.5VV o Output Voltage I o=1to40mA V i=14.5to27VI o=1to70mA V i=19V 11.411.412.612.6VV∆V o Line Regulation V i=14.5to27V T j=25o CV i=16to27V T j=25o C 250200mVmV∆V o Load Regulation I o=1to100mA T j=25o CI o=1to40mA T j=25o C 10050mVmVI d Quiescent Current T j=25o CT j=125o C 6.56mAmA∆I d Quiescent Current Change I o=1to40mA0.1mA ∆I d Quiescent Current Change V i=16to27V 1.5mA eN Output Noise Voltage B=10Hz to100KHz T j=25o C80µV SVR Supply Voltage Rejection I o=40mA f=120Hz T j=25o CV i=15to25V3742dB V d Dropout Voltage 1.7V L78L0010/19ELECTRICAL CHARACTERISTICS FOR L78L15AB AND L78L15AC(refer to the test circuits,V i=23V,I o=40mA,C i=0.33µF,C o=0.1µF,T j=0to125o C for L78L15AC,T j=-40to125o C for L78L15AB,unless otherwise specified)Symbol Parameter Test Conditions Min.Typ.Max.Unit V o Output Voltage T j=25o C14.41515.6VV o Output Voltage I o=1to40mA V i=17.5to30VI o=1to70mA V i=23V 14.2514.2515.7515.75VV∆V o Line Regulation V i=17.5to30V T j=25o CV i=20to30V T j=25o C 300250mVmV∆V o Load Regulation I o=1to100mA T j=25o CI o=1to40mA T j=25o C 15075mVmVI d Quiescent Current T j=25o CT j=125o C 6.56mAmA∆I d Quiescent Current Change I o=1to40mA0.1mA ∆I d Quiescent Current Change V i=20to30V 1.5mA eN Output Noise Voltage B=10Hz to100KHz T j=25o C90µV SVR Supply Voltage Rejection I o=40mA f=120Hz T j=25o CV i=18.5to28.5V3439dB V d Dropout Voltage 1.7VELECTRICAL CHARACTERISTICS FOR L78L18AB AND L78L18AC(refer to the test circuits,V i=27V,I o=40mA,C i=0.33µF,C o=0.1µF,T j=0to125o C for L78L18AC,T j=-40to125o C for L78L18AB,unless otherwise specified)Symbol Parameter Test Conditions Min.Typ.Max.Unit V o Output Voltage T j=25o C17.31818.7VV o Output Voltage I o=1to40mA V i=22to33VI o=1to70mA V i=27V 17.117.118.918.9VV∆V o Line Regulation V i=22to33V T j=25o CV i=22to33V T j=25o C 320270mVmV∆V o Load Regulation I o=1to100mA T j=25o CI o=1to40mA T j=25o C 17085mVmVI d Quiescent Current T j=25o CT j=125o C 6.56mAmA∆I d Quiescent Current Change I o=1to40mA0.1mA∆I d Quiescent Current Change V i=23to33V 1.5mA eN Output Noise Voltage B=10Hz to100KHz T j=25o C120µV SVR Supply Voltage Rejection I o=40mA f=120Hz T j=25o CV i=23to33V3338dBV d Dropout Voltage 1.7V11/19ELECTRICAL CHARACTERISTICS FOR L78L24AB AND L78L24AC(refer to the test circuits,V i=33V,I o=40mA,C i=0.33µF,C o=0.1µF,T j=0to125o C for L78L24AC,T j=-40to125o C for L78L24AB,unless otherwise specified)Symbol Parameter Test Conditions Min.Typ.Max.Unit V o Output Voltage T j=25o C232425VV o Output Voltage I o=1to40mA V i=27to38VI o=1to70mA V i=33V 22.822.825.225.2VV∆V o Line Regulation V i=27to38V T j=25o CV i=28to38V T j=25o C 350300mVmV∆V o Load Regulation I o=1to100mA T j=25o CI o=1to40mA T j=25o C 200100mVmVI d Quiescent Current T j=25o CT j=125o C 6.56mAmA∆I d Quiescent Current Change I o=1to40mA0.1mA ∆I d Quiescent Current Change V i=28to38V 1.5mA eN Output Noise Voltage B=10Hz to100KHz T j=25o C200µV SVR Supply Voltage Rejection I o=40mA f=120Hz T j=25o CV i=29to35V3137dB V d Dropout Voltage 1.7V12/19Figure3:L78L05/12/24Thermal Shutdown.Figure4:L78L05/12Quiescent Current vsOutput CurrentFigure5:L78L05Quiescent Current vs Input Voltage.Figure6:L78L05/12/24Output Characteristics.Figure1:L78L05/12Output Voltage vs AmbientTemperatureFigure2:L78L05/12/24Load Characteristics.13/19Figure7:L78L05/12/24Ripple Rejection.Figure8:L78L05Dropout Characteristics. Figure9:L78L00Series Short Circuit OutputCurrent.TYPICAL APPLICATIONS:Figure10:High Output Current Short Circuit Protected14/19Figure11:Output Boost Circuit.Figure12:Current Regulator.Figure13:Adjustable Output Regulator15/19SO-8MECHANICAL DATAmm inch DIM.MIN.TYP.MAX.MIN.TYP.MAX.A 1.750.068a10.10.250.0030.009 a2 1.650.064 a30.650.850.0250.033 b0.350.480.0130.018 b10.190.250.0070.010 C0.250.50.0100.019 c145(typ.)D 4.8 5.00.1880.196E 5.8 6.20.2280.244e 1.270.050e3 3.810.150F 3.8 4.00.140.157L0.4 1.270.0150.050 M0.60.023 S8(max.)0016023 16/19SOT-89MECHANICAL DATAmm milsDIM.MIN.TYP.MAX.MIN.TYP.MAX.A 1.4 1.655.163.0B0.440.5617.322.0B10.360.4814.218.9C0.350.4413.817.3C10.350.4413.817.3D 4.4 4.6173.2181.1D1 1.62 1.8363.872.0E 2.29 2.690.2102.4e 1.42 1.5755.961.8e1 2.92 3.07115.0120.9H 3.94 4.25155.1167.3L0.89 1.235.047.2P025H17/19TO-92MECHANICAL DATAmm inch DIM.MIN.TYP.MAX.MIN.TYP.MAX.A 4.58 5.330.1800.210B 4.45 5.20.1750.204C 3.2 4.20.1260.165D12.70.500E 1.270.050F0.40.510.0160.020 G0.350.1418/19Information furnished is believed to be accurate and reliable.However,STMicroelectronics assumes no responsibility for the consequence s of use of such information nor for any infringement of patents or other rights of third parties which may result from its use.No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics.Specification mentioned in this publication are subject to change without notice.This publication supersedes and replaces all information previously supplied.STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.The ST logo is a registered trademark of STMicroelectronics©1998STMicroelectronics–Printed in Italy–All Rights ReservedSTMicroelectronics GROUP OF COMPANIESAustralia-Brazil-Canada-China-France-Germany-Italy-Japan-Korea-Malaysia-Malta-Mexico-Morocco-The Netherlands-Singapore-Spain-Sweden-Switzerland-Taiwan-Thailand-United Kingdom-U.S.A..19/19。

LH28F640BFB-PBTL80资料

• Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company.• When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions.(1) The products covered herein are designed and manufactured for the following application areas. When using theproducts covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph(3).• Office electronics• Instrumentation and measuring equipment• Machine tools• Audiovisual equipment• Home appliance• Communication equipment other than for trunk lines(2) Those contemplating using the products covered herein for the following equipment which demands highreliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system.• Control and safety devices for airplanes, trains, automobiles, and other transportation equipment• Mainframe computers• Traffic control systems• Gas leak detectors and automatic cutoff devices• Rescue and security equipment• Other safety devices and safety equipment, etc.(3) Do not use the products covered herein for the following equipment which demands extremely high performancein terms of functionality, reliability, or accuracy.• Aerospace equipment• Communications equipment for trunk lines• Control equipment for the nuclear power industry• Medical equipment related to life support, etc.(4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a salesrepresentative of the company.• Please direct all queries regarding the products covered herein to a sales representative of the company.PAGE 0.8mm pitch 60-Ball CSP Pinout (3)Pin Descriptions (4)Simultaneous Operation ModesAllowed with Four Planes (5)Memory Map (6)Identifier Codes and OTP Addressfor Read Operation (7)Identifier Codes and OTP Address forRead Operation on Partition Configuration (7)OTP Block Address Map for OTP Program (8)Bus Operation (9)Command Definitions (10)Functions of Block Lock and Block Lock-Down (12)Block Locking State Transitions uponCommand Write (12)Block Locking State Transitions uponWP# Transition (13)Status Register Definition (14)PAGE Extended Status Register Definition (15)Partition Configuration Register Definition (16)Partition Configuration (16)1 Electrical Specifications (17)1.1 Absolute Maximum Ratings (17)1.2 Operating Conditions (17)1.2.1 Capacitance (18)1.2.2 AC Input/Output Test Conditions (18)1.2.3 DC Characteristics (19)1.2.4 AC Characteristics- Read-Only Operations (21)1.2.5 AC Characteristics- Write Operations (25)1.2.6 Reset Operations (27)1.2.7 Block Erase, Full Chip Erase,(Page Buffer) Program andOTP Program Performance (28)2 Related Document Information (29)CONTENTSLH28F640BFB-PBTL8064Mbit (4Mbit×16)Page Mode Dual Work Flash MEMORY64M density with 16Bit I/O InterfaceHigh Performance Reads• 80/35ns 8-Word Page ModeConfigurative 4-Plane Dual Work• Flexible Partitioning• Read operations during Block Erase or (Page Buffer) Program• Status Register for Each PartitionLow Power Operation• 2.7V Read and Write Operations• V CCQ for Input/Output Power Supply Isolation• Automatic Power Savings Mode Reduces I CCRin Static ModeEnhanced Code + Data Storage• 5µs Typical Erase/Program SuspendsOTP (One Time Program) Block• 4-Word Factory-Programmed Area• 4-Word User-Programmable AreaHigh Performance Program with Page Buffer• 16-Word Page Buffer• 5µs/Word (Typ.) at 12V V PPOperating Temperature 0°C to +70°CCMOS Process (P-type silicon substrate) Flexible Blocking Architecture• Eight 4K-word Parameter Blocks• One-hundred and twenty-seven 32K-word Main Blocks• Bottom Parameter LocationEnhanced Data Protection Features• Individual Block Lock and Block Lock-Down with Zero-Latency• All blocks are locked at power-up or device reset.• Absolute Protection with V PP≤V PPLK• Block E rase, Full Chip E rase, (Page Buffer) Word Program Lockout during Power TransitionsAutomated Erase/Program Algorithms• 3.0V Low-Power 11µs/Word (Typ.)Programming• 12V No Glue Logic 9µs/Word (Typ.)Production Programming and 0.5s Erase (Typ.)Cross-Compatible Command Support• Basic Command Set• Common Flash Interface (CFI)Extended Cycling Capability• Minimum 100,000 Block Erase Cycles0.8mm pitch 60-Ball CSPETOX TM* Flash TechnologyNot designed or rated as radiation hardenedThe product, which is 4-Plane Page Mode Dual Work (Simultaneous Read while Erase/Program) Flash memory, is a low power, high density, low cost, nonvolatile read/write storage solution for a wide range of applications. The product can operate at V CC=2.7V-3.6V and V PP=1.65V-3.6V or 11.7V-12.3V. Its low voltage operation capability greatly extends battery life for portable applications.The product provides high performance asynchronous page mode. It allows code execution directly from Flash, thus eliminating time consuming wait states. Furthermore, its newly configurative partitioning architecture allows flexible dual work operation.The memory array block architecture utilizes Enhanced Data Protection features, and provides separate Parameter and Main Blocks that provide maximum flexibility for safe nonvolatile code and data storage.Fast program capability is provided through the use of high speed Page Buffer Program.Special OTP (One Time Program) block provides an area to store permanent code such as a unique number.* ETOX is a trademark of Intel Corporation.Table 1.Pin DescriptionsSymbol Type Name and FunctionA0-A21INPUT ADDRESS INPUTS: Inputs for addresses. 64M: A0-A21DQ0-DQ15INPUT/OUTPUT DATA INPUTS/OUTPUTS: Inputs data and commands during CUI (Command User Interface) write cycles, outputs data during memory array, status register, query code, identifier code and partition configuration register code reads. Data pins float to high-impedance (High Z) when the chip or outputs are deselected. Data is internally latched during an erase or program cycle.CE#INPUT CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense amplifiers. CE#-high (V IH) deselects the device and reduces power consumption to standby levels.RST#INPUT RESET: When low (V IL), RST# resets internal automation and inhibits write operations which provides data protection. RST#-high (V IH) enables normal operation. After power-up or reset mode, the device is automatically set to read array mode. RST# must be low during power-up/down.OE#INPUT OUTPUT ENABLE: Gates the device’s outputs during a read cycle.WE#INPUT WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on the rising edge of CE# or WE# (whichever goes high first).WP#INPUT WRITE PROTECT: When WP# is V IL, locked-down blocks cannot be unlocked. Erase or program operation can be executed to the blocks which are not locked and not locked-down. When WP# is V IH, lock-down is disabled.V PP INPUT MONITORING POWER SUPPLY VOLTAGE: V PP is not used for power supply pin. With V PP≤V PPLK, block erase, full chip erase, (page buffer) program or OTP program cannot be executed and should not be attempted.Applying 12V±0.3V to V PP provides fast erasing or fast programming mode. In this mode, V PP is power supply pin. Applying 12V±0.3V to V PP during erase/program can only be done for a maximum of 1,000 cycles on each block. V PP may be connected to 12V±0.3V for a total of 80 hours maximum. Use of this pin at 12V beyond these limits may reduce block cycling capability or cause permanent damage.V CC SUPPLY DE VICE POWE R SUPPLY (2.7V-3.6V): With V CC≤V LKO, all write attempts to the flash memory are inhibited. Device operations at invalid V CC voltage (see DC Characteristics) produce spurious results and should not be attempted.V CCQ SUPPLY INPUT/OUTPUT POWE R SUPPLY (2.7V-3.6V): Power supply for all input/outputpins.GND SUPPLY GROUND: Do not float any ground pins.NC NO CONNECT: Lead is not internally connected; it may be driven or floated.NOTES:1. "X" denotes the operation available.2. Configurative Partition Dual Work Restrictions:Status register reflects partition state, not WSM (Write State Machine) state - this allows a status register for each partition. Only one partition can be erased or programmed at a time - no command mands must be written to an address within the block targeted by that command.Table 2.Simultaneous Operation Modes Allowed with Four Planes (1, 2)IF ONE PARTITION IS:THEN THE MODES ALLOWED IN THE OTHER PARTITION IS:Read Array Read ID/OTP Read Status Read Query Word Program Page Buffer Program OTP Program Block Erase Full Chip Erase ProgramSuspendBlockEraseSuspend Read Array X X X X X X X X X Read ID/OTP X X X X X X X X X Read Status X X X X X X XX XX X Read Query X X X X XXXXX Word Program X X X X X Page Buffer Program XXX XXOTP Program X Block E rase XXX XFull Chip Erase X Program Suspend X X X X XBlock Erase SuspendXXXXXXXNOTES:1. The address A 21-A 16 are shown in below table for reading the manufacturer code, device code, device configuration code and OTP data.2. Bottom parameter device has its parameter blocks in the plane0 (The lowest address).3. Block Address = The beginning location of a block address within the partition to which the Read Identifier Codes/OTP command (90H) has been written.DQ 15-DQ 2 are reserved for future implementation.4. PCRC=Partition Configuration Register Code.5. OTP-LK=OTP Block Lock configuration.6. OTP=OTP Block data.NOTES:1. The address to read the identifier codes or OTP data is dependent on the partition which is selected when writing the Read Identifier Codes/OTP command (90H).2. Refer to Table 12 for the partition configuration register.Table 3.Identifier Codes and OTP Address for Read OperationCodeAddress [A 15-A 0]Data [DQ 15-DQ 0]Notes Manufacturer Code Manufacturer Code0000H 00B0H 1Device CodeBottom Parameter Device Code 0001H00B1H 1, 2Block Lock Configuration CodeBlock is Unlocked Block Address + 2DQ 0 = 03Block is LockedDQ 0 = 13Block is not Locked-Down DQ 1 = 03Block is Locked-DownDQ 1 = 13Device Configuration Code Partition Configuration Register 0006H PCRC 1, 4OTPOTP Lock0080H OTP-LK 1, 5OTP 0081-0088HOTP1, 6Table 4.Identifier Codes and OTP Address for Read Operation on Partition Configuration (1) (64M-bit device)Partition Configuration Register (2)Address (64M-bit device)PCR.10PCR.9PCR.8[A 21-A 16]00000H 00100H or 10H 01000H or 20H 10000H or 30H 01100H or 10H or 20H 11000H or 20H or 30H 10100H or 10H or 30H 11100H or 10H or 20H or 30HNOTES:1. Refer to DC Characteristics. When V PP ≤V PPLK , memory contents can be read, but cannot be altered.2. X can be V IL or V IH for control pins and addresses, and V PPLK or V PPH1/2 for V PP . See DC Characteristics for V PPLK and V PPH1/2 voltages.3. RST# at GND±0.2V ensures the lowest power consumption.4. Command writes involving block erase, full chip erase, (page buffer) program or OTP program are reliably executed when V PP =V PPH1/2 and V CC =2.7V-3.6V.5. Refer to Table 6 for valid D IN during a write operation.6. Never hold OE# low and WE# low at the same timing.7. Refer to Appendix of LH28F640BF series for more information about query code.Table 5.Bus Operation (1, 2)Mode Notes RST#CE#OE#WE#Address V PP DQ 0-15Read Array 6V IH V IL V IL V IH X X D OUT Output Disable V IH V IL V IH V IH X X High Z Standby V IH V IH X X X X High Z Reset3V IL X X X X X High Z Read Identifier Codes/OTP 6V IH V IL V IL V IH See Table 3 and Table 4X See Table 3 and Table 4Read Query 6,7V IH V IL V IL V IH See AppendixX See Appendix Write4,5,6V IHV ILV IHV ILXXD INNOTES:1. Bus operations are defined in Table 5.2. All addresses which are written at the first bus cycle should be the same as the addresses which are written at the second bus cycle.X=Any valid address within the device.PA=Address within the selected partition.IA=Identifier codes address (See Table 3 and Table 4).QA=Query codes address. Refer to Appendix of LH28F640BF series for details.BA=Address within the block being erased, set/cleared block lock bit or set block lock-down bit.WA=Address of memory location for the Program command or the first address for the Page Buffer Program command.OA=Address of OTP block to be read or programmed (See Figure 3).PCRC=Partition configuration register code presented on the address A 0-A 15.3. ID=Data read from identifier codes. (See Table 3 and Table 4).QD=Data read from query database. Refer to Appendix of LH28F640BF series for details.SRD=Data read from status register. See Table 10 and Table 11 for a description of the status register bits.WD=Data to be programmed at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first) during command write cycles.OD=Data within OTP block. Data is latched on the rising edge of WE# or CE# (whichever goes high first) during command write cycles.N-1=N is the number of the words to be loaded into a page buffer.4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock configuration code, partition configuration register code and the data within OTP block (See Table 3 and Table 4).The Read Query command is available for reading CFI (Common Flash Interface) information.5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked block can be erased or programmed when RST# is V IH .6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup.7. Following the third bus cycle, input the program sequential address and write data of "N" times. Finally, input the any valid address within the target block to be programmed and the confirm command (D0H). Refer to Appendix ofTable mand Definitions (11)CommandBusCycles Req ’d Notes First Bus CycleSecond Bus Cycle Oper (1)Addr (2)Data Oper (1)Addr (2)Data (3)Read Array1Write PA FFH Read Identifier Codes/OTP ≥ 24Write PA 90H Read IA or OA ID or OD Read Query ≥ 24Write PA 98H Read QA QD Read Status Register 2Write PA 70H ReadPASRDClear Status Register 1Write PA 50H Block Erase 25Write BA 20H Write BA D0H Full Chip Erase 25,9Write X 30H Write X D0H Program25,6Write WA 40H or 10H Write WA WD Page Buffer Program ≥ 45,7Write WA E8H WriteWAN-1Block Erase and (Page Buffer) Program Suspend18,9Write PA B0H Block Erase and (Page Buffer) Program Resume 18,9Write PA D0H Set Block Lock Bit 2Write BA 60H Write BA 01H Clear Block Lock Bit 210Write BA 60H Write BA D0H Set Block Lock-down Bit 2Write BA 60H Write BA 2FH OTP Program29Write OA C0H Write OA OD Set Partition Configuration Register2WritePCRC60HWritePCRC04HLH28F640BF series for details.8. If the program operation in one partition is suspended and the erase operation in other partition is also suspended, the suspended program operation should be resumed first, and then the suspended erase operation should be resumed next. 9. Full chip erase and OTP program operations can not be suspended. The OTP Program command can not be accepted while the block erase operation is being suspended.10. Following the Clear Block Lock Bit command, block which is not locked-down is unlocked when WP# is V IL. When WP# is V IH, lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration.11. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used.NOTES:1. DQ 0=1: a block is locked; DQ 0=0: a block is unlocked.DQ 1=1: a block is locked-down; DQ 1=0: a block is not locked-down.2. Erase and program are general terms, respectively, to express: block erase, full chip erase and (page buffer) program operations.3. At power-up or device reset, all blocks default to locked state and are not locked-down, that is,[001] (WP#=0) or [101] (WP#=1), regardless of the states before power-off or reset operation.4. When WP# is driven to V IL in [110] state, the state changes to [011] and the blocks are automatically locked.5. OTP (One Time Program) block has the lock function which is different from those described above.NOTES:1. "Set Lock" means Set Block Lock Bit command, "Clear Lock" means Clear Block Lock Bit command and "Set Lock-down" means Set Block Lock-Down Bit command.2. When the Set Block Lock-Down Bit command is written to the unlocked block (DQ 0=0), the corresponding block is locked-down and automatically locked at the same time.3. "No Change" means that the state remains unchanged after the command written.4. In this state transitions table, assumes that WP# is not changed and fixed V IL or V IH .Table 7.Functions of Block Lock (5) and Block Lock-DownCurrent StateErase/Program Allowed (2)State WP#DQ 1(1)DQ 0(1)State Name [000]000Unlocked Yes [001](3)001Locked No [011]011Locked-down No [100]100Unlocked Yes [101](3)101LockedNo [110](4)110Lock-down Disable Yes [111]111Lock-down DisableNoTable 8.Block Locking State Transitions upon Command Write (4)Current StateResult after Lock Command Written (Next State)State WP#DQ 1DQ 0Set Lock (1)Clear Lock (1)Set Lock-down (1)[000]000[001]No Change [011](2)[001]001No Change (3)[000][011][011]011No Change No Change No Change [100]100[101]No Change [111](2)[101]101No Change [100][111][110]110[111]No Change [111](2)[111]111No Change[110]No ChangeNOTES:1. "WP#=0→1" means that WP# is driven to V IH and "WP#=1→0" means that WP# is driven to V IL .2. State transition from the current state [011] to the next state depends on the previous state.3. When WP# is driven to V IL in [110] state, the state changes to [011] and the blocks are automatically locked.4. In this state transitions table, assumes that lock configuration commands are not written in previous, current and next state.Table 9.Block Locking State Transitions upon WP# Transition (4)Previous StateCurrent StateResult after WP# Transition (Next State)State WP#DQ 1DQ 0WP#=0→1(1)WP#=1→0(1)-[000]000[100]--[001]001[101]-[110](2)[011]011[110]-Other than [110](2)[111]--[100]100-[000]-[101]101-[001]-[110]110-[011](3)-[111]111-[011]Table 10.Status Register DefinitionR R R R R R R R 15141312111098 WSMS BESS BEFCES PBPOPS VPPS PBPSS DPS R 76543210SR.15 - SR.8 = RESERVED FOR FUTUREENHANCEMENTS (R)SR.7 = WRITE STATE MACHINE STATUS (WSMS)1 = Ready0 = BusySR.6 = BLOCK ERASE SUSPEND STATUS (BESS)1 = Block Erase Suspended0 = Block Erase in Progress/CompletedSR.5 = BLOCK ERASE AND FULL CHIP ERASESTATUS (BEFCES)1 = Error in Block Erase or Full Chip Erase0 = Successful Block Erase or Full Chip EraseSR.4 = (PAGE BUFFER) PROGRAM ANDOTP PROGRAM STATUS (PBPOPS)1 = Error in (Page Buffer) Program or OTP Program0 = Successful (Page Buffer) Program or OTP ProgramSR.3 = V PP STATUS (VPPS)1 = V PP LOW Detect, Operation Abort0 = V PP OKSR.2 = (PAGE BUFFER) PROGRAM SUSPENDSTATUS (PBPSS)1 = (Page Buffer) Program Suspended0 = (Page Buffer) Program in Progress/CompletedSR.1 = DEVICE PROTECT STATUS (DPS)1 = Erase or Program Attempted on aLocked Block, Operation Abort0 = UnlockedSR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)NOTES:Status Register indicates the status of the partition, not WSM (Write State Machine). Even if the SR.7 is "1", the WSM may be occupied by the other partition when the device is set to 2, 3 or 4 partitions configuration.Check SR.7 to determine block erase, full chip erase, (page buffer) program or OTP program completion. SR.6 - SR.1 are invalid while SR.7="0".If both SR.5 and SR.4 are "1"s after a block erase, full chip erase, (page buffer) program, set/clear block lock bit, set block lock-down bit, set partition configuration register attempt, an improper command sequence was entered.SR.3 does not provide a continuous indication of V PP level. The WSM interrogates and indicates the V PP level only after Block Erase, Full Chip Erase, (Page Buffer) Program or OTP Program command sequences. SR.3 is not guaranteed to report accurate feedback when V PP≠V PPH1, V PPH2 or V PPLK. SR.1 does not provide a continuous indication of block lock bit. The WSM interrogates the block lock bit only after Block E rase, Full Chip E rase, (Page Buffer) Program or OTP Program command sequences. It informs the system, depending on the attempted operation, if the block lock bit is set. Reading the block lock configuration codes after writing the Read Identifier Codes/OTP command indicates block lock bit status.SR.15 - SR.8 and SR.0 are reserved for future use and should be masked out when polling the status register.Table 11.Extended Status Register DefinitionR R R R R R R R 15141312111098 SMS R R R R R R R 76543210XSR.15-8 = RESERVED FOR FUTUREENHANCEMENTS (R)XSR.7 = STATE MACHINE STATUS (SMS)1 = Page Buffer Program available0 = Page Buffer Program not availableXSR.6-0 = RESERVED FOR FUTURE ENHANCEMENTS (R)NOTES:After issue a Page Buffer Program command (E8H), XSR.7="1" indicates that the entered command is accepted. If XSR.7 is "0", the command is not accepted and a next Page Buffer Program command (E8H) should be issued again to check if page buffer is available or not.XSR.15-8 and XSR.6-0 are reserved for future use and should be masked out when polling the extended status register.1 Electrical Specifications 1.1 Absolute Maximum Ratings *Operating TemperatureDuring Read, Erase and Program......0°C to +70°C (1)Storage TemperatureDuring under Bias...............................-10°C to +80°C During non Bias................................-65°C to +125°C V oltage On Any Pin(except V CC and V PP )..............-0.5V to V CC +0.5V (2)V CC and V CCQ Supply V oltage..........-0.2V to +3.9V (2)V PP Supply V oltage....................-0.2V to +12.6V (2, 3, 4)Output Short Circuit Current...........................100mA (5)*WARNING: Stressing the device beyond the "AbsoluteMaximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.NOTES:1. Operating temperature is for commercial temperature product defined by this specification.2. All specified voltages are with respect to GND.Minimum DC voltage is -0.5V on input/output pins and -0.2V on V CC and V PP pins. During transitions,this level may undershoot to -2.0V for periods <20ns.Maximum DC voltage on input/output pins is V CC +0.5V which, during transitions, may overshoot to V CC +2.0V for periods <20ns.3. Maximum DC voltage on V PP may overshoot to +13.0V for periods <20ns.4. V PP erase/program voltage is normally 2.7V-3.6V.Applying 11.7V-12.3V to V PP during erase/program can be done for a maximum of 1,000 cycles on the main blocks and 1,000 cycles on the parameter blocks.V PP may be connected to 11.7V-12.3V for a total of 80hours maximum.5. Output shorted for no more than one second. No more than one output shorted at a time.1.2 Operating ConditionsNOTES:1. See DC Characteristics tables for voltage range-specific specification.2. Applying V PP =11.7V-12.3V during a erase or program can be done for a maximum of 1,000 cycles on the main blocks and 1,000 cycles on the parameter blocks. A permanent connection to V PP =11.7V-12.3V is not allowed and can cause damage to the device.ParameterSymbol Min.Typ.Max.Unit NotesOperating Temperature T A 0+25+70°C V CC Supply Voltage V CC 2.7 3.0 3.6V 1I/O Supply VoltageV CCQ 2.7 3.0 3.6V 1V PP V oltage when Used as a Logic Control V PPH1 1.65 3.0 3.6V 1V PP Supply V oltageV PPH211.71212.3V 1, 2Main Block Erase Cycling: V PP =V PPH1100,000Cycles Parameter Block Erase Cycling: V PP =V PPH1100,000Cycles Main Block Erase Cycling: V PP =V PPH2, 80 hrs.1,000Cycles Parameter Block Erase Cycling: V PP =V PPH2, 80 hrs.1,000Cycles Maximum V PP hours at V PPH280Hours1.2.3 DC CharacteristicsV CC=2.7V-3.6VSymbol Parameter Notes Min.Typ.Max.Unit Test Conditions I LI Input Load Current1-1.0+1.0µA V CC=V CC Max.,V CCQ=V CCQ Max.,V IN/V OUT=V CCQ orGND I LO Output Leakage Current1-1.0+1.0µAI CCS V CC Standby Current1420µA V CC=V CC Max.,CE#=RST#=V CCQ±0.2V, WP#=V CCQ or GNDI CCAS V CC Automatic Power Savings Current1,4420µA V CC=V CC Max.,CE#=GND±0.2V, WP#=V CCQ or GNDI CCD V CC Reset Power-Down Current1420µA RST#=GND±0.2VI CCR Average V CC ReadCurrentNormal Mode1,71525mA V CC=V CC Max.,CE#=V IL,OE#=V IH,f=5MHz Average V CC ReadCurrentPage Mode8 Word Read1,7510mAI CCW V CC (Page Buffer) Program Current 1,5,72060mA V PP=V PPH1 1,5,71020mA V PP=V PPH2I CCE V CC Block Erase, Full ChipErase Current1,5,71030mA V PP=V PPH11,5,7410mA V PP=V PPH2I CCWS I CCES V CC (Page Buffer) Program orBlock Erase Suspend Current1,2,710200µA CE#=V IHI PPSI PPRV PP Standby or Read Current1,6,725µA V PP≤V CCI PPW V PP (Page Buffer) Program Current 1,5,6,725µA V PP=V PPH1 1,5,6,71030mA V PP=V PPH2I PPE V PP Block Erase, Full ChipErase Current1,5,6,725µA V PP=V PPH11,5,6,7515mA V PP=V PPH2I PPWS V PP (Page Buffer) ProgramSuspend Current1,6,725µA V PP=V PPH11,6,710200µA V PP=V PPH2I PPES V PP Block Erase Suspend Current 1,6,725µA V PP=V PPH1 1,6,710200µA V PP=V PPH2NOTES:1. All currents are in RMS unless otherwise noted. Typical values are the reference values at V CC =3.0V and T A =+25°C unless V CC is specified.2. I CCWS and I CCES are specified with the device de-selected. If read or (page buffer) program is executed while in block erase suspend mode, the device ’s current draw is the sum of I CCES and I CCR or I CCW . If read is executed while in (page buffer) program suspend mode, the device ’s current draw is the sum of I CCWS and I CCR .3. Block erase, full chip erase, (page buffer) program and OTP program are inhibited when V PP ≤V PPLK , and not guaranteed in the range between V PPLK (max.) and V PPH1(min.), between V PPH1(max.) and V PPH2(min.) and above V PPH2(max.).4. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle completion. Standard address access timings (t A VQV ) provide new data when addresses are changed.5. Sampled, not 100% tested.6. V PP is not used for power supply pin. With V PP ≤V PPLK , block erase, full chip erase, (page buffer) program and OTP program cannot be executed and should not be attempted.Applying 12V±0.3V to V PP provides fast erasing or fast programming mode. In this mode, V PP is power supply pin and supplies the memory cell current for block erasing and (page buffer) programming. Use similar power supply trace widths and layout considerations given to the V CC power bus.Applying 12V±0.3V to V PP during erase/program can only be done for a maximum of 1,000 cycles on each block. V PP may be connected to 12V±0.3V for a total of 80 hours maximum.7. The operating current in dual work is the sum of the operating current (read, erase, program) in each plane.V IL Input Low V oltage 5-0.40.4V V IH Input High V oltage52.4V CCQ + 0.4VV OLOutput Low Voltage 50.2VV CC =V CC Min.,V CCQ =V CCQ Min.,I OL =100µA V OH Output High Voltage 5V CCQ -0.2VV CC =V CC Min.,V CCQ =V CCQ Min.,I OH =-100µAV PPLK V PP Lockout during Normal Operations3,5,60.4VV PPH1V PP during Block E rase, Full Chip E rase, (Page Buffer) Program or OTP Program Operations6 1.65 3.0 3.6VV PPH2V PP during Block E rase, Full Chip E rase, (Page Buffer) Program or OTP Program Operations 611.71212.3V V LKOV CC Lockout V oltage1.5VV CC =2.7V-3.6VSymbol ParameterNotes Min.Typ.Max.Unit Test ConditionsDC Characteristics (Continued)。

GS841E18AT中文资料

GS841E18AT/B-180/166/150/130/100256K x 18 Sync Cache Tag 180 MHz–100 MHz3.3 V V DD3.3 V and 2.5 V I/OTQFP, BGACommercial Temp Industrial Temp Features• 3.3 V +10%/–5% core power supply, 2.5 V or 3.3 V I/O supply• Dual Cycle Deselect (DCD)• Intergrated data comparator for Tag RAM application • FT mode pin for flow through or pipeline operation• LBO pin for Linear or Interleave (Pentium TM and X86) Burst mode• Synchronous address, data I/O, and control inputs • Synchronous Data Enable (DE)• Asynchronous Output Enable (OE)• Asynchronous Match Output Enable (MOE)• Byte Write (BWE) and Global Write (GW) operation • Three chip enable signals for easy depth expansion • Internal self-timed write cycle• JTAG Test mode conforms to IEEE standard 1149.1• JEDEC-standard 100-lead TQFP package and 119-BGA • Pb-Free 100-lead TQFP package availableFunctional DescriptionThe GS841E18A is a 256K x 18 high performance synchronous DCD SRAM with integrated Tag RAM comparator. A 2-bit burst counter is included to provide burst interface with Pentium TM and other high performance CPUs. It is designed to be used as a Cache Tag SRAM, as well as data SRAM. Addresses, data IOs, match output, chip enables (CE1, CE2, CE3), address control inputs (ADSP, ADSC, ADV), and write control inputs (BW1, BW2, BWE, GW, DE) are synchronous and are controlled by a positive-edge-triggered clock (CLK).Output Enable (OE), Match Output Enable, and power down control (ZZ) are asynchronous. Burst can be initiated with either ADSP or ADSC inputs. Subsequent burst addresses are generated internally and are controlled by ADV. The burst sequence is either interleave order (Pentium TM or x86) or linear order, and is controlled by LBO.Output registers and the Match output register are provided andcontrolled by the FT mode pin (Pin 14). Through use of the FT mode pin, I/O registers can be programmed to perform pipeline or flow through operation. Flow Through mode reduces latency.Byte write operation is performed by using Byte Write Enable (BWE) input combined with two individual byte write signals BW1-2. In addition, Global Write (GW) is available for writing all bytes at one time.Compare cycles begin as a read cycle with output disabled so that compare data can be loaded into the data input register. Thecomparator compares the read data with the registered input data and a match signal is generated. The match output can be either in Pipeline or Flow Through modes controlled by the FT signal.Low power (Standby mode) is attained through the assertion of the ZZ signal, or by stopping the clock (CLK). Memory data is retained during Standby mode.JTAG boundary scan interface is provided using IEEE standard 1149.1 protocol. Four pins—Test Data In (TDI), Test Data Out(TDO), Test Clock (TCK) and Test Mode Select (TMS)—are used to perform JTAG function.The GS841E18A operates on a 3.3 V power supply and all inputs/outputs are 3.3 V- or 2.5 V-LVTTL-compatible. Separate output (V DDQ ) pins are used to allow both 3.3 V or 2.5 V IO interface.Dual Cycle Deselect (DCD)The GS841E18A is a DCD pipelines synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. DCD SRAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of the clock.Parameter Synopsis–180-166-150-133-100Pipeline 3-1-1-1t cycle t KQ I DD 5.5 ns 3.2 ns 335 mA 6.0 ns 3.5 ns 310 mA 6.6 ns 3.8 ns 275 mA 7.5 ns 4.0 ns 250 mA 10 ns 4.5 ns 190 mA Flow Through 2-1-1-1t KQ t cycle I DD8 ns 9.1 ns 210 mA8.5 ns 10 ns 190 mA10 ns 10 ns 190 mA11 ns 15 ns 140 mA12 ns 15 ns 140 mAGS841E18AT/B-180/166/150/130/100Pin Configuration (Package T)807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS D DQ V SS V DDQ DQ DQ V DD NC V SS DQ DQ V DDQ V SS DQ DQ DQ P V SS V DDQ V DDQ V SS DQ DQ V SS VDDQ DQ DQ V SS NC V DD ZZ DQ DQ V DDQ V SS DQ DQ V SS V DDQL B O A A A A A 1A 0T M S T D I V S SV D DT D O T C K A A A A A AA A C E 1C E 2 N C N C B W 2B W 1C E 3C L K G W B W E VD DV S SO E A D S C A D S P A D V A AA 256K x 18Top View DQ P A NC NC NC NC NC DE MATCHMOENC NC NC NC NC NC NCNC NC 100999897969594939291908988878685848382813132333435363738394041424344454647484950FTGS841E18AT/B-180/166/150/130/100 GS841E18A PadOut—119-Bump BGA—Top View (Package B)1234567A V DDQ A A ADSP A A V DDQB NC E2A ADSC A E3NCC NC A A V DD A A NCD DQ B NC V SS NC V SS DQ P NCE NC DQ B V SS E1V SS NC DQ AF V DDQ NC V SSG V SS DQ A V DDQG NC D Q B B B ADV NC NC DQ AH DQ B N C V SS GW V SS DQ A NCJ V DDQ V DD NC V DD NC V DD V DDQK NC DQ B V SS CK V SS NC DQ AL DQ B NC NC NC B A DQ A NCM V DDQ DQ B V SS BW V SS MATCH V DDQN DQ B NC V SS A1V SS DQ A DEP NC DQ P V SS A0V SS MOE DQ AR NC A LBO V DD FT A NCT NC A A NC A A ZZU V DDQ TMS TDI TCK TDO NC V DDQGS841E18AT/B-180/166/150/130/100TQFP Pin DescriptionSymbol DescriptionAn Address Input Signals—Inputs are registered and must meet setup and hold times, as specified onpage 11.CLK Clock Input SignalBWE Byte Write Enable Signal—The byte write enable signal needs to be combined with one of the fourbyte write signals for a write operation to occur.BW1Byte Write signal for data outputs 1 thru 8BW2Byte Write signal for data outputs 9 thru 16GW Global Write EnableCE1,CE2, CE3Chip EnablesOE Output EnableADV Burst address advanceADSP, ADSC Address status signalsDQ Data Input and Output pinsDQP Parity Input and Output pinsMATCH Match OutputMOE Match Output EnableDE Data Enable—Data input registers are updated only when DE is active.ZZ Power down control—Application of ZZ will result in a low standby power consumption.FT Flow Through or Pipeline modeLBO Linear Order Burst modeTMS Test Mode SelectTDI Test Data InTDO Test Data OutTCK Test ClockV DD 3.3 V power supplyV SS GroundV DDQ 2.5 V/3.3 V output power supplyNC No ConnectGS841E18AT/B-180/166/150/130/100PBGA Pin DescriptionSymbol DescriptionAn Address Input Signals—Inputs are registered and must meet setup and hold times, as specified onpage 11.CLK Clock Input SignalBWE Byte Write Enable Signal—The byte write enable signal needs to be combined with one of the fourbyte write signals for a write operation to occur.BW1Byte Write signal for data outputs 1 thru 8BW2Byte Write signal for data outputs 9 thru 16GW Global Write EnableCE1,CE2, CE3Chip EnablesOE Output EnableADV Burst address advanceADSP, ADSC Address status signalsDQ Data Input and Output pinsDQP Parity Input and Output pinsMATCH Match OutputMOE Match Output EnableDE Data Enable—Data input registers are updated only when DE is active.ZZ Power down control—Application of ZZ will result in a low standby power consumption.FT Flow Through or Pipeline modeLBO Linear Order Burst modeTMS Test Mode SelectTDI Test Data InTDO Test Data OutTCK Test ClockV DD 3.3 V power supplyV SS GroundV DDQ 2.5 V/3.3 V output power supplyNC No ConnectGS841E18AT/B-180/166/150/130/100Functional Block DiagramA1A0A0A1D0D1Q1Q0B INARY C OUNTERLoadD QR EGISTE RD QRegister D QRegister D QRegister D QRegister D QRegister DQRegisterDQRegisterA0-17LBO ADV CLK ADSC ADSPGW BWE BW1BW2CE1CE2CE3FTDQ1-16OE ZZPowerdown Control256K X 18Memory Array18181818218AQDDQP1-2DEDQRegisterMatchTAP ControllerInstruction Reg.ID Reg.Bypass Reg Boundary Scan Registers 54TCKTMS TDIA, DQ, ControlTDOMOE always (Ø)GS841E18AT/B-180/166/150/130/100Mode Pin FunctionLBOFunctionL Linear Burst H or NCInterleaved BurstFTFunctionL Flow Through H or NCPipelinePower Down ControlNote:There are pull up devices on LBO and FT pins and pull down device on ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.ZZFunctionL or NC Active HStandby, IDD = ISBLinear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110Interleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100Note: H = logic high, L = logic low, NC = no connectByte Write FunctionFunctionGWBWEBW1BW2Read H H X X Read H L H H Write all bytes L X X X Write all bytes H L L L Write byte 1H L L H Write byte 2HLHLGS841E18AT/B-180/166/150/130/100Notes:1.X means “don’t care,” H means “logic high,” L means “logic low.”2.Write is the logic function of GW, BWE, BW1, BW2. See Byte Write Function table for detail.3.All inputs, except OE, must meet setup and hold on rising edge of CLK.4.Suspending busrt generates a wait cycle.5.ADSP LOW along with SRAM being selected always initiates a Read cycle at the L-H edge of the clock (CLK).6.A Write cycle can only be performed by setting Write low for the clock L-H edge of the subsequent wait cycle. Refer to page 12 for the Write timing diagram.Synchronous Truth TableOperationAddress UsedCE1CE2CE3ADSP ADSC ADV Write OE CLK DQ Deselect Cycle, Power Down none H X X X L X X X L-H High-Z Deselect Cycle, Power Down none L L X L X X X X L-H High-Z Deselect Cycle, Power Down none L X H L X X X X L-H High-Z Deselect Cycle, Power Down none L L X H L X X X L-H High-Z Deselect Cycle, Power Down none L X H H L X X X L-H High-Z Read Cycle, Begin Burst external L H L L X X X L L-H Q Read Cycle, Begin Burst external L H L L X X X H L-H High-Z Read Cycle, Begin Burst external L H L H L X H L L-H Q Read Cycle, Begin Burst external L H L H L X H H L-H High-Z Write Cycle, Begin Burst external L H L H L X L X L-H D Read Cycle, Continue Burst next X X X H H L H L L-H Q Read Cycle, Continue Burst next X X X H H L H H L-H High-Z Read Cycle, Continue Burst next H X X X H L H L L-H Q Read Cycle, Continue Burst next H X X X H L H H L-H High-Z Write Cycle, Continue Burst next X X X H H L L X L-H D Write Cycle, Continue Burst next H X X X H L L X L-H D Read Cycle, Suspend Burst current X X X H H H H L L-H Q Read Cycle, Suspend Burst current X X X H H H H H L-H High-Z Read Cycle, Suspend Burst current H X X X H H H L L-H Q Read Cycle, Suspend Burst current H X X X H H H H L-H High-Z Write Cycle, Suspend Burst current X X X H H H L X L-H D Write Cycle, Suspend BurstcurrentHXXXHHLXL-HDGS841E18AT/B-180/166/150/130/100Notes:1.X means “don’t care,” H means “logic high,” L means “logic low.”2.Write is the logic function of GW, BWE, BW1, BW2. See Byte Write Function table for detail.3.CE is defined as CE1=L, CE2=H and CE3=L4.All signals are synchronous and are sampled by CLK except OE and MOE. OE and MOE are asynchronous and drive the bus immediately.)Note:Permanent damage to the device may occur if the Absolute Maximun Ratings are exceeded. Functional operation should be restricted to the recommended operation conditions. Exposure to higher than recommended voltages, for an extended period of time, could effect the performance and reliability of this component.Truth Table For Read/Write/Compare/Fill Write OperationCEWriteDEMOEOEMatchDQRead L H X X L —Q Write L L L X H —D Compare L H L L H Data Out D Fill Write L L H X X —X Match Deselect H X X L X High High Z DeselectHXXHXHigh ZHigh ZAbsolute Maximum Ratings (Voltage reference to V SS = 0 V)SymbolDescriptionCommericalUnitV DD Supply Voltage –0.5 to 4.6V V DDQ Output Supply Voltage –0.5 to V DD V V CLK CLK Input Voltage –0.5 to 6V V in Input Voltage –0.5 to V DD + 0.5 (≤ 4.6 V max. )V V out Output Voltage –0.5 to V DD + 0.5 (≤ 4.6 V max. )V I out Output Current per I/O +/–20mA P D Power Dissipation 1.5WT OPR Operating Temperature 0 to 70o C T STGStorage Temperature–55 to 125oCGS841E18AT/B-180/166/150/130/100Notes:1.Junction temperature is a function of SRAM power dissapation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance.2.SCMI G-38-87.3.Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1.Package Thermal CharacteristicsRatingLayer BoardSymbolTQFP maxPBGA maxUnitNotesJunction to Ambient (at 200 lfm)single R ΘJA 3228°C/W 1,2Junction to Ambient (at 200 lfm)four R ΘJA 2018°C/W 1,2Junction to Case (TOP)—R ΘJC74°C/W3Notes: 1.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.3.Output load 2 for t LZ , t HZ , t OLZ and t OHZ .4.Device is deselected as defined by the Truth Table.AC Test Conditions(VDD = 3.135 V–3.6 V, Ta = 0–70°C)ParameterConditionsInput high level V IH = 2.3 V Input low level V IL = 0.2 V Input slew rate TR = 1 V/ns Input reference level 1.25 V Output reference level1.25 V Output loadFig. 1& 2DQVT = 1.25 V50W 30pF 1DQ2.5 V F IG . 1Output load 1Output load 2F IG . 2225W 225W5pF 1GS841E18AT/B-180/166/150/130/100DC Characteristics and Supply Currents(Voltage reference to V SS = 0 V)(VDD = 3.135 V–3.6 V, Ta = 0–70°C for Commercial Temperature Offering)Parameter Symbol Test Conditions Min MaxInput Leakage Current(except ZZ, FT, LBO pins)I IL V IN = 0 to V DD–1 uA 1 uAZZ Input Current Iin ZZ V DD ≥V IN ≥V IH0 V≤ V IN ≤ V IH–1 uA–1 uA1 uA300 uAMode Input Current (FT & LBO pins)Iin MV DD ≥V IN ≥V IL0 V≤ V IN ≤ V IL–30 0uA–1 uA1 uA1 uAOutput Leakage Current I ol Output Disable,V OUT = 0 to V DD–1 uA 1 uAOutput High Voltage V OH I OH = –4 mA, V DDQ = 2.375 V 1.7 VOutput High Voltage V OH I OH = –4 mA, V DDQ = 3.135 V 2.4 VOutput Low Voltage V OL I OL = +4 mA0.4 VGS841E18AT/B-180/166/150/130/100Operating CurrentsParameter Test Conditions Symbol-180-166-150-133-100Unit 0to70°C–40to85°Cto70°C–40to+85°Cto70°C–40to+85°Cto70°C–40to+85°Cto70°C–40to+85°CO perating Current Device Selected;All other inputs≥ V IH O r ≤ V ILOutput openI DDPipeline335345310320275285250260190200mAI DDFlowThrough210220190200190200140150140150mAStandby Current ZZ≥ V DD – 0.2 VI SBPipeline20303040304030403040mAI SBFlowThrough20303040304030403040mADeselect Supply Current Device Deselected;All other inputs≥ V IH OR≤ V ILI DDPipeline55651101201051151001108090mAI DDFlowThrough40508090809065756575mAGS841E18AT/B-180/166/150/130/100Notes:1.These parameters are sampled and are not 100% tested2.ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and holdtimes as specified above.AC Electrical CharacteristicsParameterSymbol-180-166-150-133-100UnitMinMaxMinMaxMinMaxMinMaxMinMaxPipelineClock Cycle Time tKC 5.5— 6.0— 6.7—7.5—10—ns Clock to Output Valid tKQ — 3.2— 3.5— 3.8—4— 4.5ns Clock to Output InvalidtKQX 1.5— 1.5— 1.5— 1.5— 1.5—ns Clock to Output in Low-Z tLZ 1 1.5— 1.5— 1.5— 1.5— 1.5—ns Clock to Match Valid tKM — 3.2— 3.5— 3.8—4— 4.5ns Clock to Match Invalid tKMX 1.5— 1.5— 1.5— 1.5— 1.5—ns Clock to Match in Low-Z tMLZ 1 1.5— 1.5— 1.5— 1.5— 1.5—ns Flow ThroughClock Cycle Time tKC 9.1—10.0—10.0—15.0—15.0—ns Clock to Output Valid tKQ —8.0—8.5—10.0—11.0—12.0ns Clock to Output InvalidtKQX 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock to Output in Low-Z tLZ 1 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock to Match Valid tKM —8.5—8.5—10.0—11.0—12.0ns Clock to Match Invalid tKMX 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock to Match in Low-Z tMLZ 1 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock HIGH Time tKH 1.3— 1.3— 1.5— 1.7—2—ns Clock LOW Time tKL 1.5— 1.5— 1.7—1.9—2.2—ns Clock to Output in High-Z tHZ 1 1.53.2 1.5 3.5 1.5 3.8 1.54 1.55ns OE to Output Valid tOE — 3.2— 3.5— 3.8—4—5ns OE to output in Low-Z tOLZ 10—0—0—0—0—ns OE to output in High-Z tOHZ 1— 3.2— 3.5— 3.8—4—5ns MOE to Match Valid tMOE — 3.2— 3.5— 3.8—4—5ns MOE to Match in Low-Z tMOLZ 10—0—0—0—0—ns MOE to Match in High-ZtMOHZ 1— 3.2— 3.5— 3.8—4—5ns Setup time tS 1.5— 1.5— 1.5— 2.0— 2.0—ns Hold time tH 0.5—0.5—0.5—0.5—0.5—ns ZZ setup time tZZS 25—5—5—5—5—ns ZZ hold time tZZH 21—1—1—1—1—ns ZZ recoverytZZR20—20—20—20—20—nsGS841E18AT/B-180/166/150/130/100Pipeline Mode TimingBegin Read A Cont Deselect Deselect Write BRead C Read C+1Read C+2Read C+3Cont Deselect DeselecttHZtKQXtKQtLZtHtStOHZtOEtHtStHtStHtStH tStHtStStHtStHtStHtStKCtKL tKHQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)ABCHi-ZDeselected with E1E2 and E3 only sampled with ADSCADSC initiated readCK ADSPADSCADVAo–AnGWBWBa–BdE1E2E3GDQa–DQdGS841E18AT/B-180/166/150/130/100Flow Through Mode TimingBegin Read A ContDeselect Write B Read C Read C+1Read C+2Read C+3Read C DeselecttHZtKQX tLZtH tStOHZtOE tKQtHtS tHtS tHtStH tStHtS tHtStHtS tHtS tH tStH tS tHtS tKCtKL tKHABCQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)Q(C)E2 and E3 only sampled with ADSP and ADSCE1 masks ADSPADSC initiated readDeselected with E1E1 masks ADSPFixed HighCK ADSPADSCADVAo–AnGWBWBa–BdE1E2E3GDQa–DQdGS841E18AT/B-180/166/150/130/100Pipeline Compare Fill Write CycleHit Miss Fill WriteA BBA A tKMtKMtKMXtKM tMOE tMLZtH tStH tStH tStH tStH tSKAddressDQCEW GDE MOEMatchGS841E18AT/B-180/166/150/130/100Flow Through Compare Fill Write CycleHit Miss Fill WriteA BBA A tKMtKM tKMXtKM tMOE tMLZtH tStH tStH tStH tStH tSKAddressDQCEW GDE MOEMatchGS841E18AT/B-180/166/150/130/100TQFP Package Drawing (Package T)D1D E1EPin 1be cLL1A2A1YθNotes:1.All dimensions are in millimeters (mm).2.Package width and length do not include mold protrusion.SymbolDescriptionMin.Nom.MaxA1Standoff 0.050.100.15A2Body Thickness 1.35 1.40 1.45b Lead Width 0.200.300.40c Lead Thickness 0.09—0.20D Terminal Dimension 21.922.022.1D1Package Body 19.920.020.1E Terminal Dimension 15.916.016.1E1Package Body 13.914.014.1e Lead Pitch —0.65—L Foot Length 0.450.600.75L1Lead Length —1.00—Y Coplanarity 0.10θLead Angle0°—7°GS841E18AT/B-180/166/150/130/100Package Dimensions—119-Bump FPBGA (Package B, Variation 2)A B C D E F G H J K L M N P R T U1 2 3 4 5 6 77 6 5 4 3 2 1A1 TOP VIEWA1 BOTTOM VIEW 1.277.621.2720.3214±0.1022±0.10BA 0.20(4x)Ø0.10Ø0.30CC A B S S Ø0.60~0.90 (119x)CSEATING PLANE0.15C0.50~0.701.86.±0.130.70±0.050.15CA B C D E F G H J K L M N P R T U0.56±0.05S SGS841E18AT/B-180/166/150/130/100 Ordering InformationOrg Part Number1Type Package Speed 2(MHz/ns)T A3Status256K x 18GS841E18AT-180DCD Pipeline/Flow Through TQFP180/8C256K x 18GS841E18AT-166DCD Pipeline/Flow Through TQFP166/8.5C256K x 18GS841E18AT-150DCD Pipeline/Flow Through TQFP150/10C256K x 18GS841E18AT-133DCD Pipeline/Flow Through TQFP133/11C256K x 18GS841E18AT-100DCD Pipeline/Flow Through TQFP100/12C256K x 18GS841E18AT-180I DCD Pipeline/Flow Through TQFP180/8I256K x 18GS841E18AT-166I DCD Pipeline/Flow Through TQFP166/8.5I256K x 18GS841E18AT-150I DCD Pipeline/Flow Through TQFP150/10I256K x 18GS841E18AT-133I DCD Pipeline/Flow Through TQFP133/11I256K x 18GS841E18AT-100I DCD Pipeline/Flow Through TQFP100/12I256K x 18GS841E18AGT-180DCD Pipeline/Flow Through Pb-Free TQFP180/8C256K x 18GS841E18AGT-166DCD Pipeline/Flow Through Pb-Free TQFP166/8.5C256K x 18GS841E18AGT-150DCD Pipeline/Flow Through Pb-Free TQFP150/10C256K x 18GS841E18AGT-133DCD Pipeline/Flow Through Pb-Free TQFP133/11C256K x 18GS841E18AGT-100DCD Pipeline/Flow Through Pb-Free TQFP100/12C256K x 18GS841E18AGT-180I DCD Pipeline/Flow Through Pb-Free TQFP180/8I256K x 18GS841E18AGT-166I DCD Pipeline/Flow Through Pb-Free TQFP166/8.5I256K x 18GS841E18AGT-150I DCD Pipeline/Flow Through Pb-Free TQFP150/10I256K x 18GS841E18AGT-133I DCD Pipeline/Flow Through Pb-Free TQFP133/11I256K x 18GS841E18AGT-100I DCD Pipeline/Flow Through Pb-Free TQFP100/12I256K x 18GS841E18AB-180DCD Pipeline/Flow Through119 BGA (var. 2)180/8C256K x 18GS841E18AB-166DCD Pipeline/Flow Through119 BGA (var. 2)166/8.5C256K x 18GS841E18AB-150DCD Pipeline/Flow Through119 BGA (var. 2)150/10C256K x 18GS841E18AB-133DCD Pipeline/Flow Through119 BGA (var. 2)133/11C256K x 18GS841E18AB-100DCD Pipeline/Flow Through119 BGA (var. 2)100/12C256K x 18GS841E18AB-180I DCD Pipeline/Flow Through119 BGA (var. 2)180/8I256K x 18GS841E18AB-166I DCD Pipeline/Flow Through119 BGA (var. 2)166/8.5I256K x 18GS841E18AB-150I DCD Pipeline/Flow Through119 BGA (var. 2)150/10I256K x 18GS841E18AI-133I DCD Pipeline/Flow Through119 BGA (var. 2)133/11I256K x 18GS841E18AB-100I DCD Pipeline/Flow Through119 BGA (var. 2)100/12INotes:1.Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS841E18AT-166T.2.The speed column indicates the cycle frequency (Mhz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Eachdevice is Pipeline / Flow through mode selectable by the user.3.T A = C = Commercial Temperature Range. T A = I = Industrial Temperature Range.4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of whichare covered in this data sheet. See the GSI Technology web site for a complete listing of current offerings.GS841E18AT/B-180/166/150/130/100Specifications cited are subject to change without notice. For latest documentation see .Rev: 1.03 4/200521/21© 2001, GSI Technology 4Mb Synchronous Tag RAM Datasheet Revision History Rev. Code: Old;NewTypes of Changes Format or Content Page /Revisions;Reason GS841E18A_r1• Creation of new datasheet GS841E18A_r1;GS841E18A_r1_01Content • Moved TCK from U6 (incorrect placement) to U4 (correct placement) on BGA• Changed U6 to NCGS841E18A_r1_01; GS841E18A_r1_02Format/Content • Updated format• Added 180 MHz speed bin• Updated timing diagrams• Updated mechanical drawings• Added Pb-Free info for TQFPGS841E18A_r1_02;GS841E18A_r1_03Content• Added Pipeline Compare Fill Write Cycle and Flow ThroughCompare Fill Write Cycle timing diagrams 元器件交易网。

BL-420生物机能实验系统用户手册

BL-420生物机能实验系统用户手册在您使用BL-420生物机能实验系统进行正常实验之前，请您先认真阅读这本《用户手册》，它会循序渐进地帮助您完整地掌握整套BL-420生物机能实验系统的使用方法，特别是教会您熟练地使用为BL-420生物机能实验系统配套的软件——BL-420E+生物信号显示与处理软件来完成各种生物机能实验。

✍欢迎使用BL-420生物机能实验系统✍ BL-420生物机能实验系统软、硬件安装BL-420——仅供参考目录✍§1 欢迎使用BL-420生物机能实验系统 ......................... 错误！未指定书签。

✍§1.1BL-420系统概述...................................... 错误！未指定书签。

✍§1.2BL-420系统原理...................................... 错误！未指定书签。

✍§1.3BL-420系统特点...................................... 错误！未指定书签。

✍§3.5.6 区间测量数据结果的导出......................... 错误！未指定书签。

✍§4 BL-420E+软件菜单介绍 .................................... 错误！未指定书签。

✍§4.1文件菜单............................................. 错误！未指定书签。

✍§4.2设置菜单............................................. 错误！未指定书签。

✍§4.3输入信号菜单......................................... 错误！未指定书签。

BL-B2141P中文资料

45 30 35 30 35 30 35 45 30 35 30 35 45 35 45 30 35 30 35 45 35 90 45 30 35 30 45 90 45 30 35 30 45 30 35 45 30 30 35 45 30 35 45 45 30 35 45 35 30 30
80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 40 80 80 80 80 80 40 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80
Material/Emitted Color
Typ Max Typ.
T-1 Standard 1.0″ Lead 3φ
T-1 Standard 1.0″ Lead 3φ
T-1 1.0″ Lead 3φ
BL-B4541 BL-B2141 BL-B3141 BL-B2441 BL-B3441 BL-B2341 BL-BX1341 BL-B45V1 BL-B21V1 BL-B31V1 BL-B24V1 BL-B34V1 BL-B43V1 BL-BX13V1 BL-B45V1G BL-B21V1G BL-B31V1G BL-B24V1G BL-B34V1G BL-B43V1G BL-BX13V1G BL-B51V1H BL-B45V1H BL-B21V1H BL-B31V1H BL-B24V1H BL-B46V1H BL-B51V1J BL-B45V1J BL-B21V1J BL-B31V1J BL-B24V1J BL-B43V1M BL-B23V1M BL-B33V1M BL-B44V1M BL-B24V1M BL-B2141P BL-B3141P BL-B4541P BL-B2341P BL-B3341P BL-B4341P BL-B4541Q BL-B2141Q BL-B3141Q BL-B4141Q BL-B3341Q BL-B2341Q BL-BX1341Q

W78E58B中文手册

? ? ? ? :December 22, 2004
-1-
? ? : SC1
W78E58B
8.3 AC特性................................................................................................................ 25
8.3.1 时钟输入波形...................................................................................................................... 25 8.3.2 程序读取周期...................................................................................................................... 26 8.3.3 数据读取周期...................................................................................................................... 26 8.3.4 数据写周期.......................................................................................................................... 27 8.3.5 端口访问周期...................................................................................................................... 27

ICX418AKL资料

– 1 –E01503A29Sony reserves the right to change products and specifications without prior notice. This information does not convey any license byany implication or otherwise under any patents or other right. Application circuits shown, if any , are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.ICX418AKLDiagonal 8mm (Type 1/2) CCD Image Sensor for NTSC Color Video CamerasDescriptionThe ICX418AKL is an interline CCD solid-state image sensor suitable for NTSC color video cameras with a diagonal 8mm (T ype 1/2) system. Compared with the current product ICX038DNA, basic characteristics such as sensitivity, smear, dynamic range and S/N are improved drastically .This chip features a field period readout system and an electronic shutter with variable charge-storage time. This chip is compatible with the pins of the ICX038DNA and has the same drive conditions.Features••Low smear (–5.0dB compared with the ICX038DNA)••High S/N•High resolution and low dark current •Excellent antiblooming characteristics•Y •Continuous variable-speed shutter •Substrate bias:Adjustment free (external adjustment also possible with 6 to 14V)•Reset gate pulse:5Vp-p adjustment free (drive also possible with 0 to 9V)•Horizontal register:5V driveDevice Structure•Interline CCD image sensor •Optical size:Diagonal 8mm (T ype 1/2)•Number of effective pixels:768 (H) × 494 (V) approx. 380K pixels •T otal number of pixels:811 (H) × 508 (V) approx. 410K pixels •Chip size:7.40mm (H) × 5.95mm (V)•Unit cell size:8.4µm (H) × 9.8µm (V)•Optical black:Horizontal (H) direction:Front 3 pixels, rear 40 pixelsVertical (V) direction:Front 12 pixels, rear 2 pixels•Number of dummy bits:Horizontal 22Vertical 1 (even fields only)•Substrate material:Silicon– 2 –Block Diagram and Pin Configuration (T op View)N CV D S U BN CG N DG N DR DφR GN CH φ1H φ2V O U TV D DG N DV LV φ1G N DφS U BV φ2V φ3V φ4Pin Description Pin No.Pin No.1234567891011121314151617181920Symbol DescriptionV φ4V φ3V φ2φSUB GND V φ1V L GND V DD V OUTVertical register transfer clock Vertical register transfer clock Vertical register transfer clock Substrate clock GNDVertical register transfer clock Protective transistor bias GNDOutput circuit supply voltage Signal outputSymbol DescriptionNC V DSUB NC GND GND RD φRG NC H φ1H φ2Substrate bias circuit supply voltageGND GNDReset drain bias Reset gate clockHorizontal register transfer clock Horizontal register transfer clock– 3 –Absolute Maximum RatingsItemSubstrate clock φSUB – GND Supply voltage Clock input voltageVoltage difference between vertical clock input pins Voltage difference between horizontal clock input pins H φ1, H φ2 – V φ4φRG – GND φRG – φSUB V L – φSUBPins other than GND and φSUB – V L Storage temperature Operating temperature–0.3 to +50–0.3 to +18–55 to +10–15 to +20 to +10 to +15 to +17 –17 to +17–10 to +15 –55 to +10 –65 to +0.3 –0.3 to +30 –30 to +80 –10 to +60V V V V V V V V V V V V °C °C∗1Ratings Unit Remarks∗1+27V (Max.) when clock width < 10µs, clock duty factor < 0.1%.V DD , V RD , V DSUB , V OUT – GND V DD , V RD , V DSUB , V OUT – φSUB V φ1, V φ2, V φ3, V φ4 – GND V φ1, V φ2, V φ3, V φ4 – φSUB– 4 –DC CharacteristicsOutput circuit supply currentItemI DDSymbol 5.0Min.Unit RemarksT yp.Max.mA10.0Bias Conditions 1 [when used in substrate bias internal generation mode]Output circuit supply voltage Reset drain voltage Protective transistor biasSubstrate bias circuit supply voltage Substrate clock∗1V L setting is the V VL voltage of the vertical transfer clock waveform, or the same supply voltage as the V Lpower supply for the V driver should be used. (When CXD1267AN is used.)∗2Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD.ItemV DD V RD V L V DSUB φSUBSymbol 15.015.0∗115.0∗2Min.V VVUnit RemarksT yp.Max.14.5514.5514.5515.4515.4515.45V RD = V DDBias Conditions 2 [when used in substrate bias external adjustment mode]Output circuit supply voltage Reset drain voltage Protective transistor biasSubstrate bias circuit supply voltage Substrate voltage adjustment range Substrate voltage adjustment precision∗3V L setting is the V VL voltage of the vertical transfer clock waveform, or the same supply voltage as the V Lpower supply for the V driver should be used. (When CXD1267AN is used.)∗4Connect to GND or leave open.∗5The setting value of the substrate voltage (V SUB ) is indicated on the back of the image sensor by aspecial code. When adjusting the substrate voltage externally, adjust the substrate voltage to the indicated voltage. The adjustment precision is ±3%. However, this setting value has not significance when used in substrate bias internal generation mode.V SUB code — one character indicationCode and optimal setting correspond to each other as follows.ItemV DD V RD V L V DSUB V SUB ∆V SUBSymbol 15.015.0∗3∗4Min.V VV %Unit RemarksT yp.Max.14.5514.556.0–315.4515.4514.0+3V RD = V DD∗5∗5<Example> "L" → V SUB = 9.0VV SUB codeOptimal setting f 6.5G 7.0h 7.5J 8.0K 8.5L 9.0m9.5N10.0P10.5Q11.0S12.0U13.0V13.5W14.0R11.5T12.5E6.0– 5 –Clock Voltage Conditions∗1Input the reset gate clock without applying a DC bias. In addition, the reset gate clock can also be driven with the following specifications.Readout clock voltageVertical transfer clock voltageHorizontal transfer clock voltage Reset gate clock voltage ∗1Substrate clock voltage ItemV VTV VH1, V VH2V VH3, V VH4V VL1, V VL2,V VL3, V VL4V φV| V VH1 – V VH2 |V VH3 – V VH V VH4 – V VH V VHH V VHL V VLH V VLLV φH V HL V RGL V φRGV RGLH – V RGLLV φSUBSymbol 14.55–0.05–0.2–9.68.3–0.25–0.254.75–0.054.523.0Min.122222222222334445Waveform diagramV VH = (V VH1 + V VH2)/2V VL = (V VL3 + V VL4)/2V φV = V VH n – V VL n (n = 1 to 4)High-level coupling High-level coupling Low-level coupling Low-level coupling Low-level coupling RemarksReset gate clock voltageItemV RGL V φRGSymbol 44Waveform diagramRemarks15.000–9.09.05.00∗15.024.0T yp.15.450.050.05–8.59.650.10.10.10.50.50.50.55.250.055.50.825.0Max.UnitV V V VVp-p V V V V V V V Vp-pV VVp-pVVp-p–0.28.5Min.09.0T yp.0.29.5Max.Unit VVp-p– 6 –Horizontal transfer clock equivalent circuitVertical transfer clock equivalent circuit H φ1H φ212V φ4V φ3Clock Equivalent Circuit ConstantC φV1, C φV3C φV2, C φV4C φV12, C φV34C φV23, C φV41C φH1C φH2C φHH C φRG C φSUB R 1, R 3R 2, R 4R GNDSymbol Capacitance between vertical transfer clock and GNDCapacitance between vertical transfer clocksCapacitance between horizontal transfer clock and GND Capacitance between horizontal transfer clocks Capacitance between reset gate clock and GND Capacitance between substrate clock and GND Vertical transfer clock series resistor Vertical transfer clock ground resistorItemMin.270027008203301009147116809110068T yp.Max.pF pF pF pF pF pF pF pF pF ΩΩΩUnit Remarks– 7 –Drive Clock Waveform Conditions (1) Readout clock waveform(2) Vertical transfer clock waveformV VH = (V VH1 + V VH2)/2V VL = (V VL3 + V VL4)/2V φV = V VH n – V VL n (n = 1 to 4)100%90%10%0%0VVT– 8 –(3) Horizontal transfer clock waveformV RGLH is the maximum value and V RGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, V RGL is the average value of V RGLH and V RGLL .V RGL = (V RGLH + V RGLL )/2Assuming V RGH is the minimum value during the period twh, then:V φRG = V RGH – V RGLNegative overshoot level during the falling edge of RG is V RGLm .(5) Substrate clock waveform100%90%10%0%V SUBV HLV RGHV RGLV RGLHRG waveformV RGLL H φ1V RGLmV RGL + 0.5V– 9 –Clock Switching Characteristics∗1When vertical transfer clock driver CXD1267AN is used.∗2tf ≥ tr – 2ns.∗3The overlap period for twh and twl of horizontal transfer clocks H φ1 and H φ2 is two.Min.twoT yp.Max.1620Unit nsRemarks ItemHorizontal transfer clockSymbol H φ1, H φ2∗3Min.twh T yp.Max.Min.T yp.Max.Min.T yp.Max.Min.T yp.Max.twltrtf2.3111.52.5205.38131.8205.3851150.010.013190.50.515150.010.013250190.5Unit µs ns nsµs ns µsRemarksDuring readout ∗1∗2During drainchargeItem Readout clock Vertical transfer clockReset gate clock Substrate clockSymbol V TV φ1, V φ2,V φ3, V φ4H φH φ1H φ2φRG φSUBH o r i z o n t a l t r a n s f e r c l o c k0.5During imagingDuring parallel-serialconversionImage Sensor CharacteristicsItem Sensitivity Saturation signal SmearVideo signal shading Uniformity between video signal channels Dark signalDark signal shading Flicker YFlicker R-YFlicker B-YLine crawl RLine crawl GLine crawl BLine crawl WLag SymbolSYsatSmSHy∆Sr∆SbYdt∆YdtFyFcrFcbLcrLcgLcbLcwLagMin.10401000T yp.1300–115Max.–105202510102125533330.5UnitmVmVdB%%%%mVmV%%%%%%%%Measurementmethod123445567888999910RemarksT a = 60°CZone 0 and IZone 0 to II'T a = 60°CT a = 60°CZone Definition of Video Signal ShadingMeasurement SystemNote) Adjust the amplifier gain so that the gain between [∗A] and [∗Y], and between [∗A] and [∗C] equals 1.Chroma signal output(T a = 25°C)– 10 –– 11 –Image Sensor Characteristics Measurement MethodMeasurement conditions1)In the following measurements, the device drive conditions are at the typical values of the bias and clock voltage conditions. (when used with substrate bias external adjustment, set the substrate voltage to the value indicated on the device.)2)In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black level (OB) is used as the reference for the signal output, which is taken as the value of Y signal output or chroma signal output of the measurement system. Color coding of this image sensor & Composition of luminance (Y) and chroma (color difference) signalsAs shown in the left figure, fields are read out. The charge is mixed by pairs such as A1 and A2 in the A field. (pairs such as B in the B field)As a result, the sequence of charges output as signals from the horizontal shift register (Hreg) is, for line A1, (G + Cy),(Mg + Y e), (G + Cy), and (Mg + Y e).These signals are processed to form the Y signal and chroma (color difference) signal. The Y signal is formed by adding adjacent signals, and the chroma signal is formed by subtracting adjacent signals. In other words,the approximation:Y = {(G + Cy) + (Mg + Y e)} × 1/2= 1/2 {2B + 3G + 2R}is used for the Y signal, and the approximation:R – Y = {(Mg + Y e) – (G + Cy)}= {2R – G}is used for the chroma (color difference) signal. For line A2, the signals output from Hreg in sequence are (Mg + Cy), (G + Y e), (Mg + Cy), (G + Y e).The Y signal is formed from these signals as follows:Y = {(G + Y e) + (Mg + Cy)} × 1/2= 1/2 {2B + 3G + 2R}This is balanced since it is formed in the same way as for line A1.In a like manner, the chroma (color difference) signal is approximated as follows:– (B – Y)= {(G + Y e) – (Mg + Cy)}= – {2B – G}In other words, the chroma signal can be retrieved according to the sequence of lines from R – Y and – (B – Y)in alternation. This is also true for the B field.BA1A2HregColor Coding Diagram, measure the minimum value of the Y signal.[dB] (1/10V method conversion value)4.Video signal shadingSet to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so that the average value of the Y signal output is 200mV. Then measure the maximum (Ymax [mV]) and minimum (Ymin [mV]) values of the Y signal and substitute the values into the following formula.SHy = (Ymax – Ymin)/200 × 100 [%]5.Uniformity between video signal channelsSet to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal output is 200mV, and then measure the maximum (Crmax, Cbmax [mV]) and minimum (Crmin, Cbmin [mV]) values of the R – Y and B – Y channels of the chroma signal and substitute the values into the following formula.∆Sr = | (Crmax – Crmin)/200 | × 100 [%]∆Sb = | (Cbmax – Cbmin)/200 | × 100 [%]6.Dark signalMeasure the average value of the Y signal output (Ydt [mV]) with the device ambient temperature 60°C andthe device in the light-obstructed state, using the horizontal idle transfer level as a reference.– 12 –– 13 –7.Dark signal shadingAfter measuring 6, measure the maximum (Ydmax [mV]) and minimum (Ydmin [mV]) values of the dark signal output and substitute the values into the following formula.∆Ydt = Ydmax – Ydmin [mV]8.Flicker 1) FySet to standard imaging condition II . Adjust the luminous intensity so that the average value of the Y signal output is 200mV , and then measure the difference in the signal level between fields (∆Yf [mV]). Then substitute the value into the following formula.Fy = (∆Yf/200) × 100 [%]2) Fcr, FcbSet to standard imaging condition II . Adjust the luminous intensity so that the average value of the Y signal output is 200mV , insert an R or B filter, and then measure both the difference in the signal level between fields of the chroma signal (∆Cr, ∆Cb) as well as the average value of the chroma signal output (CAr, CAb).Substitute the values into the following formula.Fci = (∆Ci/CAi) × 100 [%] (i = r, b)9.Line crawlsSet to standard imaging condition II . Adjust the luminous intensity so that the average value of the Y signal output is 200mV , and then insert a white subject and R, G, and B filters and measure the difference between Y signal lines for the same field (∆Ylw, ∆Ylr, ∆Ylg, ∆Ylb [mV]). Substitute the values into the following formula.Lci = (∆Yli/200) × 100 [%] (i = w, r, g, b)10. LagAdjust the Y signal output value generated by strobe light to 200mV . After setting the strobe light so that it strobes with the following timing, measure the residual signal (Ylag). Substitute the value into the following g = (Ylag/200) ×100 [%]FLDV1Strobe lighttimingOutput– 14 –ICX418AKLD r i v e C i r c u i t 1 (s u b s t r a t e b i a s i n t e r n a l g e n e r a t i o n m o d e )–9V15VX S U B X V 2X V 1X S G 1X V 3X S G 2X V 4H φ2H φ1R G– 15 –ICX418AKLD r i v e C i r c u i t 2 (s u b s t r a t e b i a s e x t e r n a l a d j u s t m e n t m o d e )–9V15X S U B X V 2X V 1X S G 1X V 3X S G 2X V 4H φ2H φ1R G– 16 –Spectral Sensitivity Characteristics (Excludes lens characteristics and light source characteristics)Sensor Readout Clock Timing ChartUnit: µsOdd FieldEven FieldV1V2V3V4V1V2V3V41.00.80.60.40.20400450500CyY eMgG550Wave Length [nm]R e l a t i v e R e s p o n s e600650700– 17 –D r i v e T i m i n g C h a r t (V e r t i c a l S y n c )F L DV DB L KH DV 1V 2V 3V 4C CD O U T– 18 –D r i v e T i m i n g C h a r t (H o r i z o n t a l S y n c )H DB L KH 1H 2R GV 1V 2V 3V 4S U BNotes on Handling1)Static charge preventionCCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures.a)Either handle bare handed or use non-chargeable gloves, clothes or material.Also use conductive shoes.b)When handling directly use an earth band.c)Install a conductive mat on the floor or working table to prevent the generation of static electricity.d)Ionized air is recommended for discharge when handling CCD image sensor.e)For the shipment of mounted substrates, use boxes treated for the prevention of static charges.2)Solderinga)Make sure the package temperature does not exceed 80°C.b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30Wsoldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.c)T o dismount an image sensor, do not use a solder suction equipment. When using an electric desolderingtool, use a thermal controller of the zero cross On/Off type and connect it to ground.3)Dust and dirt protectionImage sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operation as required, and use them.a)Perform all assembly operations in a clean room (class 1000 or less).b)Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Shoulddirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.)c)Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass.d)Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool whenmoving to a room with great temperature differences.e)When a protective tape is applied before shipping, just before use remove the tape applied forelectrostatic protection. Do not reuse the tape.4) Installing (attaching)a)Remain within the following limits when applying a static load to the package. Do not apply any load morepackage may fracture, etc., depending on the flatness of the ceramic portions. Therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive.– 19 –c)The adhesive may cause the marking on the rear surface to disappear, especially in case the regulatedvoltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area, and indicated values should be transferred to other locations as a precaution.d)The upper and lower ceramic are joined by low melting point glass. Therefore, care should be taken not toperform the following actions as this may cause cracks.•Applying repeated bending stress to the outer leads.•Heating the outer leads for an extended period with a soldering iron.•Rapidly cooling or heating the package.•Applying any load or impact to a limited portion of the low melting point glass using tweezers or other sharp tools.•Prying at the upper or lower ceramic using the low melting point glass as a fulcrum.Note that the same cautions also apply when removing soldered products from boards.e)Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyano-acrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference)5) Othersa)Do not expose to strong light (sun rays) for long periods, color filters will be discolored. When highluminance objects are imaged with the exposure level control by electronic-iris, the luminance of the image-plane may become excessive and discolor of the color filter will possibly be accelerated. In such a case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the power-off mode should be properly arranged. For continuous using under cruel condition exceeding the normal using condition, consult our company.b)Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage orusage in such conditions.– 20 –– 21 –ICX418AKLP a c k a g e O u t l i n e U n i t : m mSony CorporationP A C K A G E S T R U C T U R EP A C K A G E M A T E R I A L L E A D T R E A T M E N T L E A D M A T E R I A L P A C K A G E M A S S C e r -D I PT I N P L A T I N G42 A L L O Y2.6gD R A W I N G N U M BE RA S -B 14-01(E )20p i n D I P (600m i l )c e .'” i sd V i s ± 1˚.1.41 ± 0.15m m .i s l e s s t h a n 60µm .e i n d e x i s 1.5.9.T h e n o t c h a n d t h e h o l e o n t h e b o t t o m m u s t n o t b e u s e d f o r r e f e r e n c e o f f i x i n g .。

蓝光技术资料

3.1. 系统结构框图 ......................................................................................................................................... 15 3.2. 系统主要部件性能指标 ......................................................................................................................... 15
目录
目录 .................................................................... 1 第一章 BL2000 串行控制系统功能介绍 ........................................... 6
1.1. 基本功能列表 ........................................................................................................................................... 6 1.2.特殊功能列表 ............................................................................................................................................. 8 1.3.安全保护功能列表 ................................................................................................................................... 12 1.4.可选功能列表 ........................................................................................................................................... 12

BL-R4130中文资料

ChipAbsolute MaximumRatingsElectro-optical Data (At 20mA) ViewingAngle 2θ 1/2(deg)DrawingNo. Vf (V)Iv (mcd)Package Part No.Material/EmittedColorPeak Wave Length λp (nm) Lens Appearance∆λ (nm) Pd (mw) If (mA) Peak (mA)Typ Max Typ.BL-R5131GaP/GaP/Bright Red 700 90 40 15 50 2.2 2.6 1.0 BL-R4531 GaAsP/GaP/Hi-Eff Red 635 Red Diffused 45 80 30 150 2.0 2.6 7.0 BL-R2131 GaP/GaP/Green 568 Green Diffused 30 80 30 150 2.2 2.6 7.0 BL-R3131 GaAsP/GaAs/Yellow 585 Yellow Diffused 35 80 30 150 2.1 2.6 6.0 BL-R4131GaAsP/GaP/Orange 635 Orange Diffused 45 80 30 150 2.0 2.6 7.0 2.0x4.0x 7.0mm 1.0″ LeadRectangular Flangeless BL-R9131 GaP/GaP/Pure Green 555 Green Diffused 25 80 30 150 2.2 2.6 1.0 120L-025BL-R5421DGaP/GaP/Bright Red 700 90 40 15 50 2.2 2.6 6.0 BL-R4621DGaAsP/GaP/Hi-Eff Red 635 Red Trans 45 80 30 150 2.0 2.6 12.0 BL-R2421D GaP/GaP/Green 568 Green Trans 30 80 30 150 2.2 2.6 12.0 BL-R3421D GaAsP/GaP/Yellow 585 Yellow Trans 35 80 30 150 2.1 2.6 10.0 BL-R4421DGaAsP/GaP/Orange 635 Orange Trans 25 80 30 150 2.0 2.6 12.0 1.3x4.0x4.0mm 1.0″ Lead RectangularBL-R9421D GaP/GaP/Pure Green 555 Green Trans 30 80 30 150 2.2 2.6 1.0 80L-026BL-R5121FGaP/GaP/Bright Red 700 90 40 15 50 2.2 2.6 0.6 BL-R4521F GaAsP/GaP/Hi-Eff Red 635 Red Diffused 45 80 30 150 2.0 2.6 3.0 BL-R2121FGaP/Gap/Green 568 Green Diffused 30 80 30 150 2.2 2.6 3.0 BL-R3121FGaAsP/GaP/ Yellow 585 Yellow Diffused 35 80 30 150 2.1 2.6 2.5 1.9x3.1x 4.0mm0.5″ LeadRectangular BL-R4121FGaAsP/GaP/Orange 635 Orange Diffused 25 80 30 150 2.0 2.6 3.0 120L-027BL-R5421GGaP/GaP/Bright Red 700 90 40 15 50 2.2 2.6 0.6 BL-R4621G GaAsP/GaP/Hi-Eff Red 635 Red Trans 45 80 30 150 2.0 2.6 3.5 BL-R2421G GaP/GaP/Green 568 Green Trans 30 80 30 150 2.2 2.6 3.5 1.2x3.4x4.0mm 0.5″ Lead RectangularBL-R3421GGaAsP/GaP/Yellow 585 Yellow Trans 35 80 30 150 2.1 2.6 3.0 60L-028BL-R5141HGaP/GaP/Bright Red 700 90 40 15 50 2.2 2.6 1.0 BL-R4541HGaAsP/GaP/Hi-Eff Red 635 Red Diffused 45 80 30 150 2.0 2.6 4.0 BL-R2141H GaP/GaP/Green 568 Green Diffused 30 80 30 150 2.2 2.6 4.0 BL-R3141H GaAsP/GaP/Yellow 585 Yellow Diffused 35 80 30 150 2.1 2.6 3.0 BL-R4141HGaAsP/GaP/Orange 635 Orange Diffused 45 80 30 150 2.0 2.6 4.0 1.7x4.0x6.9mm 1.0″ Lead RectangularBL-R9141H GaP/GaP/Pure Green 555 Green Diffused 25 80 30 150 2.2 2.6 0.5 140L-029BL-R5132GaP/GaP/Bright Red 700 90 40 15 50 2.2 2.6 6.0 BL-R4632GaAsP/GaP/Hi-Eff Red 635 Red Diffused 45 80 30 150 2.0 2.6 10.0 BL-R2132 GaP/GaP/Green 568 Green Diffused 30 80 30 150 2.2 2.6 10.0 BL-R3132 GaAsP/GaP/Yellow 585 Yellow Diffused 35 80 30 150 2.1 2.6 8.0 BL-R4132GaAsP/GaP/Orange 635 Orange Diffused 25 80 30 150 2.0 2.6 10.0 2.0x5.0x7.8mm 1.0″ Lead RectangularBL-R9132 GaP/GaP/Pure Green 555 Green Diffused 30 80 30 150 2.2 2.6 1.5 120L-030BL-R5132BGaP/GaP/Bright Red 700 90 40 15 50 2.2 2.6 0.8 BL-R4532B GaAsP/GaP/Hi-Eff Red 635 Red Diffused 45 80 30 150 2.0 2.6 5.0 BL-R2132BGaP/Gap/Green 568 Green Diffused 30 80 30 150 2.2 2.6 5.0 BL-R3132BGaAsP/GaP/Yellow 585 Yellow Diffused 35 80 30 150 2.1 2.6 4.0 2.0x5.0x 7.5mm1.0″ LeadRectangular BL-R4132BGaAsP/GaP/Orange 635 Orange Diffused 25 80 30 150 2.0 2.6 0.4 120L-031BL-R5132CGaP/GaP/Bright Red 700 90 40 15 50 2.2 2.6 0.8 BL-R4532C GaAsP/GaP/Hi-Eff Red 635 Red Diffused 45 80 30 150 2.0 2.6 4.0 BL-R2132C GaP/GaP/Green 568 Green Diffused 30 80 30 150 2.22.64.02.5x5.1x5.4mm 1.0″ Lead RectangularBL-R3132CGaAsP/GaP/Yellow585Yellow Diffused3580301502.1 2.63.0130L-032Notes: 1. All Dimensions are in millimeters (inches).2. Tolerance is ±0.25mm (.010″)STANDARD LED LAMPS (RECTANGULAR TYPES)ChipAbsolute MaximumRatings Electro-optical Data (At 20mA)Vf (V) Iv (mcd)PackagePart No.Material/EmittedColor Peak Wave Length λP (nm) Lens Appearance£G λ (nm) Pd (mw) If (mA) Peak (mA) Typ Max Typ ViewingAngle 2θ 1⁄2 (deg)Drawing No. BL-R5132RGaP/GaP/Bright Red 700 90 40 15 50 2.2 2.6 1.2 BL-R4532RGaAsP/GaP/Hi-Eff Red 635 Red Diffused 45 80 30 150 2.0 2.6 8.0 BL-R2132R GaP/GaP/Green 568 Green Diffused 30 80 30 150 2.2 2.6 8.0 BL-R3132R GaAsP/GaP/Yellow 585 Yellow Diffused 35 80 30 150 2.1 2.6 7.0 BL-R4132RGaAsP/GaP/Orange635 Orange Diffused 45 80 30 150 2.0 2.6 8.0 1.9x5.0x6.8mm 1.0″ Lead RectangularBL-RX1132R GaP/GaP/Hi-Eff Green 568 Green Diffused 30 80 30 150 2.2 2.6 12.0 140L-033BL-R5432TGaP/GaP/Bright Red 700 90 40 15 50 2.2 2.6 30.0 BL-R4632TGaAsP/GaP/Hi-Eff Red 635 Red Trans 45 80 30 150 2.0 2.6 80.0 BL-R2432T GaP/GaP/Green 568 Green Trans 30 80 30 150 2.2 2.6 80.0 BL-R3432T GaAsP/GaP/Yellow 585 Yellow Trans 35 80 30 150 2.1 2.6 70.0 BL-R4432TGaAsP/GaP/Orange635 Orange Trans 45 80 30 150 2.0 2.6 80.0 2.4x5.0x8.6mm 1.0″ Lead RectangularBL-RX1432T GaP/GaP/Hi-Eff Green 568 Green Trans 30 100 30 150 2.2 2.6 100 40L-034BL-R5133GaP/GaP/Bright Red 700 90 40 15 50 2.2 2.6 0.8 BL-R4533GaAsP/GaP/Hi-Eff Red 635 Red Diffused 45 80 30 150 2.0 2.6 5.0 BL-R2133 GaP/Gap/Green 568 Green Diffused 30 80 30 150 2.2 2.6 5.0 BL-R3133 GaAsP/GaP/Yellow 585 Yellow Diffused 35 80 30 150 2.1 2.6 4.0 BL-R4133GaAsP/GaP/Orange 635 Orange Diffused 45 80 30 150 2.0 2.6 5.0 1.4x4.7x7.0mm 1.0″ Lead RectangularBL-RX1133 GaP/Gap/Pure Green 568 Green Diffused 30 80 30 150 2.2 2.6 8.0 125L-035BL-R5130GaP/GaP/Bright Red 700 90 40 15 50 2.2 2.6 1.0 BL-R4530 GaAsP/GaP/Hi-Eff Red 635 Red Diffused 45 80 30 150 2.0 2.6 7.0 BL-R2130GaP/GaP/Green 568 Green Diffused 30 80 30 150 2.2 2.6 7.0 BL-R3130GaAsP/GaP/Yellow 585 Yellow Diffused 35 80 30 150 2.1 2.6 6.0 5.0x5.0x 7.1mm1.0″ LeadRectangular BL-R4130 GaAsP/GaP/Orange 635 Orange Diffused 25 80 30 150 2.0 2.6 7.0 150L-036BL-R5130NGaP/GaP/Bright Red 700 90 40 15 50 2.2 2.6 1.0 BL-R4530NGaAsP/GaP/Hi-Eff Red 635 Red Diffused45 80 30 150 2.0 2.6 7.0 BL-R2130N GaP/Gap/Green 568 30 80 30 150 2.2 2.6 7.0 BL-RX1130N GaP/GaP/Hi-Eff Green 568 Green Diffused 30 80 30 150 2.2 2.6 10.0 BL-R3130NGaAsP/GaP/Yellow 585 Yellow Diffused 35 80 30 150 2.1 2.6 6.0 5.0x5.0x7.1mm 1.0″ Lead RectangularBL-R4130N GaAsP/GaP/Orange 635 Orange Diffused 45 80 30 150 2.0 2.6 7.0 150L-037BL-R513PGaP/GaP/Bright Red 700 90 40 15 50 2.2 2.6 2.0 BL-R453PGaAsP/GaP/Hi-Eff Red 635 Red Diffused45 80 30 150 2.0 2.6 8.0 BL-R213P GaP/GaP/Green 568 30 80 30 150 2.2 2.6 8.0 BL-RX113P GaP/GaP/Hi-Eff Green 568 Green Diffused 30 80 30 150 2.2 2.6 11.0 BL-R313PGaAsP/GaP/Yellow 585 Yellow Diffused 35 80 30 150 2.1 2.6 7.0 3.7x6.3x6.8mm 1.0″ Lead RectangularBL-R413P GaAsP/GaP/Orange 635 Orange Diffused 45 80 30 150 2.0 2.6 8.0 120L-038BL-R513TGaP/GaP/Bright Red 700 90 40 15 50 2.2 2.6 1.0 BL-R453TGaAsP/GaP/Hi-Eff Red 635 Red Diffused45 80 30 150 2.0 2.6 6.0 BL-R213T GaP/GaP/Green 568 30 80 30 150 2.2 2.6 6.0 BL-RX113T GaP/GaP/Hi-Eff Green 568 Green Diffused 30 80 30 150 2.2 2.6 8.0 BL-R313TGaAsP/GaP/Yellow 585 Yellow Diffused 35 80 30 150 2.1 2.6 5.0 3.6x3.6x7.2mm 1.0″ Lead RectangularBL-R413TGaAsP/GaP/Orange635Orange Diffused4580301502.02.66.0120L-039元器件交易网元器件交易网STANDARD LED LAMPS (RECTANGULAR TYPES)Notes: 1. All Dimensions are in millimeters (inches).。

DL-S41-H2 高清 HDMI 自动切换器产品说明书

11675 Ridgeline Drive Colorado Springs, CO 80921Rev 181116Phone: 719-260-0061Toll-Free: 800-530-8998Fax: 719-260-0075DL-S41-H2 Quick Install GuideThis guide is for quick installati on only. For complete owners manual and list of commands, go to or use a QR reader to access the manual via QR code below.Scan QR Code with your Smart-phone or TabletDL-S41-H2 Quick Guide2The DL-S41-H2 is an slimline HDMI 2.0b auto switcher with four HDMI video inputs and one HDMI output. This switcher supports HDMI video resoluti ons up to 4Kx2K@60Hz 4:4:4, HDR, and multi channel audio. In additi on to passing EDID informati on from the display, there are multi ple built-in EDID setti ngs to simplify an installati on. The switcher will de-embed digital stereo audio to provide an analog audio source for an existi ng audio system. The switcher also supports audio return channel (ARC) for transmitti ng audio back to HDMI input and audio output ports from display device.When in auto-switch mode, the switcher will switch to an HDMI input as soon as a new source is connected. When the acti ve is removed, the switcher will select the ﬁ rst source on the lowest numbered input. The switcher may also be controlled via RS232, IR with the included remote, or from the source butt on on the front of the switcher.P roduct Overview P ackage Contents•DL-S41-H2 HDMI 2.0b Auto Switcher •Quick Install Guide •(1) IR Remote •(1) IR Receiver •(1) RS232 3.5mm to DB9 adapter cable •(1) DC5V 1A power supply with US, UK, EU and AU power adapter plugs •(2) Mounti ng ears with mounti ng screws • (4) Plasti c cushionsDL-S41-H2 Quick Guide3F ront and Rear PanelsFront161. AUTO/SOURCE - Auto / manual mode switching selecti on• Press and hold 3 seconds to switch between switching modes2. POWER LED - Illuminates RED when power is applied3. AUDIO MODE LED - Audio mode indicator• When LED is green, unit is in de-embed mode• When LED is yellow, unit is in ARC mode4. SOURCE MODE LED - Switch mode indicator• When LED is green, unit is in manual switch mode• When LED is yellow, unit is in auto switch mo de5. HDMI INPUT LEDS - Illuminates GREEN when there is an HDMI input on the corresponding channel6. FIRMWARE - USB port for ﬁ rmware updatesDL-S41-H2 Quick Guide4Rear 13456781. HDMI IN 1-3 - HDMI inputs 1 - 3 for HDMI sources2. (ARC) HDMI IN 4 - ARC compati ble HDMI input3. HDMI OUTPUT - HDMI output to connect to display technology4. AUDIO OUTPUT - 3.5mm audio output jack5. RS232 - 3.5mm serial control output6. IR IN - 3.5mm IR input port for IR receiver (included)7. EDID - 4 pin dip switch for EDID setti ngs8. DC 5V - DC barrel port for 5V power adapter (included)DL-S41-H2 Quick Guide5Connecti vity Instructi ons1. Verify all components included are present before installati on.2. System should be installed in a clean environment with proper temperature and humidity.3. All A/V devices including switcher should be connected together before powering on.4. Connect HDMI source devices to HDMI inputs5. Connect an HDMI display device to the HDMI output port6. Connect the AUDIO OUTPUT port on receiver to audio ampliﬁ er (opti onal)7. Connect the supplied IR receiver to the IR IN port to control switcher with supplied IR remote (opti onal)8. Connect RS232 port for serial control (opti onal)Note : A complete list of RS232 commands are located in the DL-S41-H2 owners manual locate online at 9. Set EDID dip switch to desired EDID setti ngNote : DL-S41-H2 ships with all dip switches in the OFF positi on or pass through EDID communicati on10. Connect the included power supply to the DL-S41-H2 switcher11. Power on att ached audio / video and control devicesDL-S41-H2 Quick Guide6Cabling Wiring RequirementsRS232 Wiring Connect the 3rd party controller device RX signal to TX pin of the DL-S41-H2 DB9 breakout cable. Then connect the controller TX signal to the RX in to complete wiring.Audio Output Wiring Below is an audio cable pin-out that is compatible with the DL-S41-H2 audio outputLEFTRIGHT GROUNDDL-S41-H2 Quick Guide7T echnical Speciﬁ cati onsVIDEO Video Inputs (4) HDMI Video Input Connector (4) HDMI type A Input Video Signal HDMI Video Output (1) HDMI Video Output Connector (1) HDMI type A Output Video Signal HDMI Input Resoluti ons Support-ed Up to 3840 x 2160 @ 60Hz, 4:4:4, 8bit color depth Standards Compliant with HDMI 2.0b & HDCP2.2AUDIO Supported output formats PCM 2.0Audio Output Stereo analog Audio Output Connector (1) 3.5mm TRS audio jack Audio Output Impedance 70 Ohms Frequency Response 20Hz~20K Hz CONTROL Control Port / Connector(1) IR / 3.5mm connector (1) RS232 / 3.5mm connector OTHER System Bandwidth 18Gbps Operati ng Temperature -10C ~ +55C Storage Temperature -25C ~ +70C Humidity 10% ~ 90%Power Supply Input:100V~240V AC; Output: 5V DC 1A Power Consumpti on 5 watt s Dimension (W*H*D)194mm * 12mm * 81mm / 7.6” * .47” * 3.2”Weight 180g / .4 lbs Warranty 5 years Certi ﬁ cati on CE, FCC, RoHSThank you for your purchase.For Technical Support please call our toll free number at *********************************************Digitalinx is a brand of:11675 Ridgeline DriveColorado Springs, Colorado80921 USAPhone: 719-260-0061Fax: 719-260-0075Toll-Free: 800-530-8998。

LBSS84LT1G中文资料

LBSS84LT1G1SOT –2323Power MOSFET130 mAmps, 50 VoltsP–Channel SOT–23These miniature surface mount MOSFETs reduce power loss conserve energy, making this device ideal for use in small power management circuitry.Typical applications are dc–dc converters, load switching,power management in portable and battery–powered products such as computers, printers, cellular and cordless telephones.•Energy Efficient•Miniature SOT–23 Surface Mount Package Saves Board Space Symbol Value Unit Drain–to–Source VoltageV DSS 50V dc Gate–to–Source Voltage – Continuous V GS±20V dc Drain Current– Continuous @ T A = 25°C– Pulsed Drain Current (t p ≤ 10µs)I DI DM 130520mATotal Power Dissipation @ T A = 25°C P D 225mW Operating and Storage Temperature RangeT J ,T stg –55 to 150°C Thermal Resistance – Junction–to–Ambient R θJA 556°C/W Maximum Lead Temperature for Soldering Purposes, for 10 secondsT L260°C RatingMAXIMUM RATINGS (T J = 25C unless otherwise noted)°12SourceMarking DiagramPD WW = Work Week•Pb-Free Package is available.DevicePackageShipping LBSS84LT1G SOT-233000/Tape&Reel LBSS84LT3GSOT-2310000/Tape&ReelORDERING INFORMATIONELECTRICAL CHARACTERISTICS (T= 25°C unless otherwise noted)2.Switching characteristics are independent of operating junction temperature.LBSS84LT1GTYPICAL ELECTRICAL CHARACTERISTICS00.30.40.10.60.2Figure 1. Transfer CharacteristicsI D , D R A I N C U R R E N T (A M P S )V GS , GATE-TO-SOURCE VOLTAGE (VOLTS)Figure 2. On–Region CharacteristicsV DS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)0.5LBSS84LT1GR D S (o n ), D R A I N -T O -S O U R C E R E S I S T A N C E (N O R M A L I Z E D )R D S (o n ), D R A I N -T O -S O U R C E R E S I S T A N C E (O H M S )Figure 5. On–Resistance Variation with TemperatureT J , JUNCTION TEMPERATURE (°C)Figure 6. Gate Charge)Q T , TOTAL GATE CHARGE (pC)TYPICAL ELECTRICAL CHARACTERISTICS0.0010.11V SD , DIODE FORWARD VOLTAGE (VOLTS)Figure 7. Body Diode Forward VoltageI D , D I O D E C U R R E N T (A M P S )0.01NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M,19822. CONTROLLING DIMENSION: INCH.INCHES MILLIMETERSDIM MIN MAX MIN MAX A 0.11020.1197 2.80 3.04B 0.04720.0551 1.20 1.40C 0.03500.04400.89 1.11D 0.01500.02000.370.50G 0.07010.0807 1.78 2.04H 0.00050.00400.0130.100J 0.00340.00700.0850.177K 0.01400.02850.350.69L 0.03500.04010.89 1.02S 0.08300.1039 2.10 2.64V0.01770.02360.450.60PIN 1. BASE2. EMITTER3. COLLECTORSOT -23VLBSS84LT1GReel DimensionsMetric Dimensions Govern –– English are in parentheses for reference onlyEMBOSSED TAPE AND REEL DATAFOR DISCRETESAT MaxOutside Dimension Measured at EdgeGInside Dimension Measured Near Hub20.2mm Min (.795’’)1.5mm Min(.06’’)13.0mm ± 0.5mm(.512 ±.002’’)50mm Min (1.969’’)Full RadiusSize A Max GT Max8 mm12mm 16mm 24 mm330mm (12.992’’) 330mm (12.992’’) 360mm (14.173’’) 360mm (14.173’’)8.4mm+1.5mm, -0.0(.33’’+.059’’, -0.00)12.4mm+2.0mm, -0.0(.49 ’’+ .079’’, -0.00)16.4mm+2.0mm, -0.0(.646’’+.078’’, -0.00)24.4mm+2.0mm, -0.0(.961’’+.070’’, -0.00)14.4mm (.56’’)18.4mm (.72’’)22.4mm (.882’’)30.4mm (1.197’’)LESHAN RADIO COMPANY, LTD.Storage ConditionsTemperature: 5 to 40 Deg.C (20 to 30 Deg. C is preferred) Humidity: 30 to 80 RH (40 to 60 is preferred )Recommended Period: One year after manufacturing(This recommended period is for the soldering condition only. The characteristics and reliabilities of the products are not restricted to this limitation)元器件交易网Shi p ment S p ecification10 Reel12 Inner Box/Carton 360KPCS/CartonDim(Unit:mm)Dim(Unit:mm)10Reel/Inner Box30KPCS/Inner Box460mm*400mm*420mm8000PCS/Reel (SOT-723,SOD-723)3000PCS/Reel80KPCS/Inner Box (SOT-723,SOD-723)960KPCS/Carton (SOT-723,SOD-723)LESHAN RADIO COMPANY, LTD.元器件交易网。

LBZX84XXXXLT1G中文资料

LBZX84XXXXLT1GSERIES132SOT– 23 (TO–236AB)PLASTICTHERMAL CHARACTERISTICSCharacteristicSymbol Max Unit Total Device Dissipation FR-5 Board* P D225mW T A = 25°CDerate above 25°C1.8 mW/°C Thermal Resistance Junction to Ambient R QJA 556°C/W Total Device DissipationP D300mW Alumina Substrate,** T A = 25°C Derate above 25°C2.4mW/°C Thermal Resistance Junction to Ambient R QJA 417 °C/W Junction and Storage T emeprature T J , T stg150°C**FR-5 = 1.0 x 0.75 x 0.62 in.**Alumina = 0.4 x 0.3 x 0.024 in. 99.5% alumina.Zener Voltage Regulator DiodesMAXIMUM CASE TEMPERATURE FOR SOLDERING PURPOSES: 260°C for 10 secondsLESHAN RADIO COMPANY, LTD.Ordering InformationDevicePackageShipping LBZX84XXXXLT1G SOT-233000/Tape&Reel LBZX84XXXXLT3GSOT-2310000/Tape&Reelƽ We declare that the material of productcompliance with RoHS requirements.GENERAL DATA — 225mW SOT-23LESHAN RADIO COMPANY, LTD.ELECTRICAL CHARACTERISTICS − BZX84CxxxLT1 SERIES (STANDARD TOLERANCE)(Pinout: 1-Anode, 2-No Connection, 3-Cathode) (T A = 25°C unless otherwise noted, V F = 0.90 V Max. @ I F = 10 mA)(Devices listed in bold, italic are ON Semiconductor Preferred devices.)Device*Device Marking V Z1 (Volts)@I ZT1=5mA (Note 3)Z ZT1(W )@ I ZT1 =5 mA V Z2 (V)@I ZT2=1mA (Note 3)Z ZT2(W )@ I ZT2 =10 mA V Z3 (V)@I ZT3=20mA(Note 3)Z ZT3(W )@ I ZT3 =20 mA Max Reverse Leakage Current q VZ (mV/k)@ I ZT1 = 5 mA C (pF)@ V R = 0f = 1 MHz Min Nom Max Min Max Min Max V R VoltsI R m A @Min Max LBZX84C2V4LT1G Z11 2.2 2.4 2.6100 1.7 2.1600 2.6 3.250501−3.50450LBZX84C2V7LT1G Z12 2.5 2.7 2.9100 1.9 2.46003 3.650201−3.50450LBZX84C3V0LT1G Z13 2.83 3.295 2.1 2.7600 3.3 3.950101−3.50450LBZX84C3V3LT1G Z14 3.1 3.3 3.595 2.3 2.9600 3.6 4.24051−3.50450LBZX84C3V6LT1G Z15 3.4 3.6 3.890 2.7 3.3600 3.9 4.54051−3.50450LBZX84C3V9LT1G Z16 3.7 3.9 4.190 2.9 3.5600 4.1 4.73031−3.5−2.5450LBZX84C4V3LT1G W94 4.3 4.690 3.34600 4.4 5.13031−3.50450LBZX84C4V7LT1G Z1 4.4 4.7580 3.7 4.7500 4.5 5.41532−3.50.2260LBZX84C5V1LT1G Z2 4.8 5.1 5.460 4.2 5.34805 5.91522−2.7 1.2225LBZX84C5V6LT1G Z3 5.2 5.6640 4.86400 5.2 6.31012−2.0 2.5200LBZX84C6V2LT1G Z4 5.8 6.2 6.610 5.6 6.6150 5.8 6.86340.4 3.7185LBZX84C6V8LT1G Z5 6.4 6.87.215 6.37.280 6.47.4624 1.2 4.5155LBZX84C7V5LT1G Z677.57.915 6.97.98078615 2.5 5.3140LBZX84C8V2LT1G Z77.78.28.7157.68.7807.78.860.75 3.2 6.2135LBZX84C9V1LT1G Z88.59.19.6158.49.61008.59.780.56 3.87.0130LBZX84C10LT1G Z99.41010.6209.310.61509.410.7100.27 4.58.0130LBZX84C11LT1G Y110.41111.62010.211.615010.411.8100.18 5.49.0130LBZX84C12LT1G Y211.41212.72511.212.715011.412.9100.18 6.010.0130LBZX84C13LT1G Y312.41314.13012.31417012.514.2150.187.011.0120LBZX84C15LT1G Y413.81515.63013.715.520013.915.7200.0510.59.213.0110LBZX84C16LT1G Y515.31617.14015.21720015.417.2200.0511.210.414.0105LBZX84C18LT1G Y616.81819.14516.71922516.919.2200.0512.612.416.0100LBZX84C20LT1G Y718.82021.25518.721.122518.921.4200.051414.418.085LBZX84C22LT1G Y820.82223.35520.723.225020.923.4250.0515.416.420.085LBZX84C24LT1GY922.82425.67022.725.525022.925.7250.0516.818.422.080DeviceDevice Marking V Z1 Below @I ZT1=2mAZ ZT1Below @ I ZT1 =2 mA V Z2 Below @I ZT2=0.1m-A Z ZT2Below @ I ZT4 =0.5 mA V Z3 Below @I ZT3=10mA Z ZT3Below @ I ZT3 =10 mA Max Reverse Leakage Current q VZ(mV/k) Below @ I ZT1 = 2 mA C (pF)@ V R = 0f = 1 MHzMin Nom Max Min Max Min Max V R (V)I R m A @Min Max LBZX84C27LT1G Y1025.12728.9802528.930025.229.3450.0518.921.425.370LBZX84C30LT1G Y112830328027.83230028.132.4500.052124.429.470LBZX84C33LT1G Y123133358030.83532531.135.4550.0523.127.433.470LBZX84C36LT1G Y133436389033.83835034.138.4600.0525.230.437.470LBZX84C39LT1G Y1437394113036.74135037.141.5700.0527.333.441.245LBZX84C43LT1G Y1540434615039.74637540.146.5800.0530.137.646.640LBZX84C47LT1G Y1644475017043.75037544.150.5900.0532.942.051.840LBZX84C51LT1G Y1748515418047.65440048.154.61000.0535.746.657.240LBZX84C56LT1G Y1852566020051.56042552.160.81100.0539.252.263.840LBZX84C62LT1G Y1958626621557.46645058.2671200.0543.458.871.635LBZX84C68LT1G Y2064687224063.47247564.273.21300.0547.665.679.835LBZX84C75LT1GY2170757925569.47950070.380.21400.0552.573.488.635Zener voltage is measured with a pulse test current I Z at an ambient temperature of 25°C.TYPICAL CHARACTERISICSGENERAL DATA — 225mW SOT –23876543210-1-2-323456789101112100101101001K1001011101000.40.50.60.70.80.91.01.11.2V Z , NOMINAL ZENER VOLTAGE (V)Figure 1. Temperature Coefficients (Temperature Range –55°C to +150°C)V Z , NOMINAL ZENER VOLTAGE (V)Figure 2. Temperature Coefficients (Temperature Range –55°C to +150°C)V Z , NOMINAL ZENER VOLTAGEFigure 3. Effect of Zener Voltage onZener ImpedanceV F , FORWARD VOLTAGE (V)Figure 4. Typical Forward Voltageθ V Z , T E M P E R A T U R E C O E F F I C I E N T (m V / °C )θ V Z , T E M P E R A T U R E C O E F F I C I E N T (m V / ° C )Z Z T , D Y N A M I C I M P E D A N C E (Ω)I F , F O R W A R D C U R R E N T (m A )V Z @ I ZTTYPICAL T C VALUES FOR MMBZ5221BLT1S E R I E STYPICAL T C VALUESFOR MMBZ5221BLT1S E R I E ST J = 25°CI Z(AC) = 0.1 I Z(DC)f = 1 kHzV Z @ I ZTI Z = 1 mA5 mA 20 mA1000100101150°C75 V (MMBZ5267BLT1)91 V (MMBZ5270BLT1)75°C 25°C0°CLESHAN RADIO COMPANY, LTD.TYPICAL CHARACTERISICSGENERAL DATA — 225mW SOT –23100010010111010010001001010.10.010.0010.00010.0000101020304050607080901001010.1002468101210305070901001010.10.01BIAS AT50% OF V Z NOMV Z , NOMINAL ZENER VOLTAGE (V)Figure 5. Typical Capacitance V Z , NOMINAL ZENER VOLTAGE (V)Figure 6. Typical Leakage CurrentV Z , ZENER VOLTAGE (V)Figure 7. Zener Voltage versus Zener Current(V Z Up to 12 V)V Z , ZENER VOLTAGE (V)Figure 8. Zener Voltage versus Zener Current(12 V to 91 V)T A = 25°C0 V BIAS 1 V BIAST A = 25°CT A = 25°C+150°C+25°C –55°CC , C A P A C I T A N C E (p F )I R , L E A K A G E C U R R E N T (µA )I Z , Z E N E R C U R R E N T (m A )I Z , Z E N E R C U R R E N T (m A )LESHAN RADIO COMPANY, LTD.GENERAL DATA — 225 mW SOT-23225 mW SOT-23Zener Voltage Regulator Diodes — Surface MountedMULTIPLE PACKAGE QUANTITY (MPQ)REQUIREMENTSNOTES:1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.A B C D G H J K L S VI N C H E S MILLIMETERS D I M M I N M A X M I N M A X 2.801.200.890.371.780.0130.0850.450.892.100.453.041.401.110.502.040.1000.1770.601.022.500.600.11020.04720.03500.01500.07010.00050.00340.01800.03500.08300.01770.11970.05510.04400.02000.08070.00400.00700.02360.04010.09840.0236(Refer to Section 10 for Surface Mount, Thermal Data and Footprint Information.)SOT-23 FootprintA LSVG123CKJB DHSTYLE 8:PIN 1. ANODE2. NO CONNECTION3. CATHODEinches mm ()0.0370.950.0370.950.0792.00.0350.90.0310.8(Refer to Section 10 for more information on Packaging Specifications.)Package Option Type No. SuffixMPQ (Units)Tape and Reel T13K Tape and AmmoT310KLESHAN RADIO COMPANY, LTD.Reel DimensionsMetric Dimensions Govern –– English are in parentheses for reference onlyEMBOSSED TAPE AND REEL DATAFOR DISCRETESAT MaxOutside Dimension Measured at EdgeGInside Dimension Measured Near Hub20.2mm Min (.795’’)1.5mm Min(.06’’)13.0mm ± 0.5mm(.512 ±.002’’)50mm Min (1.969’’)Full RadiusSize A Max GT Max 8 mm330mm (12.992’’)8.4mm+1.5mm, -0.0(.33’’+.059’’, -0.00)14.4mm (.56’’)LESHAN RADIO COMPANY, LTD.Storage ConditionsTemperature: 5 to 40 Deg.C (20 to 30 Deg. C is preferred) Humidity: 30 to 80 RH (40 to 60 is preferred )Recommended Period: One year after manufacturing(This recommended period is for the soldering condition only. The characteristics and reliabilities of the products are not restricted to this limitation)元器件交易网Shi p ment S p ecification10 Reel12 Inner Box/Carton 360KPCS/CartonDim(Unit:mm)Dim(Unit:mm)10Reel/Inner Box30KPCS/Inner Box460mm*400mm*420mm8000PCS/Reel (SOT-723,SOD-723)3000PCS/Reel80KPCS/Inner Box (SOT-723,SOD-723)960KPCS/Carton (SOT-723,SOD-723)LESHAN RADIO COMPANY, LTD.元器件交易网。

2SK3418中文资料

1 1 1 1
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)
1.
2
元器件交易网
2SK3418
160
1000 300
10
PW
µs
120
100 30
80
10 3
00 = 1 µs m DC 10 m Op s (1 s e (T rati sho c = on t) 25 )
1
40
1 0.3
0
50
100
150
200
元器件交易网
2SK3418
N MOS FET
ADJ-208-1030 (Z) 1 2000. 07
• RDS(on) = 4.3mΩ typ. • • (4V )
TO-220AB
D
G
1 2 S 3
元器件交易网
2SK3418
(Ta=25
· · VDSS VGSS ID ID (pulse) IDR IAP EAR Pch Tch Tstg –55
100-0004 (011) 261-3131 ( (022) 223-0121 ( (03) 3212-1111 ( (025) 241-8161 ( (029) 271-9411 ( (027) 325-2161 (03) 3270-2111 ( (0263) 36-6632 (045) 451-5000 (
Vin 10 V
50Ω
V DD = 30 V
Vout
7
元器件交易网
2SK3418
mm
10.16±0.2 2.79 ±0.2 1.27 9.5 8.0
+ 0.2
φ 3.6 - 0.08
+ 0.1
4.44±0.2 1.26±0.15

FELCOM12系列产品说明书

Tech Date Box 1 - FELCOM12 Display Wt: 24 lbs. Dim: 20"x 17"x 21"Part No.Description Quantity Yes Remarks 1IB581LCD Terminal Display with CPU 12000-138-599BTC-5100 PS/2 Keyboard 13000-055-405Blank Floppy Disk 1.44M 14004-437-270IB581 Software Floppy Disk 1updated periodically Box 2 - FELCOM12 Comm. Unit Wt: 30 lbs. Dim: 13"x 13"x 28"Part No.Description Quantity Yes Remarks 1IC212Communication Unit BDU 12000-802-080Tapping Screw 63000-861-937Knob Bolt 24004-437-990Hanger Assembly 15100-087-911Hanger Washer 26OME-561-30Z Operator's Manual 17OSE-561-30Z Operator's Guide 1Box 2 Con't. - FELCOM12 Antenna Unit "Part No.Description Quantity Yes Remarks 1IC112Antenna Unit Felcom 121Box 2 Con't. - FELCOM12PC Installation Kit "Part No.Description Quantity Yes Remarks 1IC302Distress Alert Unit 22IC303Telex Indicator 1Not in FELCOM12PC 3000-108-138Ground Wire 1sub 000-043-2594000-112-543Power Cable 1"5000-127-108DB9-DB9 Cable 1"6000-802-084Tapping Screw 4"7100-217-010Label INMAR 1"8100-237-670Hook Loop Fastener 4"9100-237-680Hook Loop Fastener 4"10100-248-051Label Keyboard 1"11100-248-060Label CSD 1"12000-122-400Power Cable 1sub 004-438-00013000-508-663Conn SRCN6A16-10P 1"14590-300-310Copper Strap 1.2M 1"15000-802-080Tapping Screw 6sub 000-043-34416000-861-937Knob Bolt 2"17100-087-911Hanger Washer 2"18004-437-990Hanger Assembly 1"19000-108-424Crimp Lug FV2-33sub 004-438-010 (X 3)20000-508-662Conn SRCN6A16-7P 3"21000-538-113Crimp Lug FV1.25-315"22000-802-079Tapping Screw 3 x 1012"23000-802-393Hole Plug 3"24000-808-099Bushing 3"25100-208-272Distress Cover 2sub 000-041-294PACKING LIST FOR RC1540IC212IC112IB581/12FELCOM12INSTTech Date Box 2 Con't. - FELCOM12PC Installation Kit "Part No.Description Quantity Yes Remarks 26100-248-770Distress Label 2sub 000-041-29427Distress Alert Procedures 128Precautions-Inmarsat C Felcom12129Precautions-IC302130OSC-561-31Z Simple E-Mail Felcom10/11/12131Creating Internet Message 132Activation Registration Form 133IME-561-30Z Installation Manual 1Box 3 - Cable Wt: 14 lbs. Dim: 10"x 13"x 14"Part No.Description Quantity Yes Remarks 1000-138-86730M Coax Cable 150M available 2000-133-058Conn. N-P-5DFB-113000-139-927Cable Assembly 16S023814000-566-000Grounding Wire 15000-835-526Self Bounding Tape 16000-854-118Adhesive 17000-862-182Hex Bolt M6 x 12 SUS30418000-862-129Hex Bolt M6 x 16 SUS30449100-251-820Antenna Mounting Pipe 110*000-117-599*50M with 8D-FB-CV Conn.**sub for 30M Box 4 - FS5000TPart No.Description Quantity Yes Remarks 1FS5000T 400W HF SSB Transceiver 1Serial No.2508 - Box 5 - FS5000C Wt: 63 lbs. Dim: 25"x 16"x 19"Part No.Description Quantity Yes Remarks1FS5000C Control Unit Keyboard Display 12OME-551-90Z Operator's Manual 13OSE-551-90Z Operator's Guide 14000-112-623Handset HS-6000FZ515100-121-490Plastic Frequency Card Holder 16100-121-500Frequency Table Card 27000-865-859Nylon Push Rivet FNRP 3 x 6.548000-801-662Tapping Screw M3 x 2069100-095-691Handset Hanger 210100-095-701Stopper Bracket 111100-095-711Template 1PACKING LIST FOR RC1540FS5000T For Internal Use Only FS5000C FELCOM12CBL FELCOM12INSTTech Date Box 5 (cont'd) - AT5000"Part No.Description Quantity Yes Remarks 1AT5000Automatic Antenna Coupler 1Box 5 (cont'd) - FS5000INST Wt: 27 lbs. Dim: 25"x 19"x 14"Part No.Description Quantity Yes Remarks 1000-538-114Crimp Lug FV1.25-41coupler 2000-800-054Hex Bolt M6 x 304"3000-864-129Flat Washer M68"4100-164-380Blind Cap 1"5000-500-512RF Connector MP73transceiver 6000-538-113Crimp Lug FV1.25-32"7000-800-488Tapping Screw M5 x 206"8000-864-128Flat Washer M56"9000-110-961Phono Plug PJ-2240-P 310000-121-824In-Line Plug 211000-116-634Cable Gland NW-12M 2control unit 12000-538-113Crimp Lug FV1.25-32"13000-800-488Tapping Screw M5 x 204"14000-864-128Flat Washer M54"15000-864-971Nylon Washer M54"Box 6 - Cable Wt: 11 lbs. Dim: 20"x 17"x 12"Part No.Description Quantity Yes Remarks 1000-106-043Interconnect Cable 10M "5 pr"2Serial No.3503 -Checked By:Box 7 - DP6 Modem Unit Wt: 13 lbs. Dim: 9"x 13"x 22"Part No.Description Quantity Yes Remarks1DP-6NBDP Modem Unit 12OME-561-00Z Operator's Manual 13IME-561-00Z Installation Manual 14OSE-561-00Z Operator's Guide 15590-300-310Copper Strap 1.2M 16000-867-553Tapping Screw M5 x 2547000-864-128Flat Washer M548000-120-946DB25 Connector 29000-112-543Power Cable Assembly 3M 110000-508-663Connector SCRN6A16-10P 1PACKING LIST FOR RC1540For Internal Use Only AT5000FS5000INST FS5000CBL DP6MAINTech Date Box 8 - DP6 LCD Terminal Wt: 24 lbs. Dim: 20"x 17"x 21"Part No.Description Quantity Yes Remarks 1IB581Monochrome LCD Terminal 1with DP6 on CPU 2000-138-599Mini Keyboard with Cable & Plug 13000-055-405Blank Floppy Disk 1.44M 1unformatted 4004-447-090DP6 Software "Floppy Disk"15000-108-138Grounding Wire 2M 16000-112-543Power Cable Assembly 3M 17000-127-108Data Cable DB25-DB25 "5M"18000-802-084Tapping Screw M6 x 2049100-217-010BCM Label 110100-237-670Hook Loop Fastener 1411100-237-680Hook Loop Fastener 2412100-248-050Label 113100-248-060Label "Compass Safe Distance"1Serial No.3516 - Checked By:Box 9 - DSC60 Terminal ReceiverPart No.Description Quantity Yes Remarks 1DSC60DSC Terminal / Watch Receiver 12OME-562-80Z Operator's Manual 13IME-562-80Z Installation Manual 14005-950-250Mounting Bracket 15005-948-710Mouunting Knob Assembly 2sub 005-950-1806000-800-414Tapping Screw M6 x 205"7000-864-129Flat Washer M65"8000-144-917External Speaker with Cord & Plug 1Serial No.2596 - Checked By:Box 10 & 11 - FM8500 (x 2)Wt: 17 lbs. Dim: 9"x 15"x 18"Part No.Description Quantity Yes Remarks1FM8500Main Unit 12OME-560-30Z Operator's Manual 13IME-560-30Z Installation Manual 14Distress Alert Procedure 15000-138-000Handset Bracket Assembly 16100-274-720Distress button Cover Assembly 17000-108-368Plug FM14-4P 18000-111-537Plug FM14-5P 19000-116-185Plug FM14-6P 110000-113-345Plug FM14-7P 111000-500-346Plug HS16P-2112005-992-690Bracket Assembly 113000-800-601Knobs 2PACKING LIST FOR RC1540DSC60For Internal Use Only FM8500IB581/6For Internal Use OnlyTech Date Serial No.2596 - Checked By:Box 10 & 11 (con't) - FM8500 (x 2)"000-800-414Tapping Screw 6 6 x 2015000-864-129Flat Washer 6M616100-087-911Hanger Washer 217100-100-390Knob Washer 2on knob 18OSE-560-30Z Operator's Guide 1Serial No.1375 - Checked By:Box 12 & 13 - PP510 (x 2)Wt: 27 lbs. Dim: 18"x 17"x 16"Part No.Description Quantity Yes Remarks 1PP51024V Dot Matrix Printer 12PP5-100-002Paper Carriage Assy 13000-133-029Ribbon Cassette 14004-434-410Printer Fixtures (2pc)1sub 000-043-2575Carrier Mount 2"6Knurled Screws for Mounting 2"7Hook Loop Fastener Strip 2"8000-802-081Tapping Screw 4"9100-217-010"BCM" Sticker 1"10100-222-480"Compass Safe" Sticker 1"11000-132-249Power Cable Assy 112RC1-500-019Cable 6 ft. Centronics 36p>DB25113AYT214Roll Paper 114OME-508-00Z Operator's Manual 1Box 14 - PR850A Wt: 86 lbs. Dim: 16"x 20"x 20"Part No.Description Quantity Yes Remarks 1PR805A Rectifier AC to 24 VDC 1w/ auto switchover2Label Voltage Selection (100-240V)13Lug Solder Type 24Lug Crimp 35Tapping Screw 66Washer Flat 67Voltage Alternation List 1For Internal Use Only FM8500PR850A PACKING LIST FOR RC1540For Internal Use Only PP510Tech Date Box (Crate) 15 - FUSA1500Wt: 296 lbs. Dim: 32"x 36"x 47"Part No.Description Quantity Yes Remarks 1FUSA1500A3 Pre-Wired Rack w/ meter 1with NMEA distributor 2Shore-Based Maintenance Certificate 1& incl mic bracket 3"E Meter" Owner's Manual 14IME-GMD-10Z Console Installation Manual 15RC1-500-034ATC Fuse 3A 36RC1-500-014Bulb 5W 24V 17RC1-500-060Connector PL2592FELCOM12KIT (Installed in IC212 - in Box 1)Part No.Description Quantity Yes Remarks 1006-969-200GPS Module GN74NNCC NE 12RF Mini Coax 138 pin VH Pigtail (to CPU J8)1rev 6/03PACKING LIST FOR RC1540FUSA1500FELCOM12KIT。

美的bl1214a说明书

美的bl1214a说明书
规格参数
产品亮点冷热双杯
产品容量 1.75L
热杯容量 1.4L
操作方式触摸式
档位调节8档
美食菜单榨汁/果汁，豆浆，绞肉适用人数2-5人
加热功能支持
预约功能支持，12小时
自动清洗支持，一键清洗
产品电压220V/50Hz
额定功率加热：800W
搅拌功率1200W
电机转速36000r/min
其他规格
外形设计香槟金
产品尺寸224*208*487mm 产品重量7.3kg
产品材质杯体材质：玻璃刀头精钢八叶破壁刀产品附件
包装清单榨汁机x1
玻璃搅拌杯x1
研磨杯x1
专业绞肉杯x1
说明书/保修卡（合订) x1
保修信息
保修政策全国联保，享受三包服务质保时间1年
客服电话
电话备注24小时电话服务。

DS21448DK资料

Device Power-Up and Reset................................................................................................................ 18 Register Map........................................................................................................................................ 18 Control Registers ................................................................................................................................. 19
6.2.1 6.2.2 6.2.3 6.2.4 Remote Loopback (RLB) ..................................................................................................................... 31 Local Loopback (LLB) .......................................................................................................................... 31 Analog Loopback (LLB) ....................................................................................................................... 31 Dual Loopback (DLB)........................................................................................................................... 31

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STANDARD LED LAMPS (CYLINDRICAL TYPES)ChipAbsolute MaximumRatingsElectro-optical Data(At 20mA) Vf (V) Iv (mcd) PackagePart No.Material/EmittedColor Peak Wave Length λP (nm) Lens Appearance£G λ (nm) Pd (mw) If (mA) Peak(mA)Typ Max Typ Viewing Angle 2θ 1⁄2 (deg) Drawing No. BL-C5121GaP/GaP/Bright Red 700 90 40 15 50 2.2 2.6 1.2 BL-C4521 GaAsP/GaP/Hi-Eff Red 635 Red Diffused 45 80 30 150 2.0 2.6 9.0 BL-C2121 GaP/GaP/Green 568 Green Diffused 30 80 30 150 2.2 2.6 9.0 Cyclindrical 0.5″ Lead4.5£pBL-C3121 GaP/GaP/Hi-Eff Green 585 Yellow Diffused 35 80 30 150 2.1 2.6 8.0 150L-040BL-C5132 GaP/GaP/Bright Red 700 90 40 15 50 2.2 2.6 3.0 BL-C4532GaAsP/GaP/Hi-Eff Red 635 Red Diffused 45 80 30 150 2.0 2.6 9.0 BL-C2132GaP/GaP/Green 568 30 80 30 150 2.2 2.6 9.0 BL-CX1132 GaP/GaP/Hi-Eff Green 568 Green Diffused30 80 30 150 2.2 2.6 12.0 BL-C3132GaAsP/GaP/Yellow 585 Yellow Diffused 35 80 30 150 2.1 2.6 8.0 1.0″ Lead Cylindrical£p3.0BL-C4132 GaAsP/GaP/Orange 635 Orange Diffused 45 100 30 150 2.0 2.6 9.0 130L-041BL-C5435 GaP/GaP/Bright Red 700 90 40 15 50 2.2 2.6 5.0 BL-C4635GaAsP/GaP/Hi-Eff Red 635 Red Trans 45 80 30 150 2.0 2.6 15.0 BL-C2435 GaP/GaP/Green 568 30 80 30 150 2.2 2.6 15.0 BL-CX1435 GaP/GaP/Hi-Eff Green 568 Green Trans 30 80 30 150 2.2 2.6 18.0 BL-C3435 GaAsP/GaP/Yellow 585 Yellow Trans 35 80 30 150 2.1 2.6 12.0 1.0″ Lead Cylindrical£p3.0BL-C4435 GaAsP/GaP/Orange 635 Orange Trans 45 100 30 150 2.0 2.6 15.0 120L-042BL-C5436 GaP/GaP/Bright Red 700 90 40 15 50 2.2 2.6 5.0 BL-C4636GaAsP/GaP/Hi-Eff Red 635 Red Trans 45 80 30 150 2.0 2.6 14.0 BL-C2436GaP/Gap/Green 568 30 80 30 150 2.2 2.6 14.0 BL-CX1436 GaP/GaP/Hi-Eff Green 568 Green Trans 30 80 30 150 2.2 2.6 16.0 BL-C3436 GaAsP/GaP/Yellow 585 Yellow Trans 35 80 30 150 2.1 2.6 13.0 1.0″ Lead Cylindrical£p5.0BL-C4436GaAsP/GaP/Orange635Orange Trans 45100301502.02.614.0120L-043元器件交易网STANDARD LED LAMPS (CYLINDRICAL TYPES)Notes: 1. All Dimensions are in millimeters (inches).2. Tolerance is ±0.25mm (.010″)STANDARD LED LAMPS (TOWER TYPES)ChipAbsolute MaximumRatings Electro-opticalData(At 20mA) Vf (V) Iv (mcd)PackagePart No.Material/EmittedColorPeak Wave Lengt h λP (nm) Lens Appearance£G£f (nm) Pd (mw) If (mA) Peak (mA)Typ Max Typ Viewi ng Angle 2θ 1⁄2 (deg) Drawi ng No.BL-S5131 GaP/GaP/Bright Red 700 90 40 15 50 2.2 2.6 1.2 BL-S4531 GaAsP/GaP/Hi-Eff Red 635 Red Diffused 45 80 30 150 2.0 2.6 6.0 BL-S2131 GaP/GaP/Green 568 Green Diffused 30 80 30 150 2.2 2.6 6.0 Panel Dot 1.0″ Lead £p1.75BL-S3131GaAsP/GaP/Yellow 585 Yellow Diffused 35 80 30 150 2.1 2.6 4.0 75 L-044BL-S5132GaP/GaP/Bright Red 700 90 40 15 50 2.2 2.6 1.2 BL-S4532GaAsP/GaP/Hi-Eff Red 635 Red Diffused 45 80 30 150 2.0 2.6 6.0 BL-S2132GaP/GaP/Green 568 30 80 30 150 2.2 2.6 6.0 BL-SX1132 GaP/GaP/Hi-Eff Green 568 Green Diffused 30 80 30 150 2.2 2.6 9.0 BL-S3132GaAsP/GaP/Yellow 585 Yellow Diffused 35 80 30 150 2.1 2.6 5.0 1.0″ LeadTowerφ3.0BL-S4132 GaAsP/GaP/Orange 635 Orange Diffused 45 80 30 150 2.0 2.6 6.0 100L-045BL-S5133GaP ⁄GaP ⁄Bright Red 700 90 40 15 50 2.2 2.6 1.4 BL-S4533GaAsP/GaP/Hi-Eff Red 635 Red Diffused 45 80 30 150 2.0 2.6 6.0 BL-S2133GaP/GaP/Green 568 30 80 30 150 2.2 2.6 6.0 BL-SX1133GaP/Gap/Hi-Eff Green 568 Green Diffused 30 80 30 150 2.2 2.6 9.0 BL-S3133GaAsP/GaP/Yellow 585 Yellow Diffused 35 80 30 150 2.1 2.6 5.0 1.0″ LeadTowerφ2.75 BL-S4133 GaAsP/GaP/Orange 635 Orange Diffused 45 80 30 150 2.0 2.6 6.0 100L-046BL-S5136GaP/GaP/Bright Red 700 90 40 15 50 2.2 2.6 1.2 BL-S4536GaAsP/GaP/Hi-Eff Red 635 Red Diffused 45 80 30 150 2.0 2.6 7.0 BL-S2136GaP/Gap/Green 568 30 80 30 150 2.2 2.6 7.0 BL-SX1136 GaP/Gap/Hi-Eff Green 568 Green Diffused 30 80 30 150 2.2 2.6 10.0 BL-S3136GaAsP ⁄GaP ⁄Yellow 585 Yellow Diffused 35 80 30 150 2.1 2.6 6.0 1.0″ LeadTowerφ2.0BL-S4136 GaAsP ⁄GaP ⁄Orange 635 Orange Diffused 45 80 30 150 2.0 2.6 7.0 70L-047BL-S5137GaP/GaP/Bright Red 700 90 40 15 50 2.2 2.6 15 BL-S4537GaAsP/GaP/Hi-Eff Red 635 Red Diffused 45 80 30 150 2.0 2.6 22 BL-S2137GaP/GaP/Green 568 30 80 30 150 2.2 2.6 22 BL-SX1137 GaP/GaP/Hi-Eff Green 568 Green Diffused 30 80 30 150 2.2 2.6 25 BL-S3137GaAsP/GaP/Yellow 585 Yellow Diffused 35 80 30 150 2.1 2.6 21 1.0″ LeadTowerφ2.8BL-S4137 GaAsP/GaP/Orange 635 Orange Diffused 45 80 30 150 2.0 2.6 22 100L-048 BL-S5137AGaP/GaP/Bright Red 700 90 40 15 50 2.2 2.6 15 BL-S4537AGaAsP/GaP/Hi-Eff Red 635 Red Diffused 45 80 30 150 2.0 2.6 22 BL-S2137AGaP/GaP/Green 568 30 80 30 150 2.2 2.6 22 BL-SX1137A GaAsP/GaP/Hi-Eff Green 568 Green Diffused30 80 30 150 2.2 2.6 25 BL-S3137AGaAsP/GaP/Orange 585 Yellow Diffused 35 80 30 150 2.1 2.6 21 1.0″ LeadTowerφ3.0BL-S4137A GaAsP/GaP/Orange 635 Orange Diffused 45 80 30 150 2.0 2.6 2270L-049BL-S51L8GaP/GaP/Bright Red 700 90 40 15 50 2.2 2.6 1.0 BL-S45L8GaAsP/GaP/Hi-Eff Red 635 Red Diffused 45 80 30 150 2.0 2.6 5.0 BL-S21L8GaP/GaP/Green 568 30 80 30 150 2.2 2.6 5.0 BL-SX11L8 GaAsP/GaP/Hi-Eff Green 568 Green Diffused30 80 30 150 2.2 2.6 8.0 BL-S31L8GaAsP/GaP/Yellow 585 Yellow Diffused 35 80 30 150 2.1 2.6 4.0 1.0″ LeadTowerφ1.8BL-S41LL8 GaAsP/GaP/Orange 635 Orange Diffused 45 80 30 150 2.0 2.6 5.0 70L-050 BL-S5149GaP/GaP/Bright Red 700 90 40 15 50 2.2 2.6 1.0 BL-S4549 GaAsP/GaP/Hi-Eff Red 635 Red Diffused 45 80 30 150 2.0 2.6 8.0 BL-S2149 GaP/Gap/Green 568 Green Diffused 30 80 30 150 2.2 2.6 8.0 BL-S31149GaAsP/GaP/Green 568 Yellow Diffused 30 80 30 150 2.2 2.6 7.0 1.0″ Lead Tower φ2.0 BL-S4149GaAsP/GaP/Orange 635 Orange Diffused 35 80 30 150 2.1 2.6 8.0 100L-051 BL-S5149A GaP/GaP/Bright Red 700 90 40 15 50 2.2 2.6 1.0 BL-S4549AGaAsP/GaP/Hi-Eff Red 635 Red Diffused 45 80 30 150 2.0 2.6 8.0 BL-S2149A GaP/GaP/Green 568 Green Diffused 30 80 30 150 2.2 2.6 8.0 1.0″ LeadTowerφ2.0BL-S31149AGaAsP/GaP/Yellow585Yellow Diffused 3580301502.12.67.0120L-052Remark: 1. Hi-eff Red/Hight-Effici1ency Red. 2. Trans/Transparent.3. 2θ 1/2 The off-axis angle at which the luminous intensity is half the axial luminous intensity.STANDARD LED LAMPS (TOWER TYPES)Notes: 1. All Dimensions are in millimeters (inches).2. Tolerance is ±0.25mm (.010″)STANDARD LED LAMPS (TOWER TYPES)。