CY7C1351G-133BGC中文资料

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CY7C9915-2JXC资料

Each output can be hardwired to one of nine delay or function configurations. Delay increments of 0.42 to 1.6 ns are determined by the operating frequency with outputs able to skew up to ±6 time units from their nominal “zero” skew position. The completely integrated PLL allows external load and transmission line delay effects to be canceled. When this “zero delay” capability of the LVPSCB is combined with the selectable output skew functions, the user can create output-to-output delays of up to ±12 time units.
Notes:
Skew Select Matrix
The skew select matrix is comprised of four independent sections. Each section has two low-skew, high-fanout drivers (xQ0, xQ1), and two corresponding three-level function select (xF0, xF1) inputs. Table 2 below shows the nine possible output functions for each section as determined by the function select inputs. All times are measured with respect to the REF input assuming that the output connected to the FB input has 0tU selected.

CY7C1352F-133AC中文资料

4.5
ns
205
mA
40
mA
Pin Configuration
100-Pin TQFP
NC
NC
81 A
82 A
85 ADV/LD
86 OE
87 CEN
WE
89 CLK
VSS
VDD
CE3
BWA
BWB
95 NC
96 NC
CE2
CE1
99 A
A
83
84
88
90
91
92
93
94
97
98
100
NC
1
NC
2
NC
• Internally self-timed output buffer control to eliminate the need to use OE
• Byte Write capability • 256K x 18 common I/O architecture • Single 3.3V power supply • 2.5V / 3.3V I/O Operation • Fast clock-to-output times
NC
77
VDDQ
76
VSS
75
NC
74
DQPA
73
DQA
72
DQA
71
VSS
70
VDDQ
69
DQA
68
DQA
67
VSS
BYTE A
66
NC
65
VDD
64
ZZ
63
DQA
62
DQA
61

CY7C9925资料

PRELIMINARY3.3V/2.5V Programmable Skew Clock BufferCY7C9925Features•All output pair skew <100 ps (typical)•Input Frequency Range: 3.75 MHz to 200 MHz •Output Frequency Range: 3.75 MHz to 200 MHz •User-selectable output functions—Selectable skew to 18 ns—Inverted and non-inverted—Operation at 1⁄2 and 1⁄4 input frequency—Operation at 2x and 4x input frequency (input as low as 3.75 MHz)•Zero input-to-output delay•3.3V Core power supply•Split 2.5V or 3.3V Output power supplies•± 2.5% Output Duty Cycle Distortion for 3.3V Output •LVTTL outputs drive 50Ω terminated lines•Low operating current•32-pin QFN package•Jitter < 100ps peak-to-peak (< 15 ps RMS)Functional DescriptionThe CY7C9925 RoboClock is 200-MHz Low-voltage Program-mable Skew Clock Buffer that offers user-selectable control over system clock functions. This multiple-output clock driver provides the system integrator with functions necessary to optimize the timing of high-performance computer systems. Eight individual drivers, arranged as four pairs of user-control-lable outputs, can each drive terminated transmission lines with impedances as low as 50Ω while delivering minimal and specified output skews and full-swing logic levels (LVTTL).Each output can be hardwired to one of nine delay or function configurations. Delay increments of 0.32 to 1.6 ns are deter-mined by the operating frequency with outputs able to skew up to ±6 time units from their nominal “zero” skew position. The completely integrated PLL allows external load and trans-mission line delay effects to be canceled. When this “zero delay” capability of the LVPSCB is combined with the selectable output skew functions, the user can create output-to-output delays of up to ±12 time units.Divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. When combined with the internal PLL, these divide functions allow distribution of a low-frequency clock that can be multi-plied by two or four at the clock destination. This facility minimizes clock distribution difficulty while allowing maximum system clock speed and flexibility.Block Diagram DescriptionPhase Frequency Detector and FilterThese two blocks accept inputs from the Reference Frequency (REF) input and the Feedback (FB) input and generate correction information to control the frequency of the Voltage-Controlled Oscillator (VCO). These blocks, along with the VCO, form a Phase-Locked Loop (PLL) that tracks the incoming REF signal.VCO and Time Unit GeneratorThe VCO accepts analog control inputs from the PLL filter block and generates a frequency that is used by the time unit generator to create discrete time units that are selected in the skew select matrix. The operational range of the VCO is deter-mined by the FS control pin. The time unit (t U ) is determined by the operating frequency of the device and the level of the FS pin as shown in Table 1.Skew Select MatrixThe skew select matrix is comprised of four independent sections. Each section has two low-skew, high-fanout drivers (xQ0, xQ1), and two corresponding three-level function select (xF0, xF1) inputs. Table 2 below shows the nine possible output functions for each section as determined by the function select inputs. All times are measured with respect to the REF input assuming that the output connected to the FB input has 0t U selected.Notes:1.For all three-state inputs, HIGH indicates a connection to V CC , LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry holds an unconnected input to V CC /2.2.The level to be set on FS is determined by the “normal” operating frequency (f NOM ) of the V CO and Time Unit Generator (see Logic Block Diagram). Nominal frequency (f NOM ) always appears at 1Q0 and the other outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the REF and FB inputs will be f NOM when the output connected to FB is undivided. The frequency of the REF and FB inputs will be f NOM /2 or f NOM /4 when the part is configured for a frequency multiplication by using a divided output as the FB input.Pin DefinitionsPin I/O TypeDescription29Ref Input LVTTL/LVCMOSReference Clock Input 13FB Input LVTTL Feedback Clock Input31FS Input Three-level Three Level Frequency Range Select 22,231F0, 1F1Input Three-level Three level function select for 1Q0,1Q125,262F0, 2F1Input Three-level Three level function select for 2Q0,2Q132,13F0, 3F1Input Three-level Three level function select for 3Q0,3Q12, 34F0, 4F1Input Three-level Three level function select for 4Q0,4Q127TestInputThree-level Three level select for test modes 19,201Q0, 1Q1Output LVTTL Output Pair 15,162Q0, 2Q1Output LVTTL Output Pair 10,113Q0, 3Q1Output LVTTL Output Pair 6,74Q0, 4Q1Output LVTTL Output Pair21VCCN1 Power POWER 3.3V or 2.5V Power Supply for output pair 1Q0 and 1Q1. 14VCCN2 Power POWER 3.3V or 2.5V Power Supply for output pair 2Q0 and 2Q1. 12VCCN3 Power POWER 3.3V or 2.5V Power Supply for output pair 3Q0 and 3Q1. 5VCCN4 Power POWER 3.3V or 2.5V Power Supply for output pair 4Q0 and 4Q1. 4,30VCCQPower POWER 3.3V Core Power 8,9,17,18,24,28GNDGroundPOWERGroundTable 1.Frequency Range Select and t U Calculation [1]FS [2]f NOM (MHz)where N =Approximate Frequency (MHz) At Which t U = 1.0nsMin.Max.LOW 15304422.7MID 25502638.5HIGH402001662.5t U 1f NOM N×-----------------------=Note:3.FB connected to an output selected for “zero” skew (i.e., xF1 = xF0 = MID).Table 2.Programmable Skew Configurations [1]Function SelectsOutput Functions1F1, 2F1, 3F1, 4F11F0, 2F0, 3F0, 4F01Q0, 1Q1,2Q0, 2Q13Q0, 3Q14Q0, 4Q1LOW LOW –4t U Divide by 2Divide by 2LOW MID –3t U –6t U –6t U LOW HIGH –2t U –4t U –4t U MID LOW –1t U –2t U –2t U MID MID 0t U 0t U 0t U MID HIGH +1t U +2t U +2t U HIGH LOW +2t U +4t U +4t U HIGH MID +3t U +6t U +6t U HIGHHIGH+4t UDivide by 4InvertedFigure 1. Typical Outputs with FB Connected to a Zero-Skew Output [3]t 0– 6t Ut 0– 5t Ut 0– 4t Ut 0– 3t Ut 0– 2t Ut 0– 1t Ut 0t 0+1tUt 0t 0t 0t 0t 0+2tU+3tU+4tU+5tU+6tUFBInput REFInput– 6t U – 4t U – 3t U – 2t U – 1t U 0t U +1t U +2t U +3t U +4t U +6t U DIVIDED INVERTLM LH (N/A)ML (N/A)MM (N/A)MH (N/A)HL HM LL/HH HH3Fx 4Fx (N/A)LL LM LH ML MM MH HL HM HH (N/A)(N/A)(N/A)1Fx 2FxTest ModeThe TEST input is a three-level input. In normal system operation, this pin is connected to ground, allowing the CY7C9925 to operate as explained briefly above (for testing purposes, any of the three-level inputs can have a removable jumper to ground, or be tied LOW through a 100Ω resistor.This will allow an external tester to change the state of these pins.)If the TEST input is forced to its MID or HIGH state, thedevice will operate with its internal phase locked loop discon-nected, and input levels supplied to REF will directly control all outputs. Relative output to output functions are the same as in normal mode.In contrast with normal operation (TEST tied LOW). All outputs will function based only on the connection of their own function select inputs (xF0 and xF1) and the waveform characteristics of the REF input.Operational Mode DescriptionsFigure 2 shows the LVPSCB configured as a zero-skew clock buffer. In this mode the CY7C9925 can be used as the basis for a low-skew clock distribution tree. When all of the function select inputs (xF0, xF1) are left open, the outputs are aligned and may each drive a terminated transmission line to an independent load. The FB input can be tied to any output inthis configuration and the operating frequency range is selected with the FS pin. The low-skew specification, coupled with the ability to drive terminated transmission lines (with impedances as low as 50Ω), allows efficient printed circuit board design.Figure 3 shows a configuration to equalize skew between metal traces of different lengths. In addition to low skew between outputs, the LVPSCB can be programmed to stagger the timing of its outputs. The four groups of output pairs can each be programmed to different output timing. Skew timing can be adjusted over a wide range in small increments with the appropriate strapping of the function select pins. In this config-uration the 4Q0 output is fed back to FB and configured forFigure 2. Zero-Skew and/or Zero-Delay Clock DriverSYSTEM CLOCKL1L2L3L4LENGTH L1=L2=L3=L4FB REF FS 4F04F13F03F12F02F11F01F14Q04Q13Q03Q12Q02Q11Q01Q1TESTZ 0LOADLOADLOADLOADREFZ 0Z 0Z 0Figure 3. Programmable-Skew Clock DriverLENGTH L1=L2L3<L2by 6inches L4>L2by 6inchesSYS-TEM CLOCKL1L2L3L4FB REF FS 4F04F13F03F12F02F11F01F14Q04Q13Q03Q12Q02Q11Q01Q1TESTZ 0LOADLOADLOADLOADREFZ 0Z 0Z 0zero skew. The other three pairs of outputs are programmed to yield different skews relative to the feedback. By advancing the clock signal on the longer traces or retarding the clock signal on shorter traces, all loads can receive the clock pulse at the same time.In this illustration the FB input is connected to an output with 0-ns skew (xF1, xF0 = MID) selected. The internal PLL synchronizes the FB and REF inputs and aligns their rising edges to insure that all outputs have precise phase alignment.Clock skews can be advanced by ±6 time units (t U ) when using an output selected for zero skew as the feedback. A wider range of delays is possible if the output connected to FB is also skewed.Since “Zero Skew”, +t U , and –t U are defined relative to output groups, and since the PLL aligns the rising edges of REF and FB,it is possible to create wider output skews by proper selection of the xFn inputs. For example a +10 t U between REF and 3Qx can be achieved by connecting 1Q0 to FB and setting 1F0 = 1F1 = GND,3F0 = MID, and 3F1 = High. (Since FB aligns at –4 t U and 3Qx skews to +6 t U , a total of +10 t U skew is realized.) Many other config-urations can be realized by skewing both the output used as the FB input and skewing the other outputs.Figure 4 shows an example of the invert function of the LVPSCB. In this example the 4Q0 output used as the FB input is programmed for invert (4F0 = 4F1 = HIGH) while the other three pairs of outputs are programmed for zero skew. When 4F0 and 4F1 are tied HIGH, 4Q0 and 4Q1 become inverted zero phase outputs. The PLL aligns the rising edge of the FB input with the rising edge of the REF. This causes the 1Q, 2Q,and 3Q outputs to become the “inverted” outputs with respect to the REF input. By selecting which output is connect to FB,it is possible to have 2 inverted and 6 non-inverted outputs or 6 inverted and 2 non-inverted outputs. The correct configu-ration would be determined by the need for more (or fewer)inverted outputs. 1Q, 2Q, and 3Q outputs can also be skewed to compensate for varying trace delays independent of inversion on 4Q.Figure 5 illustrates the LVPSCB configured as a clock multi-plier. The 3Q0 output is programmed to divide by four and is fed back to FB. This causes the PLL to increase its frequency until the 3Q0 and 3Q1 outputs are locked at 20 MHz while the 1Qx and 2Qx outputs run at 80 MHz. The 4Q0 and 4Q1outputs are programmed to divide by two, which results in a 40-MHz waveform at these outputs. Note that the 20- and 40-MHz clocks fall simultaneously and are out of phase on their rising edge. This will allow the designer to use the rising edges of the 1⁄2 frequency and 1⁄4 frequency outputs without concern for rising-edge skew. The 2Q0, 2Q1, 1Q0, and 1Q1outputs run at 80 MHz and are skewed by programming their select inputs accordingly. Note that the FS pin is wired for 80-MHz operation because that is the frequency of the fastest output.Figure 6 demonstrates the LVPSCB in a clock divider appli-cation. 2Q0 is fed back to the FB input and programmed for zero skew. 3Qx is programmed to divide by four. 4Qx is programmed to divide by two. Note that the falling edges of the 4Qx and 3Qx outputs are aligned. This allows use of the rising edges of the 1⁄2 frequency and 1⁄4 frequency without concern for skew mismatch. The 1Qx outputs are programmed to zero skew and are aligned with the 2Qx outputs. In this example,the FS input is grounded to configure the device in the 15- toFigure 4. Inverted Output ConnectionsFB REF FS 4F04F13F03F12F02F11F01F14Q04Q13Q03Q12Q02Q11Q01Q1TESTREFFigure 5. Frequency Multiplier with Skew Connections Figure 6. Frequency Divider ConnectionsFB REF FS 4F04F13F03F12F02F11F01F14Q04Q13Q03Q12Q02Q11Q01Q1TESTREF20 MHz20 MHz 40 MHz 80 MHzFB REF FS 4F04F13F03F12F02F11F01F14Q04Q13Q03Q12Q02Q11Q01Q1TESTREF20 MHz5 MHz 10 MHz 20 MHz30-MHz range since the highest frequency output is running at 20 MHz.Figure 7 shows some of the functions that are selectable on the 3Qx and 4Qx outputs. These include inverted outputs and outputs that offer divide-by-2 and divide-by-4 timing. An inverted output allows the system designer to clock different subsystems on opposite edges, without suffering from the pulse asymmetry typical of non-ideal loading. This function allows the two subsystems to each be clocked 180 degrees out of phase, but still to be aligned within the skew spec.The divided outputs offer a zero-delay divider for portions of the system that need the clock to be divided by either two or four, and still remain within a narrow skew of the “1X” clock.Without this feature, an external divider would need to be added, and the propagation delay of the divider would add to the skew between the different clock signals.These divided outputs, coupled with the Phase Locked Loop,allow the LVPSCB to multiply the clock rate at the REF input by either two or four. This mode will enable the designer to distribute a low-frequency clock between various portions of the system, and then locally multiply the clock rate to a more suitable frequency, while still maintaining the low-skew charac-teristics of the clock driver. The LVPSCB can perform all of the functions described above at the same time. It can multiply by two and four or divide by two (and four) at the same time that it is shifting its outputs over a wide range or maintaining zero skew between selected outputs.Figure 8 shows the CY7C9925 connected in series to construct a zero-skew clock distribution tree between boards.Delays of the downstream clock buffers can be programmed to compensate for the wire length (i.e., select negative skew equal to the wire delay) necessary to connect them to themaster clock source, approximating a zero-delay clock tree.Cascaded clock buffers will accumulate low-frequency jitter because of the non-ideal filtering characteristics of the PLL filter. It is recommended that not more than two clock buffers be connected in series.Figure 7. Multi-Function Clock DriverFigure 8. Board-to-Board Clock Distribution27.5-MHz DISTRIBUTIONCLOCK110-MHz INVERTEDZ 027.5-MHz110-MHz ZERO SKEW110-MHzSKEWED –2.273 ns (–4t U )FB REF FS 4F04F13F03F12F02F11F01F14Q04Q13Q03Q12Q02Q11Q01Q1TESTREFLOADLOADLOADLOADZ 0Z 0Z 0SYSTEM CLOCKZ 0L1L2L3L4FBREF FS 4F04F13F03F12F02F11F01F14Q04Q13Q03Q12Q02Q11Q01Q1TESTREF4F04F13F03F12F02F11F01F14Q04Q13Q03Q12Q02Q11Q01Q1REF FS FB LOADLOADLOADLOADLOADTESTZ 0Z 0Z 0Absolute Maximum ConditionsParameter Description Condition Min.Max.Unit V DD Supply Voltage Nonfunctional–0.5 4.6VDC V IN Input Voltage REF Relative to V CC–0.5 4.6VDC V IN Input Voltage Except REF Relative to V CC–0.5V DD + 0.5VDC LU I Latch-up Immunity Functional300mA T S Temperature, Storage Nonfunctional–65+125°C T A Temperature, Operating Ambient Commercial Temperature0+70°C T A Temperature, Operating Ambient Industrial Temperature–40+85°C T J Junction Temperature Industrial Temperature125°C ØJc Dissipation, Junction to Case Functional TBD°C/W ØJa Dissipation, Junction to Ambient Functional TBD°C/W ESD h ESD Protection (Human Body Model)2000V M SL Moisture Sensitivity Level MSL – 1Class G ATES Total Functional Gate Count Assembled Die TBD Each UL–94Flammability Rating@ 1/8 in.V–0class FIT Failure in Time Manufacturing test10ppm T PU Power-up time for all V DD s to reach0.05500msminimum specified voltage (power rampsmust be monotonic)C IN Input Capacitance[4]T A = 25°C, f = 1 MHz, V CC = 3.3V–10pF Z OUT Output Impedance Low to High (Rising edge)27ΩHigh to Low (Falling edge)7ΩElectrical Characteristics Over the Operating Range[5]Parameter Description Test Conditions Min.Max.V CCQ Core Power Supply@3.3V ± 10% 2.97 3.63V V CCN[1:4]Output Buffer Power Supply@3.3V ± 10% 2.97 3.63V@2.5V ± 5% 2.375 2.625V V OH Output HIGH Voltage V CC = Min., I OH = –20 mA (3.3V) 2.4–VV CC = Min., I OH = –15 mA (2.5V) 1.8–V OL Output LOW Voltage V CC = Min., I OL = 36 mA (3.3V)–0.45VV CC = Min., I OL = 20 mA (2.5V)–0.42.0V CC V V IH Input HIGH Voltage(REF and FB inputs only)[6]V IL Input LOW Voltage–0.50.8V (REF and FB inputs only)[6]Min. ≤ V CC≤ Max.0.87 * V CC V CC V V IHH Three-Level Input HIGHVoltage (Test, FS, xFn)[7]V IMM Three-Level Input MIDMin. ≤ V CC≤ Max.0.47 * V CC0.53 * V CC V Voltage (Test, FS, xFn)[7]Min. ≤ V CC≤ Max.0.00.13 * V CC V V ILL Three-Level Input LOWVoltage (Test, FS, xFn)[7]I IH Input HIGH Leakage CurrentV CC = Max., V IN = Max.–10µA (REF and FB inputs only)Notes:4.Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters.5.See the last page of this specification for Group A subgroup testing information.6.V IH and V IL for FB inputs guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect this parameters.I IL Input LOW Leakage Current(REF and FB inputs only)V CC = Max., V IN = 0.4V–10–µAI IHH Input HIGH Current(Test, FS, xFn)V IN = V CC–200µAI IMM Input MID Current(Test, FS, xFn)V IN = V CC/2–5050µAI ILL Input LOW Current(Test, FS, xFn)V IN = GND––200µA I OS Short Circuit Current[8]V CC = MAX, V OUT = GND (25° only)––200mAI CCQ Operating Current Used byInternal Circuitry V CCN = V CCQ = Max., All InputSelects Open–90mA–100I CCN Output Buffer Current perOutput Pair[9]V CCN = V CCQ = Max., I OUT = 0 mAInput Selects Open, f MAX–14mAPD Power Dissipation perOutput Pair[10]V CCN = V CCQ = Max., I OUT = 0 mAInput Selects Open, f MAX–78mWElectrical Characteristics Over the Operating Range (continued)[5]Parameter Description Test Conditions Min.Max.AC Test Loads and WaveformsAC Input SpecificationsParameter Description Condition Min.Max.UnitT R,T F Input Rise/Fall Edge Rate0.8V – 2.0V–10ns/VT PWC Input Clock Pulse HIGH or LOW2–nsT DCIN Input Duty Cycle PLL1090%Test Mode3070F REF Reference Input Frequency FS=LOW 3.7530MHzFS=MID 6.2550FS=HIGH10200[11]Notes:7.These inputs are normally wired to V CC, GND, or left unconnected (actual threshold voltages vary as a percentage of V CC). Internal termination resistors holdunconnected inputs at V CC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional t LOCK time before all data sheet limits are achieved.8.CY7C9925 should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only.9.Total output current per output pair can be approximated by the following expression that includes device current plus load current:CY7C9925:I CCN = [(4 + 0.11F) + [[((835 –3F)/Z) + (.0022FC)]N] x 1.1WhereF = frequency in MHzC = capacitive load in pFZ = line impedance in ohmsN = number of loaded outputs; 0, 1, or 2FC = F ∗ C10.Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power dissipation due to theload circuit:PD = [(22 + 0.61F) + [[(1550 + 2.7F)/Z) + (.0125FC)]N] x 1.1See note 9 for variable definition.11.In test mode, Max REF input frequency is 133MHz.Switching Characteristics Over the Operating Range[2, 12]Parameter Description Min.Typ.Max.Unitf NOM Operating ClockFrequency in MHz FS = LOW[1, 2]15–30MHz FS = MID[1, 2]25–50FS = HIGH[1, 2 ]40–200F OUT Output Frequency FS=LOW 3.75–30MHzFS=MID 6.25–50FS=HIGH10–200F VCO VCO Frequency160–800MHz F BW Loop Bandwidth–1–MHz t U Programmable Skew Unit See Table1t SKEWPR Zero Output Matched-Pair Skew (XQ0, XQ1)[13, 15]–0.050.1nst SKEW0Zero Output Skew (All Outputs)[13, 16,17]–0.10.2nst SKEW1Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)[13, 18]–0.250.3nst SKEW2Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)[13, 18]–0.30.5nst SKEW3Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)[13, 18]–0.250.5nst SKEW4Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)[13, 18]–0.50.9nst DEV Device-to-Device Skew[14, 19]––0.75nst PD Propagation Delay, REF Rise to FB Rise–0.15–+0.15nst ODCV3.3Output Duty Cycle Variation at 3.3V[20]47.55052.5%t ODCV2.5Output Duty Cycle Variation at 2.5V[20]455055%t PWH3.3Output HIGH Time Variation at 3.3V[21]47.55052.5%t PWH2.5Output HIGH Time Variation at 2.5V[21]455055%t PWL3.3Output LOW Time Variation at 3.3V[21]47.55052.5%t PWL2.5Output LOW Time Variation at 2.5V[21]455055%t ORISE Output Rise Time[21, 22]0.15 1.0 1.5nst OFALL Output Fall Time[21, 22]0.15 1.0 1.5nst LOCK PLL Lock Time[23]––0.5mst JR Cycle-to-Cycle Output Jitter RMS[14]––15psPeak-to-Peak[14]––100pst PJ Period Jitter RMS[14]––25psPeak-to-Peak[14]––150pst PHJ Phase Jitter Peak-to-Peak[14]––100ps Notes:12.Test measurement levels for the CY7C9925 are TTL levels (1.5V to 1.5V). T est conditions assume signal transition times of 2 ns or less and output loading as shownin the AC T est Loads and Waveforms unless otherwise specified.13.SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same t U delay has been selected when all areloaded with 30 pF and terminated with TTLAC T est Load.14.Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.15.t SKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0t U.16.t SKEW0 is defined as the skew between outputs when they are selected for 0t U. Other outputs are divided or inverted but not shifted.17.C L=0 pF. For C L=30 pF, t SKEW0=0.35 ns.18.There are three classes of outputs: Nominal (multiple of t U delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2or Divide-by-4 mode).19.t DEV is the output-to-output skew between any two devices operating under the same conditions (V CC ambient temperature, air flow, etc.)20.t ODCV is measure at V CCN/2.21.Specified with outputs loaded with 30 pF for the CY7C9925 devices. Devices are terminated through 50Ω to V CC/2.t PWH is measured at 2.0V. t PWL is measured at0.8V for 3.3V power supply. t PWH is measured at 1.7V. t PWL is measured at 0.7V for 2.5V power supply.22.t ORISE and t OFALL measured between 0.8V and 2.0V for 3.3V power supply. t ORISE and t OFALL measured between 0.7V and 1.7V for 2.5V power supply23.t LOCK is the time that is required before synchronization is achieved. This specification is valid only after V CC is stable and within normal operating limits. This parameter ismeasured from the application of a new signal or frequency at REF or FB until t PD is within specified limits.AC Timing DiagramsOrdering InformationOrdering Code Package TypeOperating RangeCY7C9925LFXC 32-QFN packageCommercial, 0°C to 70°C CY7C9925LFXT 32-QFN package - Tape and Reel Commercial,0°C to 70°C CY7C9925LFXI 32-QFN packageIndustrial, –40°C to 85°C CY7C9925LFXIT32-QFN package - Tape and ReelIndustrial, –40°C to 85°Ct ODCVt ODCVt REFREFFBQOTHER QINVERTED QREF DIVIDED BY 2REF DIVIDED BY 4t RPWHt RPWLt PDt SKEWPR,t SKEW0,1t SKEWPR,t SKEW0,1t SKEW2t SKEW2t SKEW3,4t SKEW3,4t SKEW3,4t SKEW1,3,4t SKEW2,4t JRPackage Drawing and Dimensions32-Lead QFN (5 x 5 mm) LF32A51-85188-**All product and company names mentioned in this document are trademarks of their respective holders.Document #: 38-07688 Rev. **Page 11 of 12© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.Document #: 38-07688 Rev. **Page 12 of 12Document History Page Document Title: CY7C9925 3.3V/2.5V Programmable Skew Clock Buffer Document Number: 38-07688REV.ECN NO.Issue Date Orig. of Change Description of Change **236309See ECN RGL New Data Sheet。

CY7C1338G-133AXC资料

PRELIMINARY4-Mbit (128K x 32) Flow-Through Sync SRAMCY7C1338GFeatures•128K X 32 common I/O•3.3V –5% and +10% core power supply (V DD)•2.5V or 3.3V I/O supply (V DDQ)•Fast clock-to-output times—6.5 ns (133-MHz version)—7.5 ns (117-MHz version)—8.0 ns (100-MHz version)•Provide high-performance 2-1-1-1 access rate •User-selectable burst counter supporting Intel®Pentium® interleaved or linear burst sequences •Separate processor and controller address strobes •Synchronous self-timed write•Asynchronous output enable•Lead-Free 100-pin TQFP and 119-ball BGA packages •“ZZ” Sleep Mode option Functional Description[1]The CY7C1338G is a 131,072 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automati-cally for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables(BW[A:D], and BWE), and Global Write (GW). Asynchronous i nputs include the Output Enable (OE) and the ZZ pin.The CY7C1338G allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV).The CY7C1338G operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.Note:1.For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on .Selection Guide133 MHz 117 MHz 100 MHz Unit Maximum Access Time6.57.58.0ns Maximum Operating Current 225220205mA Maximum Standby Current404040mAShaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.Pin Configurations100-Pin TQFPAAAAA 1A 0N C N CV S SV D DN C A AAAA ANC DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NC V DD DQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A NCNC DQ C DQ C V DDQ V SSQ DQ C DQ CDQ C DQ C V SSQ V DDQ DQ C DQ C NC V DD NC V SS DQ D DQ D V DDQ V SSQ DQ D DQ D DQ D DQ D V SSQ V DDQ DQ D DQ D NCAAC E 1C E 2B W DB W CB W BB W AC E 3V D DV S SC L KG WB W EO E A D S P A A123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495080797877767574737271706968676665646362616059585756555453525110099989796959493929190898887868584838281BYTE ABYTE CAA D V A D S C ZZ M O D E N C BYTE BDQ B BYTE DCY7C1338GPin DefinitionsName I/O DescriptionA0, A1, A Input-Synchronous Address Inputs used to select one of the 128K address location s. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1,CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter.BW A,BW B BW C,BW DInput-SynchronousByte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.Sampled on the rising edge of CLK.GW Input-Synchronous Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE).BWE Input-Synchronous Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write.CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation.CE1Input-Synchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH.CE1 is sampled only when a new external address is loaded.CE2Input-Synchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external address is loaded.CE3Input-Synchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. CE3 is sampled only when a new external address is loaded.OE Input-Asynchronous Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.ADV Input-Synchronous Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically increments the address in a burst cycle.Pin Configurations (continued)2345671A B C D E F G H J K L M N P R T U V DDQNCNCNCDQ CDQ DDQ CDQ DA A A AADSP V DDQ CE2ADQ CV DDQDQ CV DDQV DDQV DDQDQ DDQ DNCNCV DDQV DDCLKV DDV SSV SSV SSV SSV SSV SSV SSV SSNCNCNCNCNCNCNCNCNCNCNCV DDQV DDQV DDQA A AANCAAAAAAA0A1DQ A DQ CDQ ADQ ADQ ADQ BDQ BDQ BDQ BDQ BDQ BDQ BDQ ADQ ADQ ADQ ADQ BV DDDQ CDQ CDQ CV DDDQ DDQ DDQ DDQ DADSCNCCE1OEADVGWV SSV SSV SSV SSV SSV SSV SSV SS NCMODENCNCBW BBW CNC V DD NCBW ANCBWEBW DZZ119-Ball BGAFunctional OverviewAll synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t C0) is 6.5 ns (133-MHz device).The CY7C1338G supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium ® and i486™processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user-selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access.Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW [A:D]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry.Three synchronous Chip Selects (CE 1, CE 2, CE 3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE 1is HIGH.Single Read AccessesA single read access is initiated when the following conditions are satisfied at clock rise: (1) CE 1, CE 2, and CE 3 are all asserted active, and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter/control logic and presented to the memory core.If the OE input is asserted LOW, the requested data will be available at the data outputs a maximum to t CDV after clock rise. ADSP is ignored if CE 1 is HIGH.Single Write Accesses Initiated by ADSPThis access is initiated when the following conditions are satisfied at clock rise: (1) CE 1, CE 2, CE 3 are all asserted active, and (2) ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst inputs (GW, BWE, and BW[A:D ])are ignored during this first clock cycle. If the write inputs are asserted active (see Write Cycle Descriptions table for appropriate states that indicate a write) on the next clock rise, the appropriate data will be latched and written into the device. Byte writes are allowed.During byte writes, BW A controls DQ A and BWB controls DQ B .BWC controls DQ C , and BW D controls DQ D . All I/Os are tri-stated during a byte write.Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be tri-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of OE.ADSPInput-Synchronous Address Strobe from Processor, sampled on the rising edge of CLK, active LOW . Whenasserted LOW, addresses presented to the device are captured in the address registers. A [1:0] arealso loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog-nized. ASDP is ignored when CE 1 is deasserted HIGHADSC Input-Synchronous Address Strobe from Controller, sampled on the rising edge of CLK, active LOW . When assertedLOW, addresses presented to the device are captured in the address registers. A [1:0] are also loadedinto the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.ZZInput-Asynchronous ZZ “sleep” Input, active HIGH . When asserted HIGH places the device in a non-time-critical “sleep”condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating.ZZ pin has an internal pull-down.DQsI/O-Synchronous Bidirectional Data I/O lines . As inputs, they feed into an on-chip data register that is triggered bythe rising edge of CLK. As outputs, they deliver the data contained in the memory location specifiedby the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE . When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs are placed in a tri-state condition.V DD Power Supply Power supply inputs to the core of the device .V SS GroundGround for the core of the device .V DDQ I/O Power SupplyPower supply for the I/O circuitry . V SSQ I/O Ground Ground for the I/O circuitry . MODEInput-StaticSelects Burst Order . When tied to GND selects linear burst sequence. When tied to V DD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up.NCNo Connects . Not Internally connected to the die.Pin Definitions (continued)Name I/ODescriptionSingle Write Accesses Initiated by ADSCThis write access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, (2) ADSC is asserted LOW, (3) ADSP is deasserted HIGH, and (4) the write input signals (GW, BWE, and BW[A:D]) indicate a write access. ADSC is ignored if ADSP is active LOW.The addresses presented are loaded into the address register and the burst counter/control logic and delivered to the memory core. The information presented to DQ[A:D] will be written into the specified address location. Byte writes are allowed. During byte writes, BW A controls DQ A, BW B controls DQ B, BW C controls DQ C, and BW D controls DQ D. All I/Os are tri-stated when a write is detected, even a byte write. Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be tri-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of OE.Burst SequencesThe CY7C1338G provides an on-chip two-bit wraparound burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input.A LOW on MODE will select a linear burst sequence. A HIGH on MODE will select an interleaved burst order. Leaving MODE unconnected will cause the device to default to a inter-leaved burst sequence.Sleep ModeThe ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep”mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CEs, ADSP, and ADSC must remain inactive for the duration of t ZZREC after the ZZ input returns LOW.Interleaved Burst Address Table(MODE = Floating or V DD)FirstAddressA1, A0SecondAddressA1, A0ThirdAddressA1, A0FourthAddressA1, A0 00011011010011101011000111100100 Linear Burst Address Table (MODE = GND) FirstAddressA1,A0SecondAddressA1,A0ThirdAddressA1,A0FourthAddressA1,A0 00011011011011001011000111000110ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min.Max.Unit I DDZZ Snooze mode standby current ZZ > V DD– 0.2V40mA t ZZS Device operation to ZZ ZZ > V DD – 0.2V2t CYC ns t ZZREC ZZ recovery time ZZ < 0.2V2t CYC ns t ZZI ZZ active to snooze current This parameter is sampled2t CYC ns t RZZI ZZ Inactive to exit snooze current This parameter is sampled0nsTruth Table[2, 3, 4, 5, 6]Cycle Description AddressUsed CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQDeselected Cycle, Power-down None H X X L X L X X X L-H tri-state Deselected Cycle, Power-down None L L X L L X X X X L-H tri-state Deselected Cycle, Power-down None L X H L L X X X X L-H tri-state Deselected Cycle, Power-down None L L X L H L X X X L-H tri-state Deselected Cycle, Power-down None X X X L H L X X X L-H tri-state Snooze Mode, Power-down None X X X H X X X X X X tri-state Read Cycle, Begin Burst External L H L L L X X X L L-H QRead Cycle, Begin Burst External L H L L L X X X H L-H tri-state Write Cycle, Begin Burst External L H L L H L X L X L-H DRead Cycle, Begin Burst External L H L L H L X H L L-H QRead Cycle, Begin Burst External L H L L H L X H H L-H tri-state Read Cycle, Continue Burst Next X X X L H H L H L L-H QRead Cycle, Continue Burst Next X X X L H H L H H L-H tri-state Read Cycle, Continue Burst Next H X X L X H L H L L-H QRead Cycle, Continue Burst Next H X X L X H L H H L-H tri-state Write Cycle, Continue Burst Next X X X L H H L L X L-H DWrite Cycle, Continue Burst Next H X X L X H L L X L-H DRead Cycle, Suspend Burst Current X X X L H H H H L L-H QRead Cycle, Suspend Burst Current X X X L H H H H H L-H tri-state Read Cycle, Suspend Burst Current H X X L X H H H L L-H QRead Cycle, Suspend Burst Current H X X L X H H H H L-H tri-state Write Cycle, Suspend Burst Current X X X L H H H L X L-H DWrite Cycle, Suspend Burst Current H X X L X H H L X L-H D Notes:2.X = “Don't Care.” H = Logic HIGH, L = Logic LOW.3.WRITE = L when any one or more Byte Write enable signals (BW A, BW B, BW C, BW D) and BWE = L or GW= L. WRITE = H when all Byte write enable signalsA B C D4.The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.5.The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW X. Writes may occur only on subsequent clocksafter the or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle.6.OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE isinactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).Partial Truth Table for Read/Write[2, 7]Function GW BWE BW D BW C BW B BW A Read H H X X X X Read H L H H H H Write Byte A H L H H H L Write Byte B H L H H L H Write Bytes B, A H L H H L L Write Byte C H L H L H H Write Bytes C, A H L H L H L Write Bytes C, B H L H L L H Write Bytes C, B, A H L H L L L Write Byte D H L L H H H Write Bytes D, A H L L H H L Write Bytes D, B H L L H L H Write Bytes D, B, A H L L H L L Write Bytes D, B H L L L H H Write Bytes D, B, A H L L L H L Write Bytes D,C,A H L L L L H Write All Bytes H L L L L L Write All Bytes L X X X X X Note:7.Table only lists a partial listing of the byte write combinations. Any combination of BW X is valid. Appropriate write will be done based on which byte write is active.Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not tested.)Storage Temperature .................................–65°C to +150°C Ambient Temperature withPower Applied.............................................–55°C to +125°C Supply Voltage on V DD Relative to GND........–0.5V to +4.6V DC Voltage Applied to Outputsin tri-state............................................–0.5V to V DDQ + 0.5V DC Input Voltage....................................–0.5V to V DD + 0.5V Current into Outputs (LOW).........................................20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015)Latch-up Current..................................................... >200 mA Operating RangeRangeAmbientTemperature]V DD V DDQ Commercial0°C to +70°C 3.3V −5%/+10% 2.5V –5%to V DD Industrial–40°C to +85°CElectrical Characteristics Over the Operating Range[8, 9]Parameter Description Test ConditionsCY7C1338GUnit Min.Max.V DD Power Supply Voltage 3.135 3.6V V DDQ I/O Supply Voltage 2.375V DD V V OH Output HIGH Voltage V DDQ = 3.3V, V DD = Min., I OH = –4.0 mA 2.4VV DDQ = 2.5V, V DD = Min., I OH = –1.0 mA 2.0V V OL Output LOW Voltage V DDQ = 3.3V, V DD = Min., I OL = 8.0 mA0.4VV DDQ = 2.5V, V DD = Min., I OL = 1.0 mA0.4V V IH Input HIGH Voltage V DDQ = 3.3V 2.0V DD + 0.3V VV DDQ = 2.5V 1.7V DD + 0.3V V V IL Input LOW Voltage[8]V DDQ = 3.3V–0.30.8VV DDQ = 2.5V–0.30.7V I X Input Load Current (except ZZ andMODE)GND ≤ V I≤ V DDQ−55µA Input Current of MODE Input = V SS–30µAInput = V DD5µA Input Current of ZZ Input = V SS–5µAInput = V DD30µA I OZ Output Leakage Current GND ≤ V I≤ V DD, Output Disabled–55µA I OS Output Short Circuit Current V DD = Max., V OUT = GND–300µAI DD V DD Operating Supply Current V DD = Max., I OUT = 0 mA,f = f MAX= 1/t CYC 7.5-ns cycle, 133 MHz225mA8.0-ns cycle, 117 MHz220mA 10-ns cycle, 100 MHz205mAI SB1Automatic CE Power-DownCurrent—TTL Inputs Max. V DD, Device Deselected,V IN≥ V IH or V IN≤ V IL, f = f MAX,inputs switching7.5-ns cycle, 133 MHz90mA8.0-ns cycle, 117 MHz85mA10-ns cycle, 100 MHz80mAI SB2Automatic CE Power-DownCurrent—CMOS Inputs Max. V DD, Device Deselected,V IN≥ V DD – 0.3V or V IN≤ 0.3V,f = 0, inputs staticAll speeds40mAI SB3Automatic CE Power-DownCurrent—CMOS Inputs Max. V DD, Device Deselected,V IN≥V DDQ – 0.3V or V IN≤ 0.3V,f = f MAX, inputs switching7.5-ns cycle, 133 MHz75mA8.0-ns cycle, 117 MHz70mA10-ns cycle, 100 MHz65mAI SB4Automatic CE Power-DownCurrent—TTL Inputs Max. V DD, Device Deselected,V IN≥ V DD – 0.3V or V IN≤ 0.3V,f=0, inputs staticAll speeds45mAShaded areas contain advance information.Notes:8.Overshoot: V IH(AC) < V DD +1.5V (Pulse width less than t CYC/2), undershoot: V IL(AC) > -2V (Pulse width less than t CYC/2).9.TPower-up: Assumes a linear ramp from 0v to V DD(min.) within 200ms. During this time V IH < V DD and V DDQ < V DD.Thermal Resistance [10]Parameter DescriptionTest ConditionsTQFP PackageBGA PackageUnit ΘJAThermal Resistance (Junction to Ambient)Test conditions follow standard test methods and procedures formeasuring thermal impedance, per EIA / JESD51.TBD TBD °C/W ΘJC Thermal Resistance(Junction to Case)TBDTBD°C/WCapacitance [10]Parameter DescriptionTest Conditions TQFP PackageBGA Package UnitC IN Input Capacitance T A = 25°C, f = 1 MHz,V DD = 3.3V. V DDQ = 3.3V55pF C CLK Clock Input Capacitance 55pF C I/OInput/Output Capacitance57pFAC Test Loads and WaveformsSwitching Characteristics Over the Operating Range [11, 12, 13, 14, 15, 16]Parameter Description133 MHz117 MHz 100 MHz Unit Min.Max.Min.Max.Min.Max.t POWER V DD (Typical) to the first Access [11]111msClock t CYC Clock Cycle Time 7.58.510ns t CH Clock HIGH 2.5 3.0 4.0ns t CLClock LOW2.53.04.0nsOutput Times t CDV Data Output Valid After CLK Rise 6.57.58.0ns t DOHData Output Hold After CLK Rise2.02.02.0nsShaded areas contain advance information.Notes:10.Tested initially and after any design or process change that may affect these parameters.11.This part has a voltage regulator internally; t POWER is the time that the power needs to be supplied above V DD (minimum) initially before a read or write operationcan be initiated.12.t CHZ , t CLZ ,t OELZ , and t OEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.13.At any given voltage and temperature, t OEHZ is less than t OELZ and t CHZ is less than t CLZ to eliminate bus contention between SRAMs when sharing the samedata bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions.14.This parameter is sampled and not 100% tested.15.Timing reference level is 1.5V when V DDQ = 3.3V and is 1.25V when V DDQ = 2.5V.16.Test conditions shown in (a) of AC Test Loads unless otherwise noted.OUTPUTR = 317ΩR = 351Ω5pFINCLUDING JIG AND SCOPE (a)(b)OUTPUTR L = 50ΩZ 0= 50ΩV T = 1.5V3.3VALL INPUT PULSESV DDQ GND90%10%90%10%≤1ns≤1ns(c)OUTPUTR = 1667ΩR =1538Ω5pFINCLUDING JIG AND SCOPE(a)(b)OUTPUTR L = 50ΩZ 0= 50ΩV T = 1.25V2.5VALL INPUT PULSES V DDQGND90%10%90%10%≤1ns≤1ns(c)3.3V I/O Test Load2.5V I/O Test Loadt CLZ Clock to Low-Z [12, 13, 14]0ns t CHZ Clock to High-Z [12, 13, 14] 3.5 3.5 3.5ns t OEV OE LOW to Output Valid3.53.5 3.5ns t OELZ OE LOW to Output Low-Z [12, 13, 14]0ns t OEHZOE HIGH to Output High-Z [12, 13, 14]3.53.53.5ns Setup Times t AS Address Set-up Before CLK Rise 1.5 2.0 2.0ns t ADS ADSP , ADSC Set-up Before CLK Rise 1.5 2.0 2.0ns t ADVS ADV Set-up Before CLK Rise1.52.0 2.0ns t WES GW, BWE, BW X Set-up Before CLK Rise 1.5 2.0 2.0ns t DS Data Input Set-up Before CLK Rise 1.5 1.5 1.5ns t CESChip Enable Set-up1.52.02.0ns Hold Times t AH Address Hold After CLK Rise 0.50.50.5ns t ADH ADSP , ADSC Hold After CLK Rise 0.50.50.5ns t WEH GW ,BWE , BW X Hold After CLK Rise 0.50.50.5ns t ADVH ADV Hold After CLK Rise 0.50.50.5ns t DH Data Input Hold After CLK Rise 0.50.50.5ns t CEHChip Enable Hold After CLK Rise0.50.50.5nsSwitching Characteristics Over the Operating Range (continued)[11, 12, 13, 14, 15, 16]Parameter Description133 MHz117 MHz 100 MHz Unit Min.Max.Min.Max.Min.Max.Timing Diagrams[17]Timing Diagrams (continued)[17, 18]Timing Diagrams (continued)[17, 19, 20]ZZ Mode Timing [21, 22]Ordering InformationSpeed (MHz)Ordering Code Package Name Package TypeOperating Range 133CY7C1338G-133AXC A101Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm)CommercialCY7C1338G-133BGC BG119119-Ball PBGA (14 x 22 x 2.4mm)CY7C1338G-133BGXC BG119Lead-Free 119-Ball PBGA (14 x 22 x 2.4mm)CY7C1338G-133AXI A101Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm)Industrial CY7C1338G-133BGI BG119119-Ball PBGA (14 x 22 x 2.4mm)CY7C1338G-133BGXIBG119Lead-Free 119-Ball PBGA (14 x 22 x 2.4mm)117CY7C1338G-117AXC A101Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm)Commercial CY7C1338G-117BGC BG119119-Ball PBGA (14 x 22 x 2.4mm)CY7C1338G-117BGXCBG119Lead-Free 119-Ball PBGA (14 x 22 x 2.4mm)CY7C1338G-117AXI A101Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm)Industrial CY7C1338G-117BGI BG119119-Ball PBGA (14 x 22 x 2.4mm)CY7C1338G-117BGXIBG119Lead-Free 119-Ball PBGA (14 x 22 x 2.4mm)100CY7C1338G-100AXC A101Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm)Commercial CY7C1338G-100BGC BG119119-Ball PBGA (14 x 22 x 2.4mm)CY7C1338G-100BGXC BG119Lead-Free 119-Ball PBGA (14 x 22 x 2.4mm)CY7C1338G-100AXI A101Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm)Industrial CY7C1338G-100BGI BG119119-Ball PBGA (14 x 22 x 2.4mm)CY7C1338G-100BGXIBG119Lead-Free 119-Ball PBGA (14 x 22 x 2.4mm)Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Lead-Free BGX package will be available in 2005.Notes:21.Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.22.DQs are in high-Z when exiting ZZ sleep mode.Timing Diagrams (continued)Package DiagramsDocument #: 38-05521 Rev. *A Page 16 of 17Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.Package Diagrams(continued)Document History PageDocument Title: CY7C1338G 4-Mbit (128K x 32) Flow-Through Sync SRAM Document Number: 38-05521REV.ECN NO.Issue Date Orig. ofChange Description of Change**224369See ECN RKF New data sheet*A278513See ECN VBL Deleted 66 MHzChanged TQFP to PB-Free TQFP in Ordering Info sectionAdded PB-Free BG package。

CY7C63723-PC中文资料

元器件交易网CY7C63743CY7C63722/23CY7C63743enCoRe™ USBCombination Low-Speed USB & PS/2Peripheral ControllerTABLE OF CONTENTS1.0 FEATURES (5)2.0 FUNCTIONAL OVERVIEW (6)2.1 enCoRe USB - The New USB Standard (6)3.0 LOGIC BLOCK DIAGRAM (7)4.0 PIN CONFIGURATIONS (7)5.0 PIN ASSIGNMENTS (7)6.0 PROGRAMMING MODEL (8)6.1 Program Counter (PC) (8)6.2 8-bit Accumulator (A) (8)6.3 8-bit Index Register (X) (8)6.4 8-bit Program Stack Pointer (PSP) (8)6.5 8-bit Data Stack Pointer (DSP) (9)6.6 Address Modes (9)6.6.1 Data (9)6.6.2 Direct (9)6.6.3 Indexed (9)7.0 INSTRUCTION SET SUMMARY (10)8.0 MEMORY ORGANIZATION (11)8.1 Program Memory Organization (11)8.2 Data Memory Organization (12)8.3 I/O Register Summary (13)9.0 CLOCKING (14)9.1 Internal/External Oscillator Operation (15)9.2 External Oscillator (16)10.0 RESET (16)10.1 Low-voltage Reset (LVR) (16)10.2 Brown Out Reset (BOR) (16)10.3 Watchdog Reset (WDR) (17)11.0 SUSPEND MODE (17)11.1 Clocking Mode on Wake-up from Suspend (18)11.2 Wake-up Timer (18)12.0 GENERAL PURPOSE I/O PORTS (18)12.1 Auxiliary Input Port (21)13.0 USB SERIAL INTERFACE ENGINE (SIE) (22)13.1 USB Enumeration (22)13.2 USB Port Status and Control (22)14.0 USB DEVICE (24)14.1 USB Address Register (24)14.2 USB Control Endpoint (24)14.3 USB Non-control Endpoints (25)14.4 USB Endpoint Counter Registers (26)15.0 USB REGULATOR OUTPUT (27)16.0 PS/2 OPERATION (27)17.0 SERIAL PERIPHERAL INTERFACE (SPI) (28)17.1 Operation as an SPI Master (29)17.2 Master SCK Selection (29)17.3 Operation as an SPI Slave (29)17.4 SPI Status and Control (30)17.5 SPI Interrupt (31)17.6 SPI Modes for GPIO Pins (31)18.0 12-BIT FREE-RUNNING TIMER (31)19.0 TIMER CAPTURE REGISTERS (32)20.0 PROCESSOR STATUS AND CONTROL REGISTER (35)21.0 INTERRUPTS (36)21.1 Interrupt Vectors (37)21.2 Interrupt Latency (37)21.3 Interrupt Sources (37)22.0 USB MODE TABLES (42)23.0 REGISTER SUMMARY (47)24.0 ABSOLUTE MAXIMUM RATINGS (48)25.0 DC CHARACTERISTICS (48)26.0 SWITCHING CHARACTERISTICS (50)27.0 ORDERING INFORMATION (55)28.0 PACKAGE DIAGRAMS (55)LIST OF FIGURESFigure 8-1. Program Memory Space with Interrupt Vector Table (11)Figure 8-2. Data Memory Organization (12)Figure 9-1. Clock Oscillator On-chip Circuit (14)Figure 9-2. Clock Configuration Register (Address 0xF8) (14)Figure 10-1. Watchdog Reset (WDR, Address 0x26) (17)Figure 12-1. Block Diagram of GPIO Port (one pin shown) (19)Figure 12-2. Port 0 Data (Address 0x00) (19)Figure 12-3. Port 1 Data (Address 0x01) (19)Figure 12-4. GPIO Port 0 Mode0 Register (Address 0x0A) (20)Figure 12-5. GPIO Port 0 Mode1 Register (Address 0x0B) (20)Figure 12-6. GPIO Port 1 Mode0 Register (Address 0x0C) (20)Figure 12-7. GPIO Port 1 Mode1 Register (Address 0x0D) (20)Figure 12-8. Port 2 Data Register (Address 0x02) (21)Figure 13-1. USB Status and Control Register (Address 0x1F) (23)Figure 14-1. USB Device Address Register (Address 0x10) (24)Figure 14-2. Endpoint 0 Mode Register (Address 0x12) (25)Figure 14-3. USB Endpoint EP1, EP2 Mode Registers (Addresses 0x14 and 0x16) (26)Figure 14-4. Endpoint 0,1,2 Counter Registers (Addresses 0x11, 0x13 and 0x15) (26)Figure 17-1. SPI Block Diagram (28)Figure 16-1. Diagram of USB-PS/2 System Connections (28)Figure 17-2. SPI Data Register (Address 0x60) (29)Figure 17-3. SPI Control Register (Address 0x61) (30)Figure 17-4. SPI Data Timing (31)Figure 18-1. Timer LSB Register (Address 0x24) (31)Figure 18-2. Timer MSB Register (Address 0x25) (32)Figure 18-3. Timer Block Diagram (32)Figure 19-1. Capture Timers Block Diagram (33)Figure 19-2. Capture Timer A-Rising, Data Register (Address 0x40) (33)Figure 19-3. Capture Timer A-Falling, Data Register (Address 0x41) (34)Figure 19-4. Capture Timer B-Rising, Data Register (Address 0x42) (34)Figure 19-5. Capture Timer B-Falling, Data Register (Address 0x43) (34)Figure 19-6. Capture Timer Status Register (Address 0x45) (34)Figure 19-7. Capture Timer Configuration Register (Address 0x44) (34)Figure 20-1. Processor Status and Control Register (Address 0xFF) (35)Figure 21-1. Global Interrupt Enable Register (Address 0x20) (38)Figure 21-2. Endpoint Interrupt Enable Register (Address 0x21) (39)Figure 21-3. Interrupt Controller Logic Block Diagram (40)Figure 21-4. Port 0 Interrupt Enable Register (Address 0x04) (40)Figure 21-5. Port 1 Interrupt Enable Register (Address 0x05) (40)Figure 21-6. Port 0 Interrupt Polarity Register (Address 0x06) (41)Figure 21-7. Port 1 Interrupt Polarity Register (Address 0x07) (41)Figure 21-8. GPIO Interrupt Diagram (41)Figure 26-1. Clock Timing (51)Figure 26-2. USB Data Signal Timing (51)Figure 26-3. Receiver Jitter Tolerance (52)Figure 26-4. Differential to EOP Transition Skew and EOP Width (52)Figure 26-5. Differential Data Jitter (52)Figure 26-7. SPI Slave Timing, CPHA = 0 (53)Figure 26-6. SPI Master Timing, CPHA = 0 (53)Figure 26-8. SPI Master Timing, CPHA = 1 (54)Figure 26-9. SPI Slave Timing, CPHA = 1 (54)LIST OF TABLESTable 8-1. I/O Register Summary (13)Table 11-1. Wake-up Timer Adjust Settings (18)Table 12-1. Ports 0 and 1 Output Control Truth Table (21)Table 13-1. Control Modes to Force D+/D– Outputs (24)Table 17-1. SPI Pin Assignments (31)Table 19-1. Capture Timer Prescalar Settings (Step size and range for FCLK = 6 MHz) (35)Table 21-1. Interrupt Vector Assignments (37)Table 22-1. USB Register Mode Encoding for Control and Non-Control Endpoints (42)Table 22-2. Decode table for Table 22-3: “Details of Modes for Differing Traffic Conditions” (44)Table 22-3. Details of Modes for Differing Traffic Conditions (45)Table 28-1. CY7C63722-XC Probe Pad Coordinates in microns ((0,0) to bond pad centers) (57)1.0 Features•enCoRe™ USB - enhanced Component Reduction—Internal oscillator eliminates the need for an external crystal or resonator—Interface can auto-configure to operate as PS/2 or USB without the need for external components to switch between modes (no GPIO pins needed to manage dual mode capability)—Internal 3.3V regulator for USB pull-up resistor—Configurable GPIO for real-world interface without external components•Flexible, cost-effective solution for applications that combine PS/2 and low-speed USB, such as mice, gamepads, joysticks, and many others.•USB Specification Compliance—Conforms to USB Specification, Version 2.0—Conforms to USB HID Specification, Version 1.1—Supports 1 Low-Speed USB device address and 3 data endpoints—Integrated USB transceiver—3.3V regulated output for USB pull-up resistor•8-bit RISC microcontroller—Harvard architecture—6-MHz external ceramic resonator or internal clock mode—12-MHz internal CPU clock—Internal memory—256 bytes of RAM—8 Kbytes of EPROM—Interface can auto-configure to operate as PS/2 or USB—No external components for switching between PS/2 and USB modes—No GPIO pins needed to manage dual mode capability•I/O ports—Up to 16 versatile General Purpose I/O (GPIO) pins, individually configurable—High current drive on any GPIO pin: 50 mA/pin current sink—Each GPIO pin supports high-impedance inputs, internal pull-ups, open drain outputs or traditional CMOS outputs —Maskable interrupts on all I/O pins•SPI serial communication block—Master or slave operation—2 Mbit/s transfers•Four 8-bit Input Capture registers—Two registers each for two input pins—Capture timer setting with 5 prescaler settings—Separate registers for rising and falling edge capture—Simplifies interface to RF inputs for wireless applications•Internal low-power wake-up timer during suspend mode—Periodic wake-up with no external components•Optional 6-MHz internal oscillator mode—Allows fast start-up from suspend mode•Watchdog Reset (WDR)•Low-voltage Reset at 3.75V•Internal brown-out reset for suspend mode•Improved output drivers to reduce EMI•Operating voltage from 4.0V to 5.5VDC•Operating temperature from 0 to 70 degrees Celsius•CY7C63723 available in 18-pin SOIC, 18-pin PDIP•CY7C63743 available in 24-pin SOIC, 24-pin PDIP•CY7C63722 available in DIE form•Industry standard programmer support2.0 Functional Overview2.1enCoRe USB - The New USB StandardCypress has re-invented its leadership position in the low-speed USB market with a new family of innovative microcontrollers. Introducing...enCoRe USB—“enhanced Component Reduction.” Cypress has leveraged its design expertise in USB solutions to create a new family of low-speed USB microcontrollers that enables peripheral developers to design new products with a minimum number of components. At the heart of the enCoRe USB technology is the breakthrough design of a crystal-less oscillator. By integrating the oscillator into our chip, an external crystal or resonator is no longer needed. We have also integrated other external components commonly found in low-speed USB applications such as pull-up resistors, wake-up circuitry, and a 3.3V regulator. All of this adds up to a lower system cost.The CY7C637xx is an 8-bit RISC One Time Programmable (OTP) microcontroller. The instruction set has been optimized specif-ically for USB and PS/2 operations, although the microcontrollers can be used for a variety of other embedded applications. The CY7C637xx features up to 16 general purpose I/O (GPIO) pins to support USB, PS/2 and other applications. The I/O pins are grouped into two ports (Port 0 to 1) where each pin can be individually configured as inputs with internal pull-ups, open drain outputs, or traditional CMOS outputs with programmable drive strength of up to 50 mA output drive. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Note the GPIO interrupts all share the same “GPIO” interrupt vector. The CY7C637xx microcontrollers feature an internal oscillator. With the presence of USB traffic, the internal oscillator can be set to precisely tune to USB timing requirements (6 MHz ±1.5%). Optionally, an external 6-MHz ceramic resonator can be used to provide a higher precision reference for USB operation. This clock generator reduces the clock-related noise emissions (EMI). The clock generator provides the 6- and 12-MHz clocks that remain internal to the microcontroller.The CY7C637xx has 8 Kbytes of EPROM and 256 bytes of data RAM for stack space, user variables, and USB FIFOs.These parts include low-voltage reset logic, a watchdog timer, a vectored interrupt controller, a 12-bit free-running timer, and capture timers. The low-voltage reset (LVR) logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at EPROM address 0x0000. LVR will also reset the part when V CC drops below the operating voltage range. The watchdog timer can be used to ensure the firmware never gets stalled for more than approximately 8 ms. The microcontroller supports 10 maskable interrupts in the vectored interrupt controller. Interrupt sources include the USB Bus-Reset, the 128-µs and 1.024-ms outputs from the free-running timer, three USB endpoints, two capture timers, an internal wake-up timer and the GPIO ports. The timers bits cause periodic interrupts when enabled. The USB endpoints interrupt after USB transactions complete on the bus. The capture timers interrupt whenever a new timer value is saved due to a selected GPIO edge event. The GPIO ports have a level of masking to select which GPIO inputs can cause a GPIO interrupt. For additional flexibility, the input transition polarity that causes an interrupt is programmable for each GPIO pin. The interrupt polarity can be either rising or falling edge.The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources as noted above (128 µs and 1.024 ms). The timer can be used to measure the duration of an event under firmware control by reading the timer at the start and end of an event, and subtracting the two values. The four capture timers save a programmable 8 bit range of the free-running timer when a GPIO edge occurs on the two capture pins (P0.0, P0.1).The CY7C637xx includes an integrated USB serial interface engine (SIE) that supports the integrated peripherals. The hardware supports one USB device address with three endpoints. The SIE allows the USB host to communicate with the function integrated into the microcontroller. A 3.3V regulated output pin provides a pull-up source for the external USB resistor on the D– pin.The USB D+ and D– USB pins can alternately be used as PS/2 SCLK and SDATA signals, so that products can be designed to respond to either USB or PS/2 modes of operation. PS/2 operation is supported with internal pull-up resistors on SCLK and SDATA, the ability to disable the regulator output pin, and an interrupt to signal the start of PS/2 activity. No external components are necessary for dual USB and PS/2 systems, and no GPIO pins need to be dedicated to switching between modes. Slow edge rates operate in both modes to reduce EMI.3.0 Logic Block Diagram4.0 Pin Configurations5.0 Pin AssignmentsNameI/O CY7C63723CY7C63743CY7C63722Description18-Pin 24-Pin 25-Pad D–/SDATA,D+/SCLK I/O 121315161617USB differential data lines (D– and D+), or PS/2 clock and data signals (SDATA and SCLK)P0[7:0]I/O1, 2, 3, 4,15, 16, 17, 181, 2, 3, 4,21, 22, 23, 241, 2, 3, 4,22, 23, 24, 25GPIO Port 0 capable of sinking up to 50 mA/pin, or sinking controlled low or high programmable current.Can also source 2 mA current, provide a resistive pull-up, or serve as a high-impedance input. P0.0 and P0.1 provide inputs to Capture Timers A and B, respec-tively.P1[7:0]I/O5, 145, 6, 7, 8,17, 18, 19, 205, 6, 7, 8,18, 19, 20, 21IO Port 1 capable of sinking up to 50 mA/pin, or sinking controlled low or high programmable current. Can alsosource 2 mA current, provide a resistive pull-up, or serve as a high-impedance input.Wake-Up 12-bit Timer USB &D+,D–P1.0–P1.7Interrupt ControllerPort 0P0.0–P0.7GPIO8-bit RISC Xtal RAM 256 Byte EPROM 8K ByteCoreBrown-out Reset XcvrWatch Timer Dog 3.3V Port 1GPIO Capture TimersUSB Engine PS/2Internal Oscillator Oscillator Low ResetVoltage RegulatorTimerSPIXTALOUTXTALIN/P2.1VREG/P2.01234569111516171819202221P0.0P0.1P0.2P0.3P1.0P1.2VSS VREG/P2.0P0.6P1.5P1.1P1.3D+/SCLK P1.7D–/SDATA VCC14P0.710VPPXTALIN/P2.1XTALOUT121378P1.4P1.62423P0.4P0.524-pin SOIC/PDIPCY7C6374312346781011121315161817P0.0P0.1P0.2P0.3VSS VREG/P2.0P0.4P0.6P0.7D+/SCLK D–/SDATA VCC18-pin SOIC/PDIPP0.59VPPXTALIN/P2.1XTALOUTCY7C63723514P1.0P1.1Top View4 5 6 7 8 93 P 0.21 P 0.0 2 P 0.125 P 0.4 24 P 0.523 P 0.622 21 20 19 1811121314151617P0.3P1.0P1.2P1.4P1.6 VSS VSS V P P X T A L I N /P 2.1V R E G X T A L O U T V C C D -/S D A T A D+/SCLK P0.7P1.1P1.3P1.5P1.7CY7C63722-XCDIE106.0 Programming ModelRefer to the CYASM Assembler User’s Guide for more details on firmware operation with the CY7C637xx microcontrollers.6.1Program Counter (PC)The 14-bit program counter (PC) allows access for up to 8 Kbytes of EPROM using the CY7C637xx architecture. The program counter is cleared during reset, such that the first instruction executed after a reset is at address 0x0000. This instruction is typically a jump instruction to a reset handler that initializes the application.The lower 8 bits of the program counter are incremented as instructions are loaded and executed. The upper 6 bits of the program counter are incremented by executing an XPAGE instruction. As a result, the last instruction executed within a 256-byte “page”of sequential code should be an XPAGE instruction. The assembler directive “XPAGEON” will cause the assembler to insert XPAGE instructions automatically. As instructions can be either one or two bytes long, the assembler may occasionally need to insert a NOP followed by an XPAGE for correct execution.The program counter of the next instruction to be executed, carry flag, and zero flag are saved as two bytes on the program stack during an interrupt acknowledge or a CALL instruction. The program counter, carry flag, and zero flag are restored from the program stack only during a RETI instruction.Please note the program counter cannot be accessed directly by the firmware. The program stack can be examined by reading SRAM from location 0x00 and up.6.28-bit Accumulator (A)The accumulator is the general-purpose, do everything register in the architecture where results are usually calculated.6.38-bit Index Register (X)The index register “X” is available to the firmware as an auxiliary accumulator. The X register also allows the processor to perform indexed operations by loading an index value into X.6.48-bit Program Stack Pointer (PSP)During a reset, the program stack pointer (PSP) is set to zero. This means the program “stack” starts at RAM address 0x00 and “grows” upward from there. Note that the program stack pointer is directly addressable under firmware control, using the MOV PSP ,A instruction. The PSP supports interrupt service under hardware control and CALL, RET, and RETI instructions under firmware control.During an interrupt acknowledge, interrupts are disabled and the program counter, carry flag, and zero flag are written as two bytes of data memory. The first byte is stored in the memory addressed by the program stack pointer, then the PSP is incremented.The second byte is stored in memory addressed by the program stack pointer and the PSP is incremented again. The net effect is to store the program counter and flags on the program “stack” and increment the program stack pointer by two.The return from interrupt (RETI) instruction decrements the program stack pointer, then restores the second byte from memory addressed by the PSP . The program stack pointer is decremented again and the first byte is restored from memory addressed by the PSP . After the program counter and flags have been restored from stack, the interrupts are enabled. The effect is to restore the program counter and flags from the program stack, decrement the program stack pointer by two, and re-enable interrupts.The call subroutine (CALL) instruction stores the program counter and flags on the program stack and increments the PSP by two.XTALIN/P2.1IN 912136-MHz ceramic resonator or external clock input, or P2.1 inputXTALOUT OUT1013146-MHz ceramic resonator return pin or internal oscillator outputV PP 71011Programming voltage supply, ground for normal operation V CC111415Voltage supplyVREG/P2.0 81112Voltage supply for 1.3-k Ω USB pull-up resistor (3.3V nominal). Also serves as P2.0 input.V SS699, 10Ground5.0 Pin Assignments (continued)NameI/O CY7C63723CY7C63743CY7C63722Description18-Pin 24-Pin 25-PadThe return from subroutine (RET) instruction restores the program counter, but not the flags, from program stack and decrements the PSP by two.Note that there are restrictions in using the JMP, CALL, and INDEX instructions across the 4-KB boundary of the program memory. Refer to the CYASM Assembler User’s Guide for a detailed description.6.58-bit Data Stack Pointer (DSP)The data stack pointer (DSP) supports PUSH and POP instructions that use the data stack for temporary storage. A PUSH instruction will pre-decrement the DSP, then write data to the memory location addressed by the DSP. A POP instruction will read data from the memory location addressed by the DSP, then post-increment the DSP.During a reset, the Data Stack Pointer will be set to zero. A PUSH instruction when DSP equals zero will write data at the top of the data RAM (address 0xFF). This would write data to the memory area reserved for a FIFO for USB endpoint 0. In non-USB applications, this works fine and is not a problem.For USB applications, the firmware should set the DSP to an appropriate location to avoid a memory conflict with RAM dedicated to USB FIFOs. The memory requirements for the USB endpoints are shown in Section 8.2. For example, assembly instructions to set the DSP to 20h (giving 32 bytes for program and data stack combined) are shown below:MOV A,20h; Move 20 hex into Accumulator (must be D8h or less to avoid USB FIFOs)SWAP A,DSP; swap accumulator value into DSP register6.6Address ModesThe CY7C637xx microcontrollers support three addressing modes for instructions that require data operands: data, direct, and indexed.6.6.1DataThe “Data” address mode refers to a data operand that is actually a constant encoded in the instruction. As an example, consider the instruction that loads A with the constant 0x30:•MOV A, 30hThis instruction will require two bytes of code where the first byte identifies the “MOV A” instruction with a data operand as the second byte. The second byte of the instruction will be the constant “0xE8h”. A constant may be referred to by name if a prior “EQU” statement assigns the constant value to the name. For example, the following code is equivalent to the example shown above:•DSPINIT: EQU 30h•MOV A,DSPINIT6.6.2Direct“Direct” address mode is used when the data operand is a variable stored in SRAM. In that case, the one byte address of the variable is encoded in the instruction. As an example, consider an instruction that loads A with the contents of memory address location 0x10h:•MOV A, [10h]In normal usage, variable names are assigned to variable addresses using “EQU” statements to improve the readability of the assembler source code. As an example, the following code is equivalent to the example shown above:•buttons: EQU 10h•MOV A,[buttons]6.6.3Indexed“Indexed” address mode allows the firmware to manipulate arrays of data stored in SRAM. The address of the data operand is the sum of a constant encoded in the instruction and the contents of the “X” register. In normal usage, the constant will be the “base” address of an array of data and the X register will contain an index that indicates which element of the array is actually addressed:•array: EQU 10h•MOV X,3•MOV A,[x+array]This would have the effect of loading A with the fourth element of the SRAM “array” that begins at address 0x10h. The fourth element would be at address 0x13h.7.0 Instruction Set SummaryRefer to the CYASM Assembler User’s Guide for detailed information on these instructions. Note that conditional jump instructions (i.e., JC, JNC, JZ, JNZ) take 5 cycles if jump is taken, 4 cycles if no jump.MNEMONIC Operand Opcode Cycles MNEMONIC Operand Opcode Cycles HALT 007NOP 204ADD A,expr data014INC A acc214ADD A,[expr] direct026INC X x224ADD A,[X+expr] index037INC [expr] direct237ADC A,expr data044INC [X+expr] index248ADC A,[expr] direct056DEC A acc254ADC A,[X+expr] index067DEC X x264SUB A,expr data074DEC [expr] direct277SUB A,[expr] direct086DEC [X+expr] index288SUB A,[X+expr] index097IORD expr address295SBB A,expr data0A4IOWR expr address2A5SBB A,[expr] direct0B6POP A2B4SBB A,[X+expr] index0C7POP X2C4OR A,expr data0D4PUSH A2D5OR A,[expr] direct0E6PUSH X2E5OR A,[X+expr] index0F7SWAP A,X2F5AND A,expr data104SWAP A,DSP305AND A,[expr] direct116MOV [expr],A direct315AND A,[X+expr] index127MOV [X+expr],A index326XOR A,expr data134OR [expr],A direct337XOR A,[expr] direct146OR [X+expr],A index348XOR A,[X+expr] index157AND [expr],A direct357CMP A,expr data165AND [X+expr],A index368CMP A,[expr] direct177XOR [expr],A direct377CMP A,[X+expr] index188XOR [X+expr],A index388MOV A,expr data194IOWX [X+expr] index396MOV A,[expr] direct1A5CPL 3A4MOV A,[X+expr] index1B6ASL 3B4MOV X,expr data1C4ASR 3C4MOV X,[expr] direct1D5RLC 3D4reserved 1E RRC 3E4XPAGE 1F4RET 3F8MOV A,X404DI 704MOV X,A414EI 724MOV PSP,A604RETI 738CALL addr50 - 5F10JMP addr80-8F5JC addr C0-CF 5 (or 4) CALL addr90-9F10JNC addr D0-DF 5 (or 4)JZ addr A0-AF 5 (or 4)JACC addr E0-EF7JNZ addr B0-BF 5 (or 4)INDEX addr F0-FF148.0 Memory Organization8.1Program Memory Organization[1]After reset Address14 -bit PC0x0000Program execution begins here after a reset.0x0002USB Bus Reset interrupt vector0x0004128-µs timer interrupt vector0x0006 1.024-ms timer interrupt vector0x0008USB endpoint 0 interrupt vector0x000A USB endpoint 1 interrupt vector0x000C USB endpoint 2 interrupt vector0x000E SPI interrupt vector0x0010Capture timer A interrupt Vector0x0012Capture timer B interrupt vector0x0014GPIO interrupt vector0x0016Wake-up interrupt vector0x0018Program Memory begins here0x1FDF8 KB PROM ends here (8K - 32 bytes). See Note below Figure 8-1. Program Memory Space with Interrupt Vector TableNote:1.The upper 32 bytes of the 8K PROM are reserved. Therefore, the user’s program must not overwrite this space.8.2Data Memory OrganizationThe CY7C637xx microcontrollers provide 256 bytes of data RAM. In normal usage, the SRAM is partitioned into four areas: program stack, data stack, user variables and USB endpoint FIFOs as shown below:After reset Address8-bit DSP8-bit PSP0x00Program Stack Growth(User’s firmware movesDSP)8-bit DSP User Selected Data Stack GrowthUser Variables0xE8USB FIFO for Address A endpoint 20xF0USB FIFO for Address A endpoint 10xF8USB FIFO for Address A endpoint 0Top of RAM Memory0xFFFigure 8-2. Data Memory Organization8.3I/O Register SummaryI/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads the selected port into the accumulator. IOWR writes data from the accumulator to the selected port. Indexed I/O Write (IOWX) adds the contents of X to the address in the instruction to form the port address and writes data from the accumulator to the specified port. Note that specifying address 0 with IOWX (e.g., IOWX 0h) means the I/O port is selected solely by the contents of X.Note:All bits of all registers are cleared to all zeros on reset, except the Processor Status and Control Register (Figure20-1). All registers not listed are reserved, and should never be written by firmware. All bits marked as reserved should always be written as 0 and be treated as undefined by reads.Table 8-1. I/O Register SummaryRegister Name I/O Address Read/Write Function Fig. Port 0 Data0x00R/W GPIO Port 012-2 Port 1 Data0x01R/W GPIO Port 112-3 Port 2 Data0x02R Auxiliary input register for D+, D–, VREG, XTALIN 12-8 Port 0 Interrupt Enable0x04W Interrupt enable for pins in Port 021-4 Port 1 Interrupt Enable0x05W Interrupt enable for pins in Port 121-5 Port 0 Interrupt Polarity 0x06W Interrupt polarity for pins in Port 021-6 Port 1 Interrupt Polarity 0x07W Interrupt polarity for pins in Port 121-7 Port 0 Mode0 0x0A W Controls output configuration for Port 012-4 Port 0 Mode10x0B W12-5 Port 1 Mode00x0C W Controls output configuration for Port 112-6 Port 1 Mode10x0D W12-7 USB Device Address0x10R/W USB Device Address register14-1 EP0 Counter Register0x11R/W USB Endpoint 0 counter register14-4 EP0 Mode Register0x12R/W USB Endpoint 0 configuration register14-2 EP1 Counter Register0x13R/W USB Endpoint 1 counter register14-4 EP1 Mode Register0x14R/W USB Endpoint 1 configuration register14-3 EP2 Counter Register0x15R/W USB Endpoint 2 counter register14-4 EP2 Mode Register0x16R/W USB Endpoint 2 configuration register14-3 USB Status & Control0x1F R/W USB status and control register13-1 Global Interrupt Enable0x20R/W Global interrupt enable register21-1 Endpoint Interrupt Enable0x21R/W USB endpoint interrupt enables21-2 Timer (LSB)0x24R Lower 8 bits of free-running timer (1 MHz)18-1 Timer (MSB)0x25R Upper 4 bits of free-running timer18-2 WDR Clear0x26W Watchdog Reset clear-Capture Timer A Rising0x40R Rising edge Capture Timer A data register19-2 Capture Timer A Falling0x41R Falling edge Capture Timer A data register19-3 Capture Timer B Rising0x42R Rising edge Capture Timer B data register19-4 Capture Timer B Falling0x43R Falling edge Capture Timer B data register19-5 Capture TImer Configuration0x44R/W Capture Timer configuration register19-7 Capture Timer Status0x45R Capture Timer status register19-6 SPI Data0x60R/W SPI read and write data register17-2 SPI Control0x61R/W SPI status and control register17-3 Clock Configuration0xF8R/W Internal / External Clock configuration register9-2 Processor Status & Control0xFF R/W Processor status and control20-1。

CY7C1411AV18资料

Errata Revision: *CMay 02, 2007RAM9 QDR-I/DDR-I/QDR-II/DDR- II ErrataCY7C129*DV18/CY7C130*DV25CY7C130*BV18/CY7C130*BV25/CY7C132*BV25CY7C131*BV18 / CY7C132*BV18/CY7C139*BV18CY7C191*BV18/CY7C141*AV18 / CY7C142*AV18/CY7C151*V18 /CY7C152*V18This document describes the DOFF issue for QDRII/DDRII and the Output Buffer and JTAG issues for QDRI/DDRI/QDRII/DDRII. Details include trigger conditions, possible workarounds and silicon revision applicability.This document should be used to compare to the respective datasheet for the devices to fully describe the device functionality.Please contact your local Cypress Sales Representative for availability of the fixed devices and any other questions.Devices AffectedTable 1. List of Affected devicesProduct StatusAll of the above densities and revisions are available in sample as well as production quantities.QDR/DDR DOFF Pin, Output Buffer and JTAG Issues Errata SummaryThe following table defines the issues and the fix status for the different devices which are affected.Density & Revision Part Numbers Architecture 9Mb - Ram9(90 nm)CY7C130*DV25QDRI/DDRI 9Mb - Ram9(90 nm)CY7C129*DV18QDRII 18Mb - Ram9(90nm)CY7C130*BV18CY7C130*BV25CY7C132*BV25QDRI/DDRI18Mb - Ram9(90nm)CY7C131*BV18CY7C132*BV18CY7C139*BV18CY7C191*BV18QDRII/DDRII36Mb - Ram9(90nm)CY7C141*AV18CY7C142*AV18QDRII/DDRII 72Mb -Ram9(90nm)CY7C151*V18CY7C152*V18QDRII/DDRIIItemIssueDeviceFix Status1.DOFF pin is used for enabling/dis-abling the DLL circuitry within the SRAM. To enable the DLL circuitry, DOFF pin must be externally tied HIGH. The QDR-II/DDR-II devices have an internal pull down resistor of ~5K . The value of the external pull-up resistor should be 500 or less in order to ensure DLL is enabled.9Mb - “D” Rev - Ram918Mb - “B” Rev - Ram936Mb - “A” Rev - Ram972Mb - Ram9QDR-II/DDR-II DevicesThe fix involved removing the in-ternal pull-down resistor on the DOFF pin. The fix has been im-plemented on the new revision and is now available.ΩΩTable 2.Issue Definition and fix status for different devices1. DOFF Pin Issue•ISSUE DEFINITIONThis issue involves the DLL not turning ON properly if a large resistor is used (eg:-10K ) as an external pullup resistor to enable the DLL. If a 10K or higher pullup resistor is used externally, the voltage on DOFF is not high enough to enable the DLL.•PARAMETERS AFFECTEDThe functionality of the device will be affected because of the DLL is not turning ON properly. When the DLL is enabled, all AC and DC parameters on the datasheet are met. •TRIGGER CONDITION(S)Having a 10K or higher external pullup resistor for disabling the DOFF pin.•SCOPE OF IMPACTThis issue will alter the normal functionality of the QDRII/DDRII devices when the DLL is disabled.•EXPLANATION OF ISSUEFigure 1 shows the DOFF pin circuit with an internal 5K internal resistor. The fix planned is to disable the internal 5K leaker.•WORKAROUND2.O/P Buffer enters a locked up unde-fined state after controls or clocks are left floating. No proper read/write access can be done on the device until a dummy read is performed.9Mb - “D” Rev - Ram918Mb - “B” Rev - Ram936Mb - “A” Rev - Ram972Mb - Ram9QDR-I/DDR-I/QDR-II/DDR-II Devices The fix has been implemented onthe new revision and is now avail-able.3.The EXTEST function in the JTAG test fails when input K clock is floating in the JTAG mode.9Mb - “D” Rev - Ram918Mb - “B” Rev - Ram936Mb - “A” Rev - Ram972Mb - Ram9QDR-I/DDR-I/QDR-II/DDR-II DevicesThe fix involved bypassing the ZQ circuitry in JTAG mode. This was done by overriding the ZQ circuit-ry by the JTAG signal. The fix has been implemented on the new re-vision and is now available.Figure 1.DOFF pin with the 5K internal resistorItemIssueDeviceFix StatusΩΩΩΩΩΩThe workaround is to have a low value of external pullup resistor for the DOFF pin (recommended value is <500). When DOFF pins from multiple QDR devices are connected through the same pull-up resistors on the board, it is recommended that this DOFF pin be directly connected to Vdd due to the lower effective resistance since the "leakers" are in parallel.Figure 2 shows the proposed workaround and the fix planned.•FIXSTATUSFix involved removing the internal pull-down resistor on the DOFF pin. The fix has been implemented on the new revision and is now available. The new revision is an increment of the existing revision. The following table lists the devices affected, current revision and the new revision after the fix.Table 3.List of Affected Devices and the new revison2.Output Buffer IssueFigure 2.Proposed workaround with the 500 external pullupCurrent Revision New Revision after the FixCY7C129*DV18CY7C129*EV18CY7C131*BV18CY7C131*CV18CY7C132*BV18CY7C132*CV18CY7C139*BV18CY7C139*CV18CY7C191*BV18CY7C191*CV18CY7C141*AV18CY7C141*BV18CY7C142*AV18CY7C142*BV18CY7C151*V18CY7C151*AV18CY7C152*V18CY7C152*AV18ΩΩ•ISSUE DEFINITIONThis issue involves the output buffer entering an unidentified state when the input signals (only Control signals or Clocks) are floating during reset or initialization of the memory controller after power up. •PARAMETERS AFFECTEDNo timing parameters are affected. The device may drive the outputs even though the read operation is not enabled. A dummy read is performed to clear this condition.•TRIGGER CONDITION(S)Input signals(namely RPS# for QDR-I/QDRII , WE# and LD# for DDR-I/DDRII) or Clocks (K/K# and/or C/C#) are floating during reset or initialization of the memory controller after power up.•SCOPE OF IMPACTThis issue will jeopardize any number of writes or reads which take place after the controls or clock are left floating. This can occur anywhere in the SRAM access ( all the way from power up of the memory device to transitions taking place for read/write accesses to the memory device) if the above trigger conditions are met.•EXPLANATION OF ISSUEFigure 3 shows the output register Reset circuit with an SR Latch circled. This latch has two inputs with one of them coming from some logic affected by the clock and RPS#(QDR) or WE# and LD#(DDR).The issue happens when clocks are glitching/toggling with controls floating. This will cause the SR latch to be taken into an unidentified state. The SR Latch will need to be reset by a dummy read operation if this happens. Array•WORKAROUNDThis is viable only if the customer has the trigger conditions met during reset or initialization of the memory controller after power up. In order for the workaround to perform properly, Cypress recommends the insertion of a minimum of 16 “dummy” READ operations to every SRAM device on the board prior to writing any meaningful data into the SRAM. After this one “dummy” READ operation, the device will perform properly.“Dummy” READ is defined as a read operation to the device that is not meant to retrieve required data. The “dummy” READ can be to any address location in the SRAM. Refer to Figure 4 for the dummy read implemen-tation.In systems where multiple SRAMs with multiple RPS# lines are used, a dummy read operation will have to be performed on every SRAM on the board. Below is an example sequence of events that can be performed before valid access can be performed on the SRAM.1) Initialize the Memory Controller2) Assert RPS# Low for each of the memory devicesNote:For all devices with x9 bus configuration, the following sequence needs to be performed:1) For the 72M / 36M / 18M x9 devices drive address pin A2 / A10 / A3 low respectively and perform dummyread.2) For the 72M / 36M / 18M x9 devices drive address pin A2 / A10 / A3 high respectively and perform dummyread.If the customer has the trigger conditions met during normal access to the memory then there is no workaround at this point.•FIX STATUSThe fix has been implemented on the new revision and is now available. The new revision is an increment of the existing revision. Please refer to Table 4 for the list of devices affected, current revision and the new revision after the fix.3. JTAG Mode Issue•ISSUE DEFINITIONIf the input clock (K Clock) is left floating when the device is in JTAG mode, spurious high frequency noise on this input can be interpreted by the device as valid clocks. This could cause the impedance matching circuitry (ZQ) on the QDR/DDR devices to periodically load itself with incorrect values. These incorrect values in the ZQ register could force the outputs into a High-Impedance state. The ZQ circuitry requires at least 1000 valid K clock cycles to drive the outputs from high impedance to low impedance levels.•PARAMETERS AFFECTEDThis issue only affects the EXTEST command when the device is in the JTAG mode. The normal functionality of the device will not be affected.•TRIGGER CONDITION(S)EXTEST command executed immediately after power-up without providing any K clock cycles.•SCOPE OF IMPACTThis issue only impacts the EXTEST command when device is tested in the JTAG mode. Normal functionality of the device is not affected. •EXPLANATION OF ISSUEImpedance matching circuitry (ZQ) is present on the QDR/DDR devices to set the desired impedance on the outputs. This ZQ circuitry is updated every 1000 clock cycles of K clock to ensure that the impedance of the O/P is set to valid state. However, when the device is operated in the JTAG mode immediately after power-up, high frequency noise on the input K clock can be treated by the ZQ circuitry as valid clocks thereby setting the outputs in to a high-impedance mode. If a minimum of 1000 valid K clocks are applied before performing the JTAG test, this should clear the ZQ circuitry and ensure that the outputs are driven to valid impedance levels.•WORKAROUNDElimination of the issue: After power-up, before any valid operations are performed on the device, insert a minimum of 1000 valid clocks on K input.•FIX STATUSThe fix involved bypassing the ZQ circuitry in JTAG mode. This was done by overriding the ZQ circuitry by the JTAG signal. The fix has been implemented on the new revision and is now available. The new revision is an increment of the existing revision. Please refer to Table 4 for the list of devices affected, current revision and the new revision after the fix..Table 4.List of Affected devices and the new revisionCurrent Revision New Revision after the FixCY7C129*DV18CY7C129*EV18CY7C130*DV25CY7C130*EV25CY7C130*BV18CY7C130*CV18CY7C130*BV25CY7C130*CV25CY7C132*BV25CY7C132*CV25CY7C131*BV18CY7C131*CV18CY7C132*BV18CY7C132*CV18CY7C139*BV18CY7C139*CV18CY7C191*BV18CY7C191*CV18CY7C141*AV18CY7C141*BV18CY7C142*AV18CY7C142*BV18CY7C151*V18CY7C151*AV18CY7C152*V18CY7C152*AV18ReferencesAll 90nm QDRI/DDRI/QDRII/DDRII datasheets:-Table 5.List of Datasheet spec# for the Affected devicesSpec#Part#DensityArchitecture38-05628CY7C1304DV259-MBIT QDR(TM) SRAM 4-WORD BURST 38-05632CY7C1308DV259-MBIT DDR-I SRAM 4-WORD BURST 001-00350CY7C1292DV18/1294DV189-MBIT QDR- II(TM) SRAM 2-WORD BURST 38-05621CY7C1316BV18/1916BV18/1318BV18/1320BV1818-MBIT DDR-II SRAM 2-WORD BURST 38-05622CY7C1317BV18/1917BV18/1319BV18/1321BV1818-MBIT DDR-II SRAM 4-WORD BURST 38-05623CY7C1392BV18/1393BV18/1394BV1818-MBIT DDR-II SIO SRAM 2-WORD BURST 38-05631CY7C1323BV2518-MBIT DDR-I SRAM 4-WORD BURST 38-05630CY7C1305BV25/1307BV2518-MBIT QDR(TM) SRAM 4-WORD BURST 38-05627CY7C1303BV25/1306BV2518-MBIT QDR(TM) SRAM 2-WORD BURST 38-05629CY7C1305BV18/1307BV1818-MBIT QDR(TM) SRAM 4-WORD BURST 38-05626CY7C1303BV18/1306BV1818-MBIT QDR(TM) SRAM 2-WORD BURST 38-05619CY7C1310BV18/1910BV18/1312BV18/1314BV1818-MBIT QDR - II (TM) SRAM 2-WORD BURST 38-05620CY7C1311BV18/1911BV18/1313BV18/1315BV1818-MBIT QDR - II SRAM 4-WORD BURST 38-05615CY7C1410AV18/1425AV18/1412AV18/1414AV1836-MBIT QDR-II(TM) SRAM 2-WORD BURST 38-05614CY7C1411AV18/1426AV18/1413AV18/1415AV1836-MBIT QDR(TM)-II SRAM 4-WORD BURST 38-05616CY7C1416AV18/1427AV18/1418AV18/1420AV1836-MBIT DDR-II SRAM 2-WORD BURST 38-05618CY7C1417AV18/1428AV18/1419AV18/1421AV1836-MBIT DDR-II SRAM 4-WORD BURST 38-05617CY7C1422AV18/1429AV18/1423AV18/1424AV1836-MBIT DDR-II SIO SRAM 2-WORD BURST 38-05489CY7C1510V18/1525V18/1512V18/1514V1872-MBIT QDR-II SRAM 2-WORD BURST 38-05363CY7C1511V18/1526V18/1513V18/1515V1872-MBIT QDR(TM)-II SRAM 4-WORD BURST 38-05563CY7C1516V18/1527V18/1518V18/1520V1872-MBIT DDR-II SRAM 2-WORD BURST 38-05565CY7C1517V18/1528V18/1519V18/1521V1872-MBIT DDR-II SRAM 4-WORD BURST 38-05564CY7C1522V18/1529V18/1523V18/1524V1872-MBITDDR-II SIO SRAM 2-WORD BURSTDocument History PageDocument Title: RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata Document #: 001-06217 Rev. *CREV.ECN NO.IssueDateOrig. ofChange Description of Change**419849See ECN REF New errata for Ram9 QDR2/DDR2 SRAMs.*A493936See ECN QKS Added Output buffer and JTAG mode issues, Item#2 and #3Added 9Mb QDR-II Burst of 2 and QDR-1/DDR-I part numbers.*B733176See ECN NJY Added missing part numbers in the title for Spec#’s 38-05615,38-05614,38-05363,38-05563 on Table 5 on page 7.*C1030020 See ECN TBE Updated the fix status of the three issues, and modified the description forthe Output Buffer workaround for x9 devices on page 5.。

CY7C131中文资料

1K x 8 Dual-Port Static RAMCY7C130/CY7C131CY7C140/CY7C141Features•True Dual-Ported memory cells which allow simulta-neous reads of the same memory location •1K x 8 organization•0.65-micron CMOS for optimum speed/power •High-speed access: 15 ns•Low operating power: I CC = 110 mA (max.)•Fully asynchronous operation •Automatic power-down•Master CY7C130/CY7C131 easily expands data bus width to 16 or more bits using slave CY7C140/CY7C141•BUSY output flag on CY7C130/CY7C131; BUSY input on CY7C140/CY7C141•INT flag for port-to-port communication•Available in 48-pin DIP (CY7C130/140), 52-pin PLCC, 52-Pin TQFP .•Pb-Free packages availableFunctional DescriptionThe CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master dual-port RAM in conjunction with the CY7C140/CY7C141 slave dual-port device in systems requiring 16-bit or greater word widths. It is the solution to applications requiring shared or buffered data, such as cache memory for DSP , bit-slice, or multiprocessor designs.Each port has independent control pins; chip enable (CE), write enable (R/W), and output enable (OE). Two flags are provided on each port, BUSY and INT. BUSY signals that the port is trying to access the same location currently being accessed by the other port. INT is an interrupt flag indicating that data has been placed in a unique location (3FF for the left port and 3FE for the right port). An automatic power-down feature is controlled independently on each port by the chip enable (CE) pins.The CY7C130 and CY7C140 are available in 48-pin DIP . The CY7C131 and CY7C141 are available in 52-pin PLCC, 52-pin Pb-free PLCC, 52-pin PQFP and 52-pin Pb-free PQFP .Note:1.CY7C130/CY7C131 (Master): BUSY is open drain output and requires pull-up resistor2.Open drain outputs: pull-up resistor required.Logic Block DiagramPin Configurations131415161718192021222326272832313029333635342425GND123456789101138394044434241454847461237R/W L CE L BUSY L INT L OE L A 0L A 1L A 2L A 3L A 4L A 5L A 6L A 7L A 8L A 9L I/O 0L I/O 1L I/O 2L I/O 3L I/O 4L I/O 5L I/O 6L I/O 7L CE R R/W R BUSY R INT R OE R A 0R A 1R A 2R A 3R A 4R A 5R A 6R A 7R A 8R A 9R I/O 7R I/O 6R I/O 5R I/O 4R I/O 3R I/O 2R I/O 1R I/O 0RV CCDIP Top View7C1307C140R/W L BUSY LCE L OE LA 9L A 0LA 0RA 9R R/W R CE R OE RCE R OE R CE L OE L R/W LR/W RI/O 7L I/O 0L I/O 7R I/O 0R BUSY RINT LINT RARBITRATIONLOGIC(7C130/7C131ONLY)ANDINTERRUPT LOGICCONTROL I/O CONTROLI/O MEMORY ARRAYADDRESS DECODERADDRESS DECODER[1][2][2]Pin Configuration (continued )1V C CTop ViewPLCC OE R A 0R 8910111213141516171819204645444342414039383736353421222324252627282930313233765432525150494847A 1R A 2R A 3R A 4R A 5R A 6R A 7R A 8R A 9R NC I/O 7RA 1LA 2L A 3L A 4L A 5L A 6L A 7L A 8L A 9L I/O 0L I/O 1L I/O 2L I/O 3LI /O I /O I /O I /O I /O I /O I /O I /O I /O I /O I /O 4L 5L6L 7L0R 1R2R 3R 4R5R 6RN C G N DO E B U S Y I N T A N C R /W C E R /W B U S Y I N T N C0LL L LL L C E R R R R7C1317C14146123456789101112133938373635343332313029282714151617181920212223242526525150494847454443424140Top ViewPQFPV C CO E B U S Y I N T A N C R /W C E R /W B U S Y I N T N C0LL L LL L C E R R R ROE R A 0R A 1R A 2R A 3R A 4R A 5R A 6R A 7R A 8R A 9R NC I/O 7RA 1L A 2L A 3L A 4L A 5L A 6L A 7L A 8L A 9L I/O 0L I/O 1L I/O 2L I/O 3LI /O I /O I /O I /O I /O I /O I /O I /O I /O I /O I /O 4L 5L6L 7L0R 1R2R 3R 4R5R 6RN C G N D 7C1317C141Pin DefinitionsLeft PortRight PortDescriptionCE L CE R Chip Enable R/W L R/W R Read/Write Enable OE LOE ROutput Enable A 0L –A 11/12L A 0R –A 11/12R AddressI/O 0L –I/O 15/17L I/O 0R –I/O 15/17R Data Bus Input/Output INT L INT R Interrupt Flag BUSY L BUSY RBusy Flag V CC Power GNDGroundSelection Guide7C131-15[3]7C141-157C131-25[3]7C141-257C130-307C131-307C140-307C141-307C130-357C131-357C140-357C141-357C130-457C131-457C140-457C141-457C130-557C131-557C140-557C141-55Unit Maximum Access Time 152530354555ns Maximum Operating CurrentCom’l/Ind 190170170120120110mAMilitary 170170120Maximum Standby CurrentCom’l/Ind 756565454535mAMilitary656545Shaded areas contain preliminary information.Note:3.15 and 25-ns version available only in PLCC/PQFP packages.Maximum Ratings[4](Above which the useful life may be impaired. For user guide-lines, not tested.)Storage Temperature .................................–65°C to +150°C Ambient Temperature withPower Applied.............................................–55°C to +125°C Supply Voltage to Ground Potential(Pin 48 to Pin 24)...........................................–0.5V to +7.0V DC Voltage Applied to Outputsin High Z State...............................................–0.5V to +7.0V DC Input Voltage............................................–3.5V to +7.0V Output Current into Outputs (LOW).............................20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015)Latch-Up Current.................................................... >200 mA Operating RangeRangeAmbientTemperature V CC Commercial0°C to +70°C 5V ± 10% Industrial–40°C to +85°C 5V ± 10% Military[5]–55°C to +125°C 5V ± 10%Electrical Characteristics Over the Operating Range[6]Parameter Description Test Conditions 7C131-15[3]7C141-157C130-30[3]7C131-25,307C140-307C141-25,307C130-35,457C131-35,457C140-35,457C141-35,457C130-557C131-557C140-557C141-55Unit Min.Max.Min.Max.Min.Max.Min.Max.V OH Output HIGHVoltageV CC = Min., I OH = –4.0 mA 2.4 2.4 2.4 2.4VV OL Output LOWVoltage I OL = 4.0 mA0.40.40.40.4V I OL = 16.0 mA[7]0.50.50.50.5V IH Input HIGH Voltage 2.2 2.2 2.2 2.2V V IL Input LOW Voltage0.80.80.80.8V I IX Input LeakageCurrentGND < V I < V CC–5+5–5+5–5+5–5+5µAI OZ Output LeakageCurrent GND < V O < V CC,Output Disabled–5+5–5+5–5+5–5+5µAI OS Output ShortCircuit Current[8, 9]V CC = Max.,V OUT = GND–350–350–350–350mAI CC V CC OperatingSupply Current CE = V IL,Outputs Open,f = f MAX[10]Com’l190170120110mAMil170120I SB1Standby CurrentBoth Ports,TTL Inputs CE L and CE R >V IH, f = f MAX[10]Com’l75654535mAMil6545I SB2Standby CurrentOne Port,TTL Inputs CE L or CE R > V IH,Active Port OutputsOpen,f = f MAX[10]Com’l1351159075mAMil11590I SB3Standby CurrentBoth Ports,CMOS Inputs Both Ports CE L andCE R >V CC – 0.2V,V IN > V CC – 0.2Vor V IN < 0.2V, f = 0Com’l15151515mAMil1515Shaded areas contain preliminary information.Note:4.The Voltage on any input or I/O pin cannot exceed the power pin during power-up.5.T A is the “instant on” case temperature6.See the last page of this specification for Group A subgroup testing information.7.BUSY and INT pins only.8.Duration of the short circuit should not exceed 30 seconds.9.This parameter is guaranteed but not tested.10.At f = f MAX, address and data inputs are cycling at the maximum frequency of read cycle of 1/t RC and using AC Test Waveforms input levels of GND to 3V.I SB4Standby Current One Port, CMOS InputsOne Port CE L or CE R > V CC – 0.2V,V IN > V CC – 0.2V or V IN < 0.2V, Active Port Outputs Open, f = f MAX [10]Com’l 1251058570mAMil10585Capacitance [9]Parameter DescriptionTest ConditionsMax.Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V CC = 5.0V15pF C OUTOutput Capacitance10pFElectrical Characteristics Over the Operating Range [6] (continued)Parameter Description Test Conditions 7C131-15[3]7C141-157C130-30[3]7C131-25,307C140-307C141-25,307C130-35,457C131-35,457C140-35,457C141-35,457C130-557C131-557C140-557C141-55Unit Min.Max.Min.Max.Min.Max.Min.Max.AC Test Loads and Waveforms3.0V 5V OUTPUTR1 893ΩR2347Ω30pF INCLUDING JIGAND SCOPEGND90%90%10%≤ 5ns≤5ns5V OUTPUTR1 893ΩR2347Ω5pFINCLUDING JIGAND SCOPE(a)(b)OUTPUT1.40VEquivalent to:THÉVENIN EQUIVALENT5V 281Ω30pFBUSY OR INT(CY7C130/CY7C131ONLY)10%ALL INPUT PULSES 250ΩSwitching Characteristics Over the Operating Range[6, 11]Parameter Description7C131-15[3]7C141-157C130-25[3]7C131-257C140-257C141-257C130-307C131-307C140-307C141-30Unit Min.Max.Min.Max.Min.Max.READ CYCLEt RC Read Cycle Time152530ns t AA Address to Data Valid[12]152530ns t OHA Data Hold from Address Change000ns t ACE CE LOW to Data Valid[12]152530ns t DOE OE LOW to Data Valid[12]101520ns t LZOE OE LOW to Low Z[9, 13, 14]333ns t HZOE OE HIGH to High Z[9, 13, 14]101515ns t LZCE CE LOW to Low Z[9, 13, 14]355ns t HZCE CE HIGH to High Z[9, 13, 14]101515ns t PU CE LOW to Power-Up[9]000ns t PD CE HIGH to Power-Down[9]152525ns WRITE CYCLE[15]t WC Write Cycle Time152530ns t SCE CE LOW to Write End122025ns t AW Address Set-Up to Write End122025ns t HA Address Hold from Write End222ns t SA Address Set-Up to Write Start000ns t PWE R/W Pulse Width121525ns t SD Data Set-Up to Write End101515ns t HD Data Hold from Write End000ns t HZWE R/W LOW to High Z[14]101515ns t LZWE R/W HIGH to Low Z[14]000ns Shaded areas contain preliminary information.Note:11.Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specifiedI OL/I OH, and 30-pF load capacitance.12.AC Test Conditions use V OH = 1.6V and V OL = 1.4V.13.At any given temperature and voltage condition for any given device, t HZCE is less than t LZCE and t HZOE is less than t LZOE.14.t LZCE, t LZWE, t HZOE, t LZOE, t HZCE and t HZWE are tested with C L = 5pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.15.The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal canterminate a write by going high. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.BUSY/INTERRUPT TIMING t BLA BUSY LOW from Address Match 152020ns t BHA BUSY HIGH from Address Mismatch [16]152020ns t BLC BUSY LOW from CE LOW 152020ns t BHC BUSY HIGH from CE HIGH [16]152020ns t PS Port Set Up for Priority 555ns t WB [17]R/W LOW after BUSY LOW 000ns t WH R/W HIGH after BUSY HIGH 132030ns t BDD BUSY HIGH to Valid Data152530ns t DDD Write Data Valid to Read Data Valid Note 18Note 18Note 18ns t WDD Write Pulse to Data Delay Note 18Note 18Note 18ns INTERRUPT TIMINGt WINS R/W to INTERRUPT Set Time 152525ns t EINS CE to INTERRUPT Set Time 152525ns t INS Address to INTERRUPT Set Time 152525ns t OINR OE to INTERRUPT Reset Time [16]152525ns t EINR CE to INTERRUPT Reset Time [16]152525ns t INRAddress to INTERRUPT Reset Time [16]152525nsShaded areas contain preliminary information.Note:16.These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.17.CY7C140/CY7C141 only.18.A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:BUSY on Port B goes HIGH. Port B’s address is toggled. CE for Port B is toggled.R/W for Port B is toggled during valid read.Switching Characteristics Over the Operating Range [6, 11] (continued)ParameterDescription7C131-15[3]7C141-157C130-25[3]7C131-257C140-257C141-257C130-307C131-307C140-307C141-30UnitMin.Max.Min.Max.Min.Max.Switching Characteristics Over the Operating Range [6,11]Parameter Description7C130-357C131-357C140-357C141-357C130-457C131-457C140-457C141-457C130-557C131-557C140-557C141-55UnitMin.Max.Min.Max.Min.Max.READ CYCLE t RC Read Cycle Time 354555ns t AA Address to Data Valid [12]354555ns t OHA Data Hold from Address Change 0ns t ACE CE LOW to Data Valid [12]354555ns t DOE OE LOW to Data Valid [12]202525ns t LZOE OE LOW to Low Z [9, 13, 14]333ns t HZOE OE HIGH to High Z [9, 13, 14]202025ns t LZCECE LOW to Low Z [9, 13, 14]555nst HZCE CE HIGH to High Z [9, 13, 14]202025ns t PU CE LOW to Power-Up [9]0ns t PD CE HIGH to Power-Down [9]353535ns WRITE CYCLE [15]t WC Write Cycle Time 354555ns t SCE CE LOW to Write End 303540ns t AW Address Set-Up to Write End 303540ns t HA Address Hold from Write End 222ns t SA Address Set-Up to Write Start 000ns t PWE R/W Pulse Width253030ns t SD Data Set-Up to Write End 152020ns t HD Data Hold from Write End 0ns t HZWE R/W LOW to High Z [14]202025ns t LZWE R/W HIGH to Low Z [14]ns BUSY/INTERRUPT TIMINGt BLA BUSY LOW from Address Match 202530ns t BHA BUSY HIGH from Address Mismatch [16]202530ns t BLC BUSY LOW from CE LOW 202530ns t BHC BUSY HIGH from CE HIGH [16]202530ns t PS Port Set Up for Priority 555ns t WB [17]R/W LOW after BUSY LOW 000ns t WH R/W HIGH after BUSY HIGH 303535ns t BDD BUSY HIGH to Valid Data354545ns t DDD Write Data Valid to Read Data Valid Note 18Note 18Note 18ns t WDDWrite Pulse to Data DelayNote 18Note 18Note 18nsINTERRUPT TIMING t WINS R/W to INTERRUPT Set Time 253545ns t EINS CE to INTERRUPT Set Time 253545ns t INS Address to INTERRUPT Set Time 253545ns t OINR OE to INTERRUPT Reset Time [16]253545ns t EINR CE to INTERRUPT Reset Time [16]253545ns t INRAddress to INTERRUPT Reset Time [16]253545nsSwitching Characteristics Over the Operating Range [6,11] (continued)Parameter Description7C130-357C131-357C140-357C141-357C130-457C131-457C140-457C141-457C130-557C131-557C140-557C141-55Unit Min.Max.Min.Max.Min.Max.Switching WaveformsRead Cycle No. 1[19, 20]Read Cycle No. 2[19, 21]Read Cycle No. 3[20]Notes:19.R/W is HIGH for read cycle.20.Device is continuously selected, CE = V IL and OE = V IL .21.Address valid prior to or coincident with CE transition LOW.t RCt AAt OHADATA VALIDPREVIOUS DATA VALIDDATA OUTADDRESSEither Port Address Accesst ACEt LZOEt DOEt HZOEt HZCEDATA VALIDDATA OUTCE OEt LZCEt PUI CC I SBt PDEither Port CE/OE Accesst BHAt BDDVALIDt DDDt WDDADDRESS MATCHADDRESS MATCHR/W R ADDRESS RD INRADDRESS LBUSY LDOUT Lt PSt BLARead with BUSY , Master: CY7C130 and CY7C131t RCt PWEVALIDt HDWrite Cycle No. 1 (OE Three-States Data I/Os—Either Port [15, 22]Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)[16, 23]Notes:22.PWE or t HZWE + t SD to allow the data I/O pins to enter high impedanceand for data to be placed on the bus for the required t SD .23.If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.Switching Waveforms (continued)t AWt WCDATA VALIDHIGH IMPEDANCEt SCEt SAt PWEt HDt SDt HACER/WADDRESSt HZOEOED OUTDATA INEither Portt AWt WCt SCEt SAt PWEt HDt SDt HZWEt HAHIGH IMPEDANCEDATA VALIDt LZWEADDRESSCER/WDATA OUTDATA INBusy Timing Diagram No. 1 (CE Arbitration)Busy Timing Diagram No. 2 (Address Arbitration)Switching Waveforms (continued)ADDRESS MATCHt PSCE L Valid First:t BLCt BHCADDRESS MATCHt PSt BLCt BHCADDRESS L,RBUSY RCE LCE RBUSY LCE RCE LADDRESS L,RCE R Valid First:Left Address Valid First:ADDRESS MATCHt PSADDRESS LBUSY RADDRESS MISMATCHt RC or t WC t BLA t BHAADDRESS RADDRESS MATCHADDRESS MISMATCHt PSADDRESS LBUSY Lt RC or t WC t BLA t BHAADDRESS RRight Address Valid First:Switching Waveforms (continued)Busy Timing Diagram No. 3Write with BUSY (Slave:CY7C140/CY7C141)CEt PWER/Wt WB t WH BUSYInterrupt Timing Diagrams Switching Waveforms (continued)WRITE 3FFt INSt WCt EINSRight Side Clears INT Rt HAt SAt WINSREAD 3FF t RCt EINRt HAt INTt OINRWRITE 3FEt INSt WCt EINSt HAt SAt WINSRight Side Sets INT LLeft Side Sets INT RLeft Side Clears INT LREAD 3FE t EINRt HAt INRt OINRt RC ADDR RCE LR/W L INT LOE LADDR RR/W R CE RINT LADDR RCE RR/W R INT ROE RADDR LR/W LCE LINT RTypical DC and AC Characteristics1.41.00.44.04.55.05.56.0–55251251.21.01201008060402001.02.03.04.0O U T P U T S O U R C E C U R R E N T (m A )SUPPLY VOLTAGE (V)NORMALIZED SUPPLY CURRENTvs. SUPPLY VOLTAGENORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE AMBIENT TEMPERATURE (°C)OUTPUT VOLTAGE (V)OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 0.00.80.80.60.6N O R M A L I Z E D I C C , I S BV CC = 5.0V V IN = 5.0V V CC = 5.0V T A = 25°C0I CC1.61.41.21.00.8–55125N O R M A L I Z E D t A ANORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE AMBIENT TEMPERATURE (°C)1.41.31.21.00.94.04.55.05.56.0N O R M A L I Z E D t A ASUPPLY VOLTAGE (V)NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 120140*********0.01.02.03.04.0O U T P U T S I N K C U R R E N T (m A )080OUTPUT VOLTAGE (V)OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE0.60.8 1.251.00.751040N O R M A L I Z E D I C C0.50NORMALIZED I CC vs. CYCLE TIME CYCLE FREQUENCY (MHz)3.02.52.01.50.501.02.03.05.0N O R M A L I Z E D t P C25.030.020.010.05.00200400600800D E L T A t A A (n s )015.00.0SUPPLY VOLTAGE (V)TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE CAPACITANCE (pF)TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING4.010001.020300.20.61.2I SB30.20.4251.1V V IN = 0.5VN O R M A L I Z E D I C C , I S BI CCI SB3T A = 25°CV CC = 5.0VV CC = 5.0V T A = 25°CT A = 25°CCC = 4.5V V CC = 4.5V T A = 25°COrdering InformationSpeed(ns)Ordering Code PackageName Package TypeOperatingRange30CY7C130-30PC P2548-Lead (600-Mil) Molded DIP Commercial CY7C130-30PI P2548-Lead (600-Mil) Molded DIP Industrial 35CY7C130-35PC P2548-Lead (600-Mil) Molded DIP Commercial CY7C130-35PI P2548-Lead (600-Mil) Molded DIP Industrial CY7C130-35DMB D2648-Lead (600-Mil) Sidebraze DIP Military45CY7C130-45PC P2548-Lead (600-Mil) Molded DIP Commercial CY7C130-45PI P2548-Lead (600-Mil) Molded DIP Industrial CY7C130-45DMB D2648-Lead (600-Mil) Sidebraze DIP Military55CY7C130-55PC P2548-Lead (600-Mil) Molded DIP Commercial CY7C130-55PI P2548-Lead (600-Mil) Molded DIP Industrial CY7C130-55DMB D2648-Lead (600-Mil) Sidebraze DIP Military15CY7C131-15JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C131-15JXC J6952-Lead Pb-Free Plastic Leaded Chip CarrierCY7C131-15NC N5252-Pin Plastic Quad FlatpackCY7C131-15JI J6952-Lead Plastic Leaded Chip Carrier Industrial CY7C131-15JXI J6952-Lead Pb-Free Plastic Leaded Chip Carrier25CY7C131-25JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C131-25JXC J6952-Lead Pb-Free Plastic Leaded Chip CarrierCY7C131-25NC N5252-Pin Plastic Quad FlatpackCY7C131-25NXC N5252-Pin Pb-Free Plastic Quad FlatpackCY7C131-25JI J6952-Lead Plastic Leaded Chip Carrier Industrial CY7C131-25NI N5252-Pin Plastic Quad Flatpack30CY7C131-30JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C131-30NC N5252-Pin Plastic Quad FlatpackCY7C131-30JI J6952-Lead Plastic Leaded Chip Carrier Industrial 35CY7C131-35JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C131-35NC N5252-Pin Plastic Quad FlatpackCY7C131-35JI J6952-Lead Plastic Leaded Chip Carrier Industrial CY7C131-35NI N5252-Pin Plastic Quad Flatpack45CY7C131-45JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C131-45NC N5252-Pin Plastic Quad FlatpackCY7C131-45JI J6952-Lead Plastic Leaded Chip Carrier Industrial CY7C131-45NI N5252-Pin Plastic Quad Flatpack55CY7C131-55JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C131-55JXC J6952-Lead Pb-Free Plastic Leaded Chip CarrierCY7C131-55NC N5252-Pin Plastic Quad FlatpackCY7C131-55NXC N5252-Pin Pb-Free Plastic Quad FlatpackCY7C131-55JI J6952-Lead Plastic Leaded Chip Carrier Industrial CY7C131-55JXI J6952-Lead Pb-Free Plastic Leaded Chip CarrierCY7C131-55NI N5252-Pin Plastic Quad Flatpack30CY7C140-30PC P2548-Lead (600-Mil) Molded DIP Commercial CY7C140-30PI P2548-Lead (600-Mil) Molded DIP Industrial 35CY7C140-35PC P2548-Lead (600-Mil) Molded DIP Commercial CY7C140-35PI P2548-Lead (600-Mil) Molded DIP Industrial CY7C140-35DMBD2648-Lead (600-Mil) Sidebraze DIP Military 45CY7C140-45PC P2548-Lead (600-Mil) Molded DIP Commercial CY7C140-45PI P2548-Lead (600-Mil) Molded DIP Industrial CY7C140-45DMBD2648-Lead (600-Mil) Sidebraze DIP Military 55CY7C140-55PC P2548-Lead (600-Mil) Molded DIP Commercial CY7C140-55PI P2548-Lead (600-Mil) Molded DIP Industrial CY7C140-55DMBD2648-Lead (600-Mil) Sidebraze DIP Military 15CY7C141-15JC J6952-Lead Plastic Leaded Chip Carrier CommercialCY7C141-15NC N5252-Pin Plastic Quad Flatpack 25CY7C141-25JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C141-25JXC J6952-Lead Pb-Free Plastic Leaded Chip Carrier CY7C141-25NC N5252-Pin Plastic Quad Flatpack CY7C141-25JI J6952-Lead Plastic Leaded Chip Carrier Industrial CY7C141-25NIN5252-Pin Plastic Quad Flatpack 30CY7C141-30JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C141-30NC N5252-Pin Plastic Quad Flatpack CY7C141-30JIJ6952-Lead Plastic Leaded Chip Carrier Industrial 35CY7C141-35JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C141-35NC N5252-Pin Plastic Quad Flatpack CY7C141-35JI J6952-Lead Plastic Leaded Chip Carrier Industrial CY7C141-35NIN5252-Pin Plastic Quad Flatpack 45CY7C141-45JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C141-45NC N5252-Pin Plastic Quad Flatpack CY7C141-45JI J6952-Lead Plastic Leaded Chip Carrier Industrial CY7C141-45NIN5252-Pin Plastic Quad Flatpack 55CY7C141-55JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C141-55NC N5252-Pin Plastic Quad Flatpack CY7C141-55JI J6952-Lead Plastic Leaded Chip Carrier Industrial CY7C141-55NIN5252-Pin Plastic Quad FlatpackOrdering Information (continued)Speed (ns)Ordering Code Package Name Package TypeOperating RangeMILITARY SPECIFICATIONS Group A Subgroup Testing Note:24.CY7C140/CY7C141 only.DC CharacteristicsParameterSubgroups V OH 1, 2, 3V OL 1, 2, 3V IH 1, 2, 3V IL Max.1, 2, 3I IX 1, 2, 3I OZ 1, 2, 3I CC 1, 2, 3I SB11, 2, 3I SB21, 2, 3I SB31, 2, 3I SB41, 2, 3Switching CharacteristicsParameterSubgroups READ CYCLEt RC 7, 8, 9, 10, 11t AA 7, 8, 9, 10, 11t ACE 7, 8, 9, 10, 11t DOE7, 8, 9, 10, 11WRITE CYCLEt WC 7, 8, 9, 10, 11t SCE 7, 8, 9, 10, 11t AW 7, 8, 9, 10, 11t HA 7, 8, 9, 10, 11t SA 7, 8, 9, 10, 11t PWE 7, 8, 9, 10, 11t SD 7, 8, 9, 10, 11t HD7, 8, 9, 10, 11BUSY/INTERRUPT TIMINGt BLA 7, 8, 9, 10, 11t BHA 7, 8, 9, 10, 11t BLC 7, 8, 9, 10, 11t BHC 7, 8, 9, 10, 11t PS 7, 8, 9, 10, 11t WINS 7, 8, 9, 10, 11t EINS 7, 8, 9, 10, 11t INS 7, 8, 9, 10, 11t OINR 7, 8, 9, 10, 11t EINR 7, 8, 9, 10, 11t INR7, 8, 9, 10, 11BUSY TIMINGt WB [24]7, 8, 9, 10, 11t WH 7, 8, 9, 10, 11t BDD7, 8, 9, 10, 11Package Diagrams48-Lead (600-Mil) Sidebraze DIP D26MIL-STD-1835 D-14 Config. C51-80044 **Document #: 38-06002 Rev. *DPage 18 of 19All products and company names mentioned in this document may be the trademarks of their respective holders.Package Diagrams (continued)51-85020-*A48-Lead (600-Mil) Molded DIP P2551-85042-**52-Lead Pb-Free Plastic Quad Flatpack N5252-Lead Plastic Quad Flatpack N52Document History PageDocument Title: CY7C130/CY7C131/CY7C140/CY7C141 1K x 8 Dual-Port Static RAM Document Number: 38-06002REV.ECN NO.IssueDateOrig. ofChange Description of Change**11016909/29/01SZV Change from Spec number: 38-00027 to 38-06002*A12225512/26/02RBI Power up requirements added to Maximum Ratings Information*B236751See ECN YDT Removed cross information from features section*C325936See ECN RUY Added pin definitions table, 52-pin PQFP package diagram and Pb-freeinformation*D393153See ECN YIM Added CY7C131-15JI to ordering informationAdded Pb-Free parts to ordering information:CY7C131-15JXI。

CY7C67300-100AI资料

CY7C67300 EZ-Host™ Programmable EmbeddedUSB Host/Peripheral ControllerTABLE OF CONTENTS1.0 INTRODUCTION (10)1.1 EZ-Host Features (10)2.0 TYPICAL APPLICATIONS (11)3.0 FUNCTIONAL OVERVIEW (11)3.1 Processor Core (11)3.1.1 Processor (11)3.1.2 Clocking (11)3.1.3 Memory (11)3.1.4 Interrupts (11)3.1.5 General Timers and Watchdog Timer (11)3.1.6 Power Management (11)4.0 INTERFACE DESCRIPTIONS (11)4.1 USB Interface (13)4.1.1 USB Features (13)4.1.2 USB Pins. (14)4.2 OTG Interface (14)4.2.1 OTG Features (14)4.2.2 OTG Pins. (14)4.3 External Memory Interface (14)4.3.1 External Memory Interface Features (14)4.3.2 External Memory Access Strobes (14)4.3.3 Page Registers (15)4.3.4 Merge Mode (15)4.3.5 Program Memory Hole Description (15)4.3.6 DMA to External Memory Prohibited (15)4.3.7 External Memory Interface Pins (16)4.3.8 External Memory Interface Block Diagrams (17)4.4 General Purpose I/O Interface (GPIO) (18)4.4.1 GPIO Description (18)4.4.2 Unused Pin Descriptions (18)4.5 UART Interface (18)4.5.1 UART Features (18)4.5.2 UART Pins. (18)4.6 I2C EEPROM Interface (18)4.6.1 I2C EEPROM Features (18)4.6.2 I2C EEPROM Pins. (18)4.7 Serial Peripheral Interface (18)4.7.1 SPI Features (19)4.7.2 SPI Pins (19)4.8 High-speed Serial Interface (19)4.8.1 HSS Features (19)4.8.2 HSS Pins (20)4.9 Programmable Pulse/PWM Interface (20)4.9.1 Programmable Pulse/PWM Features (20)4.9.2 Programmable Pulse/PWM Pins. (20)4.10 Host Port Interface (20)4.10.1 HPI Features (20)4.10.2 HPI Pins. (21)TABLE OF CONTENTS (continued)4.11 IDE Interface (21)4.11.1 IDE Features (22)4.11.2 IDE Pins (22)4.12 Charge Pump Interface (22)4.12.1 Charge Pump Features (23)4.12.2 Charge Pump Pins. (23)4.13 Booster Interface (23)4.13.1 Booster Pins. (24)4.14 Crystal Interface (25)4.14.1 Crystal Pins (25)4.15 Boot Configuration Interface (25)4.16 Operational Modes (26)4.16.1 Coprocessor Mode (26)4.16.2 Standalone Mode (26)5.0 POWER-SAVINGS AND RESET DESCRIPTION (27)5.1 Power-Savings Mode Description (27)5.2 Sleep (27)5.3 External (Remote) wakeup Source (27)5.4 Power-On-Reset Description (27)5.5 Reset Pin (27)5.6 USB Reset (27)6.0 MEMORY MAP (28)6.1 Mapping (28)6.1.1 Internal Memory (28)6.1.2 External Memory (28)7.0 REGISTERS (30)7.1 Processor Control Registers (30)7.1.1 CPU Flags Register [0xC000] [R] (30)7.1.2 Bank Register [0xC002] [R/W] (31)7.1.3 Hardware Revision Register [0xC004] [R] (31)7.1.4 CPU Speed Register [0xC008] [R/W] (32)7.1.5 Power Control Register [0xC00A] [R/W] (33)7.1.6 Interrupt Enable Register [0xC00E] [R/W] (35)7.1.7 Breakpoint Register [0xC014] [R/W] (36)7.1.8 USB Diagnostic Register [0xC03C] [R/W] (37)7.1.9 Memory Diagnostic Register [0xC03E] [W] (38)7.2 External Memory Registers (39)7.2.1 Extended Page n Map Register [R/W] (39)7.2.2 Upper Address Enable Register [0xC038] [R/W] (39)7.2.3 External Memory Control Register [0xC03A] [R/W] (40)7.3 Timer Registers (41)7.3.1 Watchdog Timer Register [0xC00C] [R/W] (41)7.3.2 Timer n Register [R/W] (42)7.4 General USB Registers (42)7.4.1 USB n Control Register [R/W] (42)7.5 USB Host Only Registers (45)7.5.1 Host n Control Register [R/W] (45)7.5.2 Host n Address Register [R/W] (46)TABLE OF CONTENTS (continued)7.5.3 Host n Count Register [R/W] (46)7.5.4 Host n Endpoint Status Register [R] (47)7.5.5 Host n PID Register [W] (48)7.5.6 Host n Count Result Register [R] (49)7.5.7 Host n Device Address Register [W] (50)7.5.8 Host n Interrupt Enable Register [R/W] (50)7.5.9 Host n Status Register [R/W] (52)7.5.10 Host n SOF/EOP Count Register [R/W] (53)7.5.11 Host n SOF/EOP Counter Register [R] (53)7.5.12 Host n Frame Register [R] (54)7.6 USB Device Only Registers (54)7.6.1 Device n Endpoint n Control Register [R/W] (55)7.6.2 Device n Endpoint n Address Register [R/W] (56)7.6.3 Device n Endpoint n Count Register [R/W] (57)7.6.4 Device n Endpoint n Status Register [R/W] (57)7.6.5 Device n Endpoint n Count Result Register [R/W] (59)7.6.6 Device n Port Select Register [R/W] (60)7.6.7 Device n Interrupt Enable Register [R/W] (60)7.6.8 Device n Address Register [W] (63)7.6.9 Device n Status Register [R/W] (63)7.6.10 Device n Frame Number Register [R] (65)7.6.11 Device n SOF/EOP Count Register [W] (66)7.7 OTG Control Registers (66)7.7.1 OTG Control Register [0xC098] [R/W] (66)7.8 GPIO Registers (68)7.8.1 GPIO Control Register [0xC006] [R/W] (68)7.8.2 GPIO n Output Data Register [R/W] (70)7.8.3 GPIO n Input Data Register [R] (70)7.8.4 GPIO n Direction Register [R/W] (71)7.9 IDE Registers (71)7.9.1 IDE Mode Register [0xC048] [R/W] (71)7.9.2 IDE Start Address Register [0xC04A] [R/W] (72)7.9.3 IDE Stop Address Register [0xC04C] [R/W] (72)7.9.4 IDE Control Register [0xC04E] [R/W] (73)7.9.5 IDE PIO Port Registers [0xC050 - 0xC06F] [R/W] (74)7.10 HSS Registers (74)7.10.1 HSS Control Register [0xC070] [R/W] (75)7.10.2 HSS Baud Rate Register [0xC072] [R/W] (77)7.10.3 HSS Transmit Gap Register [0xC074] [R/W] (77)7.10.4 HSS Data Register [0xC076] [R/W] (78)7.10.5 HSS Receive Address Register [0xC078] [R/W] (78)7.10.6 HSS Receive Counter Register [0xC07A] [R/W] (79)7.10.7 HSS Transmit Address Register [0xC07C] [R/W] (79)7.10.8 HSS Transmit Counter Register [0xC07E] [R/W] (79)7.11 HPI Registers (80)7.11.1 HPI Breakpoint Register [0x0140] [R] (80)7.11.2 Interrupt Routing Register [0x0142] [R] (81)7.11.3 SIEXmsg Register [W] (82)7.11.4 HPI Mailbox Register [0xC0C6] [R/W] (83)7.11.5 HPI Status Port [] [HPI: R] (83)TABLE OF CONTENTS (continued)7.12 SPI Registers (85)7.12.1 SPI Configuration Register [0xC0C8] [R/W] (86)7.12.2 SPI Control Register [0xC0CA] [R/W] (87)7.12.3 SPI Interrupt Enable Register [0xC0CC] [R/W] (89)7.12.4 SPI Status Register [0xC0CE] [R] (89)7.12.5 SPI Interrupt Clear Register [0xC0D0] [W] (90)7.12.6 SPI CRC Control Register [0xC0D2] [R/W] (91)7.12.7 SPI CRC Value Register [0xC0D4] [R/W] (92)7.12.8 SPI Data Register [0xC0D6] [R/W] (92)7.12.9 SPI Transmit Address Register [0xC0D8] [R/W] (93)7.12.10 SPI Transmit Count Register [0xC0DA] [R/W] (93)7.12.11 SPI Receive Address Register [0xC0DC [R/W] (93)7.12.12 SPI Receive Count Register [0xC0DE] [R/W] (94)7.13 UART Registers (94)7.13.1 UART Control Register [0xC0E0] [R/W] (94)7.13.2 UART Status Register [0xC0E2] [R] (95)7.13.3 UART Data Register [0xC0E4] [R/W] (96)7.14 PWM Registers (96)7.14.1 PWM Control Register [0xC0E6] [R/W] (97)7.14.2 PWM Maximum Count Register [0xC0E8] [R/W] (98)7.14.3 PWM n Start Register [R/W] (99)7.14.4 PWM n Stop Register [R/W] (99)7.14.5 PWM Cycle Count Register [0xC0FA] [R/W] (100)8.0 PIN DIAGRAM (101)9.0 PIN DESCRIPTIONS (101)10.0 ABSOLUTE MAXIMUM RATINGS (105)11.0 OPERATING CONDITIONS (105)12.0 CRYSTAL REQUIREMENTS (XTALIN, XTALOUT) (105)13.0 DC CHARACTERISTICS (105)13.1 USB Transceiver (106)14.0 AC TIMING CHARACTERISTICS (107)14.1 Reset Timing (107)14.2 Clock Timing (107)14.3 SRAM Read Cycle (108)14.4 SRAM Write Cycle (109)14.5 I2C EEPROM Timing (110)14.6 HPI (Host Port Interface) Write Cycle Timing (111)14.7 HPI (Host Port Interface) Read Cycle Timing (112)14.8 IDE Timing (113)14.9 HSS BYTE Mode Transmit (113)14.10 HSS Block Mode Transmit (113)14.11 HSS BYTE and BLOCK Mode Receive (113)14.12 Hardware CTS/RTS Handshake (114)15.0 REGISTERS SUMMARY (114)16.0 ORDERING INFORMATION (118)17.0 PACKAGE DIAGRAMS (118)LIST OF FIGURESFigure 1-1. Block Diagram (10)Figure 4-1. Page n Registers External Address Pins Logic (15)Figure 4-2. Interfacing to 64k × 8 Memory Array (17)Figure 4-3. Interfacing up to 256k × 16 for External Code/Data (17)Figure 4-4. Interfacing up to 512k × 8 for External Code/Data (17)Figure 4-5. Charge Pump (23)Figure 4-6. Power Supply Connection With Booster (24)Figure 4-7. Power Supply Connection Without Booster (24)Figure 4-8. Crystal Interface (25)Figure 4-9. Minimum Standalone Hardware Configuration – Peripheral Only (26)Figure 6-1. Memory Map (29)Figure 7-1. Processor Control Registers (30)Figure 7-2. CPU Flags Register (30)Figure 7-3. Bank Register (31)Figure 7-4. Revision Register (31)Figure 7-5. CPU Speed Register (32)Figure 7-6. Power Control Register (33)Figure 7-7. Interrupt Enable Register (35)Figure 7-8. Breakpoint Register (36)Figure 7-9. USB Diagnostic Register (37)Figure 7-10. Memory Diagnostic Register (38)Figure 7-11. External Memory Control Registers (39)Figure 7-12. Extended Page n Map Register (39)Figure 7-13. External Memory Control Register (39)Figure 7-14. External Memory Control Register (40)Figure 7-15. Timer Registers (41)Figure 7-16. Watchdog Timer Register (41)Figure 7-17. Timer n Register (42)Figure 7-18. General USB Registers (42)Figure 7-19. USB n Control Register (43)Figure 7-20. USB Host Only Register (45)Figure 7-21. Host n Control Register (45)Figure 7-22. Host n Address Register (46)Figure 7-23. Host n Count Register (46)Figure 7-24. Host n Endpoint Status Register (47)Figure 7-25. Host n PID Register (49)Figure 7-26. Host n Count Result Register (49)Figure 7-27. Host n Device Address Register (50)Figure 7-28. Host n Interrupt Enable Register (50)Figure 7-29. Host n Status Register (52)Figure 7-30. Host n SOF/EOP Count Register (53)Figure 7-31. Host n SOF/EOP Counter Register (54)Figure 7-32. Host n Frame Register (54)Figure 7-33. USB Device Only Registers (55)Figure 7-34. Device n Endpoint n Control Register (55)Figure 7-35. Device n Endpoint n Address Register (57)Figure 7-36. Device n Endpoint n Count Register (57)Figure 7-37. Device n Endpoint n Status Register (58)Figure 7-38. Device n Endpoint n Count Result Register (60)LIST OF FIGURES (continued)Figure 7-39. Device n Port Select Register (60)Figure 7-40. Device n Interrupt Enable Register (61)Figure 7-41. Device n Address Register (63)Figure 7-42. Device n Status Register (63)Figure 7-43. Device n Frame Number Register (65)Figure 7-44. Device n SOF/EOP Count Register (66)Figure 7-45. OTG Registers (66)Figure 7-46. OTG Control Register (66)Figure 7-47. GPIO Registers (68)Figure 7-48. GPIO Control Register (68)Figure 7-49. GPIO n Output Data Register (70)Figure 7-50. GPIO n Input Data Register (70)Figure 7-51. GPIO n Direction Register (71)Figure 7-52. IDE Registers (71)Figure 7-53. IDE Mode Register (71)Figure 7-54. IDE Start Address Register (72)Figure 7-55. IDE Stop Address Register (72)Figure 7-56. IDE Control Register (73)Figure 7-57. HSS Registers (74)Figure 7-58. HSS Control Register (75)Figure 7-59. HSS Baud Rate Register (77)Figure 7-60. HSS Transmit Gap Register (77)Figure 7-61. HSS Data Register (78)Figure 7-62. HSS Receive Address Register (78)Figure 7-63. HSS Receive Counter Register (79)Figure 7-64. HSS Transmit Address Register (79)Figure 7-65. HSS Transmit Counter Register (79)Figure 7-66. HPI Registers (80)Figure 7-67. HPI Breakpoint Register (80)Figure 7-68. Interrupt Routing Register (81)Figure 7-69. SIEXmsg Register (82)Figure 7-70. HPI Mailbox Register (83)Figure 7-71. HPI Status Port (83)Figure 7-72. SPI Registers (85)Figure 7-73. SPI Configuration Register (86)Figure 7-74. SPI Control Register (87)Figure 7-75. SPI Interrupt Enable Register (89)Figure 7-76. SPI Status Register (89)Figure 7-77. SPI Interrupt Clear Register (90)Figure 7-78. SPI CRC Control Register (91)Figure 7-79. SPI CRC Value Register (92)Figure 7-80. SPI Data Register (92)Figure 7-81. SPI Transmit Address Register (93)Figure 7-82. SPI Transmit Count Register (93)Figure 7-83. SPI Receive Address Register (93)Figure 7-84. SPI Receive Count Register (94)Figure 7-85. UART Registers (94)Figure 7-86. UART Control Register (94)Figure 7-87. UART Status Register (95)LIST OF FIGURES (continued)Figure 7-88. UART Data Register (96)Figure 7-89. PWM Registers (96)Figure 7-90. PWM Control Register (97)Figure 7-91. PWM Maximum Count Register (98)Figure 7-92. PWM n Start Register (99)Figure 7-93. PWM n Stop Register (99)Figure 7-94. PWM Cycle Count Register (100)Figure 8-1. EZ-Host Pin Diagram (101)LIST OF TABLESTable 4-1. Interface Options for GPIO Pins (12)Table 4-2. Interface Options for External Memory Bus Pins (12)Table 4-3. USB Port Configuration Options (13)Table 4-4. USB Interface Pins (14)Table 4-5. OTG Interface Pins (14)Table 4-6. External Memory Interface Pins (16)Table 4-7. UART Interface Pins (18)Table 4-8. I2C EEPROM Interface Pins (18)Table 4-9. SPI Interface Pins (19)Table 4-10. HSS Interface Pins (20)Table 4-11. PWM Interface Pins (20)Table 4-12. HPI Interface Pins (21)Table 4-13. HPI Addressing (21)Table 4-14. IDE Throughput (22)Table 4-15. IDE Interface Pins (22)Table 4-16. Charge Pump Interface Pins (23)Table 4-17. Charge Pump Interface Pins (24)Table 4-18. Crystal Pins (25)Table 4-19. Boot Configuration Interface (25)Table 5-1. Wakeup Sources (27)Table 7-1. Bank Register Example (31)Table 7-2. CPU Speed Definition (32)Table 7-3. Force Select Definition (38)Table 7-4. Memory Arbitration Select (38)Table 7-5. Period Select Definition (41)Table 7-6. USB Data Line Pull-up and Pull-down Resistors (44)Table 7-7. Port A/B Force D± State (44)Table 7-8. Port Select Definition (47)Table 7-9. PID Select Definition (49)Table 7-10. Mode Select Definition (69)Table 7-11. Mode Select Definition (72)Table 7-12. IDE PIO Port Registers (74)Table 7-13. Scale Select Field Definition for SCK Frequency (86)Table 7-14. CRC Mode Definition (91)Table 7-15. UART Baud Select Definition (95)Table 7-16. Prescaler Select Definition (97)Table 9-1. Pin Descriptions (101)Table 12-1. Crystal Requirements (105)Table 13-1. DC Characteristics (105)Table 13-2. DC Characteristics: Charge Pump (106)Table 15-1. Register Summary (114)Table 16-1. Ordering Information (118)1.0 INTRODUCTIONEZ-Host™ (CY7C67300) is Cypress Semiconductor’s first full-speed, low-cost multiport host/peripheral controller. EZ-Host is designed to easily interface to most high-performance CPUs to add USB host functionality. EZ-Host has its own 16-bit RISC processor to act as a coprocessor or operate in standalone mode. EZ-Host also has a programmable I/O interface block allowing a wide range of interface options.Figure 1-1. Block Diagram1.1EZ-Host Features•Single-chip programmable USB dual-role (Host/Peripheral) controller with two configurable Serial Interface Engines (SIEs) and four USB ports•Support for USB On-The-Go (OTG) protocol•On-chip 48-MHz 16-bit processor with dynamically switchable clock speed•Configurable I/O block supporting a variety of I/O options or up to 32 bits of General Purpose I/O (GPIO)•4K x 16 internal masked ROM containing built-in BIOS that supports a communication ready state with access to I2C EEPROM Interface, external ROM, UART, or USB•8K x 16 internal RAM for code and data buffering•Extended memory interface port for external SRAM and ROM•16-bit parallel Host Port Interface (HPI) with a DMA/Mailbox data path for an external processor to directly access all of the on-chip memory and control on-chip SIEs•Fast serial port supports from 9600 baud to 2.0 Mbaud•SPI support in both master and slave•On-chip 16-bit DMA/Mailbox data path interface•Supports 12-MHz external crystal or clock•3.3V operation•Package option — 100-pin TQFP2.0 Typical ApplicationsEZ-Host is a very powerful and flexible dual role USB controller that supports a wide variety of applications. It is primarily intended to enable host capability in applications such as:•Set-top boxes•Printers•KVM switches•Kiosks•Automotive applications•Wireless access points.3.0 Functional Overview3.1Processor Core3.1.1ProcessorEZ-Host has a general-purpose 16-bit embedded RISC processor that runs at 48 MHz.3.1.2ClockingEZ-Host requires a 12-MHz source for clocking. Either an external crystal or TTL level oscillator may be used. EZ-Host has an internal PLL that produces a 48-MHz internal clock from the 12-MHz source.3.1.3MemoryEZ-Host has a built-in 4K × 16 masked ROM and an 8K × 16 internal RAM. The masked ROM contains the EZ-Host BIOS. The internal RAM can be used for program code or data.3.1.4InterruptsEZ-Host provides 128 interrupt vectors. The first 48 vectors are hardware interrupts and the following 80 vectors are software interrupts.3.1.5General Timers and Watchdog TimerEZ-Host has two built-in programmable timers and a Watchdog timer. All three timers can generate an interrupt to the EZ-Host.3.1.6Power ManagementEZ-Host has one main power saving mode, Sleep. Sleep mode pauses all operations and provides the lowest power state.4.0 Interface DescriptionsEZ-Host has a wide variety of interface options for connectivity. With several interface options available, EZ-Host can act as a seamless data transport between many different types of devices.See Table4-1 and Table4-2 to understand how the interfaces share pins and which can coexist. It should be noted that some interfaces have more then one possible port location selectable through the GPIO Control Register [0xC006]. Below are some general guidelines:•HPI and IDE interfaces are mutually exclusive.•If 16-bit external memory is required, then HSS and SPI default locations must be used.•I2C EEPROM and OTG do not conflict with any interfaces.Notes:1.Default interface location.2.Alternate interface location.Table 4-1. Interface Options for GPIO Pins GPIO Pins HPIIDEPWMHSSSPIUARTI2C OTGGPIO31SCL/SDA GPIO30SCL/SDAGPIO29OTGIDGPIO28TX [1]GPIO27RX [1]GPIO26PWM3CTS [1]GPIO25GPIO24INT IOREADY GPIO23nRD IOR GPIO22nWR IOW GPIO21nCS GPIO20A1CS1GPIO19A0CS0GPIO18A2PWM2RTS [1]GPIO17A1PWM1RXD [1]GPIO16A0PWM0TXD [1]GPIO15D15D15GPIO14D14D14GPIO13D13D13GPIO12D12D12GPIO11D11D11MOSI [1]GPIO10D10D10SCK [1]GPIO9D9D9nSSI [1]GPIO8D8D8MISO [1]GPIO7D7D7TX [2]GPIO6D6D6RX [2]GPIO5D5D5GPIO4D4D4GPIO3D3D3GPIO2D2D2GPIO1D1D1GPIO0D0D0Table 4-2. Interface Options for External Memory Bus Pins MEM Pins HPIIDEPWMHSS SPIUARTI2COTGD15CTS [2]D14RTS [2]D13RXD [2]D12TXD [2]D11MOSI [2]D10SCK [2]D9nSSI [2]D8MISO [2]D[7:0]A[18:0]CONTROL4.1USB InterfaceEZ-Host has two built-in Host/Peripheral SIEs and four USB transceivers that meet the USB 2.0 specification requirements for full and low speed (high speed is not supported). In Host mode, EZ-Host supports four downstream ports, each support control, interrupt, bulk, and isochronous transfers. In Peripheral mode, EZ-Host supports one peripheral port with eight endpoints for each of the two SIEs. Endpoint 0 is dedicated as the control endpoint and only supports control transfers. Endpoints 1 though 7 support Interrupt, Bulk (up to 64 Bytes/packet), or Isochronous transfers (up to 1023 Bytes/packet size). EZ-Host also supports a combi-nation of Host and Peripheral ports simultaneously as shown in Table4-3.Table 4-3. USB Port Configuration OptionsPort Configurations Port 1A Port 1B Port 2A Port 2BOTG OTG–––OTG + 2 Hosts OTG–Host HostOTG + 1 Host OTG–Host–OTG + 1 Host OTG––HostOTG + 1 Peripheral OTG–Peripheral–OTG + 1 Peripheral OTG––Peripheral4 Hosts Host Host Host Host3 Hosts Any Combination of Ports2 Hosts Any Combination of Ports1 Host Any Port2 Hosts + 1 Peripheral Host Host Peripheral–2 Hosts + 1 Peripheral Host Host–Peripheral2 Hosts + 1 Peripheral Peripheral–Host Host2 Hosts + 1 Peripheral–Peripheral Host Host1 Host + 1 Peripheral Host–Peripheral–1 Host + 1 Peripheral Host––Peripheral1 Host + 1 Peripheral–Host–Peripheral1 Host + 1 Peripheral–Host Peripheral–1 Host + 1 Peripheral Peripheral–Host–1 Host + 1 Peripheral Peripheral––Host1 Host + 1 Peripheral–Peripheral–Host1 Host + 1 Peripheral–Peripheral Host–2 Peripherals Peripheral–Peripheral–2 Peripherals Peripheral––Peripheral2 Peripherals–Peripheral–Peripheral2 Peripherals–Peripheral Peripheral–1 Peripheral Any Port4.1.1USB Features•USB 2.0-compliant for full and low speed•Up to four downstream USB host ports•Up to two upstream USB peripheral ports•Configurable endpoint buffers (pointer and length), must reside in internal RAM•Up to eight available peripheral endpoints (one control endpoint)•Supports Control, Interrupt, Bulk, and Isochronous transfers•Internal DMA channels for each endpoint•Internal pull-up and pull-down resistors•Internal Series termination resistors on USB data lines4.1.2USB Pins.Table 4-4. USB Interface PinsPin Name Pin NumberDM1A22DP1A23DM1B18DP1B19DM2A9DP2A10DM2B4DP2B54.2OTG InterfaceEZ-Host has one USB port that is compatible with the USB On-The-Go supplement to the USB 2.0 specification. The USB OTG port has a various hardware features to support Session Request Protocol (SRP) and Host Negotiation Protocol (HNP). OTG is only supported on USB PORT 1A.4.2.1OTG Features•Internal Charge Pump to supply and control VBUS•VBUS Valid Status (above 4.4V)•VBUS Status for 2.4V< VBUS <0.8V•ID Pin Status•Switchable 2KΩ internal discharge resistor on VBUS•Switchable 500Ω internal Pull-up resistor on VBUS•Individually switchable internal Pull-up and Pull-down resistors on the USB Data Lines4.2.2OTG Pins.Table 4-5. OTG Interface PinsPin Name Pin NumberDM1A22DP1A23OTGVBUS11OTGID41CSwitchA13CSwitchB124.3External Memory InterfaceEZ-Host provides a robust interface to a wide variety of external memory arrays. All available external memory array locations can contain either code or data. The CY16 RISC processor directly addresses a flat memory space from 0x0000 to 0xFFFF. 4.3.1External Memory Interface Features•Supports 8-bit or 16-bit SRAM or ROM•SRAM or ROM can be used for code or data space•Direct addressing of SRAM or ROM•Two external memory mapped page registers4.3.2External Memory Access StrobesAccess to external memory is sampled asynchronously on the rising edge of strobes with a minimum of one wait state cycle. Up to seven wait state cycles may be inserted for external memory access. Each additional wait state cycle stretches the external memory access time by 21 nsec. An external memory device with 12-nsec access time is necessary to support 48-MHz code execution.4.3.3Page RegistersEZ-Host allows extended data or program code to be stored in external SRAM, or ROM. The total size of extended memory can be up to 512K bytes. The CY16 processor can access extended memory via two address regions of 0x8000-0x9FFF and 0xA000-0xBFFF. The page register 0xC018 can be used to control the address region 0x8000-0x9FFF and the page register 0xC01A controls the address region of 0xA000-0xBFFF.Figure4-1 illustrates that when the nXMEMSEL pin is asserted the upper CPU address pins are driven by the contents of the Page x Registers.Figure 4-1. Page n Registers External Address Pins Logic4.3.4Merge ModeMerge modes enabled through the External Memory Control Register [0xC03] allow combining of external memory regions in accordance with the following:•nXMEMSEL is active from 0x8000 to 0xBFFF•nXRAMSEL is active from 0x4000 to 0x7FFF when RAM Merge is disabled; nXRAMSEL is active from 0x4000 to 0xBFFF when RAM Merge is enabled•nXROMSEL is active from 0xC100 to 0xDFFF when ROM Merge is disabled; nXROMSEL is active from 0x8000 to 0xDFFF (excluding the 0xC000 to 0xC0FF area) when ROM Merge is enabled4.3.5Program Memory Hole DescriptionCode residing in the 0xC000-0xC0FF address space is not accessible by the cpu.4.3.6DMA to External Memory ProhibitedEZ-Host supports an internal DMA engine to rapidly move data between different functional blocks within the chip. This DMA engine is used for SIE1, SIE2, HPI, SPI, HSS, and IDE but it can only transfer data between the specified block and internal RAM or ROM. Setting up the DMA engine to transfer to or from an external memory space might result in internal RAM data corruption because the hardware (i.e HSS/HPI/SIE1/SIE2/IDE) does not explicitly check the address range. For example, setting up a DMA transfer to external address 0x8000 might result in a DMA transfer into address 0x0000.External Memory Related Resource Considerations:•By default A[18:15] are not available for general addressing and are driven high on power up. The Upper Address Enable Register must be written appropriately to enable A[18:15] for general addressing purposes.•47k ohm external pull-up on A15-pin for 12-MHz crystal operation.•During the 3-msec BIOS boot procedure the CPU external memory bus is active.•ROM boot load value 0xC3B6 located at 0xC100.•HPI, HSS, SPI, SIE1, SIE2, and IDE can't DMA to external memory arrays.•Page 1 banking is always enabled and is in effect from 0x8000 to 0x9FFF.•Page 2 banking is always enabled and is in effect from 0xA000 to 0xBFFF.•CPU memory bus strobes may wiggle when chip selects are inactive.4.3.7External Memory Interface PinsTable 4-6. External Memory Interface PinsPin Name Pin Number nWR64nRD62 nXMEMSEL (optional nCS)34nXROMSEL (ROM nCS)35nXRAMSEL (RAM nCS)36A1896A1795A1697A1538A1433A1332A1231A1130A1027A925A824A720A617A58A47A33A22A11nBEL/A099nBEH98D1567D1468D1369D1270D1171D1072D973D874D776D677D578D479D380D281D182D0834.3.8External Memory Interface Block DiagramsFigure4-2 illustrates how to connect a 64k × 8 memory array (SRAM/ROM) to the EZ-Host external memory interface.Figure 4-2. Interfacing to 64k × 8 Memory ArrayFigure4-3 illustrates the interface for connecting a 16-bit ROM or 16-bit RAM to the EZ-Host external memory interface. In 16-bit mode, up to 256K words of external ROM or RAM are supported. Note that the Address lines do not map directly.Figure 4-3. Interfacing up to 256k × 16 for External Code/DataFigure4-4 illustrates the interface for connecting an 8-bit ROM or 8-bit RAM to the EZ-Host external memory interface. In 8-bit mode, up to 512K bytes of external ROM or RAM are supported.Figure 4-4. Interfacing up to 512k × 8 for External Code/Data4.4General Purpose I/O Interface (GPIO)EZ-Host has up to 32 GPIO signals available. Several other optional interfaces use GPIO pins as well and may reduce the overall number of available GPIOs.4.4.1GPIO DescriptionAll Inputs are sampled asynchronously with state changes occurring at a rate of up to two 48-MHZ clock cycles. GPIO pins are latched directly into registers, a single flip-flop.4.4.2Unused Pin DescriptionsUnused USB pins should be three-stated with the D+ line pulled high through the internal pull-up resistor and the D- line pulled low through the internal pull-down resistor.Unused GPIO pins should be configured as outputs and driven low.4.5UART InterfaceEZ-Host has a built-in UART interface. The UART interface supports data rates from 900 to 115.2K baud. It can be used as a development port or for other interface requirements. The UART interface is exposed through GPIO pins.4.5.1UART Features•Supports baud rates of 900 to 115.2K•8-N-14.5.2UART Pins.Table 4-7. UART Interface PinsPin Name Pin NumberTX42RX434.6I2C EEPROM InterfaceEZ-Host provides a master only I2C interface for external serial EEPROMs. The serial EEPROM can be used to store application specific code and data. This I2C interface is only to be used for loading code out of EEPROM, it is not a general I2C interface. The I2C EEPROM interface is a BIOS implementation and is exposed through GPIO pins. Please refer to the BIOS documentation for additional details on this interface.4.6.1I2C EEPROM Features•Supports EEPROMs up to 64KB (512K bit)•Auto-detection of EEPROM size4.6.2I2C EEPROM Pins.Table 4-8. I2C EEPROM Interface PinsPin Name Pin NumberSMALL EEPROMSCK39SDA40LARGE EEPROMSCK40SDA394.7Serial Peripheral InterfaceEZ-Host provides a SPI interface for added connectivity. EZ-Host may be configured as either an SPI master or SPI slave. The SPI interface can be exposed through GPIO pins or the External Memory port.。

USB控制芯片cy7c68013中文手册

■ 单芯片集成 USB 2.0 收发器、智能串行接口引擎 (SIE) 和增强型 8051 微处理器
■ 适用性、外观和功能均与 FX2 兼容 ❐ 引脚兼容 ❐ 目标代码兼容 ❐ 功能兼容（FX2LP 是超集）
■ 超低功耗：ICC 在任何模式下都不超过 85 mA ❐ 适合总线和电池供电的应用
■ 软件：8051 代码运行介质： ❐ 内部 RAM，通过 USB 下载 ❐ 内部 RAM，从 EEPROM 加载 ❐ 外部存储设备（128 引脚封装）
内部ram通过usb下载内部ram从eeprom加载外部存储设备128引脚封装数据ram四个可编程的bulkinterruptisochronous端点附加的可编程bulkinterrupt64位端点16位外部数据接口可生成智能介质标准错误校正码ecc通用可编程接口generalprogrammableinterfacegpif支持多个readyrdy输入和controlctl输出符合行业标准的集成增强型805148mhz24mhz12mhzcpu操作两个usart33v工作电压容限输入为5v向量化usb中断和gpiffifo中断分离的control传输设置部分和数据部分数据缓冲控制器在100400khz下运行集成的四个先进先出fifo缓冲集成胶合逻辑和fifo有助于降低系统成本16位总线之间的自动转换易于与asicdspic相连的接口有商业和工业温度等级供选择除vfbga外的所有封装feedbackcy7c68013acy7c68014acy7c68015acy7c68016a文件编号
表 1. 特殊功能寄存器
x
8x
0
IOA
1
SP
2
DPL0
3
DPH0
4
DPL1
5

CY7C135-25JC中文资料

4K x 8 Dual-Port Static RAM and 4K x 8 Dual-PortSRAM with SemaphoresCY7C135CY7C1342Features•True Dual-Ported memory cells which allow simulta-neous reads of the same memory location •4K x 8 organization•0.65-micron CMOS for optimum speed/power •High-speed access: 15 ns•Low operating power: I CC = 160 mA (max.)•Fully asynchronous operation •Automatic power-down•Semaphores included on the 7C1342 to permit software handshaking between ports •Available in 52-pin PLCCFunctional DescriptionThe CY7C135 and CY7C1342 are high-speed CMOS 4K x 8 dual-port static RAMs. The CY7C1342 includes semaphores that provide a means to allocate portions of the dual-port RAM or any shared resource. Two ports are provided permitting in-dependent, asynchronous access for reads and writes to any location in memory. Application areas include interproces-sor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory.Each port has independent control pins: chip enable (CE), read or write enable (R/W), and output enable (OE). The CY7C135 is suited for those systems that do not require on-chip arbitration or are intolerant of wait states. Therefore, the user must be aware that simultaneous access to a location is possible. Semaphores are offered on the CY7C1342 to as-sist in arbitrating between ports. The semaphore logic is com-prised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indi-cates that a shared resource is in use. An automatic pow-er-down feature is controlled independently on each port by a chip enable (CE) pin or SEM pin (CY7C1342 only).The CY7C135 and CY7C1342 are available in 52-pin PLCC.1342–1R/W L CE L OE LA 11L A 0LA 0RA 11R R/W R CE R OE RCE R OE R CE L OE L R/W LR/W RI/O 7L I/O 0LI/O 7R I/O 0RSEMAPHORE ARBITRATION (7C1342only)CONTROL I/O CONTROLI/O MEMORY ARRAYADDRESS DECODERADDRESS DECODER(7C1342only)SEMLSEMRLogic Block Diagram(7C1342only)Selection Guide7C135–157C1342–157C135–207C1342–207C135–257C1342–257C135–357C1342–357C135–557C1342–55Maximum Access Time (ns)1520253555Maximum Operating Current (mA)Commercial 220190180160160Maximum Standby Current for I SB1(mA)Commercial 6050403030Pin ConfigurationsA 11R 1V C C7C1342Top ViewPLCC 8910111213141516171819204645444342414039383736353421222324252627282930313233765432525150494847I /O I /O I /O I /O I /O I /O I /O I /O I /O I /O I /O 4L 5L 6L 7L0R 1R 2R 3R 4R 5R 6RN C G N D O E S E M A R /W C E R /W S E M 0LL L L L C E RR RA 10LA 10ROE R A 0R A 1R A 2R A 3R A 4R A 5R A 6R A 7R A 8R A 9R NC I/O 7RA 1LA 2L A 3L A 4L A 5L A 6L A 7L A 8L A 9L I/O 0L I/O 1L I/O 2L I/O 3L1V C C7C135Top ViewPLCC 8910111213141516171819204645444342414039383736353421222324252627282930313233765432525150494847I /O I /O I /O I /O I /O I /O I /O I /O I /O I /O I /O 4L 5L 6L 7L0R 1R 2R 3R 4R 5R 6RN C G N D O E N /C A R /W C E R /W 0LL L L C E R RA 10LA 10RR A 0R A 1R A 2R A 3R A 4R A 5R A 6R A 7R A 8R A 9R NC I/O 7RA 1LA 2L A 3L A 4L A 5L A 6L A 7L A 8L A 9L I/O 0L I/O 1L I/O 2L I/O 3LN /CA 11R A 11LA 11L1342–31342–4Pin DefinitionsLeft Port Right Port DescriptionA 0L–11L A 0R–11R Address Lines CE L CE R Chip Enable OE L OE R Output Enable R/W L R/W R Read/Write EnableSEM L(CY7C1342 only)SEM R(CY7C1342 only)Semaphore Enable. When asserted LOW, allows access to eight semaphores. The three least significant bits of the address lines will determine which semaphore to write or read. The I/O 0 pin is used when writing to a semaphore. Semaphores are requested by writing a 0 into the respective location.Maximum Ratings[1]Storage Temperature ..................................–65°C to +150°C Ambient Temperature withPower Applied..............................................–55°C to +125°C Supply Voltage to Ground Potential(Pin 48 to Pin 24)............................................–0.5V to +7.0V DC Voltage Applied to Outputsin High Z State................................................–0.5V to +7.0V DC Input Voltage[2].........................................–3.0V to +7.0V Static Discharge Voltage...........................................> 2001V (per MIL-STD-883, Method 3015)Latch-Up Current....................................................> 200 mA Operating RangeRangeAmbientTemperature V CC Commercial0°C to +70°C 5V ± 10%Industrial–40°C to +85°C5V ± 10%Electrical Characteristics Over the Operating Range[4]7C135–15 7C1342–157C135–207C1342–27C135–257C1342–25Parameter Description Test Conditions Min.Max.Min.Max.Min.Max.UnitV OH Output HIGH Voltage V CC = Min., I OH = –4.0 mA 2.4 2.4 2.4V V OL Output LOW Voltage V CC = Min., I OL = 4.0 mA0.40.40.4V V IH Input HIGH Voltage 2.2 2.2 2.2V V IL Input LOW Voltage0.80.80.8V I IX Input Load Current GND ≤ V I≤ V CC–10+10–10+10–10+10µA I OZ Output Leakage Current Outputs Disabled,GND ≤ V O≤ V CC–10+10–10+10–10+10µAI CC Operating Current V CC = Max.,I OUT = 0 mA Com’l220190180mA Ind.190I SB1Standby Current(Both Ports TTL Levels)CE L and CE R≥ V IH,f = f MAX[5]Com’l605040mAInd.50I SB2Standby Current(One Port TTL Level)CE L and CE R≥ V IH,f = f MAX[5]Com’l130120110mAInd.120I SB3Standby Current(Both Ports CMOS Levels)Both Ports CE and CE R≥V CC – 0.2V,V IN≥ V CC – 0.2Vor V IN≤ 0.2V, f = 0[5]Com’l151515mAInd.30I SB4Standby Current(One Port CMOS Level)One Port CE L orCE R≥ V CC – 0.2V,V IN≥V CC – 0.2V or V IN≤ 0.2V,Active Port Outputs, f =f MAX[5]Com’l125115100mAInd.115Notes:1.The Voltage on any input or I/O pin cannot exceed the power pin during power-up.2.Pulse width < 20 ns.3.T A is the “instant on” case temperature.4.See the last page of this specification for Group A subgroup testing information.5.f MAX = 1/t RC = All inputs cycling at f = 1/t RC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby I SB3.Electrical Characteristics Over the Operating Range [4](continued)7C135–357C1342–357C135–557C1342–55Parameter DescriptionTest ConditionsMin.Max.Min.Max.Unit V OH Output HIGH Voltage V CC = Min., I OH = –4.0 mA 2.42.4V V OL Output LOW VoltageV CC = Min., I OL = 4.0 mA0.40.4V V IH 2.22.2V V IL Input LOW Voltage 0.80.8V I IX Input Load Current GND ≤ V I ≤ V CC–10+10–10+10µA I OZ Output Leakage Current Outputs Disabled, GND ≤ V O ≤ V CC –10+10–10+10µA I CC Operating Current V CC = Max., I OUT = 0 mA Com’l 160160mAV CC = Max., I OUT = 0 mA Ind.180180I SB1Standby Current(Both Ports TTL Levels)CE L and CE R ≥ V IH , f = f MAX[5]Com’l 3030mA Ind.4040I SB2Standby Current (One Port TTL Level)CE L and CE R ≥ V IH , f = f MAX [5]Com’l 100100mA Ind.110110I SB3Standby Current (Both Ports CMOS Levels)Both Ports CE and CE R ≥ V CC – 0.2V , V IN ≥ V CC – 0.2Vor V IN ≤ 0.2V , f = 0[5]Com’l 1515mA Ind.3030I SB4Standby Current(One Port CMOS Level)One Port CE L or CE R ≥ V CC – 0.2V , V IN ≥ V CC – 0.2V or V IN ≤ 0.2V , Active Port Outputs, f = f MAX [5]Com’l 9090mA Ind.100100Capacitance [6]ParameterDescriptionTest ConditionsMax.Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V CC = 5.0V10pF C OUTOutput Capacitance10pFAC Test Loads and WaveformsNote:6.Tested initially and after any design or process changes that may affect these parameters.3.0V GND90%90%10%≤3ns≤3ns10%ALL INPUT PULSES(a) Normal Load (Load 1)R1=893Ω5VOUTPUTR1=347ΩC=30pFR TH =250ΩV TH =1.4VOUTPUTC=30pF(b) Thévenin Equivalent (Load 1)(c) Three-State Delay (Load 3)R TH =250ΩV XOUTPUTC =5pF1342–51342–61342–71342–8Switching Characteristics Over the Operating Range[7, 8]7C135–15 7C1342–157C135–207C1342–207C135–257C1342–257C135–357C1342–357C135–557C1342–55Parameter Description Min.Max.Min.Max.Min.Max.Min.Max.Min.Max.Unit READ CYCLEt RC Read Cycle Time1520253555ns t AA Address to Data Valid1520253555ns t OHA Output Hold FromAddress Change33333ns t ACE CE LOW to Data Valid1520253555ns t DOE OE LOW to Data Valid1013152025ns t LZOE[9,10,11]OE Low to Low Z33333ns t HZOE[9,10,11]OE HIGH to High Z1013152025ns t LZCE[9,10,11]CE LOW to Low Z33333ns t HZCE[9,10,11]CE HIGH to High Z1013152025ns t PU[11]CE LOW to Power Up00000ns t PD[11]CE HIGH to Power Down1520253555ns WRITE CYCLEt WC Write Cycle Time1520253555ns t SCE CE LOW to Write End1215203050ns t AW Address Set-Up to Write End1215203050ns t HA Address Hold from Write End22222ns t SA Address Set-Up to Write Start00000ns t PWE Write Pulse Width1215202550ns t SD Data Set-Up to Write End1013151525ns t HD Data Hold from Write End00000ns t HZWE[10,11]R/W LOW to High Z1013152025ns t LZWE[10,11]R/W HIGH to Low Z33333ns t WDD[12]Write Pulse to Data Delay3040506070ns t DDD[12]Write Data Valid to ReadData Valid2530303540ns SEMAPHORE TIMING[13]t SOP SEM Flag Update Pulse(OE or SEM)1010101515ns t SWRD SEM Flag Write to Read Time55555ns t SPS SEM Flag Contention Window55555ns Notes:7.See the last page of this specification for Group A subgroup testing information.8.Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specifiedI OL/I OH and 30-pF load capacitance.9.At any given temperature and voltage condition for any given device, t HZCE is less than t LZCE and t HZOE is less than t LZOE.10.Test conditions used are Load 3.11.This parameter is guaranteed but not tested.12.For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.13.Semaphore timing applies only to CY7C1342.Switching WaveformsNotes:14.R/W is HIGH for read cycle.15.Device is continuously selected, CE = V IL and OE = V IL .16.Address valid prior to or coincident with CE transition LOW.17.CE L = CE R =LOW; R/W L = HIGHt RCt AAt OHADATA VALIDPREVIOUS DATA VALIDDATA OUTADDRESSEither Port Address Access1342–9Read Cycle No. 1[14,15]t ACEt LZOEt DOEt HZOEt HZCEDATA VALIDDATA OUTSEMor CE OEt LZCEt PUI CC I SBt PDEither Port CE/OE Access1342–10Read Cycle No. 2[14,16][13]VALIDt DDDt WDDMATCHMATCHR/W RDATA INRDATA OUTLt wcADDRESS Rt PWEVALIDtSDtHDADDRESS L1342–11Read Timing with Port-to-Port [17]Notes:18.terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.19.R/W must be HIGH during all address transactions.20.If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t PWE or (t HZWE + t SD ) to allow the I/O drivers to turn off and data to be placed on thebus for the required t SD . If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as short as the specified t PWE .21.Switching Waveforms (continued)t AWt WCDATA VALIDHIGH IMPEDANCEt SCEt SAt PWEt HDt SDt HAt HZOEtLZOESEM OR CER/WADDRESS OEDATA OUTDATA IN1342–12Write Cycle No. 1: OE Three-States Data I/Os (Either Port)[18,19,20][13]t AWt WCt SCEt SAt PWEt HDt SDt HZWEt HAHIGH IMPEDANCESEM OR CER/WADDRESSDATA OUTDATA INt LZWEDATA VALID1342–13Write Cycle No. 2:R/W Three-States Data I/Os (Either Port)[19, 21][13]Notes:22.CE = HIGH for the duration of the above timing (both write and read cycle).23.I/O 0R = I/O 0L = LOW (request semaphore); CE R = CE L = HIGH.24.Semaphores are reset (available to both ports) at cycle start.25.If t SPS is violated, it is guaranteed that only one side will gain access to the semaphore.Switching Waveforms (continued)t SOPt AASEMR/WOEI/O 0VALID ADDRESSVALID ADDRESSt HDDATA IN VALIDDATA OUT VALIDt OHAA 0–A 2t AWt HAt ACEt SOPt SCEt SDt SAt PWEt SWRDt DOEWRITE CYCLEREAD CYCLE1342–14Semaphore Read After Write Timing, Either Side (CY7C1342 only)[22]MATCHt SPSA 0L –A 2LMATCHR/W L SEM LA 0R –A 2RR/W R SEM R1342–15Timing Diagram of Semaphore Contention (CY7C1342 only)[23,24,25]ArchitectureThe CY7C135 consists of an array of 4K words of 8 bits each of dual-port RAM cells, I/O and address lines, and control sig-nals (CE, OE, R/W). Two semaphore control pins exist for the CY7C1342 (SEM L/R).Functional DescriptionWrite OperationData must be set up for a duration of t SD before the rising edge of R/W in order to guarantee a valid write. Since there is no on-chip arbitration, the user must be sure that a specific loca-tion will not be accessed simultaneously by both ports or erro-neous data could result. A write operation is controlled by ei-ther the OE pin (see Write Cycle No. 1 timing diagram) or the R/W pin (see Write Cycle No. 2 timing diagram). Data can be written t HZOE after the OE is deasserted or t HZWE after the falling edge of R/W. Required inputs for write operations are summarized in Table 1.If a location is being written to by one port and the opposite port attempts to read the same location, a port-to-port flowthrough delay is met before the data is valid on the output. Data will be valid on the port wishing to read the location t DDD after the data is presented on the writing port.Read OperationWhen reading the device, the user must assert both the OE and CE pins. Data will be available t ACE after CE or t DOE after OE are asserted. If the user of the CY7C1342 wishes to ac-cess a semaphore, the SEM pin must be asserted instead of the CE pin. Required inputs for read operations are summa-rized in Table 1.Semaphore OperationThe CY7C1342 provides eight semaphore latches which are separate from the dual port memory locations. Semaphores are used to reserve resources which are shared between the two ports. The state of the semaphore indicates that a re-source is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a zero to a sema-phore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for t SOP before attempting to read the semaphore. The semaphore value will be available t SWRD + t DOE after the rising edge of the semaphore write. If the left port was successful (reads a zero), it assumes control over the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one), the left side will succeed in gaining control of the semaphore. If the left side no longer requires the sema-phore, a one is written to cancel its request.Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip enable for the semaphore latches. CE must remain HIGH during SEM LOW. A0–2 represents the semaphore address. OE and R/W are used in the same man-ner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect.When writing to the semaphore, only I/O0 is used. If a 0 is written to the left port of an unused semaphore, a one will appear at the same semaphore address on the right port. That semaphore can now only be modified by the side showing a zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore will be set to one for both sides. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the sema-phore. Table 2 shows sample semaphore operations.When reading a semaphore, all eight data lines output the semaphore value. The read value is latched in an output reg-ister to prevent the semaphore from changing state during a write from the other port. If both ports request a semaphore control by writing a 0 to a semaphore within t SPS of each other, it is guaranteed that only one side will gain access to the sema-phore.Initialization of the semaphore is not automatic and must be reset during initialization program at power-up. All sema-phores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed.Table 1. Non-Contending Read/WriteInputs OutputsOperationCE R/W OE SEM I/O0 – I/O7H X X H High Z Power-DownH H L L Data Out ReadSemaphoreX X H X High Z I/O Lines DisabledH L X L Data In Write to Semaphore L H L H Data Out ReadL L X H Data In WriteL X X L Illegal Condition Table 2. Semaphore Operation ExampleFunctionI/O0-7LeftI/O0-7Right StatusNo Action11Semaphore freeLeft port writessemaphore01Left port obtainssemaphoreRight port writes 0 tosemaphore01Right side is deniedaccessLeft port writes 1 tosemaphore10Right port is grantedaccess to Sema-phoreLeft port writes 0 tosemaphore10No change. Left portis denied access Right port writes 1 tosemaphore01Left port obtainssemaphoreLeft port writes 1 tosemaphore11No port accessingsemaphore address Right port writes 0 tosemaphore10Right port obtainssemaphoreRight port writes 1 tosemaphore11No port accessingsemaphoreLeft port writes 0 tosemaphore01Left port obtainssemaphoreLeft port writes 1 tosemaphore11No port accessingsemaphoreTypical DC and AC Characteristics1008070600.01.02.03.05.05090V CC =5.0V T A =25°C 4.04.04.55.05.56.014012010080604001.02.03.0 5.0O U T P U T S O U R C E C U R R E N T (m A )SUPPLY VOLTAGE (V)NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE AMBIENT TEMPERATURE (°C)OUTPUT VOLTAGE (V)OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 0.0N O R M A L I Z E D I , I C C0I CC 1.21.11.00.9–55125N O R M A L I Z E D t A ANORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE AMBIENT TEMPERATURE (°C)1.051.004.04.55.0 5.56.0N O R M A L I Z E D t A ASUPPLY VOLTAGE (V)NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGEO U T P U T S I N K C U R R E N T (m A )OUTPUT VOLTAGE (V)OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE V CC =5.0VT A =25°C0.80.95 1.251.00.751050N O R M A L I Z E D I C C0.50NORMALIZED I CC vs.CYCLE TIME CYCLE FREQUENCY (MHz)1.00.750.2501.02.03.05.0N O R M A L I Z E D t P C20.010.05.00200400600800D E L T A t (n s )015.00.0SUPPLY VOLTAGE (V)TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE CAPACITANCE (pF)TYPICAL ACCESS TIME CHANGEvs. OUTPUT LOADING4.010000.50A A 2030I SBS BN O R M A L I Z E D I , I C CS B251.10V CC =4.5V T A =25°CV CC =5.0V T A =25°C V IN =0.5V401.00.60.41.20.220V CC =5.0V T A =25°C4.01.4–55251251.21.00.80.60.6V CC =5.0V V IN =5.0V I CC0.20.4I SB30.8Document #: 38-06038 Rev. *B Page 11 of 12© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.Ordering Information4K x8 Dual-Port SRAM Speed (ns)Ordering Code Package Name Package TypeOperating Range 15CY7C135–15JC J6952-Lead Plastic Leaded Chip Carrier Commercial 20CY7C135–20JC J6952-Lead Plastic Leaded Chip Carrier Commercial 25CY7C135–25JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C135–25JI J6952-Lead Plastic Leaded Chip Carrier Industrial 35CY7C135–35JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C135–35JI J6952-Lead Plastic Leaded Chip Carrier Industrial 55CY7C135–55JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C135–55JIJ6952-Lead Plastic Leaded Chip CarrierIndustrial4K x8 Dual-Port SRAM with Semaphores Speed (ns)Ordering Code Package Type Package TypeOperating Range 15CY7C1342–15JC J6952-Lead Plastic Leaded Chip Carrier Commercial 20CY7C1342–20JC J6952-Lead Plastic Leaded Chip Carrier Commercial 25CY7C1342–25JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C1342–25JI J6952-Lead Plastic Leaded Chip Carrier Industrial 35CY7C1342–35JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C1342–35JI J6952-Lead Plastic Leaded Chip Carrier Industrial 55CY7C1342–55JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C1342–55JIJ6952-Lead Plastic Leaded Chip CarrierIndustrialPackage Diagrams52-Lead Plastic Leaded Chip Carrier J6951-85004-*ADocument #: 38-06038 Rev. *B Page 12 of 12Document History PageDocument Title: CY7C135/CY7C1342 4K x 8 Dual Port Static RAM and 4K x 8 Dual Port Static RAM w/Semaphores Document Number: 38-06038REV.ECN NO.Issue Date Orig. of Change Description of Change**11018110/21/01SZV Change from Spec number: 38-00541 to 38-06038*A 12228812/27/02RBI Power up requirements added to Maximum Ratings Information *B236763SEE ECNYDTRemoved cross information from features section。

cy7c63813usb编程例

一、概述CY7CxxxUSB是一款功能强大的USB控制器芯片，具有广泛的应用领域。

本文将介绍CY7CxxxUSB的编程例，并详细讲解其编程操作步骤和注意事项，以帮助开发者更好地理解和应用该芯片。

二、CY7CxxxUSB编程概述1. CY7CxxxUSB是一款USB控制器芯片，集成了USB2.0设备控制器、8位多功能微控制器和大量外设接口。

它具有丰富的接口和功能，可以满足各种USB设备的控制需求。

2. 该芯片支持多种开发工具，可通过C语言或汇编语言进行编程。

三、CY7CxxxUSB编程步骤1. 下载并安装CYxxx开发工具要开始CY7CxxxUSB的编程，首先需要下载和安装Cypress公司提供的CYxxx开发工具。

该开发工具可以在Cypress官全球信息站免费下载，安装完成后即可开始编程操作。

2. 创建工程和配置环境在CYxxx开发工具中，选择“新建工程”并设置相关工程参数，包括芯片型号、时钟频率等。

然后配置开发环境，包括引脚分配、中断设置等。

3. 编写程序在CYxxx开发工具中，进行源代码的编写。

开发者可以根据自己的需求编写具体的功能代码，例如USB设备的数据传输、中断处理、外设控制等。

4. 编译和下载完成程序编写后，进行代码的编译和下载。

通过CYxxx开发工具的编译和下载功能，将程序烧录到CY7CxxxUSB芯片中。

四、CY7CxxxUSB编程注意事项1. 理解芯片的规格书和技术手册，熟悉芯片的功能和特性。

2. 注意引脚分配和连接，确保芯片与外围电路的正常连接。

3. 注意时钟频率和时序要求，保证芯片工作的稳定性和可靠性。

五、结语通过本文的介绍，相信读者对CY7CxxxUSB的编程有了更深入的了解。

该芯片具有丰富的功能和广泛的应用领域，是一款非常优秀的USB控制器芯片。

希望本文的内容能帮助开发者更好地应用和开发CY7CxxxUSB，为各种USB设备的控制提供更好的解决方案。

六、CY7CxxxUSB编程实例在本节中，我们将以一个具体的示例来演示如何使用CY7CxxxUSB进行编程。

CY7C123资料

256 x 4 Static RAMCY7C123Features•256 x 4 static RAM for control store in high-speed computers•CMOS for optimum speed/power •High speed—7 ns (commercial)—10 ns (military)•Low power—660 mW (commercial)—825 mW (military)•Separate inputs and outputs•5-volt power supply ±10% tolerance both commercial and military•TTL-compatible inputs and outputs •24 pins•300-mil packageFunctional DescriptionThe CY7C123 is a high-performance CMOS static RAM orga-nized as 256 words by 4 bits. Easy memory expansion is pro-vided by an active LOW chip select one (CS 1) input, an active HIGH chip select two (CS 2) input, and three-state outputs.Writing to the device is accomplished when the chip select one (CS 1) and write enable (WE) inputs are both LOW and the chip select two input is HIGH. Data on the four data inputs (D 0through D 3) is written into the memory location specified on the address pins (A 0 through A 7). The outputs are precondi-tioned so that the write data is present at the outputs when the write cycle is complete. This precondition operation ensures minimum write recovery times by eliminating the “write recov-ery glitch.”Reading the device is accomplished by taking the chip select one (CS 1) and output enable (OE) inputs LOW, while the write enable (WE) and chip select two (CS 2) inputs remain HIGH.Under these conditions, the contents of the memory location specified on the address pins will appear on the four output pins (O 0 through O 3).The output pins remain in high-impedance state when chip select one (CS 1) or output enable (OE) is HIGH, or write en-able (WE) or chip select two (CS 2) is LOW.A die coat is used to insure alpha immunity.COLUMN DECODERLogic Block DiagramPin ConfigurationC123–116x 64ARRAYA 0A 1A 2A 3R O W D E C O D E RS E N S E A M P SDA T A INPUT CONTROLO 0O 1O 2O 3A 4A 5A 6D 0D 1D 2D 3OEWE CS 1CS 2C123–2A 7O 112345678910111415162019181721242322Top ViewDIP/SOJ A 2A 3A 4A 5A 6V SS D 0D 1O 2V CC A 1A 0WE CS 1CS 2D 3D 2O 3OE V SSO 0V CC 1213A 7Selection Guide7C123–77C123–97C123–107C123–127C123–15Maximum Access Time (ns)Commercial 7912Military101215Maximum Operating Current (mA)Commercial120120120Military150150150元器件交易网Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not tested.)Storage T emperature ..................................–65°C to+150°C Ambient T emperature withPower Applied..............................................–55°C to+125°C Supply Voltage to Ground Potential(Pins 24 and 18 to Pins 7 and 12)[1]...............–0.5V to+7.0V DC Voltage Applied to Outputsin High Z State[1].............................................–0.5V to+7.0V DC Input Voltage[1].........................................–0.5V to +7.0V Output Current into Outputs (LOW).............................20 mA Latch-Up Current.................................................... >200 mAOperating RangeRangeAmbientTemperature V CC Commercial0°C to + 70°C 5V ± 10%Military[2]–55°C to + 125°C 5V ± 10%Electrical Characteristics Over the Operating Range[3]7C123–7 7C123–97C123–107C123–157C123–12UnitParameter Description Test Conditions Min.Max.Min.Max.Min.Max.V OH Output HIGH Voltage V CC = Min., I OH = –5.2 mA 2.4 2.4 2.4V V OL Output LOW Voltage V CC = Min., I OL = 8.0 mA 0.40.40.4V V IH Input HIGH Voltage 2.2V CC 2.2V CC 2.2V CC V V IL Input LOW Voltage[1]–0.8+0.8–0.8+0.8–0.8+0.8V I IX Input Load Current V SS < V I < V CC–10+10–10+10–10+10µAI OZ Output Current(High Z)V SS < V OUT < V CC,Output Disabled–10+10–10+10–10+10µAI CC Power SupplyCurrent V CC = Max.,I OUT = 0 mA,f = f MAX = 1/t RCCommercial120120mAMilitary150150mACapacitance[4]Parameter Description Test Conditions Max.UnitC IN Input Capacitance T A = 25°C, f = 1 MHz,V CC = 5.0V 8pFC OUT Output Capacitance8pFLogic Table[5]InputOE CS1CS2WE D0 – D3Outputs Mode X H X X X High Z Not Selected X X L X X High Z Not SelectedL L H H X O0 – O3Read Stored Data X L H L L High Z Write “0”X L H L H High Z Write “1”H L H H X High Z Output Disabled Notes:1.V IL(min.) = –3.0V for pulse durations of less than 20 ns.2.T A is the “instant on” case temperature.3.See the last page of this specification for Group A subgroup testing information.4.T ested initially and after any design or process changes that may affect these parameters.5.H = High Voltage, L = Low Voltage, X = Don’t Care, and High Z = High Impedance.AC Test Loads and Waveforms3.0V 5V OUTPUTR1 470ΩR2224Ω20pFGND90%90%10%≤3ns≤ 3ns5V OUTPUTC123–3R2224Ω5pF(a)(b)OUTPUT1.62VINCLUDING JIG AND SCOPE INCLUDING JIG AND SCOPER1 470ΩEquivalent to:THÉ V ENIN EQUIVALENT10%ALL INPUT PULSESC123–4152ΩSwitching Characteristics Over the Operating Range [3]7C123–77C123–97C123–107C123–127C123–15Parameter Description Min.Max.Min.Max.Min.Max.Min.Max.Min.Max.UnitREAD CYCLE t RC Read Cycle Time 79101215ns t AA Address to Data Valid 79101215ns t ACS Chip Select to Data Valid 788810ns t DOE OE LOW to DataValid 788810ns t HZCS Chip Select to High Z [6,7]566 6.58ns t HZOE OE HIGH to High Z [6]5666.58ns t LZCS Chip Select to Low Z [7]22222ns t LZOE OE LOW to LowZ 22222ns WRITE CYCLEt WC Write Cycle Time 79101215ns t HZWE WE LOW to High Z [6] 5.56678ns t LZWE WE HIGH to LowZ 22222ns t PWE WE Pulse Width5 6.57811ns t SD Data Set-Up to WriteEnd 567811ns t HD Data Hold from Write End 11111ns t SA Address Set-Up to Write Start 0.51122ns t HA Address Hold from Write End 1.5 1.5222ns t SCS CS LOW to Write End 5 6.57811ns t AWAddress Set-Up to Write End5.57.581013nsNotes:6.Transition is measured at steady-state HIGH level – 500 mV or steady-state LOW level +500 mV on the output from 1.5V level on the input with load shown inpart (b) of AC T est Loads.7.At any given temperature and voltage condition, t HZCS is less than t LZCS for any given device.Switching WaveformsRead Cycle [8,9]Write Cycle [8,9]Notes:8.Measurements are referenced to 1.5V unless otherwise stated.9.Timing diagram represents one solution that results in an optimum cycle time. Timing may be changed in various applications as long as the worst case limitsare not violated.t RCt AAt ACSt HZCSCS 1–CS 2OEDA T A OUTADDRESSt LZCSt DOEt HZOEt LZOEC123–5DA T A VALIDt WCt SCSt SAt HDt AWt HAt PWEt SDt HZWEt LZWEADDRESSCS 1–CS 2WEDA T A INDA T A OUTC123–6Typical DC and AC Characteristics1.21.41.00.60.40.24.04.55.05.56.01.61.41.21.00.8–5525125–55251251.21.00.8N O R M A L I Z E D t A A90756045301501.02.03.04.0O U T P U T S O U R C E C U R R E N T (m A )SUPPL Y VOLT AGE (V)NORMALIZED SUPPLY CURRENT vs.SUPPLY VOLTAGENORMALIZED ACCESS TIME vs.AMBIENT TEMPERATURE AMBIENT TEMPERA TURE (°C)NORMALIZED SUPPLY CURRENT vs.AMBIENT TEMPERATURE AMBIENT TEMPERATURE (°C)OUTPUT VOLT AGE (V)OUTPUT SOURCE CURRENT vs.OUTPUT VOLTAGE 0.00.81.41.31.21.11.00.94.04.55.05.56.0N O R M A L I Z E D t A ASUPPL Y VOLT AGE(V)NORMALIZED ACCESS TIME vs.SUPPLY VOLTAGE 0.60.40.20.0N O R M A L I Z E D I C C , I S BN O R M A L I Z E D I C C , I S BV CC =5.0V V IN =5.0VI CCI CCV CC =5.0VV CC =5.0V T A =25°CI SBT A =25°C0.60.803.02.52.01.51.00.50.01.02.03.04.0N O R M A L I Z E D I P OSUPPL Y VOLT AGE (V)TYPICAL POWER-ON CURRENT vs.SUPPLY VOLTAGE 1.11.00.910203040CYCLE FREQUENCY (MHz)NORMALIZED I CC vs.CYCLE TIME 0.05.00.8V CC =5.0V T A =25°C V IN =0.5V300360180120600.01.02.03.04.0O U T P U T S I N K C U R R E N T (m A )0240OUTPUT VOLT AGE (V)OUTPUT SINK CURRENT vs.OUTPUT VOLTAGEV CC =5.0V T A =25°C30100200400600800020CAPACIT ANCE (pF)TOTAL ACCESS TIME CHANGE vs.OUTPUT LOADINGV CC =4.5V T A =25°CD E L T A t (n s )AA 10005.0I SBN O R M A L I Z E D I P OMILITARY SPECIFICATIONS Group A Subgroup Testing Document #: 38–00060–FOrdering InformationSpeed (ns)Ordering Code Package Name Package TypeOperating Range 7CY7C123–7PC P13A 24-Lead (300-Mil) Molded DIP Commercial CY7C123–7VC V1324-Lead Molded SOJ9CY7C123–9PC P13A 24-Lead (300-Mil) Molded DIP Commercial CY7C123–9VC V1324-Lead Molded SOJ10CY7C123–10DMB D1424-Lead (300-Mil) CerDIP Military12CY7C123–12PC P13A 24-Lead (300-Mil) Molded DIP Commercial CY7C123–12DMB D1424-Lead (300-Mil) CerDIP Military 15CY7C123–15DMBD1424-Lead (300-Mil) CerDIPMilitaryDC CharacteristicsParameterSubgroups V OH 1, 2, 3V OL 1, 2, 3V IH 1, 2, 3V IL Max.1, 2, 3I IX 1, 2, 3I OZ 1, 2, 3I CC1, 2, 3Switching CharacteristicsParameter SubgroupsREAD CYCLEt RC 7, 8, 9, 10, 11t AA 7, 8, 9, 10, 11t ACS 7, 8, 9, 10, 11t DOE7, 8, 9, 10, 11WRITE CYCLEt WC 7, 8, 9, 10, 11t PWE 7, 8, 9, 10, 11t SD 7, 8, 9, 10, 11t HD 7, 8, 9, 10, 11t SA 7, 8, 9, 10, 11t HA 7, 8, 9, 10, 11t SCS 7, 8, 9, 10, 11t AW7, 8, 9, 10, 11© Cypress Semiconductor Corporation, 1993. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Package Diagrams24-Lead (300-Mil)CerDIP D14MIL–STD–1835D–9 Config.A24-Lead (300-Mil)MoldedDIP P13/P13APackage Diagrams (continued)24-Lead Molded SOJ V13。

CY7C1515AV18资料

Page 2 of 31 [+] Feedback
元器件交易网
Logic Block Diagram (CY7C1513AV18)
CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CY7C1515AV18
18 D[17:0]
A(19:0) 20
■ Variable drive HSTL output buffers
■ JTAG 1149.1 compatible test access port
■ Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1511AV18 – 8M x 8 CY7C1526AV18 – 8M x 9 CY7C1513AV18 – 4M x 18 CY7C1515AV18 – 2M x 36
Address Register
21
A(20:0)
2M x 8 Array 2M x 8 Array 2M x 8 Array 2M x 8 Array
Read Data Reg. 32 16
16
Control Logic
RPS
C C
Reg.
Reg. 8 8
Reg.
8
8
8
CQ CQ Q[7:0]
Logic Block Diagram (CY7C1526AV18)
Address Register
21
A(20:0)
2M x 9 Array 2M x 9 Array 2M x 9 Array 2M x 9 Array
Read Data Reg. 36 18

CJ135_芯片资料

28V 1ms; 1Hz: 35V 32V -40° … 150°C
Block Diagram
CJ135 ADConverter
Lambda Probe
Filter
SPI
μC
Features

Enhanced diagnostics capability (OBD II conform) Extended Ri- (temperature) measurement range till 6kOhm
IPE SPI APE
ECK
/CS SCK SI SO GND SPI
µC
APE R1101C1来自09 L1102MES
PWM
Enable IN
Plug
GNDS GNDD UMP
Input
PWM
Rcode
C1105
GND C1103 C1102
PWMEnableOUT
RGND RG R1104
UMM MUP MUM
R1107
R1108
C1111
Power stage for sensor heater e.g. CJ945, CJ950
3.3V digital I/O configuration
Regional sales Europe/Japan USA/Canada China Korea
contacts bosch.semiconductors@ bosch.semiconductors@ bosch.semiconductors@ bosch.semiconductors@
Automotive Electronics Product Information
CJ135 - Lambda Probe Interface IC

CY7C63513C中文资料

Low-Speed High I/O, 1.5-Mbps USB ControllerCY7C63413C CY7C63513C CY7C63613CFeatures•Low-cost solution for low-speed applications with high I/O requirements such as keyboards, keyboards with integrated pointing device, gamepads, and many others•USB Specification Compliance—Conforms to USB Specification, Versions 1.1 and 2.0—Conforms to USB HID Specification, Version 1.1—Supports 1 device address and 3 data endpoints —Integrated USB transceiver •8-bit RISC microcontroller —Harvard architecture—6-MHz external ceramic resonator —12-MHz internal CPU clock •Internal memory —256 bytes of RAM —8 Kbytes of EPROM•Interface can auto-configure to operate as PS2 or USB •I/Oport—The CY7C63413C/513C have 24 General Purpose I/O (GPIO) pins (Port 0 to 2) capable of sinking 7 mA per pin (typical)—The CY7C63613C has 12 General Purpose I/O (GPIO) pins (Port 0 to 2) capable of sinking 7 mA per pin (typical)—The CY7C63413C/513C have eight GPIO pins (Port 3) capable of sinking 12 mA per pin (typical) which can drive LEDs —The CY7C63613C has four GPIO pins (Port 3) capable of sinking 12 mA per pin (typical) which can drive LEDs —Higher current drive is available by connecting multiple GPIO pins together to drive a common output —Each GPIO port can be configured as inputs with internal pull-ups or open drain outputs or traditional CMOS outputs —The CY7C63513C has an additional eight I/O pins on a DAC port which has programmable current sink outputs —Maskable interrupts on all I/O pins•12-bit free-running timer with one microsecond clock ticks•Watch Dog Timer (WDT)•Internal Power-On Reset (POR)•Improved output drivers to reduce EMI•Operating voltage from 4.0V to 5.5V DC•Operating temperature from 0 to 70 degrees Celsius •CY7C63413C available in 40-pin PDIP , 48-pin SSOP , 48-pin SSOP - Tape reel, all in Lead-Free versions for production•CY7C63513C available in 48-pin SSOP Lead-Free packages for production•CY7C63613C available in 24-pin SOIC Lead-Free packages for production•Industry-standard programmer supportFunctional OverviewThe CY7C63413C/513C/613C are 8-bit RISC One Time Programmable (OTP) microcontrollers. The instruction set has been optimized specifically for USB operations, although the microcontrollers can be used for a variety of non-USB embedded applications.The CY7C63413C/513C features 32 General-Purpose I/O (GPIO) pins to support USB and other applications. The I/O pins are grouped into four ports (Port 0 to 3) where each port can be configured as inputs with internal pull-ups, open drain outputs, or traditional CMOS outputs. The CY7C63413C/513C have 24 GPIO pins (Ports 0 to 2) that are rated at 7 mA typical sink current. The CY7C63413C/513C has 8 GPIO pins (Port 3) that are rated at 12 mA typical sink current, which allows these pins to drive LEDs.The CY7C63613C features 16 General-Purpose I/O (GPIO)pins to support USB and other applications. The I/O pins are grouped into four ports (Port 0 to 3) where each port can be configured as inputs with internal pull-ups, open drain outputs,or traditional CMOS outputs. The CY7C63613C has 12 GPIO pins (Ports 0 to 2) that are rated at 7 mA typical sink current.The CY7C63613C has 4 GPIO pins (Port 3) that are rated at 12 mA typical sink current, which allows these pins to drive LEDs.Multiple GPIO pins can be connected together to drive a single output for more drive current capacity. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcon-troller. Note the GPIO interrupts all share the same “GPIO”interrupt vector.The CY7C63513C features an additional 8 I/O pins in the DAC port. Every DAC pin includes an integrated 14-Kohm pull-up resistor. When a “1” is written to a DAC I/O pin, the output current sink is disabled and the output pin is driven high by theinternal pull-up resistor. When a “0” is written to a DAC I/O pin,the internal pull-up is disabled and the output pin provides the programmed amount of sink current. A DAC I/O pin can be used as an input with an internal pull-up by writing a “1” to the pin.元器件交易网The sink current for each DAC I/O pin can be individually programmed to one of sixteen values using dedicated Isink registers. DAC bits [1:0] can be used as high current outputs with a programmable sink current range of 3.2 to 16 mA (typical). DAC bits [7:2] have a programmable current sink range of 0.2 to 1.0 mA (typical). Again, multiple DAC pins can be connected together to drive a single output that requires more sink current capacity. Each I/O pin can be used to generate a DAC interrupt to the microcontroller and the interrupt polarity for each DAC I/O pin is individually program-mable. The DAC port interrupts share a separate “DAC”interrupt vector.The Cypress microcontrollers use an external 6-MHz ceramic resonator to provide a reference to an internal clock generator. This clock generator reduces the clock-related noise emissions (EMI). The clock generator provides the 6 and 12-MHz clocks that remain internal to the microcontroller.The CY7C63413C/513C/613C are offered with single EPROM options. The CY7C63413C, CY7C63513C and the CY7C63613C have 8 Kbytes of EPROM.These parts include Power-on Reset logic, a Watch Dog Timer, a vectored interrupt controller, and a 12-bit free-running timer. The Power-On Reset (POR) logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at EPROM address 0x0000. The Watch Dog Timer can be used to ensure the firmware never gets stalled for more than approximately 8 ms. The firmware can get stalled for a variety of reasons, including errors in the code or a hardware failure such as waiting for an interrupt that never occurs. The firmware should clear the Watch Dog Timer periodically. If the Watch Dog Timer is not cleared for approx-imately 8 ms, the microcontroller will generate a hardware watch dog reset.The microcontroller supports eight maskable interrupts in the vectored interrupt controller. Interrupt sources include the USB Bus-Reset, the 128-µs and 1.024-ms outputs from the free-running timer, three USB endpoints, the DAC port, and the GPIO ports. The timer bits cause an interrupt (if enabled) when the bit toggles from LOW “0” to HIGH “1.” The USB endpoints interrupt after either the USB host or the USB controller sends a packet to the USB. The DAC ports have an additional level of masking that allows the user to select which DAC inputs can cause a DAC interrupt. The GPIO ports also have a level of masking to select which GPIO inputs can cause a GPIO interrupt. For additional flexibility, the input transition polarity that causes an interrupt is programmable for each pin of the DAC port. Input transition polarity can be programmed for each GPIO port as part of the port configuration. The interrupt polarity can be either rising edge (“0” to “1”) or falling edge (“1”to “0”).The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources as noted above (128-µs and 1.024-ms). The timer can be used to measure the duration of an event under firmware control by reading the timer twice: once at the start of the event, and once after the event is complete. The difference between the two readings indicates the duration of the event measured in microseconds. The upper four bits of the timer are latched into an internal register when the firmware reads the lower eight bits. A read from the upper four bits actually reads data from the internal register, instead of the timer. This feature eliminates the need for firmware to attempt to compensate if the upper four bits happened to increment right after the lower 8 bits are read.The CY7C63413C/513C/613C include an integrated USB serial interface engine (SIE) that supports the integrated peripherals. The hardware supports one USB device address with three endpoints. The SIE allows the USB host to commu-nicate with the function integrated into the microcontroller. Finally, the CY7C63413C/513C/613C support PS/2 operation. With appropriate firmware the D+ and D– USB pins can also be used as PS/2 clock and data signals. Products utilizing these devices can be used for USB and/or PS/2 operation with appropriate firmware.1.CY7C63613C is not bonded out for all GPIO pins shown in Logic Block Diagram. Refer to pin configuration diagram for bonded out pins. See note on page 12for firmware code needed for unused GPIO pins..Programming Model14-bit Program Counter (PC)The 14-bit Program Counter (PC) allows access for up to 8 kilobytes of EPROM using the CY7C63413C/513C/613C architecture. The program counter is cleared during reset, such that the first instruction executed after a reset is at address 0x0000. This is typically a jump instruction to a reset handler that initializes the application.The lower eight bits of the program counter are incremented as instructions are loaded and executed. The upper six bits of the program counter are incremented by executing an XPAGE instruction. As a result, the last instruction executed within a 256-byte “page” of sequential code should be an XPAGE instruction. The assembler directive “XPAGEON” will cause the assembler to insert XPAGE instructions automatically. As instructions can be either one or two bytes long, the assembler may occasionally need to insert a NOP followed by an XPAGE for correct execution.The program counter of the next instruction to be executed, carry flag, and zero flag are saved as two bytes on the program stack during an interrupt acknowledge or a CALL instruction. The program counter, carry flag, and zero flag are restored from the program stack only during a RETI instruction.Please note the program counter cannot be accessed directly by the firmware. The program stack can be examined by reading SRAM from location 0x00 and up.8-bit Accumulator (A)The accumulator is the general purpose, do everything register in the architecture where results are usually calcu-lated.8-bit Index Register (X)The index register “X” is available to the firmware as an auxiliary accumulator. The X register also allows the processor to perform indexed operations by loading an index value into X.8-bit Program Stack Pointer (PSP)During a reset, the Program Stack Pointer (PSP) is set to zero. This means the program “stack” starts at RAM address 0x00 and “grows” upward from there. Note the program stack pointer is directly addressable under firmware control, using the MOV PSP,A instruction. The PSP supports interrupt service under hardware control and CALL, RET, and RETI instructions under firmware control.Pin DefinitionsName I/OCY7C63413C CY7C63513C CY7C63613CDescription 40-Pin48-Pin Die48-Pin24-PinD+, D–I/O1,21,21,21,21,2USB differential data; PS/2 clock anddata signalsP0[7:0]I/O15,26,1625,17,2418,2317,32,1831,19,3020,2917,32,18,31,19,30,20,2917,32,18,31,19,30,20,297, 18, 8, 17, 9,16, 10, 15GPIO port 0 capable of sinking 7 mA(typical)P1[3:0]I/O11,30,12,29,13,28,14,2711,38,12,37,13,36,14,3511,38,12,37,13,36,14,3511,38,12,37,13,36,14,355, 20, 6, 19GPIO Port 1 capable of sinking 7 mA(typical).P2I/O7,34,8,33,9,32,10,317,42,8,41,9,40,10,397,42,8,41,9,40,10,397,42,8,41,9,40,10,39n/a GPIO Port 2 capable of sinking 7 mA(typical).P3[7:4]I/O3,38,4,37,5,36,6,353,46,4,45,5,44,6,433,46,4,45,5,44,6,433,46,4,45,5,44,6,433, 22, 4, 21GPIO Port 3 capable of sinking 12 mA(typical).DAC I/O n/a n/a15,34,16,33,21,28,22,2715,34,16,33,21,28,22,27n/a DAC I/O Port with programmablecurrent sink outputs. DAC[1:0] offer aprogrammable range of 3.2 to 16 mAtypical. DAC[7:2] have a program-mable sink current range of 0.2 to 1.0mA typical. DAC I/O Port not bondedout on CY7C63613C. See note onpage 12 for firmware code needed forunused pins.XTAL ININ 21252525136-MHz ceramic resonator or externalclock inputXTAL OUT OUT22262626146-MHz ceramic resonatorV PP1923232311Programming voltage supply, groundduring operationV CC4048484824Voltage supplyVss20,3924,4724,4724,4712, 23GroundDuring an interrupt acknowledge, interrupts are disabled and the 14-bit program counter, carry flag, and zero flag are written as two bytes of data memory. The first byte is stored in the memory addressed by the program stack pointer, then the PSP is incremented. The second byte is stored in memory addressed by the program stack pointer and the PSP is incre-mented again. The net effect is to store the program counter and flags on the program “stack” and increment the program stack pointer by two.The Return From Interrupt (RETI) instruction decrements the program stack pointer, then restores the second byte from memory addressed by the PSP. The program stack pointer is decremented again and the first byte is restored from memory addressed by the PSP. After the program counter and flags have been restored from stack, the interrupts are enabled. The effect is to restore the program counter and flags from the program stack, decrement the program stack pointer by two, and re-enable interrupts.The Call Subroutine (CALL) instruction stores the program counter and flags on the program stack and increments the PSP by two.The Return From Subroutine (RET) instruction restores the program counter, but not the flags, from program stack and decrements the PSP by two.8-bit Data Stack Pointer (DSP)The Data Stack Pointer (DSP) supports PUSH and POP instructions that use the data stack for temporary storage. A PUSH instruction will pre-decrement the DSP, then write data to the memory location addressed by the DSP. A POP instruction will read data from the memory location addressed by the DSP, then post-increment the DSP.During a reset, the Data Stack Pointer will be set to zero. A PUSH instruction when DSP equal zero will write data at the top of the data RAM (address 0xFF). This would write data to the memory area reserved for a FIFO for USB endpoint 0. In non-USB applications, this works fine and is not a problem. For USB applications, it is strongly recommended that the DSP is loaded after reset just below the USB DMA buffers. Address ModesThe CY7C63413C/513C/613C microcontrollers support three addressing modes for instructions that require data operands: data, direct, and indexed. DataThe “Data” address mode refers to a data operand that is actually a constant encoded in the instruction. As an example, consider the instruction that loads A with the constant 0xE8:•MOV A,0E8hThis instruction will require two bytes of code where the first byte identifies the “MOV A” instruction with a data operand as the second byte. The second byte of the instruction will be the constant “0xE8”. A constant may be referred to by name if a prior “EQU” statement assigns the constant value to the name. For example, the following code is equivalent to the example shown above:•DSPINIT: EQU 0E8h•MOV A,DSPINITDirect“Direct” address mode is used when the data operand is a variable stored in SRAM. In that case, the one byte address of the variable is encoded in the instruction. As an example, consider an instruction that loads A with the contents of memory address location 0x10:•MOV A, [10h]In normal usage, variable names are assigned to variable addresses using “EQU” statements to improve the readability of the assembler source code. As an example, the following code is equivalent to the example shown above:•buttons: EQU 10h•MOV A,[buttons]Indexed“Indexed” address mode allows the firmware to manipulate arrays of data stored in SRAM. The address of the data operand is the sum of a constant encoded in the instruction and the contents of the “X” register. In normal usage, the constant will be the “base” address of an array of data and the X register will contain an index that indicates which element of the array is actually addressed:•array: EQU 10h•MOV X,3•MOV A,[x+array]This would have the effect of loading A with the fourth element of the SRAM “array” that begins at address 0x10. The fourth element would be at address 0x13.Instruction Set SummaryMNEMONIC operand opcode cycles MNEMONIC operand opcode cycles HALT 007NOP204ADD A,expr data014INC A acc214ADD A,[expr] direct026INC X x224ADD A,[X+expr] index037INC [expr]direct237ADC A,expr data044INC [X+expr]index248ADC A,[expr]direct056DEC A acc254ADC A,[X+expr]index067DEC X x264SUB A,expr data074DEC [expr]direct277SUB A,[expr]direct086DEC [X+expr]index288SUB A,[X+expr]index097IORD expr address295SBB A,expr data0A4IOWR expr address2A5SBB A,[expr]direct0B6POP A2B4SBB A,[X+expr]index0C7POP X2C4OR A,expr data0D4PUSH A2D5OR A,[expr]direct0E6PUSH X2E5OR A,[X+expr]index0F7SWAP A,X2F5AND A,expr data104SWAP A,DSP305AND A,[expr]direct116MOV [expr],A direct315AND A,[X+expr]index127MOV [X+expr],A index326XOR A,expr data134OR [expr],A direct337XOR A,[expr]direct146OR [X+expr],A index348XOR A,[X+expr]index157AND [expr],A direct357CMP A,expr data165AND [X+expr],A index368CMP A,[expr]direct177XOR [expr],A direct377CMP A,[X+expr]index188XOR [X+expr],A index388MOV A,expr data194IOWX [X+expr]index396MOV A,[expr]direct1A5CPL3A4MOV A,[X+expr]index1B6ASL3B4MOV X,expr data1C4ASR3C4MOV X,[expr]direct1D5RLC3D4 reserved1E RRC 3E4 XPAGE1F4RET 3F8MOV A,X404DI704MOV X,A414EI724MOV PSP,A604RETI738 CALL addr50-5F10JMP addr80-8F5JC addr C0-CF5 CALL addr90-9F10JNC addr D0-DF5JZ addr A0-AF5JACC addr E0-EF7JNZ addr B0-BF5INDEX addr F0-FF14Memory OrganizationProgram Memory Organizationafter reset Address14-bit PC0x0000Program execution begins here after a reset0x0002USB Bus Reset interrupt vector0x0004128-µs timer interrupt vector0x0006 1.024-ms timer interrupt vector0x0008USB address A endpoint 0 interrupt vector0x000A USB address A endpoint 1 interrupt vector0x000C USB address A endpoint 2 interrupt vector0x000E Reserved0x0010Reserved0x0012Reserved0x0014DAC interrupt vector0x0016GPIO interrupt vector0x0018Reserved0x001A Program Memory begins here(8K - 32 bytes)0x1FDF8-KB PROM ends here (CY7C63413C, CY7C63513C, CY7C63613C) Figure 1. Program Memory Space with Interrupt Vector TableData Memory OrganizationThe CY7C63413C/513C/613C microcontrollers provide 256 bytes of data RAM. In normal usage, the SRAM is partitioned into four areas: program stack, data stack, user variables and USB endpoint FIFOs as shown below:after reset Address8-bit PSP0x00Program Stack begins here and grows upward8-bit DSP user Data Stack begins here and grows downwardThe user determines the amount of memory requiredUser Variables0xE8USB FIFO for Address A endpoint 20xF0USB FIFO for Address A endpoint 10xF8USB FIFO for Address A endpoint 0Top of RAM Memory0xFFI/O Register SummaryI/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads the selected port into the accumulator. IOWR writes data from the accumu-lator to the selected port. Indexed I/O Write (IOWX) adds the contents of X to the address in the instruction to form the port address and writes data from the accumulator to the specified port. Note that specifying address 0 (e.g., IOWX 0h) means the I/O port is selected solely by the contents of X.Table 1.I/O Register SummaryRegister Name I/O Address Read/Write FunctionPort 0 Data0x00R/W GPIO Port 0Port 1 Data0x01R/W GPIO Port 1Port 2 Data0x02R/W GPIO Port 2Port 3 Data0x03R/W GPIO Port 3Port 0 Interrupt Enable0x04W Interrupt enable for pins in Port 0Port 1 Interrupt Enable0x05W Interrupt enable for pins in Port 1Port 2 Interrupt Enable0x06W Interrupt enable for pins in Port 2Port 3 Interrupt Enable0x07W Interrupt enable for pins in Port 3GPIO Configuration0x08R/W GPIO Ports ConfigurationsUSB Device Address A0x10R/W USB Device Address AEP A0 Counter Register0x11R/W USB Address A, Endpoint 0 counter registerEP A0 Mode Register0x12R/W USB Address A, Endpoint 0 configuration register EP A1 Counter Register0x13R/W USB Address A, Endpoint 1 counter registerEP A1 Mode Register0x14R/C USB Address A, Endpoint 1 configuration register EP A2 Counter Register0x15R/W USB Address A, Endpoint 2 counter registerEP A2 Mode Register0x16R/C USB Address A, Endpoint 2 configuration register USB Status & Control0x1F R/W USB upstream port traffic status and control register Global Interrupt Enable0x20R/W Global interrupt enable registerEndpoint Interrupt Enable0x21R/W USB endpoint interrupt enablesTimer (LSB)0x24R Lower eight bits of free-running timer (1 MHz) Timer (MSB)0x25R Upper four bits of free-running timer that are latchedwhen the lower eight bits are read.WDR Clear0x26W Watch Dog Reset clearDAC Data0x30R/W DAC I/O[2]DAC Interrupt Enable0x31W Interrupt enable for each DAC pinDAC Interrupt Polarity0x32W Interrupt polarity for each DAC pinDAC Isink0x38-0x3F W One four bit sink current register for each DAC pin Processor Status & Control0xFF R/W Microprocessor status and controlNote:2.DAC I/O Port not bonded out on CY7C63613C. See note on page 12 for firmware code needed for unused GPIO pins.ClockingThe XTAL IN and XTAL OUT are the clock pins to the microcon-troller. The user can connect a low-cost ceramic resonator or an external oscillator can be connected to these pins to provide a reference frequency for the internal clock distribution and clock doubler.An external 6-MHz clock can be applied to the XTAL IN pin if the XTAL OUT pin is left open. Please note that grounding the XTAL OUT pin is not permissible as the internal clock is effec-tively shorted to ground.ResetThe USB Controller supports three types of resets. All registers are restored to their default states during a reset. The USB Device Addresses are set to 0 and all interrupts are disabled. In addition, the Program Stack Pointer (PSP) and Data Stack Pointer (DSP) are set to 0x00. For USB applica-tions, the firmware should set the DSP below 0xE8 to avoid a memory conflict with RAM dedicated to USB FIFOs. The assembly instructions to do this are shown below:Mov A, E8h ; Move 0xE8 hex into Accumulator Swap A,dsp; Swap accumulator value into dsp registerThe three reset types are:1.Power-On Reset (POR)2.Watch Dog Reset (WDR)B Bus Reset (non hardware reset)The occurrence of a reset is recorded in the Processor Status and Control Register located at I/O address 0xFF. Bits 4, 5,and 6 are used to record the occurrence of POR, USB Reset,and WDR respectively. The firmware can interrogate these bits to determine the cause of a reset.The microcontroller begins execution from ROM address 0x0000 after a POR or WDR reset. Although this looks like interrupt vector 0, there is an important difference. Resetprocessing does NOT push the program counter, carry flag,and zero flag onto program stack. That means the reset handler in firmware should initialize the hardware and begin executing the “main” loop of code. Attempting to execute either a RET or RETI in the reset handler will cause unpredictable execution results.Power-On Reset (POR)Power-On Reset (POR) occurs every time the V CC voltage to the device ramps from 0V to an internally defined trip voltage (Vrst) of approximately 1/2 full supply voltage. In addition to the normal reset initialization noted under “Reset,” bit 4 (PORS) of the Processor Status and Control Register is set to “1” to indicate to the firmware that a Power-On Reset occurred. The POR event forces the GPIO ports into input mode (high impedance), and the state of Port 3 bit 7 is used to control how the part will respond after the POR releases.If Port 3 bit 7 is HIGH (pulled to V CC ) and the USB IO are at the idle state (DM HIGH and DP LOW) the part will go into a semi-permanent power down/suspend mode, waiting for the USB IO to go to one of Bus Reset, K (resume) or SE0. If Port 3 bit 7 is still HIGH when the part comes out of suspend, then a 128-µs timer starts, delaying CPU operation until the ceramic resonator has stabilized.If Port 3 bit 7 was LOW (pulled to V SS ) the part will start a 96-ms timer, delaying CPU operation until V CC has stabilized,then continuing to run as reset.Firmware should clear the POR Status (PORS) bit in register 0xFF before going into suspend as this status bit selects the 128-µs or 96-ms start-up timer value as follows: IF Port 3 bit 7is HIGH then 128-µs is always used; ELSE if PORS is HIGH then 96-ms is used; ELSE 128-µs is used.Watch Dog Reset (WDR)The Watch Dog Timer Reset (WDR) occurs when the Most Significant Bit (MSB) of the 2-bit Watch Dog Timer Register transitions from LOW to HIGH. In addition to the normal resetFigure 2. Clock Oscillator On-chip CircuitXTALOUTXTALINClock Distribution clk2xClock Doublerclk1x (to Microcontroller)(to USB SIE)30 pF30 pFAt least 8.192 ms WDR goes high Execution begins at Reset Vector 0X008.192 ms 2.048 mssince last write to WDT for 2.048 msto 14.336 msFigure 3. Watch Dog Reset (WDR)initialization noted under “Reset,” bit 6 of the Processor Status and Control Register is set to “1” to indicate to the firmware that a Watch Dog Reset occurred.The Watch Dog Timer is a 2-bit timer clocked by a 4.096-ms clock (bit 11) from the free-running timer. Writing any value to the write-only Watch Dog Clear I/O port (0x26) will clear the Watch Dog Timer.In some applications, the Watch Dog Timer may be cleared in the 1.024-ms timer interrupt service routine. If the 1.024-ms timer interrupt service routine does not get executed for 8.192ms or more, a Watch Dog Timer Reset will occur. A Watch Dog Timer Reset lasts for 2.048 ms after which the microcontroller begins execution at ROM address 0x0000. The USB trans-mitter is disabled by a Watch Dog Reset because the USB Device Address Register is cleared. Otherwise, the USB Controller would respond to all address 0 transactions. The USB transmitter remains disabled until the MSB of the USB address register is set.General Purpose I/O PortsPorts 0 to 2 provide 24 GPIO pins that can be read or written.Each port (8 bits) can be configured as inputs with internal pull-ups, open drain outputs, or traditional CMOS outputs. Please note an open drain output is also a high-impedance (no pull-up) input. All of the I/O pins within a given port have the same configuration. Ports 0 to 2 are considered low current drive with typical current sink capability of 7 mA.The internal pull-up resistors are typically 7 k Ω. Two factors govern the enabling and disabling of the internal pull-up resistors: the port configuration selected in the GPIO Configu-ration register and the state of the output data bit. If the GPIO Configuration selected is “Resistive” and the output data bit is “1,” then the internal pull-up resistor is enabled for that GPIO pin. Otherwise, Q1 is turned off and the 7-k Ω pull-up is disabled. Q2 is “ON” to sink current whenever the output data bit is written as a “0.” Q3 provides “HIGH” source current when the GPIO port is configured for CMOS outputs and the output data bit is written as a “1”. Q2 and Q3 are sized to sink and source, respectively, roughly the same amount of current to support traditional CMOS outputs with symmetric drive.Figure 4. Block Diagram of a GPIO LineGPIO PinV CC7 k ΩESDGPIO CFGmode 2 bitsData Out LatchInternal Data BusPort ReadPort WriteInterrupt EnableC o n t r o lC o n t r o lto Interrupt ControllerQ1Q2Q3Internal BufferTable 2.Port 0 DataAddr: 0x00Port 0 DataP0[7]P0[6]P0[5]P0[4]P0[3]P0[2]P0[1]P0[0]R/WR/WR/WR/WR/WR/WR/WR/WTable 3.Port 1 DataAddr: 0x01Port 1 DataP1[7]P1[6]P1[5]P1[4]P1[3]P1[2]P1[1]P1[0]R/WR/WR/WR/WR/WR/WR/WR/WTable 4.Port 2 DataAddr: 0x02Port 2 DataP2[7]P2[6]P2[5]P2[4]P2[3]P2[2]P2[1]P2[0]R/WR/WR/WR/WR/WR/WR/WR/W。

NCP1351中文资料

NCP1351Product PreviewVariable Off Time PWM ControllerThe NCP1351 is a current−mode controller targeting low power off−line flyback Switched Mode Power Supplies (SMPS) where cost is of utmost importance. Based on a fixed peak current technique (quasi−fixed T ON), the controller decreases its switching frequency asthe load becomes lighter. As a result, a power supply using the NCP1351 naturally offers excellent no−load power consumption, while optimizing the efficiency in other loading conditions. When the frequency decreases, the peak current is gradually reduced down to approximately 30% of the maximum peak current to prevent transformer mechanical resonance. The risk of acoustic noise is thus greatly diminished while keeping good standby power performance. An externally adjustable timer permanently monitors the feedback activity and protects the supply in presence of a short−circuit or an overload. Once the timer elapses, NCP1351 stops switching and stays latched for version A, and tries to restart for Version B.The internal structure features an optimized arrangement which allows one of the lowest available startup current, a fundamental parameter when designing low standby power supplies.The negative current sensing technique minimizes the impact of the switching noise on the controller operation and offers the user to select the maximum peak voltage across his current sense resistor. Its power dissipation can thus be application optimized.Finally, the bulk input ripple ensures a natural frequency smearing which smooths the EMI signature.Features•Quasi−fixed T ON, Variable T OFF Current Mode Control •Extremely Low Current Consumption at Startup•Peak Current Compression Reduces Transformer Noise •Primary or Secondary Side Regulation•Dedicated Latch Input for OTP, OVP •Programmable Current Sense Resistor Peak V oltage •Natural Frequency Dithering for Improved EMI Signature •Easy External Over Power Protection (OPP)•Undervoltage Lockout•Very Low Standby Power via Off−time Expansion •Internal Temperature Shutdown•SOIC−8 PackageTypical Applications•Auxiliary Power Supply•Printer, Game Stations, Low−Cost Adapters•Off−line Battery ChargerThis document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.SOIC−8D SUFFIXCASE 7511MARKING DIAGRAMPIN CONNECTIONSx= A, B, C, or D OptionsA= Assembly LocationY= YearWW= Work WeekG= Pb−Free DeviceFB TIMERCtCSGNDLATCHVCCDRV(Top View)Device Package Shipping†ORDERING INFORMATIONNCP1351ADR2G SOIC−8(Pb−Free)2500 / Tape & Reel†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our T ape and Reel Packaging Specifications Brochure, BRD8011/D.NCP1351BDR2G SOIC−8(Pb−Free)2500 / Tape & ReelFigure 1. Typical Application CircuitPIN FUNCTION DESCRIPTIONPin N°Pin Name Function Pin Description 1FB Feedback Input Injecting Current in this Pin Reduces Frequency2Ct Oscillator Frequency A capacitor sets the maximum switching frequency at no feedback current 3CS Current Sense Input Senses the Primary Current4GND––5DRV Driver Output Driving Pulses to the Power MOSFET6V CC Supply Input Supplies the controller up to 28 V7Latch Latchoff Input A positive voltage above V LATCH fully latches off the controller 8Timer Fault Timer Capacitor Sets the time duration before fault validationINTERNAL CIRCUIT ARCHITECTUREFigure 2. A Version (Latched Short−Circuit Protection)FBCtCSGNDCCFBCtCC CSGNDFigure 3. B Version (Auto−recovery Short−Circuit Protection)MAXIMUM RATINGSSymbol Rating Value UnitV SUPPLY Maximum Supply on V CC Pin 6−0.3 to 28VI SUPPLY Maximum Current in V CC Pin 620mAV DRV Maximum Voltage on DRV Pin 5−0.3 to 20VI DRV Maximum Current in DRV Pin 5$400mAV MAX Supply Voltage on all pins, except Pin 6 (V CC), Pin 5 (DRV)−0.3 to 10VI MAX Maximum Current in all Pins Except Pin 6 (V CC) and Pin 5 (DRV)$10mAI FBmax Maximum Injected Current in Pin 1 (FB)0.5mAR Gmin Minimum Resistive Load on DRV Pin33k WR q JA Thermal Resistance Junction−to−Air200°C/W T JMAX Maximum Junction Temperature150°C Storage Temperature Range−60 to +150°CESD Capability, Human Body Model V per Mil−STD−883, Method 30152kVESD Capability, Machine Model200VStresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.NOTE:This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78.Electrical Characteristics (For typical values T J = 25°C, for Min/Max Values T J = −25°C to +125°C, Max T J = 150°C, V CC = 12 V unless otherwise noted)Symbol Rating Pin Min Typ Max Unit SUPPLY SECTION AND V CC MANAGEMENTVCC ON V CC Increasing Level at Which Driving Pulses are Authorized6151822V VCC STOP V CC Decreasing Level at Which Driving Pulses are Stopped68.38.99.5V VCC HYST Hysteresis Vcc ON − Vcc STOP66−−V V ZENER Clamped V CC When Latched off / Burst Mode Activation6−6−V ICC1Startup Current6−−10m A ICC2Internal IC Consumption with I FB = 50 m A, F SW = 65 kHz and C L = 06− 1.0 1.8mA ICC3Internal IC Consumption with I FB = 50 m A, F SW = 65 kHz and C L = 1 nF6− 1.6 2.5mA ICC LATCH Current Flowing into V CC pin that Keeps the Controller Latched620−−m A CURRENT SENSEI CSmin Minimum Source Current (I FB = 90 m A)T J = 0°C to +125°C3617075m AI CSmin Minimum Source Current (I FB = 90 m A)T J = −25°C to +125°C3587075m A I CSmax Maximum Source Current (I FB = 50 m A)T J = 0°C to +125°C3251270289m A I CSmax Maximum Source Current (I FB = 50 m A)T J = −25°C to +125°C3242270289m AV TH Current Sense Comparator Threshold Voltage3102035mV t delay Propagation Time Delay (CS Falling Edge to Gate Output)3−160300ns TIMING CAPACITORV OFFSET Minimum Voltage on C T Capacitor, I FB = 30 m A2475510565mV VCT MAX Voltage on C T Capacitor at I FB = 150 m A25−−VI CT Source Current (Ct Pin Grounded)2101112m A VCT MIN Minimum Voltage on C T, Discharge Switch Activated2−−20mV T DISCH C T Capacitor Discharge Time (Activated at DRV Turn−on)21m s V FAULT C T Capacitor Level at Which Fault Timer Starts A, B Versions20.40.50.6V FEEDBACK SECTIONV FB FB Pin Voltage for an Injected Current of 200 m A1−0.7−VI FAULT FB Current Under Which a Fault is Detected A, B versions1−40−m A I FBcomp FB Current at Which CS Compression Starts1−60−m AI FBred FB Current at Which CS Compression is Finished1−80−m A Drive OutputT r Output Voltage Rise−time @ CL = 1 nF, 10 − 90% of Output Signal5−90−ns T f Output Voltage Fall−time @ CL = 1 nF, 10 − 90% of Output Signal5−100−ns R OH Source Resistance5−80−W R OL Sink Resistance5−30−W V DRVlow DRV Pin Level at V CC Close to VCC STOP with a 33 k W Resistor to GND58.0−−V V DRVhigh DRV Pin Level at V CC = 28 V5161720V ProtectionI TIMER Timing Capacitor Charging Current81011.513m A V TIMER Fault Voltage on Pin 88 4.55 5.5V T TIMER Fault Timer Duration, C TIMER = 100 nF−−42−ms V LATCH Latching Voltage7 4.55 5.5VThe NCP1351 implements a fixed peak current mode technique whose regulation scheme implements a variable switching frequency. As shown on the typical application diagram, the controller is designed to operate with a minimum number of external components. It incorporates the following features:•Frequency Foldback: Since the switching period increases when power demand decreases, the switching frequency naturally diminishes in light load conditions. This helps to minimize switching losses and offers good standby power performance.•Very Low Startup Current: The patented internal supply block is specially designed to offer a very low current consumption during startup. It allows the use of a very high value external startup resistor, greatly reducing dissipation, improving efficiency and minimizing standby power consumption.•Natural Frequency Dithering: The quasi−fixed t ON mode of operation improves the EMI signature since the switching frequency varies with the natural bulk ripple voltage.•Peak Current Compression: As the load becomes lighter, the frequency decreases and can enter the audible range. To avoid exciting transformer mechanical resonances, hence generating acoustic noise, the NCP1351 includes a patented technique, which reduces the peak current as power goes down. As such, inexpensive transformer can be used without having noise problems.•Negative Primary Current Sensing: By sensing the total current, this technique does not modify the MOSFET driving voltage (V GS) while switching. Furthermore, the programming resistor, together withthe pin capacitance, forms a residual noise filter which blanks spurious spikes.•Programmable Primary Current Sense: It offers a second peak current adjustment variable, which improves the design flexibility.•Extended V CC Range: By accepting V CC levels up to 28 V, the device offers added flexibility in presence of loosely coupled transformers. The gate drive is safely clamped below 20 V to avoid stressing the driven MOSFET.•Easy OPP: Connecting a resistor from the CS pin to the auxiliary winding allows easy bulk voltage compensation.•Secondary or Primary Regulation: The feedback loop arrangement allows simple secondary or primary side regulation without significant additional external components.•Latch Input: If voltage on Pin 7 is externally brought above 5 V, the controller permanently latches off and stays latched until the user cycles V CC down, below 4 V typically.•Fault Timer: In presence of badly coupled transformer, it can be quite difficult to detect an overload or ashort−circuit on the primary side. When the feedback current disappears, a current source charges a capacitor connected to Pin 8. When the voltage on this pin reaches a certain level, all pulses are shut off and theV CC voltage is pulled down below the VCC(min) level. This protection is latched on the A version (the controller must be shut down and restart to resume normal operation), and auto−recovery on Version B (if the fault goes away, the controller automatically resumes operation).APPLICATION INFORMATIONThe Negative Sensing TechniqueStandard current−mode controllers use the positive sensing technique as portrayed by Figure 4. In this technique, the controller detects a positive voltage drop across the sense resistor, representative of the flowing current. Unfortunately, this solution suffers from the following drawbacks:1.Difficulties to precisely adjust the peak current. If 1 V is the maximum sense level, you mustcombine low valued resistors to reach the exact limit you need.2.The voltage developed across the sense resistor subtracts from the gate voltage. If your VCC (min)is 7 V , then the actual gate voltage at the end of the on time, assuming a full load condition, is 7 V –1 V = 6 V .3.The current in the sense resistor also includes the C iss current at turn−on. This narrow spike often disturbs the controller and requires adequate treatment through a LEB circuitry for instance.Figure 5 represents the negative current sense technique.In this simplified example, the source directly connects to the controller ground. Hence, if V CC is 8 V , the effective gate−source voltage is very close to 8 V: no sense resistor drop. How does the controller detect a negative excursion?In lack of primary current, the voltage on the CS pin reaches R offset x I CS . Let us assume that these elements lead to have 1 V on this pin. Now, when the power MOSFET activates,the current flows via the sense resistor and develop a negative voltage by respect to the controller ground. The voltage seen on the CS is nothing else than a positive voltage (R offset x I CS ) plus the voltage across the sense resistor which is negative. Thus, the CS pin voltage goes low as the primarycurrent increases. When the result reaches the threshold voltage (around 20 mV), the comparator toggles and resets the main latch. Figure 3 details how the voltage moves on the CS pin on a 1351 demoboard, whereas Figure 7 zooms on the sense resistor voltage captured by respect to the controller ground.The choice of these two elements is simple. Suppose you want to develop 1 V across the sense resistor. You would select the offset resistor via the following formula:R offset +1I CS+1270m+3.7k W (eq. 1)If you need a peak current of 2 A, then, simply apply the ohm law to obtain the sense resistor value:R sense +1I peak_max+12+0.5W (eq. 2)Due to the circuit flexibility, suppose you only have access to a 0.33 W resistor. In that case, the peak current will exceed the 2 A limit. Why not changing the offset resistor value then? To obtain 2 A from the 0.33 W resistor, you should develop:The offset resistor is thus derived by:V sense +R sense I peak_max +0.33 2+660mV(eq. 3)R offset +0.66I CS+0.66270m+2.44k W (eq. 4)If reducing the sense resistor is of good practice to improve the efficiency, we recommend to adopt sense values between 0.5 V and 1 V . Reducing the voltage below these levels will degrade the noise immunity.Figure 4. Positive Current−Sense TechniqueFigure 5. A Simplified Circuit of the Negative SenseImplementationV senseFigure 6. The Voltage on the Current Sense PinFigure 7. The Voltage Across the SenseResistorCurrent Sense PinCurrent Sense ResistorBelow are a few recommendations concerning the wiring and the PCB layout:•A small 22 pF capacitor can be placed between the CS pin and the controller ground. Place it as close as possible to the controller.•Do not place the offset resistor in the vicinity of the sense element, but put it close to the controller as well.•Regulation by frequency•The power a flyback converter can deliver relates to the energy stored in the primary inductance L p and obeys the following formulae:P out_DCM +12L P I peak 2F SW h (eq. 5)P out_CCM +12L P (I peak 2*I valley 2)F SW h(eq. 6)Where:η (eta) is the converter efficiencyI peak is the peak inductor current reached at the on time terminationI valley represents the current at the end of the off time. It equals zero in DCM.F SW is the operating frequency.Thus, to control the delivered power, we can either play on the peak current setpoint (classical peak current mode control) or adjust the switching frequency by keeping the peak current constant. We have chosen the second scheme in this NCP1351 for simplicity and ease of implementation.Thus, once the peak current has been selected, the feedback loop automatically reacts to satisfy Equations 5 and 6. The external capacitor that you connect between pin 2 and ground (again, place it close to the controller pins) sets the maximum frequency you authorize the converter to operate up to. Normalized values for this timing capacitor are 270 pF (65 kHz) and 180 pF (100 kHz). Of course, different combinations can be tried to design at higher or lower frequencies. Please note that changing the capacitor value does not affect the operating frequency at nominal line and load conditions. Again, the operating frequency is selected by the feedback loop to cope with Equations 5 and 6definitions.The feedback current controls the frequency by changing the timing capacitor end of charge voltage, as illustrated by Figure 8.Figure 8. The Current Injected into the Feedback Loop Adjusts the Switching FrequencyP outDecreases P outIncreasesFigure 9. In Light Load Conditions, the Oscillator Further Delays the Restart Time Figure 10. C t Voltage Swing at a ModerateLoadingC t VoltageC t VoltageIn light load conditions, the frequency can go down to a few hundred Hz without any problem. The internal circuitry naturally blocks the oscillator and softly shifts the restart time as shown on Figure 9 scope shot.Delays The Restart TimeIn lack of feedback current, for instance during a startup sequence or a short circuit, the oscillator frequency is pushedto the limit set by the timing capacitor. In this case, the lower threshold imposed to the timing capacitor is blocked to 500 mV (parameter V fault). This is the maximum power the converter can deliver. To the opposite, as you inject current via the optocoupler in the feedback pin, the off time expands and the power delivery reduces. The maximum threshold level in standby conditions is set to 6 V.Over Power ProtectionAs any universal−mains operated converters, the output power slightly increases at high line compared to what the power supply can deliver at low line. This discrepancy relates to the propagation delay from the point where the peak is detected to the MOSFET gate effective pulldown. It naturally includes the controller reaction time, but also the driver capability to pull the gate down. If the MOSFET Q g is too large, then this parameter will greatly affect your overpower parameter. Sometimes, the small PNP can help and we recommend it if you use a large Q g MOSFET:Figure 11. A Low−Cost PNP Improves the DriveCapability at Turn−offDRVGNDOver power protection can be done without power dissipation penalty by arranging components around the auxiliary as suggested by Figure 11. On this schematic, the diode anode swings negative during the on time. This negative level directly depends on the input voltage and offsets the current sense pin via the R OPP resistor. A small integration is necessary to reduce the O PP action in light load conditions. However, depending on the compensation level, the standby power can be affected. Again, the resistor R OPP should be placed as close as possible to the CS pin. The 22 pF can help to circumvent any picked−up noise and D2 prevents the positive loading of the 270 pF capacitor during the flyback swing. We have put a typical 100 k W O PP resistor but a tweak is required depending on your application.Figure 12. The OPP is Relatively Easy to Implement and It Does not Waste PowerR OPP 100kSuppose you would need to reduce the peak current by 15% in high−line conditions. The turn−ratio between the auxiliary winding and the primary winding is N aux . Assume its value is 0.15. Thus, the voltage on D aux cathode swings negative during the on time to a level of:V aux_peak +−V in_max N aux +−375 0.15+−56V(eq. 7)If we selected a 3.7 k W resistor for R offset , then the maximum sense voltage being developed is:V sense +3.7k 270m +1V(eq. 8)The small RC network made of R 1 and C 3, purposely limits the voltage excursion on D 2 anode. Assume the primary inductance value gives an on time of 3 μs at high−line. The voltage across C 3 thus swings down to:V C 3+t on V aux_peakR 1C 3+−3m 56150k 270p+−4.2V(eq. 9)Typically, we measured around –4 V on our 50 W prototype.By calculation, we want to decrease the peak current by15%. Compared to the internal 270 m A source, we need to derive:I offset +−0.15 270m +−40.5m A(eq. 10)Thus, from the –4 V excursion, the R OPP resistor is derived by:R OPP +440.5m+98k W(eq. 11)After experimental measurements, the resistor was normalized down to 100 k W .FeedbackUnlike other controllers, the feedback in the NCP1351works in current rather than voltage. Figure 13 details the internal circuitry of this particular section. The optocoupler injects a current into the FB pin in relationship with the input/output conditions.Figure 13. The Feedback Section Inside the NCP1351V CCClockf (IFB)V CCto R senseThe FB pin can actually be seen as a diode, forward biased by the optocoupler current. The feedback current, I FB on Figure 13, enter an internal 45 k W resistor which develops a voltage. This voltage becomes the variable threshold point for the capacitor charge, as indicated by Figure 8. Thus, in lack of feedback current (start−up or short−circuit), there is no voltage across the 45 k W and the series offset of 500 mV clamps the capacitor swing. If a 270 pF capacitor is used, the maximum switching frequency is 65 kHz.Folding the frequency back at a rather high peak current can obviously generate audible noise. For this reason, the NCP1351 uses a patented current compression technique which reduces the peak current in lighter load conditions. By design, the peak current changes from 100% of its full load value, to 30% of this value in light load conditions. This is the block placed on the lower left corner of Figure 13. In fullload conditions, the feedback current is weak and all the current flowing through the external offset resistor is:I CS +I CS_min )I dif +I CS_max *I CS_min(eq. 12)+I CS_maxAs the load goes lighter, the feedback current increases and starts to steal current away from the generators. Equation 12can thus be updated by:I CS +I CS_max *kI FB(eq. 13)Equation 13 testifies for the current reduction on the offset generator, k represents an internal coefficient. When the feedback current equals I dif , the offset becomes:I CS +I CS_min(eq. 14)At this point, the current is fully compressed and remains frozen. To further decrease the transmitted power, the frequency does not have other choice than going down.Figure 14. The NCP1351 Peak Current CompressionScheme250 m 70 m CS Current Looking to the data−sheet specifications, the maximum peak current is set to 270 m A whereas the compressed current goes down to 70 m A. The NCP1351 can thus be considered as a multi operating mode circuit:•Real fixed peak current / variable frequency mode for FB current below 60 m A.•Then maximum peak current decreases to I CS,min over a narrow linear range of I FB (to avoid instability created by a discrete jump from I CS,max to I CS,min ), between 60 m A and 80 m A.•Then if I FB keeps on increasing, in a real fixed peak current/variable frequency mode with reduced peak currentFor biasing purposes and noise immunity improvements,we recommend to wire a pulldown resistor and a capacitor in parallel from the FB pin to the controller ground (Figure 15). Please keep these elements as close as possible to the circuit. The pulldown resistor increases the optocoupler current but also plays a role in standby. We found that a 2.5 k W resistor was giving a good tradeoff between optocoupler operating current (internal pole position) and standby power.Figure 15. The Recommended FeedbackArrangement Around the FB PinV CCFault detectionThe fault detection circuitry permanently observes the FB current, as shown on Figure 17. When the feedback current decreases below 40 m A, an external capacitor is charged by a 11.7 m A source. As the voltage rises, a comparator detects when it reaches 5 V typical. Upon detection, there can be two different scenarios:1.A version: the circuit immediately latches−off and remains latched until the voltage on the current into the V CC pin drops below a few μA. The latch is made via an internal SCR circuit who holds Vcc to around 6 V when fired. As long as the current flowing through this latch is above a few m A, the circuit remains locked−out. When the user unplugs the converter, the V CC current falls down and resets the latch.2.B version: the circuit stops its output pulses and the auxiliary V CC decreases via the controller own consumption (≈600 m A). When it touches theV CC(min) point, the circuit re−starts and attempts to crank the power supply. If it fails again, an hiccup mode takes place (Figure 13).Figure 16. Hiccup Occurs with the B Version Only,the A Version Being LatchedV CCV drvThe duty−burst in fault is around 7% in this particular case.Figure 17. The Internal Fault Management Differs Depending on the Considered VersionKnowing both the ending voltage and the charge current,we can easily calculate the timer capacitor value for a given delay. Suppose we need 40 ms. In that case, the capacitor is simply:C timer +I timer TV timer+11.7m 40m 5+94nF(eq. 15)Select a 100 nF value.Latch InputThe NCP1351 features a patented circuitry which prevents the FB input to be of low impedance before the Vcc reaches the VCC ON level. As such, the circuit can work in a primary regulation scheme. Capitalizing on this typical option, Figure 18 shows how to insert a zener diode in series with the optocoupler emitter pin. In that way, the current biases the zener diode and offers a nice reference voltage,appearing at the loop closure (e.g. when the output reachesthe target). Yes, you can use this reference voltage to supplya NTC and form a cheap OTP protection.Figure 18. The Latch Input Offers Everything Needed to Implement an OTP Circuit. Another Zener Can Help combining an OVP Circuit if NecessaryV CCFigure 19. You can either directly observe the V CC level or add a small RC filter to reduce the leakage inductance contribution. The best is to directly sense the output voltage and reacts if it runs away, as offered on the rightside.R OUTDesign Example, a 19 V / 3A Universal Mains Power Supply Designing aSwitch−Mode Power Supply using the NCP1351 does not differ from a fixed frequency design. What changes,however, is the regulation method via frequency variations.In other words, all the calculations must be carried at the lowest line input where the frequency will hit the maximum value set by the C t capacitor. Let us follow the steps:V in min = 100 Vdc (bulk valley in low−line conditions)V in max = 375 Vdc V out = 19 V I out = 3 AOperating mode is CCM η = 0.8F sw = 65 kHz1.Turn Ratio. This is the first parameter to consider.The MOSFET BV dss actually dictates the amount of reflected voltage you need. If we consider a 600 V MOSFET and a 15% derating factor, we must limit the maximum drain voltage to:V ds_max +600 0.85+510V(eq. 16)Knowing a maximum bulk voltage of 375 V , the clamp voltage must be set to:V clamp +510*375+135V(eq. 17)Based on the above level, we decide to adopt a headroom between the reflected voltage and the clamp level of 50 V . If this headroom is too small, a high dissipation will occur on the RDC clamp network and efficiency will suffer. A leakage inductance of around 1% of the magnetizing value should give good results with this choice (k c = 1.6). The turn ratio between primary and secondary is simply:ǒV out )V f ǓN+V clamp k c(eq. 18)Solving for N gives:N +N sp +k C ǒV out )V f ǓV clamp +1.6 (19)0.8)135(eq. 19)+0.234Let us round it to 0.25 or 1/N = 4Figure 20. Primary Inductance Current Evolutionin CCMLSWt2.Calculate the maximum operating duty−cycle for this flyback converter operated in CCM:d max +V out ńN V out ńN )V in_min+19 419 4)100+0.43(eq. 20)In this equation, the CCM duty−cycle does not exceed 50%. The design should thus be free of subharmonic oscillations in steady−state conditions. If necessary, negative ramp compensation is however feasible by the auxiliary winding.3.To obtain the primary inductance, we can use thefollowing equation which expresses the inductancein relationship to a coefficient k. This coefficientactually dictates the depth of the CCM operation.If it goes to 2, then we are in DCM.L+(V in_min d max)2F SW KP in(eq. 21)where K = D I L/I I and defines the amount of ripple we want in CCM (see Figure 20).•Small K: deep CCM, implying a large primary inductance, a low bandwidth and a large leakage inductance.•Large K: approaching BCM where the RMS losses are the worse, but smaller inductance, leading to a better leakage inductance.From Equation 16, a K factor of 0.8 (40% ripple) ensures a good operation over universal mains. It leads to an inductance of:L+(10043)265k0.872+493m H(eq. 22)+1.34A peak−to−peak (eq. 23)D I L+V in_min d maxLF SW+1930.8100The peak current can be evaluated to be:I in_avg+P outh V in_min+1000.43493m65k+712mA(eq. 24)I peak+I avgd)D I L2+0.7120.43)1.342+2.33A(eq. 25)On Figure 20, I1 can also be calculated:I I+I peak*D I L2+2.33*1.342+1.65A(eq. 26)The valley current is also found to be:I valley+I peak*D I L+2.33*u1.34+1.0A(eq. 27)4.Based on the above numbers, we can now evaluatethe RMS current circulating in the MOSFET andthe sense resistor:I d_rms+I I dǸ1)13ǒD I L2I1Ǔ2Ǹ(eq. 28)+1.650.651)13ǒ 1.342 1.65Ǔ2Ǹ+1.1A5.The current peaks to 2.33 A. Selecting a 1 V dropacross the sense resistor, we can compute its value:R sense+1I peak+12.5+0.4W(eq. 29)To generate 1 V, the offset resistor will be 3.7 k W, as alreadyexplained. Using Equation 28, the power dissipated in thesense element reaches:P sense+R sense I d_rms2+0.4 1.12+484mW(eq. 30)6.To switch at 65 kHz, the C t capacitor connected topin 2 will be selected to 180 pF.7.As the load changes, the operating frequency willautomatically adjust to satisfy either equation 5(high power, CCM) or equation 6 in lighter loadconditions (DCM).Figure 21 portrays a possible application schematicimplementing what we discussed in the above lines.。