HY57V64820HGT-S中文资料

4 Banks x 2M x 8Bit Synchronous DRAMThis document is a general product description and is subject to change without notice.Hynix Semiconductor does not assume any responsibility for use DESCRIPTIONThe Hynix HY57V64820HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V64820HG is organized as 4banks of 2,097,152x8.HY57V64820HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)FEATURES•Single 3.3±0.3V power supply•All device pins are compatible with LVTTL interface •JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch•All inputs and outputs referenced to positive edge of sys-tem clock•Data mask function by DQM •Internal four banks operation•Auto refresh and self refresh •4096 refresh cycles / 64ms•Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full page for Sequential Burst- 1, 2, 4 or 8 for Interleave Burst•Programmable CAS Latency ; 2, 3 ClocksORDERING INFORMATIONPart No.Clock FrequencyPower Organization Interface PackageHY57V64820HGT-5/55/6/7200/183/166/143MHzNormal4Banks x 2Mbits x8LVTTL 400mil 54pin TSOP IIHY57V64820HGT-K 133MHz HY57V64820HGT-H 133MHz HY57V64820HGT-8125MHz HY57V64820HGT-P 100MHz HY57V64820HGT-S 100MHz HY57V64820HGLT-5/55/6/7200/183/166/143MHzLow powerHY57V64820HGLT-K 133MHz HY57V64820HGLT-H 133MHz HY57V64820HGLT-8125MHz HY57V64820HGLT-P 100MHz HY57V64820HGLT-S100MHzPIN DESCRIPTIONPIN PIN NAME DESCRIPTIONCLK Clock The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLKCKE Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refreshCS Chip Select Enables or disables all inputs except CLK, CKE and DQMBA0, BA1Bank Address Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activityA0 ~ A11Address Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8 Auto-precharge flag : A10RAS, CAS, WE Row Address Strobe,Column Address Strobe,Write EnableRAS, CAS and WE define the operationRefer function truth table for detailsDQM Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode DQ0 ~ DQ7Data Input/Output Multiplexed data input / output pinVDD/VSS Power Supply/Ground Power supply for internal circuits and input buffersVDDQ/VSSQ Data Output Power/Ground Power supply for output buffersNC No Connection No connectionFUNCTIONAL BLOCK DIAGRAM 2Mbit x 4banks x 8 I/O Synchronous DRAMABSOLUTE MAXIMUM RATINGSNote : Operation at above absolute maximum rating can adversely affect device reliabilityDC OPERATING CONDITION (TA=0 to 70°C )Note :1.All voltages are referenced to V SS = 0V2.V IH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration3.V IL (min) is acceptable -2.0V AC pulse width with ≤3ns of durationAC OPERATING CONDITION (TA=0 to 70°C , V DD =3.3 ± 0.3V, V SS =0V)Note :1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF) For details, refer to AC/DC output circuitParameterSymbolRatingUnitAmbient Temperature T A 0 ~ 70°C Storage TemperatureT STG -55 ~ 125°C Voltage on Any Pin relative to V SS V IN , V OUT -1.0 ~ 4.6V Voltage on V DD relative to V SS V DD, V DDQ -1.0 ~ 4.6V Short Circuit Output Current I OS 50mA Power DissipationP D 1W Soldering Temperature ⋅ TimeT SOLDER260 ⋅ 10°C ⋅ SecParameterSymbol Min Typ.Max Unit Note Power Supply Voltage V DD , V DDQ 3.0 3.3 3.6V 1Input High Voltage V IH 2.0 3.0V DDQ + 2.0V 1,2Input Low VoltageV ILV SSQ - 2.00.8V1,3ParameterSymbol Value Unit NoteAC Input High / Low Level VoltageV IH / V IL 2.4/0.4V Input Timing Measurement Reference Level Voltage Vtrip 1.4V Input Rise / Fall TimetR / tF 1ns Output Timing Measurement Reference LevelVoutref 1.4V Output Load Capacitance for Access Time MeasurementCL50pF1CAPACITANCE (TA=25°C , f=1MHz)OUTPUT LOAD CIRCUITDC CHARACTERISTICS I (TA=0 to 70°C , V DD =3.3±0.3V)Note :1.V IN = 0 to 3.6V, All other pins are not tested under V IN =0V2.D OUT is disabled, V OUT =0 to3.6VParameterPinSymbol Min Max Unit Input capacitanceCLKC I124pF A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS, WE, DQMCI 2 2.55pF Data input / output capacitanceDQ0 ~ DQ7C I/O26.5pFParameterSymbolMin.Max Unit Note Input Leakage Current I LI -11uA1Output Leakage Current I LO -11uA 2Output High Voltage V OH 2.4-V I OH = -4mA Output Low VoltageV OL-0.4VI OL = +4mADC CHARACTERISTICS II (TA=0 to 70°C , V DD =3.3±0.3V, V SS =0V)Note :1.I DD1 and I DD4 depend on output loading and cycle rates. Specified values are measured with the output open2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II3.HY57V64820HGT-7/K/H/8/P/S4.HY57V64820HGLT-7/K/H/8/P/SParameterSymbolTest ConditionSpeedUnitNote-6-7-K -H -8-P/S Operating CurrentI DD1Burst length=1, One bank active t RC ≥ t RC (min), I OL =0mA 908585858580mA 1Precharge Standby Current in Power Down ModeI DD2P CKE ≤ V IL (max), t CK = min 2mA I DD2PSCKE ≤ V IL (max), t CK = ∞2mAPrecharge Standby Current in Non Power Down ModeI DD2NCKE ≥ V IH (min), CS ≥ V IH (min), t CK = min Input signals are changed one time during 2clks. All other pins ≥ V DD -0.2V or ≤ 0.2V 15mAI DD2NSCKE ≥ V IH (min), t CK = ∞Input signals are stable.12mA Active Standby Current in Power Down ModeI DD3P CKE ≤ V IL (max), t CK = min 6mA I DD3PSCKE ≤ V IL (max), t CK = ∞5mAActive Standby Current in Non Power Down ModeI DD3NCKE ≥ V IH (min), CS ≥ V IH (min), t CK = min Input signals are changed one time during 2clks. All other pins ≥ V DD -0.2V or ≤ 0.2V 30mAI DD3NSCKE ≥ V IH (min), t CK = ∞Input signals are stable.20mA Burst Mode Operating Current I DD4t CK ≥ t CK (min), I OL =0mA All banks activeCL=3150150150150130120mA 1CL=2NANA120mA Auto Refresh Current I DD5t RRC ≥ t RRC (min), All banks active 160mA 2Self Refresh CurrentI DD6CKE ≤ 0.2V1mA 3400uA4AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)Note :1.Assume tR / tF (input rise and fall time ) is 1ns2.Access times to be measured with input signals of 1v/ns edge rateParameterSymbol-6-7-K-H-8-P-SUnitNoteMinMaxMin MaxMin MaxMin MaxMin MaxMin MaxMin MaxSystem clock cycle timeCASLatency = 3tCK361000710007.510007.5100081000101000101000nsCASLatency = 2tCK210107.510101012ns Clock high pulse width tCHW 2.5- 2.5- 2.5- 2.5-3-3-3-ns 1Clock low pulse widthtCLW 2.5- 2.5- 2.5- 2.5-3-3-3-ns 1Access time from clockCASLatency = 3tAC3- 5.4- 5.4- 5.45.4-66-6ns2CASLatency = 2tAC2-6-6- 5.46-6-6-8ns Data-out hold time tOH 2.7- 2.7- 2.7- 2.7-3-3-3-ns Data-Input setup time tDS 1.5- 1.5- 1.5- 1.5-2-2-2-ns 1Data-Input hold time tDH 0.8-0.8-0.8-0.8-1-1-1-ns 1Address setup time tAS 1.5- 1.5- 1.5- 1.5-2-2-2-ns 1Address hold time tAH 0.8-0.8-0.8-0.8-1-1-1-ns 1CKE setup time tCKS 1.5- 1.5- 1.5- 1.5-2-2-2-ns 1CKE hold time tCKH 0.8-0.8-0.8-0.8-1-1-1-ns 1Command setup time tCS 1.5- 1.5- 1.5- 1.5-2-2-2-ns 1Command hold time tCH 0.8-0.8-0.8-0.8-1-1-1-ns 1CLK to data output in low Z-timetOLZ1- 1.5- 1.5- 1.5-1-1-2-nsCLK to dataoutput in high Z-time CASLatency = 3tOHZ35.45.45.45.4666nsCASLatency = 2tOHZ2nsAC CHARACTERISTICS IINote :1. A new command can be given tRRC after self refresh exitParameterSymbol-6-7-K-H-8-P-SUnitNoteMinMax Min Max Min Max Min Max Min Max Min Max Min Max RAS Cycle TimeOperationt RC 60-62-65-65-68-70-70-ns Auto Refresht RRC 60-62-65-65-68-70-70-ns RAS to CAS Delay t RCD 18-20-15-20-20-20-20-ns RAS Active Time t RAS 42100K 42120K 45120K 45120K 48120K 50120K 50120K ns RAS Precharge Timet RP18-20-15-20-20-20-20-ns RAS to RAS Bank Active Delay t RRD 12-14-15-15-16-20-20-ns CAS to CAS Delay t CCD 1-1-1-1-1-1-1-CLK Write Command to Data-In Delayt WTL 0-0-0-0-0-0-0-CLKData-In to Precharge Commandt DPL 2-1-1-1-1-1-1-CLK Data-In to Active Command t DAL 5-4-4-4-4-3-3-CLK DQM to Data-Out Hi-Z t DQZ 2-2-2-2-2-2-2-CLK DQM to Data-In Mask t DQM 0-0-0-0-0-0-0-CLK MRS to New Commandt MRD2-1-1-1-1-1-1-CLK Precharge to Data Output Hi-ZCASLatency = 3t PROZ33-3-3-3-3-3-3-CLKCASLatency = 2t PROZ22-2-2-2-2-2-2-CLK Power Down Exit Time t PDE 1-1-1-1-1-1-1-CLK Self Refresh Exit Time t SRE 1-1-1-1-1-1-1-CLK 1Refresh Timet REF-64-64-64-64-64-64-64msDEVICE OPERATING OPTION TABLEHYHY57V64820(L)T-657V64820HG(L)T-7HY57V64820HG(L)T-KHY57V64820HG(L)T-HHY57V64820HG(L)T-8HY57V64820HG(L)T-PHY57V64820HG(L)T-SCAS LatencytRCD tRAS tRC tRP tAC tOH 166MHz(6ns)3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.4ns 2.7ns 143MHz(7ns)3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns 133MHz(7.5ns)2CLKs3CLKs6CLKs9CLKs3CLKs5.4ns2.7nsCAS LatencytRCD tRAS tRC tRP tAC tOH 143MHz(7ns)3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns 133MHz(7.5ns)3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns 100MHz(10ns)2CLKs2CLKs5CLKs7CLKs2CLKs6ns3nsCAS LatencytRCD tRAS tRC tRP tAC tOH 133MHz(7.5ns)2CLKs 2CLKs 6CLKs 8CLKs 2CLKs 5.4ns 2.7ns 125MHz(8ns)3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns 100MHz(10ns)2CLKs2CLKs5CLKs7CLKs2CLKs6ns3nsCAS LatencytRCD tRAS tRC tRP tAC tOH 133MHz(7.5ns)3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns 125MHz(8ns)3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns 100MHz(10ns)2CLKs2CLKs5CLKs7CLKs2CLKs6ns3nsCAS LatencytRCD tRAS tRC tRP tAC tOH 125MHz(8ns)3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 6ns 3ns 100MHz(10ns)2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 83MHz(12ns)2CLKs2CLKs5CLKs7CLKs2CLKs6ns3nsCAS LatencytRCD tRAS tRC tRP tAC tOH 100MHz(10ns)2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 83MHz(12ns)2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 66MHz(15ns)2CLKs2CLKs4CLKs6CLKs2CLKs6ns3nsCAS LatencytRCD tRAS tRC tRP tAC tOH 100MHz(10ns)3CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 83MHz(12ns)2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 66MHz(15ns)2CLKs2CLKs4CLKs6CLKs2CLKs6ns3nsCOMMAND TRUTH TABLENote :1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high2. X = Don ′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address, Opcode = Operand Code, NOP = No OperationCommandCKEn-1CKEn CS RAS CAS WE DQM ADDRA10/AP BA NoteMode Register Set H X L L L L XOP codeNo Operation H XHXXXXXLH H H Bank Active HXLLHHXRAVReadHXLHLHXCALV Read with Autoprecharge H WriteHXLHLLXCALVWrite with Autoprecharge H Precharge All BanksHXLLHLXXHXPrecharge selected Bank L VBurst Stop H XLH HLX X DQM H X V X Auto RefreshH H L L L H X XBurst-READ-Single-WRITEH X L L L L X A9 Pin High(Other Pins OP code)Self Refresh 1EntryH L L L L H XXExitLHHXXXXL H H H Precharge power downEntryHLHXXXXXL H H HExitLHHXXXXL H H H Clock SuspendEntry H LHXXXXXLVVVExitLHXXHY57V64820HGRev. 0.5/Sep. 02 11PACKAGE INFORMATION400mil 54pin Thin Small Outline Package元器件交易网。