V53C516405AK50中文资料

MOSEL VITELIC V53C516405A4M X 4 EDO PAGE MODECMOS DYNAMIC RAMV53C516405A5060 Max. RAS Access Time, (t RAC)50 ns60 ns Max. Column Address Access Time, (t CAA)25 ns30 ns Min. Extended Data Out Page Mode Cycle Time, (t PC)20 ns25 ns Min. Read/Write Cycle Time, (t RC)84 ns104 nsFeaturess4M x 4-bit organizations EDO Page Mode for a sustained data rate of 50 MHzs RAS access time: 50, 60, 70 nss Low power dissipations Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh, Hidden Refresh s Refresh Interval: 4096 cycles/64 mss Available in 24/26-pin 300 mil SOJ, and 24/26-pin 300 mil TSOP-IIs Single +5 V ±10% Power Supplys TTL Interface DescriptionThe V53C516405A is a 4,194,304 x 4 bit high-performance CMOS dynamic random access memory. The V53C516405A offers Page mode operation with Extended Data Output. The V53C516405A has a symmetric address, 12-bit row and 10-bit column.All inputs are TTL compatible. EDO Page Mode operation allows random access up to 1024 x 4 bits, within a page, with cycle times as short as 20ns. These features make the V53C516405A ideally suited for a wide variety of high performance computer systems and peripheral applications.Device Usage ChartOperating Temperature Range Package Outline Access Time (ns)PowerTemperatureMarkK T5060Std.0°C to 70°C•••••BlankMOSEL VITELIC V53C516405APin NamesA0–A11Row, Column Address InputsRAS Row Address StrobeCAS Column Address StrobeWE Write EnableOE Output EnableI/O1–I/O4Data Input, OutputV CC+5V SupplyV SS0V SupplyNC No ConnectDescription Pkg.Pin CountSOJ K24/26TSOP-II T24/2624/26 Pin Plastic SOJ /TSOP-IIPIN CONFIGURATIONTop ViewMOSEL VITELIC V53C516405AAbsolute Maximum Ratings*Operating temperature range..................0 to 70 °C Storage temperature range...............-55 to 150 °C Input/output voltage.......-0.5 to min (V CC+0.5, 7) V Power supply voltage............................-1.0V to 7V Power dissipation..........................................1.0 W Data out current (short circuit)......................50 mA *Note:Operation above Absolute Maximum Ratings can adversely affect device reliability.Capacitance*T A = 25°C, V CC = 5 V ± 10%, V SS = 0 V, f = 1 MHz *Note: Capacitance is sampled and not 100% tested.Symbol Parameter Min.Max.Unit C IN1Address Input—5pFC IN2RAS, CAS, WE, OE—7pFC OUT Data Input/Output—7pFBlock DiagramMOSEL VITELIC V53C516405A DC and Operating Characteristics (1-2)T A = 0°C to 70°C, V CC = 5 V ± 10%, V SS = 0 V, t T = 2ns, unless otherwise specified.Symbol Parameter AccessTimeV53C516405AUnit Test Conditions Notes Min.Typ.Max.I LI Input Leakage Current(any input pin)–1010µA V SS≤ V IN≤ V CC + 0.5V1I LO Output Leakage Current(for High-Z State)–1010µA V SS≤ V OUT≤ V CC + 0.5VRAS, CAS at V IH1I CC1V CC Supply Current,Operating 5080mA t RC = t RC (min.)2, 3, 4 6070I CC2V CC Supply Current,TTL Standby 2mA RAS, CAS at V IHother inputs ≥ V SSI CC3V CC Supply Current,RAS-Only Refresh 5080mA t RC = t RC (min.)2, 4 6070I CC4V CC Supply Current,EDO Page ModeOperation 5035mA Minimum Cycle2, 3, 4 6030I CC5V CC Supply Current,during CAS-before-RASRefresh 50120mA2, 4 60110I CC6V CC Supply Current,CMOS Standby 1.0mA RAS ≥ V CC – 0.2 V,CAS ≥ V CC – 0.2 Vother inputs ≥ V SS1V CC Power Supply Voltage 4.5 5.0 5.5VV IL Input Low Voltage –0.50.8V1 V IH Input High Voltage 2.4V CC+0.5V1 V OL Output Low Voltage0.4V I OL = 4.2 mA1 V OH Output High Voltage 2.4V I OH = –5 mA1MOSEL VITELIC V53C516405AAC Characteristics(5, 6)T A = 0 to 70 ˚C,V CC = 5 V ± 10 %, t T = 2 ns#Symbol Parameter-50-60Unit Note min.max.min.max.Common Parameters1t RC Random read or write cycle time84–104–ns2t RP RAS precharge time30–40–ns3t RAS RAS pulse width5010k6010k ns4t CAS CAS pulse width810k1010k ns5t ASR Row address setup time0–0–ns6t RAH Row address hold time8–10–ns7t ASC Column address setup time0–0–ns8t CAH Column address hold time8–10–ns9t RCD RAS to CAS delay time 12371445ns10t RAD RAS to column address delay 10251230ns11t RSH RAS hold time1315–ns12t CSH CAS hold time4050–ns13t CRP CAS to RAS precharge time5–5–ns14t T Transition time (rise and fall) 150150ns7 15t REF Refresh period–64–64msRead Cycle16t RAC Access time from RAS –50–60ns8, 9 17t CAC Access time from CAS –13–15ns8, 9 18t CAA Access time from column address–25–30ns8,10 19t OEA OE access time–13–15ns20t RAL Column address to RAS lead time25–30–ns21t RCS Read command setup time0–0–ns22t RCH Read command hold time 0–0–ns11 23t RRH Read command hold time referenced to RAS 0–0–ns11 24t CLZ CAS to output in low-Z 0–0–ns8 25t OFF Output buffer turn-off delay 013015ns12 26t OEZ Output turn-off delay from OE013015ns12 27t DZC Data to CAS low delay 0–0–ns13 28t DZO Data to OE low delay0–0–ns13 29t CDD CAS high to data delay 10–13–ns14 30t ODD OE high to data delay 10–13 –ns14Write Cycle31t WCH Write command hold time 8–10–ns 32t WP Write command pulse width 8–10–ns 33t WCS Write command setup time 0–0–ns 1534t RWL Write command to RAS lead time 8–10–ns 35t CWL Write command to CAS lead time 8–10–ns 36t DS Data setup time 0–0–ns 1637t DHData hold time8–10–ns16Read-modify-Write Cycle38t RWC Read-write cycle time 113–138–ns 39t RWD RAS to WE delay time 64–77–ns 1540t CWD CAS to WE delay time27–32–ns 1541t AWD Column address to WE delay time 39–47–ns 1542t OEHOE command hold time10–13–nsEDO Page Mode Cycle43t PC EDO page mode cycle time 20–25–ns 44t CP CAS precharge time8–10–ns 45t CPA Access time from CAS precharge –27–32ns 746t COH Output data hold time5–5–ns 47t RASP RAS pulse width in EDO mode 50200k 60200k ns 48t RHPC CAS precharge to RAS Delay 27–32–ns 49t OESOE setup time prior to CAS5–5nsEDO Page Mode Read-modify-Write Cycle50t PRWC EDO page mode read-write cycle time 58–68–ns 51t CPWDCAS precharge to WE41–49–nsCAS-before-RAS Refresh Cycle52t CSR CAS setup time 10–10–ns 53t CHR CAS hold time10–10–ns 54t RPC RAS to CAS precharge time 5–5–ns 55t WRP Write to RAS precharge time 10–10–ns 56t WRHWrite hold time referenced to RAS10–10–nsAC Characteristics (5, 6)T A = 0 to 70 ˚C,V CC = 5 V ± 10 %, t T = 2 ns#SymbolParameter-50-60Unit Notemin.max.min.max.CAS-before-RAS Counter Test Cycle57t CPTCAS precharge time35–40–nsTest Mode61t WTS Write command setup time 10–10–ns 62t WTH Write command hold time 10–10–ns 63t CHRT CAS hold time30–30–ns 64t RAHTRAS hold time in test mode30–30–nsAC Characteristics (5, 6)T A = 0 to 70 ˚C,V CC = 5 V ± 10 %, t T = 2 ns#SymbolParameter-50-60Unit Notemin.max.min.max.Notes:1)All voltages are referenced to V SS.2)I CC1, I CC3, I CC4 and I CC5 depend on cycle rate.3)I CC1 and I CC4 depend on output loading. Specified values are obtained with the output open.4)Address can be changed once or less while RAS = V IL. In case of I CC4 it can be changed once or less during a EDOpage mode cycle5)An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has to bea refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimumof 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.6)AC measurements assume t T = 2 ns.7)V IH (min.) and V IL (max.) are reference levels for measuring timing of input signals. Transition times are also measuredbetween V IH and V IL.8)Measured with the specified current load and 100 pF at V OL = 0.8 V and V OH = 2.0 V. Access time is determined bythe latter of t RAC, t CAC, t CAA,t CPA, t OEA . t CAC is measured from tristate.9)Operation within the t RCD (max.) limit ensures that t RAC (max.) can be met. t RCD (max.) is specified as a reference pointonly. If t RCD is greater than the specified t RCD (max.) limit, then access time is controlled by t CAC.10)Operation within the t RAD (max.) limit ensures that t RAC (max.) can be met. t RAD (max.) is specified as a reference pointonly. If t RAD is greater than the specified t RAD (max.) limit, then access time is controlled by t CAA.11)Either t RCH or t RRH must be satisfied for a read cycle.12)t OFF (max.), t OEZ (max.) define the time at which the output achieves the open-circuit conditions and are not referencedto output voltage levels. t OFF is referenced from the rising edge of RAS or CAS, whichever occurs last.13)Either t DZC or t DZO must be satisfied.14)Either t CDD or t ODD must be satisfied.15)t WCS, t RWD, t CWD and t AWD are not restrictive operating parameters. They are included in the data sheet as electricalcharacteristics only. If t WCS > t WCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if t RWD > t RWD (min.), t CWD > t CWD (min.) and t AWD > t AWD (min.), the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate.16)These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles.Waveforms of Read CycleRASCASAddressWEOEI/O(Inputs)I/O(Outputs)V IHV IL“H” or “L”WL1V IHV ILV IHV ILV IHV ILV IHV ILV IH V ILV VWaveforms of Write Cycle (Early Write) RASCASAddressWEOEI/O(Inputs)I/O (Outputs)“H” or “L”WL2 V IHV ILV IHV ILV IHV ILV IHV ILV IHV ILV IHV ILV OHV OLWaveforms of Write Cycle (OE Controlled Write)“H” or “L”RASCASAddressWEOEI/O(Inputs)I/O(Outputs)WL3V IHV ILV V V IHV ILV IHV ILV IHV ILV IHV ILV IHV ILWaveforms of Read-Write (Read-Modify-Write) CycleI/O(Outputs)I/O(Inputs)OEWE“H” or “L”RASCASAddressWL4V IH V ILV IHV ILV IHV ILV IHV ILV IHV ILV IHV ILV OLVWaveforms of EDO Page Mode Read CycleRASI/O WEAddressCASV IHV IL“H” or “L”OE(Output)WL5V IHV ILV IHV ILV IHV ILV OHV OLV IH V ILWaveforms of EDO Page Mode Early Write CycleRASI/O (Input)WEAddressCAS“H” or “L”OEWL8V IHV ILV IHV ILV IHV ILV IHV ILV V V IHV ILWaveforms of RAS Only Refresh CycleAddressRASCASI/O(Outputs)“H” or “L”WL9V IH V ILV IHV ILV IHV ILV OHV OLWaveforms of CAS-before-RAS Refresh Cycle“H” or “L”RASI/O(Outputs)I/O(Inputs)OEWECASWL10V V ILV V ILV V ILV V ILV V ILV VWaveforms of Hidden Refresh Read CycleRASI/O(Outputs)I/O(Inputs)OEWEAddressCAS“H” or “L”WL11V V ILV V ILV V ILV V ILV V ILV V ILV VWaveforms of Hidden Refresh Early Write CycleRASI/O(Output)I/O (Input)WEAddressCAS“H” or “L”WL12V V V V V V V V V V V OHV OLWaveforms of CAS-before-RAS Refresh Counter Test CycleRASI/O(Inputs)OE WEAddressCASI/O(Outputs)I/O(Outputs)I/O(Inputs)WEOERead Cycle:Write Cycle:V V V V V V V V V V V V V V V V V V V V V VWaveforms of Test Mode EntryI/O(Outputs)I/O(Inputs)OEWECASRAS“H” or “L”AddressWL15V V V V V V V V V V V V V V OFFTest ModeAs the V53C516405A is organized internally as 1M x 16-bits, a test mode cycle using 4:1 compres-sion can be used to improve test time. Note that in the 4M x 4 version the test time is reduced by 1/4 for a N test pattern.In a test mode “write” the data from each I/O pin is written into four 1M blocks simultaneously (all “1” s or all “0” s). In test mode “read” each I/O output is used for indicating the test mode result. If the inter-nal four bits are equal, the I/O would indicate a “1”.If they were not equal, the I/O would indicate a “0”. The WCBR cycle (WE, CAS before RAS) puts the device into test mode. To exit from test mode, a “CAS before RAS refresh”, “RAS only refresh” or “Hidden refresh” can be used.Refresh during test mode operation can be performed by normal read cycles or by WCBR refresh cycles.Row addresses A0 through A9 have to kept high to perform a testmode entry cycle. All other address-es are don’t care.Block Diagram in Test ModePackage Diagrams24/26-pin 300 mil SOJ24/26-pin 300 mil TSOP-IIMOSEL VITELIC WORLDWIDE OFFICES V53C516405A© Copyright 1998, MOSEL VITELIC Inc.3/98Printed in U.S.A. U.S. SALES OFFICESThe information in this document is subject to change without notice.MOSEL VITELIC makes no commitment to update or keep cur-rent the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC.MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica-tions. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil-ity for consequential or incidental arising from any use of its prod-ucts. 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