51.2 A New Low Power PMOS Poly-Si Inverter and Driving Circuits

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AMOLED-LTPS-OLED介绍

Seal & Encapsulation
Module Process
Evaluation Process
Driver IC Attachment
FPC
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TFT Process
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Silicon Material
a-Si:H Poly Si Single Si
Crystallization
New a-Si & gate oxide New structure & Circuit
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TFT Issue - ELA LTPS TFT
Merits & Demerits

ELA-LTPS TFT AMOLED W/S

Good Stability of TFT Circuit Integration Possibility of PMOS TFT Low Uniformity of Transistor High investment and Process cost Low scalability (Gen. 4)
Total Material Cost : 85.5%
BLU Pol.
BLU
Pol. C/F Glass+Encap
basically low material cost
C/F 30.3% Glass 7.6% Ref : SDI (’06.1)
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AMOLED Development History
STN TFT OLED
50% Mobile Display Div.

Sub-1V CMOS Voltage Reference Based on Weighted Vgs

cuit .
1 Introduction
The usage of portable devices such as mo bile p ho nes is rapidly sp reading all over t he world. So me simple self2biasing circuit s such as voltage references are widely used in t hese bat tery2opera2 ted devices. In t he past ,voltage references have u2 sually co nsisted of bandgap references , which can be implemented using parasitic vertical BJ Ts in standard CMOS technology [ 1 ,2 ] . However , t he parasitic bipolar t ransistor in a CMOS p rocess is u2 sually not very well characterized , and t he power efficiency is not sufficient for low2power operatio ns due to t he large dropo ut voltage. It is expected t hat t he whole system will be able to operate o n a single 1V supply in t he near f ut ure. In t his paper , a sub21V voltage reference in standard CMOS technology based o n t he weighted gate2so urce voltage difference bet ween an nMOS and a p MOS is p resented. The design techniques for achieving good performance are al so p resented in detail .

MEMS 实验使用L-Edit画PMOS布局图

XXXXXXXX大学（MEMS）实验报告实验名称使用 L-Edit 画PMOS 布局图实验时间年月日专业姓名学号预习操作座位号教师签名总评一、实验目的：1、熟悉版图设计工具L-Edit的使用方法，并且能正确的使用这些工具；2、掌握版图设计的设计规则；3、能运用L-Edit 实现器件的布局图，以PMOS与NMOS设计为例；二、基本原理：1、CMOS器件的制作工艺2、PMOS器件和NMOS器件的版图实验原理截图：（1）PMO版图设计原理图：（2）CMOS版图设计原理图：3、设计版图时的注意事项：（1）L-Edit编辑环境是预设在P型基板上，故在P型基板上制作PMOS的第一步是需要做出N Well区，即需设定N阱区；然而对于NMOS则不需要N Well群区。

此外在设计版图时，需要将图绘制在原点之上，否则不利用版图截面的观察。

（2）改变图形大小的方法：“alt+鼠标拖动边框”；移动图形的方法“alt+鼠标拖动图形”；（3）绘制各图层之前需先通过Tools---DRC Setup查看对应的设计规则，从而选择确定图层的大小；绘制完一个图层都需DRC 进行设计规则检查；（4）各图层绘制无先后顺序的规定；（5）绘图时可适当使用“尺子”功能,以确保版图设计的对称性；清除图中的“尺寸”使用“View---Objects---Rules”或者选中后删除。

（6）对版图设计时，要注意时刻遵循设计规则，否则会出错误。

（7）对版图进行截面观察时，应注意选择好文件的路径，并且要设置好适当的界线位置。

三、实验内容及步骤：（1）打开 L-Edit 程序。

（2）另存新文件：选择 File---Save As命令，打开“另存为”对话框，在“保存在”下拉列表框中选择存储目录，在“文件名”文本框中输入新文件名称，例如：exp3。

（3）取代设定：选择File---Replace Setup命令，单击出现的对话框的From file 下拉列表右侧的 Browser按钮，择…:\LEdit83\Samples\SPR\example1\lights.tdb文件，再单击 OK 按钮，就可将 lights.tdb 文件的设定选择性应用在目前编辑的文件，包括格点设定、图层设定等。

5 V pMOS器件的热载流子注入退化机理

5 V pMOS器件的热载流子注入退化机理杨翰琪;刘小红;吕康;魏家行;孙伟锋【摘要】研究了低压pMOS器件热载流子注入HCI(Hot-Carrier Injection)退化机理,分析了不同的栅压应力下漏极饱和电流(Idsat)退化出现不同退化趋势的原因.结合实测数据并以实际样品为模型进行了器件仿真,研究表明,快界面态会影响pMOS器件迁移率,导致Idsat的降低;而电子注入会降低pMOS器件阈值电压(Vth),导致Idsat的上升.当栅压为-7.5 V时,界面态的产生是导致退化的主要因素,在栅压为-2.4 V的应力条件下,电子注入在热载流子退化中占主导作用.【期刊名称】《电子器件》【年(卷),期】2018(041)005【总页数】4页(P1093-1096)【关键词】pMOS;热载流子注入;不同栅压应力;TCAD仿真【作者】杨翰琪;刘小红;吕康;魏家行;孙伟锋【作者单位】东南大学国家专用集成电路系统工程技术研究中心,南京210096;华润上华半导体有限公司,江苏无锡214000;华润上华半导体有限公司,江苏无锡214000;东南大学国家专用集成电路系统工程技术研究中心,南京210096;东南大学国家专用集成电路系统工程技术研究中心,南京210096【正文语种】中文【中图分类】TN386.1随着集成电路制造工艺迅速向深亚微米、超深亚微米方向不断发展,热载流子效应已经成为限制器件与电路的寿命及可靠性的主要因素之一[1-2]。

目前,对MOS器件的热载流子退化研究主要是针对n型金属氧化物半导体晶体管(nMOSFET)。

由于在相同电场中迁移率小的空穴获得的动能远小于迁移率大的电子,所以在相同电压偏置下,p型金属氧化物半导体晶体管(pMOSFET)中热空穴引起的器件损伤远小于nMOS器件中热电子引起的器件损伤,因此pMOS器件的热载流子退化的研究一直为人们所忽视[3-5]。

但随着器件尺寸进入亚微米和深亚微米范围,pMOS器件的热载流子退化变得越来越严重,已成为CMOS电路退化以及失效不可忽视的因素,所以对pMOS器件的热载流子退化进行深入研究是十分必要的。

一种常温下聚苯乙烯微流控芯片的制备方法(英文)

Sensors and Actuators B 248(2017)311–317Contents lists available at ScienceDirectSensors and Actuators B:Chemicalj o u r n a l h o m e p a g e :w w w.e l s e v i e r.c o m /l o c a t e /s nbSilicon based solvent immersion imprint lithography for rapid polystyrene microﬂuidic chip prototypingJingdong Chen a ,∗,Wenjie Wang a ,Weibang Ji a ,Shaoding Liu a ,Qiushu Chen b ,Bimin Wu b ,Rhima Coleman b ,Xudong Fan a ,b ,∗aKey Lab of Advanced Transducers and Intelligent Control System,Ministry of Education and Shanxi Province,College of Physics and Optoelectronics,Taiyuan University of Technology,79Yingze Street,Taiyuan 030024,PR China bDepartment of Biomedical Engineering,University of Michigan,1101Beal Avenue,Ann Arbor,Michigan 48109,USAa r t i c l ei n f oArticle history:Received 12December 2016Received in revised form 24March 2017Accepted 28March 2017Available online 30March 2017Keywords:Polystyrene chip Si-SIILHigh aspect ratio Cell culturea b s t r a c tPolystyrene (PS)is preferred over polydimethylsiloxane (PDMS)in microﬂuidics for applications in cell biology.However,PS has not found widespread use in microﬂuidics due mainly to the lack of rapid pro-totyping techniques.Here we address this issue by developing a silicon based solvent immersion imprint lithography (Si-SIIL)technique.Silicon is rigid,mechanically robust,and highly compatible with standard microfabrication processes,and therefore,is a promising candidate for molds.Various PS microﬂuidic channels as small as 20␮m in width with the aspect ratio as high as 5were demonstrated using Si-SIIL.Bubbles and bending generated in the fabrication process were analyzed and eliminated.The surface roughness was about 27nm (rms).Compared to the untreated PS,the molded PS retained almost the same surface properties,as characterized by contact angle measurement and X-ray photoelectron spec-troscopy.Cell culture was tested to demonstrate the utility of Si-SIIL in cell biology applications.The results show that PS,with the aid of Si-SIIL,can be an alternative material to PDMS in building microﬂuidic chips.©2017Elsevier B.V.All rights reserved.1.IntroductionIn the past decade microﬂuidics in biological applications has experienced signiﬁcant growth due to its advantages of small vol-ume,low cost,short reaction time,and high throughput [1–5].The materials for microﬂuidics usually include silicon,glass,and poly-mer [6].While silicon and glass were commonly used in the earlier years of microﬂuidics development [7,8],polymer has become an increasingly attractive alternative [9–12].Polymers encompass a large class of materials,including two major categories:elastomers and thermoplastics [13].Since Whitesideset al.[14]fabricated com-plex microﬂuidic devices based on polydimethylsiloxane (PDMS),it has been widely employed in microﬂuidics due to its low cost,optical transparency,biocompatibility,and simple processing and prototyping [9,15,16].However,despite all the afore mentioned beneﬁcial properties,PDMS suffers from easy deformation,rapid liquid evaporation,absorption of molecules into the polymer,∗Corresponding authors.E-mail addresses:chenjingdong@ (J.Chen),xsfan@ (X.Fan).leaching of uncross-linked oligomers,and hydrophobic recovery [17,18],which signiﬁcantly limit its adoption in microﬂuidics for biological research.As an alternative microﬂuidic material,polystyrene (PS),one of the mostly used thermoplastics,has been studied and used for macroscopic cell culture and bioanalysis,thanks to its low cost,optical transparency,biocompatibility,chemical stability,and physical rigidity [19,20].Furthermore,it can easily be transferred from hydrophobic to hydrophilic by plasma treatment and remains hydrophilic for 4weeks,about 4times longer than PDMS [21].As such,PS is preferred over PDMS in microﬂuidics for cell biology applications.However,the fabrication of PS microﬂuidic chips is usually more difﬁcult and expensive than PDMS.Therefore,it is crucial to develop simple and cost-effective processes with high resolution and repeatability for rapid PS microﬂuidic prototyping.In the past,a number of PS microfabrication methods have been explored.Hot embossing relies on relatively high tempera-ture (120◦C,20◦C above the glass transition temperature of PS)and metal molds to create microﬂuidic devices [22,23].However,metal molds are fabricated by a laser system,which process is time-consuming and of high cost,and therefore,may not be suitable for/10.1016/j.snb.2017.03.1460925-4005/©2017Elsevier B.V.All rights reserved.312J.Chen et al./Sensors and Actuators B248(2017)311–317rapid lab ser cutting is another technology to fab-ricate microﬂuidic devices[24].For example,Li et al.[25]used a CO2laser to create droplet microﬂuidic devices on a PS substrate. Laser cutting is a mask-free method,but its process is sequential and becomes very time-consuming and costly with a large number of devices.In contrast,injection molding is capable of fabricating multiple microﬂuidics simultaneously with low costs.However,it requires dedicated tools such as injection moldingmachines[26]. Johnson et al.[27]and Pentecost et al.[28]developed a method similar to the injection molding method but free of injection mold-ing machines.In their method,PS powder was poured into an aluminum weighing dish and then heated to250◦C for several hours.Unfortunately,this process does not allow for room tem-perature fabrication.To circumvent such an issue,Nargang et al.[29]used several toxic chemicals,e.g.,toluene,isopropanol,and cyclohexanone,to dissolve PS before the use of a PDMS mold.A major drawback of this method is the distortion(such as swelling) in the PDMS mold in the presence of those chemical solutions [30].Therefore,it is crucial toﬁnd a solvent that can dissolve PS, but does not distort the PDMS mold.Gamma-butyrolactone and delta-valerolactone were found to be appropriate solvents based on their ability to dissolve PS without swelling PDMS[30].How-ever,they need seven days to form a PS solution in a tubeﬁlled with PS solid and organic solvent[30].Recently,solvent immer-sion imprint lithography(SIIL)has been developed that enables complete PS microﬂuidics prototyping in a single processing step [31,32].In this method,the PS surface isﬁrst softened by acetone and then imprinted with a PDMS mold.SIIL is simple and rapid and does not require sophisticated tools or heating processes.How-ever,PDMS has an elastic modulus of about1–3MPa,three orders of magnitude lower than that of thermoplastics like PS(∼3GPa), which makes PDMS easy to deform[17,31].Consequently,it is dif-ﬁcult to transfer structures with highﬁdelity from a PDMS mode to PS,especially when a high aspect ratio is needed[31].Here we developed a silicon based solvent immersion imprint lithography(Si-SIIL)method for rapid PS microﬂuidics prototyping. Silicon is much more rigid than PDMS and highly compatible with standard microfabrication processes,and therefore,is a promis-ing candidate for molds.In this article,we present the details of the Si-SIIL and contrast it with PDMS-SIIL whenever possible.Var-ious microﬂuidic channels as small as20␮m in width with the aspect ratio as high as5were demonstrated.Characterization of the Si-SIIL molded PS chips using contact angle measurement,X-ray photoelectron spectroscopy(XPS),and cell cultivation is also discussed.2.Material and methods2.1.Fabrication of Si moldThe silicon mold with inverse structures was fabricated using standard microfabrication technology using the following steps.(1) A silicon wafer was cleaned using a mixture of H2SO4and H2O2 solution.(2)A300nm SiO2layer was deposited on the wafer by plasma enhanced chemical vapor deposition(PECVD),which was used to form the mask layer for subsequent silicon etching.(3) The silicon wafer was spin-coated with a5␮m AZ4620photoresist layer,followed by baking at95◦C for120s,exposure to UV light for 5.5s,and development for45s.In order to increase the strength of the photoresist layer,the wafer was baked at110◦C for120s.(4) The SiO2layer was etched by reactive ion etching[33]for about 40min.(5)The Si wafer was etched for different amount of time using deep reactive ion etching[34]to obtain different depths.(6) Finally,the photoresist was removed using acetone.2.2.Si-SIIL protocolThe basic procedures of Si-SIIL are summarized as follows.The PS surface wasﬁrst softened using solvent,then the softened sur-face was imprinted with a Si mold,andﬁnally the PS was bonded to a PS substrate.Acetone was used to soften PS according to the SIIL method[31].During Si-SIIL,a1.48mm thick PS slab was immersed in acetone solvent for0.5–3min at room temperature.Acetone dif-fuses into the PS to form a surface“gel”layer(Fig.1(a)).A drop of acetone was dropped on the surface of a Si mold until acetone spread completely over the mold(Fig.1(b)).The immersed PS was removed from the acetone solution and subsequently placed on the Si mold.A weight(about1kg)was placed on the other side of the PDMS slab via a2mm thick PDMS slab to provide pressure for structure transfer(Fig.1(c)).The PS slab and the mold were placed in a small vacuum chamber for1.5h to let acetone evaporate and subsequently release the PS from the mold.Note that without the vacuum chamber,acetone evaporation and the PS release take10h. In contrast,in PDMS based SIIL,the porous PDMS enables rapid sol-vent removal from the polymer and quick PS release[31].Finally, another PS slab punched with inlets/outlets was immersed in ace-tone for about5s,and then bonded with the PS slab with structures (Fig.1(d)).2.3.Gel layer thickness and transmittanceThe immersed PS slab after acetone evaporation was used for the ultraviolet-visible(UV-vis)measurement.Then the PS slab was broken into two pieces to measure the gel layer thickness.2.4.Water contact angle measurementTo study the effect of immersion time in acetone on the PS sur-face properties,the static water contact angle was measured using droplets of water(about1␮l)applied to the free surface of PS slabs that underwent acetone immersion,acetone immersion followed by O2plasma treatment,and no treatment.2.5.Cell cultureThe biocompatibility of the PS after Si-SIIL was assessed by 24h cultivation of transduced ATDC5cells,which are derived from mouse teratocarcinoma.The responsiveness and proliferation of the cells on the chip were determined by drug-induced lumines-cence,while cell morphology and death rate were visualizedby Fig.1.Illustration of the Si-SIIL protocol.(a)A PS slab is immersed in acetone for0.5–3min under room temperature to form a surface“gel”layer on both sides.(b)A drop of acetone is dropped and uniformly distributed on the silicon mold surface.(c)The softened PS is placed on the silicon mold and then a weight is placed on the other side of the PS slab via a PDMS cushion(2mm thick)to provide the pressure for structure transfer.(d)Another PS slab with inlets/outlet is immersed in acetone for about5s and then bonded with theﬁrst PS slab via manual pressing.J.Chen et al./Sensors and Actuators B248(2017)311–317313Fig.2.(a)A prototype of a PS microﬂuidic chip with an aspect ratio of5(30␮m wide,150␮m deep).Blue ink was used for visualization of the channel.(b)SEM image of the circled part in(a).(c)Image of a channel cross section.ﬂuorescence imaging[19].The PS chip was rinsed with DI water and air dried before sterilized in a UV hood overnight.Collagen coat-ing was performed before UV sterilization for improvement of cell adhesion.Then,cells were seeded on the PS surface within the Si-SIIL deﬁnedﬂuidic channels.Cells were incubated in a37◦C,5%CO2 incubator.6h after seeding,doxycycline was added to the medium, which can stimulate luciferase expression inside the transduced cells.The substrate D-luciferin was added11h after seeding.Lumi-nescence was measured12h and24h after seeding.Then cells were exposed to acridine orange and propidium iodide to visualize live and dead cells simultaneously.Propidium iodide can only enter and stain dead cells by interacting with DNA,generating redﬂuores-cence(>600nm)upon excitation around570nm.Acridine orange, on the other hand,can diffuse freely through live cell membrane and interact with DNA,resulting in a greenﬂuorescence(∼520nm) signal upon excitation around500nm.3.Results and discussion3.1.CharacterizationPS microﬂuidic chips with various channel widths and heights(20␮m×25␮m,30␮m×150␮m,100␮m×100␮m,and 150␮m×100␮m)were fabricated successfully using Si-SIIL.It is shown that structures with an aspect ratio(height:width)as high as5(30␮m in width,150␮m in height)can be imprinted,much higher than0.24aspect ratio achieved previously with PDMS-SIIL [31](Note:an aspect ratio of2was achieved with PDMS-SIIL,but in a channel of only about3␮m long).In order to test the bond-ing performance,we injected blue ink into the chip and no leakage was observed from the channel,as shown in Fig.2(a).The images of scanning electron microscope(SEM)and a channel cross sec-tion are shown in Figs.2(b)and(c),respectively.The wall oftheFig.3.AFM images of(a)Si mold,(b)original PS,(c)PS after immersion,and(d)PS after imprint,showing an average surface roughness(rms)of about1.7nm,1.8nm,4.9nm, and27nm,respectively,over an area of400␮m2.314J.Chen et al./Sensors and Actuators B248(2017)311–317Fig.4.The gel layer thickness and the transmittance related to the immersion time of PS in acetone.The gel layer thickness increases and the transmittance decreases with the immersion time of PS in acetone.channel is not completely vertical and the angle between the wall and the bottom of channel is about85◦,which might be caused by shrinkage of the gel layer during the drying process.Fig.3shows the images of roughness distribution of the Si mold,the original PS,the PS after immersion,and the PS after imprint measured by atomic force microscopy(AFM),giving an average surface roughness rms of about1.7nm,1.8nm,4.9nm,and27nm,respectively,over an area of400␮m2.We note that the surface roughness is different from between the channel wall and the place of without structure. As compared to the plane part of without structure,the protrusion structure of the mold may cause in-homogeneities in imprint and drying process,which may further increase the roughness.Acetone diffuses into the PS to generate a surface gel layer.The gel layer after acetone evaporation is visually different from the bare PS.Fig.4shows the gel layer growth and the transmittance decrease over the immersion time of PS in acetone.The gel layer thickness increases with the immersion time but the progress slows down gradually,which reﬂects the acetone diffusion process inside the PS.In about2.5min,the gel layer reaches150␮m,which meets the need for imprint a channel of150␮m in depth.The visible light(wavelength:400–760nm)transmittance of a 1.48mm thick bare PS is about89%.According to Lambert-Beer law, the transmittance T of a sample is related to its absorbance A by:T=10−A e−bxwhere b is the extinction coefﬁcient.x is the thickness of the sample. The extinction coefﬁcient of the bare PS is about0.08mm−1.The decrease in the transmittance after the PS immersed in acetone is due to the formation of the gel layer,which has an extinction coefﬁcient of about2mm−1based on the results in Fig.4.The Si mold can be re-used.The number of reuses depending on the features on the mold.For example,the Si mold with high aspect ratios(e.g.,L×W×H=1cm×30␮m×150␮m)could be re-used about4–10times on average due to high aspect ratios and long channel lengths.Any damage along the1cm thin protrusion on the mold will make it unsuitable for re-use.In contrast,a Si mold with low aspect ratios(e.g.,L×W×H=1cm×20␮m×25␮m)had been re-used more than50times without any damage to the mold or failure in the channels.Although a minimum resolution of20␮m was presented,we believe that20␮m is not the resolution limit of the method and fea-tures smaller than20␮m can be imprinted.However,with smaller features,the Si mold becomes easier to get damaged due to a large aspect ratio,making the Si-SIIL practicallychallenging.Fig.5.(a)Image of the rough PS surface caused by the gas generated from the contact of Si mold and PS;(b)Image of the smooth PS surface using a drop of acetone dropped on the silicon mold surface.3.2.Bubble formation and eliminationIt is important to create a PS structure with a smooth inner sur-face.Previously,in the PDMS-SIIL method,since the gas generated at the interface of PDMS and PS can be vented out via the PDMS mold due to its high gas permeability[35–37],the PS surface qual-ity could be maintained and no bubbles were observed.However, this is not the case for a silicon mold,which is impermeable to gases. Gas trapped between the silicon mold and the PS slab resulted in bubbles and patches on the PS surface,as shown in Fig.5(a).To solve this issue,a drop of acetone was dropped on the silicon mold surface.Acetone spread completely over the mold to remove the gas near the mold surface.Therefore,when the PS slab was sub-sequently placed on the mold,they were in contact via a layer of acetone and there was no gas between the PS slab and the mold. The resultant clean PS slab is shown in Fig.5(b).3.3.PS bending and eliminationIdeally,the side of a PS slab that does not have any structures should not be treated with acetone in order to maintain a smooth and clean surface.However,the PS slab with a single side(the side with structures)treated with acetone bends(Fig.6(a))due to the different stresses between the side with and without acetone treat-ment.Tomitigate and even eliminate PS bending,in our studies both sides of the PS slab were acetone treated.To avoid bubbles generated at the interface between theﬂat side of the PS slab(the side without structures)and the weight.A2mm thick PDMS slab was placed between the PS and the weight to vent out residual gases.As a result,a PS slab free of bending and bubbles on both sides can be fabricated(Fig.6(b)).Note that the PDMS slab used here had no structures and was employed simply to avoid PS bending.3.4.Water contact angle measurementThe water contact angle of the original PS prior to acetone immersion was93◦,which agrees well with values from the lit-erature[29].The contact angle for the PS with0.5min,1min,and 2min immersion in acetone was90◦,92◦,and91◦,respectively, as shown in Fig.7,suggesting that acetone(and the immersion time)has little effect on surface hydrophobicity.To reduce adsorp-tion of hydrophobic molecules,the PS surface can be made moreJ.Chen et al./Sensors and Actuators B 248(2017)311–317315Fig.6.(a)A bent PS slab caused by the different stresses on both sides due to acetone treatment of only single side.(b)A straight PS slab when both sides of a PS is treated with acetone.To further removes bubbles on the ﬂat side (the side without structures),a 2mm thick PDMS slab is placed between the PS and the heavy object to vent out gases at theinterface.Fig.7.Water contact angles of PS at different immersion time.(a)no immersion,(b)0.5min immersion,(c)1min immersion,(d)2min immersion,(e)no immersion and 5min O 2treatment,(f)2min immersion and 5min O 2treatment.hydrophilic using oxygen plasma treatment [38–40].The water contact angle for the PS with 5min of O 2plasma treatment was 25◦(without prior acetone immersion)and 27◦(with 2min of prior ace-tone immersion),as shown in Fig.7,indicative of a more hydrophilic surface.The surface can remain hydrophilic for 4weeks [19,21].The hydrophobic recovery can be further delayed by storing PS chips in water after treatment [19].3.5.X-ray photoelectron spectroscopyIn order to better understand the PS surface chemistry change after Si-SIIL,XPS was carried out to characterize the surface ele-ment composition.Fig.8compares the relative atom contents of C1s (C-C or C-H bonds,99.67%vs.69.79%),O 1s (C-O bonds,0.25%vs.17.96%),and Si 2p (Si-O bonds 0.08%vs.12.26%)in the original PS and after acetone treatment and imprint on a Si mold.Signif-icant O 1s increase is expected,as acetone is an oxidation agent.The increase of Si 2p is due to the use of the Si mold.Those changes have little effect on water contact angles,as previously shown in Fig.7.Fig.8.XPS analysis of the surface element of original PS and PS after acetone immer-sion and imprint on Si mold.3.6.Cell culture50,000cells were seeded on a 6cm 2Si-SIIL treated PS chip.As control,50,000cells were also seeded on the bottom of a conven-tional culture plate well.Luminescence measurement shows that cells on the PS chip had a similar increase trend (around 3fold)in 12h (from 12h after seeding to 24h after seeding)as those on the cell culture plate (Table 1).This suggests that cells on the PS chip have similar growth rate and luciferase expression level as control.Difference in absolute luminescence counts between the control well and PS chips results mainly from different optical characteristics of the chip and the well plate.For ﬂuorescence imag-ing,culture medium was removed and the chip was rinsed with PBS buffer,then stained for 4min with 5␮g/mL propidium iodide and 2␮g/mL acridine orange.Then cells were rinsed with PBS and imaged immediately using an Olympus ﬂuorescence microscope.As shown in Fig.9,cells on a Si-SIIL treated PS chip had normal morphology and no dead cells were visible on the chip.We also performed the same test with a PS chip coated with collagen.No sig-niﬁcant difference was observed in luminescence tests,compared to the non-coated chip,in 24-hour incubation (Table 1),suggesting that cells adhered to and proliferated normally on the PS chip either with or without the collagen coating.These experiment results sug-gest that the Si-SIIL treatment on PS surface does not affect the biocompatibility of PS.Cells can adhere on the treated PS surfaceTable 1Luminescence measurement of cell culture on the chip.12h luminescence24h luminescenceGrowth ratioControl well95290 3.05PS chip w/o collagen 8482984 3.52PS chip w/collagen91027172.99316J.Chen et al./Sensors and Actuators B 248(2017)311–317Fig.9.Fluorescence images of cells on the control well (a),on non-coated PS chip (b)and on collagen coated chip (c).No dead cells (stained red)were observed on any of the three surfaces.Density difference between the collagen-coated (c)and the non-coated (b)chips results mainly from the initial seeding condition.Scale bar:100␮m.maintaining a normal morphology,proliferate and reach similar luciferase expression level upon drug stimulation as in commercial well plate without the need for collagen coating.4.ConclusionsPS has become an increasingly attractive alternative in microﬂu-idics due to its high mechanical strength and biocompatibility.The Si-SIIL method that we have developed makes it possible for con-veniently prototyping PS based microﬂuidics with micron-sized channels and high aspect ratios.Our results show that the molded PS surface exhibited almost the same surface properties as the orig-inal PS.Cell culture tests were also performed,suggesting that the Si-SIIL does not have any adverse effect on cell growth.The results show that PS,with the aid of Si-SIIL,can be an alternative material to PDMS in building microﬂuidic chips.However,the Si-SIIL technology at the current stage comes with some drawbacks.First,we note that the PS/mold release time is long.Even with a vacuum chamber,it takes about 1.5h to separate the PS chip from the mold,which is a bottleneck in the rapid pro-totyping.Second,the extinction coefﬁcient is changed to 2mm −1from 0.08mm −1after acetone immersion due to gel layer forma-tion,which leads to the transmittance reduction of the PS chip.Although high transmittance may not be needed for many applica-tions,improved optical transmission quality will certainly broaden the utility of the Si-SIIL.Third,compared to SIIL,three additional processing steps are added,spreading acetone on the PS surface,adding a PDMS cushion,and immersing another PS slab.Finally,the number of re-uses is relatively low for the Si mold with extremely high aspect ratios and long channels.AcknowledgementsThis work was supported by the National Natural Science Foundation of China (61501317and 61471254),Scientiﬁc and Technological Innovation Programs of Higher Education Insti-tutions in Shanxi (2016141),and the Project of International Cooperation of Shanxi Province (2015081025).We thank Xiaochun Li in Taiyuan University of Technology for the help in AFM and water contact angle measurement,Xiang Chen and Yanjie Su in Shanghai Jiao Tong University for the help in SEM and XPS measurement.References[1]E.K.Sackmann,A.L.Fulton,D.J.Beebe,The present and future role ofmicroﬂuidics in biomedical research,Nature 507(2014)181–189.[2]J.Chen,D.Chen,Y.Xie,T.Yuan,X.Chen,Progress of microﬂuidics for biologyand medicine,Nano-Micro Lett.5(2013)66–80.[3]X.Fan,S.-H.Yun,The potential of optoﬂuidic biolasers,Nat.Methods 11(2014)141–147.[4]T.Tian,J.Li,Y.Song,L.Zhou,Z.Zhu,C.J.Yang,Distance-based microﬂuidicquantitative detection methods for point-of-care testing,Lab Chip 16(2016)1139–1151.[5]R.-J.Yang,H.-H.Hou,Y.-N.Wang,L.-M.Fu,Micro-magnetoﬂuidics inmicroﬂuidic systems:a review,Sens.Actuators B 224(2016)1–15.[6]K.Ren,J.Zhou,H.Wu,Materials for microﬂuidic chip fabrication,AccountsChem.Res.46(2013)2396–2406.[7]H.Van Lintel,v.d.F.Pol,S.Bouwstra,A piezoelectric micropump based onmicromachining of silicon,Sens.Actuators B 15(1988)153–167.[8]D.J.Harrison,A.Manz,Z.Fan,H.Luedi,H.M.Widmer,Capillaryelectrophoresis and sample injection systems integrated on a planar glass chip,Anal.Chem.64(1992)1926–1932.[9]A.Alrifaiy,O.A.Lindahl,K.Ramser,Polymer-based microﬂuidic devices forpharmacy,biology and tissue engineering,Polymers 4(2012)1349–1398.[10]Z.Wang,D.Voicu,L.Tang,W.Li,E.Kumacheva,Microﬂuidic studies ofpolymer adsorption in ﬂow,Lab Chip 15(2015)2110–2116.[11]P.-C.Chen,L.H.Duong,Novel solvent bonding method for thermoplasticmicroﬂuidic chips,Sens.Actuators B 237(2016)556–562.[12]D.Konstantinou,A.Shirazi,A.Sadri,E.W.Young,Combined hot embossingand milling for medium volume production of thermoplastic microﬂuidic devices,Sens.Actuators B 234(2016)209–221.[13]P.N.Nge,C.I.Rogers,A.T.Woolley,Advances in microﬂuidic materials,functions,integration,and applications,Chem.Rev.113(2013)2550–2583.[14]D.C.Duffy,J.C.McDonald,O.J.Schueller,G.M.Whitesides,Rapid prototypingof microﬂuidic systems in poly (dimethylsiloxane),Anal.Chem.70(1998)4974–4984.[15]S.Hill,W.Qian,W.Chen,J.Fu,Surface micromachining ofpolydimethylsiloxane for microﬂuidics applications,Biomicroﬂuidics 10(2016)054114.[16]J.Park,K.H.Jo,H.Y.Park,J.H.Hahn,Spatially controlled silica coating inpoly(dimethylsiloxane)microchannels with the sol-gel process,Sens.Actuators B 232(2016)428–433.[17]E.Berthier,E.W.Young,D.Beebe,Engineers are from PDMS-land,Biologistsare from Polystyrenia,Lab Chip 12(2012)1224–1237.[18]C.T.Culbertson,T.G.Mickleburgh,S.A.Stewart-James,K.A.Sellens,M.Pressnall,Micro total analysis systems:fundamental advances and biological applications,Anal.Chem.86(2014)95–118.[19]P.M.van Midwoud,A.Janse,M.T.Merema,G.M.Groothuis,E.Verpoorte,Comparison of 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1 Ultra Low-Voltage Current Mirrors and Pseudo Di#erential Pairs

1 Ultra Low-Voltage Current Mirrors and PseudoDiﬀerential PairsYngvar Berg,Tor Sverre LandeAbstract—In this paper we present both novel current-mirrors and a novel pseudo diﬀerential pairs usingﬂoating-gate transistors available in standard double-poly CMOS. The circuits are modeled and simulated down to50mV sup-ply voltage.Wide dynamic range combined with high lin-earity is achieved with Early eﬀect compensation using min-imum transistors.I.IntroductionWhy would anybody start to reinvent such a funda-mental circuit as a current-mirror?The well known sim-ple current-mirror with familiar modiﬁcations like Wilson-mirror or cascading,reduces some of the systematic errors introduced by the Early eﬀect.These are all designed for reasonable supply voltages allowing suﬃcient headroom. Facing decreasing supply voltages in digital circuits,the surviving analog designer must follow andﬁnd a way to cope with the reduced headroom.The signal-to-noise ratio is decreasing(SNR∼V2dd)with decreasing supply voltage, but traditional circuits are doing pretty well even down to 1V power supply.Extrapolating into the future with ul-tra low supply voltages(ULV)<1V,the headroom stolen by keeping circuits like current-mirrors in saturation is a signiﬁcant portion of the available dynamic range.By using the FGUVMOS transistor[2],[3],[4]available in any double-poly CMOS process,ULV circuits may be implemented with rail-to-rail operation and Early eﬀect cancelling.The FGUVMOS transistor may be utilized in both digital and analog design,but familiar circuits like current-mirrors must be redesigned to meet the require-ments of ULV circuits.Before we proceed with the FGUVMOS curent-mirror, some words about the constraints and conditions estab-lished in FGUVMOS circuits.As indicated inﬁgure1, Fig.1.The generic FGUVMOS circuit element.The small circlesindicate UV-windows.there is always one PMOS stacked on top of one NMOS transistor.The height is always two with a common drain-Dept.of Informatics,University of Oslo,Gaustadalleen23,P.O.Box 1080,Blindern,N-0316Oslo,Norway.Fax:+4722852401.Email: yngvarb@iﬁ.uio.no node,but of course additional MOS transistors may be added in parallel(both Ps and Ns).However,eachﬂoat-ing gate may have several inputs connected throughﬂoat-ing capacitors,compensating for the limited stacking.All FGUVMOS circuits must be tuned or programmed using short-wave UV-light(UV-C)[2],[7],[5].The supply rails are used to provide the speciﬁcﬂoating-gate oﬀsets(thresh-old shift)in an adaptive reverse bias mode.Note that all transistors on a chip,or even a wafer,may be programmed simultaneously without using any additional programming circuitry except power-rails.Two important conditions are established during the adaptation:1.The threshold voltage of all PMOS transistors is pro-grammed to a small negative voltage relative to the V dd supply rail,while the threshold voltage of all NMOS tran-sistors is tuned to a small positive voltage relative to the V ss supply rail(substrate).By reverse biasing the supply-rails, the source and drain on all transistors are interchanged. The nodes between the PMOS and NMOS are strongly driven by a source-follower conﬁguration to a equilibrium voltage,V be(≡V DD/2),maintained also under normal bi-asing conditions.The currentﬂowing through the stacked transistors is matched and will result in a balanced equi-librium current,I be,under normal biasing.2.A useful consequence of the current matching is equal-ized transconductances[2]due to shifting of the threshold voltage.We have that is g mN/g mP=1in weak inversion and g mN/g mP=2Fig.2.(a)The commonﬂoating-gate current mirror.(b)The splitﬂoating-gate current mirror.Fig.3.Floating-gate current mirror characteristics.behavior as modulation of the equilibrium condition.Forsimplicity,we will model the weak inversion behavior know-ing that a similar analysis may be done for strong inver-sion as well.The input modulation of the drain currentas a function of the i th input terminal may be expressedasΓk i i=exp{K i(V i−V be)}.The accumulated drain cur-rent modulation of m inputs is expressed as the productΓ= m i=1(Γi)k i.The eﬀective drain current of a FGU-VMOS transistor may then be written asI d=I beΓ=I bemi=1(Γi)k i.In the following,this kind of equilibrium point analysis will be used to analyze circuit behavior.III.The split floating gate current mirror An already publishedﬂoating-gate current mirror[8]is shown inﬁgure2(a).As expected channel-shortening severely degrades this circuit,especially for small transistor dimensions.Theoretically,the worst case current mismatch due to the Early eﬀect is proportional to V DD/V e,where V e is the Early voltage.The output distortion(error)may be expressed as the ratio I out/I in.A simulation of the circuit behavior for small currents is shown inﬁgure3.A linear mismatch(error)as a function|V in−V out|around the bal-anced equilibrium voltage imply that the transistors are in saturation.The Early voltage V e for the transistors in this example are4V.The error is varying between±12%.Fig.5.The average error of the splitﬂoating-gate current mirror. The splitﬂoating-gate mirror circuit is shown inﬁgure2 (b).Theﬂoating gates of the current mirror are controlled through capacitor C i and C o.As for all FGUVMOS cir-cuits we have that when the input V in is equal to V be the output V out is equal to V be,and theﬂoating gate voltages are equal.If we choose C o/C i>1,the error due toﬁnite drain conductance can be reduced.The capacitive inputs to the splitﬂoating gate current mirror must be matched with Early voltage and the actual transistor ing a simple model for the Early eﬀect, g d=V−1ewe have:k o(V eN o−V be)V eN i]nU T.(1)where V eNi and V eNo are the Early voltages for the input-and output transistors,respectively.The current mismatch due to Early eﬀect is compensated for by using slightly dif-ferent slope factors for the input and output transistors by making the capacitors diﬀerent.To illustrate the power of this technique,a split gate current mirror with short transistors(V e≈0.8V)was simulated using HSPICE.Un-fortunately,the non-linear gate capacitance will appear as a current-dependent error.For aﬁxed C o/C i ratio op-timized for minimal error at a speciﬁc current level,the error will increase for diﬀerent current levels as shown in3outI in(a) Current mirror(b) Current inverterFig.6.FGUVMOS circuits;(a)current mirror and(b)current inverter.ﬁgure4.The error for current levels larger than100nA is due to the output transistor entering the linear region.In spite of this problem the errors are acceptable.A common gate design with Early voltage equal to0.8V would have an±35%error!The matching improvement factor is140 for a supply voltage at0.5V[3].If the capacitive division factor is optimized for a speciﬁc current level(oﬀset),the average error is close to0.1%.The currents are perfectly matched when V in=V out=V be.The average error as a funcion of I max forﬁxed C o/C i optimized for current level I max=15nA is shown inﬁgure5.IV.Current invertersOne of the essential properties of FGUVMOS circuits is the large degree of symmetry.We may explore this symme-try and make a current mirror with an inverted output as shown in inﬁgure6(b).In this way we get a true analog current inverter.The input current of the single input FGUVMOS circuits inﬁgure6(a)may be expressed as I in=I beΓNiThe output current of the current mirror may be ex-pressed asI out=I beΓNo=I be(ΓNi)k N oI in.The accuracy of the current mirror and current inverter may be increased by optimizing the ratio C No/C Ni and C P o/C Ni respectively according to Eq.1to compensate for the Early eﬀect.The current mirror and current in-verter characteristics are shown inﬁgure7together with aFig.7.FGUVMOS circuit characteristics;current mirror and cur-rent inverter.Fig.8.The output voltage of a FGUVMOS circuit as a function of the input voltage.common-gate design.As expected the Early eﬀect compen-sation is eﬀective.The dynamic range of currents are close to three orders of magnitude for a supply voltage equal to 0.7V and a capacitive division factor(k No/k Ni)equal to 0.57.The split gate characteristics are close to“perfect”and the error is signiﬁcantly reduced compared to the com-mon gate design.In fact,also the voltage of the current-inverter is the inverse of the input-voltage.Consider the current mirror and current inverter inﬁgure6,the output voltage V out is a function of the input current or input voltage V in, V out=V dd−V in=4V in2V in1Fig.9.Simple ultra low-voltage FGUVMOS pseudo diﬀerential pair.V.Differential input stageThe merits of the well-known diﬀerential pair,both inMOS and bipolar circuits,are indisputable.Close to everyoperational ampliﬁer is,for good reasons,equipped witha diﬀerential pair as an input stage.The question is howto avoid the loss of headroom imposed by the tail-currentgenerator,usually a transistor operated in saturation.Re-cently Motorola[1]announced a1V rail-to-rail -ing their SMARTMOS process and back-gate biasing toachieve this goal.With the use of the FGUVMOS transis-tor,a pseudo-diﬀerential pair may be implemented usingstandard CMOS technology giving rail-to-rail operation.The circuit is shown to work below100mV,but practicalapplications will normally require a higher SNR.In the following a simple pseudo diﬀerential pair is in-troduced and later a more elaborate structure using splitgate current mirrors is presented.VI.The simple ULV pseudo differential pairThe ULV pseudo diﬀerential pair is shown inﬁgure9.The intuitive operation may be hard to understand,butusing the notation introduced above,the behavior may bedescribed quite simply.A.Current levelAs usual the input to a diﬀerential stage would be a dif-ferential input voltage given by V in1−V in2.The V b terminalis the equivalent of a tail-current source.The output cur-rent level is determined by the equilibrium point currentand the actual current scaling(compression)performed bythe capacitive division in the pseudo diﬀerential pair.Theinternal currents I1,I2and I3may be expressed asI1=I be(ΓVin1)k1(ΓVb)k3I2=I be(ΓVin2)k1(ΓVb)k3I3=I be(ΓVx)−k5=I1+I2.The diﬀerential output currents I4and I5may be ex-pressed asI4=I be(ΓVin1)k2(ΓVx)k4the simple ultra low-voltage pseudo diﬀerential pair.=I be(ΓVin1)k2(I bek5=I be(ΓVb)−k3k4k4k5I5=I be(ΓVb)−k3k4k4k5.(3)We have that0≤k1+k3≤1,0≤k2+k4≤1and0≤k5≤1.If k2=k1and k5/k4=1the output currentsareI4=I be(ΓVb)−k3((ΓVin1)k1(ΓVin1)k1+(ΓVin2)k1),where I bt=I4+I5=I be(ΓVb)−k3is the bias current.Fi-nallyﬁnding the diﬀerence I4−I5yieldsI4−I5=I bt tanh(K1(V in1−V in2))Both formally and by simulation,the diﬀerential currentsof the pseudo diﬀerential pair exhibit a tanh behavior asshown inﬁgure10.The essential design parameters are the capacitive di-vision factors or k i s.It is possible to tune the pseudodiﬀerential pair by adjusting these ratios.In order tomodel a standard symmetrical diﬀerential pair we have thatk1≈k2<<1due to the fact that k2+k4≤1,k4≈k5and k5have to be large(>1/2)to keep the transistors N1N2and P in saturation.The matching of poly1/poly2ca-pacitors are generally very good compared to transistors.However,for very small capacitors,the matching will de-grade signiﬁcantly.By using the bias input capacitanceshown inﬁgure9,we increase the total capacitance of theﬂoating gate of N1and N2and the input capacitor C1canbe increased without increasing the capacitive division fac-tor k1.Equation3is based on the assumption that all5of the input capacitive division factor k i.The linear range is inversely proporti onal to the capacitive division factor. transistors are in saturation.We have to make sure that V x inﬁgure9is not pulled all the way to the supply rails. This can be achieved by using a large capacitor C5com-pared to the bias and input capacitors C3and C1,that is,we have that k5>>k1+k3.A large k5implies that k4<k5and k2<k1.The disadvantage of this tuning is an asymmetrical tanh transfer function as indicated in ﬁgure9.B.Linear rangeThe input capacitive division factor k1determines the linear range and the transconductance of the pseudo dif-ferential pair.By utilizing the well-known technique of lin-earization by capacitive division,an increased linear range may be achieved.The theoretical normalized transconduc-tances for capacitive division factors from0.01to0.79are shown inﬁgure11.By using a large capacitive division in the input stage the linear range can be extended close to rail-to-rail operation.A large capacitive divsion factor is achieved by using small input capacitors compared to the totalﬂoating capacitance in the input stage.However, implementing very small capacitors may cause signiﬁcant matching problems.The input capacitive division factor may in practical circuits be chosen in a range from0.1to 0.6.The simulated normalized transconductences for input capacitive division factors of0.1,0.4and0.55are shown inﬁgure12.Although the results are a little noisy,the increased linear transconductance may clearly be seen. C.Changing supply voltageIn general the performance of this circuit is a function of diﬀerent settings.First of all the UV-programmed initial condition will be programmed to meet the desired spec-iﬁcations,i.e.for a given supply voltage,the V t s of all transistors will be set to meet the speed requirements(if possible).By lowering the threshold voltage,larger cur-rents are pulled,increasing speed and power consumption aswell.low-voltage pseudo diﬀerential pair for input capacitive diviosion factors0.1,0.4and0.55.45voltage pseudo diﬀerential pair for supply voltage from200mV to1.5V.Fig.14.Normalized transconductance G m/G m0V dd=1.5for supply voltages ranging from50mV to1.5V.6Fig.15.ULV pseudo diﬀerential pair with reduced input capacitance.For a programmed threshold voltage,the circuit is able tooperate over a large range of supply voltages.Inﬁgure13,the output currents(I4−I5)for several supply voltages areshown.Even at50mV,the linearity of the output current isacceptable.Also the normalized tranconductances behaveswell as shown inﬁgure14.VII.ULV pseudo diff-pair with reduced inputcapacitanceAs the observant reader may have noticed already,thebiasing capacitive input inﬁgure9is loading the inputﬂoating gate.The eﬀectiveness of V b must be traded forthe eﬀectiveness of the input signal.In order to keep thesignal swing as high as possible,the biasing capacitor maybe moved with a slightly redesigned circuit.The inputcurrent is copied using two current mirrors as shown inﬁgure15and the biasing capacitor is moved to the summingNMOS transistor.The math turns out to be quite similarI1=I be(ΓVin1)k1=I be(ΓV1)−k2I2=I be(ΓVin2)k1=I be(ΓV2)−k2I3=I be(ΓVx )k5(ΓVb)k3=I1+I2, assuming that k4=k2.I4=I be(ΓV1)−k6(ΓVx)−k7=I be(ΓVb)k3k7k2k7k5I5=I be(ΓVb)k3k7k2k7k5 Assuming that k6/k2=k7/k5we have thatI4=I be(ΓVb )k3k7(ΓVin1)k1+(ΓVin2)k1)k7 k5((ΓVin2)k1k5Again,if k7/k5=1and k3=1we get the familiar tanh transfer function.Once more it is convenient to keep the capacitive division factors and actively use them for tuning as indicated above.VIII.ConclusionsThe potential of using FGUVMOS transistors in ULV analog circuits is demonstrated through the design of split foating-gate current mirrors and pseudo diﬀerential pairs. Rail-to-rail operation may be achieved even for power sup-plies down to50mV.By scaling the input capacitances, the linear range may be increased.Furthermore,a sim-ple formal treatment of FGUVMOS circuits in weak inver-sion is presented,enabling simple deduction of the transfer function,and demonstrated on two versions of the pseudo diﬀerential pair.It is our intention to present measured results at the conference.References[1]Motorola Data Sheet One Volt SMARTMOS Rail-to-RailDual Operational Ampliﬁer,MC33502.,[2]Y.Berg and nde.Programmable Floating-Gate MosLogic for Low-Power Operation.,ISCAS,june.1997.[3]Y.Berg and nde.Low-Voltage Floating-Gate Cur-rent Mirrors.,ASIC97,october.1997.[4]Y.Berg and nde.Low-Voltage Sinh Ampliﬁer.,ICECS97,december.1997.[5]Y.Berg,Dag nde.Floating-Gate UVMOSInverter,Norchip97,november.1997.[6]Burr J.B.A200mV encoder-decoder circuit using Stan-ford Ultra Low Power CMOS.,ISSCC,feb.1994.[7]R.G.Benson and D.A.Kerns.UV-Activated ConductancesAllow For Multiple Scale Learning.,IEEE Transactions on Neural Networks,vol.4,no.3,may1993.[8] B.A.Minch,C.Diorio,P.Hasler and C.A.Mead.TranslinearCircuits Using Subthreshold Floating-Gate MOS Tran-sistors.,Analog Integrated Circuits and Signal Processing,9, pp.167-179,Kluwer Academic Publishers,1996.。

开关电源输入输出电容的选择

1.2
Selecting Input Ceramic Capacitors
Load current, duty cycle, and switching frequency are several factors which determine the magnitude of the input ripple voltage. The input ripple voltage amplitude is directly proportional to the output load current. The maximum input ripple amplitude occurs at maximum output load. Also, the amplitude of the voltage ripple varies with the duty cycle of the converter. For a single phase buck regulator, the duty cycle is approximately the ratio of output to input dc voltage. A single phase buck regulator reaches its maximum ripple at 50% duty cycle. Figure 1 shows the ac rms, dc, and total rms input current vs duty cycle for a single phase buck regulator. The solid curve shows the ac rms ripple amplitude. It reaches a maximum at 50% duty cycle. The chart shows how this magnitude falls off on either side of 50%. The straight solid line shows the average value or dc component as a function of duty cycle. The curved dashed line shows the total rms current, both dc and ac, of the rectangular pulse as duty cycle varies.

FSEZ 1317 Low Power PLM [Compatibility Mode]

PSR introductionLow Power PLM Power Conversion02nd Generation PSR FamilyFAN102, FSEZ1216, FSEZ1216B/17B3rd Generation PSR Family yFAN103, , FSEZ1306S, , FSEZ1307/171Less Component Count for ChargerFSEZ1016 (multi(multi-sampling) CV ++-10%, CC + +-10% FSEZ1216 (linear predict) CV ++-5% CC ++-5%1’st PSR tech Resistor x 8 Cap. X 4Tighten CV/CC Resistor x 9 Cap. X 5FSEZ1416 (linear predict + CCM) CV ++-5% CC + +-5%FSEZ1307/17 (linear predict) CV ++-5% CC ++-5%High Power PSR Higher CEC Low ripple/St-by Resistor x 3 Cap. x2 2Less component Resistor x 3 Cap. X2Features of FAN102,FSEZ12XX• Primary side control for CV and CC (No optical ( p coupler p for feedback, No op-Amp p p for CV/CC control, No voltage g reference) ) • Fixed PWM Frequency at 42kHz with Frequency Hopping to Solve EMI Problem • Green-mode Function: PWM Frequency Linearly Decreasing • Cable Compensation p in CV mode • Cycle-by-cycle Current Limiting • VDD Over-voltage Protection with Auto recovery • VDD Under-voltage Under voltage Lockout (UVLO) • Gate Output Maximum Voltage Clamped at 18V • Fixed Over-temperature Protection with Auto recovery • SOP SOP-8 8 and DIP DIP-8 8 Package Available • Minimum external component3Features of FAN103,FSEZ13X7*• Primary side control for CV and CC (No optical ( p coupler p for feedback, No op-Amp p p for CV/CC control, No voltage g reference) ) • High voltage start up • Ultra low standby power loss • Fixed PWM Frequency q y at 50kHz with Frequency q y Hopping pp g to Solve EMI Problem • Green-mode Function: PWM Frequency Linearly Decreasing • Cable Compensation in CV mode • Cycle Cycle-by-cycle by cycle Current Limiting • VDD Over-voltage Protection with Auto recovery • VDD Under-voltage Lockout (UVLO) • Gate Output Maximum Voltage Clamped at 18V • Fixed Over-temperature Protection with Auto recovery • SOP-7 and DIP-7 Package Available • Minimum external component* : Code S soon later- FAN103: Code S May’09. May’09 - FSEZ1307 and FSEZ1317: Code S June’09).4Product Portfolio103 families FAN103PSR PWMDescription HV Built in ComV HV, ComV, ComI Built in Cs pin using SenseFet FAN103 + MosFet M F t 700V 0.5A MosFet 700V 1A MosFetcontent • 30mW standby power loss • CV/CC : ± 5%,100mV ripple • meet energy star level 5 • HV start up • Built in ComV, ComI, ComR • 50KHz • freq. reduction @ CC rangeVbusFSEZ1307S FSEZ1307EZ PSRFSEZ1317Vbus3 VDD8 HVVS 5GATE 22 VDD 7VS 5HVDRAIN87 NC 6 GNDCS16 NC3 GNDCS1COMR 4COMR 4FAN103FSEZ13X75Function ComparisonsProduct Portfolio Start up Power saving Frequency ComV, ComI C R ComR Frequency Decreasing @CC Creepage Package External comp. counts FAN103/FSEZ13x7 HV start up (JFET 500V) <30mW Meet ÕÕÕ 50KHz Built in Fi d (Built Fixed (B ilt in) i ) Yes Yes DIP7 and SOP7 Reduce 7 counts FAN102/FSEZ1216 Start up resistor <150mW 42KHz External comp. Adj t bl Adjustable No No (FSEZ1216) DIP8 -6Block Diagram of FAN1037VDD Over-voltage ProtectionWhen the voltage VDD exceeds 28V due to abnormal conditions, the PWM output will be switched off. Vc mv Gate Vcomv G t VDD8Built in Com V & Com IW3db = 1 RCError Amp. Error Amp. V f Vref0.68uF 200k p 10pF 1.36GVrefKey point• save 2 resistors & 2 capacitors • save ic pin => achieve creepage • using Novel Passive SC Filter • Î Low-cost and area-efficient SC filter for low-BW • Î high accuracy BW through freq. triming & cap. matching9Built-in COMR ResistorBuilt-in COMR Resistor ÎCost Reduction.10k~150kohmCOMR105100kohm105Key point•save 1 resistors•P diffusion resistor 10~150kohm•different compensation rate with different resistor valueComparison for 3W ChargerR6R/12K/0805C8C/560uF/10VD3N4D2N4C4C5R/1.2K/0805SGNDC7C/47P/1206D/1D/1C/4.7uF/400V C/4.7uF/400VR17R/24.9K/1206R10R/110K/0805C6C/10uF/50VD6D/1N4007N546TX/EE16NN9VDDVS52U1R16AR/2R4/85COMRCSC9C/472P/0805DRAINSource1GND3NA6HV7VSVDDCOMR4DRAIN8FSEZ1316R2R/1K/85FSEZ1216 (1A/600V) DIP8 : 36 points FSEZ1307*(0.5A/700V) SOP7 23points@•Small mechanical case for low cost shipping.•No need Snubber under 3W with 700V MOS.•Lower inserting cost:S it bl05A MOSFET d4WStand by : 26.6mW@264VacCV :±2.7%CC: ±2.1%Ripple;150mVp-p under•Suitable 0.5A MOSFET under 4W.•High Efficiency & Very Low St-by power.Ripple; 150mVp p underCEC ; 70.64% / 68.24%@AWG26(65.5%)EMI ; 6dBThank you !!! Thank you!!!。

复旦半导体工艺教材Chapter-2

3. Selective Doping Technology
Si transistor — product of doping engineering
*Device type and performance--determined by impurity doping profile ( element, concentration, distribution)
➢ Lowest power consumption than all others ➢ Noise resistance and higher reliability ➢ Main stream of VLSI/ ULSI process since late 80’s
BiCMOS
➢ Combination of high speed and low power ➢ High process complexity
Low energy ion implant and shallow junction formation — of vital importance for nano-meter CMOS fabrication
High energy ion implant for n/p wells
Rapid thermal process (RTP) and dopant atom diffusion control
*Double diffused mesa transistor process
*Transistor by planar process
➢Transistor and other circuit elements formed by planar technology
✓On-chip resistor: by diffusion; poly-Si by deposition

44 Defect-Oriented Testing in the Deep-Submicron Era High Defect Coverage with Low-Power Te

TESTING RANKS among the most expensive and difﬁcult aspects of the circuit design cycle, driving the need for innovative solutions. To this end, researchers have proposed built-in self-test (BIST) as a powerful DFT technique for addressing highly complex VLSI testing problems. BIST designs include on-chip circuitry to provide test patterns and analyze output responses. Performing tests on the chip greatly reduces the need for complex external equipment. The most commonly used fault model for BIST of digital systems is the classical single stuck-at fault model. However, in the new CMOS nanometer technologies, defects do not always behave as stuck-at faults do.1 Therefore, test generation based on the stuck-at model alone is no longer sufﬁcient for obtaining high defect coverage.2 A straightforward solution covering many misbehaviors that can occur in

用vasp计算硅的能带结构

用vasp计算硅的能带结构在最此次仿真之前，因为从未用过vasp软件，所以必须得学习此软件及一些能带的知识。

vasp是使用赝势和平面波基组，进行从头量子力学分子动力学计算的软件包。

用vasp计算硅的能带结构首先要了解晶体硅的结构，它是两个嵌套在一起的FCC布拉菲晶格，相对的位置为(a/4,a/4,a/4), 其中a=5.4A是大的正方晶格的晶格常数。

在计算中，我们采用FCC的原胞，每个原胞里有两个硅原子。

VASP计算需要以下的四个文件：INCAR（控制参数）, KPOINTS（倒空间撒点）, POSCAR（原子坐标）, POTCAR（赝势文件）为了计算能带结构，我们首先要进行一次自洽计算，得到体系正确的基态电子密度。

然后固定此电荷分布，对于选定的特殊的K点进一步进行非自洽的能带计算。

有了需要的K点的能量本征值，也就得到了我们所需要的能带。

步骤一.—自洽计算产生正确的基态电子密度：以下是用到的各个文件样本:INCAR 文件：SYSTEM = SiStartparameter for this run:NWRITE = 2; LPETIM=F write-flag & timerPREC = medium medium, high lowISTART = 0 job : 0-new 1-cont 2-samecutICHARG = 2 charge: 1-file 2-atom 10-constISPIN = 1 spin polarized calculation?Electronic Relaxation 1NELM = 90; NELMIN= 8; NELMDL= 10 # of ELM stepsEDIFF = 0.1E-03 stopping-criterion for ELMLREAL = .FALSE. real-space projectionIonic relaxationEDIFFG = 0.1E-02 stopping-criterion for IOMNSW = 0 number of steps for IOMIBRION = 2 ionic relax: 0-MD 1-quasi-New 2-CGISIF = 2 stress and relaxationPOTIM = 0.10 time-step for ionic-motionTEIN = 0.0 initial temperatureTEBEG = 0.0; TEEND = 0.0 temperature during runDOS related values:ISMEAR = 0 ; SIGMA = 0.10 broadening in eV -4-tet -1-fermi 0-gausElectronic relaxation 2 (details)Write flagsLWAVE = T write WAVECARLCHARG = T write CHGCARVASP给INCAR文件中的很多参数都设置了默认值，所以如果你对参数不熟悉，可以直接用默认的参数值。

Low power voice detection

专利名称：Low power voice detection发明人：Arijit Raychowdhury,Willem M.Beltman,James W. Tschanz,CarlosTokunaga,Michael E. Deisher,Thomas E.Walsh申请号：US13997070申请日：20111206公开号：US09633654B2公开日：20170425专利内容由知识产权出版社提供专利附图：摘要：Methods of enabling voice processing with minimal power consumption includesrecording time-domain audio signal at a first clock frequency and a first voltage, and performing Fast Fourier Transform (FFT) operations on the time-domain audio signal at a second clock frequency to generate frequency-domain audio signal. The frequency domain audio signal may be enhanced to obtain better signal to noise ratio, through one or multiple filtering and enhancing techniques. The enhanced audio signal may be used to generate the total signal energy and estimate the background noise energy. Decision logic may determine from the signal energy and the background noise, the presence or absence of the human voice. The first clock frequency may be different from the second clock frequency.申请人：Arijit Raychowdhury,Willem M. Beltman,James W. Tschanz,Carlos Tokunaga,Michael E. Deisher,Thomas E. Walsh地址：Duluth GA US,West Linn OR US,Portland OR US,Hillsboro OR US,Hillsboro OR US,Banks OR US国籍：US,US,US,US,US,US代理机构：Jordan IP Law, LLC更多信息请下载全文后查看。

一种动态自偏置的低功耗无片外电容LDO

现代电子技术Modern Electronics Technique2023年6月1日第46卷第11期Jun.2023Vol.46No.110引言低压差线性稳压器（LDO ）需要一个负载电容对输出电压的过冲进行抑制，并提高稳定性。

由于LDO 具有低噪声、低波纹、无电磁干扰（EMI ）的特性，在SoC 芯片或模数（A/D ）转换芯片中都需要LDO 作为内部电源，为芯片内部模块中的噪声敏感电路提供稳定、低噪的工作电压。

为实现高度集成，LDO 多为无片外电容[1⁃2]结构。

随着工艺的尺寸越来越小，模拟电路设计也因工艺参数和各种效应的影响变复杂。

本文基于0.13μm 工艺，设计一种采用动态自偏置[3⁃4]技术的低功耗、无片外电容LDO 。

该电路允许LDO 根据负载电流变化，在二级和三级结构之间进行转换，降低静态电流；输出端添加过冲抑制电路，优化瞬态响应；电路无需片外电容，减小外部电路节约成本。

结果表明LDO 具有低功耗、高稳定性和良好的瞬态响应。

1电路设计1.1拓扑分析传统LDO 依赖μF 级的大片外电容来维持稳定运一种动态自偏置的低功耗无片外电容LDO王梓淇，黄少卿，肖培磊，雷晓（中国电子科技集团第五十八研究所，江苏无锡214000）摘要：基于0.13μm 工艺设计的低功耗无片外电容LDO ，文中采用动态自偏置技术使电路根据负载变化，提供不同的偏置电流，实现两级和三级结构下相互转化。

电路采用Cascode Miller 补偿，实现高稳定性。

输出端加入过冲抑制电路，优化瞬态响应。

仿真得到压差电压为57mV ；在-55~125℃范围内，温漂系数为27ppm/℃；在电源电压1.2~3.3V 和负载100nA~50mA 的变化范围内，线性调整率为0.452mV/V ，负载调整率为0.074mV/mA 。

满载50mA 和电源电压1.2V 时，电源抑制比-53dB@100kHz ，环路相位裕度大于60°。

具有低输出纹波的双电感复用无桥buck-boost_PFC_变换器

第27卷㊀第11期2023年11月㊀电㊀机㊀与㊀控㊀制㊀学㊀报Electri c ㊀Machines ㊀and ㊀Control㊀Vol.27No.11Nov.2023㊀㊀㊀㊀㊀㊀具有低输出纹波的双电感复用无桥buck-boostPFC 变换器陈正格,㊀许建平,㊀陈旭,㊀漆谨(西南交通大学电气工程学院,四川成都611756)摘㊀要:单相buck-boost 功率因数校正(PFC )变换器凭借高功率因数(PF )与升降压的输出特性广泛应用于小功率非隔离LED 场合(ɤ25W ),但是随着双碳政策的推行,需要进一步提升变换器性能㊂因此提出一种双电感复用的单级无桥buck-boost 变换器,其双电感分别交替工作于电感电流不连续导通模式(DCM )与连续导通模态(CCM )㊂工作于CCM 的电感可以与电容构成LC 滤波电路减小输出纹波,工作于DCM 的电感可以使变换器仍然采用单电流闭环控制实现接近于1的PF 与输出调节㊂此外,所提出的变换器仍然可以采用含谐波注入的控制,进一步降低输出电流纹波,实现PF 与输出电流纹波的权衡㊂最后,两台实验样机验证了拓扑的可行性和理论分析的正确性㊂关键词:buck-boost ;功率因数校正;无桥;双电感复用;电感工作模态;低输出电流纹波DOI :10.15938/j.emc.2023.11.004中图分类号:TM46文献标志码:A文章编号:1007-449X(2023)11-0030-10㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀收稿日期:2022-10-28基金项目:中国博士后科学基金(2021M702709);中央高校基本科研业务费专项资金(2682022CX017)作者简介:陈正格(1991 ),男,博士,研究方向为变换器拓扑及其控制㊁可靠性分析等;许建平(1963 ),男,博士,教授,博士生导师,研究方向为高效率电能变换㊁控制及其系统;陈㊀旭(1999 ),男,硕士研究生,研究方向为电力电子与电力传动;漆㊀谨(1999 ),男,硕士研究生,研究方向为电力电子与电力传动㊂通信作者:陈正格Low output ripple single-stage bridgeless buck-boost PFCconverter with dual-inductor multiplexingCHEN Zhengge,㊀XU Jianping,㊀CHEN Xu,㊀QI Jin(School of Electrical Engineering,Southwest Jiaotong University,Chengdu 611756,China)Abstract :Single-stage buck-boost power factor correction (PFC)converter featuring high power factor (PF)and step-up /down capabilities,is widely used for low power non-isolated LED applications (ɤ25W),however,the launch of the carbon neutralization policy requires the converter to further im-prove performance.A single-stage bridgeless buck-boost converter with dual-inductor multiplexing was proposed with two inductors alternatively operating in discontinuous conduction mode (DCM)and contin-uous conduction mode (CCM).The inductor operating in CCM helps filter switching frequency ripple,and in DCM allows the converter to utilize simple single closed-loop control to achieve output current reg-ulation and near unity PF.Harmonic injection technique is applicable to the proposed converter to further reduce output current ripple.A tradeoff between PF and output current ripple was achieved.Experimen-tal tests verify the topology effectiveness and theoretical correctness.Keywords :buck-boost;power factor correction;bridgeless;inductor multiplexing;inductor conductionmode;low output current ripple0㊀引㊀言在全球范围内,照明系统消耗了近20%的电力,预计未来20年照明能源需求将进一步增加[1]㊂近十年来,传统光源正被寿命更长㊁发光效率更高的发光二极管(light emitting diode,LED)取代[1-2]㊂目前,LED照明被广泛应用于城市亮化工程㊁无人机表演㊁路灯照明㊁大型场馆照明㊁电动汽车㊁农业等多种场合[3]㊂随着LED的大范围使用,Energy star 等产品性能标识对LED的要求也变得苛刻㊂如2009年生效的标准中,仅要求功率ȡ25W的民用LED照明功率因数(power factor,PF)ȡ0.7,商用LED照明PFȡ0.9;而2011年生效的标准已对功率ȡ5W的LED照明均做出上述要求[4]㊂因此,研究高性能的LED驱动具有超前意义㊂目前,LED驱动主要性能指标包括成本㊁使用寿命㊁效率㊁光谱调节能力㊁光照范围等[4-5]㊂由于应用场合的差异,LED驱动电路的性能侧重点有所不同㊂比如,在街边路灯照明中,由于数量众多的路灯整体能耗大㊁维护成本高,LED装置的使用寿命㊁光照范围与发光效能较为重要[6-7];而在农业应用中,由于植物在不同生长阶段对不同特定波长光源有不同的反应,因此LED装置应具备精细可控的光谱调节能力㊁低启动电流与高效率等特性[8]㊂因此,为应对特定场景的不同要求,相关学者提出不同的功率因数校正变换(power factor correc-tion,PFC)电路驱动LED㊂为延长AC-DC驱动电路的使用寿命,学者们提出多种输出电流纹波抑制㊁消除电路,避免在输出侧使用寿命有限的电解电容[9-12]㊂在液晶显示器中,为实现LED高演色性(color rendering index,CRI),避免传统白光LED色移现象[13],学者们采用多路并联RGB-LED[14]㊁可快速调节母线电压的辅助电路[15]㊁母线电容可控投切[16]等方式;其次,为实现多路输出LED串的均流,简单㊁高效㊁低成本的多种无源均流电路被学者提出与分析[17-19]㊂另外,为降低电价增长带来的变换器运行成本,同时响应低碳的政策号召,各类无桥AC-DC变换器被提出[20-29]㊂这类拓扑不再使用二极管整流桥,而是通过减少电流通路中半导体器件数量实现更低的导通损耗[20]㊂近十年来,基于boost㊁Cuk㊁buck-boost 等广泛应用于AC-DC LED驱动的经典电路拓扑,学者们提出更高效的无桥AC-DC LED驱动变换器[24-27]㊂文献[24]提出基于双并联Cuk变换单元所得的无桥Cuk电路并分析其工作特性㊂文献[25]提出谐振无桥boost LED驱动电路,通过谐振电容均流网络实现多路均流㊂文献[26]基于传统boost PFC与半桥LLC谐振电路的两级架构,提出一种通过器件融合的准单级无桥电路,其具有更少的开关器件㊂文献[27]基于双buck-boost变换单元给出一种低开关管应力的单级无桥buck-boost PFC拓扑,但该类无桥拓扑的双变换单元仅交替工作于半个工频周期,器件利用率不高㊂针对文献[27]的缺点,本文提出一种通过双电感复用实现低输出电流纹波的无桥buck-boost PFC 变换器㊂所提出的变换器具有以下特性:1)其中一个电感与输入侧连接,工作于电流断续导电模式(discontinuous conduction mode,DCM),变换器可采用单闭环控制实现高PF与输出调节;2)另一电感与输出侧连接,工作于电流连续导电模式(continu-ous conduction mode,CCM),滤除更多高次输出谐波,实现低输出纹波;3)类似传统buck-boost PFC变换器,该改进型拓扑仍然可以使用含谐波注入的控制进一步降低输出电流纹波㊂本文分析变换器工作原理,推导PF值㊁输出纹波i o,rip表达式,给出谐波注入的控制方法㊂最后,通过实验验证拓扑的可行性与理论分析的正确性㊂1㊀无桥buck-boost PFC变换器1.1㊀提出的拓扑介绍由于buck-boost PFC变换器的功率通常仅为数十瓦,一般采用简单的单电流闭环控制㊂图1给出了传统buck-boost PFC变换器主电路图,包括二极管整流桥㊁开关管S㊁二极管D㊁输出电容C o㊁电感L㊁电磁干扰(electromagnetic interference,EMI)滤波电容C f㊁电感L f㊂图1㊀传统buck-boost PFC变换器及其控制Fig.1㊀Conventional buck-boost PFC converter and its control schematic13第11期陈正格等:具有低输出纹波的双电感复用无桥buck-boost PFC变换器图2(a)㊁图2(b)分别给出了单电流闭环控制和含谐波注入的单电流闭环控制无桥buck-boostPFC 变换器原理图㊂在无桥buck-boost PFC 拓扑中,包括整流二极管D R1和D R2㊁开关管S 1和S 2㊁输出二极管D 1和D 2㊁电感器L 1和L 2㊁输出电解电容C 1和C 2以及双向中间电容C 3㊂其中,S 1㊁S 2的驱动信号V gs1㊁V gs2可以完全相同,实现控制简化㊂在无桥buck-boost PFC 拓扑[22]中,由S 1㊁D 1㊁L 1和S 2㊁D 2㊁L 2组成的双buck-boost 变换单元分别仅工作在正㊁负半个工频周期,变换器整体器件利用率不高㊂本文仅增加中间电容C 3(如图2所示),可以使得双电感在半个工频周期内,分别工作于DCM 与CCM,且未增加控制复杂性㊂图2㊀提出的无桥buck-boost PFC 变换器及两种控制方法Fig.2㊀Proposed bridgeless buck-boost PFC converterand its two control schematics1.2㊀工作模态为简化分析,作如下假设:1)所有器件为理想器件;2)工频周期远大于开关周期T S ,输入电压v in 在一个开关周期内可以认为是常数㊂由于无桥buck-boost PFC 变换器在正㊁负半个工频周期的运行模式相似,本文仅给出正半工频周期工作模态图,如图3所示㊂图4给出了半个工频周期与开关周期所对应的主要器件波形图㊂由图3与图4可知,所提出的buck-boost PFC 变换器由于交流输入过零换流而存在两种工作阶段:1)当交流输入处于过零换流阶段时,变换器中间电容电压v C 3也需要完成换向;此时,变换器工作模态为A1~A3,v C 3电压不断增大,且只有一个电感处于DCM;2)当中间电容电压v C 3足够大(即存储能量足够大)时,C 3可以支撑闲置电感开始运行于CCM;此时,变换器开始运行于主要工作模态,其工作模态为B1~B4,且两个电感分别工作于CCM 与DCM㊂下边对第一㊁第二工作阶段分别进行介绍㊂首先介绍A1~A3工作模态对应的第一工作阶段㊂工作模态A1[t A0~t A1]:如图3(a)所示,当S 1导通时,v in 对L 1充电,i L 1线性增大㊂同时,C 1与C 2为负载供能㊂此阶段,i L 1增大,V C 1㊁V C 2减小㊂工作模态A2[t A1~t A2]:如图3(b)所示,当S 1关断时,i L 1通过D 1向C 1㊁C 3与负载供能,C 2继续为负载供能㊂此阶段,i L 1㊁V C 2减小,V C 1㊁v C 3增大㊂工作模态A3[t A2~t A3]:如图3(c)所示,S 1保持关断,当i L 1下降至0时,此工作模态开始㊂C 1与C 2为负载供能㊂此阶段V C 1㊁V C 2减小,v C 3不变㊂在工作模态A1~A3所示的第一工作阶段中,v C 3不断增大,V C 2不断减小,直到v C 3>V C 2时,电感L 2的两端电压v L 2不为0,变换器进入第二工作阶段,其工作模态为B1~B4㊂工作模态B1[t B0~t B1]:如图3(d)所示,当S 1导通时,v in 对L 1充电,i L 1线性增大㊂同时,L 2㊁C 3㊁C 1存储的能量向输出电容C 2与负载传递㊂此阶段,i L 2㊁v C 3㊁V C 1减小,i L 1增大㊂工作模态B2[t B1~t B2]:如图3(e)所示,当S 1关断时,i L 1通过D 1向C 1㊁负载供能㊂同时,i L 1较大的电流会导致中间电容C 3的电流方向瞬间突变㊂此时,i L 1㊁i L 2非线性减小,v C 3非线性增大㊂当v C 3增大并超过V C 2,则由于v L 2=V C 2-v C 3<0而导致i L 1开始向L 2充电,即i L 2达到谷值i L 2,va 并开始增大㊂此阶段,i L 1减小,V C 1㊁v C 3增大㊂工作模态B3[t B2~t B3]:如图3(f)所示,S 1保持关断,当i L 1下降到与i L 2相等时(即i C 3=0,因为i L 1=i L 2+i C 3),该工作模态开始㊂该阶段,v C 3不断减小,且i C 3(i L 1<i L 2)反向电流不断增大,即中间电容C 3向C 2㊁L 2传能㊂此阶段,i L 1㊁V C 1非线性下降,其中i L 1保持下降至0,i L 2增大,V C 1㊁v C 3减小㊂23电㊀机㊀与㊀控㊀制㊀学㊀报㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀第27卷㊀图3㊀提出的变换器交流换流时工作模态与主模态Fig.3㊀AC input transition operation modes and main operation modes of proposedconverter图4㊀不同工作模态的关键器件波形图Fig.4㊀Theoretical waveforms of key components in different operation modes㊀㊀工作模态B4[t B3~t B4]:如图3(g)所示,S 1保持关断,当i L 1下降到0时,该工作模态开始㊂该阶段,i L 1保持为0,L 2㊁C 3㊁C 1存储的能量向输出电容C 2与负载传递㊂此阶段,v C 3㊁V C 1非线性减小,i L 2非线性增大㊂当v C 3不断下降并小于V C 2时,则由于v L 2=V C 2-v C 3>0而导致i L 1达到峰值I L 2,pk ,i L 1开始下降㊂此阶段,V C 1㊁v C 3减小㊂2㊀变换器PF 与输出纹波性能分析2.1㊀PF 分析令输入电压峰值为V M ,角频率为ω,则v in 为v in (t )=V M sin(ωt )㊂(1)开关管的平均电流i S1,ave 可以看作输入电流i in ,表达式为i in (t )=i S1,ave (t )=V M |sin(ωt )|d 2L2L 1f S㊂(2)式中:d L 为电感的充电时占空比(即开关管的导通占空比);f S 为开关频率;sin(ωt )的绝对值表示变换器工作于正半工作周期㊂根据式(1)㊁式(2)可以推导瞬时输入功率p in与平均输入功率P in 为:p in (t )=i in (t )v in (t )=(d L V M )22L 1f S sin 2(ωt );(3)P in=1T L /2ʏT L /2i in (t )v in (t )d t =(d L V M )24L 1f S㊂(4)33第11期陈正格等:具有低输出纹波的双电感复用无桥buck-boost PFC 变换器根据式(4)可以推导出导通占空比d L 的表达式为d L =2L 1f S P in /V M ㊂(5)由式(5)可知,在理想条件下,由于L 1㊁f S ㊁P in 与V M 是固定值,占空比d L 也相对固定㊂另一方面,忽略由于使用EMI 滤波器导致的输入电压与输入电流的相位偏移,可以推导变换器的理论PF 为PF =P inV rms I rms =(d L V M )2/42L 1f SV M2ʏT L /2[i in (t )]2d t /T L=1㊂(6)式(6)表明,所提出的变换器在理想情况可以与传统buck-boost PFC 变换器一样,实现高PF㊂这是由于所提出的变换器与输入侧连接时,其工作模态与传统变换器基本相同㊂2.2㊀输出纹波与参数分析将输出星接电容等效为三角接电容,可以得到图5(a)所示的变换器工作等效电路图㊂其中C 1㊁C 2㊁C 3与等效电容C 1E ㊁C 2E ㊁C 3E 的关系为:C 1E =C 2E =C 2C 3C 1+C 2+C 3;C 3E=C 1C 2C 1+C 2+C 3㊂üþýïïïï(7)进一步地,可以将工作等效电路简化为如图5(b)所示的输出等效电路㊂在图5(b)中,相对于传统buck-boost PFC 变换器,所提出变换器的输出等效电路增加了LC 滤波㊁等效电容C 1E ㊂因此,理论上,具备实现更小的输出电流纹波的条件㊂根据式(3)㊁式(4)可知,p in =2P in sin(ωt )㊂输出二极管D 1的平均电流i D1,avg 可以表示为i D1,avg (t )=p in (t )V o =2|sin ωt |2P inV o=I o -I o cos(2ωt )㊂(8)式中I o 为输出电流平均值㊂为简化分析,仅对二倍工频谐波进行输出纹波分析,建立如图5(b)所示的输出等效电路㊂图5(b)中的等效阻抗Z eq 可以采用诺顿定理推导得到,即Z eq=(R ESR -j /2ωC 3E )(Z LC -j /2ωC 1E )R ESR -j /2ωC 3E -j /2ωC 1E +Z LC㊂(9)式中Z LC =L 1C 1E (j2ωL 1-j /2ωC 1E )㊂在图5(b)中,仅考虑输出二倍工频纹波电流(即-I o cos(2ωt ))在负载R L ㊁等效阻抗Z eq 的分流情况㊂则等效电流源I ㊃eq 为I㊃eq=I ㊃o(j /2ωC 1E )Z LC -j /2ωC 1E =I ㊃o -2j ωZ LC C 1E -1㊂(10)由式(9)㊁式(10)可以得到输出二倍工频纹波在负载侧的表达式为I ㊃RL=-Z eq I ㊃o(Z eq+R L )(2j ωZ LC C 2E +1)㊂(11)最后,变换器的输出电流纹波i o,rip 为i o,rip (t )=|I㊃RL|cos{2ωt +arctan[imag(I ㊃RL )real(I ㊃RL )]}㊂(12)图5㊀提出变换器的等效电路Fig.5㊀Equivalent circuit of the proposed converter为反映输出纹波随电容㊁电感参数的变化情况,选取典型值I o =0.5A,ω=100πrad /s,R L =50Ω,C 3=0.47μF,R ESR =20mΩ㊂根据式(12)可以得到,输出纹波电流i o,rip 峰-峰值随输出电容C 1㊁C 2与电感L 1㊁L 2的变化曲面,如图6所示㊂由图可知,所提出的变换器输出纹波电流i o,rip 主要受到输出电容C 1㊁C 2影响,即电容值越大则输出纹波越小,符合输出电容越大对二倍工频纹波滤波效果越强的规律㊂另外,电感L 1㊁L 2对i o,rip 的影响比较小,表现为电感值越大则输出纹波越小㊂43电㊀机㊀与㊀控㊀制㊀学㊀报㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀第27卷㊀图6㊀输出电流纹波随电感、电容的变化曲面Fig.6㊀Output current ripple with output capacitorsand inductors as variables2.3㊀谐波注入控制通过在控制部分引入输入谐波分量可以实现输入功率因数与输出纹波的权衡控制[9-10]㊂这种控制本质是降低PF 值至一定值(通常ȡ0.9),以实现更低的输出电流纹波㊂在实际应用中,较高的PF 值不会带来经济效益,而较低的输出纹波可以让厂家选用更小容值的低成本电容达到同样的输出纹波要求,经济效益更高㊂本文提出的无桥buck-boost PFC 变换器同样可以采用这种PF 与输出纹波的权衡控制,图2(b)给出了控制实现框图㊂这种谐波注入的控制策略,在输入功率P in 较小时,采用较大占空比;在P in 较大时,采用较小占空比,可以实现输入功率平滑传输至输出侧,减小输出纹波㊂具体占空比d L ,H 为d L ,H =ad L (1-k |sin ωt |)=2aL 1f S P in (1-k |sin ωt |)/V M ㊂(13)式中a 与k 都是常数㊂为确定a 与k 值,将式(13)中的d L ,H 代替式(4)中的d L ,可以得到谐波注入控制下的P in,H 为P in,H=2P in a 2πʏπ|sin ωt |2[1-k |sin ωt |]2d(ωt )=2P in a 2π(3πk 28-8k 3+π2)㊂(14)由于P in =P in,H ,因此,由式(14)可得a =π/(34πk 2-163k +π)㊂(15)当占空比由d L ,H 确定时,谐波注入控制下的PF 为PF =2(38k 2π-83k +π2)πʏπ{sin(ωt )[1-k |sin(ωt )|]2}2d(ωt )=2(38k 2π-83k +π2)π(516πk 4-6415k 3+94πk 2-163k +π2)㊂(16)根据式(16),图7给出了以k 为变量的PF 曲线㊂为保证PF ȡ0.9,k 可以取0.607㊂由k =0.607,可以通过式(15)确定a =2.017,则式(13)中的d L ,H 为d L ,H =4.034L 1f S P in [1-0.607|sin(ωt )|]/V M ㊂(17)根据式(3)可以得到单闭环控制的无桥buck-boost PFC 变换器瞬时输出电流为i o (t )=p in /V o =P in[1-cos(2ωt )]/V o ㊂(18)同理,根据式(18)可以得到含谐波注入的单闭环控制时的变换器瞬时输出电流为i o,H (t )=㊀4.068P inV o[1-0.607sin(ωt )]2[1-cos(2ωt )]㊂(19)图7㊀PF 随k 值的变化曲线Fig.7㊀PF curve with constant k as variable将式(18)㊁式(19)中的输出电流除以输出电流I o (I o =P in /V o )进行标幺化,可以得到i o(Norm)(t )=1-cos(2ωt );(20)i o,H(Norm)(t )=4.068[1-0.607sin(ωt )]2ˑ[1-cos(2ωt )]㊂(21)根据式(20)㊁式(21),图8给出了两种控制方法所对应的输出电流标幺值㊂可以看到,采用含谐波注入的单电流闭环控制方法可以减小输出电流的53第11期陈正格等:具有低输出纹波的双电感复用无桥buck-boost PFC 变换器波动,降低输出电流纹波㊂但是,该方法的代价就是如图7所示的PF 值仅大于等于0.9㊂图8㊀两种控制方法输出电流标幺值Fig.8㊀Normalized output current under two controlmethods3㊀实验验证由于单级buck-boost PFC 变换器通常应用于功率ɤ25W 的非隔离LED 应用场合[4]㊂因此,为验证所提出的变换器可行性,分别构建了13W 的传统buck-boost PFC 变换器(Conv.)和所提出的buck-boost PFC 变换器(Prop.)实验样机㊂其中,传统buck-boost PFC 变换器通过图1(a)所示的控制原理图实现㊂为保证控制环路参数的一致性以及实验简便性,样机均采用DSP TMS320F28335实现闭环控制㊂表1给出了关键电路参数,C 1㊁C 2串联,所以C 1=C 2=2C ,V C 1=V C 2=1/2V C ㊂图9给出了所提出的变换器实验样机,传统buck-boost PFC 变换器实验样机基于同一PCB 改造得到㊂开关管S㊁S 1㊁S 2为IPW65R125C7,整流和输出二极管为IDH06G65C5,电感L ㊁L 1㊁L 2磁芯为美磁Kool Mμ77206A7,C ㊁C 1㊁C 2均为电解电容,C 3为MKT1822系列的薄膜电容㊂注意,由于输出电容C 1和C 2是串联的(见图2),因此,C 1和C 2的电容值应为C (见图1)的两倍,但是,C 1和C 2的耐压值仅为C 的1/2㊂表1㊀电路参数Table 1㊀Circuit parameters㊀参数传统变换器所提出变换器f S /kHz 5050V in /f L 110Vac /50Hz 110Vac /50Hz I o /P o 0.5A /13W0.5A /13WL /μH140140C ∗150μF /35V300μF /16VC 3 0.47μF /63V图9㊀所提出的电感复用无桥buck-boost PFC 变换器样机Fig.9㊀Prototype of the proposed bridgeless buck-boostPFC converter with multiplexing inductors㊀㊀在110Vac 输入电压时,分别对传统buck-boost PFC 变换器与所提出的电感复用无桥buck-boost PFC 变换器实验样机进行测试㊂表2给出了具体的实验结果对比㊂表2㊀Buck-boost PFC 变换器实验结果Table 2㊀Experimental results of compared converter㊀参数传统变换器(单闭环控制)提出的变换器(单闭环控制)提出的变换器(含谐波单闭环控制)PF0.9980.9980.908THD i /% 2.9 3.345.6i o,rip /mA220190140Eff./%78.181.380.1图10给出了传统buck-boost PFC 变换器的实验波形㊂由图10(a)㊁图10(b)可知,传统变换器的电感电流i L 在每个交流工频周期中均运行于DCM,开关管漏源两端电压V ds 包络线跟随整流后输入电压V d ㊂结合图10(c)可知,这种传统变换器可以采用简单的单电流环实现稳定运行与输入电流高正弦性㊂图11给出了所提出的电感复用buck-boost PFC 变换器在单电流环控制下的实验波形㊂由图11(a)㊁图11(b)可知,在半个工频周期内,电感电流i L 1㊁i L 2分别交替工作于DCM 与CCM,验证了变换器电感的双工作模态;且中间电容电压v C 3经过短暂的换流后,与工作于CCM 的电感电流形成如图4所示的能量交互,即中间电容C 3与CCM 电感组成滤波网络实现变换器低输出纹波特性㊂另外,结合63电㊀机㊀与㊀控㊀制㊀学㊀报㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀㊀第27卷㊀图11(c)可知,所提出的变换器在单电流环控制下的输出电流纹波为190mA,与图6所示的理论计算值(206mA)接近(注:由于器件参数偏差与测量误差等因素,理论计算值与实际测量值存在一定的偏差)㊂图10㊀传统buck-boost PFC 变换器在单电流环控制时的实验波形Fig.10㊀Experimental waveforms of conventional buck-boost PFC converter图12给出了所提出的变换器在含谐波注入时的单电流环控制下的实验波形㊂由图12(a )㊁图12(b)可知,变换器电感仍然交替地工作于DCM 与CCM,未受到谐波注入的影响㊂结合图12(c)可知,在这种谐波注入控制方式下,变换器输入电流i in 有所畸变,但是变换器PF 值维持在0.908,与图7的理论计算值(PFȡ0.9)接近,验证了参数设计的准确性㊂图11㊀提出的无桥buck-boost PFC 变换器在单电流环控制时的实验波形Fig.11㊀Experimental waveforms of proposed bridge-less buck-boost PFC converter在输出电流纹波i o,rip 方面,对比图10(c)和图11(c),所提出的变换器输出电流纹波(190mA)比传统变换器(220mA)更小㊂这是因为所提出变换器的一个电感与中间电容C 3构成了LC 滤波,可以进一步减小输出纹波㊂另外,对比图11(c)和图12(c),输出电流纹波i o,rip 由190mA 降低到了140mA,降低了35.7%,验证了所提出变换器在含谐波注入控制时,可以实现更低的输出电流纹波㊂在PF㊁THD i 方面,传统变换器的PF 和THD i 分别为0.998和2.9%㊂相应地,所提出的变换器在同样的单电流闭环控制时,PF 和THD i 分别为0.99873第11期陈正格等:具有低输出纹波的双电感复用无桥buck-boost PFC 变换器和3.3%㊂两种变换器的测量数据相近,表明当所提出的变换器与传统变换器使用同样的控制策略时,他们具有几乎相同的PF 和THD i 性能㊂此外,如2.3节所述,当所提出的变换器使用含谐波注入的控制时,通过设置a ㊁k ,可以保证变换器的PF 值高于0.9(实验中为0.908),但是其输出电流纹波仅为140mA,验证了参数设计与理论分析的正确性㊂图12㊀提出的无桥buck-boost PFC 变换器在含有谐波注入控制时的实验波形Fig.12㊀Experimental waveforms of proposed bridge-less buck-boost PFC converter with the har-monic injection control在效率方面,当所提出的变换器采用无谐波注入控制时,变换器的测量效率为81.3%,当采用谐波注入控制时,该变换器的测量效率为80.1%㊂这是因为在含谐波注入的控制时,更多的输入电流谐波会流入变换器,降低了变换器效率㊂另一方面,传统变换器的测量效率仅为78.1%㊂即所提出的无桥buck-boost PFC 变换器在含谐波注入控制时㊁不含谐波注入控制时的效率都略高于传统变换器㊂4㊀结㊀论本文提出一种双电感复用无桥buck-boost PFC 变换器,提高了双变换单元在无桥拓扑中的器件利用率㊂在半个工频周期内,双电感分别交替工作于DCM㊁CCM,且不需要复杂的控制㊁额外的辅助电路㊂工作于DCM 的电感,使变换器可以采用单闭环控制实现高PF 与输出电流调节;工作于CCM 的电感,与中间电容构成额外滤波电路,减小变换器输出纹波㊂此外,该变换器仍然可以采用含谐波注入的控制方法,通过主动降低PF 至0.908,可降低35.7%的输出电流纹波㊂实验样机验证了理论分析的正确性㊂参考文献:[1]㊀WANG Yijie,ALONSO M,RUAN Xinbo.A review of LED driversand related technologies[J].IEEE Transaction on Industrial Elec-tronics,2017,64(7):5754.[2]㊀沈霞,王洪诚,许瑾.基于SEPIC 变换器的高功率因数LED 照明电源设计[J].电机与控制学报,2010,14(1):41.SHEN Xia,WANG Hongcheng,XU Jin.Design of LED lighting power supply with high power factor based on SEPIC converter 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[14]㊀JHA A,SINGH B.A PFC modified landsman converter-basedPWM-dimmable RGB HB-LED driver for large area projection ap-plications[J].IEEE Transactions on Industry Applications,2017,53(2):1552.[15]㊀LIU Pangjung,PENG Kailin.Adaptive driving bus voltage and en-ergy recycling control schemes for low-power AC-DC RGB-LEDdrivers[J].IEEE Transactions on Industrial Electronics,2017,64(10):7741.[16]㊀LIU Pangjung,HONG Zhiyuan,HUNG Chuncheng.A single-stagelow-power AC-DC RGB-LED driver with switching capacitor con-trol scheme[J].IEEE Transactions on Industrial Electronics,2021,68(4):3103.[17]㊀LIU Xueshan,WAN Yuyang,DONG Zheng,et al.Buck-boost-buck-type single-switch multistring resonant LED driver with highpower factor[J].IEEE Transactions on Power Electronics,2020,35(5):5132.[18]㊀何青青,罗全明,曹驰,等.一种模块化开环多路谐振恒流LED驱动电源[J].中国电机工程学报,2019,39(22):6688.HE Qingqing,LUO Quanming,CAO Chi,et al.A modular open-loop multi-channel resonant constant-current LED driver[J].Pro-ceeding of the CSEE,2019,39(22):6688.[19]㊀GUO Y,LI S,LEE A,et al.Single-stage AC/DC single-inductormultiple-output LED drivers[J].IEEE Transactions on Power E-lectronics,2016,31(8):5837.[20]㊀HUBER L,JANG Y,JOVANOVIC M.Performance evaluation ofbridgeless PFC boost rectifiers[J].IEEE Transactions on PowerElectronics,2008,23(3):1381.[21]㊀胡玮,康勇,王学华,等.一种改进型双升压功率因数校正电路[J].电机与控制学报,2013,17(3):40.HU Wei,KANG Yong,WANG Xuehua,et al.Improved dualboost power factor correction converter[J].Electric Machines andControl,2013,17(3):40.[22]㊀吴红飞,张炎锋,杨帆.宽输出电压范围集成Buck型无桥PFC变换器[J].中国电机工程学报,2018,38(22):6655.WU Hongfei,ZHANG Yanfeng,YANG Fan.Bridgeless power fac-tor correction converter with integrated buck converter for wideoutput voltage range applications[J].Proceeding of the CSEE,2018,38(22):6655.[23]㊀曹太强,黄俊,王军,等.基于磁集成的双Boost无桥PFC变换器研究[J].电机与控制学报,2014,18(4):6.CAO Taiqiang,HUANG Jun,WANG Jun,et al.One-cycle con-trolled bridgeless Pseudo-Boost PFC converter[J].Electric Ma-chines and Control,2014,18(4):6.[24]㊀蔡成超,沈艳霞,赵文辉,等.基于Cuk变换器的无桥LED驱动电源[J].电源学报,2019,17(4):57.CAI Chengchao,SHEN Yanxia,ZHAO Wenhui,et al.BridgelessLED driver based on Cuk converter[J].Journal of Power Sup-ply,2019,17(4):57.[25]㊀史旭,刘雪山,周群,等.基于无源均流的谐振式无桥型BoostLED驱动电源[J/OL].电源学报:1-13[2021-11-22].ht-tp:///kcms/detail/12.1420.TM.20211122.1445.004.html.SHI Xu,LIU Xueshan,ZHOU Qun,et al.A resonant bridgelessboost LED driver based on passive current balancing[J/OL].Journal of Power Supply:1-13[2021-11-22].http://kns./kcms/detail/12.1420.TM.20211122.1445.004.ht-ml.[26]㊀MA Hongbo,LAI J S,ZHENG Cong,et al.A high-efficiency qua-si-single-stage bridgeless electrolytic capacitor-free high-powerAC-DC driver for supplying multiple LED strings in parallel[J].IEEE Transactions on Power Electronics,2016,31(8):5825.[27]㊀CHEN Zhengge,DAVARI P,WANG Huai.Single-stage bridgelessbuck-boost PFC converter with DC split for low power LED appli-cations[C]//2018IEEE International Power Electronics and Ap-plication Conference and Exposition(PEAC),November4-7,2018,Shenzhen,China.2018:1-6.[28]㊀王金平,胡凡宇,侯良奎,等.一种单级无桥隔离型PFC变换器[J].中国电机工程学报,2017,37(24):7276.WANG Jinping,HU Fanyu,HOU Liangkui,et al.An isolated PFCconverter with single-stage and bridgeless properties[J].Proceed-ings of the CSEE,2017,37(24):7276.[29]㊀CHEN Zhengge,LIU Bochen,YANG Yongheng,et al.BridgelessPFC topology simplification and design procedure for performancebenchmarking[J].IEEE Transactions on Power Electronics,2021,36(7):6916.(编辑:邱赫男)93第11期陈正格等:具有低输出纹波的双电感复用无桥buck-boost PFC变换器。

Analog Devices OP221 Dual Low Power Operational Am

REV. CInformation furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.aOP221One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-4700 Fax: 781/326-8703© Analog Devices, Inc., 2002Dual Low Power Operational Amplifier,Single or Dual SupplyFEATURESExcellent TCV OS Match, 2 ␮V/؇C Max Low Input Offset Voltage, 150 ␮V Max Low Supply Current, 550 ␮A Max Single Supply Operation, 5 V to 30 VLow Input Offset Voltage Drift, 0.75 ␮V/؇C High Open-Loop Gain, 1500 V/mV Min High PSRR, 3 ␮V/VWide Common-Mode Voltage Range, V– to within 1.5 V of V+Pin Compatible with 1458, LM158, LM2904Available in Die FormGENERAL DESCRIPTIONThe OP221 is a monolithic dual operational amplifier that can be used either in single or dual supply operation. The wide supply voltage range, wide input voltage range, and low supply current drain of the OP221 make it well-suited for operation from batteries or unregulated power supplies.The excellent specifications of the individual amplifiers combined with the tight matching and temperature tracking between channelsSIMPLIFIED SCHEMATIC–IN +IN*ACCESSIBLE IN CHIP FORM ONL YV+OUTPUTV–8-Lead SOIC (S-Suffix)NC = NO CONNECT+IN A V–+IN B –IN A OUT A V+OUT B–IN B PIN CONNECTIONSprovide high performance in instrumentation amplifier designs.The individual amplifiers feature very low input offset voltage,low offset voltage drift, low noise voltage, and low bias current.They are fully compensated and protected.Matching between channels is provided on all critical parameters including input offset voltage, tracking of offset voltage vs. tem-perature, non-inverting bias currents, and common-mode rejection.OP221–SPECIFICATIONS(Electrical Characteristics at V s = ؎2.5 V to ؎15 V, T A = 25؇C, unless otherwise noted.)OP221GParameter Symbol Conditions Min Typ Max Unit Input Offset Voltage V OS250500m VInput Offset Current Ios V CM = 0 1.57nAInput Bias Current I B V CM = 070120nAInput Voltage Range IVR V+ = 5 V, V– = 0 V10/3.5VV S = ±15 V–15/13.5Common-Mode CMRR V+ = –5 V, V– = 0 VRejection Ratio0 V £ V CM £ 3.5 V7585V S = ±15 V dB–15 V £ V CM£ 13.5 V8090Power Supply PSRR V S = ±2.5 V to ± 15 V32100m V/V Rejection Ratio V– = 0 V, V+ = 5 V to 30 V57180Large-Signal Avo V S = ±15 V, R L = 10 k WVoltage Gain V O = ±10 V800V/mVOutput Voltage V O V+ = 5 V, V– = 0 V0.8/4VSwing R L = 10 k WV S = 15 V, R L = 10 k W±13.5Slew Rate SR R L = 10 k W20.20.3V/m S Bandwidth BW600kHz Supply Current I SY V S = ±2.5 V, No Load550650m A (Both Amplifiers)V S = ±15 V, No Load850900–2–REV. COP221 SPECIFICATIONS(Electrical Characteristics at V S = ؎2.5 V to ؎15 V, –40؇C £ T A£ +85؇C, unless otherwise noted.)OP221GParameter Symbol Conditions Min Typ Max Unit Average Input TCV OS23m V/∞C Offset Voltage Drift1Input Offset Voltage V OS400700m VInput Offset Current I OS V CM = 0210nA Input Bias Current I B V CM = 080140nA Input Voltage Range IVR V+ = 5 V, V– = 0 V20/3.2VV S = ±15 V–15/13.2Common-Mode CMRR V+ = –5 V, V– = 0 VRejection Ratio0 V £ V CM £ 3.5 V7080V S = ±15 V dB–15 V £ V CM£ 13.5 V7585Power Supply PSRR V S = ±2.5 V to ± 15 V57180m V/V Rejection Ratio V– = 0 V, V+ = 5 V to 30 V100320Large-Signal A VO V S = ±15 V, R L = 10 k WVoltage Gain V O = ±10 V600V/mV Output Voltage V O V+ = 5 V, V– = 0 V0.9/3.7Swing R L = 10 k W VV S = 15 V, R L = 10 k W13.2Supply Current I SY V S = ±2.5 V, No Load600750m A (Both Amplifiers)V S = ±15 V, No Load9501000NOTES1Sample tested.2Guaranteed by CMRR test limits.Matching Characteristics at V s = ؎15 V, T A = 25؇C, unless otherwise noted.OP221GParameter Symbol Conditions Min Typ Max Unit Input OffsetVoltage Match D V OS250600m V Average NoninvertingBias Current I B+120nA Noninverting Input I OS+410nA Offset CurrentCommon-ModeRejection Ratio D CMRR V CM = –15 V to 13.5 V72dB Match1Power SupplyRejection Ratio D PSRR V S = ±2.5 V to ± 15 V140m V/V Match2NOTES1D CMRR is 20 log10 V CM/D CME, where V CM is the voltage applied to both noninverting inputs and D CME is the difference in common-mode input-referred error.2D PSRR is: Input-Referred Differential ErrorD V SREV. C–3–REV. C–4–OP221–SPECIFICATIONS.OP221GParameter Symbol Conditions Min Typ Max Unit Input Offset Voltage Match D V OS 400800m V Average Noninverting I B +V CM = 0140nA Bias Current Input OffsetIC D V OS 35m V ∞C Voltage Tracking Noninverting Input I OS +V CM = 0612nAOffset Current Common-Mode Rejection Ratio D CMRR V CM = –15 V to 13.2 V 7280dBMatch 1Power Supply Rejection Ratio D PSRR 140m V/VMatch 2NOTES 1D CMRR is 20 log 10 V CM /D CME, where V CM is the voltage applied to both noninverting inputs and D CME is the difference in common-mode input-referred error.2D PSRR is: Input-Referred Differential ErrorD V S(Matching Characteristics at V s = ؎15 V, –40؇C £ T A £ +85؇C for OP221G, unless other-wise noted. G is sample tested.)REV. C OP221–5–CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the OP221 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.ABSOLUTE MAXIMUM RATINGS (Note 1)Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±18 V Differential Input Voltage . . . . . . . . . .30 V or Supply Voltage Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .Supply Voltage Output Short-Circuit Duration . . . . . . . . . . . . . . . .IndefiniteStorage Temperature Range . . . . . . . . . . . .–65∞C to +150∞C Operating Temperature RangeOP221G . . . . . . . . . . . . . . . . . . . . . . . . . . . .–40∞C to +85∞C Lead Temperature (Soldering 60 sec) . . . . . . . . . . . . . .300∞CJunction Temperature (T J ) .. . . . . . . . . . . .–65∞C to +150∞C Figure 1. Dice CharacteristicsPackage Type ␪JA (Note 2)␪JC Unit 8-Lead SOIC(S)15843∞C/WNOTES1Absolute maximum ratings apply to both DI CE and packaged parts, unless otherwise noted.2␪JA is specified for device soldered to printed circuit board for SOIC package.ORDERING GUIDET A = +25؇C Operating Package V OS MAX Plastic Temperature Options(␮V)8-LeadRange150150300500500500OP221GS XIND RN-8REV. COP221–Typical Perfomance Characteristics–6–TEMPERA TURE – ؇C O P E N -L O O P G A I N – d B 140120100806040200TPC 1.Open-Loop Gain at ±15 V vs.Temperature FREQUENCY – HzO P E N -L O O P G A I N – d B12080604020100TPC 4.Open-Loop Gain at ±15 V vs.FrequencyTEMPERA TURE – ؇C P H A S E M A R G I N – D e g r e e s555045400.350.300.250.20650kG A I N B A N D W I D T H – H zS L E W R A T E –V /␮s e cTPC 7.Phase Margin, Gain Bandwidth,and Slew Rate vs. T emperatureTEMPERA TURE – ؇C O P E N -L O O P G A I N – d B 140120100806040200TPC 2.Open-Loop Gain at ± 5 V vs.TemperatureFREQUENCY – Hz110100C L O SE D -L O O P G A I N – d B70–1060302010050401k 10k 100k 1M 10MTPC 5.Closed-Loop Gain vs.FrequencyFREQUENCY – HzP S R R – d B120100806040200TPC 8.PSRR vs. FrequencySUPPL Y VOL T AGE – VO P E N -L O O P G A I N – d B140120100806040200TPC 3.Open-Loop Gain at vs.Supply VoltageFREQUENCY – HzV O L T A G E G A I N –d B25100k1M10M5P H AS E S H I F T – D e g r e e s2015100–580220200180140160120100TPC 6.Gain and Phase Shift vs.FrequencyC M R R – H zFREQUENCY – Hz12010080604020010100TPC 9.CMRR vs. FrequencyREV. C OP221–7–FREQUENCY – HzP E A K -T O -P E A K A M P L I T U T D E – V301K1M10k 100k 2824201612840TPC 10.Maximum Output Swing vs. FrequencyFREQUENCY – HzV O L T A G E N O I S E – n V /H z11k101001001080706050402030TPC 13.Voltage Noise Density vs.Frequency LOAD RESIST ANCE – ⍀M A X I M U M O U T P U T – V16100100k1k 10k 14121086420TPC 11.Maximum Output Voltage vs. Load ResistanceFREQUENCY – HzC U R R E N T N O I SE – p A H z100.111k1.010100TPC 13.Current Noise Density vs.FrequencyLOAD RESIST ANCE – ⍀M A X I M U M O U T P U T – V100100k1k 10k 2.01.00TPC 12.Maximum Output Voltage vs. Load ResistanceREV. COP221–8–Figure 3a.Inverting Step ResponseFigure 3b.Inverting Step ResponseFigure 5.Inverting Test CircuitFigure 2a.Noninverting Step ResponseFigure 2b.Noninverting Step ResponseFigure 4.Noninverting Test CircuitREV. C OP221–9–SPECIAL NOTES ON THE APPLICATION OF DUAL MATCHED OPERATIONAL AMPLIFIERSAdvantages of Dual Monolithic Operational AmplifiersDual matched operational amplifiers provide the engineer with a powerful tool for designing instrumentation amplifiers and many other differential-input circuits. These designs are based on the principle that careful matching between two operational amplifiers can minimize the effect of dc errors in the individual amplifiers.Reference to the circuit shown in Figure 6, a differential-in,differential-out amplifier, shows how the reductions in error can be accomplished. Assuming the resistors used are ideally matched,the gain of each side will be identical. If the offset voltages of each amplifier are perfectly matched, then the net differential voltage at the amplifier’s output will be zero. Note that the output offset error of this amplifier is not a function of the offset voltage of the individual amplifiers, but only a function of the difference (degree of matching) between the amplifiers’ offset voltages. This error-cancellation principle holds for a considerable number of input referred error parameters—offset voltage, offset voltage drift, inverting and noninverting bias currents, common mode and power supply rejection ratios. Note also that the impedances of each input, both common-mode and differential-mode, are high and tightly matched, an important feature not practical with single operation amplifier circuits.–Figure 6.Differential-In, Differential-Out AmplifierINSTRUMENTATION AMPLIFIER APPLICATIONS Two-Op Amp ConfigurationThe two-op amp circuit (Figure 7) is recommended where the common-mode input voltage range is relatively limited; the common-mode and differential voltage both appear at V1. The high open-loop gain of the OP221 is very important in achieving good CMRR in this configuration. Finite open-loop gain of A1(Ao1) causes undesired feedthrough of the common-mode input.For Ad/Ao, << 1, the common-mode error (CME) at the out-put due to this effect is approximately (2 Ad/Ao1) x VCM. This circuit features independent adjustment of CMRR and differ-ential gain.Three-Op Amp ConfigurationThe three-op amp circuit (Figure 8) has increased common-mode voltage range because the common-mode voltage is not amplified as it is in Figure 7. The CMR of this amplifier is directly proportional to the match of the CMR of the input op amps. CMRR can be raised even further by trimming the output stage resistors.V V O – A D V DV O = 12R2R1+V d +–VCMR3R4R4R3R4R3R3R4R2R1IF R1 = R2 = R3 = R4, THEN V O = 2 1 +V DR1R0Figure 7.Two-Op Amp CircuitV V V OFigure 8.Three-Op Amp CircuitREV. COP221–10–OUTLINE DIMENSIONS8-Lead Standard Small Outline Package [SOIC]Narrow Body (RN-8)Dimensions shown in millimeters and (inches)45؇PLANECONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGNCOMPLIANT TO JEDEC STANDARDS MS-012AAREV. C OP221–11–Revision HistoryLocationPage10/02—Data Sheet changed from REV. B to REV. C.Deleted 8-Lead CERDIP Package (Q-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2–4Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106/02—Data Sheet changed from REV. A to REV. B.Edits to 8-Lead SOIC Package (R-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1009/01—Data Sheet changed from REV. 0 to REV. A.Edits to PIN CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Global deletion of references to OP221B and OP221C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2, 3, 4Edits to WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Edits to PACKAGE TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5)C(2/1––423C.A.S.UNIDETNIRP –12–。

Supertex TP0606 低阈值增强型MOS接口电路说明书

Supertex inc.TP0606Features►Low threshold (-2.4V max.) ►High input impedance►Low input capacitance (80pF typ.) ►Fast switching speeds ►Low on-resistance►Free from secondary breakdown►Low input and output leakageApplications►Logic level interfaces – ideal for TTL and CMOS ►Solid state relays►Battery operated systems ►Photo voltaic drives ►Analog switches►General purpose line drivers►Telecom switchesGeneral DescriptionThis low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown.Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired.P-Channel Enhancement-ModeVertical DMOS FETAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.TO-92 (N3)GATESOURCEDRAINTO-92 (N3)Product MarkingPin ConfigurationPackage may or may not include the following marks: Si orFor packaged products, -G indicates package is RoHS compliant (‘Green’). Devices in Wafer / Die form are RoHS compliant (‘Green’).Refer to Die Specification VF25 for layout and dimensions.YY = Year Sealed WW = Week Sealed= “Green” PackagingSiTP 0606 Y Y W W= 25OC unless otherwise specified)1. All D.C. parameters 100% tested at 25O C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)2. All A.C. parameters sample tested.Notes:† I D (continuous) is limited by max rated T j .Switching Waveforms and Test CircuitINPUTOUTPUT0VVDD0V-10VTypical Performance CurvesI D (a m p e r e )G F S (s i e m e n s )V DS (volts)I D (a m p e r e s )t p (seconds)GS = -10VTypical Performance Curves (cont.)C (p i c o f a r a d s )2.01.61.20.80.4B V D S S (n o r m a l i z e d )BV Variation with TemperatureR D S (O N ) (n o r m a l i z e d )I D (a m p e r e s )Q G (nanocoulombs)V DS (volts)Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//)©2011 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.Supertex inc.1235 Bordeaux Drive, Sunnyvale, CA 94089(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to /packaging.html .)3-Lead TO-92 Package Outline (N3)JEDEC Registration TO-92.* This dimension is not specified in the JEDEC drawing.† This dimension differs from the JEDEC drawing.Drawings not to scale.Supertex Doc.#: DSPD-3TO92N3, Version E041009.Seating。

集成电路设计-part1-5

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半定制设计——标准单元设计
标准单元布图方法在布图时，从单元库中调出标准单元按行排列，行与行之间留有布线通道，同行或相邻行的单元相连可通过单元行的上、下通道完成。隔行单元之间的垂直方向互连则必须借用事先预留在“标准单元”内部的走线道（feedthrough）或在两单元间设臵的“走线道单元 ”（feed-through cell）或“空单元”（empty cell）来完成连接。
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不同设计方法比较
表二不同的设计模式的芯片面积、性能和掩膜制作方式
全定制小高全部设计模式标准单元门阵列较小中等较高中等全部金属连线及孔 FPGA 大低不需要
芯片面积芯片性能制作掩膜
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不同设计方法比较
大批量的产品，如微处理器，存储器等宜采用全定制设计方法。小批量ASIC产品则采用半定制的门阵列或宏单元阵列设计方法。单件、批量很小的产品、试验电路则采用FPGA设计方法。电性能要求较高，而批量较小的产品，或中批量产品则采用标准单元设计方式。
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不同设计方法比较
芯片费用公式：
CT CD / N CP /( yn)
每个芯片的总费用： N：总产量 Cp：每个圆片的制造费用 CD：设计及制版费 n：圆片上芯片数 y：圆片成品率
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不同设计方法比较
从设计规模考虑：设计成本、效率、质量、是相互制约的。如果设计一个高质量的版图，需要付出较高的成本，同时使设计效率下降。反之，如果要求低成本和较高效率，那么往往要在设计质量上作出某些让步。

mulitism简易教程第3章解析

第3章元(器)件库与元(器)件编辑
例3.2 以电容元件为例对现实元件进行编辑。双击现实电容元件图标，可得到图3-6所示的对话框。
第3章元(器)件库与元(器)件编辑图3-6 电容元件对话框
第3章元(器)件库与元(器)件编辑
点击图3-6中的Edit按钮，可得到图3-7所示的对话框。通过该对话框，可以编辑电容元件的标号、引脚和电参数。需要注意的是，不能对交互元件(在Multisim中，将用来显示电路仿真结果的显示器件(如发光二极管等)称为交互元编辑例3.3 以NPN晶体管为例，通过其属性对话框(见图3-10)
对其参数进行设置。
图3-10 NPN晶体管属性对话框
第3章元(器)件库与元(器)件编辑
在图3-10中的Fault页中，可以对管子开路、短路情况进行设置分析；在Value页中，可以对管子引脚进行编辑。点击图3-10中的Edit Model按钮，弹出图3-11所示对话框，通过该对话框可对NPN晶体管的参数进行设置。
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(a) 图3-3 调幅信号源
第3章元(器)件库与元(器)件编辑
(b) 图3-3 调幅信号源
第3章元(器)件库与元(器)件编辑 (2) 在图3-3(a)中，双击调幅信号源图标，可弹出图3-4所
示的属性对话框。
图3-4 属性对话框
第3章元(器)件库与元(器)件编辑
3.1.2 基本元件库
第3章元(器)件库与元(器)件编辑
(1) NPN晶体管 (3) PNP晶体管 (5) 虚拟四端双极性NPN晶体管 (7) NPN复合晶体管 (9) 带偏置电阻的NPN晶体管 (11)晶体管阵列 (13)三端N沟道耗尽型MOS管 (15)三端P沟道耗尽型MOS管 (17) 三端N沟道增强型MOS管 (19) 三端P沟道增强型MOS管 (21) 虚拟四端N沟道耗尽型MOS管 (23) 虚拟四端N沟道增强型MOS管 (25) N沟道J型场效应管 (27) P沟道J型场效应管 (29) 虚拟N沟道砷化镓场效应管 (31) N沟道功率MOS管 (33)互补功率MOS管