How the voltage reference affects ADC performance Part 1
ADC选择最合适的基准电压源和放大器
如何为您的ADC选择最合适的基准电压源和放大器主题: 驱动精密ADC:如何为您的ADC选择最合适的基准电压源和放大器?在线问答:[问:callhxw] 如何评定一颗ADC非线性?丢码?[答:Jing] you can use ADC"s INL and DNL parameter to evaluate thenon-linearity and you can also use ENOB parameter to check code loss. Thanks!Generally ENOB releated with ADC"s SNR [2006-2-28 10:32:08] [问:吉星] 在差分输入时,不考虑直流,使用差分放大器和变压器哪个更好.[答:Mariah] Transformer is better for the better noise and distortion performance, especially in very high frequencies. [2006-2-28 10:32:14] [问:Jane Yang] 请问应如何处理板级噪声对于高精度AD的影响?特别是输入部分的噪声?[答:Jing] This is a good question and it"s very difficult to answer. Generally, You should consider all the input noise derived fromsensor/AMP/BUFFER. You can also use a LPF to reduce the input noise. Remember the BGP of AMP should be 100x of ADC"s throughput. Thanks! [2006-2-28 10:34:30][问:石林艳] AD变换的参考基准源很重要,对模拟供电电源和数字供电电源的要求也很高吗[答:Rui] 模拟供电电源,和数字供电电源相对基准源来说,精度要求相对较低,一般情况下用10uF的电容和0.1uF滤波即可。
Precision voltage references
Precision voltage referencesIntroductionOne reason why designing a data conversion system is such a challenge is the fact that the system accuracy very much depends on the accuracy of the voltage established by the internal or external DC voltage reference. The voltage reference is used to produce a precise value of output voltage for setting the full-scale input of the data conversion system. In an analog-to-digital converter(ADC), the DC voltage reference together with the analog input signal is used to generate the digitized output signal.And in a digital-to-analog converter (DAC), the DACselects and produces an analog output from the DC refer-ence voltage according to the digital input signal presented at the input of the DAC. Any errors in the reference volt-age over the operating temperature range will adversely affect the linearity and spurious free dynamic range (SFDR) of the ADC/DAC. Practically all voltage refer-ences vary with time or environmental factors such as humidity, pressure, and temperature. As a result most CMOS ADCs/DACs have internal references suitable only for applications demanding ≤12-bit resolution eventhough the converter may be capable of higher resolution.Modern CMOS converters operate from 3.3-V or 5-V sup-plies, which limits the on-chip voltage reference to aband-gap reference. By way of the external reference pins provided on the chip, an external precision reference can also be connected to a CMOS ADC or DAC. A precision external voltage reference has a much lower temperature coefficient, thermal hysteresis, and long-term drift than an on-chip band-gap voltage reference; therefore, in applications demanding high accuracy (14-bit or 16-bit ADCs/DACs), an external precision voltage reference is often required.Precision voltage references are available with varying degrees of precision and initial accuracy over someoperating temperature range. But often what is not obvi-ous when reading a manufacturer’s data sheet is how theinitial accuracy of the device is affected by other key device parameters such as line regulation, load regulation, initial voltage error, output voltage temperature coefficient (TC),output voltage noise, turn-on settling time, thermal hyste-resis, quiescent supply current, and long-term stability.The design originsModern voltage references are constructed using the energy-band-gap voltage of integrated transistors, buried zener diodes, and junction field-effect transistors. Each technology offers inherent performance characteristics that can be enhanced with compensation networks or additional active circuitry. The basis topologies for the band-gap, buried zener, and XFET references are shown in Figures 1, 2, and 3, respectively.Texas Instruments Incorporated Data AcquisitionBy Perry Miller, Application Specialist—Data Converters, Texas Instruments, Dallas,and Doug Moore, Managing Director, Thaler Corp., Tucson, Arizona Continued on next pageTexas Instruments IncorporatedData AcquisitionBand-gap referenceAt its simplest, a band-gap reference is simply two tran-sistors with different emitter areas used for generating a voltage proportional to absolute temperature. V BE1and V BE2have opposite temperature coefficients. The voltage V CC is converted to a current I 1and I 2that are mirrored to the output branch. The output equation is(1)where λis the scale factor, V BE1is the base-emitter volt-age of the larger of the two transistors, and V BE2is thebase-emitter voltage of the second transistor.The band-gap references are widely used in ADC/DAC converters as well as for external reference source because they are fairly inexpensive. Generally, they are used in system designs where a maximum accuracy of 10 bits is required. Band-gap references typically have an initial error of 0.5–1.0% and a TC of 25–50 ppm/°C. The output voltage noise is typically 15–30 µV p-p (0.1–10 Hz) with a long-term stability of 20–30 ppm/1000 hrs.Zener referenceThe zener voltage reference and feedback amplifier shown in Figure 2 are used to provide a very stable output. A current source is used to bias a 6.3-V zener diode. The zener voltage is divided by the resistor network R1 and R2.This voltage is applied to the non-inverting input of the operational amplifier, which amplifies the voltage to the required output voltage. The amplifier gain is determined by the resistor networks R3 and R4, where G = 1 + R4/R3.A 6.3-V zener diode is used because it is the most stable zener diode over time and temperature.The output equation is(2)Buried zener diode references are more expensive than band-gap references but provide a higher performance level. They typically have an initial error of 0.01–0.04%, a TC of 1–10 ppm/°C, and less than 10-µV p-p (0.1- to 10-Hz)),V V (V V BE2BE1BE1O −λ+=noise. The long-term stability is typically 6–15 ppm/1000hrs. Buried zener-based references are frequently used for 12-bit, 14-bit, and higher resolution systems because the performance of the buried zener-based references can be extended by incorporating nonlinear temperature com-pensation networks into the design. The compensation network is trimmed at several temperatures to optimize the electrical performance over the operating tempera-ture range.XFET referenceThe XFET reference is a new reference technique that consists of two junction field-effect transistors, one of which has an extra channel implant to raise the pinch-off voltage. The two JFETs are run at the same drain current.The difference in pinch-off voltage is amplified and used to form a voltage reference. The general equation is(3)where ∆V P is the difference in pinch-off voltage betweenthe two FETs and I PTAT is the positive temperature coefficient correction current.The simplified schematic for the XFET reference is shown in Figure 3.The XFET references are relatively new and provide a performance level between band-gap and zener refer-ences.The initial error is typically 0.06%, a TC of 10 ppm/°C,and 15-µV p-p (0.1- to 10-Hz) noise. The long-term stability is 0.2 ppm/1000 hrs.Reference selection for a 14-bit converterSpecified parameters for voltage references include line regulation, load regulation, initial voltage error, output voltage temperature coefficient (TC), output voltage noise, turn-on settling time, thermal hysterisis, quiescent supply current, and long term stability.The most important parameters for data acquisition systems design are initial error, output voltage tempera-ture coefficient (TC), thermal hysteresis, noise, and long-term stability of the voltage reference device.Table 1 summarizes the major error sources for the three references that are compared in this application note. The data represents the highest grade for each)(R3),(I R1R3R2R1V V PTAT P O +++∆=Table 1. Voltage reference major error sources (all information is based on published data sheets)Continued from previous page× V . ZR3R41R2R1R2V O++=Texas Instruments Incorporated Data Acquisitionrespective model in the 8-pin plastic DIP package over the industrial temperature range (–40°C to +85°C). The poorest-performing references are band-gap type and are not included in this summary. Buried zener diodes have better overall performance than band-gap devices and the XFET references. The buried zener reference with a third-order temperature compensation network (VRE3050) is the best performer with respect to initial error, TC, and thermal hysteresis.Explanation of parametersInitial error—The output voltage tolerance of a refer-ence after the device is turned on and warmed up. It is usually measured without a load applied. In many applica-tions, initial error is the most important specification.Often instrument manufacturers will specify a reference with a tight initial error so they do not have to perform room-temperature systems calibration after assembly.Temperature coefficient (TC)—A change in output voltage due to change in temperature usually expressed in ppm/°C. It is the second most important specification after initial accuracy. For many instrument manufacturers,a voltage reference with a temperature coefficient less than 1 ppm/°C makes it possible not to have to perform a system temperature calibration, a slow and costly process.Of the three TC specification methods (slope, butterfly,and box), the box method is most commonly used. A box is formed by the min/max limits for the nominal output voltage over the operating temperature range. The equa-tion follows.(4)6MIN MAX nominal MIN MAX 10)T (T V V V TC ×−×−=This method corresponds more accurately to the method of test and provides a closer estimate of actual error than the other methods. The box method guarantees limits for the temperature error but does not specify the exact shape and slope of the device under test. Assuming a 5-V reference with a 0.6-ppm/°C TC over the industrial tem-perature range, a plot of the box calculation method would appear as in Figure 4.A designer who needs a 14-bit accurate data acquisition system over the industrial temperature range (–40°C to +85°C) will need a voltage reference with a TC of 1.0 ppm/°C if the reference is allowed to contribute an error equivalent to 1 LSB. For 1/2 LSB equivalent error from the reference, a voltage reference with a tempera-ture coefficient of 0.5 ppm/°C would be needed. Figure 5shows the required reference TC vs. ∆T change from25°C for resolution rang-ing from 8 bits to 20 bits.Thermal hysteresis—A change in output voltage as a result of a tempera-ture change. When references experience a temperature change and return to the initial tem-perature, they do not always have the same initial output voltage.Thermal hysteresis is dif-ficult to correct and is a major error source in sys-tems that experience tem-perature changes of 25°C or more. Voltage refer-ence manufacturers are starting to include this important specification in their datasheets.Continued on next pageTexas Instruments IncorporatedData AcquisitionNoise (1/f and broadband)—Electrical noise on the output of a voltage reference. It can include wideband ther-mal noise and narrowband 1/f noise.Wideband noise can be effectively filtered with a simple RC network. 1/f noise is inherent in the reference and cannot be filtered. It is specified in the 0.1- to 10-Hz range. Low 1/f noise refer-ences are important in precision designs.Long-term drift—A slow change inoutput voltage that occurs over months of operation. Long-term drift is usually expressed in ppm/1000 hrs. In zener references, the long-term drift is typi-cally 6 ppm/1000 hrs. and decreases atan exponential rate over time. Additional temperature burn-in of the reference can accelerate the stability of a zener reference. The XFET reference has excellent long-term stability—0.2 ppm/1000 hrs.Turn-on settling time—A change in voltage over a specified time interval after the power is applied. Most references settle to 0.1% in less than 10 µs. Turn-on settling time is important for portable battery systems that conserve energy by powering the circuitry only for short periods of time.Line regulation—An error produced by a change in the input voltage. This dc specification does not include the effects of ripple voltage or line transients.Load regulation—An error produced by a change in load current. Like line regulation, this dc specification does not include the effects of load transients.PCB layout—Poor printed circuit board layout can adversely affect the performance of the reference. Poor layout can affect the output voltage, noise, and thermal performance of the device. Inherent stress in the PCB can also be transferred to the reference and can shift the out-put voltage.ConclusionIt has been shown that a number of key parameters must be evaluated before selecting an external reference for a high-resolution data acquisition system. The XFET refer-ence is suitable for systems that will be held at a constant temperature and where good long-term stability of the reference is important. In 14-bit conversion systems that are designed for the industrial operating temperature range, the VRE3050 is the preferred device because of its better initial error, TC, and thermal hysteresis performance.References1.Analog Devices Inc., Low Noise, Micropower,Precision Reference ADR293 Datasheet.2.Paul R. Gray and Robert G. Meyer, Analysis and Design of Analog Integrated Circuits ,3rd ed. (John Wiley & Sons, Inc., 1992).3.Maxim Corp., MAX6250, Low Noise Precision,+2.5 V +4.096 V +5 V Voltage Reference Datasheet.4.Texas Instruments, THS1265, 12-bit, 65 MSPS,IF Sampling Communications A/D converter.5.Texas Instruments, THS1470, 14-bit, 70 MSPS,IF Sampling Communications A/D converter.6.Thaler Corp., Precision Reference VRE3050Datasheet.Continued from previous pageIMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. 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带隙基准
Key words: Bandgap Reference; Layout; Power Supply Rejection Ratio; Temperature Coefficient
III
目
第1章 1.1
录
绪论············································································ 1 带隙基准源概述······························································1 1.1.1 1.1.2 带隙基准源的研究现状········································· 1 研究目的及意义···········································设计········································· 17 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 设计指标·························································· 17 带隙基准源架构·················································17 核心电路设计···················································· 20 运放设计·························································· 22 偏置电路设计···················································· 23
基于Cadence的基准电压源设计与仿真
之 差来实现。由于耗尽型晶体管在电路中一般不用,所以这种方 法 在 大 多 数 CMOS电路中也是不用的。虽然这种方法实现的基准 十 分 稳 定 ,但 由 于 增 强 型 和 耗 尽 型 器 件 的 阈 值 电 压 的 灵 敏 度 ,从 而很难准确地确定基准的实际值。(3)用 一 个 PTAT (与绝对温度 成 比 例 )电路的正温度相关性抵消一个p n 结的负温度相关性。 这 种 方 法 是 双 极 性 和 双 CMOS技术来说现在最常用的方法。一般 地将这种方法实现的电压基准称为带隙基3; V qi
(5)
已知
管 (或基极一发射极结)的电压的差异来实现的。
输出电压公式为:
V^ = Vbe + K V t
(1)
V B E 的温度系数约为-2mV/oC,V T 的温度系数约为0. 085mV/
〇C。对 上 式 求 导 得 :
The Design and Simulation of reference Voltage Source based on Cadence
Qian Xiang
(School of electronics and technology, Wuxi Professional College of Science and Technology,Wuxi Jiangsu, 214028)
〇引言
基 准 电 压 源 是 模 拟 电 路 中 的 重 要 组 成 部 分 ,它要 求 与 电 源 和 温 度 的 关 系 尽 量 小 。在 集 成 电 路 中 实 现 电 压 基 准 基 本 采 用 以 下 三 种 方 法 :(1)利用稳压二极管在反偏时的击穿来实现。但是稳压 二极管的击穿电压一般大于目前电路中的电源,所以这种方法不 再 经常使用。(2 )利用增强型晶体管和耗尽型晶体管的阈值电压
电流复用技术
10-bit 100-MS/s Pipelined ADC Using Input-Swapped Opamp Sharing and Self-Calibrated V/I ConverterMoo-Young Kim ,Student Member,IEEE ,Jinwoo Kim ,Member,IEEE ,Tagjong Lee ,Student Member,IEEE ,and Chulwoo Kim ,Senior Member,IEEEAbstract—A 31mW,10-bit 100-MS/s pipelined analog-to-digital converter (ADC),which alleviates the memory effect occurring in the opamp-sharing technique,and automatically corrects the cur-rent error of the V/I converter,has been developed.The proposed ADC achieves low-power consumption,high noise immunity,and has a small area,by employing an input-swapped opamp-sharing technique that switches the summing node in an multiplying dig-ital-to-analog converter and a V/I converter with a process,supply voltage,and temperature condition detector.The ADC shows a dif-ferential nonlinearity of less than 0.48LSB,and an integral nonlin-earity of less than 0.95LSB.Also,an signal-to-noise-and-distortion ratio of 56.2dB is measured with a 1MHz input frequency.This has been implemented in a0.18-m CMOS process,and occupies1.60.8mm 2of active area.Index Terms—Opamp-sharing,pipelined analog-to-digital con-verter (ADC),self-calibration,switched bias,V/I converter.I.I NTRODUCTIONMOST portable digital multimedia and wireless commu-nication systems require high-speed,high-resolution,and low-power analog-to-digital converters (ADCs).Accord-ingly,research into the development of low-power ADCs has become extensive over the last few years.The pipelined ADC architecture has been more optimized for high-speed operation and high-resolution than any other types of ADC [1],[2].Fig.1shows the conventional pipelined ADC architecture,consisting of a sample-and-hold amplifier (SHA),which changes the continuous analog input signal to a discrete format as the sampling clock timing,multiplying dig-ital-to-analog converters (MDACs),sub-flash ADCs to generatethe digital codes of low resolutionbits,a digital error correction logic (DCL)for the compensation of the error,a V/I converter to set the bias current of each opamp in the SHA and the MDACs,and other circuits.Manuscript received November 03,2009;revised March 08,2010;accepted May 04,2010.Date of publication June 28,2010;date of current version July 27,2011.This work was supported by the Korea Science and Engineering Foun-dation (KOSEF)Grant funded by the Korea Government (MEST)(R0A-2007-000-20059-0)and fabricated through the MPW of IC Design Education Center (IDEC)supported by the Korea Ministry of Knowledge Economy (MKE).The authors are with the Electrical and Electronics Engineering Department,Korea University,Seoul 136-713,Korea (e-mail:ckim@korea.ac.kr).Color versions of one or more of the figures in this paper are available online at .Digital Object Identifier10.1109/TVLSI.2010.2050915Fig.1.Conventional pipelined ADC architecture.The conventional pipelined ADC consumes a great deal of power due to the large number of opamps used in the SHA and the MDACs.To overcome this problem,lots of techniques have been proposed for pipelined ADCs,which may be categorized into three major methods.The first method uses the open-loop amplifier instead of the closed-loop one in the ADC [3],[4].Since the single stage opamp is implemented for the MDAC,the opamp can achieve a high-bandwidth with low-power consump-tion.However,the digital calibration circuit of a separate device is required in the ADC.Besides,it occupies a large chip area,and tends to reduce the sampling rate.Another method to reduce the power consumption is using the switched-opamp technique [5],[6].By this technique,the opamp is turned off when it is not required for the MDAC.As a result,the total power consump-tion can be reduced by 50%but this not only limits the opera-tional speed due to the turn-on delay of the opamp,but it also reduces the output range of the opamp owing to the on-resis-tance of the switch used to turn the opamp on and off.The final method is the opamp-sharing technique [7],[8].When a certain MDAC works in the sampling mode,the next stage MDAC func-tions as the amplification stage.Since the opamp is only required during the amplification mode of the MDAC,the opamps in the two adjacent stages can be shared.Therefore,the whole ADC implementing the opamp-sharing technique also dissipates very low-power consumption compared to the conventional archi-tecture.However,this method requires additional switches be-tween the input of the opamp used in the MDAC and the sam-1063-8210/$26.00©2010IEEEFig.2.Block diagram to show effects of the current error.pling capacitor.This decreases the sampling rate of the ADC.In addition,the memory effects can occur because the input of the opamp in the MDAC cannot be reset.A detailed explanation is to follow in the next section.Only one V/I converter is required in the general system.The voltage generated from the bandgap reference circuit has a very small error rate,in any circumstance.By using this voltage, the V/I converter generates several reference currents to sup-port the bias of the analog circuits.Although the V/I converter in a system is very simple and small,and only one is required in the whole system,it affects the total power consumption ofthe chip significantly.If the current errorof is gener-ated from the V/I converter,then the bandwidth of the systemhas to be satisfiedwith higher than the original target as amargin,as shown in Fig.2.To guarantee this margin,the systemrequires additional power consumptionof,due to the in-accurate V/I converter.To solve this problem,fuses,or off-chip calibration circuits,have often been used,but these require extra time,cost,and pins for testing.In this paper,a31mW,10-bit,100MS/s,pipelined ADC is described[9].First,a conventional opamp-sharing technique and the proposed input-swapped opamp-sharing technique are explained in Section II,in order to solve the aforementioned problems.The proposed opamp-sharing technique swaps the input nodes of the shared opamp used in the MDACs,known as the summing nodes,with the sampling clock timing.As a result, the proposed ADC can remove the additional switch and reduce the memory effect.Second,the architecture of conventional V/I converters and its drawbacks are covered in Section III.Also, the proposed V/I converter to overcome the disadvantages of the conventional one is explained in the same ing the process,supply voltage and temperature(PVT)detector,de-signed with only digital-gates,the proposed V/I converter de-livers constant currentflow,regardless of the PVT variations.II.O PAMP-S HARING T ECHNIQUE T OPOLOGYA.Conventional Opamp-Sharing TechniqueFig.3shows the operation of the conventional opamp-sharing technique.The opamp used in the MDAC has no correlation to the operation,while the MDAC works for the input voltage sam-pling,known as the sampling mode.The opamp is required in the MDAC only during the amplification mode.Through the opamp operation in the amplification mode,the MDAC am-plifies the difference between the sampled input signal and its quantized analog signal,generated by the sub-flash ADC and the switched-capacitor digital-to-analog converter(DAC).Next,the amplified signal,obtained from the MDAC operation,is sent tothe next stage.Eventually,one opamp can be shared intheFig.3.Conventional opamp-sharing technique.MDACand MDAC since the two MDACs do not require the opamp simultaneously in the pipelined ADC.As a result,the ADC power consumption can be reduced sig-nificantly by using this technique,compared to the conventionalarchitecture.However,additional switches are needed to sep-arate the stages that use the opamp from the rest of the cir-cuit,as shown in Fig.3.These switches degrade the settling be-havior of the MDAC due to their on-resistance.Furthermore,theoutput of each stage is affected by the previous sampling.Sincethe summing node of the opamp in the shred MDAC is neverreset,the sampled voltage,charged to the parasitic capacitances,which exists at the input MOSFETs of the opamp,accumulatesuntil the ADC is completely turned off.In the pipelined ADCwith opamp-sharing technique,this is called the memory effectproblem.Although the digital background calibration circuits cansolve the above problems[10],there is the additional burden ofincreased power consumption and area.Also,a number of clockcycles are needed in order to complete the error calibrationprocess.The techniques to change the summing nodes as theMDAC operation,presented in recent literatures,also alleviatethese errors[11],[12],but the current reusing opamp proposedin[11]is not suitable for low-voltage operations due to the sixstacked transistors that limit the output range of the opamp.The dual-input-dual-output switchable opamp explained in[12]is useful for the two channel architecture,but it dissipatesunnecessary power if it is applied to the single channel becausethe power consumption of opamp is not scaled down along thepipeline stages.B.Proposed Input-Swapped Opamp-Sharing TechniqueThe proposed10-bit100MS/s ADC has a fully differentialarchitecture for high noise immunity,and consists of an SHA forgood performance at high input frequencies,four2.8-bit/stageMDACs,four2.8-bitflash ADCs,a2-bitflash ADC,and so on,Fig.4.Block diagram of the proposedADC.Fig.5.Operation methodology of the proposed input-swapped opamp-sharing technique by changing the summing nodes.as shown in Fig.4.Only three opamps are used in total.The first one is used in the SHA,and the others are shared by the first and fourth stages,and the second and third stages,respectively.There is also the proposed V/I converter with a PVT detector for low current error under the various PVT conditions.Fig.5shows an example of the MDAC operation,which applies the proposed input-swapped opamp-sharing technique.While the second stage operates in the sampling mode,where the opamp is unnecessary,the third stage operates in the amplification mode which uses the opamp.In the next clock phase,the third stage operates in the sampling mode during the amplification mode of the second stage.Therefore,the opamps used in the second and third stages can be shared to reduce the number of opamps implemented in the proposed ADC.The opamps in the first and fourth stages can also be shared.Using the proposed opamp-sharing technique,the summing node of the MDAC switches the IN_A and the IN_B input pairs of the proposed opamp with dual-input whenever the stage uti-lizing the shared opamp is swapped.As a result,the additional switches that are connected to the summing node in series can be removed.Therefore,the proposed ADC achieves high-speed operation with improved settling behavior.Furthermore,since the summing node can be reset,the output of each stage is inde-Fig.6.Detailed operation of the summing nodes changing in the shared opamp. pendent of its previous sample,unlike the conventional opamp-sharing technique[7],[8].Fig.6describes the detailed operation of the proposed opamp-sharing technique.The proposed input-swapped opamp has a dual-input,IN_A pair(M1&M2)and IN_B pair(M3 &M4).When the opamp is used for the second stage,the summing nodes are connected to the gates of M1and M2, while the common-mode voltage is applied to the gates of M3 and M4.Therefore,the opamp operates as a general folded cascode opamp.On the other hand,when the opamp operates for the third stage,a switch(S1)is turned on,and the summing nodes are connected to the gates of M3and M4,while the common-mode voltage is applied to the gates of M1and M2. In this case,the currentflowing through M1and M2is reduced to75%of the original value because the current of M1and M2 is unnecessary for the operation of the opamp in the third stage. If the current does notflow at all for low power consumption during the amplification mode of the third MDAC,then the sampling rate is limited due to the turn-on delays of M1and M2.Therefore,the proposed opamp-sharing technique does not fully turn off the current.Instead,it decreases the current slightly to achieve a speed as high as100MS/s.The biasvoltages(and)for tuning the bias currentsare controlled by the switched-bias power reduction technique [13],as shown in Fig.7.The switched-bias circuit changes the bias voltages through the switch(S2)on/off by the clock phases.Although the gain of the opamp used in the third stage is re-duced due to the on-resistance of S1and the smaller output re-sistance,the opamp in the backward stages does not need to have a high specification.The proposed algorithm is also ap-plied in thefirst and fourth stages.However,thefirst stage re-quires a high gain opamp because its output must have at least 8bit accuracy.Therefore,the gain-boosted opamp,having less power consumption,is implemented for only M5and M6for the shared opamp of thefirst and fourth stages as shown in Fig.8. Also,the channel lengths of the M11and M12are increased to achieve high output resistance of nMOS active load.As a result, a71dB of dc gain is achieved for thefirst stage,even though the unnecessary power is dissipated for the fourthstage.Fig.7.Switched-bias power reductiontechnique.Fig.8.Gate-boosted opamp for thefirst MDAC.Fig.9shows a graph comparing the power consumption over-head with other techniques.In the conventional opamp-sharing technique,the power consumption of the opamp cannot be scaled down as the MDAC goes from thefirst stage to the second stage and from the third stage to the fourth stage.Theparison of the power consumption with other results.opamps shared in the MDACs have to satisfy the specification of the first and third MDACs,respectively,even though the opamps have the power consumption overhead for the second and fourth MDACs.The opamp current reuse technique [11]has less power efficiency compared to the conventional opamp sharing technique because the opamps are shared in the first and fourth stages and the second and third stages.However,the current reuse technique is suitable for high speed sampling,and it reduces the memory effects of opamp sharing.The proposed technique not only has the advantages of the opamp sharing technique with the opamp current reuse,but also reduces un-necessary power consumption,since the switched-bias power reduction technique is implemented with the opamp sharing.As a result,the proposed opamp-sharing technique can reduce the power consumption of the MDAC stages by 8.3%,compared to the previous approach [11].III.M AIN V/I C ONVERTER T OPOLOGYA.Conventional V/I ConvertersFig.10shows the simple V/I converter with the wide swingcascode current mirror.The,generated from the bandgap reference (BGR),controls the gate voltages of M1and M2.Then,a certain amount of current is generated by the transcon-ductanceof M1and M2.Although the V/I converter has a very simple design,using just a few MOSFETs,the gener-ated output current cannot have a constant value under diverse PVT conditions,due to variation of the mobility,the threshold voltage,and the other properties of the MOSFET.In addition,the maximum voltage compliance attheis limitedto if the body effect is neglected.Asthe voltage compliance is increased,the output current becomesmore stable,regardless ofthevariations [14].Fig.11(a)and (b)show the widely used conventional V/I con-verter,which is able to solve the above problems [15].Fig.11(a)supplies a current proportional to the resistance,which has ap-proximately 20%variation,in general.Althoughthe 20%variation is smaller than the current variation of the V/I con-verter with the wide swing cascode current mirror,the whole ADC block consumes 20%more power than necessary,due to the V/I converter,because the ADC needs to operate even with 80%of the normal current in the worst case in order toobtainFig.10.Simple V/I converter with the wide swing cascade currentmirror.Fig.11.(a)V/I converter using a resistor and (b)a switched-capacitor.a higher yield.The switched-capacitor type V/I converter has been proposed in order to reduce the current variation,as shown in Fig.11(b)but the capacitor also hasabout 10%variation of the original capacitance universally.In addition,the switch noises (such as charge injection)directly affect the analog cir-cuit.Meanwhile,both methods have higher voltage complianceatthan that of the V/I converter with the wide swing cascode current mirror.If the gain of the opamp is very large,and the width of M1is big enough,then the voltage compliance is equalto.As a result,the output current of the V/I converter,using the resistor or the switched-capacitor,is almostinsensitive to the variationofif the valueof is very small value.B.Proposed V/I Converters With PVT DetectorFig.12(a)shows the block diagram of the proposed V/I con-verter,which significantly reduces the output current error.The proposed V/I converter consists of a PVT detector,annMOSarraythat operates either in the deep-triode region or the cut off region,selectively,and anopampwhoseinput is fed to a very low DC voltage (0.2V),and theinput is connected by negative feedback.The opamp operating in the subthreshold region is used for the high gain and low-power consumption.In the subthreshold region,thecurrent,,shows an exponential dependenceon,so high-gain opamp can be designed due to largetransconductancewith small-power consumption.This high gain of opamp can overcome the threshold variation and the offset problems.In addition,the opamp has been laid out carefully to minimizeFig.12.(a)Block diagram and (b)concept of proposed V/Iconverter.Fig.13.Block diagram of the PVT detector.its offset.As a result,the source node voltage of M0becomes 0.2V and the proposed V/I converter consumes low power.Throughout the process,the supply voltage and temperature conditions change,PVT detector selects only one nMOS out of 14nMOSs and the selected nMOS goes from the cutoff region to the deep-triode region in order to maintain a relatively constant on-resistance,even under PVT variations.As a result,the cur-rent flowing through M0is also kept belowa 2%currenterror,as shown in Fig.12(b).MOSFETs of the nMOS array have a good property as a resistor because the very low voltage,0.2V ,is appliedto,and an MOSFET with the conditionof stays in the deep-triode region,wheretheis almost linear tothe .Fig.13shows a block diagram of the proposed PVT detector,consisting of the delay cells built with two static CMOS in-verters,positive-edge triggered D-FFs,and AND gates(A1A14).The PVT detector senses the position of the delay cell that delays the input clock for one cycle.As the PVT conditions change,,which is the propagation delay of the delay cell,also varies.Therefore,the position of the clock that is delayed by aphaseofin the delay cells also changes.Fig.14explains the detail operation of the V/I converter.If the phase difference between the output of the nth delaycelland the original clock (CLK)in the PVT detector istheFig.14.Detailed operation of the V/I converter.oneperiod ,then the output of D-FF at thatpointis changed from 0to 1.This point is independent of the input clock (CLK)duty ratio due to using the positive-edge triggeredD-FF.When the output oftheD-FF reaches high,the one input oftheAND gate connected with the static CMOS inverter has a value of 0and the other input has a value of 1.As a result,the output oftheANDgate,,goes high.Only one of the final outputs in the PVT detector becomes“1”and itspositionrepresents the PVT condi-tionat that moment,where presents the PVT status as a mathematical term.Even though another output with the high digital code in the PVT detector is also generated atthephase difference under the worse PVT corner,the output is removed through the control block.As the PVTconditionimproves,the PVT detector generates the output codeof high value at an AND gate further back along the chain.Theselectedsignal,induced by the PVT detector,makes onenMOSin the nMOS array go from the cut off region to the deep-triode region.Each nMOS has a differentchannel-widthand the PVTconditionis alsovarious when the one nMOS is selected by the PVT detector.As a re-sult,the on-resistance of the nMOSarraymaintains aFig.15.Simulation results of the proposed V/I converter.constant value,even under PVT variations because the on-resis-tance of the nMOS array is defined by the combination of thePVTconditionand the width of thenMOS as shownin(1)For example,if the ADC operates in the worst PVT corner,the delay of the delay cell in the PVT detector is longer than thatin normal condition.Therefore,onlythesignal becomes “high,”and M1,which has the longest channel-width in the nMOS array,operates in the deep-triode region,while the other nMOSs operate in the cutoff region.Even though the ADC op-erates in the worst PVT condition,the on-resistance applied to the V/I converter can be maintained since the channel-width of the selected nMOS is the longest.All transistors of the delay cell and nMOS array have the same channel-length for more perfect matching between the on-resistance of nMOS array and the propagation delay of the delay cell.The delay is matched by properly sizing the transistors of nMOS array through the post-layout simulation results.Fig.15showsthepost-layoutsimulationresultsoftheproposed V/I converter in the time domain where 108samples were chosen at random among the various PVT conditions (SS,TT,FF process corners,1.62V 1.98V supply voltages,and 25C 100C temperatures),and the target current is fixed to100 A.When the 100MHz clock is applied to the PVT detector,the target output current of the proposed V/I converter is generated after only one clock cycle.The output current is varied from 98to 102A under the aforementioned PVT conditions.In conclusion,the proposed V/I converterachieves 2%current error under the several PVT corners (SS,TT,FFprocessFig.16.Die photo of the proposedADC.Fig.17.Measured DNL and INL.corners,1.62V 1.98V supply voltages,and 25C 100C temperatures)which represents a significant improvement over the conventional V/I converters having a maximum error of about 20%.Therefore,6mW (which is about 20%of the total ADC power consumption)can be saved using 0.9mW consumed by the PVT detector.In addition,the proposed V/Iconverter has large voltage compliance attheas well.The maximum voltage compliance is equal to 1.6V ,whichis(0.2V).As a result,the output currentcan be kept constant(100A)even ifthe is decreased by 0.2V [14].The error of the proposed V/I converter can be reduced by increasing the resolution of PVT detector and the number of nMOS array in the V/I converter.IV .E XPERIMENTAL R ESULTSThe proposed ADC has been implemented in a0.18-m CMOS process,and it occupies an area of1.60.8mm1.28mm ,excluding the input/output (I/O)buffers,as shown in Fig.16.The ADC consumes 31mW at 100MS/swith a 1.8V supply and has1input range with a 0.9V common-mode voltage.The arbitrary waveform generator used in this test as the sine-wave signal source has a high vertical resolution,but its phase resolution is low.Therefore,it is difficult to synchronize the sine-wave input signal and the sampling clock exactly when a high input frequency is applied to the chip.Consequently,the skirting around the signal tone is generated at the input fre-quency over 10MHz and it degrades the fast Fourier transform (FFT)performance of the proposed ADC.Fig.17shows the measured static characteristics,such as the differential nonlinearity (DNL)and integral nonlinearity (INL).TABLE IP ERFORMANCE C OMPARISONS OF THE P ROPOSEDADCFig.18.Measured FFT spectrums with a 1and 10MHz input frequency.The measured DNL and INLare LSBandLSB,respectively.Also,the dynamic perfor-mance of the proposed ADC is shown in Fig.18by using an FFT spectrum analysis.This has a 56.2dB signal-to-noise-and-dis-tortion ratio (SNDR),and a 70.4dBc spurious-free dynamic range (SFDR)with a 1MHz input frequency.Also,when the input signal of 10MHz is applied,SNDR of the proposed ADC is 54.0dB and SFDR is 65.0dBc.Fig.19summarizes the measured SNDR and SFDR as a function of the input frequency when sampled at a frequency of 100MHz.Although theinputFig.19.Measured SNDR and SFDR versus input frequency.frequency is increased to 10MHz,the effective number of bits (ENOB)is maintained over 8.5bits.The dynamic performance of the proposed ADC with 1MHz input frequency is degraded slightly as the sampling frequency is higher than 100MHz,as shown in Fig.20.The performance of the proposed ADC is compared to that of other circuits using the opamp sharing technique,in Table I.The proposed ADC has a 0.76pJ/conversion-step for a figure of merit (FOM)when the input signal with the 10MHz frequency is applied.The FOM is definedas(2)Fig.20.Measured SNDR and SFDR versus sampling frequency.where is the powerconsumption,is the sampling fre-quency,and SNDR is measured at the input frequency of0.1.In conclusion,the proposed ADC has a high-power efficiency compared to other pipelined ADCs employing the opamp-sharing technique.V .C ONCLUSIONA 31mW,10-bit,100MS/s CMOS pipelined ADC,using an input-swapped opamp-sharing technique,and a V/I converter with a PVT detector has been described.The proposed ADC achieves high-speed operation and low-power consumption owing to the switched-bias power reduction technique and opamp-sharing technique,without the need for additional switches.Also,the proposed method reduces the memory ef-fect,which occurs in the opamp sharing,because the summing nodes of the MDAC are reset by swapping them in the MDAC operation.Furthermore,the proposed V/I converter self-calibrated by an on-chip PVT detector has a small current error that stays withinonly 2%.Hence,the power consumption of the pro-posed ADC can be significantly reduced,with negligible over-head,by having a smaller current margin,considering the worst case,without requiring additional test time,cost,and pins.R EFERENCES[1]B.-S.Song,S.-H.Lee,and M.F.Tompsett,“A 10-bit 15-MHz CMOSrecycling two-step A/D converter,”IEEE J.Solid-State Circuits ,vol.25,no.6,pp.1328–1338,Dec.1990.[2]S.H.Lewis,H.S.Fetterman,G.F.Gross,J.R.Ramachandran,and T.R.Viswanathan,“A 10-b 20-Msample/s analog-to digital converter,”IEEE J.Solid-State Circuits ,vol.27,no.3,pp.351–358,Mar.1992.[3]B.Murmann and B.E.Boser,“A 12-bit 75-MS/s pipelined ADC usingopen-loop residue amplification,”IEEE J.Solid-State Circuits ,vol.38,no.12,pp.2040–2050,Dec.2003.[4]E.Iroaga and B.Murmann,“A 12-bit 75-MS/s pipelined ADC usingincomplete settling,”IEEE J.Solid-State Circuits ,vol.42,no.4,pp.748–756,Apr.2007.[5]M.Waltari and K.A.I.Halonen,“1-V 9-bit pipelined switched-opampADC,”IEEE J.Solid-State Circuits ,vol.36,no.1,pp.129–134,Jan.2001.[6]H.-C.Kim,D.-K.Jung,and W.Kim,“A partially switched-opamptechnique for high speed low power pipelined,”IEEE Trans.Circuits Syst.I,Reg.Papers ,vol.53,no.4,pp.795–801,Apr.2006.[7]K.Nagaraj,H.Fetterman,J.Anidjar,S.Lewis,and R.Renninger,“A250-mW,8-b,52-Msamples/s parallel-pipelined A/D converter with re-duced the number of amplifiers,”IEEE J.Solid-State Circuits ,vol.32,no.3,pp.312–320,Mar.1997.[8]B.-M.Min,P.Kim,F.W.Bowman,D.M.Boisvert,and A.J.Aude,“A69-mW 10-bit 80-MSample/s pipelined CMOS ADC,”IEEE J.Solid-State Circuits ,vol.38,no.12,pp.2031–2038,Dec.2003.[9]M.-Y.Kim,J.Kim,T.Lee,and C.Kim,“10-bit 100MS/s CMOSpipelined A/D converter with 0.59pJ/conversion-step,”in Proc.IEEE Asian Solid-State Circuits Conf.,Nov.2008,pp.65–68.[10]J.P.Keane,P.J.Hurst,and S.H.Lewis,“Digital background cali-bration for memory effects in pipelined analog-to-digital converters,”IEEE Trans.Circuits Syst.I,Reg.Papers ,vol.53,no.3,pp.511–525,Mar.2006.[11]S.-T.Ryu and B.-S.Song,“A 10-bit 50-MHz pipelined ADC withopamp current reuse,”IEEE J.Solid-State Circuits ,vol.42,no.3,pp.475–485,Mar.2007.[12]P.Y.Wu,V.S.-L.Cheung,and H.C.Luong,“A 1-V 100-MS/s 8-bitCMOS switched-opamp pipelined ADC using loading-free architec-ture,”IEEE J.Solid-State Circuits ,vol.42,no.4,pp.730–738,Apr.2007.[13]Y.-J.Cho,D.-H.Sa,Y.-W.Kim,K.-H.Lee,H.-C.Choi,S.-H.Lee,Y.-D.Jeon,S.-C.Lee,and J.-K.Kwon,“A 10b 25MS.s 4.8mW 0.13um CMOS ADC for digital multimedia broadcasting,”in Proc.IEEE Custom Integr.Circuits Conf.,Sep.2006,pp.497–500.[14]M.Ghovanloo and K.Najafi,“A compact large voltage-compliancehigh output-impedance programmable current source for implantable microstimulators,”IEEE Trans.Biomed.Eng.,vol.52,no.1,pp.97–105,Jan.2005.[15]B.Razavi ,Design of Analog CMOS Integrated Circuits .New York:McGraw-Hill,2001.[16]J.Li,G.Manganaro,M.Copurcy,B.-M.Min,L.Tomasi,A.Alam,andR.Taylor,“A 10b 170MS/s CMOS pipelined ADC featuring 84dB SFDR without calibration,”in IEEE Symp.VLSI Circuits Dig.Techn.Papers ,Jun.2006,pp.226–227.[17]K.Chandrashekar and B.Bakkaloglu,“A 10b 50MS/s opamp-sharingpipeline A/D with current-reuse OTAs,”in Proc.IEEE Custom Integr.Circuits Conf.,Sep.2009,pp.263–266.Moo-Young Kim (S’04)received the B.S.degree in electrical and computer engineering from Korea Uni-versity,Seoul,Korea,in 2004,where he is currently pursuing the Ph.D.degree in the area of integrated circuits and systems.In 2008,he worked as a Research Student with the University of California,Los Angeles,where he re-searched and developed a 50Msps pipelined ADC.His research interests include low-power analog-to-digital converter for display applications.Mr.Kim was a recipient of the 29th IEEE SeoulSection Student Paper Contest Award (2005),the IEEE Solid-State Circuits So-ciety Seoul Chapter Best Student Paper Award (2008),the 13th Asia and South Pacific Design Automation Conference Best Design Award (2008),the 4th Sam-sung Electromechanics “Inside Edge”International Thesis Competition Bronze Award (2008),and the 1st IDEC International Conference Paper Award(2008).Jinwoo Kim (S’06–M’08)received the B.S.and M.S.degrees in electrical engineering from Korea University,Seoul,Korea,in 2006and 2008,respec-tively.In 2008,he joined Samsung Electronics Company,Kyunggi-Do,Korea,where he has been working on analog integrated circuits,especially CMOS image sensor design.His research interests include ADC and low-power circuit design.。
NPC三电平逆变器及其中点电位平衡的研究
NPC三电平逆变器及其中点电位平衡的研究一、本文概述Overview of this article随着电力电子技术的快速发展和可再生能源的大规模应用,电力转换和电能质量控制成为了电气工程领域的研究热点。
其中,三电平逆变器作为一种高效的电能转换装置,在风力发电、太阳能发电、电机驱动等领域得到了广泛应用。
然而,三电平逆变器在运行过程中,中点电位平衡问题一直是影响其性能稳定性的关键因素。
因此,对NPC(Neutral Point Clamped)三电平逆变器及其中点电位平衡的研究具有重要的理论价值和实际意义。
With the rapid development of power electronics technology and the large-scale application of renewable energy, power conversion and power quality control have become research hotspots in the field of electrical engineering. Among them, three-level inverters, as an efficient energy conversion device, have been widely used in fields such as wind power generation, solar power generation, and motor drive. However, the issue of midpoint potential balance has always been a keyfactor affecting the performance stability of three-level inverters during operation. Therefore, the study of NPC (Neutral Point Clamped) three-level inverters and their midpoint potential balance has important theoretical value and practical significance.本文旨在深入探讨NPC三电平逆变器的工作原理、中点电位平衡控制策略以及实际应用中的关键技术问题。
NI 9213 高密度温度计模块说明书
DAT ASHEETNI 921316 TC, ±78 mV, 24 Bit, 75 S/s Aggregate•Spring-terminal connectivity •50 Hz/60 Hz noise rejection•Up to 0.02 °C measurement sensitivity•250 Vrms, CAT II, channel-to-earth isolationThe NI 9213 is a high-density thermocouple module for CompactDAQ and CompactRIO chassis. Designed for higher-channel-count systems, the NI 9213 adds thermocouples to mixed-signal test systems without taking up too many slots.Kit ContentsAccessories •• NI 9213NI 9213 Getting Started Guide• NI 9940 Backshell Connector KitNI C Series OverviewNI provides more than 100 C Series modules for measurement, control, and communication applications. C Series modules can connect to any sensor or bus and allow for high-accuracy measurements that meet the demands of advanced data acquisition and control applications.•Measurement-specific signal conditioning that connects to an array of sensors and signals •Isolation options such as bank-to-bank, channel-to-channel, and channel-to-earth ground •-40 °C to 70 °C temperature range to meet a variety of application and environmentalneeds •Hot-swappable The majority of C Series modules are supported in both CompactRIO and CompactDAQ platforms and you can move modules from one platform to the other with no modification.2 | | NI 9213 DatasheetCompactRIOCompactRIO combines an open-embedded architecturewith small size, extreme ruggedness, and C Seriesmodules in a platform powered by the NI LabVIEWreconfigurable I/O (RIO) architecture. Each systemcontains an FPGA for custom timing, triggering, andprocessing with a wide array of available modular I/O tomeet any embedded application requirement. CompactDAQCompactDAQ is a portable, rugged data acquisition platformthat integrates connectivity, data acquisition, and signalconditioning into modular I/O for directly interfacing to anysensor or signal. Using CompactDAQ with LabVIEW, youcan easily customize how you acquire, analyze, visualize,and manage your measurement data.SoftwareLabVIEW Professional Development System for Windows•Use advanced software tools for large project development•Generate code automatically using DAQ Assistant and InstrumentI/O Assistant•Use advanced measurement analysis and digital signal processing•Take advantage of open connectivity with DLLs, ActiveX,and .NET objects•Build DLLs, executables, and MSI installersNI LabVIEW FPGA Module•Design FPGA applications for NI RIO hardware•Program with the same graphical environment used for desktop andreal-time applications•Execute control algorithms with loop rates up to 300 MHz•Implement custom timing and triggering logic, digital protocols, andDSP algorithms•Incorporate existing HDL code and third-party IP including Xilinx IPgenerator functions•Purchase as part of the LabVIEW Embedded Control and MonitoringSuiteNI 9213 Datasheet| © National Instruments| 3NI LabVIEW Real-Time Module•Design deterministic real-time applications with LabVIEWgraphical programming•Download to dedicated NI or third-party hardware for reliableexecution and a wide selection of I/O•Take advantage of built-in PID control, signal processing, andanalysis functions•Automatically take advantage of multicore CPUs or setprocessor affinity manually•Take advantage of real-time OS, development and debuggingsupport, and board support•Purchase individually or as part of a LabVIEW suiteNI 9213 CircuitryEach channel passes through a differential filter and then is multiplexed and sampled by a 24-bit analog-to-digital converter (ADC). The channels share a common ground, COM, that is isolated from other modules in the system.Figure 1. Input Circuitry for One Channel of the NI 9213Common-Mode VoltageThe NI 9213 common-mode range is the maximum voltage between any channel and COM. If COM is not connected, then the common-mode voltage range is the maximum voltage between any two channels. The NI 9213 measures the common-mode voltage level of each channel and returns a warning in the software if the signal is outside the common-mode voltage range.Open Thermocouple DetectionEach channel has an open thermocouple detection (OTD) circuit, which consists of a current source between the TC+ and TC- terminals. If an open thermocouple is connected to the channel, the current source forces a full-scale voltage across the terminals.4| | NI 9213 DatasheetInput ImpedanceEach channel has a resistor that produces an input impedance between the TC and COM terminals. The gain and offset errors resulting from the source impedance of connected thermocouples are negligible for most applications. Thermocouples with a higher lead resistance can introduce more significant errors.Thermocouple Measurement Accuracy Thermocouple measurement errors depend partly on the following factors:•the type of thermocouple•the accuracy of the thermocouple•the temperature that you are measuring•the resistance of the thermocouple wires•the cold-junction temperatureFor the best accuracy performance, follow these guidelines:•Set up the NI 9213 according to the getting started guide on /manuals to minimize thermal gradients across the NI 9213 terminals.•Use the autozero channel to compensate for offset errors.Cold-Junction AccuracyHeat dissipated by adjacent C Series modules or nearby heat sources can cause errors in thermocouple measurements by heating the NI 9213 terminals to a different temperature than the cold-junction compensation sensor. Thermal gradient across the terminals can cause the terminals of different NI 9213 channels to be at different temperatures, which creates accuracy errors and affects the relative accuracy between channels.The temperature measurement accuracy specifications include errors caused by the thermal gradient across the NI 9213 terminals for configurations with the NI 9213 terminals facing forward or upward.Autozero ChannelThe NI 9213 has an internal autozero channel, which can be subtracted from each thermocouple reading to compensate for offset errors. Use of the autozero channel is optional, however the NI 9213 specifications assume that autozero is applied to every sample. Refer to the documentation for the software that you are using with the NI 9213 for information about using the autozero channel.Timing ModesThe NI 9213 supports high-resolution and high-speed timing modes. High-resolution timing mode optimizes accuracy and noise and rejects power line frequencies. High-speed timing mode optimizes sample rate and signal bandwidth.NI 9213 Datasheet| © National Instruments| 5NI 9213 SpecificationsThe following specifications are typical for the range -40 °C to 70 °C unless otherwise noted.Caution Do not operate the NI 9213 in a manner not specified in this document.Product misuse can result in a hazard. You can compromise the safety protectionbuilt into the product if the product is damaged in any way. If the product isdamaged, return it to NI for repair.Warm-up time15 minutesInput CharacteristicsNumber of channels16 thermocouple channels, 1 internal autozerochannel, 1 internal cold-junction compensationchannelADC resolution24 bitsType of ADC Delta-SigmaSampling mode ScannedV oltage measurement range±78.125 mVTemperature measurement ranges Works over temperature ranges defined byNIST (J, K, T, E, N, B, R, S thermocoupletypes)Common-mode voltage rangeChannel-to-COM±1.2 V minimumCOM-to-earth ground±250 V1If you are using fewer than all channels, the sample rate might be faster. The maximum samplerate = 1/(Conversion Time x Number of Channels), or 100 S/s, whichever is smaller.Sampling faster than the maximum sample rate may result in the degradation of accuracy.2Including the autozero and cold-junction channels.6| | NI 9213 DatasheetCommon-mode rejection ratioHigh-resolution mode (at DC and 50 Hz to 60 Hz)Channel-to-COM100 dBCOM-to-earth ground>170 dBHigh-speed mode (at 0 Hz to 60 Hz)Channel-to-COM70 dBCOM-to-earth ground>150 dBInput bandwidthHigh-resolution mode14.4 HzHigh-speed mode78 Hz60 dBHigh-resolution noise rejection (at 50 Hz and60 Hz)Overvoltage protection±30 V between any two inputsDifferential input impedance78 MΩInput current50 nAInput noiseHigh-resolution mode200 nVrmsHigh-speed mode7 μVrmsGain errorHigh-resolution modeat 25 °C0.03% typicalat -40 °C to 70 °C0.07% typical, 0.15% maximum High-speed modeat 25 °C0.04% typicalat -40 °C to 70 °C0.08% typical, 0.16% maximumOffset errorHigh-resolution mode 4 μV typical, 6 μV maximumHigh-speed mode14 μV typical, 17 μV maximumOffset error from source impedance Add 0.05 μV per Ω, when source impedance>50 ΩNI 9213 Datasheet| © National Instruments| 7Cold-junction compensation accuracy0 °C to 70 °C0.8 °C typical, 1.7 °C maximum-40 °C to 70 °C 1.1 °C typical, 2.1 °C maximumMTBF852,407 hours at 25 °C;Bellcore Issue 2, Method 1,Case 3, LimitedPart Stress Method Temperature Measurement AccuracyMeasurement sensitivity3High-resolution modeTypes J, K, T, E, N<0.02 °CTypes B, R, S<0.15 °CHigh-speed modeTypes J, K, T, E<0.25 °CType N<0.35 °CType B<1.2 °CTypes R, S<2.8 °CThe following figures show the errors for each thermocouple type when connected to theNI 9213 with the autozero channel on. The figures display the maximum errors over a full temperature range and typical errors at room temperature. The figures account for gain errors, offset errors, differential and integral nonlinearity, quantization errors, noise errors, 50 Ω lead wire resistance, and cold-junction compensation errors. The figures do not account for the accuracy of the thermocouple itself.3Measurement sensitivity represents the smallest change in a temperature that a sensor can detect. It is a function of noise. The values assume the full measurement range of the standard thermocouple sensor according to ASTM E230-87.8| | NI 9213 DatasheetMeasured Temperature (°C )M e a s u r e m e n t E r r o r (°C )01342–2005030055080010501300Max (High speed), –40 to 70 °C Max (High res), –40 to 70 °CTyp (High res), room tempTyp (High speed), room temp Figure 3. Thermocouple T ype K ErrorsMeasured Temperature (°C )M e a s u r e m e n t E r r o r (°C )014532–200200400600800100012001400Max (High speed), –40 to 70 °C Max (High res), –40 to 70 °CTyp (High res), room tempTyp (High speed), room temp NI 9213 Datasheet | © National Instruments | 9Measured Temperature (°C)M e a s u r e m e n t E r r o r (°C )Max (High speed), –40 to 70 °C Max (High res), –40 to 70 °CTyp (High res), room tempTyp (High speed), room temp 0132–2002004006008001000Figure 5. Thermocouple T ype B ErrorsMeasured Temperature (°C )M e a s u r e m e n t E r r o r (°C )026420040060080010001200140016001800Max (High speed), –40 to 70 °C Max (High res), –40 to 70 °CTyp (High res), room tempTyp (High speed), room temp Figure 6. Thermocouple T ypes R and S ErrorsMeasured Temperature (°C )M e a s u r e m e n t E r r o r (°C )0264–200020040060080010001200140016001800Max (High speed), –40 to 70 °C Max (High res), –40 to 70 °CTyp (High res), room tempTyp (High speed), room temp 10 | | NI 9213 DatasheetPower RequirementsPower consumption from chassisActive mode490 mW maximumSleep mode25 μW maximumThermal dissipation (at 70 °C)Active mode840 mW maximumSleep mode710 mW maximumPhysical CharacteristicsGauge0.08 mm to 1.0 mm (28 AWG to 18 AWG)copper conductor wireWire strip length7 mm (0.28 in.) of insulation stripped from theendTemperature rating90 °C minimumWires per spring terminal One wire per spring terminalConnector securementSecurement type Screw flanges providedTorque for screw flanges0.2 N · m (1.80 lb · in.)Weight159 g (5.6 oz)Safety VoltagesConnect only voltages that are within the following limits:Between any two terminals±30 V maximumIsolationChannel-to-channel NoneChannel-to-earth groundContinuous250 Vrms, Measurement Category IIWithstand2,300 Vrms, verified by a 5 s dielectricwithstand testNI 9213 Datasheet| © National Instruments| 11Measurement Category II is for measurements performed on circuits directly connected to the electrical distribution system. This category refers to local-level electrical distribution, such as that provided by a standard wall outlet, for example, 115 V for U.S. or 230 V for Europe.Caution Do not connect the NI 9213 to signals or use for measurements withinMeasurement Categories III or IV.Hazardous LocationsU.S. (UL)Class I, Division 2, Groups A, B, C, D, T4;Class I, Zone 2, AEx nA IIC T4Canada (C-UL)Class I, Division 2, Groups A, B, C, D, T4;Class I, Zone 2, Ex nA IIC T4Europe (ATEX) and International (IECEx)Ex nA IIC T4 GcSafety and Hazardous Locations StandardsThis product is designed to meet the requirements of the following electrical equipment safety standards for measurement, control, and laboratory use:•IEC 61010-1, EN 61010-1•UL 61010-1, CSA 61010-1•EN 60079-0:2012, EN 60079-15:2010•IEC 60079-0: Ed 6, IEC 60079-15; Ed 4•UL 60079-0; Ed 5, UL 60079-15; Ed 3•CSA 60079-0:2011, CSA 60079-15:2012Note For UL and other safety certifications, refer to the product label or the OnlineProduct Certification section.Electromagnetic CompatibilityThis product meets the requirements of the following EMC standards for sensitive electrical equipment for measurement, control, and laboratory use:•EN 61326 (IEC 61326): Class A emissions; Industrial immunity•EN 55011 (CISPR 11): Group 1, Class A emissions•AS/NZS CISPR 11: Group 1, Class A emissions•FCC 47 CFR Part 15B: Class A emissions•ICES-001: Class A emissionsNote For the standards applied to assess the EMC of this product, refer to theOnline Product Certification section.Note For EMC compliance, operate this device with double-shielded cables.12| | NI 9213 DatasheetCE ComplianceThis product meets the essential requirements of applicable European Directives, as follows:•2014/35/EU; Low-V oltage Directive (safety)•2014/30/EU; Electromagnetic Compatibility Directive (EMC)•94/9/EC; Potentially Explosive Atmospheres (ATEX)Online Product CertificationRefer to the product Declaration of Conformity (DoC) for additional regulatory compliance information. To obtain product certifications and the DoC for this product, visit / certification, search by model number or product line, and click the appropriate link in the Certification column.Shock and VibrationTo meet these specifications, you must panel mount the system.Operating vibrationRandom (IEC 60068-2-64) 5 g rms, 10 Hz to 500 HzSinusoidal (IEC 60068-2-6) 5 g, 10 Hz to 500 HzOperating shock (IEC 60068-2-27)30 g, 11 ms half sine; 50 g, 3 ms half sine;18 shocks at 6 orientations EnvironmentalRefer to the manual for the chassis you are using for more information about meeting these specifications.-40 °C to 70 °COperating temperature(IEC 60068-2-1, IEC 60068-2-2)-40 °C to 85 °CStorage temperature(IEC 60068-2-1, IEC 60068-2-2)Ingress protection IP40Operating humidity (IEC 60068-2-78)10% RH to 90% RH, noncondensing Storage humidity (IEC 60068-2-78)5% RH to 95% RH, noncondensing Pollution Degree2Maximum altitude2,000 mIndoor use only.NI 9213 Datasheet| © National Instruments| 13Environmental ManagementNI is committed to designing and manufacturing products in an environmentally responsible manner. NI recognizes that eliminating certain hazardous substances from our products is beneficial to the environment and to NI customers.For additional environmental information, refer to the Minimize Our Environmental Impact web page at /environment. This page contains the environmental regulations and directives with which NI complies, as well as other environmental information not included in this document.Waste Electrical and Electronic Equipment (WEEE) EU Customers At the end of the product life cycle, all NI products must bedisposed of according to local laws and regulations. For more information abouthow to recycle NI products in your region, visit /environment/weee.电子信息产品污染控制管理办法(中国RoHS)中国客户National Instruments符合中国电子信息产品中限制使用某些有害物质指令(RoHS)。
coordinate-invariant algorithms for robot dynamics
M4.This gives us afinal color(W4.2,00000)which corresponds to a part completely processed.Now the part can be unloaded by robot R2or R3from M4and eventually leaves the cell.It is left to the reader to trace the token until it is unloaded from the cell.V.C ONCLUSIONIn this paper we have introduced a new architecture to model a large class offlexible manufacturing systems using colored Petri nets. Advantages of this new architecture are:1)cell model and part process information are separated,thuseliminating the need to update the CPN model every time there is a change in the part types manufactured in the system;2)alternate sequencing of operations is allowed during processing;3)machine assignments for operations are made dynamicallyduring processing.It is important to note that the model of the FMC created captures all possible operation sequences in the cell.Therefore,the structural analysis of the Petri net for static deadlock prevention policies is compromised.However,the important issue of deadlock can be addressed using deadlock avoidance policies as in[5].R EFERENCES[1]J.Ezpeleta and J.M.Colom,“Automatic synthesis of colored Petrinets for the control of FMS,”IEEE Trans.Robot.Automat.,vol.13,pp.327–337,June1997.[2]M.D.Byrne and P.Chutima,“Real time operational control of an FMSwith full routingflexibility,”Int.J.Prod.Econ.,vol.51,pp.109–113, 1997.[3]R.David and H.Alla,Petri Nets and Grafcet.Englewood Cliffs,NJ:Prentice-Hall,1992.[4] A. A.Desrochers and R.Y.Al-Jaar,Application of Petri Nets inManufacturing Systems.Piscataway,NJ:IEEE Press,1995.[5]N.Viswanadham,Y.Narahari,and T.L.Johnson,“Deadlock preventionand deadlock avoidance inflexible manufacturing systems using Petri net models,”IEEE Trans.Robot.Automat.,vol.6,pp.713–723,Dec.1990.Coordinate-Invariant Algorithms for Robot DynamicsScott R.Ploen and Frank C.ParkAbstract—In this article,we present,using methods from the theory of Lie groups and Lie algebras,a coordinate-invariant formulation of the dynamics of open kinematic chains.Wefirst reformulate the recursive dynamics algorithm originally given in[8]for open chains in terms of standard linear operators on the Lie algebra of the Special Euclidean ing straight forward algebraic manipulations,we then recast the resulting algorithm into a set of closed-form dynamic equations; this transformation allows one to move easily between O(n)recursive algorithms advantageous for computation,and closed-form equations advantageous for symbolic manipulation and analysis.The transforma-tion also illuminates how the choice of link reference frames affects the computational structure.We then reformulate Featherstone’s articulated body inertia algorithm[3]using this same geometric framework,and rederive Rodriguez et al.’s[11]–[13]square factorization of the mass matrix and its inverse.An efficient O(n)recursive algorithm for forward dynamics is also extracted from the inverse factorization.The resulting equations lead to a succinct high-level description of robot dynamics in both joint and operational space coordinates that minimizes symbolic complexity without sacrificing computational efficiency,and provides the basis for a dynamics formulation that does not require link reference frames in the description of the forward kinematics.Index Terms—Lie algebra,Lie group,multibody dynamics,robot dynamics.I.I NTRODUCTIONFrom the point of view of classical mechanics,deriving the equations of motion of a rigid-link manipulator is usually regarded as a straightforward procedure:once a suitable set of generalized coordinates and reference frames have been chosen,what remains is to apply either Lagrange’s or Newton and Euler’s equations to obtain the differential equations of motion.Anyone who has derived the dynamics of an actual manipulator,however,will have experienced firsthand the enormous complexity of the ensuing equations.Past research in robot dynamics has been driven primarily by a desire to reduce this complexity—there is now extensive literature on algorithms for efficiently computing the dynamics,usually in a recursive fashion(see,e.g.,[1],[3],[5]).Aside from computational considerations,however,many ad-vanced applications,particularly in robot control and planning,re-quire an explicit closed-form representation of the dynamic equations (e.g.,[6]).Recent applications suggest that a useful dynamics formu-lation should maintain the balance between computational efficiency and the ease with which it can be manipulated at a high level. Further,it should beflexible enough to admit a degree of coordinate independence,viz.,a given problem should not be bound to any Manuscript received April2,1996;revised March24,1997.This paper was recommended for publication by Associate Editor Y.F.Zheng and Editor A.Goldenberg upon evaluation of the reviewers’comments.This work was supported by the National Science Foundation under Award CMS-9403019,a U.S.Department of Education GAANN Fellowship,the Engineering Research Center for Advanced Control and Instrumentation,and the Institute for Advanced Machinery Design,Seoul National University.S.R.Ploen is currently with the Guidance and Control Analysis Group, Jet Propulsion Laboratory,California Institute of Technology,Pasadena,CA 91009USA(e-mail:sploen@).F.C.Park is with the School of Mechanical and Aerospace Engineering, Seoul National University,Seoul,Korea(e-mail:fcp@plaza.snu.ac.kr). Publisher Item Identifier S1042-296X(99)09534-8.1042–296X/99$10.00©1999IEEEspecific choice of reference frames and/or local coordinates to carry out the kinematic and dynamic analysis.Motivated in part by these considerations,Featherstone[3]has developed a recursive dynamics formulation using the machinery of classical screw theory,while Rodriguez,Jain,and Kreutz-Delgado have developed the spatial operator algebra formulation of dynamics ([11]–[13])by identifying structural similarities in the dynamic equations for open chains and the equations for discrete-time Kalman filtering.Khatib[4]has also proposed the operational space paradigm as a means of managing the complexity in dynamics-based control and planning tasks.In Park,Bobrow,and Ploen[8],the dynamic equations for an open chain manipulator are formulated in both recursive Newton–Euler and Lagrangian form using methods from the theory of Lie groups and Lie algebras.This article develops a general coordinate-invariant mathematical framework for rigid-body dynamics,based on the same set of geometric toolsfirst examined in[8],from which a complete range of dynamics algorithms(including those mentioned above)can be formulated in a uniform and mathematically consistent manner. The main elements of our geometric framework are introduced by reformulating the recursive dynamics algorithm for open chains in terms of standard linear operators on the Lie algebra of the Special Euclidean ing simple algebraic manipulations,the resulting algorithm is then recast into a set of closed-form dynamic equations; this transformation allows one to move easily between O(n)recursive algorithms advantageous for computation,and closed-form equations advantageous for symbolic manipulation and analysis.Moreover,we explicitly show the invariance of the formulation to choice of link reference frames—the effect of choice of reference frames on the structure of the recursive computations now becomes transparent. As a demonstration of the generality andflexibility of our geo-metric language for robot dynamics,we reformulate Featherstone’s articulated body inertia algorithm[3]within our geometric frame-work,and re-derive Rodriguez et al.’s[11]square factorization of the mass matrix and its inverse without invoking results from estimation theory.Along the same lines,we also re-derive their spatial operator algebra-based O(n)recursive forward dynamics algorithm, this time expressed entirely in terms of coordinate-invariant Lie algebraic operators.The operational space control formulation is also reformulated from the geometric perspective and is discussed in[10]. One of the difficulties with traditional dynamics formulations is the use of what are generally ad hoc definitions,conventions,and notation,in particular the derivation of specialized formulas which more often than not turn out to be standard results from linear algebra. Our geometric framework allows one to tap into the vast body of standard and well-known results from linear algebra and Lie theory. For example,one of the important main results of the spatial operator algebra formulation,the square factorization of the mass matrix and its inverse,turns out to be a straightforward consequence of the Matrix Inversion Lemma(or the Sherman–Morrison–Woodbury Formula).Above all,the geometric framework provides a common and unified mathematical language in which to express the ideas introduced by Silver et al.and other researchers in a concise, coordinate-invariant manner,as well as a powerful means of for-mulating dynamics algorithms for a wide range of applications.II.T HE E QUATIONS OF M OTIONA.Recursive Newton–Euler AlgorithmDue to space limitations,the reader should consult[7]–[9]for a detailed discussion of the special Euclidean group SE(3),its corresponding Lie algebra se(3),and their associated adjoint repre-sentations.We now briefly review the recursive formulation of robot dynamicsas given in[8].The idea behind the recursive formulation is a two-step iterative process where in the outward iteration the kinematics ofeach link are propagated from base to tip,and in the inward iterationthe kinetics are propagated from tip to base.We make the followingdefinitions(here all quantities are expressed in the corresponding linkframe coordinates).Let V i2<621be the generalized velocity of link i;F i2<621the total generalized force transmitted from link i01 to link i through joint i with itsfirst three components correspondingto the moment vector,and i the applied torque at joint i:Also,let f i01;i=M i e S denote the position and orientation of the link i frame relative to the link i01frame with M i2SE(3)and S i=(!i;0)2se(3):Here!i denotes a unit vector along the axis of rotation of joint i:(In this article we assume that single degree-of-freedom joints—revolute or prismatic joints—connect the links in the multibody chain.)Further,J i2<626is defined asJ i=where m i is the mass of link i;r i is the vector in link i coordinates from the origin of the link i frame to the center of mass of link i;I i is the inertia tensor of link i about the center of mass,and I323 denotes the323identity matrix.The recursive equations can now be expressed in terms of our geometric definitions and notation as follows.1)InitializationGiven:V0;_V0;F n+1:2)Forward recursion:for i=1to n dof i01;i=M i e S(1)V i=Adf(_V i01)0ad S Adf(J i V i)(4) i=S T i F i:(5)Here V0and_V0denote the generalized velocity and acceleration of the base respectively,and F n+1denotes the force acting at the tip of the open chain.In the sequel we will assume that V0=0 and that_V0=(0;g)where g2<301denotes the gravity vector in appropriate units and direction.B.Global Matrix Representation of the Newton-Euler AlgorithmBy expanding the individual equations(2)-(5)for i=1;2;111;n it can be shown that the recursive Newton–Euler algorithm admits the following global matrix representation:V=GS_q+GP0V0(6)_V=GS q+GadS_q0V+Gad S_q P0V0+GP0_V0(7) F=G T J_V+G T ad3V JV+G T P T t F n+1(8)=S T F(9)whereV =column [V 1;V 2;111;V n ]2<6n 21F =column [F 1;F 2;111;F n ]2<6n 21_q =column [_q 1;_q 2;111;_q n ]2<n 21 =column [ 1; 2;111; n ]2<n 21P 0=column [Adf]2<6n 26S =diag [S 1;S 2;111;S n ]2<6n 2n J =diag [J 1;J 2;111;J n ]2<6n 26n ad S _q =diag [0ad S;111;0ad S]2<6n 26nad 3V =diag [0ad 3V]2<6n 26n:Also,02<6n 26n is given by0=11100Ad f111...............00111AdfI 62601110Ad fI 626111...............Ad fAdf;Ad Q ];with each Q i an element of SE (3);and Ad Q(S i );if S i is expressed instead as a 424matrix then A i =Q i S i Q 01i :It is not difficult to see that any Q as defined above will preserve the structure of S;G;and J;i.e.,A and L have the same block-matrix structure as S and G;etc.Upon substitution of (15)–(17)into the equations of motion (11)–(14),we findM (q )=A T L T DLA (18)C (q;_q )=A TL T(DLad S _q 0+ad 3VD )LA _q (19) (q )=A T L T DLP 0_V 0(20)J t (q )=P t LA(21)where0=Q 0Q 01(22)ad S _q =Qad S _q Q01(23)ad 3V=Q0Tad 3VQT(24)P 0=QP 0(25)P T t =Q0T P T t :(26)The expression for 0is obtained via the following identity:I 0L 01=Q (I 0G 01)Q 01=Q 0Q 01:Upon comparing (18)–(21)to (11)–(14)it is apparent that the structure of the equations of motion is unchanged under the coordinate transformation defined by Q:This invariance is a result of the fact that M;C; and J t are direct tensor products of known tensor quantities (recall that direct products of tensors are themselves tensors).According to the transformation rules given above,under a change of coordinates A and P 0transform as vector quantities,or type (0,1)tensors,P t transforms as a covector,or a type (1,0)tensor,D transforms as an inner product acting on vectors,or a type (2,0)tensor,and L;0;ad S _q and ad 3V transform as linear operators,or (1,1)tensors.For a well-written discussion of tensor analysis see [2].Physically,different choices of Q correspond to different sets of local link reference frames in which to express the kinematic and dynamic parameters of the robot.As a concrete example con-sider a change of local link reference frames defined by Q =diag [Ad Q;111;Ad Q J i Ad 01Qformulation that can be computed recursively.A general coordinate invariant recursive algorithm is obtained by substituting (15)–(17)and (22)–(26)into the global matrix representation of the Newton–Euler algorithm (6)–(9)V =LA _q +LP 0V 0(27)_V =LA q +Lad S _q F V +Lad S _q P 0V 0+LP 0_V 0(28)F =L T D _V+L T ad 3VDV +L T P T tF n +1(29) =A TF(30)whereV =QV(31)_V =Q _V (32)F =Q0TF:(33)Upon direct expansion of (27)–(30),it can be shown that they areequivalent to the following recursive algorithm:1)InitializationGiven :V 0;_V0;F n +12)Forward recursion:for i =1to n dof i 01;i =Q i 01M i Q 01i eA(34)V i =Ad f(_V i 01)0ad AAdf(D i V i )(37) i =A T i F i :(38)Note that the above equations have exactly the same form asthe recursive Newton-Euler equations with S i replaced by A i ;M ireplaced by Q i 01M i Q 01i ;J i replaced by D i and all generalized velocities,accelerations,and forces replaced by their components in the new set of local link reference frames defined by Q:III.S QUARE F ACTORIZATION OF THE M ASS M ATRIXThe factorization of the mass matrix given in (11)is not a square factorization in the sense that S is not a square matrix.As a result it is not possible to use this factorization to invert the mass matrix explicitly.Rodriguez et al.[13]have derived a square factorization of the mass matrix and its inverse using results from estimation theory.In this section,we determine an alternative square factorization of M and M 01using our earlier Lie algebraic results,and explicitly show how this factorization transforms under a change of coordinates.Featherstone [3]has shown that the open chain equations of motion can alternately be formulated recursively in the following manner:F i =^Ji _V i +b i i =n;111;1(39)where ^Ji is the articulated body inertia of link i;and b i =b i (V i ;V i +1;S i +1;^Ji +1; i +1)is the bias force associated with link i:Upon expressing the quantities appearing in Featherstone’s articu-lated body inertia algorithm in terms of our geometric definitions andnotation it can be shown [9]that Featherstone’s ^Ji is related to the J i from the generalized Newton–Euler algorithm as follows.1)Initialization^Jn =J n :2)Backward recursion:for i =n 01to 1do^J i =J i +Ad 3f0Ad 3fS T i +1^J i +1S i +1:(40)In terms of our earlier definitions,the above recursion is equivalentto the following matrix equation:J =^J00T ^J 0+0T ^JS (S T ^JS )01S T ^J 0(41)where the symmetric matrix ^J is defined as ^J =diag [^J 1;^J 2;111;^J n ]2<6n 26n :A square factorization of M results if J is expressed as a function of ^Jin the factorization M =S T G T JGS :Proposition 1:The mass matrix M can be expressed in terms of the n 2n factors [I +S T G T 5]and as follows:M =[I +S T G T 5] [I +S T G T 5]Twhere =S T ^JS2<n 2n ;8= 01S T ^J 2<n 26n ;5=0T 8T 2<6n 2n ;and I is the 323identity matrix.Proof:Substituting (41)into S T G T JGS and using the identity 0G =G 0I yieldsM =S T G T ^JS +S T ^JGS 0S T ^JS+S T G T 0T ^JS(S T ^JS )01S T ^J 0GS:Adding and subtracting S T ^JSto the above equation and rearranging yieldsM =S T ^JS+S T (G T 0I )^JS +S T ^J T (G 0I )S +S T G T 0T ^JS(S T ^JS )01S T ^J 0GS:Using the identity G 0I =0G results inM =S T ^JS+S T G T 0T ^JS +S T ^J T 0GS +S T G T 0T ^JS(S T ^JS )01S T ^J 0GS:Upon post-multiplying the second term by (S T ^JS)01(S T ^JS );pre-multiplying the third term by (S T ^JS)(S T ^JS )0T ;and noting that (S T ^JS)01from the last term also equals (S T ^JS )01(S T ^JS )(S T ^JS)0T ;the result follows after an elementarycalculation.01;211100052;31110...............0001115n 01;n 00111IV.I NVERSIONOF THEM ASS M ATRIXThe square factorization of M immediately leads to a similar square factorization for M 01:Proposition 2:The inverse mass matrix M 01is given byM 01=[I 0S T Y 5]T 01[I 0S T Y 5]where Y =(I 0X T )012<6n 26n and X T =0T (I 0^JS(S T ^JS )01S T )=0T (I 08T S T ):Proof:Applying the well-known matrix inversion lemma (also known as the Sherman–Morrison–Woodbury Formula)(A +BCD )01=A 010A 01B (DA 01B +C 01)01DA 01to [I +S T G T 5]01and recalling G 0T =(I 00T );the result follows after a routine calculation.0011100X 2;10111000X 3;211100...............111X n;n 01I 0S k +1S T k +1^J k +1S Tk +1^Jk +1S k +1I Y1;2Y 1;3111Y 1;n 0I Y 2;3111Y 2;n ...............000111Y n 01;n00111Iqq(A k 01_q k 01+^a k 01)(51)V k =Ad f_q D k V k :(54)Once ~a and ~b have been computed it can be shown by direct expansion that (46)is equivalent to the following recursive algorithm.1)Initialization0=0;~a 1!~a 1+Ad fk 01+~a k(56) k =D k k +~b k :(57)3)InitializationP n +1=0; n ! n +Ad 3fP k +1+ (59)^P k =A T k P k(60)^ k = k 0^Pk :(61)Once ^ has been computed it can be shown by direct expansionthat (45)is equivalent to the following recursive algorithm.1)Initialization^z n +1=0;^n +1=0:(62)2)Backward recursion:for k =n to 1do^z k =Y k;k +1^z k +1+5k;k +1^ k +1(63)c k =^ k 0A T k ^zk (64)^c k = 01k c k :(65)3)Initialization0=0:(66)4)Forward recursion:for k =1to n dok =Y T k 01;k k 01+A k ^c k (67) q k =^c k 05T k 01;k k 01:(68)HereY k:k +1=X Tk +1;k=Ad 3fI 0^J k +1A k +1A T k +1A T k +1^J k +1Ak +1。
《大学基础英语》教案(英文)Book 3 Unit 9 Teaching plan
Unit NineI.Objectives✧To get familiar with the topic of environmental issues and master some useful expressionsabout it;✧Text I is a short piece of narrative writing about an unforgettable winter. Millions have gonethrough winters over and over again but few have experienced an extremely cold winter as described in the passage. In order to convey the uniqueness of this particular, never-to-be forgotten winter, the writer skillfully uses description within narration and provides a lot of specific and concrete details. He also employs two figures of speech, metaphor and personification in the text to make it more vivid and impressing. Students are supposed to learn such writing skills and use them in their writing later on.II. Teaching Emphases and Difficulties:1. The comprehension and appreciation of Text I;2. New words and expressions:grimy, overhauling, squirt, thaw, relentlessly, set in, lie in a grip of iron, impression, devoted, bellow, lullaby, rattle, mutter, intimate, puff, puckered, tweakIf winter comes, can spring be far behind?— Percy Bysshe Shelley In seed time learn, in harvest teach, in winter enjoy.— William Blake Autumn is a second spring where every leaf is a flower.— Albert Camus No winter lasts forever; no spring skips its turn.— Hal Borland To be interested in the changing seasons is a happier state of mind than to be hopelessly in love with spring.— George Santayana If Nature is opposed, we will fight her and make her obey us.— Simón Bolívar It seems clear at last that our love for the natural world — Nature — is the only means by which we can requite God’s obvious love for it.— Edward Abbey1.ListeningListen to the recording and answer the following questions.1. What is the climate like in Southern Oregon? What is the weather like there between November and March?In Southern Oregon, summers are very hot, sunny and dry, while the winters bring long spells of grey skies and drizzly rain. Between November and March it feels like it rains all the time, or at least stays pretty dark.2. What has been brightening the speaker’s mood in the past few days?The bright and sunny days in the past few days has been brightening the speaker’s mood.3. Where did she get the confirmation of the fact that the weather affects our moods?She got the confirmation of the fact that weather affects our moods in a little informational e-book called Brighten Your Life.4. According to Dr. Kripke, what is the correlation between light and our moods?According to Dr. Kripke, sadness rules where it is dark while light makes people happier.5. In the speaker’s view, why do people now spend less time outdoors? What are the benefits of spending more time outside?People now spend less time outdoors because of their laziness or routine habits. Staying outdoors can make people’s heads clear and make their energy rise. People can also get Vitamin D from the sun.ScriptLight up Your Life: How the Weather Affects Our Moods For the past three years, I’ve been living in Southern Oregon, where the summers are v ery hot, sunny and dry, while the winters bring long spells of grey skies and drizzly rain. Between November and March it feels like it rains all the time, or at least stays pretty dark. Luckily, the past few days have brought some bright, sunny days, and that’s been brightening my mood, too.I always wondered why people —especially weather forecasters —always had to equate certain weather with being “miserable” or “dreary”. I thought it was pretty much giving our power away to let something as random as the weather affect our moods.But lately I’ve been thinking more and more about the scientific validity of that. After a bit of digging, I got confirmation of the fact that light (and, by extension, weather) does indeed impact the way we feel. It’s laid o ut pretty clearly in a little informational e-book called Brighten Your Life.In the book, Dr. Kripke writes, “Think about the dark dungeons of despair, the heart of darkness, the gloominess of a funeral mood. Sadness rules where it is dark,” He goes on to say, “Think about a person who has seen the Light. Think about brilliance. Think how we describe the great joy of love by singing,’You are My Sunshine’. We know that light makes us happier.”These days, we spend more and more time indoors, and Dr. Kripke blames modern urbanization. He points out that when he was a little boy, they played outside often, and walked toschool even in the winter. After all, they didn’t have all the video games and electronic toys, and there were only a few channels on TV.But we don’t need to blame technology. In fact, technology provides an answer in Kripke’s book: bright light, which is used to treat depression and seasonal affective disorder (SAD).So if not technology, what should we blame? Laziness, perhaps, or simply routine habits. But it’s really a catch 22. We don’t feel like going outside, but we feel worse by staying in. I know that I find my head clears and my energy rises when I go outside, even if it is raining. So certainly our kids can benefit from fresh air too, not to mention the Vitamin D we get from the sun.That’s why I’m making it a personal goal this year to spend more time outside, and to take my family with me, regardless of how much my husband and I feel we need to be tied to our computers, working. Aft er all, if you’re going to light up your life, you might as well do it the natural way. Indoor lights might be good, but the biggest light of all — the sun — is even better.2.Speaking Practice1.Give an oral presentation on the summary of the listening passage.ReferenceThe key points:-my experience and consideration concerning the relationship between weather and our moods -Dr. Kripke’s statements in the e-book Brighten Your Life-what to blame for our spending more time indoors-my personal goal to spend more time outside2. Discuss and comment on the effectiveness of each other’s oral presentation.3. Work in pairs and take turns to ask and give answers about the following topics:a. Do you agree that the weather affects our moods? Have you ever had such an experience?b. Can you cite some examples from some literary works regarding the correlation betweenthe weather and people’s moods ?c. Why do people now spend more time indoors?Text I A Winter to Remember1.Pre-Reading QuestionsWhat does the title of the text suggest to you? Make your own predictions about the contents of the passage by listing two or three things that are likely to be dealt with in it.Use your imagination to make your own predictions. Then discuss with your classmates.2.General ReadingGo over the text rapidly once and fill in the grid with what you have learned from your first rapid reading.3.BackgroundIntroductionA central heating system provides warmth to the whole interior of a building (or portion of a building) from one point to multiple rooms. When combined with other systems in order to control the building climate, the whole system may be an HV AC (heating, ventilation and air conditioning) system.Central heating differs from local heating in that the heat generation occurs in one place, such as a furnace room in a house or a mechanical room in a large building (though not necessarily at the “central” geometric point). The most common method of heat generation involves the combustion of fossil fuel in a furnace or boiler. The resultant heat then gets distributed: typically by forced-air through ductwork, by water circulating through pipes, or by steam fed through pipes. Increasingly, buildings utilize solar-powered heat sources, in which case the distribution system normally uses water circulation.4.TextWords and phrases:(1) approximately: ad. (of quantities) imprecise but fairly close to correcte.g. At present there are no women among the approximately 40 cosmonauts in the Russianspace program.Worldwide, approximately 100 million sharks are killed each year, 98% exclusively fortheir fins.(2) thrilled: a. feeling intense pleasurable excitemente.g. We’re thrilled so many people are interested in trying out a new approach to onlinesharing.Also thrilled was Ryan’s father Gary, a former jump jockey and now successful trainer.(1)relentlessly: ad. in never-ceasing mannere.g. Boxers head for the gym and work out relentlessly every dayShe always questioned me relentlessly.(2)flake: a. a small thin piece of something, especially if it has come from a surface covered witha layer of somethinge.g. One flake and then another, and the deepest snow is laid.The only other sound’s the sweep of easy wind and downy flake.(3)patch: n. a small area of something that is different from the area around ite.g. There was a small patch of blue in the grey clouds.Children’s toys lay abandoned over a small patch of neat garden.(4)rambling: a. large and spreading out in many different directionse.g. Here was an old church, quaint and rambling and gabled.She had a huge, rambling country house called “The Gables”.(5)canopy: n.a covering (usually of cloth) that serves as a roof to shelter an area from theweathere.g. It was a deep pool under a high canopy of leaves.To the south Sycamore trees create a tall, broadleaf canopy.(6)scrap: n. a small irregular piece of something or a small amount of informatione.g. What they had discovered was nothing more than a scrap of metal.But in here, I cling to scrap of hope.(7)delicate: a. marked by great skill especially in meticulous techniquee.g. Thus she is represented within the church, in a delicate sculpture by Stefano Moderno.The delicate model was set in plastic to protect it.(8)churn: v. If water, mud, etc., churns, or if something churns it, it moves about violently.e.g. The tractor churned up the soil.A goose’s wings churn the air and leave an air current behind.(9)severe: a. very bad, intense, difficulte.g. Severe damage witnessed the destructive force of the storm.In a severe winter, wild animals can die from lack of food.(10)lump: n. a small piece of something solid, without a particular shapee.g. She has worked up a lump of clay into a bust.The crow flew over the river with a lump of raw liver.(11)grimy: a. something that is grimy is very dirtye.g. This place was grimy and low, the girls were careless and hardened.Heading south, it took 15 minutes to get beyond the town’s grimy ring of lightindustry.(12)grip: n.a firm controlling influencee.g. The murder stunned Croatia, revealing the grip of organised crime and corruption.The entire city seemed to shake in the grip of a giant fist.(13)tame: a. A tame animal or bird is not wild any longer, because it has been trained to live withpeople.e.g. In three days after his capture he was quite tame.It’s incredible that the tame wolf is as mild as a lamb.(14)chop: v. to cut something into smaller piecese.g. Chop cashew nuts, pine nuts, peanuts and pumpkin seeds. Mix them together.Tell the cook to chop the meat into cubes before frying it.(15)leftover: n. food that has not been eaten at the end of a meale.g. You’d best warm up the leftovers before eating them again.After a quick meal of leftovers I want to get back to work!(16)inadequate: a. not good enough, big enough, skilled enough, etc., for a particular purposee.g. The main cause for price decline was not inadequate money supply.The plan, brilliant in its conception, failed because of inadequate preparation.(17)uncooperative: a. not willing to work with or help someonee.g. They became bossy, uncooperative and hostile in their efforts to ward off depression.But it also allows uncooperative people to convert the program into proprietarysoftware.(18)overhaul: v.to repair or change the necessary parts in a machine, system, etc., that is notworking correctlye.g. Your car is badly damaged. It needs a thorough overhaul.Boeing documentation describes the methods for detecting base metal damage whilein service and during overhaul.(19)go on strike: a group of workers deliberately stop working because of a disagreement aboutpay, working conditions, etc.e.g. The coal-miners decided to go on strike for better working conditions.The union has voted to go on strike for a pay increase of 10%.(20)bucket: n. an open container with a handle, used for carrying and holding things, especiallyliquidse.g. Mother tipped the slops out of the bucket into the sink.The bucket tipped up, pouring milk all over the floor.(21)call at: to stop at a place for a short timee.g. I must call at the library to give back this book.How many ports do we call at on our passage?(22)tramp: v. to walk somewhere slowly and with heavy stepse.g. I missed the train and had to tramp it.We had to tramp the creeks.(23)lug: v. to pull or carry something heavy with difficultye.g. She lug ged the suitcase out into the hallway.I know I don’t want to lug around that extra weight.(24)promptly: ad. without delaye.g. We’ll have to leave fairly promptly if we want to catch that train.She promised she’d keep it secret and promptly went and told Ben!(25)stoop: v. to bend your body forward and downe.g. He had to stoop to go through the door.He’s too fat to stoop down.(26)furiously: ad. in a manner marked by extreme or violent energye.g. In no time did they go at each other furiously.The dog ran at the boy, barking furiously.(27)messy: a. dirty or untidye.g. In this messy room, clothes are chucked about on the floor.The man is wearing long hair, fleecy and messy and never comb.(28)thaw: v. If it thaws, the weather becomes warmer, so that ice and snow melt.e.g. She forgot to thaw out dinner, so we went out to dine.To start with, you thaw the meat in the microwave oven.(29)squirt: v. If you squirt liquid or if it squirts somewhere, it is forced out in a thin fast stream.e.g. Keep an eye on the water though, and don’t let it squirt out of the pipes!Squirt onto a clean cloth, apply and surface and polish.(30)cart: v. draw slowly or heavilye.g. After both their parents died, one of th eir father’s relatives carted off the entirecontents of the house.Do you have to cart the bag round all day?(31)eventually: ad. after a long time, or after a lot of things have happenede.g. His endless recounting of the incident eventually became unbearable.The rain belt is moving southward; it will be sunny here eventually.(32)undoubtedly: ad. with certaintye.g. Undoubtedly, public interest in folk music has declined.There was undoubtedly something charismatic and unusual about him.Notes1.in living memoryin the years which can be remembered by people still alive2.in the depths of the countryin the very remote part of the country. The depths of the country are the parts of the countryside which are far from cities and towns 在穷乡僻壤. The depths (plural) may also mean “the deepest or the worst part of something”e.g.in the depths of the oceanin the depths of winterin the depths of despair3.my whole familyFamily is a collective noun, denoting a group of individuals considered as one complete whole.More examples of collective nouns of this type:a crowd of people a team of football playersthe board of directors the whole classthe entire armyCollective nouns may take singular or plural verbs according to the following rules.1) If every member of a group is acting in the same way, the collective noun takes a singularverb.2) If the members of a group are acting separately, the collective noun takes a plural verb.3) The number of the pronouns or possessive adjectives referring to the collective nounscorrespond to the number of the collective nouns.e.g.The class are taking notes, their pens scribbling quickly over the pages of their notebooks.4.the garden was all churned upreferring to the snow in the garden which was turned upside down and inside out5.the whole countryside lay in a grip of ironthe whole countryside was hardened by ice.A grip of iron is a metaphor meaning “a frozen state”.6.Our central heating system proved both inadequate and unco-operative…inadequate — not adequateunco-operative — not co-operativee.g.He looked at me with an air of surprised disapproval.disapproval — the opposite of approvalUn-, in- and dis-are negative prefixes which mean “the opposite of” or “not”.e.g.un doubtedly un fortunately un happy un likelyin ability in competent in complete in directdis appear dis comfort dis like dis obey7.... but other people had thought of doing this too — when we called at the village shop, theshopkeeper told ... until the spring — which, of course, was a great comfort.... and our youngest son — not the most intelligent of youths — promptly took it all the way back to the farm.... only to discover the eggs had come to no harm — they were as solid as if they had been hardboiled.The dash is used in the above sentences to mark a sudden change of ideas or to give some explanation.8.there were more on orderThere were more oil-stoves being requested by the village shop to be sent to them 已向火油炉厂商进一步订货.Order in this context is a request made especially by a customer for something to be supplied.e.g.Jack placed/made an order for twenty oil-stoves to be sent before the end of November.“Shall I take your orders?” the waiter asked.9.which, of course, was a great comfortThis is a type of non-restrictive relative clause which has for its antecedent a whole sentence, or, as in this case, a clause or several clauses. Here, which refers to the fact that “although there were more on order they were unlikely to be delivered until the spring”.e.g.They invited me to go to Shakespeare’s birthplace for a visit, which was really very kind of them.The young man was asked to work under a woman, which made him feel greatly humiliated.A great comfort is an example of irony, the use of words which are clearly opposite to one’s meaning 反话. Actually the fact mentioned above could not be a comfort, because oil-stoves would not be needed when spring came.ments on the Text6.ExercisesAnswer the following questions.1. Why did the writer say that the whole countryside lay in a grip of iron?The whole countryside —the earth, the river, the gardens, the farms —was frozen solid, so solid that the countryside seemed to be kept in a hold as firm as iron.2. Why did the birds grow tamer?As it was severely cold and everything was frozen, the birds had no way of getting anything to eat, so they grew tamer and tamer so long as the frost lasted.3. What did the writer mean by “it simply went on strike”?It here refers to the central heat ing system. The clause means, “Our central heating system just refused to work. In other words, it broke down.” This is an example of personification. The writer is giving a humorous touch to the description.4. Why did the writer say “which was a great comfort” when they couldn’t buy the oil-stove?For the time being the oil-stoves were out of stock, but the mere thought of the possibility of their buying some in spring gave them little cause for satisfaction. The writer is being ironical here.5. Why did the writer call their youngest son “not the most intelligent of youth”?What the writer really meant was that their youngest son was very stupid, so stupid as to take the bucket of water all the way back to the farm from the house.6. Why did the writer think it a good thing that the dropped eggs had not become the messy remains?The writer is being ironical. They didn’t like the severe cold that winter. It caused them a lot of inconvenience and discomfort. However, there was one thing which was not quite so bad. The eggs were frozen so hard that when the children dropped them, they did not break.Text II (45 minutes):A. January WindNotes1.where lichen makes strange hieroglyphicswhere lichen growing there forms strange patterns2.In the cold of a lonely nightlate at night when it is cold and quiet3.... and stay there muttering of ice and snowbanks and deep-frozen pondsand stay there prophesying the coming of ice and snowbanks and deep-frozen pondsB O de to AutumnJohn KeatsNotes1.“Ode to Autumn”The poem is written in a three-stanza structure with a variable rhyme scheme. Each stanza is eleven lines long. In terms of the rhyme scheme, each stanza is divided into two parts. In each stanza, the first part is made up of the first four lines of the stanza, and the second part is made up of the last seven lines. The first part of each stanza follows an ABAB rhyme scheme, the first line rhyming with the third, and the second line rhyming with the fourth. The second part of each stanza is longer and varies in rhyme scheme: The first stanza is arranged CDEDCCE, and the second and third stanzas are arranged CDECDDE. An ode is a type of poem that expresses noble feelings to a person, a place or a thing.2.The first stanza describes the taste of Autumn. With the help of the sun, Autumn ripens fruitsand causes the late flowers to bloom.3.The second stanza describes the sights of Autumn. Autumn is compared to a female goddess,often seen sitting on the granary floor, her hair “soft-lifted” by the wind, and often seensleeping in the fields or watching a cyder-press squeezing the juice from apples.The third stanza describes the sounds of Autumn. The poet tells Autumn not to wonder where the songs of spring have gone, but instead to listen to her own music: at twilight, the “small gnats”hum above the sallows of the river, lifted and dropped by the wind, and “full-grown lambs” bleat from the hills, crickets sing, robins whistle from the garden, and swallows, gathering for their coming migration, sing from the skies.Exercises (refer to Workbook PP ) (45 minutes)Translation1. 今年的雨季来得特别早。
最新带隙基准源电路与版图设计
论文题目:带隙基准源电路与版图设计摘要基准电压源具有相对较高的精度和稳定度,它的温度稳定性以及抗噪性能影响着整个系统的精度和性能。
模拟电路使用基准源,或者是为了得到与电源无关的偏置,或者为了得到与温度无关的偏置,其性能好坏直接影响电路的性能稳定,可见基准源是子电路不可或缺的一部分,因此性能优良的基准源是一切电子系统设计最基本和最关键的要求之一,而集成电路版图是为了实现集成电路设计的输出。
本文的主要目的是用BiCMOS工艺设计出基准源电路的版图并对其进行验证。
本文首先介绍了基准电压源的背景发展趋势及研究意义,然后简单介绍了基准电压源电路的结构及工作原理。
接着主要介绍了版图的设计,验证工具及对设计的版图进行验证。
本设计采用40V的0.5u BiCMOS工艺库设计并绘制版图。
仿真结果表明,设计的基准电压源温度变化为-40℃~~85℃,输出电压为2.5V及1.25V。
最后对用Diva 验证工具对版图进行了DRC和LVS验证,并通过验证,表明本次设计的版图符合要求。
关键字:BiCMOS,基准电压源,温度系数,版图Subject: Research and Layout Design Of Bandgap ReferenceSpecialty: MicroelectronicsName: Zhong Ting (Signature)____Instructor: Liu Shulin (Signature)____ABSTRACTThe reference voltage source with relatively high precision and stability, temperature stability and noise immunity affect the accuracy and performance of the entire system. Analog circuit using the reference source, or in order to get the bias has nothing to do with power, or in order to be independent of temperature, bias, and its performance directly affects the performance and stability of the circuit shows that the reference source is an integral part of the sub-circuit, excellent reference source is the design of all electronic systems the most basic and critical requirements of one of the IC layout in order to achieve the output of integrated circuit design. The main purpose of this paper is the territory of the reference circuit and BiCMOS process to be verified.This paper first introduces the background of the trends and significance of the reference voltage source, and then briefly introduced the structure and working principle of the voltage reference circuit. Then introduces the layout design and verification tools to verify the design of the territory.This design uses a 40V 0.5u BiCMOS process database design and draw the layout.The simulation results show that the design of voltage reference temperature of -40 ° C ~ ~ 85 ° C, the output voltage of 2.5V and 1.25V. Finally, the Diva verification tool on the territory of the DRC and LVS verification, and validated, show that the territory of the design meet the requirements.Keywords: BiCMOS,band gap , temperature coefficient, layout目录1 绪论 (1)1.1 背景介绍及发展趋势 (1)1.2 研究意义 (3)1.3 本文主要工作 (4)2 基准电压源电路设计 (5)2.1 基准电压源的分类及特点 (5)2.2 基准电压源的温度特性 (7)2.2.1 负温度系数项V (7)BE2.2.2 正温度系数电压 (7)2.3 基本原理 (8)2.3.1 与温度无关的电路 (8)2.3.2.与电源无关的偏置电路 (8)2.4 基准电压源电路设计 (9)2.4.1 基本原理 (9)2.4.2 运放的设计 (10)2.4.3 带隙核心电路设计 (13)2.5 仿真分析 (14)3 版图设计 (19)3.1 版图设计的基础 (19)3.1.1 集成电路版图设计与掩膜版、制造工艺的关系 (19)3.1.2 版图设计的设计规则 (19)3.1.3 版图通用设计步骤 (22)3.2工艺介绍 (23)3.2.1 常见工艺简介 (23)3.2.2 BiCMOS工艺 (25)3.3 带隙基准电路的版图设计 (28)3.3.1 版图的分层及连接 (28)3.3.2 版图设计环境介绍 (29)3.3.3 器件及总体版图 (29)4 版图验证 (39)4.1 版图验证概述 (39)4.2 验证工具介绍 (38)4.2.1 Cadence概述 (38)4.2.2 Diva使用介绍 (39)4.3 版图的DRC验证 (43)4.4 版图的LVS验证 (43)5总结 (45)致谢 (48)参考文献 (49)1 绪论1.1 背景介绍及发展趋势基准源是模拟与数字系统中的核心模块之一,它被广泛应用于动态存储(DRAM)、闪存(flash memory)以及其他模拟器件中。
带隙电压基准的设计_毕业设计
0
基准电压源(Reference Voltage)是指在模拟电路或混合信号电路中用作电压基准的具有相对较高精度和稳定度的参考电压源。它的温度稳定性以及抗噪性能影响着整个电路系统的精度和性能。模拟电路使用基准源,或者是为了得到与电源无关的偏置,或是为了得到与温度无关的偏置,其性能好坏直接影响电路的性能稳定,可见基准源是子电路不可或缺的一部分,因此也可以说性能优良的基准源是一切电子系统设计最基本和最关键的要求之一。
1.1
1
N型MOS(NMOS)器件制作在p型衬底上(衬底也称作bulk或者body),两个重掺杂n区形成源端和漏端,重掺杂的(导电的)多晶硅区(通常简称poly)作为栅,一层二氧化硅使栅与衬底隔离。器件的有效作用就发生在栅氧下的衬底区。注意,这种结构中的源和漏是对称的。
源漏方向的栅的尺寸叫栅长L,与之垂直方向的栅的尺寸叫做栅宽W。由于在制造过程中,源/漏结的横向扩散,源漏之间实际的距离略小于L。定义 ,式中 称为有效沟道长度, 是沟道总长度,而 是横向扩散的长度。 与氧化层厚度 对MOS电路的性能起着非常重要的作用。因此,MOS技术发展中的主要推动力就是不是器件的其他器件参数退化而一代一代的减少这两个尺寸。从简单的角度来看,PMOS器件可通过将所有掺杂类型取反来实现,在实际中,NMOS和PMOS器件必须在同一晶片上,也就是说做在相同的衬底上。NMOS和PMOS晶体管的区别在于每个PFETs可以出于各自独立的n阱中,而所有NFETs则共享同一衬底。
(1.2)
其中 为过驱动电压,称W/L为宽长比,以上两等式是CMOS模拟电路设计的基础,它描述了 与工艺常数 ,器件的尺寸W和L以及栅和漏相对于源的电位之间的关系。
电路原理题目
电路原理题⽬第⼀章1.图中所⽰电路中,已知a点、b点的电位分别为φa=10V,φb=5V。
则电动势E=____V:电压U=____V:由参考⽅向,得E=φa?φb,U=φa?φb由已知得E=10?5=5V,U=10?5=5V2.蓄电池端纽a和b两端的电压Uab和电动势Eab的关系是:E ab=U ab E ab=?U ab E ab=?U ab-由参考⽅向知道,电压Uab是指电压从a点到b点的降低。
电动势Eab是指电压从a点到b点的升⾼。
由此得Eab=-Uab 3.图中所⽰电路中,已知a点、b点的电位分别为φa=10V,φb=5V。
则电动势E=____V:电压U=____V:E=φb?φa,U=φa?φb由已知得E=5?10=?5V,U=10?5=5V4.图中所⽰电路中,已知a点、b点的电位分别为φa=10V,φb=5V。
则电动势E=____V:电压U=____V:由参考⽅向,得E=φa?φb,U=φb?φa由已知得E=10?5=5V,U=5?10=?5V5.图中所⽰电路中,已知a点、b点的电位分别为φa=10V,φb=5V。
则电动势E=____V:电压U=____V:E=φb?φa,U=φb?φa由已知得E=5?10=?5V,U=5?10=?5V6.⼆端元件的端电压和流过的电流如图所⽰。
则⼆端元件发出的功率P=____W:由电流的参考⽅向与电压降的⽅向⼀致,得,发出功率P=-2×3=-6W 7.⼆端元件的端电压和流过的电流如图所⽰。
则⼆端元件发出的功率P=____W:由电流的参考⽅向与电压降的⽅向不⼀致,得,发出功率P=2×3=6WThe reference direction of the voltage U across the resistor R is designated as: right is positive and left is negative, while the reference direction of it’s the current I is along the arrow from left to right, then the relationship of U and I is:U=RI U=RI- U=?RIresistor R are non-associated.8.For the circuit in the figure,the voltage Uab is:U ab=?14VU ab=?14V- U ab=11V U ab=?5V U ab=1V Mark the reference direction of the voltage U as shown in figure.We getU=3?1=3VAccording to KVL, the voltage is:U ab=?8+3=?5V9.For the circuit in the figure, the current I=____A:Mark the reference direction of the current I1 as shown in figure.Based on Ohm’s law,I1=12/2=6AAccording to KCL,I=4?I1=?2A10.For the circuit in the figure, the current I=____A and the voltage U=____V :Mark the reference directions of the current I1 and the voltage U1 as shown in figure.Based on Ohm’s law,I1=12/2=6AU1=3?8=24VAccording to KCL and KVL,I=8?I1=2AU=U1+12=36V11.For the circuit in the figure, the current I =____A and the voltage U1=____V,U2 =____V:Mark the reference directions of the current I1 and the voltage U3 and U4 as shown in figure.Based on Ohm’s law,I1=9/1=9AU4=2?2=4VAccording to KCL and KVL,I=3+2?I1=?4AU1=U3+9=15VU2=U4+9=13V12.For the circuit in the figure, the current I =____A and the voltage U1=____V,U2 =____V:Mark the reference directions of the current I1 and the voltage U3 and U4 as shown in figure.Based on Ohm’s law,I1=9/1=9AU4=2?2=4VAccording to KCL and KVL,I=3+2?I1=?4AU1=U3+9=15VU2=U4+9=13V13. Given the circuit as shown in the figure,(1) when I=4A,the current of current source I S=______A ;(2) when U=9V,the current of current source I S=______A:Write the equation applying KVL,U1=3U1+I×1According to Ohm’s law and KCL,U=3×(U1/1+I)According to Ohm’s law and KCL,I S=(U+U1)/2+U1/1+ICombine and solve the equations above by using the known values.(1)当I = 4A时,Is = 4A(2)当U = 9V时,Is = 6A14. In the figure,the current of current source I S= (A)?Write the equation applying Ohm’s law and KVL,U=?100U1+40×2=?100U1+80According to Ohm’s law,U1=0.2I SAccording to KCL and Ohm’s law,U=5(I S?2)Combining the above equations, we haveI S=3.6A15.Refer to the circuit of the figure, the power delivered by theindependent source is P= _____W.Write KCL on the upper node,U/2+U/3+0.5U=12Thus,U=9VThe power delivered by the independent source isP gen=12×9=108W16. In the following circuit, find the node voltage V3=__8.75____V. (hint: use simulation tools.)第⼆章1.As Fig2-1 shown, the input resistance of the two circuitsare______Ω and______ΩSimplify the circuit, we getThe bridge is balanced and the 5 ohm resistor can be removed, we getFrom the series-parallel formula, the solved resistance isR=10ΩSolution for (b):Simplify the circuit, we getFrom the series-parallel formula, the solved resistance isR=10Ω2. The circuit in Fig 2-2 can be simplified as:Fig(a), Fig(b), Fig (c), Fig(d). Choose ()or().解析:In the Fig.2-2, the 3 ohm resistor connected in series with the 5A current source doesn’t contribute to the port voltage, it only affects the voltage of current source. So it can be removed in the simplification.Using source transformation to the circuit in Fig above, we get the circuit shown in Fig below3.The circuit in Fig 2-3 can be simplified as:Fig(a), Fig(b), Fig(c), Fig(d). Choose ().&:Remove the 10 ohm resistor connected in parallel with the 6V voltage source, because it doesn’t contributes to the port voltage, then we getTransform the 2A current source in parallel with the 10 ohm resistor into a voltage source in series with a resistor, then we getIt’s finally simplified as4.Using source transformation to solve the current I(/A) of the circuit in the figure:Using source transformation to the 8V voltage source in series with the 4 ohm resistor, we getIt’s simplified as解析:Using source transformation to the 6A current source in parallel with the 2 ohm resistor and the 3A current source in parallel with the 3 ohm resistor respectively, then we getThe current I is solvedI=(12?9)/(2+3+5)=0.3A/doc/d918d4bac5da50e2524d7ff6.html ing source transformation to solve the current I (/A) of the circuit in the figure:解析:To simplify the circuit, remove the 10A current source in parallel with the voltage source and the 10 ohm resistor in series with the 5A current source, then we getTransform the two current voltage in parallel with resistor into voltage source in series with resistor, and we getIt’s simplified asTransform the 28V voltage source in series with the 4 ohm resistor into a 7A voltage source in parallel with a 4 ohm resistor, we getTwo 4 omega resistors in parallel is 2 ohm resistor, and transform the 7A current source in parallel with the 2 ohm resistor into a 14V voltage source in series with a 2 ohm resistor, then we getThe current I is solvedI=(14?25)/(2+3+5)=?1.1A6.The voltage U ab in the circuit shown in the figure is______V:解析:Using source transformation to the dependent source in the circuit, we getApplying the KCL and KVL, the equation is written as4(1?I)+4I=8IThe current is solvedI=0.5ABased on Ohm’s Law, the voltage isU ab=8I=0.5×8=4V。
振动分析和仪器的艺术达芬奇
Peak and RMS Comparison
Relationships of Acceleration, Velocity and Displacement
The Big Picture
Sensor(s)
Cables
Signal Conditioning
Data Acquisition & Storage
– Simple Harmonic Motion
• • Oscillation about a Reference Point Modeled Mathematically as…
x(t ) X sin t
Back to the Basics…
Period, T Unit Circle
RMS
• May result in amplifier output voltage becoming “Slew Rate Limited”
–
Sensor Cables
• •
–
Output of Sinusoid looks like this: What’s Happening?
The + part of the signal is being limited by the current available to drive the cable capacitance. In the – part of the sin wave, the op-amp must “sink” the current being discharged by the cable capacitance.
severity of reciprocal of Simple – •the Represented by vibratory Period motion •the Complex time delay CPS or two Hzas Pattern – •between Expressed Recognition • RPM •signals Peak to Peak Orders •Leading Zero to Peak – • RMS – •Lagging
PAM8003 滤波器无的 2.5W 双频带音频放大器说明书
FILTERLESS 2.5W CLASS-D STEREO AUDIO AMPLIFIERDescriptionThe PAM8003 is a 2.5W, Class-D audio amplifier. It offers low THD+N, allowing it to achieve high-quality sound reproduction. The new filterless architecture allows the device to drive the speaker directly,requiring no low-pass output filters, thus saving the system cost and PCB area.With the same numbers of external components, the efficiency of the PAM8003 is much better than that of class-AB cousins. It can extend the battery life, making it ideal for portable applications.The PAM8003 is available in SO-16 package.Features∙ 2.5W Output at 10% THD with a 5Ω Load and 5V Power Supply ∙ Filterless, Low Quiescent Current and Low EMI ∙ Low THD+N∙ 64-Step DC Volume Control ∙ Superior Low Noise ∙ Short Circuit Protection ∙ Thermal Shutdown∙ Few External Components to Save the Space and Cost ∙ RoHS Pass and Green Package∙ Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) ∙ Halogen and Antimony Free. “Green” Device (Note 3)Pin AssignmentsApplications∙ LCD Monitors / TVs ∙ Notebook Computers ∙ Portable Speakers∙Portable DVD Players, Game MachinesOrdering InformationNotes:1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.2. See https:///quality/lead-free/ for more information about Diodes Incorporate d’s definitions of Halogen - and Antimony-free, "Green" and Lead-free.3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and <1000ppm antimony compounds.Typical Applications Circuit ArrayPin DescriptionsFunctional Block DiagramAbsolute Maximum Ratings (@T A = +25°C, unless otherwise specified.)These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for prolonged time periods may affect device reliability. All voltages are with respect to ground.Recommended Operating Conditions(@T A = +25°C, unless otherwise specified.)Thermal InformationElectrical Characteristics (@T A = +25°C, V DD = 5V, Gain = 24dB, R L = 8Ω, unless otherwise specified.)Typical Performance Characteristics (@T A = +25°C, unless otherwise specified.)Typical Performance Characteristics (continued) (@T A = +25°C, unless otherwise specified.)Typical Performance Characteristics (cont.) (@T A = +25°C, unless otherwise specified.)Application Information1. When the PAM8803 works with LC filters, it should be connected with the speaker before it’s powered on, otherwise it will risk being damaged easily.2. When the PAM8003 works without LC filters, it’s better to add a ferrite chip bead at the outgoing line of speaker for suppressing the possi ble electromagnetic interference.3. The recommended operating voltage is 5.5V. When the PAM8003 is powered with four battery cells, it should be noted that the voltage of four new dry or alkaline batteries is over 6.0V, higher that its operation voltage, which will probably damage the device. Therefore, its recommended to use either four Ni-MH (Nickel Metal Hydride) rechargeable batteries or three dry or alkaline batteries.4. One should not make the input signal too large. Large signal can cause the clipping of output signal when increasing the volume. This will damage the device because of big gain of the PAM8004.5. When testing the PAM8803 without LC filters by using resistor instead of speakers as the output load, the test results, e.g. THD or efficiency, will be worse than those of using speaker as load.Test Setup for Performance TestingNotes: 4. The AP AUX-0025 low pass filter is necessary for class-D amplifier measurement with AP analyzer.5. Two 22μH inductors are used in series with load resistor to emulate the small speaker for efficiency measurement.Power Supply DecouplingThe PAM8003 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output THD and PSRR as low as possible. Power supply decoupling affects low frequency response. Optimum decoupling is achieved by using two capacitors of different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resisitance (ESR) ceramic capacitor, typically 1.0µF, works best, placing it as close as possible to the device V DD terminal. For filtering lower-frequency noise signals, a large capacitor of 20µF (ceramic) or greater is recommended, placing it near the audio power amplifier.Input Capacitor (C I )Large input capacitors are both expensive and space hungry for portable designs. Clearly, a certain sized capacitor is needed to couple in low frequencies without severe attenuation. But in many cases the speakers used in portable systems, whether internal or external, have little ability to reproduce signals below 100Hz to 150Hz. Thus, using a large input capacitor may not increase actual system performance. In this case, input capacitor (CI) and input resistance (RI) of the amplifier form a high-pass filter with the corner frequency determined by equation below.In addition to system cost and size, click and pop performance is affected by the size of the input the coupling capacitor, C I . A larger input coupling capacitor requires more charge to reach its quiescent DC voltage (nominally ½ V DD ). This charge comes from the internal circuit via the feedback and is apt to create pops upon device enable. Thus, by minimizing the capacitor size based on necessary low frequency response, turn-on pops can be minimized.C R 21f II C ∏=Application Information (continued)Analog Reference Bypass Capacitor (C BYP)The Analog Reference Bypass Capacitor (C BYP) is the most critical capacitor and serves several important functions. During start-up or recovery from shutdown mode, C BYP determines the rate at which the amplifier starts up. The second function is to reduce noise caused by the power supply coupling into the output drive signal. This noise is from the internal analog reference to the amplifier, which appears as degraded PSRR and THD+N.A ceramic bypass capacitor (C BYP) with values of 0.1μF to 1.0μF is recommended for the best THD and noise performance. Increasing the bypass capacitor reduces clicking and popping noise from power on/off and entering and leaving shutdown.Undervoltage Lock-Out (UVLO)The PAM8003 incorporates circuitry designed to detect low supply voltage. When the supply voltage drops to 2.0V or below, the PAM8003 outputs are disabled, and the device comes out of this state and starts to normal function when V DD≥ 2.2V.Short Circuit Protection (SCP)The PAM8003 has short circuit protection circuitry on the outputs to prevent damage to the device when output-to-output or output-to-GND short occurs. When a short circuit is detected on the outputs, the outputs are disabled immediately. If the short was removed, the device activates again.Over-temperature ProtectionThermal protection on the PAM8003 prevents the device from damage when the internal die temperature exceeds +140°C. There is a 15° tolerance on this trip point from device to device. Once the die temperature exceeds the thermal set point, the device outputs are disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 30°C. This large hysteresis will prevent motor boating sound well and the device begins normal operation at this point without external system intervention.How to Reduce EMI (Electro Magnetic Interference)A simple solution is to put an additional capacitor 1000μF at power supply term inal for power line coupling if the traces from amplifier to speakers are short (< 20cm).Most applications require a ferrite bead filter as shown in Figure 2. The ferrite filter reduces EMI of around 1 MHz and higher. When selecting a ferrite bead, choose one with high impedance at high frequencies, and low impedance at low frequencies.Figure 2. Ferrite Bead Filter to Reduce EMIMarking InformationPackage Outline DimensionsPlease see /package-outlines.html for the latest version.SO-16SEE DETAIL 'A'11 of 12 May 2017 © Diodes IncorporatedSuggested Pad LayoutPlease see /package-outlines.html for the latest version.SO-16PAM8003Document number: DS36421 Rev. 2 - 212 of 12 May 2017 © Diodes IncorporatedPAM8003Document number: DS36421 Rev. 2 - 2。
参考电压 英语
参考电压英语
参考电压英语:reference voltage。
例句:
1、参考电压产生单元用以提供多个电压电平。
The reference voltage generation unit provides a plurality of voltage levels.
2、电路基础是单运算放大器,其不需要参考电压。
The circuit's basis is a single operational amplifier, and it needs no reference voltages.
3、那是因为0 V的参考电压通常是指众所周知的大地。
That's because the 0 V reference is usually the famous ground.
4、在电压扰动期间使用递推算法计算每一时刻的参考电压。
During the voltage sag, the reference values are replaced by those which are calculated from the actual values according to the forecast algorithm.
5、提出一种采用改变参考电压来校正热电偶非线性的简单方法。
The simple method by changing reference voltage for non-linear correction of thermocouples is introduced.。
混音delay的计算方法
混音delay的计算方法Delay mixing is a crucial aspect of the audio production process that can greatly enhance a song's depth, character, and overall sound quality. When used correctly, delay can create a sense of space and dimension in a mix, adding richness and texture to the music. However, calculating delay times can be a challenge for many aspiring mix engineers, as it requires a solid understanding of how delay works and how it impacts the overall sound of a song.混音延迟是音频制作过程中至关重要的一个方面,可以极大地增强歌曲的深度、特色和整体声音质量。
当正确使用时,延迟可以在混音中创造出一种空间和维度的感觉,为音乐增添丰富和纹理。
然而,对于许多初涉混音工程师来说,计算延迟时间可能是一个挑战,因为这需要对延迟的工作原理和对歌曲整体声音的影响有着扎实的理解。
One method for calculating delay times is to use the tempo of the song as a reference point. By knowing the tempo, you can calculate the delay times in milliseconds based on the musical divisions such as quarter notes, eighth notes, or sixteenth notes. This method allows you to synchronize the delay with the tempo of the song,creating a cohesive and rhythmically-pleasing effect that enhances the overall musicality of the mix.一种计算延迟时间的方法是以歌曲的节奏作为参考点。
浅谈参考电压(VoltageReference
浅谈参考电压(VoltageReference淺談參考電壓(Voltage Reference)CIC 林千智大多數的類比電路,都需要參考用的電壓、電流、或是『時間』。
參考電壓提供一個準則,如DAC或ADC的LSB大小、穩壓器(Regulator)的輸出電壓位準、電池充電器的開與關等,都是由參考電壓源或參考電流源所提供及決定。
近年來,由於製程的進步,以及環保的需求,使得系統操作電壓不斷地下降,舊式的各種參考電壓線路逐一失效。
本文將介紹於各個電壓下,一些典型的參考電壓產生方式。
基納(Zener)二極體與放電管(Glow-Discharge Voltage Regulator Tubes)真空管時期的參考電壓,由放電管所提供。
放電管內部填充惰性氣體,當外加電壓超過它的放電電壓後,它的屏極與陰極間會維持固定電壓,並發出霓虹燈般的亮光。
如圖1,它的實際應用方式與今日的基納二極體相似,以電阻充當電流源提供並限制放電管工作電流,形成一個分流式穩壓電路(shunt regulator),一般放電管的規格大約在50V以上。
圖1 放電管的操作當半導體逐漸取代真空管後,以離散元件組合的類比電路板常使用基納二極體作為參考電壓源使用,使用上大致與放電管相似。
圖2 定電流源提供基納二極體操作電流使用基納的參考電壓源,輸出為基納二極體P/N介面的崩潰電壓。
如圖2,使用定電流源,或是電阻,提供並限制基納二極體工作電流。
由基納二極體產生的參考電壓,可以低至2V前後。
基納二極體與幾乎所有的主、被動元件一樣,特性都會隨著溫度變化而改變。
基納二極體操作時的兩端點電壓差,會隨著溫度的改變而改變。
因此正溫度係數的基納二極體,可以利用負溫度係數的P/N介面順向導通電壓做補償,如圖3,而得到零溫度係數的電壓輸出。
圖3 以負溫度係數P/N 介面順向導通電壓進行補償圖4 以VBE Multiplier放大P/N 接面電壓提供負溫度係數電壓的二極體,如圖4,常用"VBE multiplier",得到一個可以放大倍率調整的P/N 順向導通電壓。
dcdc原边反馈电压
dcdc原边反馈电压**DCDC原边反馈电压的重要性**In the realm of power electronics, DC-to-DC converters (DCDC converters) play a crucial role in efficiently converting direct current (DC) voltage from one level to another. The primary side feedback voltage, often referred to as the primary feedback voltage, is a crucial parameter in ensuring the stable and efficient operation of these converters.在电力电子领域,直流到直流转换器(DCDC转换器)在高效地将直流(DC)电压从一个级别转换到另一个级别方面发挥着至关重要的作用。
原边反馈电压,通常称为初级反馈电压,是确保这些转换器稳定、高效运行的关键参数。
**Monitoring and Control**The primary feedback voltage is continuously monitored and used to adjust the converter's operation. By comparing the feedback voltage to a reference value, the control system can determine if the output voltage is within the desired range. If a deviation is detected, the control system adjusts the converter's internal parameters to bring the output back to the desired level.原边反馈电压被持续监测,并用于调整转换器的运行。
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111
Digital Output Code
The fundamentals of ADCs
Figure 1 shows the voltage-reference system for the successive-approximation-register (SAR) ADC that will be examined in this three-part series. As the name suggests, the ADC converts an analog voltage to a digital code. The overall system accuracy and repeatability depend on how effectively the converter executes this process. The accu racy of this conversion can be defined with static specifi ca tions, and the repeatability with dynamic specifications. Generally, the ADC static specifications are offset-voltage error, gain error, and transition noise. The ADC dynamic specifications are signal-to-noise ratio (SNR), total harmonic distortion (THD), and spurious-free dynamic range (SFDR).
111
Code Under Test
Digital Output Code
110 101 100 011 010 001 000
0
100% 0% 50% Center of Code Width
Low-Sidtion Points 1/2 FS Analog Input (FS = Full Scale) FS
where “Code” is the ADC output code in decimal form, VIN is the analog input voltage (in volts), n is the resolution of the ADC (or number of output-code bits), and VREF is the analog value of the voltage reference (in volts). This equation demonstrates that the ADC output code is directly proportional to the analog input voltage and inversely proportional to the voltage reference. Equation 1 also shows that the output code depends on the number of bits (the converter resolution). The DC errors of non-ideal ADCs are offset-voltage error and gain error. If the offset-voltage error is introduced into the transfer function, Equation 1 can be rewritten as Code = ( VIN − VOS _ ADC ) × 2n , VREF (2)
Texas Instruments Incorporated
Data Acquisition
How the voltage reference affects ADC performance, Part 1
By Bonnie Baker, Senior Applications Engineer, and Miro Oljaca, Senior Applications Engineer Introduction
5 Analog Applications Journal 2Q 2009 /aaj High-Performance Analog Products
Data Acquisition
Texas Instruments Incorporated
Figure 3. Transition noise with a 3-bit ADC
From Equation 3 it can be seen that the gain-error factor adds to the initial accuracy of VREF. The output code is inversely proportional to the combination of the voltage reference plus the gain error. The DC error caused by noise from the voltage-reference chip inversely impacts the gain accuracy of the ADC. Part 2 of this series will specifically show the impact of the voltage reference’s errors. Equations 2 and 3 can be combined to show the final transfer function: 2n Code = ( VIN − VOS _ ADC ) × (4) VREF ( 1 − GEADC ) To analyze ADC transition noise, the code transition points in the ADC’s transfer curve can be examined. These are the points where the digital output switches from one code to the next as a result of a changing analog input voltage. The transition point from code to code is not a single threshold but a small region of uncertainty. Figure 3 shows the uncertainty at these transitions that results from internal converter noise. The region of uncertainty is defined by measuring repetitive code transitions from code to code. An ADC’s transition noise has a direct effect on the signal-to-noise ratio (SNR) of the converter. Since it is important to understand this phenomenon, Part 2 of this series will look more closely at voltage-reference noise characteristics.
Equation 1 describes the typical transfer function of the ideal (error-free) ADC: Code = VIN × 2n , VREF (1)
GEADC =
Actual Gain − Ideal Gain . Actual Gain
110 101 100 011 010 001 000
Actual Transfer Function
Ideal Transfer Function
Actual Full-Scale Range Ideal Full-Scale Range
Static performance
Figure 2 shows an ideal and an actual (or non-ideal) transfer function of a 3-bit ADC. The actual transfer function has an offset-voltage error and a gain error. In the example appli ca tion circuit, only the ADC gain error, transition noise, and SNR are of concern.
Figure 1. Voltage-reference system for SAR ADC
– RO Voltage Reference + ESR CL1
CL 2
VREF VIN
ADC
DOUT
Figure 2. Ideal and actual ADC transfer functions with offset and gain errors
When designing a mixed-signal system, many designers have a tendency to examine and optimize each component separately. This myopic approach can go only so far if the goal is to have a working design at the end of the day. Given the array of different components in a system, designers must have a complete understanding of not only the individual components but also their impact on the overall system performance. When a design has an analogto-digital converter (ADC), it is critical to understand how this device interacts with the voltage reference and voltagereference buffer. This article is the first of a three-part series. Parts 2 and 3 will appear in future issues of the Analog Applications Journal. Part 1 looks at the fundamental operation of an ADC independently, exactly as many designers do, and then at the performance characteristics that have an impact on the accuracy and repeatability of the system. Part 2 will delve into the voltage-reference device, once again examin ing its fundamental operation and then the details of its impact on the performance of the ADC. Part 3 will investigate the impact of the voltage-reference buffer and the capacitors that follow it, and will discuss how to ensure that the amplifier is stable. Assumptions and conclusions will be compared to measurement results. The interplay between the driving amplifier, voltage reference, and converter will be briefly analyzed, followed by an investigation of the sources of error in the ADC’s conversion results.