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ADN8810 12位高输出电流源数据手册（版本C）说明书

12-Bit High Output Current Source Data Sheet ADN8810Rev. C Document FeedbackInformation furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. O ne Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2004–2017 Analog Devices, Inc. All rights reserved. Technical Support FEATURESHigh precision 12-bit current sourceLow noiseLong term stabilityCurrent output from 0 mA to 300 mA Output fault indicationLow driftProgrammable maximum current24-lead, 4 mm × 4 mm LFCSP3-wire serial interface APPLICATIONSTunable laser current source Programmable high output current source Automatic test equipmentFUNCTIONAL BLOCK DIAGRAM3195-0 RESET4.096VSERIALINTERF ACEADDRESSSBF AULTINDICA TIONFigure 1.GENERAL DESCRIPTIONThe ADN8810 is a 12-bit current source with an adjustable full-scale output current of up to 300 mA. The full-scale output current is set with two external sense resistors. The output compliance voltage is 2.5 V, even at output currents up to 300 mA.The device is particularly suited for tunable laser control and can drive tunable laser front mirror, back mirror, phase, gain, and amplification sections. A host CPU or microcontroller controls the operation of the ADN8810 over a 3-wire serial peripheral interface (SPI). The 3-bit address allows up to eight devices to be independently controlled while attached to the same SPI bus.The ADN8810 is guaranteed with ±4 LSB integral nonlinearity (INL) and ±0.75 LSB differential nonlinearity (DNL). Noise and digital feedthrough are kept low to ensure low jitteroperation for laser diode applications. Full-scale and scaledoutput currents are given in Equation 1 and Equation 2,respectively.SNREFFS RVI⨯≈10(1)⎪⎪⎪⎪⎭⎫⎝⎛+Ω⨯⨯⨯=1.01514096kRRVCodeI SNSNREFOUT(2)ADN8810Data SheetRev. C | Page 2 of 14TABLE OF CONTENTSFeatures .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Characteristics ................................................................ 4 Absolute Maximum Ratings ............................................................ 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ............................................. 7 Terminology ...................................................................................... 9 Functional Description (10)Setting Full-Scale Output Current ........................................... 10 Power Supplies ............................................................................ 10 Serial Data Interface ................................................................... 10 Standby and Reset Modes ......................................................... 11 Power Dissipation....................................................................... 11 Using Multiple ADN8810 Devices for Additional Output Current ......................................................................................... 11 Adding Dither to the Output Current ..................................... 12 Driving Common-Anode Laser Diodes ................................. 12 PCB Layout Recommendations ............................................... 13 Suggested Pad Layout for CP-24 Package ............................... 13 Outline Dimensions ....................................................................... 14 Ordering Guide .. (14)REVISION HISTORY11/2017—Rev. B. to Rev. CChanged R S to R SN .......................................................... Throughout Change to Figure 1 ........................................................................... 1 Changes to Maximum Full-Scale Output Current Parameter and Power Supply Rejection Ratio Parameter, Table 1 ................ 3 Moved Timing Characteristics Section, Table 2, and Figure 2 ..... 4 Added Lead Temperature Range (Soldering 10 sec) Parameter, Table 3 ................................................................................................ 5 Changes to Figure 3 and Table 4 ..................................................... 6 Changes to Setting Full-Scale Output Current Section ............. 10 Changes to Adding Dither to the Output Current Section,Figure 20, and Figure 21 ................................................................ 12 Changes to PCB Layout Recommendations Section andFigure 25 .......................................................................................... 13 Updated to Outline Dimensions .................................................. 14 3/2016—Rev. A to Rev. BChanges to Figure 3 and Table 4 ...................................................... 7 Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide . (15)4/2009—Rev. 0 to Rev. A Changes to Table 3 ............................................................................. 6 Changes to Figure 25 ...................................................................... 14 Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide . (15)1/2004—Revision 0: Initial VersionData Sheet ADN8810 SPECIFICATIONSAVDD = DVDD = 5 V, PVDD = 3.3 V, AVSS = DVSS = DGND = 0 V, T A = 25°C, covering output current (I OUT) from 2% full-scale current (I FS) to 100% I FS, unless otherwise noted.Rev. C | Page 3 of 14ADN8810Data SheetRev. C | Page 4 of 141 With respect to AVSS. 2R SN = 20 Ω. 3See Table 2 for timing specifications.TIMING CHARACTERISTICS1, 21 Guaranteed by design. Not production tested.2Sample tested during initial release and after any redesign or process change that may affect these parameters. All input signals are measured with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of (V IL + V IH )/2.SCLKC SSDIRESET*ADDRESS BIT A3 MUST BE LOGIC LOW03195-0-002Figure 2. Timing DiagramData SheetADN8810Rev. C | Page 5 of 14ABSOLUTE MAXIMUM RATINGSTable 3.Parameter Rating Supply Voltage 6 VInput VoltageGND to V S + 0.3 V Output Short-Circuit Duration to GND IndefiniteStorage Temperature Range −65°C to +150°C Operating Temperature Range−40°C to +85°C Junction Temperature Range, CP Package −65°C to +150°C Lead Temperature Range (Soldering 10 sec)300°CStresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.ESD CAUTIONADN8810Data SheetRev. C | Page 6 of 14PIN CONFIGURATION AND FUNCTION DESCRIPTIONS03195-0-003FAULT ADDR0ADDR1FB RSN ADDR2NICVREF AVDD AVSS NIC DVSS117P V D D I O U T I O U T P V D D 1E N C O M P S B NOTES1. NIC = NOT INTERNALLY CONNECTED.2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO DGND.Figure 3. Pin ConfigurationData SheetADN8810Rev. C | Page 7 of 14TYPICAL PERFORMANCE CHARACTERISTICSCODE1.2–0.84,500500I N L E R R O R (L S B )1,0001,5002,0002,5003,0003,5004,0001.00.2–0.2–0.4–0.60.80.600.403195-0-005Figure 4. Typical INL PlotCODE0.4–0.304,500500D N LE R R O R (L S B )1,0001,5002,0002,5003,0003,5004,0000.1–0.1–0.20.300.203195-0-006Figure 5. Typical DNL PlotTEMPERATURE (°C)0.200.15–0.20–4085–15∆I N L (L S B )1035600–0.05–0.10–0.150.100.0503195-0-007Figure 6. ∆INL vs. TemperatureTEMPERATURE (°C)0.200.15–0.20–4085–15∆D N L (L S B )1035600–0.05–0.10–0.150.100.0503195-0-008Figure 7. ∆DNL vs. TemperatureTEMPERATURE (°C)0.2580.2570.250–4085–15F U L L -S C A L E O U T P U T (A )1035600.2540.2530.2520.2510.2560.255R SN = 1.6Ω03195-0-009Figure 8. Full-Scale Output vs. TemperatureTEMPERATURE (°C)20.76520.75520.720–4085–15F U L L -S C A L E O U T P U T (m A )10356020.74020.73520.73020.72520.75020.745R SN = 20Ω20.76003195-0-010Figure 9. Full-Scale Output vs. TemperatureADN8810Data SheetRev. C | Page 8 of 14TEMPERATURE (°C)0.500.35I P V D D (m A )0.200.150.100.050.300.250.400.4503195-0-011Figure 10. PVDD Supply Current (I PVDD ) vs. Temperature120I D V D D (µA )864210TEMPERATURE (°C)03195-0-012Figure 11. DVDD Supply Current (I DVDD ) vs. Temperature1.51.0I A V D D (m A )1.41.31.21.1TEMPERATURE (°C)03195-0-013Figure 12. AVDD Supply Current (I AVDD ) vs. TemperatureFREQUENCY (Hz)100k1O U T P U T I M P E D A N C E (Ω)1k1001010k03195-0-014Figure 13. Output Impedance vs. FrequencyTIME (1µs/DIV)CSI OUTV O L T A GE (2.7V /D I V )03195-0-015Figure 14. Full-Scale Settling TimeTIME (200ns/DIV)CSI OUT03195-0-016Figure 15. 1 LSB Settling TimeData SheetADN8810Rev. C | Page 9 of 14TERMINOLOGYRelative AccuracyRelative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in least significant bits (LSBs), from an ideal line passing through the endpoints of the DAC transfer function. Figure 4 shows a typical INL vs. code plot. The ADN8810 INL is measured from 2% to 100% of the full-scale (FS) output.Differential NonlinearityDifferential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ± 1 LSB maximum ensures monotonicity. The ADN8810 is guaranteed monotonic by design. Figure 5 shows a typical DNL vs. code plot . Offset ErrorOffset error, or zero-code error, is an interpolation of the output voltage at code 0x000 as predicted by the line formed from the output voltages at code 0x040 (2% FS) and code 0xFFF (100% FS). Ideally, the offset error is 0 V . Offset error occurs from a combination of the offset voltage of the amplifier and offset errors in the DAC. It is expressed in LSBs.Offset DriftThis is a measure of the change in offset error with a change in temperature. It is expressed in (ppm of full-scale range)/°C. Gain ErrorGain error is a measure of the span error of the DAC. It is the deviation in slope of the output transfer characteristic from ideal. The transfer characteristic is the line formed from the output voltages at code 0x040 (2% FS) and code 0xFFF (100% FS). It is expressed as a percent of the full-scale range.Compliance VoltageThe maximum output voltage from the ADN8810 is a function of output current and supply voltage. Compliance voltage defines the maximum output voltage at a given current and supply voltage to guarantee the device operates within its INL, DNL, and gain error specifications.Output Current Change vs. Output Voltage ChangeThis is a measure of the ADN8810 output impedance and is similar to a load regulation spec in voltage references. For a given code, the output current changes slightly as output voltage increases. It is measured as an absolute value in (ppm of full-scale range)/V .O U T P U T V O L T A G E03195-0-004Figure 16. Output Transfer FunctionADN8810Data SheetRev. C | Page 10 of 14FUNCTIONAL DESCRIPTIONThe ADN8810 is a single 12-bit current output digital-to-analog converter (DAC) with a 3-wire SPI interface. Up to eight devices can be independently programmed from the same SPI bus. The full-scale output current is set with two external resistors. The maximum output current can reach 300 mA. Figure 17 shows the functional block diagram of the ADN8810.03195-0-017Figure 17. Functional Blocks, Pins, and Internal ConnectionsSETTING FULL-SCALE OUTPUT CURRENTTwo external resistors set the full-scale output current from the ADN8810. These resistors are equal in value and are labeled R SN in Figure 1. Use 1% or better tolerance resistors to achieve the most accurate output current and the highest output impedance.Equation 3 shows the approximate full-scale output current. The exact output current is determined by the data register code as shown in Equation 4. The variable code is an integer from 0 to 4095, representing the full 12-bit range of the ADN8810.SNFS R I ×≈10096.4(3)+Ω××=1.0151000,1k R R Code I SN SN OUT(4)The ADN8810 is designed to operate with a 4.096 V referencevoltage connected to VREF. The output current is directly proportional to this reference voltage. To achieve the bestperformance, use a low noise precision (the ADR292, ADR392, or REF198 is recommended).POWER SUPPLIESThere are three principal supply current paths through the ADN8810: •AVDD provides power to the analog front end of the ADN8810 including the DAC. Use this supply line topower the external voltage reference. For best performance, AVDD must be low noise.•DVDD provides power for the digital circuitry. Thisincludes the serial interface logic, the SB and RESET logic inputs, and the FAULT output. Tie DVDD to the same supply line used for other digital circuitry. It is not necessary for DVDD to be low noise.•PVDD is the power pin for the output amplifier. It canoperate from as low as 3.0 V to minimize power dissipation in the ADN8810. For best performance, PVDD must be low noise.Current is returned through the following three pins: •AVSS is the return path for both AVDD and PVDD. This pin is connected to the substrate of the die as well as the slug on the bottom of the lead frame chip scale package (LFCSP). For single-supply operation, connect this pin to a low noise ground plane.•DVSS returns current from the digital circuitry powered by DVDD. Connect DVSS to the same ground line or plane used for other digital devices in the application.•DGND is the ground reference for the digital circuitry. In a single-supply application, connect DGND to DVSS.For single-supply operation, set AVDD to 5 V , set PVDD from 3.0 V to 5 V , and connect AVSS, AGND, and DGND to ground.SERIAL DATA INTERFACEThe ADN8810 uses a serial peripheral interface (SPI) with three input signals: SDI, CLK, and CS . Figure 2 shows the timing diagram for these signals.Data applied to the SDI pin is clocked into the input shift register on the rising edge of CLK. After all 16 bits of the data-word have been clocked into the input shift register, a logic high on CS loads the shift register byte into the ADN8810. If more than 16 bits of data are clocked into the shift register before CS goes high, bits are pushed out of the register in first-in first-out (FIFO) fashion.The four MSB of the data byte are checked against the address of the device. If they match, the next 12 bits of the data byte are loaded into the DAC to set the output current. The first bit (MSB) of the data byte must be a logic zero, and the following three bits must correspond to the logic levels on pins ADDR2, ADDR1, and ADDR0, respectively, for the DAC to be updated. Up to eight ADN8810 devices with unique addresses can be driven from the same serial data bus.Table 5 shows how the 16-bit DATA input word is divided into an address byte and a data byte. The first four bits in the input word correspond to the address. Note that the first bit loaded (A3) must always be zero. The remaining bits set the 12-bit data byte for the DAC output. Three example inputs are demonstrated.•Example 1: This SDI input sets the device with an address of 111 to its minimum output current, 0 A. Connecting the ADN8810 pins ADDR2, ADDR1, and ADDR0 to VDD sets this address.• Example 2: This input sets the device with an address of 000 to a current equal to half of the full-scale output. •Example 3: The ADN8810 with an address of 100 is set to full-scale output.STANDBY AND RESET MODESApplying a logic low to the SB pin deactivates the ADN8810 and puts the output into a high impedance state. The device continues to draw 1.3 mA of typical supply current in standby. When logic high is reasserted on the SB pin, the output current returns to its previous value within 6 µs.Applying logic low to RESET sets the ADN8810 data register to all zeros, bringing the output current to 0 A. When RESET is deasserted, the data register can be reloaded. Data cannot be loaded into the device while it is in standby or reset mode.POWER DISSIPATIONThe power dissipation of the ADN8810 is equal to the output current multiplied by the voltage drop from PVDD to the output.()SN OUT OUT OUT DISS R I V PVDD I P ×−−×=²(5)The power dissipated by the ADN8810 causes a temperature increase in the device. For this reason, PVDD must be as low as possible to minimize power dissipation.While in operation, the ADN8810 die temperature, also known as junction temperature, must remain below 150°C to prevent damage. The junction temperature is approximatelyDISS JA A J P T T ×θ+=(6)where:T A is the ambient temperature in °C,θJA is the thermal resistance of the package (32°C/W). •Example 4: A 300 mA full-scale output current is required to drive a laser diode within an 85°C environment. The laser diode has a 2 V drop and PVDD is 3.3 V .Using Equation 5, the power dissipation in the ADN8810 is found to be 267 mW . At T A = 85°C, this makes the junction temperature 93.5°C, which is well below the 150°C limit. Note that even with PVDD set to 5 V , the junction temperature increases to only 110°C.USING MULTIPLE ADN8810 DEVICES FOR ADDITIONAL OUTPUT CURRENTConnect multiple ADN8810 devices in parallel to increase the available output current. Each device can deliver up to 300 mA of current. To program all parallel devices simultaneously, set all device addresses to the same address byte and drive all CS , SDI, and CLK from the same serial data interface bus. The circuit in Figure 18 uses two ADN8810 devices and delivers 600 mA to the pump laser.SERIAL INTERFACE (FROM µC OR DSP)I 600mA03195-0-018Figure 18. Using Multiple Devices for Additional Output CurrentTable 5. Serial Data Input ExamplesAddress Byte Data Byte SDI Input A3 A2 A1 A0D11 D10 D9 D8 D7 D6 D5 D4D3 D2 D1 D0 Example 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Example 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Example 31 01111 11 11 1 1 1 1ADDING DITHER TO THE OUTPUT CURRENTSome tunable laser applications require the laser diode bias current to be modulated or dithered. This is accomplished by dithering the V REF voltage input to the ADN8810. Figure 19 demonstrates one method.DITHERR203195-0-019Figure 19. Adding Dither to the Reference VoltageSet the gain of the dither by adjusting the ratio of R2 to R1. Increase C to lower the cutoff frequency of the high-pass filter created by C and R1. The cutoff frequency of Figure 19 is approximately 98 Hz.The AD8605 is recommended as a low offset, rail-to-rail input amplifier for this circuit.DRIVING COMMON-ANODE LASER DIODESThe ADN8810 can power common-anode laser diodes. These are laser diodes whose anodes are fixed to the laser module case. The module case is typically tied to either VDD or ground. For common anode to ground applications, a −5 V supply must be provided.In Figure 20, R SN sets up the diode current by the following equation:40965.16111.1096.4Code k R I SN ×Ω+×=(7)where Code is an integer value from 0 to 4095.Using the values in Figure 20, the diode current is 300.7 mA at a code value of 2045 (0x7FF), or half full-scale. This effectively provides 11-bit current control from 0 mA to 300 mA of diode current.The maximum output current of this configuration is limited by the compliance voltage at the IOUT pin of the ADN8810. The voltage at IOUT cannot exceed 1 V below PVDD, in this case, 4 V. The IOUT voltage is equal to the voltage drop across R S N plus the gate-to-source voltage of the external FET. For this reason, select a FET with a low threshold voltage.In addition, the voltage across the R SN resistor cannot exceed the voltage at the cathode of the laser diode. Given a forward laser diode voltage drop of 2 V in Figure 20, the voltage at the RSN pin (I × R SN ) cannot exceed 3 V . This sets an upper limit to the value of code in Equation 5.Although the configuration for anode-to-ground diodes is similar, the supply voltages must be shifted down to 0 V and −5 V , as shown in Figure 21. The AVDD, DVDD, and PVDD pins are connected to ground with AVSS connected to −5 V .The 4.096 V reference must also be referred to the −5 V supply voltage. The diode current is still determined by Equation 7. All logic levels must be shifted down to 0 V and −5 V levels as well. This includes RESET , CS , SCLK, SDI, SB , and all ADDR pins. Figure 22 shows a simple method to level shift a standard TTL or CMOS (0 V to 5 V) signal down using external FETs.NOTE: LEAVE FB WITH NO CONNECTION03195-0-020Figure 20. Driving Common-Anode-to-VDD Laser DiodesNOTE: LEAVE FB WITH NO CONNECTION03195-0-021Figure 21. Driving Common-Anode-to-Ground Laser Diodes with a NegativeSupplyRESETCS SCLK SDI03195-0-022Figure 22. Level Shifting TTL/CMOS LogicPCB LAYOUT RECOMMENDATIONSAlthough they can be driven from the same power supply voltage, keep DVDD and AVDD current paths separate on the printed circuit board (PCB) to maintain the highest accuracy; likewise for AVSS and DGND. Tie common potentials together at a single point located near the power regulator. This technique is known as star grounding and is shown in Figure 23. This method reduces digital crosstalk into the laser diode or load.LOGIC GROUNDRETURN03195-0-023Figure 23. Star Supply and Ground TechniqueTo improve thermal dissipation, solder the slug on the bottom of the LFCSP package be soldered to the PCB with multiple vias into a low noise ground plane. Connecting these vias to a copper area on the bottom side of the board further improves thermal dissipation.Use identical trace width and lengths for the two output sense resistors. These lengths are shown as X and Y in Figure 24. Differences in trace lengths cause differences in parasitic seriesresistance. Because the sense resistors can be as low as 1.37 Ω, small parasitic differences can lower both the output current accuracy and the output impedance. See the AN-619 Application Note for a sample layout for these traces.03195-0-024Figure 24. Use Identical Trace Lengths for Sense ResistorsSUGGESTED PAD LAYOUT FOR CP-24 PACKAGEFigure 25 shows the dimensions for the PCB pad layout for the ADN8810. The package is a 4 mm × 4 mm, 24-lead LFCSP . The metallic slug underneath the package must be soldered to a copper pad connected to AVSS, the lowest supply voltage to the ADN8810. For single-supply applications, this is ground. Use multiple vias to this pad to improve the thermal dissipation of the package.0.0270.011(0.28)0.020(0.50)CONTROLLING DIMENSIONS ARE IN MILLIMETERS03195-0-025Figure 25. Suggested PCB Layout for the CP-24-10 Pad LandingOUTLINE DIMENSIONS0.300.250.200.800.750.700.25 MIN2.202.10 SQ 2.000.50BSC0.500.400.30COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8.BOTTOM VIEWTOP VIEWSIDE VIEW4.104.00 SQ 3.900.05 MAX 0.02 NOM0.203 REFCOPLANARITY0.08PIN 1INDICATORFOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONSSECTION OF THIS DATA SHEET.02-21-2017-AEXPOSED PAD00SEATING PLANEDETAIL A (JEDEC 95)Figure 26. 24-Lead Lead Frame Chip Scale Package [LFCSP]4 mm × 4 mm Body and 0.75 mm Package Height(CP-24-10)Dimensions shown in millimetersORDERING GUIDEModel 1Temperature Range Package DescriptionPackage Option ADN8810ACPZ–40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-10 ADN8810ACPZ-REEL7–40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-101Z = RoHS Compliant Part.©2004–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03195-0-11/17(C)。

高速pcb设计与电路板分析课程讲义3

高速设计分析技术Agenda 课程安排High Speed Trends 高速设计趋势y gSynchronous Design 同步系统设计Source Synchronous Design 源同步系统设计-DDR2-DDR3Serial Link Design 高速串行设计-Interconnect consideration 互连考虑I t t id ti-Technologies 设计技术-8b/10b Encoding 8b/10b编码Trend towards serial connectivity向串行连接发展高速电路设计趋势Parallel I/O − Common Clock并行IO –共同时钟系统Pre-layout simulation for design exploration and post-layout simulation for verification可以通过SI前后仿真进行设计•Signal timing 信号时序•Signal noise 信号噪声•Undershoot and overshoot 过冲Parallel I/O − Common Clock (继续) 并行IO –共同时钟Increase data pin counts How to increase data rate? 如何提高数据速率Increase data pin counts 增加管脚Increase bus clock frequency 增加时钟频率But…… 但是……•Increase data pin counts − it’s more hard for PCB design(need more space for trace breakout, routing…..) 增加管脚造成PCB 设计困难•Increase clock frequency − it will reduce timing margin,destroy signal integrity (due to multi-drop top.), restrict data trace length, increase EMI…增加时钟频率使得时序紧张, 信号完整性问题突出, 走线线长约束严格, 电磁辐射增加…Parallel I/O − Source Synchronous并行I/O –源同步系统Provide guidelines for physical layout by sweeping the solution space 可以通过参数扫描分析确定电气约束Measurements for voltage and time specifications and worst case Measurements for voltage and time specifications and worst case report 得到最坏情况下的信号质量和时序要求Bus timing analysis 总线时序分析•Slew rate prorating/derating for Setup/Hold Time compensations (DDR2) 考虑边沿速率造成的的建立保持时间的补偿(DDR2)Increase bus clock frequency Parallel I/O − Source Synchronous (继续)并行I/O –源同步系统How to increase data rate? 如何提高数据速率Increase bus clock frequency 增加时钟频率From single strobe to dual strobe 采用读写数据采样时钟From single end strobe to differential strobe signaling 采用差分时钟•Increase bus clock frequency − there is no theoretical limit on bus clock frequency, but higher clock frequency will cause signal integrity depredation(due to multi ‐drop top.) But…… 但是……p (p p )增加时钟频率使得信号完整性问题突出…•From single strobe to differential strobe − for less timing margin while design migrates to high speed, differential strobe will increase valid timing window采用差分时钟提高速率但是因为速率提高, 时序参数更为紧张Parallel I/O -Integrating SI with Timing 并行接口分析–综合考虑SI 和时序Multiple TopologiesWaveformandSolution SpaceTiming Equation Signal Integrity and Timing Analysis integrated to one solution 信号完整性和时序分析组成一个完整的解决方案Vin_AC_HighVin_DC_HighVrefVin_DC_LowVin_AC_Low “Sim Start time” normalizedSerial I/O 串行I/OInterconnect loss of the channel (entire signal path) 考虑互连损耗Jitter controlled is required due to CDR 控制抖动Modeling complex drivers and receivers 需要更复杂的器件模型 Stress test the design with LARGE bit streams 要分析大量数据位传输S-parameter simulation (Time domain & Frequency Domain) S-参数分析, 时域和频域分析Agenda 课程安排High Speed Trends 高速设计趋势y gSynchronous Design 同步系统设计Source Synchronous Design 源同步系统设计-DDR2-DDR3Serial Link Design 高速串行设计-Interconnect consideration 互连考虑I t t id ti-Technologies 设计技术-8b/10b Encoding 8b/10b编码Synchronous Design 同步设计系统Sometimes called “Common Clock” 又叫共同时钟系统Clocks are distributed from a central point to all of the loads. 时钟信号由同一时钟源发送Max operating frequency is a function of Tco, Tpd, Setup, Hold, and M ti f i f ti f T T d S t H ld d Clock Skew最大工作频率由缓冲延时，传输延时，建立，保持时间和时钟偏移决定Synchronous Data Transfer 数据传输方式Clock 14HoldDriverT coFlight Time Setup23D0 D1 D2D0 D1 D2Driving ReceivingSynchronous Timing Terminology时序参数Cycle Time (Tcycle)时钟周期Clock Skew时钟偏移Cycle 1Cycle 2 Clock to Output (Tco)时钟输出延时Clock JitterSynchronous Timing Terminology (继续)时序参数Interconnect Delay (Tpd)互连传输延时Positive Interconnect Delay (Tpd)Negative Interconnect Delay (Tpd)Defining Tco Tco 定义Tco = time from clock rise to Vmeas into test load从时钟边沿进入器件到数据从器件输出有效的时间(数据输出接测试负载)DinClockOutput BufferInternal LogicClock rises t = 0V measT R L = 50 ΩTcoLoad for Tco measurement (from databook)Components of Tco Tco的组成ClockI t lClockDinOutputBufferInternalLogicR L= 50 Ωrisest = 0V measTcoInternal delay = from clock rise to the point where the output begins to switch内部逻辑时延External (buffer) delay = how long the buffer takes to drive the reference load to V meas缓冲器时延Clock Jitter 时钟抖动Clock Clock Jitter occurs when the clock period varies from one period to the nextDriverCycle 1Cycle 2one period to the next 考虑周期差抖动•Usually caused by PLLinstability in the clockdriver 通常由锁相环引起 Jitter increases / decreases the clock periodthe clock period,decreasing the effective clock cycle 抖动减小有效时钟周期Clock Skew 时钟偏斜Clock Driver t = 0Occurs when differentdevices see the clocktransition at differenttimesD0D0t = 1t = 2时钟到达不同器件的时延Increases / decreasesthe apparent clockcycle. Depending onwhich devices aredriving / receivingD1D2D1D2g g根据驱动接收不同变化Reduces the effectiveclock cycle 减小有效时钟周期内部偏斜和外部偏斜•时钟驱动器造成内部偏斜•而PCB布线和设计以及外部环境引起的偏斜被称为外C部偏斜tSKEW_INTRINSIC = 器件引起的偏斜tSKEW_EXTRINSIC = PCB + 布线＋工作环境引起的偏斜tSKEW = tSKEW_INTRINSIC + tSKEW_EXTRINSIC内部偏斜-输出偏斜(tSK）•单一器件的指定输出之间的偏斜(JEDEC)•输出偏斜也称为引脚到引脚的偏斜。

Cadence常用

3、Allegro的属性设定Allegro界面介绍：Option(选项)：显示正在使用的命令。

Find（选取）Design Object Find Filter选项：Groups(将1个或多个元件设定为同一组群)Comps（带有元件序号的Allegro元件）Symbols（所有电路板中的Allegro元件）Functions（一组元件中的一个元件）Nets（一条导线）Pins(元件的管脚)Vias（过孔或贯穿孔）Clines（具有电气特性的线段：导线到导线；导线到过孔；过孔到过孔）Lines（具有电气特性的线段：如元件外框）Shapes（任意多边形）Voids（任意多边形的挖空部分）Cline Segs(在clines中一条没有拐弯的导线)Other Segs(在line中一条没有拐弯的导线)Figures（图形符号）DRC errors（违反设计规则的位置及相关信息）Text（文字）Ratsnets（飞线）Rat Ts（T型飞线）Find By Name选项类型选择：Net网络；Symbol符号；Devtype设备类型；Property属性；Group分组类别选择:Name（在左下角填入）元件名称；List列表；ObjecttypeVisiblity(层面显示)View栏Conductors栏：针对所有走线层做开和关Planes栏：针对所有电源/地层做开和关Etch栏：走线Pin栏：元件管脚Via栏：过孔Drc栏：错误标示All栏：所有层面和标示定制Allegro环境文件类型：.brd(普通的电路板文件).dra(Symbols或Pad的可编辑保存文件).pad（Padstack文件，在做symbol时可以直接调用）.psm（Library文件，保存一般元件）.osm(Library文件，保存由图框及图文件说明组成的元件).bsm(Library文件，保存由板外框及螺丝孔组成的元件).fsm(Library文件，保存特殊图形元件，仅用于建立Padstack的Thermal Relief) .ssm(Library文件，保存特殊外形元件，仅用于建立特殊外形的Padstack).mdd(Library文件，保存module definition).tap(输出的包含NC drill数据的文件).scr（Script和macro文件）.art(输出底片文件).log（输出的一些临时信息文件）.color(view层面切换文件).jrl(记录操作Allegro的事件的文件)设定Drawing Size（setup\Drawing size....）设定Drawing Options(setup\Drawing option....)status:on-line DRC(随时执行DRC)Default symbol heightDisplay：Enhanced Display Mode:Display drill holes:显示钻孔的实际大小Filled pads：将via 和pin由中空改为填满Cline endcaps：导线拐弯处的平滑Thermal pads：显示Negative Layer的pin/via的散热十字孔设定Text Size（setup\Text Size....）设定格子（setup \grids...）Grids on:显示格子Non-Etch:非走线层All Etch:走线层Top：顶层Bottom：底层设定Subclasses选项（setup\subclasses...）添加\删除LayerNew Subclass..设定B/Bvia(setup\Vias\Define B/Bvia...)设定工具栏同其他工具，元件的基本操作元件的移动：（Edit\Move\Options...)Ripup etch：移动时显示飞线Stretch etch：移动时不显示飞线元件的旋转：（Edit\Spin\Find\Symbol）元件的删除：（Edit\Delete）信号线的基本操作：更改信号线的宽度（Edit\Change\Find\Clines）option\linewidth删除信号线（Edit\Delete）改变信号线的拐角（Edit\Vertex）删除信号线的拐角（Edit\Delete Vertex）显示详细信息：编辑窗口控制菜：常用元件属性（Hard_Location/Fixed）常用信号线的属性一般属性：NO_RAT；去掉飞线长度属性：propagation_delay等长属性：relative_propagation+delay差分对属性：differential pair设定元件属性(Edit\Properities\)元件加入Fixed属性：（Edit\Properities\find\comps..）设置(删除)信号线：Min_Line_width:(Edit\Properities\find\nets)设定差分对属性：setup\Electrical constraint spread sheet\Net\routing\differential pair§4、高速PCB设计知识（略）§5、建立元件库：通孔焊盘的设计：1、定义：类型Through，中间层（fixed），钻孔Drill/slot（圆形，内壁镀锡plated，尺寸）2、层的定义：BEGIN Layer（Top）层：REGULAR-PAD ＜THERMAL-PAD ＝ANTI-PADEND LAYER（同BEGIN,常用copy begin layer, then paste it）TOP SOLDERMASK:只定义REGULAR-PAD ，大于（Begin layer层regular-pad,约为1.1~1.2倍）BOTTOM SOLDERMASK（同Top soldermask,常用Top soldermask, then paste it）例1 //---------------------------------------------------------------------------------------Padstack Name: PAD62SQ32D*Type: Through*Internal pads: Fixed*Units: MILSDecimal places: 4Layer Name Geometry Width Height Offset (X/Y) Flash Name Shape Name------------------------------------------------------------------------------------------------------------------*BEGIN LAYER*REGULAR-PAD Square 62.0000 62.0000 0.0000/0.0000*THERMAL-PAD Circle 90.0000 90.0000 0.0000/0.0000*ANTI-PAD Circle 90.0000 90.0000 0.0000/0.0000*END LAYER（同BEGIN,常用copy paste）DEFAULT INTERNAL（Not Defined ）*TOP SOLDERMASK*REGULAR-PAD Square *75.0000 75.0000 0.0000/0.0000*BOTTOM SOLDER MASK*REGULAR-PAD Square *75.0000 75.0000 0.0000/0.0000TOP PASTEMASK（Not Defined ）BOTTOM PASTEMASK（Not Defined ）TOP FILMMASK（Not Defined ）BOTTOM FILMMASK（Not Defined ）NCDRILL32.0000 Circle-Drill Plated Tolerance: +0.0000/-0.0000 Offset: 0.0000/0.0000DRILL SYMBOLSquare 10.0000 10.0000－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－表贴焊盘的设计：1、定义，类型single，中间层（option），钻孔（圆形，内壁镀锡plated，尺寸一定为0）2、层的定义：BEGIN Layer（Top）层：只定义REGULAR-PADTOP SOLDERMASK:只定义REGULAR-PAD ，大于（Begin layer层regular-pad,约为1.1~1.2倍）例2 －－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－Padstack Name: SMD86REC330*Type: Single*Internal pads: Optional*Units: MILSDecimal places: 0Layer Name Geometry Width Height Offset (X/Y) Flash Name Shape Name------------------------------------------------------------------------------------------------------------------*BEGIN LAYER*REGULAR-PAD Rectangle 86 330 0/0THERMAL-PAD Not DefinedANTI-PAD Not DefinedEND LAYER（Not Defined ）DEFAULT INTERNAL（Not Defined ）*TOP SOLDERMASK*REGULAR-PAD Rectangle 100 360 0/0BOTTOM SOLDERMASK（Not Defined ）TOP PASTEMASK（Not Defined ）BOTTOM PASTEMASK（Not Defined ）TOP FILMMASK（Not Defined ）BOTTOM FILMMASK（Not Defined ）NCDRILL（Not Defined ）DRILL SYMBOLNot Defined 0 0－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－手工建立元件（主要包含四项：PIN;Geometry:SilkScreen/Assembly;Areas:Boundary/Height;RefDes：SilkScreen/Display）注意：元件应放置在坐标中心位置，即(0,0)1、File\new..\package symbol2、设定绘图区域：Setup\Drawing size...\Drawing parameter\...3、添加pin：选择padstack ，放置，右排时改变text offset（缺省为-100,改为100）置右边4、添加元件外形：（Geometery）*丝印层Silkscreen：Add\Line(Option\Active:package geometery;subclass:silkscreen_top)*装配外框Assembly：Add\Line(Option\Active:package geometery;subclass:Assembly_top)5、添加元件范围和高度：（Areas）*元件范围Boundary:Setup\Areas\package boundary....Add Line(Option\Active Class:Package geometry;subclass:Package_bound_top)*元件高度Height:Setup\Areas\package Height....Add Line(Option\Active Class:Package geometry;subclass:Package_bound_top)6、添加封装标志：（RefDes）Layout\Labels\ResDs...）*底片用封装序号（ResDes For Artwork）:Pin1附近（...RefDes:Silkscreen_Top)*摆放用封装序号（ResDes For Placement）:封装中心附近（...RefDes:Display_Top)*封装中心点（Body center）:指定封装中心位置(Add\Text\Package Geometery:Boby_centre) 7、建立Symbol文件：File\Create Symbol利用向导建立§5、建立电路板1、建立Mechanical Symbol(File\New...\mechanical symbol)绘制外框（outline）：Options\Board geometry:outline添加定位孔：Options\padstack倾斜拐角:（dimension\chamfer）尺寸标注：Manfacture\Dimension/Draft\Parameters...设定走线区域：shape\polygon...\option\route keepin:all设置摆放元件区域：Edit\z-copy shape...\options\package keepin:all;size:50.00;offset:xx设置不可摆放元件区域：setup\areas\package keepout....options\package keepout:top设定不可走线区域：setup\areas\route keepout....options\route keepout:top保存（File\save:xx.dra）§6、建立电路板（File\New...\board）建立文件放置外框Mechanical symbols和PCB标志文件Fomat symbols：Place\Manually...placement list\Mechanical symbols。

PCB&FPC专业英语

PCB专用词语A aA.O.I(Automatic Optical Inspection) 自动光学检查Acceptable quality level (AQL) 可接受质量水平Accuracy 精确度Activating 活化Active carbon treatment 活性碳处理After Pressed Thickness 压板后之厚度Alignment 校直，结盟Annular ring 锡圈Anti-Static Bag 静电胶袋Apparatus 设备，仪器Area 面积Artwork 菲林Artwork Drawing 菲林图形Artwork Film 原装菲林Artwork Modification 菲林修改Artwork No. 菲林编号Assembly 组装，装配Axis 轴B bBackplane 背板Back-up 垫板Baking 烘板Ball Grid Array (BGA) 球栅阵列Bare board 裸板Base Copper 底铜Base material 基材Bevelling 斜边Black Oxide 黑氧化Blind via hole 盲孔Blistering 起泡/水泡Board Cutting 开料Board Thickness 板厚Bottom side 底层Breakaway tab 打断点Brushing 磨刷Build-up 积层Bullet pad 子弹盘Buried hole 埋孔C cC/M(Component Marking) 元件字符Carbon ink 碳油Carrier 带板Ceramic substrate 陶瓷Certificate of Compliance 合格证书Chamfer 倒角Chemical cleaning 化学清洗Chemical corrosion 化学腐蚀Chip Scale Package (CSP) 晶片比例包装Circuit 线路Clearance 间距/间隙Color 颜色Component Side(C/S) 元件面Composite layers 复合层Computer Aided Design (CAD) 电脑辅助设计Computer Aided Manufacturing (CAM) 电脑辅助制作Computer Numerial Control (CNC) 数控Conductor 导体Conductor width/space 导体线宽/线隙Contact 接点Copper area 铜面积Copper clad 铜箔Copper foil 铜箔Copper plating 电镀铜Corner 角线Corner mark 板角记号Corner REG.Hole 角位对位孔Cracking 裂缝Creasing 皱折Criteria 规格,标准Crossection area 切面Cu/Sn Plating 镀铜锡Current efficiency 电流效率Customer 客户Customer Drilling File 客户钻孔资料Customer P/N 客户产品编号D dD/F Registration Hole 干菲林对位孔D/F(Dry Film) 干膜Date Code 日期代号Datum hole 基准参考孔Daughter board 子板Deburring 去毛刺Defect 缺陷Definition 定义Delamination 分层Delay 耽搁Delivery 交货Densitomefer 透光度计Density 密度Department 部门Description 说明Design origin 设计原点Desmear 去钻污,除胶Dessicant 防潮珠Developer 显影液,显影机Diamond 钻石Diazo film 重氮片Dielectric breakdown 介电击穿Dielectric constant 介电常数Dielectric Thickness 介电层厚度Dielectric V oltage Test 绝缘测试Dimension 尺寸Dimensional stability 尺寸稳定性Direct/indirect 直接/间接Distribution 发放Document type 文件种类Documentation Control 文件控制Double sided board 双面板Drill bit 钻咀Drilling 钻孔Drilling Roughness 钻孔粗糙度Dry Film 干菲林Dry Film-Pattern 干膜线路Dynamic 动态E eECN(Engineering Change Notification) 工程更改通知Effective date 有效期Electrical Test Fixture 电测试针床Electro migration 漏电Electroconductive paste 导电胶Electroless 无电沉Electroless copper 无电沉铜Electroless Ni 无电沉镍Electroless Gold/Au 无电沉金Engineering drawing 工程图纸Entek 有机涂覆Epoxy glass substrate 环氧玻璃基板Epoxy resin 环氧基树脂Etch 蚀刻Etchback 凹蚀Etching 蚀刻E-Test Marking 电测试标记E-Test(Electrical Test) 电测试Exposure 曝光External layer 外层F fFiducial mark 基准点Filling 填充Film Fabrication 菲林制作Final QC 最终检查Finish Overall Board Thickness 成品总板厚度Fixture 夹具Flammability 可燃性Flash Gold 薄金Flexible 易曲的,能变形的Flux 助焊剂G gGeneral information 一般资料Ghost image 重影Glass transition temperature 玻璃化湿度Gold Finger(G/F) 金手指Golden board 金板Grid 网格Ground plane 地线层H hHAL(Hot Air Leveling) 热风整平Hand Rout 手锣Hardness 硬度Heat Sealed 热密封Heat Shrink-warp 热收缩Holding time 停留时间Hole 孔Hole breakout 破环Hole density 孔的密度Hole Diameter 孔径Hole location 孔位Hole Location Chart 孔位座标表Hole Position Tolerance 孔位误差Hole size 孔尺寸Hot Air Leveling(HAL) 热风整平Humidity 湿度IIdentification 标识,指标Image 影像Imaging transfer 图形转移Impedance 阻抗Impedance Test 阻抗测试Inner copper foil 内层铜箔Inspection 检验Insulation resistance Test 绝缘测试Inter Plane Separation 内层分离Interleave Paper 隔纸Internal layer 内层Internal stress 内应力Ionic cleanliness 离子清洁度Isolation 孤立Isolation Resistance 绝缘电阻Item 项目K kKEY board 按键盘Key slot 槽孔Kraft paper 牛皮纸L lLaminate 板材Laminate Thickness 材料厚度Lamination void 层间空洞Landless hole 破孔Laser plotter 激光绘图机Laser plotting 激光绘图Laser via hole 激光穿孔Layup 层压配本Lay-up Instruction 压板指示Legend 字符Legend Width 字符宽度Length 长度Lifted Lands 残铜Line Width 线宽Liquid 液体Logic diagram 逻辑图形Logo 唛头,标记Lot size 批卡Mesh 目数M mMark 标记Master drawing 菲林图形Material Thickness 材料厚度Material Type 材料类型Max. X-out 坏板上限Max.Board Thickness After Plating 电镀后总板厚度之上限Measling 白斑Mech Drawing No. 图纸编号Mechanical cleaning 机械清洗Metal 金属Method 方法MI(Manufacturing Instruction) 生产制作指示Microstrip 微条线Min Conductor Copper Thickness 最小线路铜厚Min Hole Wall Copper Thickness 最小孔壁铜厚Min. Gold Plating Thickness 最小金厚Min. Nickel Thickness 最小镍厚Min. Tin-Lead Thickness (After HAL) （喷锡后）最小锡厚Min.Annular Ring 最小环宽Min.Spacing between Line to Line 线与线之间的最小距离Min.Spacing between Line to Pad 线与焊盘之间的最小距离Min.Spacing between Pad to Pad 焊盘与焊盘之间的最小距离Minimum 最小Mirroring 镜像Missing 缺少Model No. 产品名称Molded 模塑Mother board 主板Moulding 模房Mounting hole 安装孔Multilayer 多层板Multi-layer Laminate 多层板材料N nNegative 反面的Net list 网络表Nick 缺口No. of holes 孔数No.of Array/Panel 每个拼板套板数No.of Panel per Stack 每叠板数No.of Panel/Sheet 每张大料拼板数No.of Pcs Per Bag 每包数量No.of Unit/Array 每套单元数Normal value标准值O oOblong 椭圆形的Offset 偏移Open/short 开路/短路Optimization(design) 最佳化(设计)Organic Solerability Peservatives(OSP) 有机保护剂Originator 原作者Outer copper foil 外层铜箔Outline 外形P pPacking 包装Packing 包装Pad 焊盘Panel Area 拼板面积Panel Plated Crack 板镀缺口Panel plating 整板电镀Panel Size 拼板尺寸Panel Size After Outerlayer Cutting 外层切板后拼板尺寸Panel Utilization 拼板利用率Pass rate 通过率Passivation 钝化Pattern 线路Pattern Inspection 线路检查Pattern plating 图形电镀PCB(Printed Circuit Board) 印制线路板Peck drilling 啄钻Peel strength 剥离强度Peelable 可剥性Peelable 剥离强度Peelable Mask 可脱油Peeling 剥离Permanent 永久性PH value PH值Photo plotting 图形输出Photo via hole 菲林过孔Photographers 照片靶标Photoplotler 光绘机Physical 物理的Pin hole 销定孔Pink ring 粉红环Pinning hole 钻孔管位Pitch 间距Placement 放置Plated Though Hole(PTH) 沉铜Plating 电镀Plating Crack 电镀裂缝Plating line 电镀线Plating rack 电镀架Plating V oid 电镀针孔Plug Hole 塞孔Polymer 聚合体Porosity 孔隙率Positive 绝对的Power plane 电源层Prepreg 半固化片Primary side 首面Print 印刷Probe point 针床测点Process 工序Process flow 工序流程Product Planning Dept. 生产计划部Production 生产板Profile 外形Profiling 外形加工Profiling Process 外形加工Project No. 产品编号PTH Thermal Seress Test PTH热冲击测试PTH(Plating Through Hole) 沉铜Pull away 拉离Punch 啤模Punching 冲切Punching Mould Drawing 啤模图形Q qQA Audit 品质审计QA(Quanlity Assurance) 品质部Quad Palt Pack (QFP) 四边扁平林整器件Quantity 数量R rRaw Material Utilization 原材料利用率Recall 回收Rectifier 整流器Register mark 对位点Registration 重合点Remark 备注Resin 树脂Resin Recession 流胶Resist 抗蚀剂Resolution 分辨率Rigid 精密的Roller coating 涂覆Roughening 粗化Round pad 圆盘Routing 外形加工,铣板S sS/M Material 绿油物料S/M(Solder Mask) 阻焊Sales 销售Sample 样板Sampling inspection 抽样检验Scaling factor 缩放比例因素Scope 范围Scoring 刻槽Scratch 划痕Secondary side 第二面Section Code 组别代号Section Code Change 组别代号更改Segment 部分,片段Separated 分离Sequence 顺序Sets 套Sheet Size 大料尺寸Shematic diagram 原理图Shiny 有光泽的,发光的Silk screen 丝印Silver film 银盐片Single/double 单层/双面Slot 槽,坑Solder Mask 阻焊Solder mask on bare copper (smobc) 裸铜覆盖阻焊膜Solder side 焊接面Solder Side C/M 阻焊面字符Solder Side Cir. 焊接面线路Solder Side Circuit 焊接面Solder Side S/M 焊接面阻焊Solderability 可焊性Solvent Test 可溶性测试Spacing 线距Special requirement 特殊要求Specification 详细说明，规范Spindle 主轴Split 裂片Square pad 方块Standard 标准值Static 静态Stencial 网版Step drilling 分布钻Step scale 光梯尺Store 货仓Supplier 供应商Supported hole 支撑点Surface 表面Surface mount technology 表面组装技术Swimming 滑移T tTack 堆起Tape Programming 铬带制作Tape Test 胶带测试Target Hole 目标孔Teardrop 泪珠Template 天平Tenting 封孔Test 测试Test coupon 图样Test Parameter 测试参数Test Pattern 测试孔Testing V oltage 电压Thermal shock 热冲击Thermal stress 热应力Thickness 厚度Tin Content 锡含量Tin/Lead Stripping 退铅锡Tin-lead plating 电镀铅锡Tolerance 公差Top side 板面Touch up 修理(执漏)Training 训练Transmission 传输线Transmittance 传送Trim line 修剪U uUltrasonic cleaning 超声波清洗Undercut 侧蚀Unit Arrangement 单元排版Unit Layout Per Panel 单元拼板图Uv-blocking 阻挡紫外线V vVacunm Pack 真空包装Vacuum lamination 真空压制V-Cut V- 坑View From…观察方向由…Visual & Warpage 可视性和翘曲度Visual inspection 目检V oltage 电压W wW/F(Wet Film) 湿膜Warp & Twist 翘曲和弯曲Wet Film 湿模Width 宽度Wiring 线路。

几款电路仿真软件的对比分析

几款软件的对比分析1. PSpice 仿真软件简介：PSpice属于元件级仿真软件，模型采用spice通用语言编写，移植性强，常用的信息电子电路，是它最适合的场合。

现在使用较多的是 PSpice 8.0,工作于 Windows 环境,占用硬盘空间60M左右，整个软件由原理图编辑、电路仿真、激励编辑、元器件库编辑、波形图等几个部分组成，使用时是一个整体。

PSpice 的电路元件模型反映实际型号元件的特性，通过对电路方程运算求解，能够仿真电路的细节，特别适合于对电力电子电路中开关暂态过程的描述。

主要功能：（1）复杂的电路特性分析，如：蒙特卡罗分析（2）模拟、数字、数模电路仿真（3）集成度提高缺点：（1）不适用于大功率器件（2）采用变步长算法，导致计算时间的延长（3）仿真的收敛性较差。

2. saber仿真软件简介：被誉为全球最先进的系统仿真软件，也是唯一的多技术、多领域的系统仿真产品，现已成为混合信号、混合技术设计和验证工具的业界标准，可用于电子、电力电子、机电一体化、机械、光电、光学、控制等不同类型系统构成的混合系统仿真，这也是saber的最大特点。

Saber最为混合仿真系统，可以兼容模拟、数学、控制量的混合仿真，便于在不同层面撒谎那个分析和解决问题，其他仿真软件不具备这样的功能。

Saber的仿真真实性很好，从仿真的电路到实际的电路实现，期间参数基本不用修改。

主要功能：（1）原理图输入和仿真（2）数据可视化和分析（3）模型库（4）建模缺点：操作较复杂，原理图仿真常常不收敛导致仿真失败，很占系统资源，环路扫频耗时太长（以几十分钟计）3. PLECS仿真系统简介：被全球众多知名公司的研发工程师誉为“全球最专业的系统级电力电子电路仿真系统”，也是一个用于电路和控制结合的多功能仿真软件，尤其适用于电力电子和传动系统。

PLECS独立版本已于2010年开发，自此PLECS脱离MATLAB/Simulink。

PLECS独立版具有控制元件库和电路元件库，采用优化的解析方法，仿真速度更快，比PLECS嵌套版本快2.5倍。

cadence使用方法

cadence使用方法一焊盘制作1. smt焊盘1）所有程序→cadence SPB15.7→PCB edit utilities→Pad designer;2) parameter选项中: type选single ，internal layer 选option，Unit 选毫米或mi l；3）layer 选项中设置焊盘：选Begin layer→regular pad 设置焊盘形状和大小；thermal relief 和anti pad 选NULL；4）取名SAVE as存盘。

2．通孔焊盘1）所有程序→cadence SPB15.7→PCB edit utilities→Pad designer;2) parameter选项中: type选through，internal layer 选option,Unit 选毫米或mi l；设置焊盘钻孔大小，焊盘字符（可不设）；3）layer 选项中设置焊盘：选Begin layer→regular pad 设置焊盘形状和大小；thermal relief 和anti pad 比焊盘大0.8或1mm，同样设置end layer(底层),soldermask_top、soldermask_bottom设置比焊盘大0.15mm，paste_top、paste_bottom设置成与焊盘一样大。

4）取名save as存盘。

二封装制作1.所有程序→cadence SPB15.7→pcb editor→Allegro PCB designe XL;2．File→new,弹出New Drawing对话框，输入文件名，在Drawing type中选Package symbol→OK;3．设置绘画尺寸：Setup→drawing size ，分别设置类型、单位、左下角座标、绘图区宽、高→OK；4. 设置栅格：setup grid,将所有层栅格设为0.0254或1mil→OK；5. Layout→pins ，Options中选connect,选定焊盘、设置重复放置形式;6. 重复放置所有焊盘；7．放置元件边界区，用于DRC检查（通常与元器件一样大，与其外形丝印一样大）：Add→Rectange,右边Option中选Package geometry和place bound_top,绘制边界(此项可以不做);8．添加零件外框（集成电路再增加1脚标识）：Add→line ,选package geometry和silkscreen_top选项，在line width文本框中输入线的粗度；同样方法在Assembly_top 层添加同样图形(可不用)；9．增加Ref Des层零件标号：Layout→Labels→Refdes,打开Option选项，选择Silkscreen_Top,单击1脚附近，输入标号如U*，D*，R*之类，同样方法在Assembly_top层添加同样图形；10.取名save as存盘。

Mentor公司Layout术语词汇解析

Mentor公司Layout术语词汇解析A flag标记指定的标记。

创建后，靠近符号名称的地方，字母A出现在PACKAGE元件摘要窗口和符号编辑窗口的标志行里。

字母A代表PAC KAGE分配该符号到一个部件编码，并且检查过该分配，不需要再创建该符号。

abrasive trim研磨修整一个混合台术语，使用定向空气研磨剂在电阻器开槽，上调一个薄膜电阻的值。

厚膜混合电路制造工艺可以使用空气研磨剂修整。

absolute coordinate system绝对坐标系一个关于笛卡尔坐标系的热分析术语，用来输入点位置。

在自动热分析里，这些坐标是两条直线之间的距离。

原点和绝对坐标系的方向是固定的,从而为geometry位置、元件插入、编辑操作和其他坐标系的操作充当一个永久的参考点。

参见三角坐标系和极坐标系。

active geometry活动的geometry你可以编辑的geometry。

该活动的几何活动形状是在当前编辑窗口里的geometry。

一个高亮度显示窗框标明该活动编辑窗口。

active trim路的功能调整。

有源修整能够补偿半有源修整一个混合电路工作台术语,通常是通过修整一个电阻值来实现工作电导体参数变化、电阻和电容公差或者一个累积公差的组合物。

active window活动窗口接受你输入的窗口。

活动窗口具有高亮框。

actual shape实际形状一个实际上连接到一个电路的铜色区域。

区域填充输入形状的边界之内存在一个实际的形状。

一实际的形状不是可选择的；所有对填充区域的编辑是以选择的输入形状为基础的。

ambient temperature周围温度一个印刷电路板围绕着流动的温度。

在热分析里，周围温度在PCB上每一个成分的上面自由流动。

周围温度以对流方式在一个发热面之上流出，比如空气担当一个散热器。

表面温度比周围温度要高，对流热传导从热的表面到较冷的流动，推动表面和周围的温差。

参见有限元法和散热器。

AMPLE高级多用的语言的简称，Mentor Graphics为指定用户定制的扩展语言。

ALLEGRO封装教程

一、手工制作封装1、打开“PAD Designer”如下界面按实际需求填好后保存，如保存为cd160X30注：阻焊层比助焊层大约1MM即可2，启动Allegro PCB Ediror 选择“File”-“New”弹出对话框3、点击OK进入编辑界面，选择“SETUP”-“Design Parameters”弹出窗口4、选择“SETUP”-“Grids”打开以下窗口设置5.选择“SETUP”-“User Preference”打开以下界面6，添加管脚焊盘。

选择“LAYOUT”---“PINS”或者图标，然后设置控制面板”options”标签页中的相关选项7，设置好后，在命令窗口中输入放置的坐标如( x 0 0)按回车键确定添加。

注意，输入坐标时x要用小字母加空格8焊盘放置完成后添加Place_Bound_Top(放置约束)。

选择”SETUP”—“Areas-“—“Package Boundary”选项。

设置控制面板的”Options”然后用坐标输入放置9、设置封装限制高度，选择”SETUP”—“Areas-“—“Package Height”选项。

然后选择该封装。

设置控制面板的”Options”10、添加丝印外框。

选择“Add”—“Line”选项，设置控制面板中“Options”然后按封装要求画出丝印框11.添加标签，选择“LAYOUT”--“LABELS”—“RefDes”选择。

设置控制面板中“Options”单击屏幕区域出现文本输入框，输入标签如U* j* REF 右键单击选择“DONE ”12，选择“File”---“Save”选项，保存元件封装二、O RCAD和ALLEGRO交互式布局1，打开原理图，选中文件，然后选择“options”-----“Preferences”出现下界面三、更改坐标原点的方式1、打开文件，选择“SETUP”--“Design Parameter Editor”弹出以下界面2，第2种方式，选择“SETUP”—“Change Drawing Origin”然后单击需要设置成为坐标原点的地方四、O r CAD导出网络表打开原理图文件，选择设计文件，选择“Tloos”--“Create Netlst”弹出以下界面五、ALLEGRO导入网络表1，设置路径：选择“SETUP”-“User Preference”打开以下界面2、选择“File”--“Import”---“Logic”弹出以下界面。

生成光绘文件

钻孔文件设置一．钻孔参数设置：Manufacture——>NC——>NC P arameters1. P arameters file文件是txt格式，默认路径是当前工作目录；2. Header：在输出文件中指定一个或多个ASCII 文件，默认值为none，可不设置；3.Leader：指定在数据的引导长度。

4.Code：ASCII/EIA，指定数据的输出格式，默认为ASCII。

Excellon format（钻孔格式）1.Format：输出NC DRILL 文件中坐标数据的格式，整数（设置为3）及小数部分位数（设置为5（表示小数位后两位））（精度），要与Artwork基本参数设置匹配；2.Offset X: Y: 指定坐标数据与图纸原点的偏移量。

3. Coordinates:Absolute.Incremental输出的文件是相对坐标还是绝对坐标。

选用绝对值Absolute；4.Output units:输出数据单位选择；5.Leading zero suppression:前省零；6.Trailing zero suppression: 后省零；7.Equal coordinate suppression: 简化相同的坐标；8.Enhanced Excellon format:选择在NC Drill 和NC Route 输出文件中产生。

二．更新设计文件：Manufacture——>NC——> Drill Customization，单击Auto generatesymbols自动生成钻孔标记，再点击OK，弹出对话框确认即可。

三：设置生成钻孔表1.设置显示：关闭所有显示，仅打开Board Geomtry——>outline；2.Manufacture——>NC——>Drill Legenda)设置输出单位；b)排列方式可以不关注；c)Legends项根据PCB属性设置，有盲孔或埋孔则选择By layer；d)设置好，点击OK后，鼠标上会出现一个框，即是钻孔表的，选择好位置后点击鼠标放置，并且在Boardoutline中会显示钻孔图；Template file：钻孔图例表格的模板文件，默认为default-mil.dlt。

PCB常用英语

A aA.O.I(Automatic Optical Inspection)自动光学检查Acceptable quality level (AQL)可接受质量水平Accuracy精确度Activating活化Active carbon treatment活性碳处理After Pressed Thickness压板后之厚度Alignment校直，结盟Annular ring锡圈Anti-Static Bag静电胶袋Apparatus设备，仪器Area面积Artwork菲林Artwork Drawing菲林图形Artwork Film原装菲林Artwork Modification菲林修改Artwork No.菲林编号Assembly组装，装配Axis轴B bBackplane背板Back-up垫板Baking 烘板Ball Grid Array (BGA)球栅阵列Bare board裸板Base Copper底铜Base material基材Bevelling斜边Black Oxide黑氧化Blind via hole盲孔Blistering起泡/水泡Board Cutting开料Board Thickness板厚Bottom side底层Breakaway tab打断点Brushing磨刷Build-up积层Bullet pad子弹盘Buried hole埋孔C cC/M(Component Marking)元件字符Carbon ink碳油Carrier带板Ceramic substrate陶瓷Certificate of Compliance合格证书Chamfer倒角Chemical cleaning化学清洗Chemical corrosion化学腐蚀Chip Scale Package (CSP)晶片比例包装Circuit线路Clearance间距/间隙Color颜色Component Side(C/S)元件面Composite layers复合层Computer Aided Design (CAD)电脑辅助设计Computer Aided Manufacturing (CAM)电脑辅助制作Computer Numerical Control (CNC)数控Conductor导体Conductor width/space导体线宽/线隙Contact接点Copper area铜面积Copper clad铜箔Copper foil铜箔Copper plating0电镀铜Corner角线Corner mark板角记号Corner REG.Hole角位对位孔Cracking裂缝Creasing皱折Criterion规格,标准Crossection area切面Cu/Sn Plating镀铜锡Current efficiency电流效率Customer客户Customer Drilling File客户钻孔资料Customer P/N客户产品编号D dD/F Registration Hole干菲林对位孔D/F(Dry Film)干膜Date Code日期代号Datum hole基准参考孔Daughter board子板Deburring去毛刺Defect缺陷Definition定义Delamination分层Delay耽搁Delivery交货Densitomefer透光度计Density密度Department部门Description说明Design origin设计原点Desmear去钻污,除胶Dessicant防潮珠Developer显影液,显影机Diamond钻石Diazo film重氮片Dielectric breakdown介电击穿Dielectric constant介电常数Dielectric Thickness介电层厚度Dielectric Voltage Test绝缘测试Dimension尺寸Dimensional stability尺寸稳定性Direct/indirect直接/间接Distribution发放Document type文件种类Documentation Control文件控制Double sided board双面板Drill bit钻咀Drilling钻孔Drilling Roughness钻孔粗糙度Dry Film 干菲林Dry Film-Pattern干膜线路Dynamic动态E eECN(Engineering Change Notification)工程更改通知Effective date有效期Electrical Test Fixture电测试针床Electro migration漏电Electroconductive paste导电胶Electroless无电沉Electroless copper无电沉铜Electroless Ni无电沉镍Electroless Gold/Au无电沉金Engineering drawing工程图纸Entek有机涂覆Epoxy glass substrate环氧玻璃基板Epoxy resin环氧基树脂Etch蚀刻Etchback凹蚀Etching蚀刻E-Test Marking电测试标记E-Test(Electrical Test)电测试Exposure曝光External layer外层F fFiducial mark基准点Filling填充Film Fabrication菲林制作Final QC最终检查Finish Overall Board Thickness成品总板厚度Fixture夹具Flammability可燃性Flash Gold薄金Flexible易曲的,能变形的Flux助焊剂G gGeneral information一般资料Ghost image重影Glass transition temperature玻璃化湿度Gold Finger(G/F)金手指Golden board金板Grid网格Ground plane地线层H hHAL(Hot Air Leveling)热风整平Hand Rout手锣Hardness硬度Heat Sealed热密封Heat Shrink-warp热收缩Holding time停留时间Hole孔Hole breakout破环Hole density孔的密度Hole Diameter孔径Hole location孔位Hole Location Chart孔位座标表Hole Position Tolerance孔位误差Hole size孔尺寸Hot Air Leveling(HAL)热风整平Humidity湿度IIdentification标识,指标Image影像Imaging transfer图形转移Impedance阻抗Impedance Test阻抗测试Inner copper foil 内层铜箔Inspection检验Insulation resistance Test绝缘测试Inter Plane Separation内层分离Interleave Paper隔纸Internal layer内层Internal stress内应力Ionic cleanliness离子清洁度Isolation孤立Isolation Resistance绝缘电阻Item项目K kKEY board按键盘Key slot槽孔Kraft paper牛皮纸L lLaminate板材Laminate Thickness材料厚度Lamination void 层间空洞Landless hole破孔Laser plotter激光绘图机Laser plotting激光绘图Laser via hole激光穿孔Layup层压配本Lay-up Instruction压板指示Legend字符Legend Width字符宽度Length长度Lifted Lands残铜Line Width线宽Liquid液体Location位置Logic diagram逻辑图形Logo唛头,标记Lot size批卡M mMark标记Master drawing菲林图形Material Thickness材料厚度Material Type材料类型Max. X-out坏板上限Max.Board Thickness After Plating电镀后总板厚度之上限Measling白斑Mech Drawing No.图纸编号Mechanical cleaning机械清洗Metal金属Method方法MI(Manufacturing Instruction)生产制作指示Microstrip微条线Min Conductor Copper Thickness最小线路铜厚Min Hole Wall Copper Thickness最小孔壁铜厚Min. Gold Plating Thickness最小金厚Min. Nickel Thickness最小镍厚Min. Tin-Lead Thickness (After HAL)（喷锡后）最小锡厚Min.Annular Ring最小环宽Min.Spacing between Line to Line线与线之间的最小距离Min.Spacing between Line to Pad线与焊盘之间的最小距离Min.Spacing between Pad to Pad焊盘与焊盘之间的最小距离Minimum 最小Mirroring镜像Missing 缺少Model No.产品名称Molded模塑Mother board主板Moulding模房Mounting hole安装孔Multilayer多层板Multi-layer Laminate多层板材料N nNegative反面的Net list网络表Network网络Nick缺口No. of holes孔数No.of Array/Panel每个拼板套板数No.of Panel per Stack每叠板数No.of Panel/Sheet每张大料拼板数No.of Pcs Per Bag每包数量No.of Unit/Array每套单元数Normal value标准值O oOblong椭圆形的Offset 偏移Open/short开路/短路Optimization(design)最佳化(设计)Organic Solerability Peservatives(OSP)有机保护剂Originator原作者Outer copper foil外层铜箔Outline外形P pPacking包装Packing包装Pad焊盘Panel Area拼板面积Panel Plated Crack板镀缺口Panel plating整板电镀Panel Size拼板尺寸Panel Size After Outerlayer Cutting外层切板后拼板尺寸Panel Utilization拼板利用率Pass rate通过率Passivation钝化Pattern线路Pattern Inspection线路检查Pattern plating图形电镀PCB(Printed Circuit Board)印制线路板Peck drilling啄钻Peel strength 剥离强度Peelable可剥性Peelable 剥离强度Peelable Mask可脱油Peeling剥离Permanent永久性PH value PH值Photo plotting图形输出Photo via hole菲林过孔Photographers照片靶标Photoplotler光绘机Physical物理的Pin hole销定孔Pink ring粉红环Pinning hole钻孔管位Pitch间距Placement放置Plated Though Hole(PTH)沉铜Plating电镀Plating Crack电镀裂缝Plating line电镀线Plating rack电镀架Plating Void电镀针孔Plug Hole塞孔Polymer聚合体Porosity孔隙率Positive绝对的Power plane电源层Prepreg半固化片Primary side首面Print印刷Probe point针床测点Process工序Process flow工序流程Product Planning Dept.生产计划部Production生产板Profile外形Profiling 外形加工Profiling Process外形加工Project No.产品编号PTH Thermal Seress Test PTH热冲击测试PTH(Plating Through Hole)沉铜Pull away拉离Punch啤模Punching冲切Punching Mould Drawing啤模图形Q qQA Audit品质审计QA(Quanlity Assurance)品质部Quad Palt Pack (QFP)四边扁平林整器件Quality质量Quantity数量R rRaw Material Utilization原材料利用率Recall回收Rectifier整流器Register mark对位点Registration重合点Remark备注Resin树脂Resin Recession流胶Resist抗蚀剂Resolution分辨率Rigid精密的Roller coating涂覆Roughening粗化Round pad圆盘Routing外形加工,铣板S sS/M Material绿油物料S/M(Solder Mask)阻焊Sales 销售Sample样板Sampling inspection抽样检验Scaling factor缩放比例因素Scope范围Scoring刻槽Scratch划痕Secondary side第二面Section Code组别代号Section Code Change组别代号更改Segment部分,片段Separated分离Sequence顺序Sets套Sheet Size大料尺寸Shematic diagram原理图Shiny有光泽的,发光的Silk screen丝印Silver film银盐片Single/double单层/双面Slot 槽,坑Smear污点Solder Mask阻焊Solder mask on bare copper (smobc)裸铜覆盖阻焊膜Solder side焊接面Solder Side C/M阻焊面字符Solder Side Cir.焊接面线路Solder Side Circuit焊接面Solder Side S/M焊接面阻焊Solderability可焊性Solvent Test可溶性测试Spacing线距Special requirement 特殊要求Specification详细说明，规范Spindle主轴Split裂片Square pad方块Standard标准值Static静态Stencial网版Step drilling分布钻Step scale光梯尺Store货仓Supplier供应商Supported hole支撑点Surface表面Surface mount technology表面组装技术Swimming滑移T tTack堆起Tape Programming铬带制作Tape Test胶带测试Target Hole目标孔Teardrop 泪珠Template天平Tenting封孔Test测试Test coupon图样Test Parameter测试参数Test Pattern测试孔Testing Voltage电压Thermal shock热冲击Thermal stress热应力Thickness厚度Tin Content锡含量Tin/Lead Stripping退铅锡Tin-lead plating电镀铅锡Tolerance公差Top side板面Touch up修理(执漏) Training训练Transmission传输线Transmittance传送Trim line修剪U uUltrasonic cleaning超声波清洗Undercut侧蚀Unit Arrangement单元排版Unit Layout Per Panel单元拼板图Uv-blocking 阻挡紫外线V vVacunm Pack真空包装Vacuum lamination真空压制V-Cut V- 坑View From…观察方向由…Visual & Warpage可视性和翘曲度Visual inspection目检Voltage 电压W wW/F(Wet Film)湿膜Warp & Twist翘曲和弯曲Wet Film湿模Width宽度Wiring线路。

PCB坐标文件的导出方法与步骤

AD系列软件导出工厂所需坐标文件的方法如下：1、设置坐标原点：由于不同的贴片机器对于板子的坐标原点设定一般是不同的，我们可以任意选曲一种机器作为默认的坐标原点。

譬如说FUJI的贴片机一般是以PCB左下角为坐标原点，我们就在菜单里面选取“编辑(E)”－>“原点（O）”->“设置(S)”，然后将鼠标移动到PCB左下角，电鼠标左键确定即可。

2、导出坐标数据：导出坐标数据的方法和99se不同，我们需要在选取“文件(F)”->“装配输出(B)”->“Generates pick and place files”,点击之后出现选取输出的文件格式和输出坐标的单位，我们一般是选择TXT和公制的，这个根据不同的需求来选择；然后再点击确定，AD就会将坐标文件输出，输出的文件储存在早先设定的项目输出文件的目录里。

2011-9-23以下来自互联网：PCB坐标文件的导出方法与步骤本文来自: 原文网址：/articlescn/pcb/0079881.html.PCB坐标文件的导出方法与步骤现代电子生产企业的设计部门几乎全部采用PCB软件进行电路设计，生产制造部门也大量使用贴片机、插件机等自动化设备进行生产，如何在这两者之间建立起有效的联系，进而提高生产效率、降低生产成本是工艺技术人员研究的目标。

事实上，SMT生产线中加工设备编程所需的大多数特征数据完全可以从PCB设计文件中获取，例如元件在PCB 上的位置坐标、PCB的整体描述数据等等。

我们可以直接从PCB设计文件中导出相应的CAD 坐标数据，并与设计部门提供的BOM（Bill of Material，物料表）文件合并后转换为能驱动贴片设备运行的贴片程序，然后通过磁盘、U 盘、网络或RS-232C 接口等传送到加工设备的控制计算机中直接驱动数控加工设备。

这样不仅节省了数据准备及编程时间，也提高了数据精度、杜绝了人工处理数据时所出现的差错和数据不完整性。

微尔赛米精密LVDS传输缓冲器数据手册说明书

1FeaturesInputs/Outputs •Accepts differential or single-ended input •LVPECL, LVDS, CML, HCSL, LVCMOS •Six precision LVDS outputs •Operating frequency up to 750 MHzPower •Option for 2.5 V or 3.3 V power supply •Current consumption of 93 mA•On-chip Low Drop Out (LDO) Regulator for superior power supply noise rejectionPerformance •Ultra low additive jitter of 104 fs RMSApplications•General purpose clock distribution •Low jitter clock trees •Logic translation•Clock and data signal restoration•Wired communications: OTN, SONET/SDH, GE, 10 GE, FC and 10G FC•PCI Express generation 1/2/3 clock distribution •Wireless communications•High performance microprocessor clock distributionApril 2014Figure 1 - Functional Block DiagramZL40216Precision 1:6 LVDS Fanout BufferData SheetOrdering InformationZL40216LDG1 32 Pin QFN TraysZL40216LDF132 Pin QFN Tape and ReelMatte TinPackage Size: 5 x 5 mm-40o C to +85o CTable of ContentsFeatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Change Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.0 Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73.1 Clock Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73.2 Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123.3 Device Additive Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153.4 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163.4.1 Sensitivity to power supply noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163.4.2 Power supply filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163.4.3 PCB layout considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164.0 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175.0 Performance Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196.0 Typical Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207.0 Package Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218.0 Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22List of FiguresFigure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3 - LVPECL Input DC Coupled Thevenin Equivalent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4 - LVPECL Input DC Coupled Parallel Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 5 - LVPECL Input AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 6 - LVDS Input DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 7 - LVDS Input AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 8 - CML Input AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 9 - HCSL Input AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 10 - CMOS Input DC Coupled Referenced to VDD/2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 11 - CMOS Input DC Coupled Referenced to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 12 - Simplified LVDS Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 13 - LVDS DC Coupled Termination (Internal Receiver Termination). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 14 - LVDS DC Coupled Termination (External Receiver Termination) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 15 - LVDS AC Coupled Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 16 - LVDS AC Output Termination for CML Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 17 - Additive Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 18 - Decoupling Connections for Power Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 19 - Differential Voltage Parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 20 - Input To Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Change SummaryBelow are the changes from the February 2013 issue to the April 2014 issue:Page Item Change1Applications Added PCI Express clock distribution.6Pin Description Added exposed pad to Pin Description.7, 8Figure 3 and Figure 4Removed 22 Ohm series resistors from Figure 3 and 4. Theseresistors are not required; however there is no impact toperformance if the resistors are included.18Figure 19Clarification of V ID and V OD.Below are the changes from the November 2012 issue to the February 2013 issue:Page Item Change8Figure 4Changed text to indicate the circuit is not recommended forVDD_driver=2.5V.8Figure 5Changed pull-up and pull-down resistors from 2kOhm to100 Ohm.12Figure 12Changed gate values to +/+ on the left and -/- on the right.1.0 Package DescriptionThe device is packaged in a 32 pin QFNFigure 2 - Pin Connections2.0 Pin DescriptionPin # Name Description3, 6clk_p, clk_n,Differential Input (Analog Input). Differential input signals.28, 27, 26, 25, 24, 23, 18, 17, 16, 15, 14, 13, out0_p, out0_nout1_p, out1_nout2_p, out2_nout3_p, out3_nout4_p, out4_nout5_p, out5_nDifferential Output (Analog Output). Differential outputs.9, 19,22, 32vdd Positive Supply Voltage. 2.5 V DC or 3.3 V DC nominal. 1, 8vdd_core Positive Supply Voltage. 2.5 V DC or 3.3 V DC nominal. 2, 7,20, 21gnd Ground. 0 V.4, 510, 11,12,29,30,31NC No Connection. Leave unconnected.Exposed Pad Device GND.3.0 Functional DescriptionThe ZL40216 is an LVDS clock fanout buffer with six identical output clock drivers capable of operating at frequencies up to 750MHz.Inputs to the ZL40216 are externally terminated to allow use of precision termination components and to allow full flexibility of input termination. The ZL40216 can accept DC coupled LVPECL or LVDS and AC coupled LVPECL, LVDS, CML or HCSL input signals; single ended input signals can also be accepted. A pin compatible device with internal termination is also available.The ZL40216 is designed to fan out low-jitter reference clocks for wired or optical communications applications while adding minimal jitter to the clock signal. An internal linear power supply regulator and bulk capacitors minimize additive jitter due to power supply noise. The device operates from 2.5V+/-5% or 3.3V+/-5% supply. Its operation is guaranteed over the industrial temperature range -40°C to +85°C.The device block diagram is shown in Figure 1; its operation is described in the following sections.3.1 Clock InputsThe ZL40216 is adaptable to support different types of differential and singled-ened input signals depending on the passive components used in the input termination. The application diagrams in the following figures allow the ZL40216 to accept LVPECL, LVDS, CML, HCSL and single-ended inputs.Figure 3 - LVPECL Input DC Coupled Thevenin EquivalentFigure 4 - LVPECL Input DC Coupled Parallel TerminationFigure 5 - LVPECL Input AC CoupledFigure 6 - LVDS Input DC CoupledFigure 7 - LVDS Input AC CoupledFigure 8 - CML Input AC CoupledFigure 9 - HCSL Input AC CoupledFigure 10 - CMOS Input DC Coupled Referenced to VDD/2Figure 11 - CMOS Input DC Coupled Referenced to GroundVDD_driver R1 (kΩ)R2 (kΩ)R3 (kΩ)RA (kΩ) C (pF) 1.5 1.25 3.075open10101.81 3.8open10102.50.33 4.2open10103.30.75open4.21010Table 1 - Component Values for Single Ended Input Reference to Ground* For frequencies below 100 MHz, increase C to avoid signal integrity issues.3.2 Clock OutputsLVDS has lower signal swing than LVPECL which results in a low power consumption. A simplified diagram for the LVDS output stage is shown in Figure 12.Figure 12 - Simplified LVDS Output DriverThe methods to terminate the ZL40216 drivers are shown in the following figures.Figure 13 - LVDS DC Coupled Termination (Internal Receiver Termination)Figure 14 - LVDS DC Coupled Termination (External Receiver Termination)Figure 15 - LVDS AC Coupled TerminationFigure 16 - LVDS AC Output Termination for CML Inputs3.3 Device Additive JitterThe ZL40216 clock fanout buffer is not intended to filter clock jitter. The jitter performance of this type of device is characterized by its additive jitter. Additive jitter is the jitter the device would add to a hypothetical jitter-free clock as it passes through the device. The additive jitter of the ZL40216 is random and as such it is not correlated to the jitter of the input clock signal.The square of the resultant random RMS jitter at the output of the ZL40216 is equal to the sum of the squares of the various random RMS jitter sources including: input clock jitter; additive jitter of the buffer; and additive jitter due to power supply noise. There may be additional deterministic jitter sources, but they are not shown in Figure 17.Figure 17 - Additive Jitter3.4 Power SupplyThis device operates employing either a 2.5V supply or 3.3V supply.3.4.1 Sensitivity to power supply noisePower supply noise from sources such as switching power supplies and high-power digital components such as FPGAs can induce additive jitter on clock buffer outputs. The ZL40216 is equipped with an on-chip linear power regulator and on-chip bulk capacitors to minimize additive jitter due to power supply noise. The on-chip regulation, recommended power supply filtering, and good PCB layout all work together to minimize the additive jitter from power supply noise.3.4.2 Power supply filteringJitter levels may increase when noise is present on the power pins. For optimal jitter performance, the device should be isolated from the power planes connected to its power supply pins as shown in Figure 18. •10 µF capacitors should be size 0603 or size 0805 X5R or X7R ceramic, 6.3 V minimum rating •0.1 µF capacitors should be size 0402 X5R ceramic, 6.3 V minimum rating •Capacitors should be placed next to the connected device power pins • A 0.15 ohm resistor is recommendedZL402161891922320.1 µF 0.1 µFvdd_core10 µF 0.1 µF0.15 Ωvdd0.1 µF 10 µFFigure 18 - Decoupling Connections for Power Pins3.4.3 PCB layout considerationsThe power nets in Figure 18 can be implemented either as a plane island or routed power topology without changing the overall jitter performance of the device.4.0 AC and DC Electrical CharacteristicsAbsolute Maximum Ratings*Parameter Sym.Min.Max.Units 1Supply voltage V DD_R-0.5 4.6V 2Voltage on any digital pin V PIN-0.5V DD V 3Soldering temperature T260 °C 4Storage temperature T ST-55125 °C 5Junction temperature T j125 °C 6Voltage on input pin V input V DD V 7Input capacitance each pin C p500fF * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.* Voltages are with respect to ground (GND) unless otherwise statedRecommended Operating Conditions*Characteristics Sym.Min.Typ.Max.Units1Supply voltage 2.5 V mode V DD25 2.375 2.5 2.625V2Supply voltage 3.3 V mode V DD33 3.135 3.3 3.465V3Operating temperature T A-402585°C* Voltages are with respect to ground (GND) unless otherwise statedDC Electrical Characteristics - Current ConsumptionCharacteristics Sym.Min.Typ.Max.Units Notes 1Supply current LVDS drivers - loadedI dd_load93mA(all outputs are active)DC Electrical Characteristics - Inputs and Outputs - for 2.5/3.3 V SupplyCharacteristics Sym.Min.Typ.Max.Units Notes1Differential input common modeV ICM 1.1 1.6V for 2.5 V voltageV ICM 1.1 2.0V for 3.3 V2Differential input common modevoltage3Differential input voltage V ID0.251V4LVDS output differential voltage*V OD0.250.300.40V5LVDS Common Mode voltage V CM 1.1 1.25 1.375V* The VOD parameter was measured between 125 and 750 MHzAC Electrical Characteristics* - Inputs and Outputs (see Figure 20) - for 2.5/3.3 V supply.Characteristics Sym.Min.Typ.Max.Units Notes 1Maximum Operating Frequency1/t p750MHz2Input to output clock propagation delay t pd012ns3Output to output skew t out2out80150ps4Part to part output skew t part2part120300ps5Output clock Duty Cycle degradation t PWH/ t PWL-505Percent6LVDS Output slew rate r SL0.55V/nsFigure 19 - Differential Voltage Parameter* Supply voltage and operating temperature are as per Recommended Operating ConditionsInputt Pt PWL t pdt PWHOutputFigure 20 - Input To Output TimingAdditive Jitter at 2.5 V*Output Frequency (MHz)Jitter MeasurementFilterTypical RMS (fs)Notes112512 kHz - 20 MHz 1482212.512 kHz - 20 MHz 1523311.0412 kHz - 20 MHz 121442512 kHz - 20 MHz 115550012 kHz - 20 MHz 1076622.0812 kHz - 20 MHz 107775012 kHz - 20 MHz105Additive Jitter at 3.3 V*Output Frequency (MHz)Jitter MeasurementFilterTypical RMS (fs)Notes112512 kHz - 20 MHz 1502212.512 kHz - 20 MHz 1383311.0412 kHz - 20 MHz 120442512 kHz - 20 MHz 115550012 kHz - 20 MHz 1076622.0812 kHz - 20 MHz 106775012 kHz - 20 MHz1045.0 Performance Characterization*The values in this table were taken with an approximate slew rate of 0.8 V/ns*The values in this table were taken with an approximate slew rate of 0.8 V/ns.Additive Jitter from a Power Supply Tone*Carrier frequencyParameterTypicalUnitsNotes125MHz 25 mV at 100 kHz 24fs RMS 750MHz25 mV at 100 kHz23fs RMS* The values in this table are the additive periodic jitter caused by an interfering tone typically caused by a switching power supply. For this test, measurements were taken over the full temperature and voltage range for V DD = 3.3 V. The magnitude of the interfering tone is measured at the DUT.6.0 Typical BehaviorTypical Waveform at 155.52 MHzV OD vs FrequencyPower Supply Tone Frequency versus PSRRPower Supply Tone Magnitude versus PSRRPropagation Delay versus TemperatureNote:This is for a single device. For more details, see thecharacterization section.7.0 Package CharacteristicsThermal DataParameter Symbol Test Condition Value UnitJunction to Ambient Thermal Resistance ΘJA Still Air1 m/s2 m/s 37.433.131.5o C/WJunction to Case Thermal Resistance ΘJC24.4o C/W Junction to Board Thermal Resistance ΘJB19.5o C/W Maximum Junction Temperature*T jmax125o C Maximum Ambient Temperature T A85o C© 2014 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for communications, defense and security, aerospace and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world’s standard for time; voice processing devices; RF solutions; discrete components; security technologies and scalable anti-tamper products; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif. and has approximately 3,400 employees globally. Learn more at .Microsemi Corporate Headquarters One One Enterprise, Aliso Viejo CA 92656 USA Within the USA: +1 (800) 713-4113Outside the USA: +1 (949) 380-6100Sales: +1 (949) 380-6136Fax: +1 (949) 215-4996E-mail: ***************************Information relating to products and services furnished herein by Microsemi Corporation or its subsidiaries (collectively “Microsemi”) is believed to be reliable. However, Microsemi assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Microsemi or licensed from third parties by Microsemi, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Microsemi, or non-Microsemi furnished goods or services may infringe patents or other intellectual property rights owned by Microsemi.This publication is issued to provide information only and (unless agreed by Microsemi in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Microsemi without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical and other products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Microsemi’s conditions of sale which are available on request.For more information about all Microsemi productsvisit our website at TECHNICAL DOCUMENTATION – NOT FOR RESALE。

cadence软件使用说明8-3

Cadence 软件使用说明Last updated: 6/19/2015 2:47 PMPage 1 of 17Copyright @2011-2015, 天津铂创奇远电子科技有限公司版权所有. The material in this document constitutes an unpublished workCadence 软件使用及安装说明WangmengRevision 1.0错误！未找到引用源。

Table Of Contents1 Open Issues (3)1.1 Open Feature Issues (3)1.2 Open Implementation Issues (3)2 引言 (4)2.1 主要学习内容如下： (4)3 各方面学习内容介绍如下 (4)3.1 利用OrCAD Capture CIS进行原理图设计 (4)3.2 cadence软件对PCB的布局布线及焊盘的制作等 (5)3.3 使用Cadence公司的PCB Editor软件来进行印制电路板（PCB）的设计 (7)3.4 Cadence软件Allegro的文件类型描述 (9)4 PCB和原理图之间的联系 (10)5 Cadence Allegro V16.5 安装步骤 (14)5.1 安装注意事项： (14)5.2 个人安装步骤 (15)Copyright @2011-2015, 天津铂创奇远电子科技有限公司版权所有. The material in this document constitutes an unpublished work created in1 Open IssuesList all open issues. Include short description of resolution when closed. This should not be detailed.1.1 Open Feature Issues1)Issue:Resolution:2)Issue:Resolution:3)Issue:Resolution:1.2 Open Implementation Issues1)Issue:Resolution:2)Issue:Resolution:Copyright @2011-2015, 天津铂创奇远电子科技有限公司版权所有. The material in this document constitutes an unpublished work created in2 引言本文主要介绍了强大的PCB软件cadence的一些基本用法，涵盖了PCB原理图的绘制，PCB封装的使用，以及电路板的绘制。

210977182_功率器件的并联均流研究

电气传动2023年第53卷第3期ELECTRIC DRIVE 2023Vol.53No.3摘要：在新能源汽车的电机控制器中，由于现有模块电流能力不够、成本过高、散热能力有限，常常使用多个功率器件并联，以提高电动汽车应用的功率逆变器载流能力。

器件参数的公差、PCB 布局不对称导致的寄生参数不一致以及散热器的冷却效果导致的热量堆积，都会导致电流不均衡现象。

首先对电流不平衡的原因进行了概述，提出均流系数作为电流平衡的标准。

给出了基于热阻的导通电阻模型，分析并联器件静态均流的影响因素。

基于可变电阻区的电压电流曲线，分析了并联器件动态均流的影响因素。

通过PSPICE 建模分析了寄生电感对动态均流的影响，分析了参数差异对电流平衡的的影响，针对不同的参数差异，提出了不同的优化方法。

最后分析了电磁兼容问题对均流特性的影响，给出驱动电路的设计建议，并对栅极电压波形的优化效果进行了仿真验证。

关键词：功率器件；并联；电流平衡；寄生参数中图分类号：TM28文献标识码：ADOI ：10.19457/j.1001-2095.dqcd24454Research on Current Sharing of Parallel Power DevicesTANG Weifeng ，WANG Changjiang（School of Electrical Engineering ，Shandong University ，Jinan 250014，Shandong ，China ）Abstract:In the motor controller of new energy vehicles ，due to insufficient current capacity ，high cost ，andlimited heat dissipation capacity ，parallel power devices are often used to extend current capability of power inverter forEV applications.Current imbalance can be caused by device parameter tolerances ，parasitic parameter inconsistencies due to asymmetric PCB layout ，and heat accumulation due to the cooling effect of the heat sink.Firstly ，the causes of current imbalance were summarized ，and the current sharing coefficient ，that is the unbalance ratio ，was put forward as the measuring standard of current balance.The conduction resistance model based on thermal resistance was presented ，and the influencing factors of steady current balance of parallel devices were analyzed.Then ，based on the voltage and current curves in the variable resistance region ，the influencing factors of dynamic current balance of parallel devices were analyzed.The effect of parasitic inductance on dynamic current balance was analyzed by PSPICEsimulation ，and the influence of parameter difference on current balance was analyzed.Different optimization methodswere proposed for different parameter differences.Finally ，the influence of EMI on the current sharing characteristics was analyzed ，and the design of the drive circuit was suggested ，and the optimization effect of the gate voltage waveform was verified in the simulation.Key words:power devices ；parallel ；current sharing ；parasitics parameter作者简介：唐伟峰（1998—），男，硕士研究生，Email ：****************** 通讯作者：王长江（1965—），男，博士，教授，Email ：**********************.cn功率器件的并联均流研究唐伟峰，王长江（山东大学电气工程学院，山东济南250014）分立器件并联工作时，由于器件本身的参数、结温差异或PCB 布局的不对称，各支路的电流不可能完全一致。

(客观题)PCB设计预赛题

第七届信息技术应用水平大赛PCB设计个人赛初赛试卷一、单选题1.下列哪种不是贴片封装（）【答案】B【分数】1分【选项】A.SOT-89B.DIPC.SOT-223D.BGA2.下图中的元件最符合哪种封装名称（）【答案】A【分数】1分【选项】A.SOICB.TSOPC.QFND.DFN3.封装名称“CAPC2012N”中，数字“2012”的含义是（）【答案】A【分数】1分【选项】A.元件的长宽尺寸（公制）B.元件的长宽尺寸（英制）C.元件的IPC编号D.元件的生产商型号4.下列哪种封装在手工焊接时最为困难（）【答案】A【分数】1分【选项】A.QFNB.SOPC.DIPD.AXIAL5.Altium Designer在编辑元器件管脚名称时，采用什么符号定义“低电平”有效（）【答案】C【分数】1分【选项】A.“-”B.“/”C.“\”D.“*”6.元件符号模型属性编辑时，哪种类型可使元件符号变为跳线类型（）【答案】C【分数】1分【选项】A.StandardB.Mechanical TieD.Graphical7.如果想要屏蔽某部分电路的错误报告，可以在原理图中放置什么标记（）【答案】B【分数】1分【选项】A.Parameter Set指示或PCB Layout指示B.No ERC标记或Compile Mask指示 Class指示或Parameter Set指示D.No ERC指示或PCB Layout指示8.下列关于装配变量的描述中，不正确的是（）【答案】C【分数】1分【选项】A.通过引入器件设计参数变量，提高器件装配的灵活性B.装配变量可以被用于BOM表和装配图创建中C.装配变量必须在PCB编辑环境内设置D.所谓装配变量参数，即在元件PCB装配阶段可以变更的数据9.如需在PCB中放置字符，字体需设置为（）【答案】A【分数】1分【选项】A.TrueTypeB.StrokeC.BarCodeD.Default10.一个PCB精度5mil/5mil，无盲埋孔，包含256pin的BGA器件（1mm脚距，0.5mm焊盘直径），并需要引出绝大部分引脚，至少需要几个信号层（）【答案】C【分数】1分【选项】A. 2B. 4C. 6D.1011.用于绘制PCB外形的层，并没有硬性规定，但下列哪个层一般不用于绘制PCB外形（）【答案】A【分数】1分【选项】A.Top OverlayB.KeepoutC.MechanicalD.以上都不能12.下列哪个不是最常见的PCB铜层厚度（）【答案】D【分数】1分【选项】A.18μmB.35μmC.70μmD.140μm13.下面哪个元件类型不属于IPC元器件封装向导可以创建的封装类型（）【答案】D【分数】1分【选项】A.MELFB.CHIPC.PQFPD.TQFP14.在PCB双面板文件的自动布线器Situs布线策略配置窗口中，编辑层布线方向时，按照下列哪种方式进行设置最为合适（）【答案】C【分数】1分【选项】A.Top layer设置为：Horizontal; Bottom layer设置为：AnyB.Top layer设置为：Vertical; Bottom layer设置为：AnyC.Top layer设置为：Horizontal; Bottom layer设置为：VerticalD.Top layer设置为：Any; Bottom layer设置为：Vertical15.关于Altium Designer的PCB多人协同设计功能的描述中，正确的是（）【答案】C【分数】1分【选项】A.通过层次化原理图功能，实现PCB版图多人协同设计B.按照设计实现功能将PCB划分为多个版图区域，再由多人协同完成C.通过Vault的数据管理功能，实现差异化PCB设计数据的组合D.按照Cross Select Mode，交叉实现PCB版图多人协同设计16.在PCB中放置导线时，可切换的布线模式中，不包含（）【答案】B【分数】1分【选项】A.45°拐角和90°拐角B.任意角度拐角C.任意角度直线D.弧形拐角17.在绘制PCB元件封装时，其封装中的焊盘孔径（）【答案】D【分数】1分【选项】A.任何情况均可使用焊盘的默认值B.Hole Size的值可以大于X-Size的值C.必须根据元件引脚的实际尺寸确定D.Hole Size的值可以大于Y-Size的值18.下列哪个在Altium Designer的仿真分析中不支持（）【答案】D【分数】1分【选项】A.信号仿真B.数模混合仿真C.信号完整性分析D.电磁兼容性分析19.下列关于元器件布局的说法中，错误的是（）【答案】B【分数】1分【选项】A.可以将元器件以任意旋转角度（比如0.5°）放置B.元件可以放置在对应的Room外C.元器件边框可以放置到PCB边界以外D.元件既可以放置在顶层，也可以放置在底层20.下列关于传输线和阻抗匹配的说法中，错误的是（）【答案】C【分数】1分【选项】A.阻抗匹配包括源端匹配和末端匹配B.阻抗匹配可以防止因阻抗变化导致的信号反射C.在双层板（均为信号层）中，也很容易实现微带线D.带状线性能较微带线略好21.与高速数字信号电路设计无关的分析或测试是（）【答案】B【分数】1分【选项】A.需要进行电路信号完整性分析B.需要测试信号的电磁兼容性C.需要进行传输线阻抗特性匹配分析D.需要进行电路电源完整性分析22.大容量电解电容极性接反，可能会有哪种情况发生（）【答案】D【分数】1分【选项】A.无影响B.容值变小C.失去电容的作用D.爆裂23.散热器元件在Altium Designer中应为什么类型（）【答案】D【分数】1分【选项】A.GraphicalB.StandardC.Standard(No BOM)D.Mechanical24.发布PCB到生产厂商或部门通常需要包含哪两个（种）配置文件（）【答案】C【分数】1分【选项】A.BOM表和Gerber文件B.测试点文件和Gerber文件C.裸板制造文件和装配指令文件D.原理图文件和PCB文件25.对装配完的电路板进行首次上电测试时，出现工作电压迅速下降的现象，首先应（）【答案】A【分数】1分【选项】A.立刻断开输入电源B.观测PCB板，查找可能存在的问题C.触摸板上的元器件，找出表面温度变化异常的元件D.报告实验室老师，等候技术指导26.下面哪项最不适合作为绘制优质原理图的准则？（）【答案】B【分数】1分【选项】A.为网络命名有意义的标号并组合相关联的信号B.需要多原理图完成一个设计时，应使用多张原理图平面化拼接的设计方法C.应尽可能复用电路模块D.应使用标注和指示来规定设计意图及约束信息27.PCB元件规则检查报告的主要用途是？（）【答案】C【分数】1分【选项】A.检查原理图符号与PCB封装是否匹配B.检查是否有重复的元件位号和Unique ID，保证项目中元件的唯一性C.检查元件是否有重合的焊盘和封装，是否有短路铜皮、镜像元件等D.检查元件是否与项目中的设计规则有冲突28.Altium Designer对电子产品开发的理念体现在？（）【答案】A【分数】1分【选项】A.统一数据模型和统一设计B.版本控制C.协同设计D.PCB，FPGA，嵌入式各个设计域的多样化29.在PCB 3D视图中，下列哪个颜色不能自行设置（）【答案】B【分数】1分【选项】A.板子基材B.铜箔C.阻焊D．丝印30.实时链接供应商数据的主要目的是？（）【答案】A【分数】1分【选项】A.实时了解相关元件的参数、价格和存供货信息B.获得元件的数据手册以便于辅助设计C.获得供应商的产品目录D.为采购人员提供元件列表31.二极管的电流方向；下图中的二极管上的黑线代表的意义是（）【答案】B【分数】1分【选项】A.二极管的阳极B.二极管的阴极C.二极管导通时的电流方向D.以上都不对32.图中的二极管最难于焊接到下列哪种封装上（）【答案】D【分数】1分【选项】A.AXIAL-0.3B.DIODE-0.4C.RAD-0.1D.RESC1005N33.元件封装“CAPC3216L”与“CAPC3216M”的区别在于（）【答案】C【分数】1分【选项】A.前者元件尺寸更大B.前者元件高度更高C.前者所占PCB面积更大D.前者是贴片元件，后者是直插元件34.下列哪种封装可能的引脚数最多（）【答案】D【分数】1分【选项】A.SOT23B.SOPC.TSSOPD.BGA35.下列关于PCB中元件/封装放置的说法中，错误的是（）【答案】C【分数】1分【选项】A.可以被放置在Top Layer也可以被放置在Bottom LayerB.可以旋转任意角度放置C.可以按X键或Y键自由翻转D.可以部分露出PCB边界36.Altium Designer支持的信号层和内电层数量为（）【答案】A【分数】1分【选项】A.32个信号层和32个内电层B.32个信号层和16个内电层C.16个信号层和32个内电层D.16个信号层和16个内电层37.下列哪些元件标号和参数数值的标示方式是不推荐的（）【答案】D【分数】1分【选项】A.元件标号“R101”B.元件标号“K001”C.电容容值“4.7uF”D.电容容值“.1uF”38.下列哪项设置可以避免显示十字交叉结点（）【答案】A【分数】1分【选项】A.使用Display Cross-Overs和Convert Cross-Junctions选项B.使用Optimize Wire & Buses选项C.使用Components Cut Wires选项D.以上都不可以39.下列哪种不是多图纸设计时可采用的图纸结构（）【答案】D【分数】1分【选项】A.FlatB.HierarchicalC.GlobalD.Multi-Channel40.下列哪种电气对象在层次原理图中具有全局意义（）【答案】D【分数】1分【选项】 LabelB.PortC.Off-sheet ConnectorD.Power Port41.下列层中，哪个在PCB中没有电气意义（）【答案】D【分数】1分【选项】A.Power PlaneB.Top LayerC.Bottom LayerD.Top Solder42.多通道设计是指（）【答案】B【分数】1分【选项】A.设计中存在这个多个数据采集和处理通道B.一个设计中存在着多个完全相同的设计电路C.设计中利用了可编程逻辑器件，可以扩展多个数据通道D.设计中有很多平行的输入和输出通道43.下列哪种是正确的总线命名（）【答案】B【分数】1分【选项】A.Data0_7B.Data[0..7]C.Data(0,7)D.Data{0..7}44.下列关于参数描述不正确的是（）【答案】A【分数】1分【选项】A.无法为对象添加设计规则参数B.参数没有电气属性C.每个对象可以有多个参数D.参数可以是项目层面，也可以是文档层面45.原理图与PCB的元件映射关系是由什么维护的（）【答案】B【分数】1分【选项】A.元件标号B.Unique IDC.元件的CommentD.库链接的Design Item ID46.下列关于Altium Designer中子件的说法中，最为错误的是（）【答案】B【分数】1分【选项】A.可以将元件的多个子件放置在不同原理图中B.可以将元件的多个子件放置在多个同源的通道中C.元件的一个引脚可以出现在所有子件中D.元件的子件可以不根据功能任意划分47.在进行原理图设计ERC编译时，系统提示“Net NetY1_1 contains floating inputpins(Pin Y1-1)”信息表示（）【答案】A【分数】1分【选项】A.器件Y1的第一脚没有连接输入信号B.网络NetY1_1定义连接到浮动输入引脚C.器件Y1-1含有悬浮的输入引脚NetY1_1D.网络NetY1_1包含悬浮输入的引脚Y1-148.下列哪个仿真源能产生任意线性变化的电压（）【答案】D【分数】1分【选项】A.VSINB.VPLUSEC.VEXPD.VPWL49.下列关于传输线的说法中，错误的是（）【答案】C【分数】1分【选项】A.微带线和带状线均为传输线B.微带线中的导线越宽，特征阻抗越大C.微带线中的介质厚度越大，特征阻抗越大D.带状线一般在中间层，微带线一般只能在表层50.High Speed规则中的哪项规则用于规定信号线的布线长度（）【答案】B【分数】1分【选项】A.ParallelSegmentB.LengthC.MatchedLengthsD.StubLength51.通过哪些方式，不能为封装库添加已有的封装（）【答案】C【分数】1分【选项】A.从PCB文档中将封装复制粘贴到库中B.从另一个PCB封装库中将封装复制粘贴到库中C.从原理图文档中通过复制原理图符号将其链接的PCB封装粘贴到库中D.在库内复制粘贴52.某些高速电路板上的蛇形走线的主要作用是（）【答案】C【分数】1分【选项】A. 美观B. 匹配阻抗C. 匹配线长D. 替代小感量的电感53.下列哪种形状的焊盘孔在Altium Designer中不能实现（）【答案】C【分数】1分【选项】A.槽型B.正方型C.长方形D.圆形54.关于Altium Designer创建原理图仿真设计功能，描述错误的是（）【答案】B【分数】1分【选项】A.每个原理图电路仿真中必须包含至少一个电源仿真模型B.可以支持单张原理图设计的电路仿真C.每个元器件符号均必须自带SPCE仿真模型D.可以支持瞬态特性分析和傅里叶分析55.什么是埋孔（）【答案】C【分数】1分【选项】A.从顶层到底层贯通的过孔B.从顶层（或底层）到中间某层的过孔C.两边都不到顶层或底层的过孔（看不到的过孔）D.有特殊尺寸要求的过孔56.关于PCB图纸模板，叙述不正确的是？（）【答案】C【分数】1分【选项】A.PCB机械层可以链接到PCB图纸页面上B.PCB的白色图纸区域是可以调整大小的C.PCB中预定义的图纸模板不可更改D.标题块可以在Excel中创建，然后复制到PCB文档57.生成元件报告时，下面哪项不包含在报告之中？（）【答案】D【分数】1分【选项】A.元件参数B.元件引脚C.器件模型D.器件供应商58.下列有关在线DRC检查的说法哪个不正确？（）【答案】C【分数】1分【选项】A.在线DRC检查需要该规则在PCB规则冲突面板对话框中被使能B.在线DRC检查需要在Design Rule Checker对话框中，该规则的在线检查功能被启用C.在线DRC检查能检查出该规则使能前的设计错误D.在线DRC检查需要在Preference对话框PCB Editor – General页面的在线DRC检查功能已经开启59.下列有关信号完整性分析的说法不正确的是？（）【答案】B【分数】1分【选项】A.用来判断是否有可能发生信号完整性问题的一个常用的法则是“1/3上升时间”法则，这个描述的是如果电线的长度长于信号在1/3的上升时间所传输的距离长度的时候，反射就有可能发生B.用来计算阻抗的公式中，布线层的两侧是一侧有内电层还是两侧均有内电层将决定取用不同的公式，但假如信号层与内电层不毗临，则计算公式中将不考虑内电层的因素C.用户可以利用阻抗匹配来避免能量在源与负载之间来回反射D.在Altium Designer中有两种方法可以来完成阻抗匹配：第一种是匹配元器件，第二种是对板子布线给出所需要的阻抗，由软件自动计算出各个信号层的信号宽度，并自动指导布线60.将Preferences参数设置到云端有什么好处？（）【答案】A【分数】1分【选项】A.即使是在不同的工作地点，也可以导入相同的项目参数配置B.用户可以按照个人偏好来设置各种编辑环境的参数C.用户可以本地化参数信息，使用自己熟悉的语言操作环境D.用户可以在软件启动时打开上次的工作空间或显示主页二、多选题（20题，2分/题，共40分）1.元件引脚的电气类型选项中，不包含（）【答案】AD【分数】1分【选项】A.NoneB.PassiveC.IOD.Ground2.下列哪种情况会使得从原理图向PCB导入更改发生错误（）【答案】CD【分数】1分【选项】A.封装中两个焊盘编号重复B.封装中某焊盘的编号在原理图符号中不存在C.原理图中的某焊盘编号在封装中不存在D.原理图中存在两个标号一样的元件3.使用自动元件编号功能时，可以选择以下哪种或哪些编号顺序（）【答案】ABCD【分数】1分【选项】A.Down then CrossB.Up then CrossC.Cross then DownD.Cross then Up4.Altium Designer支持的手工交互式布线功能包括（）【答案】ABC【分数】1分【选项】A.单端网络交互式器B.差端网络交互式布线器C.多路网络交互式布线器D.元器件通用网络管脚交换5.PCB版图设计中输出的装配文件类型包括（）【答案】AC【分数】1分【选项】A.测试点（Test Point）报告B.元件清单（BOM）C.贴片数据（Pick and Place）文件D.Gerber文件6.下列哪类或哪些PCB规则属于电气类型（Electrical）的规则（）【答案】ABC【分数】1分【选项】A.安全间距（Clearance）B.短路（Short-Circuit）C.未连接网络（Un-Routed Net）D.布线宽度（Width）7.下列关于创建封装的描述中错误的是（）【答案】CD【分数】1分【选项】A.贴片元件的焊盘，通常应放置在Top LayerB.穿孔的焊盘，通常应防置在Multi-LayerC.元件的外形轮廓定义在Mechanical层D.元件的3D模型放置在Top Overlay层8.下面所列内容哪些是在PCB布线前需要完成的准备工作（）【答案】ABC【分数】1分【选项】A. 定义板层的层数，并设置好哪些是信号层，哪些是内电层，多电源系统则分割好内电层B. 定义好设计规则（Rules），对于不同作用域的设计规则通过查询语言详细指列C. 如有必要，将一些重要网络的飞线编辑成特殊的颜色，以方便后续布线时刻提醒设计师D. 确认该PCB文档内，已对所有网络就布线优先级一一做出排列，以便后续布线按照该优先级一一按序完成布线9.有关多路布线（Multi-trace）设计的说法正确的是（）【答案】ACD【分数】1分【选项】A. 多路布线设计前提，需要首先选中将布线的多个对象（焊盘，导线等）B. 多路布线适用于总线网络布线，普通网络则不适用C. 多路布线过程中，可以修改导线间的间距D. 多路布线过程中，仍然可以应用推挤功能10.下列哪些层是负片（）【答案】BD【分数】1分【选项】A.Top OverlayB.Top SolderC.Top PasteD.Power Plane11.下列哪些是可选的焊盘形状（）【答案】ABC【分数】1分【选项】A.RectangularB.RoundC.Round RectangularD.Hexagonal12.元件属性中可包含的模型有（）【答案】BCD【分数】1分【选项】A.MechanicalB.FootprintC.Signal IntegrityD.PCB3D13.下列哪种设计方法能解决潜在的信号完整性问题（）【答案】ACD【分数】1分【选项】A.合理的阻抗匹配B.对干扰源做屏蔽C.利用“1/3上升时间”法则，控制布线长度D.尽量增大相邻信号线（非差分对）的间距14.下列电平规范中，属于差分规范的是（）【答案】BD【分数】1分【选项】A.LVCMOSB.LVDSC.SSTLD.RSDS15.对于多通道原理图设计描述正确的是（）【答案】ABCD【分数】1分【选项】A.当存在多个相同电路设计模块时，可以利用多通道原理图设计功能简化设计复杂度B.在图表符属性窗口的Designator栏中，运用Repeat关键字命令创建多通道图表符模块C.在图表入口属性窗口的Name栏中，运用Repeat关键字命令创建多通道入口名称D.在多通道原理图设计中，任意通道内的元器件标号均唯一16.下列PCB图中，不合理之处有（）【答案】BCD【分数】1分【选项】A.铺铜直接连接过孔B.铺铜直接连接焊盘C.左下角芯片的丝印覆盖了焊盘D.左下角芯片没有指定PIN-1位置17.关于铺铜时的浮铜（死铜、Dead copper），下列表述不正确的是：（）【答案】ACD【分数】1分【选项】A.不影响电路性能B.会感应周围的信号，使EMC特性变坏C.具有屏蔽作用D.会影响焊接质量18.具有信号隔离功能的器件有（）【答案】BC【分数】1分【选项】A.IGBT（绝缘栅双极晶体管）B.继电器C.光电耦合器D.MOSFET19.下列哪些是Altium Designer包含的功能（）【答案】ABCD【分数】1分【选项】A.电路原理图设计B.FPGA逻辑设计C.IPC元器件封装向导D.嵌入式软件设计20.对USB数据通信从端（Slave）接口模块设计描述错误的是（）【答案】ACD【分数】1分【选项】B信号用符号RX和TX表示接收和发送B通信采用串行差分信号传输C.为了降低USB通信误码率，需尽量缩短从USB连接器到USB传输芯片间走布线长度B传输芯片的信号接收引脚应连接到USB连接器的发送引脚。

CadenceAllegro教程-17个步骤

CadenceAllegro教程-17个步骤Allegro教程-17个步骤Allegro® 是Cadence 推出的先进 PCB 设计布线工具。

Allegro 提供了良好且交互的工作接口和强大完善的功能，和它前端产品Cadence® OrCAD® Capture 的结合，为当前高速、高密度、多层的复杂 PCB 设计布线提供了最完美解决方案。

Allegro 拥有完善的Constraint 设定，用户只须按要求设定好布线规则，在布线时不违反 DRC 就可以达到布线的设计要求，从而节约了烦琐的人工检查时间，提高了工作效率！更能够定义最小线宽或线长等参数以符合当今高速电路板布线的种种需求。

软件中的 Constraint Manger 提供了简洁明了的接口方便使用者设定和查看 Constraint 宣告。

它与 Capture 的结合让 E.E. 电子工程师在绘制线路图时就能设定好规则数据，并能一起带到Allegro工作环境中，自动在摆零件及布线时依照规则处理及检查，而这些规则数据的经验值均可重复使用在相同性质的电路板设计上。

Allegro 除了上述的功能外，其强大的自动推挤 push 和贴线 hug 走线以及完善的自动修线功能更是给用户提供极大的方便；强大的贴图功能，可以提供多用户同时处理一块复杂板子，从而大大地提高了工作效率。

或是利用选购的切图功能将电路版切分成各个区块，让每个区块各有专职的人同时进行设计，达到同份图多人同时设计并能缩短时程的目的。

用户在布线时做过更名、联机互换以及修改逻辑后，可以非常方便地回编到Capture 线路图中，线路图修改后也可以非常方便地更新到Allegro 中；用户还可以在 Capture 与 Allegro 之间对对象的互相点选及修改。

对于业界所重视的铜箔的绘制和修改功能，Allegro 提供了简单方便的内层分割功能，以及能够对正负片内层的检阅。

Altium Designer 学习笔记(总结)教学内容

●∙在PCB板界面（默认是二维画面）时使用【Shift+M】键可以快速打开滤镜（即放大镜），再次使用此组合键可以退出滤镜功能，该快捷组合键同样适用于三维PCB界面。

●∙在PCB界面中，按数字键3，打开PCB板的三维界面；在三维界面时，按数字键2，则又切换到二维界面。

●∙在PCB的三维界面时，按住Shift键不松开，同时按下鼠标右键，则可以旋转PCB板。

●∙通常说的低速板一般是指最高频率小于40~50MHz的板子。

●∙画PCB板时尽量用45度的折线代替90度的折线。

●∙当新建了一个PCB项目并且又添加了两个原理图文件，在保存到指定文件夹时，默认是先保存原理图表单1、接着保存原理图表单2，最后保存的是PCB项目。

即保存的顺序是由内向外的。

在PCB项目被保存后，其实Design Workspace（工作区间）也被保存了。

●∙已打开的文件隐藏后，可以在Window下拉框里对应项中打开。

●∙打开原理图编辑器属性设置对话框（即文件选项）有四种方式，1、在Design->Document Options中打开；2、按快捷键【D+O】；3、在原理图界面边缘上或其外部双击同样能快速打开对话框；4、在原理图编辑界面中点击鼠标右键，在弹出的对话框中选择Options->Document Options。

●∙按住Ctrl键的同时按下鼠标右键，然后上下滑动鼠标也可以实现缩放功能。

●∙按Shift+Space键可以切换4种连线模式。

要注意输入法的选择，否则可能无法切换。

●∙PCB Rule和Parameter Set的属性设置都是在Place ->Directives里面打开（前者选择PCB Layout，后者选择Parameter Set），当选择Add as Rule时，添加的属性的Name都是Rule，当选择添加时，属性的Name随设置的不同而异。

●∙当点击Parameter Set后，再按F1键，则会快速打开Knowledge Center。

PADS常见问题全集

PADS常见问题全集走线很细，不是设定值有时将预拉线布好线后，所布的线变成了一根很细的线而不是我们所设定的线宽，但是查看它的属性也还是一样的最小线宽显示值的设定大于route线宽。

tool--option--global--minimumdiplaywidth或者使用R某这个快捷命令，某表示需要设定的值走线宽度无法修改，提示wrongwidthvalue 关于线宽的rule设置有误etup–deignrule–default—clearance—tracewidth修改最小值默认值和最大值布线的时候不能自动按照安全间距避开走线没有打开规则在线检查DRO关闭在线规则检查DRP打开在线规则检查PADS如何importOrcad 的netlitOrcad中的tool->createnetlit，other的formatter选取padpcb.dll，再将其后缀名.net改为.ac即可。

在PADS中如何删层PADS中如何开方槽4.0以上版本的可在编辑pad中选择lotparameter中lotte来进行设置，但只能是椭圆形的孔；也可在机械层直接标示。

在PADS中如何将其它文件中相同部分复制到新的文件中可用以下部骤:第一，在副图选择要粘贴的目标，按右键选择makereue，弹出一个菜单随变给个名字，ok键即可。

生成一个备用文件。

第二，在按右键选择reetorigin(产生选择目标的坐标)将鼠标移到该坐标上可以坐标值（在窗口的右下角处）。

第三，调出主图，将板子的格点改为“1”mil。

按makelikereue键，打开第一步生成的文件后，用“S”命令敲入第二步生成的坐标。

按左键确定。

在贴完后，在按鼠标右键点击breakorigin。

弹出一个窗口按“OK”即可。

如何在PADS中加入汉字或公司logo将公司logo或汉字用bmptopcb将。

bmp档转换为protel的。

pcb格式，再在protel中import，e某port某.d某f文檔，在PADS中import即可。

多年碰到的Allegro问题集合

Allegro问题集1、Allegro 如何设置route keepin,package keepinsetup->area->route keepin,package keepin ->画框edit ->z-copy->options->package keepin,route keepin->offset->50->点击外框2、ALLEGRO 如何生成钻孔文件Manufacture -> NC -> Drill Customization->auto generate symbolsManufacture -> NC -> Drill LegendManufacture -> NC ->NC parameters->enhanced excellon format->closeManufacture -> NC -> NC Drill->auto tool select->optimize drill head travel3、Allegro 如何设置间距setup -> constraints->set standard values->default value form4、在Allegro中，在布线完成之后如何改变叠层设置选Setup-> Cross-section如果要设置板层厚度, 先定义板层材料setup->materials5、如何在allegro中使specttra保护手工布线route->automatic router->sections-> all but select->选择要保护的net6、如何在allegro中使specttra用45度布线route->route Autormatic->Setup->enable Diagonal RuotingwireGride,安全间距Via Gride,线宽在specttra出错时可以用route->route Checks 检查错误在allegro中查找多于的线头clineTOOLS -> REPORTS -> Dangling line Report7、Allegro 过孔定义,查找多余的cline创建过孔setup ->vias->auto define bbvia ->create bbvia->input padname->generate自动布线的过孔指定Setup-> Constraints->Physical (lines/vias) rule set->Set Values->Via list property->Name清除多余的clineRout->Gloss->Parameters或查找多余的clineTOOLS->REPORTS->Dangling line Reportcline 连接线line 边框线等8、Allegro 的gloss功能45度角转换rote -> gloss-> parameters-> line smoothing -> okgloss圆弧转换rote -> gloss-> parameters->convert corner to arc-> okgloss泪滴和T型走线rote -> gloss-> parameters->pad and T connection fillet-> okgloss局部gloss功能rote -> gloss-> windows9、在Allegro中如何修改线宽在Allegro的Setup－>constraints里的set standard values中可定义每一层走线的宽度，比如，可以定义VCC和GND的线宽为10 Mil。

在HFSS中完成PCB与三维器件的联合仿真

• 3D Components • HFSS 3D LAYOUT • Layout Driven System Verification
HFSS 3D Layout的优势
• EDA操作风格 • 快速的网格生成 • 确保S参数的因果性和无源性 • 所有LAYOUT元素均为参数化模型 • 智能化端口设置 • 简洁的边界条件设置
HFSS 3D Layout在R17中的新功能
• 与HFSS项目的动态链接 • 三维器件布局 • LAYOUT显示优化
支持SIWAVE求解技术
• 完成大尺寸PCB的仿真 • Layout检查
• 线性网络协同仿真 • 网络分组 • 器件建模
三维器件布局演示
Agenda
• 3D Components • HFSS 3D LAYOUT • Layout Driven System Verification
Layout Driven System Verification
需要怎么样系统级电磁仿真？将三维实体器件，基于模型的器件与LAYOUT版图放在一起各部分使用最合适的求解技术（HFSS, HFSS 3D LAYOUT或者SIWAVE）基于自动化电路技术捕捉系统的整体效应
实施Layout Driven System Verification的步骤
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plane hole 4hfss
-2.50
-5.00
S Parameter in db
-7.50
-10.00
-12.50
Curve Info
dB(S(P1,P2)) self ind
dB(S(STRIPLINE_SYMMETRIC_PERFORATED_PLANE_A_0_T1,STRIPLINE_SYMMETRIC_PERFORATED_PLANE_A_0_T2)) Import1