XC9510H1333中文资料
Xeon处理器型号详解
英特尔至强处理器型号大全第1页：双核至强UP：3000、3100系列3000系列“Conroe”酷睿---扣肉2006年9月末英特尔发布了代号为“Conroe”（产品代码80557）的双核至强3000系列CPU，它只不过是英特尔主流“Conroe”的重新贴牌产品，商标采用了酷睿2 Duo（用于消费级的桌面产品），和其它大多数至强处理器不同，它们只支持单CPU运算，使用Socket T (LGA775)，前端总线速度1066MHz，支持英特尔增强的自动降频和虚拟化技术，但不支持超线程。
主频二级缓存L2 CACHE 前端总线散热设计功耗3100系列“Wolfdale”狼之谷代号为“Wolfdale”（产品代码80570）3100系列双核至强CPU只是对英特尔主流产品Wolfdale进行了重新包装，采用相同的65纳米制造工艺和6MB二级缓存，和大多数至强不同，它们仅支持单CPU运算，使用Socket T (LGA775)，前端总线1333MHz，支持增强的自动降频和虚拟化技术，但不支持超线程。
主频二级缓存L2 CACHE 前端总线散热设计功耗第2页：四核至强UP：3200、3300、3400和3500系列——英特尔的多核之路：四核、六核至强3200系列“Kentsfield”2007年1月7日，英特尔发布了重新包装过的四核（2x2）酷睿2 Quad处理器，即至强3200系列（产品代码80562），2x2四核心包括两个独立的双核芯片，包括三个型号X3210、X3220和X3230，分别运行在2.13GHz、2.4GHz 和2.66GHz。
和300系列类似，这些型号只支持单CPU运算，前端总线1066MHz，其目标定位于刀片服务器市场，X3220也当作Core2 Quad Q6600销售，X3230对应到Q6700。
主频二级缓存L2 CACHE 前端总线散热设计功耗3300系列“Yorkfield”英特尔发布重新包装的四核酷睿2 Quad Yorkfield Q9400和Q9x50处理器时，同期发布了至强3300系列（产品代码80569），它包含两个独立的双核芯片，采用了45纳米制造工艺，型号包括X3320、X3350、X3360和X3370，分别运行在2.50GHz、2.66GHz、2.83GHz和3.0GHz，每个芯片统一使用6MB二级缓存（但X3320每块芯片二级缓存只有3MB），前端总线1333MHz，所有型号都支持英特尔64位（x86-64实现），XD位和虚拟化技术，也支持按需供电，使用LAG775 Socket。
XC9536XL-5PCG44C中文资料
© 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at /legal.htm .All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.Features• 5 ns pin-to-pin logic delays•System frequency up to 178 MHz •36 macrocells with 800 usable gates •Available in small footprint packages -44-pin PLCC (34 user I/O pins)-44-pin VQFP (34 user I/O pins)-48-pin CSP (36 user I/O pins)-64-pin VQFP (36 user I/O pins)-Pb-free available for all packages•Optimized for high-performance 3.3V systems -Low power operation-5V tolerant I/O pins accept 5 V, 3.3V, and 2.5Vsignals- 3.3V or 2.5V output capability-Advanced 0.35 micron feature size CMOSFast FLASH™ technology •Advanced system features -In-system programmable-Superior pin-locking and routability withFast CONNECT™ II switch matrix -Extra wide 54-input Function Blocks-Up to 90 product-terms per macrocell withindividual product-term allocation-Local clock inversion with three global and oneproduct-term clocks-Individual output enable per output pin-Input hysteresis on all user and boundary-scan pininputs-Bus-hold circuitry on all user pin inputs-Full IEEE Standard 1149.1 boundary-scan (JTAG) •Fast concurrent programming•Slew rate control on individual outputs •Enhanced data security features •Excellent quality and reliability-Endurance exceeding 10,000 program/erasecycles-20 year data retention-ESD protection exceeding 2,000V•Pin-compatible with 5V-core XC9536 device in the 44-pin PLCC package and the 48-pin CSP packageWARNING: Programming temperature range of T A = 0° C to +70° CDescriptionThe XC9536XL is a 3.3V CPLD targeted for high-perfor-mance, low-voltage applications in leading-edge communi-cations and computing systems. It is comprised of two54V18 Function Blocks, providing 800 usable gates with propagation delays of 5ns. See Figure 2 for architecture overview.Power EstimationPower dissipation in CPLDs can vary substantially depend-ing on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell in a XC9500XL device may be configured for low-power mode (from the default high-performance mode). In addi-tion, unused product-terms and macrocells are automati-cally deactivated by the software to further conserve power.For a general estimate of I CC , the following equation may be used:I CC (mA) = MC HS (0.175*PT HS + 0.345) + MC LP (0.052*PT LP+ 0.272) + 0.04 * MC TOG (MC HS +MC LP )* fwhere:MC HS = # macrocells in high-speed configurationPT HS = average number of high-speed product terms per macrocellMC LP = # macrocells in low power configurationPT LP = average number of low power product terms per macrocellf = maximum clock frequencyMCTOG = average % of flip-flops toggling per clock (~12%)This calculation was derived from laboratory measurements of an XC9500XL part filled with 16-bit counters and allowing a single output (the LSB) to be enabled. The actual I CC value varies with the design application and should be veri-fied during normal system operation. Figure 1 shows the above estimation in a graphical form. For a more detailed discussion of power consumption in this device, see XilinxXC9536XL High Performance CPLDDS058 (v1.9) April 3, 2007Product Specificationapplication note XAPP114, “Understanding XC9500XLCPLD Power.”Figure 1: Typical I CC vs. Frequency for XC9536XLFigure 2: XC9536XL ArchitectureFunction Block outputs (indicated by the bold line) drive the I/O Blocks directly.2DS058 (v1.9) April 3, 2007Absolute Maximum Ratings (2)Recommended Operation ConditionsQuality and Reliability CharacteristicsDC Characteristic Over Recommended Operating ConditionsSymbol DescriptionValue Units V CC Supply voltage relative to GND –0.5 to 4.0V V IN Input voltage relative to GND (1)–0.5 to 5.5V V TS Voltage applied to 3-state output (1)–0.5 to 5.5VT STG Storage temperature (ambient)(3)–65 to +150o C T JJunction temperature+150o CNotes:1.Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, thedevice pins may undershoot to –2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. External I/O voltage may not exceed V CCINT by 4.0V.2.Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stressratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.3.For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb-freepackages, see XAPP427.Symbol ParameterMin Max Units V CCINT Supply voltage for internal logic and input buffersCommercial T A = 0o C to 70o C 3.0 3.6V Industrial T A = –40o C to +85o C3.0 3.6V V CCIO Supply voltage for output drivers for 3.3V operation 3.0 3.6V Supply voltage for output drivers for 2.5V operation 2.3 2.7V V IL Low-level input voltage 00.80V V IH High-level input voltage 2.0 5.5V V OOutput voltageV CCIOVSymbol ParameterMin Max Units T DR Data Retention20-Years N PE Program/Erase Cycles (Endurance)10,000-Cycles V ESDElectrostatic Discharge (ESD)2,000-VoltsSymbol ParameterTest ConditionsMin Max Units V OH Output high voltage for 3.3V outputs I OH = –4.0 mA 2.4-V Output high voltage for 2.5V outputs I OH = –500 μA 90%V CCIO-V V OL Output low voltage for 3.3V outputs I OL = 8.0 mA -0.4V Output low voltage for 2.5V outputs I OL = 500 μA-0.4V I IL Input leakage current V CC = Max; V IN = GND or V CC -±10μA I IH I/O high-Z leakage current V CC = Max; V IN = GND or V CC -±10μA I IHI/O high-Z leakage currentV CC = Max; V CCIO = Max; V IN = GND or 3.6V -±10μA V CC Min < V IN < 5.5V-±50μA C IN I/O capacitanceV IN = GND; f = 1.0 MHz-10pF I CCOperating supply current (low power mode, active)V IN = GND, No load; f = 1.0 MHz10 (Typical)mA4DS058 (v1.9) April 3, 2007AC CharacteristicsSymbol ParameterXC9536XL-5XC9536XL-7XC9536XL-10Units Min Max Min Max Min Max T PD I/O to output valid - 5.0-7.5-10.0ns T SU I/O setup time before GCK 3.7- 4.8- 6.5-ns T H I/O hold time after GCK 0-0-0-ns T CO GCK to output valid- 3.5- 4.5- 5.8ns f SYSTEM Multiple FB internal operating frequency-178.6-125-100MHzT PSU I/O setup time before p-term clock input 1.7- 1.6- 2.1-ns T PH I/O hold time after p-term clock input 2.0- 3.2- 4.4-ns T PCO P-term clock output valid - 5.5-7.7-10.2ns T OE GTS to output valid - 4.0- 5.0-7.0ns T OD GTS to output disable- 4.0- 5.0-7.0ns T POE Product term OE to output enabled -7.0-9.5-11.0ns T POD Product term OE to output disabled -7.0-9.5-11.0ns T AO GSR to output valid -10.0-12.0-14.5ns T PAO P-term S/R to output valid -10.5-12.6-15.3ns T WLH GCK pulse width (High or Low) 2.8- 4.0- 4.5-ns T APRPW Asynchronous preset/reset pulse width (High or Low)5.0-6.5-7.0-ns T PLHP-term clock pulse width (High or Low)5.0- 6.5-7.0-nsFigure 3: AC Load CircuitInternal Timing ParametersSymbol Parameter XC9536XL-5XC9536XL-7XC9536XL-10Units Min Max Min Max Min MaxBuffer DelaysT IN Input buffer delay- 1.5- 2.3- 3.5ns T GCK GCK buffer delay- 1.1- 1.5- 1.8ns T GSR GSR buffer delay- 2.0- 3.1- 4.5ns T GTS GTS buffer delay- 4.0- 5.0-7.0ns T OUT Output buffer delay- 2.0- 2.5- 3.0ns T EN Output buffer enable/disable delay-0-0-0ns Product Term Control DelaysT PTCK Product term clock delay- 1.6- 2.4- 2.7ns T PTSR Product term set/reset delay- 1.0- 1.4- 1.8ns T PTTS Product term 3-state delay- 5.5-7.2-7.5ns Internal Register and Combinatorial DelaysT PDI Combinatorial logic propagation delay-0.5- 1.3- 1.7ns T SUI Register setup time 2.3- 2.6- 3.0-ns T HI Register hold time 1.4- 2.2- 3.5-ns T ECSU Register clock enable setup time 2.3- 2.6- 3.0-ns T ECHO Register clock enable hold time 1.4- 2.2- 3.5-ns T COI Register clock to output valid time-0.4-0.5- 1.0ns T AOI Register async. S/R to output delay- 6.0- 6.4-7.0ns T RAI Register async. S/R recover before clock 5.07.510.0ns T LOGI Internal logic delay- 1.0- 1.4- 1.8ns T LOGILP Internal low power logic delay- 5.0- 6.4-7.3ns Feedback DelaysT F Fast CONNECT II feedback delay- 1.9- 3.5- 4.2ns Time AddersT PTA Incremental product term allocator delay-0.7-0.8- 1.0ns T SLEW Slew-rate limited delay- 3.0- 4.0- 4.5ns6DS058 (v1.9) April 3, 2007XC9536XL I/O Pins (2)XC9536XL Global, JTAG and Power Pins (1)Function Block Macro-cellPC44VQ44CS48VQ64BScanOrderFunction BlockMacro-cellPC44VQ44CS48VQ64BScan Order11240D6910521139D785112341C710102224438E5748135(1)43(1)B7(1)15(1)992342(1)36(1)E6(1)5(1)4514442C61196244337E7642156(1)44(1)B6(1)16(1)932540(1)34(1)F6(1)2(1)391682A619902639(1)33(1)G7(1)64(1)36177(1)1(1)A7(1)17(1)87273832G663331893C52084283731F5623019115B52281293630G56127110126A424782103529F46024111137B425752113428G45721112148A327722123327E356181131812B233692132923F250151141913B135662142822G148121152014C236632152721F14591162216C338602162620E24461172418D242572172519E1433118--D33954218--E449Notes:1.Global control pin.2.The pin-outs are the same for Pb-free versions of packages.Pin Type PC44VQ44CS48VQ64I/O/GCK1543B715I/O/GCK2644B616I/O/GCK371A717I/O/GTS14236E65I/O/GTS24034F62I/O/GSR 3933G764TCK 1711A130TDI 159B328TDO 3024G253TMS 1610A229V CCINT 3.3V 21, 4115, 35C1, F73, 37V CCIO 2.5V/3.3V3226G355GND 10, 23, 314, 17, 25A5, D1, F321, 41, 54No Connects--C4, D41, 4, 12, 13, 14, 18, 23, 26, 31, 32, 34, 40, 46, 47, 51, 52, 58, 59Notes:1.The pin-outs are the same for Pb-free versions of packages.Device Part Marking and Ordering Combination InformationDevice Ordering and Part Marking Number Speed(pin-to-pin delay)Pkg. SymbolNo. ofPins Package TypeOperating Range (1)XC9536XL-5PC44C 5 ns PC4444-pin Plastic Lead Chip Carrier (PLCC)C XC9536XL-5VQ44C 5 ns VQ4444-pin Quad Flat Pack (VQFP)C XC9536XL-5CS48C 5 ns CS4848-ball Chip Scale Package (CSP)C XC9536XL-5VQ64C 5 ns VQ6464-pin Quad Flat Pack (VQFP)C XC9536XL-7PC44C 7.5 ns PC4444-pin Plastic Lead Chip Carrier (PLCC)C XC9536XL-7VQ44C 7.5 ns VQ4444-pin Quad Flat Pack (VQFP)C XC9536XL-7CS48C 7.5 ns CS4848-ball Chip Scale Package (CSP)CXC9536XL-7VQ64C 7.5 ns VQ6464-pin Quad Flat Pack (VQFP)C XC9536XL-7PC44I 7.5 ns PC4444-pin Plastic Lead Chip Carrier (PLCC)I XC9536XL-7VQ44I 7.5 ns VQ4444-pin Quad Flat Pack (VQFP)I XC9536XL-7CS48I 7.5 ns CS4848-ball Chip Scale Package (CSP)I XC9536XL-7VQ64I 7.5 ns VQ6464-pin Quad Flat Pack (VQFP)I XC9536XL-10PC44C 10 ns PC4444-pin Plastic Lead Chip Carrier (PLCC)C XC9536XL-10VQ44C 10 ns VQ4444-pin Quad Flat Pack (VQFP)C XC9536XL-10CS48C 10 ns CS4848-ball Chip Scale Package (CSP)C XC9536XL-10VQ64C 10 ns VQ6464-pin Quad Flat Pack (VQFP)C XC9536XL-10PC44I 10 ns PC4444-pin Plastic Lead Chip Carrier (PLCC)I XC9536XL-10VQ44I 10 ns VQ4444-pin Quad Flat Pack (VQFP)I XC9536XL-10CS48I 10 ns CS4848-ball Chip Scale Package (CSP)I XC9536XL-10VQ64I 10 ns VQ6464-pin Quad Flat Pack (VQFP)I XC9536XL-5PCG44C 5 ns PCG4444-pin Plastic Lead Chip Carrier (PLCC); Pb-freeC XC9536XL-5VQG44C5 nsVQG4444-pinQuad Flat Pack (VQFP); Pb-freeCNotes:1.Due to the small size of chip scale packages, part marking on these packages does not follow the abovesample and the complete part number cannot be included in the marking. Part marking on chip scale packages by line:·Line 1 = X (Xilinx logo), then truncated part number (no XC), i.e., 95xxxXL.·Line 2 = Not related to device part number.·Line 3 = Not related to device part number.·Line 4 = Package code, speed, operating temperature, three digits not related to part number. Package codes: C1 = CS48, C2 = CSG48.8DS058 (v1.9) April 3, 2007XC9536XL-5CSG48C 5 ns CSG4848-ball Chip Scale Package (CSP); Pb-free C XC9536XL-5VQG64C 5 ns VQG6464-pin Quad Flat Pack (VQFP); Pb-free C XC9536XL-7PCG44C 7.5 ns PCG4444-pin Plastic Lead Chip Carrier (PLCC); Pb-freeC XC9536XL-7VQG44C 7.5 ns VQG4444-pin Quad Flat Pack (VQFP); Pb-free C XC9536XL-7CSG48C 7.5 ns CSG4848-ball Chip Scale Package (CSP); Pb-free C XC9536XL-7VQG64C 7.5 ns VQG6464-pin Quad Flat Pack (VQFP); Pb-free C XC9536XL-7PCG44I 7.5 ns PCG4444-pin Plastic Lead Chip Carrier (PLCC); Pb-freeI XC9536XL-7VQG44I 7.5 ns VQG4444-pin Quad Flat Pack (VQFP); Pb-free I XC9536XL-7CSG48I 7.5 ns CSG4848-ball Chip Scale Package (CSP); Pb-free I XC9536XL-7VQG64I 7.5 ns VQG6464-pin Quad Flat Pack (VQFP); Pb-free I XC9536XL-10PCG44C 10 ns PCG4444-pin Plastic Lead Chip Carrier (PLCC); Pb-freeC XC9536XL-10VQG44C 10 ns VQG4444-pin Quad Flat Pack (VQFP); Pb-free C XC9536XL-10CSG48C 10 ns CSG4848-ball Chip Scale Package (CSP); Pb-free C XC9536XL-10VQG64C 10 ns VQG6464-pin Quad Flat Pack (VQFP); Pb-free C XC9536XL-10PCG44I 10 ns PCG4444-pin Plastic Lead Chip Carrier (PLCC); Pb-freeIXC9536XL-10VQG44I 10 ns VQG4444-pin Quad Flat Pack (VQFP); Pb-free I XC9536XL-10CSG48I 10 ns CSG4848-ball Chip Scale Package (CSP); Pb-free I XC9536XL-10VQG64I10 nsVQG6464-pinQuad Flat Pack (VQFP); Pb-freeINotes:1. C = Commercial: T A = 0° to +70°C; I = Industrial: T A = –40° to +85°C.Device Ordering and Part Marking Number Speed(pin-to-pin delay)Pkg. SymbolNo. ofPins Package TypeOperating Range (1)Warranty DisclaimerTHESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT /warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE LAWS AND REGULATIONS.Further ReadingThe following Xilinx links go to relevant XC9500XL CPLD documentation, including XAPP111, Using the XC9500XL Timing Model, and XAPP784, Bulletproof CPLD Design Practices. Simply click on the link and scroll down.Data Sheets, Application Notes, and White Papers.PackagingRevision HistoryThe following table shows the revision history for this document.Date Version Revision09/28/98 1.0Initial Xilinx release.08/28/00 1.1Added VQ44 package.06/20/02 1.2Updated I CC equation, page 1. Removed -4 device. Added industrial availability to -7device. Added additional I IH test conditions and measurements to DC Characteristics table.06/18/03 1.3Updated T SOL from 260 to 220o C. Added Device Part Marking and updated OrderingInformation.08/21/03 1.4Updated Package Device Marking Pin 1 orientation.07/15/04 1.5Added Pb-free documentation09/15/04 1.6Added T APRPW specification to AC Characteristics.07/15/05 1.7Move to Product Specification03/22/06 1.8Add Warranty Disclaimer.04/03/07 1.9Add programming temperature range warning on page 1.10DS058 (v1.9) April 3, 2007。
倍福PLC卡件介绍
AC-2——异步电机用高频MOSFET逆变器AC2代表了当今最为先进的技术(IMS功率模块，Flash内存，微处理器控制，Can Bus)。
下面分别给出AC2的图片和内部结构示意图。
图1 AC2的图片和内部结构示意图BC3150是PROFIBUS—DP总线端子控制器总线端子控制器是带 PLC 控制功能的总线耦合器。
控制器有一个 PROFIBUS-DP 现场总线接口，可在 PROFIBUS-DP 系统中作为智能从站使用。
“紧凑型”总线端子控制器 BC3150 比较小巧而且经济。
BC3150 通过 K-BUS 总线扩展技术，可连接多达 255 个总线端子。
PROFIBUS 控制器自动检测波特率，最大可至 12 M波特率，使用两个地址选择开关分配地址。
总线端子控制器使用符合 IEC 61131-3 标准的 TwinCAT 进行编程。
组态和编程接口用于装载 PLC 程序，如果使用软件 PLC TwinCAT，则其 PLC 程序也可通过现场总线装载。
所连接的总线端子的输入/输出在 PLC 的缺省设置中被赋值。
可对每个总线端子进行配置，使其直接通过现场总线实现与上层控制单元的数据交换。
同样，预处理的数据也可通过现场总线实现总线端子控制器和上层控制器之间的数据交换。
BK3150是PRORIBUS—DP总线端子耦合器PROFIBUS-DP “紧凑型”总线耦合器 BK3150 扩展了 Beckhoff 总线端子系统，比较小巧而经济。
可以连接多达 64 个总线端子；若采用端子总线扩展技术，则可连接多达 255 个总线端子。
PROFIBUS 总线耦合器具有自动波特率检测功能，速率最大可以达到 12 Mbaud ，2 个地址选择开关用作地址分配。
对于现场总线连接，有提供 1 个 D-sub9 针接口，用于订货号为 ZS1031-3000 或 ZB3100 的 PROFIBUS 接头。
CX1020-0xxx 基本 CPU 模块CX1020 基本 CPU 模块通过一个功能更为强大的 1GHz Intel® M CPU 对现有CX1000 系列产品进行了扩展。
G.SKILL DDR3内存型号参考清单说明书
G.SKILL F3-3000C12Q-16GTXDG16GB (4 x 4GB )SS--- 1.65V●●●G.SKILL F3-2933C12D-8GTXDG8GB (2 x 4GB )SS--12-14-14-35 1.65V●●G.SKILL F3-2933C12Q-16GTXDG16GB (4 x 4GB )SS--12-14-14-35 1.65V●●●G.SKILL F3-2800C11Q-16GTXD(XMP)16GB(4GBx4)DS--11-13-13-35 1.65V●●CORSAIR CMD16GX3M4A2666C11 (XMP)4GB DS--11-13-13-35 1.65V●●●G.SKILL F3-2666C11Q-16GTXD(XMP)16GB(4GBx4)DS--11-13-13-35 1.65V●●●Team TXD34G2666HC11CBK8GB ( 2x 4GB )SS--11-13-13-35 1.65V●●●Team TXD38G2666HC11CBK16GB ( 2x 8GB )DS--11-13-13-35 1.65V●●G.SKILL F3-2600CL10Q-16GBZMD(XMP)16GB(4x 4GB)DS--10-12-12-31 1.65V●●G.SKILL F3-2600CL11Q-32GBZHD(XMP)32GB(8GBX4)DS--11-13-13-35 1.65V●●ADATA AX3U2600GW8G1116GB ( 2x 8GB )DS--11-13-13-35 1.65V●●CORSAIR CMGTX8(XMP)8GB (2GBx 4)SS--10-12-10-27 1.65V●●G.SKILL F3-2400C10D-8GTX(XMP)8GB(2x 4GB)SS--10-12-12-31 1.65V●●●G.SKILL F3-19200CL11Q-16GBZHD(XMP1.3)16GB ( 4GB x4 )DS--11-11-11-31 1.65V●●G.SKILL F3-19200CL 10Q-32GBZHD(XMP)8GB DS--10-12-12-31 1.65V●●●KINGMAX FLLE88F-C8KKAA HAIS(XMP)2GB SS--10-11-10-30 1.8V●●●KINGSTON KHX24C11T2K2/8X(XMP)4GB DS--- 1.65V●●●ADATA AX3U2400GW8G1116GB ( 2x 8GB )DS--11-13-13-35 1.65V●●ADATA AX3U2400G4G10-DG2(XMP)4GB DS--10-12-12-31 1.65V●●Team TXD38G2400HC10QBK8GB DS--10-12-12-31 1.65V●●●KINGSTON KHX2250C9D3T1K2/4GX(XMP)4GB ( 2x 2GB )DS--- 1.65V●●●GEIL GET34GB2200C9DC(XMP)2GB DS--9-10-9-28 1.65V●●GEIL GET38GB2200C9ADC(XMP)4GB DS--9-11-9-28 1.65V●●KINGMAX FLKE85F-B8KJAA-FEIS(XMP)2GB DS--- 1.5V●●CORSAIR CMT16GX3M4X2133C9(XMP 1.3)16GB ( 4GB x4 )DS--9-11-10-27 1.50V●●●CORSAIR CMT4GX3M2A2133C9(XMP)4GB(2x 2GB)DS--9-10-9-24 1.65V●●●CORSAIR CMT4GX3M2B2133C9(XMP)4GB(2x 2GB)DS--9-10-9-27 1.50V●CORSAIR CMT8GX3M2B2133C9(XMP)8GB ( 4GB x 2)DS--9-11-9-27 1.50V●●●G.SKILL F3-17000CL9Q-16GBZH(XMP1.3)16GB ( 4GB x4 )DS--9-11-10-28 1.65V●●●G.SKILL F3-17000CL11Q2-64GBZLD(XMP)8GB DS--11-11-11-31 1.5V●●●G.SKILL F3-2133C11Q-32GZL(XMP)8GB DS--11-11-11-31 1.5V●●●GEIL GE34GB2133C9DC(XMP)2GB DS--9-9-9-28 1.65V●●GEIL GU34GB2133C9DC(XMP)4GB(2 x 2GB)DS--9-9-9-28 1.65V●●KINGSTON KHX2133C11D3K4/16GX(XMP)16GB ( 4GB x4 )DS--- 1.65V●●●KINGSTON KHX2133C11D3T1K2/16GX(XMP)16GB(8GB x 2)DS--- 1.6V●●●KINGSTON KHX21C11T1BK2/16X(XMP)16GB(8GBx2)DS--- 1.6V●●●KINGSTON KHX2133C9AD3T1K2/4GX(XMP)4GB ( 2x 2GB )DS--- 1.65V●●●KINGSTON KHX2133C9AD3X2K2/4GX(XMP)4GB(2 x 2GB)DS--9-11-9-27 1.65V●●●KINGSTON KHX2133C9AD3T1K4/8GX(XMP)8GB(4 x 2GB)DS--9-11-9-27 1.65V●KINGSTON KHX21C11T1BK2/8X(XMP)8GB(4GBx2)DS--- 1.6V●●●KINGSTON KHX2133C9AD3T1FK4/8GX(XMP)8GB(4x 2GB)DS--- 1.65V●●KINGSTON KHX21C11T3K4/32X8GB DS--- 1.65V●●●ADATA AX3U2133XW8G1016GB ( 2x 8GB )DS--10-11-11-30 1.65V●●●ADATA AX3U2133XC4G10-2X(XMP)4GB DS--10-11-11-30 1.65V●●●ADATA AX3U2133XW8G10-2X(XMP)8GB DS--10-11-11-30 1.65V●●●Team TXD34096M2133HC11-L4GB SS--- 1.5V●●●Team TLD38G2133HC11ABK8GB DS--11-11-11-31 1.65V●●●Apacer78.AAGD5.9KD(XMP)6GB(3 x 2GB)DS--9-9-9-27 1.65V●●●CORSAIR CMZ4GX3M2A2000C10(XMP)4GB(2 x 2GB)SS--10-10-10-27 1.50V●●●CORSAIR CMT6GX3M3A2000C8(XMP)6GB(3 x 2GB)DS--8-9-8-24 1.65V●●●G.SKILL F3-16000CL9D-4GBFLS(XMP)4GB(2 x 2GB)DS--9-9-9-24 1.65V●●G.SKILL F3-16000CL9D-4GBTD(XMP)4GB(2 x 2GB)DS--9-9-9-27 1.65V●●G.SKILL F3-16000CL6T-6GBPIS(XMP)6GB (3x 2GB )DS--6-9-6-24 1.65V●●●GEIL GUP34GB2000C9DC(XMP)4GB(2 x 2GB)DS--9-9-9-28 1.65V●●KINGSTON KHX2000C9AD3T1K2/4GX(XMP)4GB ( 2x 2GB )DS--- 1.65V●●KINGSTON KHX2000C9AD3W1K2/4GX(XMP)4GB ( 2x 2GB )DS--- 1.65V●●KINGSTON KHX2000C9AD3W1K3/6GX(XMP)6GB ( 3x 2GB )DS--- 1.65V●●KINGSTON KHX2000C9AD3T1K3/6GX(XMP)6GB (3x 2GB )DS--- 1.65V●●CORSAIR CMT4GX3M2A1866C9(XMP)4GB(2 x 2GB)DS--9-9-9-24 1.65V●●●CORSAIR CMT6GX3MA1866C9(XMP)6GB(3 x 2GB)DS--9-9-9-24 1.65V●●CORSAIR CMZ8GX3M2A1866C9(XMP)8GB(2 x 4GB)DS--9-10-9-27 1.50V●●●CRUCIAL BLE4G3D1869DE1TXO.16FMD(XMP)4GB DS--9-9-9-27 1.5V●●●CRUCIAL BLT4G3D1869DT1TX0.13FKD(XMP)4GB DS--9-9-9-27 1.5V●●●CRUCIAL BLT4G3D1869DT2TXOB.16FMR(XMP)4GB DS--9-9-9-27 1.5V●●G.SKILL F3-14900CL9Q-16GBZL(XMP1.3)16GB ( 4GB x4 )DS--9-10-9-28 1.5V●●●G.SKILL F3-14900CL10Q2-64GBZLD(XMP1.3)64GB ( 8GBx 8 )DS--10-11-10-30 1.5V●●●G.SKILL F3-14900CL9D-8GBXL(XMP)8GB(2 x 4GB)DS--9-10-9-28 1.5V●●G.SKILL F3-14900CL9Q-8GBXL(XMP)8GB(2GBx4)DS--9-9-9-24 1.6V●●●KINGSTON KHX1866C9D3K4/16GX(XMP)16GB ( 4GB x4 )DS--- 1.65V●●●KINGSTON KHX1866C11D3P1K2/8G8GB ( 4GB x 2)DS--- 1.5V●●●KINGSTON KHX1866C9D3K2/8GX(XMP)8GB(4GBX2)DS--- 1.65V●●●KINGSTON KHX18C10T3K4/32X8GB DS--- 1.5V●●●ADATA AX3U1866XW8G1016GB ( 2x 8GB )DS--10-11-10-30 1.5V●●●Team TLD38G1866HC10SBK8GB DS--10-11-10-30 1.5V●●●APACER4GB UNB PC3-12800 CL114GB SS APACER AM5D6008BQQSCK--●●●Apacer78.B1GE3.9L10C4GB DS Apacer KZZC AM5D5908DEQSCK--●●●APACER8GB UNB PC3-12800 CL118GB DS APACER AM5D6008BQQSCK--●●●CORSAIR CMD12GX3M6A1600C8(XMP)12GB(6x2GB)DS--8-8-8-24 1.65V●●●CORSAIR CMZ32GX3M4X1600C10(XMP)32GB(8GBx4)DS--10-10-10-27 1.50V●●●CORSAIR CMP4GX3M2A1600C8(XMP)4GB(2 x 2GB)DS--8-8-8-24 1.65V●●●CORSAIR CMP4GX3M2A1600C9(XMP)4GB(2 x 2GB)DS--9-9-9-24 1.65V●●●CORSAIR CMP4GX3M2C1600C7(XMP)4GB(2 x 2GB)DS--7-8-7-20 1.65V●●●CORSAIR CMX4GX3M2A1600C9(XMP)4GB(2 x 2GB)DS--9-9-9-24 1.65V●●●CORSAIR TR3X6G1600C8 G(XMP)6GB(3 x 2GB)DS--8-8-8-24 1.65V●●●CORSAIR TR3X6G1600C8D G(XMP)6GB(3 x 2GB)DS--8-8-8-24 1.65V●●●CORSAIR TR3X6G1600C9 G(XMP)6GB(3 x 2GB)DS--9-9-9-24 1.65V●●●CORSAIR CMP8GX3M2A1600C9(XMP)8GB(2 x 4GB)DS--9-9-9-24 1.65V●●●CORSAIR CMZ8GX3M2A1600C7R(XMP)8GB(2 x 4GB)DS--7-8-7-20 1.50V●●CORSAIR CMX8GX3M4A1600C9(XMP)8GB(4 x 2GB)DS--9-9-9-24 1.65V●●●CORSAIR CMZ8GX3M1A1600C10(XMP)8GB DS--10-10-10-27 1.50V●●●Crucial BL25664BN1608.16FF(XMP)6GB(3 x 2GB)DS--- 1.65V●●●G.SKILL F3-12800CL7D-4GBRH(XMP)4GB(2 x 2GB)SS--7-7-7-24 1.6V●●●G.SKILL F3-12800CL7D-4GBRM(XMP)4GB(2 x 2GB)DS--7-8-7-24 1.6V●●●G.SKILL F3-12800CL8D-4GBRM(XMP)4GB(2 x 2GB)DS--8-8-8-24 1.60V●●G.SKILL F3-12800CL9D-4GBECO(XMP)4GB(2 x 2GB)DS--9-9-9-24XMP 1.35V●●G.SKILL F3-12800CL9D-4GBRL(XMP)4GB(2 x 2GB)DS--9-9-9-24 1.5V●●●G.SKILL F3-12800CL7D-8GBRH(XMP)8GB(2 x 4GB)DS--7-8-7-24 1.6V●●●G.SKILL F3-12800CL8D-8GBECO(XMP)8GB(2 x 4GB)DS--8-8-8-24XMP 1.35V●●●G.SKILL F3-12800CL9D-8GBRL(XMP)8GB(2 x 4GB)DS--9-9-9-24 1.5V●●●G.SKILL F3-12800CL10S-8GBXL(XMP)8GB DS--10-10-10-30-●●●GEIL GET316GB1600C9QC(XMP)16GB ( 4x 4GB )DS--9-9-9-28 1.6V●●●HYNIX HMT351U6CFR8C-PB4GB DS HYNIX H5TQ2G83CFR PBC--●●●KINGMAX FLGE85F-B8KJ9A FEIS(XMP)2GB DS--- 1.5V●●●KINGMAX FLGE85F-B8MF7 MEEH(XMP)2GB DS--7 1.8V/1.9V●KINGSTON KHX1600C9D3P1K2/4G4GB(2 x 2GB)SS--- 1.5V●●●KINGSTON KHX1600C9D3K3/12GX(XMP)12GB(3x4GB)DS--9-9-9-27 1.65V●●●KINGSTON KHX1600C9D3T1BK3/12GX(XMP)12GB(3x4GB)DS--9-9-9-27 1.65V●●KINGSTON KHX1600C9D3K4/16GX(XMP)16GB ( 4GB x4 )DS--- 1.65V●●●KINGSTON KHX16C9K2/1616GB(8GBx2)DS--- 1.5V●●KINGSTON KHX1600C9AD3/2G2GB DS--- 1.65V●●●KINGSTON KVR1600D3N11/2G-ES2GB DS KTC D1288JPNDPLD9U11-11-11-28 1.35V-1.5V●●●KINGSTON KHX1600C7D3K2/4GX(XMP)4GB ( 2x 2GB )DS--- 1.65V●●●KINGSTON KHX1600C8D3K2/4GX(XMP)4GB(2 x 2GB)DS--8 1.65V●●●KINGSTON KHX1600C8D3T1K2/4GX(XMP)4GB(2 x 2GB)DS--8 1.65V●●●KINGSTON KHX1600C9D3K2/4GX(XMP)4GB(2 x 2GB)DS--9 1.65V●●●KINGSTON KHX1600C9D3LK2/4GX(XMP)4GB(2 x 2GB)DS--9XMP 1.35V●●●KINGSTON KHX1600C9D3X2K2/4GX(XMP)4GB(2 x 2GB)DS--9-9-9-27 1.65V●●●KINGSTON KVR16N11/4(矮版）4GB DS KINGSTON D2568GEROPGGBU- 1.5V●●●KINGSTON KHX1600C9D3T1K3/6GX(XMP)6GB ( 3x 2GB )DS--- 1.65V●●KINGSTON KHX1600C9D3K3/6GX(XMP)6GB(3 x 2GB)DS--9 1.65V●●KINGSTON KHX1600C9D3T1BK3/6GX(XMP)6GB(3 x 2GB)DS--9-9-9-27 1.65V●●●KINGSTON KHX1600C9D3K2/8GX(XMP)8GB(2 x 4GB)DS--- 1.65V●●KINGSTON KHX1600C9D3P1K2/8G8GB(2 x 4GB)DS--- 1.5V●●●KINGSTON KHX16C10B1K2/16X(XMP)8GB DS--- 1.5V●●●KINGSTON KHX16C9P1K2/16(XMP)8GB DS--- 1.5V●●●PSC AL9F8L93B-GN2E4GB SS PSC XHP284C3G-M--●●●PSC ALAF8L93B-GN2E8GB DS PSC XHR425C3G-M--●●●Transcend8G DDR3 1600 DIMM CL118GB DS SEC 222 HYKO6MD9639W--●●●Transcend8G DDR3 1600 DIMM CL118GB DS Transcend E223X8BO648S--●●●ADATA AD3U1600C2G11-B2GB SS-N/A--●●●ADATA AD3U1600W4G11-B4GB SS ADATA F209X8BR6413--●●●ADATA AX3U1600GW8G916GB ( 2x 8GB )DS--9-9-9-24 1.5V●●●ADATA AX3U1600W8G1116GB ( 2x 8GB )DS--11-11-11-28 1.5V●●●ADATA AXDU1600GW8G9B16GB ( 2x 8GB )DS--11-11-11-28 1.5V●●●ADATA AD3U1600C4G11-B4GB DS-N/A--●●●ADATA AD3U1600W8G11-B8GB DS ADATA F211X8B0640A--●●SanMax SMD-4G68HP-16KZ4GB DS HYNIX H5TQ2G83BFR PBC--●●●TEAM TED34G1600HC11BK4GB DS--11-11-11-28-●●●TEAM TLD34G1600HC9BK(XMP)4GB DS--9-9-24 1.5V●●●Team TED38G1600HC11BK8GB DS--11-11-11-28-●●●A-DATA AD3U1333C2G92GB SS A-DATA3CCD-1509HNA1126L--●●●A-DATA AX3U1333C2G9-BP2GB SS----●●●A-DATA AD31333G002GMU2GB DS--8-8-8-24 1.65-1.85V●●Apacer78.A1GC6.9L12GB DS Apacer AM5D5808DEWSBG--●●●Apacer78.A1GC6.9L12GB DS Apacer AM5D5808FEQSBG9-●●●Apacer AU02GFA33C9NBGC2GB DS Apacer AM5D5808APQSBG--●●●Apacer78.B1GDE.9L10C4GB DS Apacer AM5D5908CEHSBG--●●●CORSAIR TR3X6G1333C9 G6GB(3x 2GB)SS--9-9-9-24 1.50V●●●CORSAIR CMD24GX3M6A1333C9(XMP)24GB(6x4GB)DS--9-9-9-24 1.60V●●CORSAIR TW3X4G1333C9D G4GB(2 x 2GB)DS--9-9-9-24 1.50V●●●CORSAIR CM3X4GA1333C9N24GB DS CORSAIR256MBDCJGELC04011369-9-9-24-●●●CORSAIR CMX4GX3M1A1333C94GB DS--9-9-9-24 1.50V●●●CORSAIR CMD8GX3M4A1333C78GB(4 x 2GB)DS--7-7-7-20 1.60V●●●Crucial CT25664BA1339.16FF2GB DS Micron9KF27D9KPT9-●●●Crucial BL25664BN1337.16FF (XMP)6GB(3 x 2GB)DS--7-7-7-24 1.65V●●●ELPIDA EBJ21UE8EDF0-DJ-F2GB DS ELPIDA J1108EDSE-DJ-F- 1.35V(low voltage)●●●G.SKILL F3-10666CL8D-4GBECO(XMP)4GB(2 x 2GB)DS--8-8-8-8-24XMP 1.35V●●●G.SKILL F3-10666CL7T-6GBPK(XMP)6GB(3 x 2GB)DS--7-7-7-18 1.5~1.6V●G.SKILL F3-10666CL7D-8GBRH(XMP)8GB(2 x 4GB)DS--7-7-7-21 1.5V●●●GEIL GG34GB1333C9DC4GB(2 x 2GB)DS GEIL GL1L128M88BA12N9-9-9-24 1.3V(low voltage)●●●GEIL GV34GB1333C9DC4GB(2 x 2GB)DS--9-9-9-24 1.5V●●●GEIL GVP34GB1333C7DC4GB(2 x 2GB)DS--7-7-7-24 1.5V●●●Hynix HMT325U6BFR8C-H92GB SS Hynix H5TQ2G83BFRH9C--●●●Hynix HMT125U6TFR8A-H92GB DS Hynix H5TC1G83TFRH9A- 1.35V(low voltage)●●●Hynix HMT351U6BFR8C-H94GB DS Hynix H5TQ2G83BFRH9C--●●●KINGMAX FLFE85F-C8KF9 CAES2GB SS KINGMAX KFC8FMFXF-DXX-15A--●●●KINGMAX FLFE85F-C8KL9 NAES2GB SS KINGMAX KFC8FNLXF-DXX-15A--●●●KINGMAX FLFE85F-C8KM9 NAES2GB SS KINGMAX KFC8FNMXF-BXX-15A--●●KINGMAX FLFE85F-B8KL9 NEES2GB DS KINGMAX KKB8FNWBFGNX-26A--●●●KINGMAX FLFF65F-C8KL9 NEES4GB DS KINGMAX KFC8FNLXF-DXX-15A--●●●KINGMAX FLFF65F-C8KM9 NEES4GB DS KINGMAX KFC8FNMXF-BXX-15A--●●●KINGSTON KVR1333D3N9/2G(矮版)2GB SS Hynix H5TQ2G83AFRH9C9-●●●KINGSTON KVR1333D3S8N9/2G2GB SS Micron IID77 D9LGK- 1.5V●●●KINGSTON KVR1333D3S8N9/2G-SP(矮版)2GB SS ELPIDA J2108BCSE-DJ-F- 1.5V●●●KINGSTON KVR1333D3N9/2G(矮版)2GB DS ELPIDA J1108BFBG-DJ-F9 1.5V●●●KINGSTON KVR1333D3N9/2G-SP(矮版)2GB DS KTC D1288JEMFNGD9U- 1.5V●●●KINGSTON KVR1333D3N9/2G-SP(矮版)2GB DS KINGSTON D1288JPSFPGD9U- 1.5V●●●KINGSTON KHX1333C7D3K2/4GX(XMP)4GB(2 x 2GB)DS--7 1.65V●●●KINGSTON KHX1333C9D3UK2/4GX(XMP)4GB(2 x 2GB)DS--9XMP 1.25V●●KINGSTON KVR1333D3N9/4G(矮版)4GB DS ELPIDA J2108BCSE-DJ-F- 1.5V●●●KINGSTON KVR1333D3N9/4G4GB DS KTC D2568JENCNGD9U- 1.5V●●●KINGSTON KVR1333D3N9/4G4GB DS Hynix H5TQ2G83AFR--●●●KINGSTON KVR1333D3N9/4G-SP(矮版)4GB DS KINGSTON D2568JENCPGD9U- 1.5V●●●Micron MT8JTF25664AZ-1G4D12GB SS Micron OJD12D9LGK--●●●Micron MT8JTF25664AZ-1G4M12GB SS MICRON IJM22 D9PFJ--●●●Micron MT16JTF51264AZ-1G4D14GB DS Micron OLD22D9LGK--●●●NANYA NT4GC64B8HG0NF-CG4GB DS NANYA NT5CB256M8GN-CG--●●●PSC AL8F8G73F-DJ22GB DS PSC A3P1GF3FGF--●●●SAMSUNG M378B5773DH0-CH92GB SS SAMSUNG K4B2G0846D--●●●SAMSUNG M378B5673FH0-CH92GB DS SAMSUNG K4B1G0846F--●●●SAMSUNG M378B5273CH0-CH94GB DS SAMSUNG K4B2G0846C--●●●SAMSUNG M378B1G73AH0-CH98GB DS SAMSUNG K4B4G0846A-HCH9--●●Super Talent W1333UB2GS2GB DS SAMSUNG K4B1G0846F9-●●●Super Talent W1333UB4GS4GB DS SAMSUNG K4B2G0846C--●●●Super Talent W1333UX6GM6GB(3x 2GB)DS Micron0BF27D9KPT9-9-9-24 1.5V●●●Transcend JM1333KLN-2G2GB SS HYNIX H5TQ2G83BZRH9C--●●●Transcend8G DDR3 1333 DIMM CL98GB DS Transcend E207X8BO643Y--●●Transcend8G DDR3 1333 DIMM CL98GB DS-N/A--●●●KINGSTEK KSTD3PC-106002GB SS MICRON PE911-125E--●●●TEAM TED34G1333HC9BK4GB DS--9-9-9-24-●●TEAM TED38G1333HC9BK8GB DS--9-9-9-24-●●●Crucial CT25664BA1067.16FF2GB DS Micron9HF22D9KPT7-●●●ELPIDA EBJ21UE8EDF0-AE-F2GB DS ELPIDA J1108EDSE-DJ-F- 1.35V(low voltage)●●●KINGSTON KVR1066D3N7/2G2GB DS ELPIDA J1108BFSE-DJ-F- 1.5V●●●KINGSTON KVR1066D3N7/4G4GB DS Hynix H5TQ2G83AFR7 1.5V●●●4 DIMM Slots• 1 DIMM: Supports one module inserted in any slot as Single-channel memory configuration• 2 DIMM: Supports one pair of modules inserted into eithor the yellow slots or the dark brown slots as one pair of Dual-channel memory configuration• 4 DIMM: Supports 4 modules inserted into both the yellow and dark brown slots as two pairs of Dual-channel memory configuration-When installing total memory of 4GB capacity or more, Windows 32-bit operation system may only recognize less than 3GB. Hence, a total installed memory of less than 3GB is recommended.-It is recommended to install the memory modules from the yellow slots for better overclocking capability.-The default DIMM frequency depends on its Serial Presence Detect (SPD), which is the standard way of accessing information from a memory module.Under the default state, some memory modules for overclocking may operate at a lower frequency than the vendor-marked value.。
CS5340-CZZR中文资料
Single-Ended Analog Input
AINR Switch-Cap ADC
High-Pass Filter
Low-Latency Digital Filters
Serial Port
VL 1.8 V to 5 V
Auto-detect MCLK Divider
Master Clock
Slave Mode Auto-detect
2. PIN DESCRIPTION .............................................................................................................................. 13 3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 14 4. APPLICATIONS ................................................................................................................................... 15
192 kHz 101 dB Dynamic Range at 5 V -94 dB THD+N 90 mW Power Consumption High-Pass Filter to Remove DC Offsets Analog/Digital Core Supplies from 3.3 V to 5 V Supports Logic Levels between 1.8 V and 5 V Auto-detect Mode Selection in Slave Mode Auto-Detect MCLK Divider Pin Compatible with CS5341
XMC1300 Boot Kit用户手册说明书
XMC1300 Boot KitPart Number: KIT_XMC13_BOOT_001Features∙XMC1300 Microcontroller with 200KB Flash∙Detachable SEGGER J-Link∙Motor control timer∙MATH co-processor∙Motor position interface∙Digital power conversionPLEASE SEE THE FOLLOWING PAGES FOR USERS MANUALXMC1300 CPU Card For XMC1000 FamilyCPU-13A-V1XMC1300 CPU CardBoard User's Manual Revision 2.0, 2013-12-18Edition 2013-12-18Published byInfineon Technologies AG81726 Munich, Germany© 2013 Infineon Technologies AGAll Rights Reserved.Legal DisclaimerThe information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party.InformationFor further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office ().WarningsDue to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office.Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or otherTrademarks of Infineon Technologies AGAURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPIM™,EconoPACK™,EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™,my-d™, NovalithIC™, OptiMOS™, ORIGA™, POWERCODE™, PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™.Other TrademarksAdvance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of D ECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektr onix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited.Last Trademarks Update 2011-11-11Table of Contents1Overview (7)1.1Key Features (7)1.2Block Diagram (7)2Hardware Description (8)2.1Power Supply (8)2.2Reset (9)2.3Clock Generation (9)2.4Boot Option (9)2.5Debug Interface and virtual com port (9)2.6LED (9)2.7Potentiometer (10)2.8Application Card connector (10)3Production Data (12)3.1Schematics (12)3.2Layout and Geometry (15)3.3Bill of Material (15)List of FiguresFigure 1Block Diagram of XMC1300 CPU Card (7)Figure 2XMC1300 CPU Card (8)Figure 3Power Supply circuit (8)Figure 4LEDs circuit (10)Figure 5Potentiometer Circuit (10)Figure 6Pinout of the 2x30 pin edge connector (11)Figure 7Schematic 1 of 2 XMC1300 CPU Card (13)Figure 8Schematic 2 of 2 XMC1300 CPU Card (14)Figure 9XMC1300 CPU Card layout and geometry (15)List of TablesTable 1Debug connector X201 (9)Table 2LEDs Pinout (10)Table 3XMC1300 CPU Card (15)IntroductionThis document describes the features and hardware details of the XMC1300 CPU Card. This board is mounted with ARM® Cortex TM-M0 based XMC1300 Microcontroller from Infineon Technologies AG. This board is part of Infineon’s XMC1000 Application Kits1 OverviewThe XMC1300 CPU board (CPU-13A-V1) houses the XMC1300 Microcontroller and a 2x30 pin edge for application expansion. The board along with application cards (e.g. Colour LED Card, White LED Card) demonstrates the capabilities of XMC1300. The main use case for this board is to demonstrate the generic features of XMC1300 device including tool chain. The focus is safe operation under evaluation conditions. The board is neither cost nor size optimized and does not serve as a reference design.1.1 Key FeaturesThe XMC1300 CPU Card is equipped with the following features∙XMC1300 (ARM®Cortex TM-M0 based) Microcontroller, TSSOP38∙Connection to XMC1300 application cards via card edge connector∙Detachable J-Link debugger and UART virtual COM port, with micro USB connector∙Six user LEDs∙Potentiometer, connected to analog input P2.5∙Power supply via Micro-USB connector1.2 Block DiagramFigure 1 shows the functional block diagram of the XMC1300 CPU Card.Features include:−On board Debugger, for downloading and debugging of application code−Virtual com port for uart communication with terminal program e.g. Hyperterminal.−2x30 card edge connector, for extension to application card e.g. Colour LED Card and White LED Card.− 6 User LEDs connected to GPIO P0.0, P0.1, P0.6, P0.7, P0.8 and P0.9−Variable resistor R110 connected to Analog input P2.5−All the pins of XMC1300 are accessible via the connector JP101, JP102, JP103 and JP104Figure 1 Block Diagram of XMC1300 CPU Card2 Hardware DescriptionThe following sections give a detailed description of the hardware and how it can be used.Figure 2 XMC1300 CPU Card2.1 Power SupplyXMC1300 CPU Card is powered from the micro USB connector (5V); however, there is a current limit that can be drawn from the host PC through USB. If the CPU-13A-V1 board is used to drive other application board (e.g. Colour LED Card, White LED Card) and the total current required exceeds 500mA, then the board needs to be powered by external power supply connected to VDD and GND connection on board.The XMC1300 device can operate by power supply of 1.8V till 5.5Vdc. On this board, 5Vdc is used to power the XMC1300 device. However, if user wants to power the XMC1300 device with 3.3Vdc, then, set Jumper at JP201 to 3.3V side.Figure 3 Power Supply circuit2.2 ResetXMC1300 does not have a reset pin, hence, user can unplug and replug the USB cable to achieve power-on master reset.2.3 Clock GenerationNo external clock source is required. XMC1300 has two internal oscillators DCO1 and DCO2. DCO1 has a clock output of 64MHz. DCO2 is used to generate the standby clock running at 32.768KHz which used for Real Time Clock too. The main clock, MCLK and fast peripherial clock, PCLK, are generated from DCO1’s output.2.4 Boot OptionAfter power-on reset with master reset, XMC1300 device will enter different boot mode depend on the BMI (Boot Mode Index) value stored in XMC1300’s f lash configuration sector 0 (CS0). The BMI value pre-programmed on the XMC1300 device on CPU Card is User mode with debug enabled, hence, the XMC1300 device will start to run the application code in its embedded Flash after power on reset.2.5 Debug Interface and virtual com portXMC1300 CPU Card has on-board debugger which supports Serial Wire Debug (SWD) and Single Pin Debug (SPD) as debug interface. SPD is a proprietary debugging protocol from Infineon Technologies and it requires only 1 pin for debug communication. The debugger also provides a virtual COM port which support UART communication via P1.3 (rx-in) and P1.2 (tx-out) of XMC1300. There is a 2x5 pins Header Debug connector X201.Table 1 Debug connector X2012.6 LEDThe port pins P0.0, P0.1, P0.6, P0.7, P0.8 and P0.9 are connected to LED101, LED102, LED103, LED104, LED105 and LED106 respectively. The LED is turn on by output ‘L ow’ at the port pin.Figure 4 LEDs circuit2.7 PotentiometerXMC1300 CPU Card provides a potentiometer R110 for ease of use and testing of the on-chip analog to digital converter. The potentiometer is connected to the analog input P2.5. The analog output of the potentiometer is the same the VDDP voltage supplied to the XMC1300 device.Figure 5 Potentiometer Circuit2.8 Application Card connectorXMC1300 CPU Card has a 2x30 pins card edge connector. The mating connector is SAMTEC HSEC8-130-01-L-RA-XX.Figure 6 Pinout of the 2x30 pin edge connector3 Production Data3.1 SchematicsThis chapter contains the schematics for the XMC1300 CPU Card:∙Figure 7: CPU, Pin Headers, Potentiometer and LED and 60pin Edge connector ∙Figure 8: On-board Debugger, Power Supply3.2 Layout and GeometryFigure 9 XMC1300 CPU Card layout and geometry 3.3 Bill of Materialw w w.i n f i n e o n.c o m。
技术规格及详细参数
双发双收，环向锁定。199个UHF频率通道可选用，抗干扰，使用距离100M以上。数字音量控制系统，轻触式按键设置，易于设定和操作。接收器和发射器同时具有LCD液晶显示功能，所有工作状态清楚显示。参考品牌范围：惠威、爱浪、博士、飞浪
安装及
验收
调式安装线材包（1.5M卡农连接线两根，四芯插各４个，300支无氧铜音响线１００米，音响移动固定架子等）货物运送到每个乡镇学校（含运输费、上下货等费用）交付使用验收时提供使用说明书，参数说明书及工厂3年免费保修卡以便验收核对。
网卡: 10/100/1000以太网LAN
扩展接口:PCI槽(空闲/总数) PCI（3个）PCI-E PCIe x 1（1个）、PCIe x16
电源:300W
操作系统:出厂自带正版WIN7专业版，含光盘介质；
其他要求：1、硬件还原卡，硬盘保护，带防震垫，网络同传，增量拷贝，断点传输功能，
２、出厂自带软件：电脑基本使用教程，网络及浏览器疑难故障排除，人工杀毒，/SOHO路由器配置
４１０台
扩声功放
功率：立体声输出：650W+650W（8欧）输入电平0.775V,信燥比98dB,失真度小于0.03%.
频率响应20Hz-20kHz.
采用软启动方式，风扇速度自动调节，带液晶显示屏，功放输出保护：完全短路、过载、过温负载保护，可随时监控设备运行状态。（提供产品彩页加盖原工厂公章）ቤተ መጻሕፍቲ ባይዱ考品牌范围：惠威、爱浪、博士、飞浪
３、提供该厂家3C认证，项目授权原件和服务承诺书原件（一年包换，三年免费质保及上门）
４１０台
安装及
验收
货物运送到每个乡镇学校（含运输费、上下货等费用）交付使用验收时提供使用说明书，参数说明书及工厂一年包换三年免费上门保修卡以便验收核对。
深圳市佳鸿威 XC 系列可编程控制器 说明书(特殊指令篇)
目录前言..............................................................................................................................................- 1 - 本手册的内容构成..............................................................................................................- 1 - 手册的适用范围..................................................................................................................- 2 - 手册中的约定俗成..............................................................................................................- 3 - 关联手册..............................................................................................................................- 3 - 手册的获取途径..................................................................................................................- 4 - 1 PID控制功能 (1)1-1．概述 (2)1-2．指令形式 (2)1-3．参数设置 (4)1-3-1．寄存器定义表 (4)1-3-2．参数说明 (5)1-4．自整定模式 (7)1-5．高级模式 (8)1-6．应用要点 (9)1-7．程序举例 (9)2 C语言功能块 (11)2-1．概述 (12)2-2．指令形式 (12)2-3．操作步骤 (13)2-4．函数的导入、导出 (15)2-5．功能块的编辑 (16)2-6．程序举例 (17)2-7．应用要点 (18)2-8．函数表 (19)3 顺序功能块BLOCK (21)3-1．BLOCK基本概念 (23)3-1-1．BLOCK概述 (23)3-1-2．引入BLOCK的原因 (24)3-2．BLOCK的调用 (25)3-2-1．BLOCK的添加 (25)3-2-2．BLOCK的转移 (28)3-2-3．BLOCK的删除 (29)3-2-4．BLOCK的修改 (29)3-3．BLOCK内部指令的编辑 (31)3-3-1．命令语列表 (31)3-3-2．脉冲配置 (33)3-3-3．Modbus指令 (34)3-3-4．Wait指令 (34)3-3-5．变频器配置 (35)3-3-6．自由格式通讯 (39)3-4．BLOCK的执行方式 (41)3-5．BLOCK内部指令的编写要求 (44)3-6．BLOCK相关指令 (46)3-6-1．指令说明 (46)3-6-2．指令的执行时序 (48)3-7．BLOCK执行标志位/寄存器 (52)3-8．程序举例 (53)4 特殊功能指令 (55)4-1．脉宽调制[PWM] (57)4-2．频率测量[FRQM] (58)4-3．精确定时[STR]、[STRR]、[STRS] (60)4-4．中断[EI]、[DI]、[IRET] (63)4-4-1．外部中断 (63)4-4-2．定时中断 (67)附录1 特殊功能版本要求 (69)附录2 PLC资源冲突表 (70)本手册涉及XC系列可编程控制器的高级指令的应用，主要介绍XC系列可编程控制器的本体PID控制指令、C语言功能块、顺序功能块BLOCK、特殊功能指令等，各章节内容概览如下：1．PID控制功能本章重点介绍本体XC系列PID指令的应用，包括指令的调用、参数的设定，使用注意点，程序例等。
悍马主板说明书
环境安全性须知 z 灰尘、潮湿以及剧烈的温度变化都会影响主板的使用寿命,请尽量避免在这些恶劣环
境地方放置和使用。 z 本产品的标准使用环境温度为 0 度～40 度 (数据来自于主芯片要求)。 z 一般情况下，当环境温度变化过大, 可能导致接插件 (CONNECTOR) 之间产生接触性
- II -
安全指导
1. 请仔细阅读这些安全指导。 2. 请保留这份用户手册以便日后参考。 3. 在您开始安装之前请将设备放置于稳定可靠的平台上面。 4. 在您将设备连接电源供应器之前请确保电源电压合乎标准。 5. 设备上所有的警告,警示您都应该注意。 6. 在安装附加的接口与模块之前请将设备与连接器间的连接断开。 7. 决不能让任何液体流入机箱的开口处,这样的行为有可能会引起火灾或电击。 8. 不正确的电池替换可能会引起爆炸.请使用制造厂商建议的电池类型作替换。 9. 如果发生下列情形,请专职的服务人员为您检查您的设备：
商标布告 (按字母表的顺序排列)
所有的品牌,产品,徽标,商标和公司名称都是属于商标或注册商标各自的拥有者。 AMD, Phenom™ II x 4；Phenom™ II x 3；Phenom™ II x2；Athlon II™ x4；Athlon II™ x3；Athlon II™ x2；Sempron™是AMD有限公司的注册商标。 AMI ® 是American Megatrend, Inc.的注册商标。 Kensington 和 MicroSaver 是Kensington 科技集团的注册商标。 Microsoft 是Microsoft有限公司的注册商标。 Netware® 是Novell, Inc的注册商标。 AMD, AMD徽标是AMD有限公司在美国和其它国家的注册商标。 PS/2 和 OS®/2 是International Business Machines有限公司的注册商标。 PCMCIA 和 CardBus 是个人电脑存储卡国际联合会的注册商标。 Windows® 98/2000/ /XP/Vista/7 是Microsoft有限公司的注册商标。
CX系列产品使用与维护
2 英信CX系列安装部件图解
cx300 cx500 cx700
2.1 CX300
2.1.1 体系结构
存储 处理器
SP 光纤通道 x 2 镜像缓存 CPU FC 后备电源 风扇 电源 风扇 电源 风扇 后备电源
CMI
存储 处理器
SP 光纤通道 x 2 镜像缓存 CPU FC
A/C Input 一个HSSDC磁盘接口
2.2 CX500
2.2.1 体系结构
存储处理器 存储处理器
CMI
SP 光纤通道 x 2 镜像缓存 CPU FC CPU FC 后备电源 风扇 电源 风扇 风扇 后备电源 SP 光纤通道 x 2 镜像缓存 CPU FC CPU FC
CX500 - 部门存储
120K IOPS 和 760 MB/s 带宽 四个前端主机连接、四个后端磁盘连接 最多可支持 120 个驱动器（FC： 146 GB ATA：320 GB ） 4 GB 标准缓存
CX700 - 数据中心存储
200K IOPS 和 1,520 MB/s 带宽 八个前端主机连接、八个后端磁盘连接 最多可支持 240 个驱动器（FC：146 GB；ATA：320 GB） 8 GB 标准缓存
4.2 安装存储软件
1) 登录存储系统
在IE Browser中输入SP-A(或SP-B)的IP地址 输入用户名，密码admin/password
2) 进入存储系统主界面
3) 安装存储软件，NDU的进程
B 准备工作
一根NULL cable modem 一个管理电脑（Server, PC, Laptop） 在Laptop上安装Navisphere 6.x CLI IP地址, 子网掩码, 主机名, 网关 参阅CX-Series 初始化安装文档
2011典型内存 4GB DDR3 1333
技术参数
CL延迟
9-9-9-24
其他参数
工作电压
1.5V
保修信息
保修政策
全国联保，享受三包服务
质保时间
终身质保
客服电话
800-810-1972
电话备注
星期一到星期五：上午8：00-17：00
详细内容
售后服务由品牌厂商提供，支持全国联保，内存自购买日起，可享有三包服务。以上声明不对因意外事故、天灾、操作失误、使用环境、人为伤害以及未经授权的拆卸、修理、改装造成的损害或被厂商证明为非原厂生产的正规产品的损坏负责。消费者在送修之前请务必自行将内容先行备份，送修后的产品中所有内容都将被清除。进入官网>>
数据来源：中关村在线报价中心()
超频能力一般
优点：
现在价格便宜，我150实体店入手的，超到1600一直没问题。
缺点：
超1866时开不了机，是不是内存体质差了点，难不成我买的是假货？我的主板都是华硕Z68-V PRO，能支持更高的频率。
总结：
价格可以，性能一般。
金士顿2GB DDR3 1333
保修信息
保修政策
全国联保，享受三包服务
质保时间
终身质保
客服电话
800-810-1972
电话备注
星期一到星期五：上午8：00-17：00
详细内容
售后服务由品牌厂商提供，支持全国联保，内存自购买日起，可享有三包服务。以上声明不对因意外事故、天灾、操作失误、使用环境、人为伤害以及未经授权的拆卸、修理、改装造成的损害或被厂商证明为非原厂生产的正规产品的损坏负责。消费者在送修之前请务必自行将内容先行备份，送修后的产品中所有内容都将被清除。进入官网>>
FPGA可编程逻辑器件芯片XC9536-10PCG44I中文规格书
Configuration Sequence Startup (Step8)Figure 5-11:Startup Sequence (Step 8)After the configuration frames are loaded, the bitstream asserts the DESYNC command, and then the START command instructs the device to enter the startup sequence. Thestartup sequence is controlled by an eight-phase (phases 0–7) sequential state machine that is clocked by the JTAG clock or any user clock defined by the BitGen -g StartupCLK option. The startup sequencer performs the tasks outlined in Table5-15.Table 5-15:User-Selectable Cycle of Startup EventsPhase Event1–6Wait for DCMs and PLLs to lock (optional)1–6Assert Global Write Enable (GWE), allowing RAMs and flip-flops to change state1–6Negate Global 3-State (GTS), activating I/O1–6Release DONE pin7Assert End Of Startup (EOS)The specific order of startup events (except for EOS assertion) is user-programmablethrough BitGen options (refer to UG628, Command Line Tools User Guide). Table5-15 shows the general sequence of events, although the specific phase for each of these startup events is user-programmable (EOS is always asserted in the last phase). Refer to Chapter2,Configuration Interface Basics, for important startup option guidelines. By default, startup events occur as shown in Table5-16.Table 5-16:Default BitGen Sequence of Startup EventsPhase Event4Release DONE pin5Negate GTS, activating I/O6Assert GWE, allowing RAMs and flip-flops to change state7Assert EOSThe startup sequence can be forced to wait for the DCMs and PLLs to lock with theappropriate BitGen options. These options are typically set to prevent DONE and GWE from being asserted (preventing device operation) before the DCMs and PLLs have locked.Startup can wait for DCMs and PLLs by assigning the LCK_CYCLE option to a startup phase. If this is not done, startup does not wait for any DCMs or PLLs. When theLCK_CYCLE is set to a startup phase, the FPGA waits for all DCMs and PLLs to lock prior to moving to the next phase of startup. To only wait for specific DCMs to lock, assign the STARTUP_WAIT attribute to those instances. There is no corresponding attribute for PLLs.When waiting for DCM and PLL lock, the GTS startup setting must be enabled on a phase before LCK_CYCLE. Failing to do so results in the FPGA waiting for the clock componentsChapter 5:Configuration Detailsindefinitely and never completing startup. For additional information on using theLCK_CYCLE feature in master configuration modes, see Required Data Spacing between MultiBoot Images, page 138.The DONE signal is released by the startup sequencer on the cycle indicated by the user, but the startup sequencer does not proceed until the DONE pin actually sees a logic High. The DONE pin is an open-drain bidirectional signal with an internal pull-up by default. By releasing the DONE pin, the device simply stops driving a logic Low and the pin is weakly pulled High. Table 5-17 shows signals relating to the startup sequencer. Figure 5-12 shows the waveforms relating to the startup sequencer.In a Slave configuration mode, additional clocks are needed after DONE goes High to complete the startup events. In Master configuration mode, the FPGA provides these clocks. The number of clocks necessary varies depending on the settings selected for the startup events. A general rule is to apply eight clocks (with DIN all 1’s) after DONE has gone High. More clocks are necessary if the startup is configured to wait for the DCM and PLLs to lock (LCK_CYCLE).When using the external master clock (USERCCLK) pin, I/O standard becomes enabled at the EOS phase. As I/O standard changes from the default pre-configuration value to the user specified value, a glitch might appear. It is recommended to use clock enables or a reset to prevent glitches from affecting the design.Table 5-17:Signals Relating to the Startup SequencerSignal NameTypeAccess (1)DescriptionDONEBidirectional (2)DONE pin or Spartan-6 FPGA Status RegisterIndicates configuration is complete. Can be held Low externally to synchronize startup with other FPGAs. GWE StatusSpartan-6 FPGA Status RegisterGlobal Write Enable (GWE). When deasserted, GWE disables the CLB and the IOB flip-flops as well as other synchronous elements on the FPGA.GTSGlobal 3-State (GTS). When asserted, GTS disables all the I/O driversexcept for the configuration pins.DCM_LOCKDCM_LOCK indicates when all DCMs and PLLs have locked. This signal is asserted by default. It is active if the STARTUP_WAIT option is used on a DCM and the LCK_CYCLE option is used when the bitstream is generated.Notes:rmation on the Spartan-6 FPGA status register is available in Table 5-35, page 105. Information on accessing the device status register via JTAG is available in Table 6-5, page 124. Information on accessing the device status register via SelectMAP is available in Table 6-1, page 119.2.Open-drain output with internal pull-up by default; the optional driver is enabled using the BitGen DriveDone option.3.GWE is asserted synchronously to the configuration clock (CCLK) and has a significant skew across the part. Therefore, sequential elements might not be released synchronously to the system clock and timing violations can occur during startup. It is recommended to reset the design after startup and/or apply some other synchronization technique.Required Data Spacing between MultiBoot ImagesChapter 7:Reconfiguration and MultiBootChapter 9:Advanced Configuration InterfacesMultiple Device SelectMAP ConfigurationMultiple Spartan-6 devices in Slave SelectMAP mode can be connected on a common SelectMAP bus (Figure 9-3). In a SelectMAP bus, the D, CCLK, RDWR_B, BUSY,PROGRAM_B, DONE, and INIT_B pins share a common connection between all of the devices. To allow each device to be accessed individually, the CSI_B (Chip Select) inputs must not be tied together. External control of the CSI_B signal is required and is usually provided by a microprocessor or CPLD.If Readback is going to be performed on the device after configuration, the RDWR_B and BUSY signals must be handled appropriately. (For details, refer to Chapter 6, Readback and Configuration Verification .)Otherwise, RDWR_B can be tied Low and BUSY can be ignored. The BUSY signal never needs to be monitored when configuring Spartan-6 devices. Refer to Bitstream Loading (Steps 4-7), page 85 and to Chapter 6, Readback and Configuration Verification .Notes relevant to Figure 9-3:1.The DONE pin is by default an open-drain output requiring an external pull-up resistor. In this arrangement, the active DONE driver must be disabled.2.The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is required.3.The BitGen startup clock setting must be set for CCLK for SelectMAP configuration.4.The BUSY signals can be left unconnected if readback is not needed.5.An external controller such as a microprocessor or CPLD is needed to control configuration.Figure 9-3:Multiple Slave Device Configuration on an 8-Bit SelectMAP Bus。
XC9510AXXXSX资料
1351XC9510 ETR1007_001.doc◆Synchronous Step-Down DC/DC Converterwith Built-In LDO Regulator Plus Voltage Detector ◆Step-Down DC/DC Converter's Output Connected InSeries with LDO Regulator◆High Efficiency, Low Noise Regulated Output ◆SOP-8 Package for High Current ◆Small-Footprint ◆Output Current DC/DC:800mA, VR: 400mA ◆Ceramic Capacitor Compatible (Low ESR capacitors)■GENERAL DESCRIPTION The XC9510 series consists of a step-down DC/DC converter and a high-speed LDO regulator connected in series with the DC/DC converter's output. A voltage detector is also built-in.A highly efficient, low noise output is possible since the regulator is stepped-down further from the DC/DC output. The DC/DC converter block incorporates a P-channel driver transistor and a synchronous N-channel switching transistor.With an external coil, diode and two capacitors, the XC9510can deliver output currents up to 800mA at efficiencies over 90%. The XC9510 is designed for use with small ceramic capacitors. A choice of three switching frequencies are available, 300 kHz, 600 kHz, and 1.2 MHz. Output voltage settings for the DC/DC is set-up internally in 100mV steps within the range of 1.6V to 4.0V(±2.0%) and for the VR are set-up internally within the range of 0.9V to 4.0V (±2.0%).For the VD, the range is of 0.9V to 5.0V (±2.0%). The soft start time of the series is internally set to 5ms. With the built-in U.V.L.O. (Under Voltage Lock Out) function, the internal P-channel driver transistor is forced OFF when input voltage becomes 1.4 V or lower. The operational states of the DC/DC and the regulator blocks can be changed by inputting three kinds of voltage level via the CE/MODE pin. The functions of the MODE pin can be selected via the external control pin to switch the DC/DC control mode and the disable pin to shut down the regulator block.■APPLICATIONS●CD-R / RW, DVD ●HDD●PDAs, portable communication modem ●Cellular phones ●Palmtop computers●Cameras, video recorders■TYPICAL APPLICATION CIRCUIT■FEATURESInput Voltage Range : 2.4V ~ 6.0VLow ESR Capacitor : Ceramic capacitor compatible (Low ESR Capacitors) VD Function : Detects output voltage from theV DOUT pin while sensing either V DD , D COUT , or V ROUT internally. N-ch open drain output<DC/DC Converter Block>Output Voltage Range : 1.6V ~ 4.0V (Accuracy ±2%) Output Current : 800mA Controls : PWM Control,PWM, PWM/PFMAutomatic Switching ExternalOscillation Frequency : 300kHz, 600kHz, 1.2MHz <Regulator Block>Output Voltage Range : 0.9V ~ 4.0V (Accuracy ±2%) Current Limit : 600mA Dropout Voltage : 160mV @ I OUT =200mA(V OUT =2.8V)High Ripple Rejection : 60dB @1kHz (V OUT =2.8V)■TYPICAL PERFORMANCE CHARACTERISTICS1352XC9510 Series■PIN CONFIGURATIONSOP-8 (TOP VIEW)■PIN ASSIGNMENTDESIGNATORDESCRIPTION SYMBOL DESCRIPTION① Control Methods AndThe VD Sense Pin As chart below: -②③Setting Voltage & SpecificationsInternal standard : Setting voltage and specifications of each DC/DC, VR, and VD Based on the internal standard)3 : 300kHz6 : 600kHz④ DC/DC OscillationFrequencyC : 1.2MHz⑤ Package S : SOP-8R : Embossed Tape, standard feed⑥Device OrientationL : Embossed Tape, reverse feedSERIES TYPE DC/DC CONTROL METHODSCE=”VCEH” LEVELCE=”VCEM” LEVEL CE=”VCEL” LEVELVD SENSEPIN AV DD B D COUT C - - DC/DC: OFFVR: OFFVD: ON V ROUT D V DD E D COUT F PWM ControlDC/DC: ON VR: OFF VD: ON DC/DC: ON VR: ON VD: ON DC/DC: OFF VR: OFF VD: ON V ROUT H V DD K D COUT XC9510LPWM, PFM/PWM Manual SwitchPFM / PWM Automatic SwitchPWM ControlDC/DC: OFF VR: OFF VD: ONV ROUTPIN NUMBERPIN NAMEFUNCTION1 P GND Power Ground2 CE/MODE Chip Enable / MODE Switch3 V DD Power Supply4 V DOUT VD Output5 A GND Analog Ground6 V ROUT VR Output7 D COUT DC/DC Output8 LX Switch■PRODUCT CLASSIFICATION●Ordering InformationXC9510①②③④⑤⑥ Theinput for the voltage regulator block comes from the DC/DC. ●Control Methods, CE/MODE Pin, VDSENSE Pin1353XC9510SeriesMARK① ②PRODUCT SERIES1 0XC9510****S*MARKDC/DC CONTROLCE/MODE PIN (H level)CE/MODE PIN(M level)CE/MODE PIN(L level)VD SENSE PRODUCT SERIESA V DD XC9510A***S*B DC OUT XC9510B***S* C - -VR OUT XC9510C***S* D V DD XC9510D***S* E DC OUT XC9510E***S* F PWM ControlVR:OFF VR:ON VR OUT XC9510F***S* H V DD XC9510H***S* K DC OUT XC9510K***S* LPWM,PFM/PWM Manual Switch PFM/PWM Auto SwitchPWM ControlDC/DC:OFFVR:OFFVD:ON VR OUT XC9510L***S*■MARKING RULE●SOP-8①②Represents product series③Represents DC/DC control methods, CE/MODE pins and VD sense pin■PACKAGING INFORMATION●SOP-8SOP-8(TOP VIEW)1354XC9510 SeriesMARK④ ⑤DC/DC VR VD 1 3 3.3V 1.8V 4.0V XC9510*13*S*MARK OSCILLATION FREQUENCY PRODUCT SERIES3 300kHz XC9510***3A* 6 600kHz XC9510***6A* C 1.2MHzXC9510***CA*MARK PRODUCTION YEAR3 20034 2004■BLOCK DIAGRAM⑧⑨Represents production lot number0 to 9,A to Z reverse character 0 to 9, A to Z repeated (G,I,J,O,Q,W excepted) Note: No character inversion used* Diodes shown in the above circuit are protective diodes.④⑤Represents detect voltage DC/DC,VR and VDex)⑦Represents last digit of production year.ex)⑥Represents oscillation frequency .■MARKING RULE (Continued)PRODUCT SERIES1355XC9510SeriesPARAMETER SYMBOL RATINGS UNIT V DD Pin Voltage VDD - 0.3 ~ 6.5 V DC OUT Pin Voltage DC OUT - 0.3 ~ V DD + 0.3 V VR OUT Pin Voltage VR OUT - 0.3 ~ V DD + 0.3VVR OUT Pin Current IR OUT 800 mA VD OUT Pin Voltage VD OUT - 0.3 ~ V DD + 0.3VVD OUT Pin Current I VD 50 mALx Pin Voltage Lx - 0.3 ~ V DD + 0.3VLx Pin Current ILx ±1300 mA CE/MODE Pin Voltage CE/MODE- 0.3 ~ V DD + 0.3V Power DissipationSOP-8Pd 650* mW Operating Temperature Range Topr - 40 ~ + 85 ℃ Storage Temperature Range Tstg- 55 ~ + 125℃■ABSOLUTE MAXIMUM RATINGSTa = 25℃(*) When PC board mounted.1356XC9510 SeriesPARAMETER SYMBOLCONDITIONSMIN.TYP .MAX.UNITSCIRCUITSupply Current 1 I DD 1 V IN =CE=D COUT5.0V - 250 310 μA 1 Supply Current 2 I DD 2 V IN =CE=5.0V, D COUT 0V - 300 360 μA 1 Stand-by Current (*1) I STBV IN =6.5V, CE=0V -3.07.0μA1Input Voltage Range V IN 2.4 - 6.0 V - CE ‘H’ Level Voltage *XC9510D/E/F V CEHV DD -0.3- V DD V 2 CE ‘H’ Level Voltage *XC9510H/K/L V CEHV DD -0.3- V DD V 3CE ‘M’ Level Voltage V CEM 0.6 - V DD -1.2 V 3 CE ‘L’ Level Voltage V CELV SS - 0.25 V 3CE ‘H’ Level Current I CEH- 0.1 - 0.1 μA 1 CE ‘L’ Level CurrentI CEL- 0.1 - 0.1 μA1=====■ELECTRICAL CHARACTERISTICSXC9510xxxCSx●Common CharacteristicsTopr=25℃●DC/DC Converter (2.2V product)1357XC9510Series■ELECTRICAL CHARACTERISTICS (Continued)XC9510xxxCSx (Continued)●Regulator (1.8V product)Topr=25℃Test conditions: Unless otherwise stated:DC/DC : VIN=3.6V [@ DC OUT :2.2V] VR: V IN = 2.8V (V IN =VR OUT (T) + 1.0V) VD: V IN =5.0VCommon conditions for all test items: CE=V IN , MODE=0V * VR OUT (T) : Setting output voltageNOTE:*1 : Including VD supply current (VD operates when in stand-by mode.) *2 : Including hysteresis operating voltage range. *3 : ON resistance (Ω)= 0.05 (V) / ILX (A)*4 : EFFI = { ( Output Voltage x Output Current ) / ( Input Voltage x Input Current) } x 100*5 : Time until it short-circuits DC OUT with GND through 1Ωof resistance from a state of operation and is set to DC OUT =0Vfrom current limit pulse generating. *6 : Vdif = (V IN 1(*7)- VR OUT 1(*8))*7 : V IN 1 = The input voltage when VR OUT 1 appears as input voltage is gradually decreased.*8 : VR OUT 1 = A voltage equal to 98% of the output voltage whenever an amply stabilized I OUT {VR OUT (T) + 1.0V} is input.*9 : Current limit = When V IN is low, limit current may not be reached because of voltage falls caused by ON resistance orserial resistance of coils.*10: Integral latch circuit=latch time may become longer and latch operation may not work when V IN is 3.0V or more. *11: V DR (E) = VD release voltage*12: When temperature is high, a current of approximately 5.0μA (maximum) may leak.XC9510 SeriesCircuit 1 Supply Current, Stand-by Current, CE Current Circuit 2Output Voltage (VR), Load Regulation, Dropout Voltage,Maximum Output Current, (MODE Voltage)Circuit 3 Output Voltage (DC/DC) Oscillation Frequency,U.V.L.O. Voltage, Soft-start Time, CE Voltage,Circuit 4Minimum Duty Cycle, Maximum Duty Cycle Maximum Output Current, Efficiency, (PFM Duty Cycle),(MODE Voltage)Circuit 5 Lx ON Resistance Circuit 6Current Limit 1 (DC/DC)■TEST CIRCUITSCL:4.7uF(ceramic, IROUT<300mA)10uF(ceramic, IROUT>300mA)ILX13581359XC9510SeriesCircuit 7Current Limit 2 (VR), Short Circuit Current (VR) Circuit 8Detect Voltage, Release Voltage (Hysteresis Range)* For the measurement of the VDD_Sense products, the input voltage was controlled.Circuit 9 VD Output Current Circuit 10Latch TimeCircuit 11 Off-Leak Circuit 12Ripple Rejection Rate■TEST CIRCUITS (Continued)ΩCL:4.7uF(ceramic, IROUT<300mA)10uF(ceramic, IROUT>300mA)(ceramic)* For the measurement of the VDD_Sense products, the input voltage was controlled.1360XC9510 SeriesFOSC L1.2MHz 4.7μH (CDRH4D28C, SUMIDA)600kHz 10μH (CDRH5D28, SUMIDA) 300kHz22μH (CDRH6D28, SUMIDA)CINCL1CL2 *2IR OUT<300mA 4.7μ F (ceramic, TAIYO YUDEN) 4.7μF(ceramic, TAIYO YUDEN)10μF(ceramic, TAIYO YUDEN)IR OUT >300mA10μF (ceramic, TAIYO YUDEN)■TYPICAL APPLICATION CIRCUITSOP-8 (TOP VIEW)*1 The DC/DC converter of the XC9510 series automatically switches between synchronous / non-synchronous. The Schottky diode is not normally needed. However, in cases where high efficiency is required when using the DC/DC converter during in the light load while in non-synchronous operation, please connect a Schottky diode externally.*2 Please be noted that the recommend value above of the CL2 may be changed depending on the input voltage value and setting voltage value.■OPERATIONAL EXPLANATIONThe XC9510 series consists of a synchronous step-down DC/DC converter,a high speed LDO voltage regulator, and avoltage detector. Since the LDO voltage regulator is stepped-down from the DC/DC’s output,high efficiency and low noise is possible even at lower output voltages.●DC/DC ConverterThe series consists of a reference voltage source, ramp wave circuit, error amplifier, PWM comparator, phase compensation circuit, output voltage adjustment resistors, driver transistor, synchronous switch, current limiter circuit,U.V.L.O. circuit and others. The series ICs compare, using the error amplifier, the voltage of the internal voltage reference source with the feedback voltage from the V OUT pin through split resistors. Phase compensation is performed on the resulting error amplifier output, to input a signal to the PWM comparator to determine the turn-on time during PWM operation. The PWM comparator compares, in terms of voltage level, the signal from the error amplifier with the ramp wave from the ramp wave circuit, and delivers the resulting output to the buffer driver circuit to cause the Lx pin to output a switching duty cycle. This process is continuously performed to ensure stable output voltage. The current feedback circuit monitors the P-channel MOS driver transistor current for each switching operation, and modulates the error amplifier output signal to provide multiple feedback signals. This enables a stable feedback loop even when a low ESR capacitor, such as a ceramic capacitor, is used, ensuring stable output voltage.<Reference Voltage Source>The reference voltage source provides the reference voltage to ensure stable output voltage of the DC/DC converter.<Ramp Wave Circuit>The ramp wave circuit determines switching frequency. The frequency is fixed internally and can be selected from 300kHz, 600 kHz and 1.2 MHz. Clock pulses generated in this circuit are used to produce ramp waveforms needed for PWM operation, and to synchronize all the internal circuits.<Error Amplifier>The error amplifier is designed to monitor output voltage. The amplifier compares the reference voltage with the feedback voltage divided by the internal split resistors. When a voltage lower than the reference voltage is fed back, the output voltage of the error amplifier increases. The gain and frequency characteristics of the error amplifier output are fixed internally to deliver an optimized signal to the mixer.1361■OPERATIONAL EXPLANATION (Continued)<PWM/PFM>The XC9510A to F series are PWM control, while the XC9510H to L series can be automatically switched between PWM control and PWM/PFM control. The PWM of the XC9510A to F series are controlled on a specified frequency from light loads through the heavy loads. Since the frequency is specified, the composition of a noise filter etc. becomes easy.However, the efficiency at the time of the light load may become low.The XC9510H to L series can switch in any timing between PWM control and PWM/PFM automatic switching control.The series cannot control only PFM mode. If needed, the operation can be set on a specified frequency; therefore, the control of the noise etc. is possible and the high efficiency at the time of the light load during PFM control mode is possible. With the automatic PWM/PFM switching control function, the series ICs are automatically switched from PWM control to PFM control mode under light load conditions. If during light load conditions the coil current becomes discontinuous and on-time rate falls lower than 30%, the PFM circuit operates to output a pulse with 30% of a fixed on-time rate from the Lx pin. During PFM operation with this fixed on-time rate, pulses are generated at different frequencies according to conditions of the moment. This causes a reduction in the number of switching operations per unit of time, resulting in efficiency improvement under light load conditions. However, since pulse output frequency is not constant, consideration should be given if a noise filter or the like is needed. Necessary conditions for switching to PFM operation depend on input voltage, load current, coil value and other factors.<Synchronous / Non-synchronous>The XC9510 series automatically switches between synchronous / non-synchronous according to the state of the DC/DC converter.Highly efficient operations are achievable using the synchronous mode while the coil current is in a continuous state. The series enters non-synchronous operation when the built-in N-ch switching transistor for synchronous operation is shutdown which happens when the load current becomes low and the operation changes to a discontinuous state. The IC can operate without an external schottky diode because the parasitic diode in the N-ch switching transistor provides the circuit's step-down operation. However, since Vf of the parasitic diode is a high 0.6V, the efficiency level during non-synchronous operation shows a slight decrease. Please use an external schottky diode if high efficiency is required during light load current. ●Continuous Mode: Synchronous●Discontinuous Mode: Non-Synchronous■OPERATIONAL EXPLANATION (Continued)<Current Limit>The current limiter circuit of the XC9510 series monitors the current flowing through the P-channel MOS driver transistor connected to the Lx pin, and features a combination of the constant-current type current limit mode and the operation suspension mode.①When the driver current is greater than a specific level, the constant-current type current limit function operatesto turn off the pulses from the Lx pin at any given timing.②When the driver transistor is turned off, the limiter circuit is then released from the current limit detection state.③At the next pulse, the driver transistor is turned on. However, the transistor is immediately turned off in thecase of an over current state.④When the over current state is eliminated, the IC resumes its normal operation.The IC waits for the over current state to end by repeating the steps ① through ③ . If an over current state continues for 8msec* and the above three steps are repeatedly performed, the IC performs the function of latching the OFF state of the driver transistor, and goes into operation suspension mode. Once the IC is in suspension mode, operations can be resumed by either turning the IC off via the CE/MODE pin, or by restoring power to the V IN pin. The suspension mode does not mean a complete shutdown, but a state in which pulse output is suspended; therefore, the internal circuitry remains in operation. The constant-current type current limit of the XC9510 series can be set at 1.1A.<U.V.L.O. Circuit>When the V IN pin voltage becomes 1.4 V or lower, the P-channel output driver transistor is forced OFF to prevent false pulse output caused by unstable operation of the internal circuitry. When the V IN pin voltage becomes 1.8 V or higher, switching operation takes place. By releasing the U.V.L.O. function, the IC performs the soft start function to initiate output startup operation. The soft start function operates even when the V IN pin voltage falls momentarily below the U.V.L.O. operating voltage. The U.V.L.O. circuit does not cause a complete shutdown of the IC, but causes pulse output to be suspended; therefore, the internal circuitry remains in operation.●High Speed LDO Voltage RegulatorThe voltage regulator block of the XC9510 series consists of a reference voltage source, error amplifier, and current limiter circuit.The voltage divided by split resistors is compared with the internal reference voltage by the error amplifier.The P-channel MOSFET, which is connected to the VR OUT pin, is then driven by the subsequent output signal. The output voltage at the VR OUT pin is controlled and stabilized by a system of negative feedback. A stable output voltage is achievable even if used with low ESR capacitors as a phase compensation circuit is built-in.<Reference Voltage Source>The reference voltage source provides the reference voltage to ensure stable output voltage of the regulator.<Error Amplifier>The error amplifier compares the reference voltage with the signal from VR OUT, and the amplifier controls the output of the P-ch driver transistor.<Current Limit Circuit>The voltage regulator block includes a combination of a constant current limiter circuit and a foldback circuit. When the load current reaches the current limit level, the current limiter circuit operates and the output voltage of the voltage regulator block drops. As a result of this drop in output voltage, the foldback circuit operates, output voltage drops further and the load current decreases. When the VR OUT and GND pin are shorted, the load current of about 30mA flows. 13621363■OPERATIONAL EXPLANATION (Continued)●Voltage DetectorThe detector block of the XC9510 series detects output voltage from the VD OUT pin while sensing either V DD , DC OUT , or VR OUT internally. (N-channel Open Drain Type)< CE / MODE Pin Function>The operation of the XC9510 series' DC/DC converter block and voltage regulator block will enter into the shut down mode when a low level signal is input to the CE/MODE pin. During the shut down mode, the current consumption occurs only in the detector and is 3.0μA (TYP .), with a state of high impedance at the Lx pin and DC OUT pin. The IC starts its operation by inputting a high level signal or a middle level signal to the CE/MODE pin. The input to the CE/MODE pin is a CMOS input and the sink current is 0μA (TYP .). The operation of the XC9510D to F series' voltage detector block will enter into stand-by mode when a high level signal is input to the CE/MODE pin. The voltage regulator block will operate when a middle level signal is input. But when a low level signal is input, the voltage regulator block will enter into stand-by mode. With the XC9510H to L series control can be PWM control when the CE/MODE pin is 'M' level and PWM/PFM automatic switching control when the CE/MODE pin is 'H' level.●Application Information 1. The XC9510 series is designed for use with ceramic output capacitors. If, however, the potential difference betweendropout voltage or output current is too large, a ceramic capacitor may fail to absorb the resulting high switching energy and oscillation could occur on the output. If the input-output potential difference is large, connect an electrolytic capacitor in parallel to compensate for insufficient capacitance.2. Spike noise and ripple voltage arise in a switching regulator as with a DC/DC converter. These are greatly influenced by externalcomponent selection, such as the coil inductance, capacitance values, and board layout of external components. Once the design has been completed, verification with actual components should be done.3. When the difference between V IN and V OUT is large in PWM control, very narrow pulses will be outputted, and thereis the possibility that some cycles may be skipped completely.4. When the difference between V IN and V OUT is small, and the load current is heavy, very wide pulses will be outputtedand there is the possibility that some cycles may be skipped completely: in this case, the Lx pin may not go low at all.■NOTES ON USE●DC/DC Waveform (3.3V, 1.2MHz)< External Components>L:4.7μH(CDRH4D28C,SUMIDA)CIN:4.7μF(ceramic) CL:10μF(ceramic) < External Components>L:4.7μH(CDRH4D28C,SUMIDA)CIN:4.7μF(ceramic) CL:10μF(ceramic)1364●Application Information (Continued)5. The IC's DC/DC converter operates in synchronous mode when the coil current is in a continuous state andnon-synchronous mode when the coil current is in a discontinuous state. In order to maintain the load current value when synchronous switches to non-synchronous and vise versa, a ripple voltage may increase because of the repetition of switching between synchronous and non-synchronous. When this state continues, the increase in the ripple voltage stops. To reduce the ripple voltage, please increase the load capacitance value or use a schottky diode externally. When the current used becomes close to the value of the load current when synchronous switches to non- synchronous and vise versa, the switching current value can be changed by changing the coil inductance value. In case changes to coil inductance are to values other than the recommended coil inductance values, verification with actual components should be done.Ics=(V IN - DC OUT) x OnDuty / (L x Fosc)Ics: Switching current from synchronous rectification to non-synchronous rectification OnDuty: OnDuty ratio of P-ch driver transistor (.=.step down ratio : DC OUT / V IN)L: Coil inductance valueFosc: Oscillation frequencyID OUT: The DC/DC load current(the sum of the DC/DC's and the regulator's load if the regulator has load.)6. When the XC9510H to L series operates in PWM/PFM automatic switching control mode, the reverse current maybecome quite high around the load current value when synchronous switches to non-synchronous and vise versa (also refer to no. 5 above). Under this condition, switching synchronous rectification and non-synchronous rectification may be repeated because of the reverse current, and the ripple voltage may be increased to 100mV or more. The reverse current is the current that flows in the PGND direction through the N-ch driver transistor from the coil. The conditions which cause this operation are as follows.PFM Duty < Step down ratio = DC OUT / V IN x 100 (%)PFM Duty: 30% (TYP.)Please switch to PWM control via the MODE function in cases where the load current value of the DC/DC converter is close to synchronous.■NOTES ON USE (Continued)●DC/DC Waveform (1.8V, 600kHz) @ VIN=6.0V< External Components>L:10μH(CDRH5D28C,SUMIDA)CIN:4.7μF(ceramic)CL:10μF(ceramic)Step down ratio : 1.8V / 6.0V = 30%<PFM Duty 31%>1365●Application Information (Continued)7. With the DC/DC converter of the IC, the peak current of the coil is controlled by the current limit circuit. Since thepeak current increases when dropout voltage or load current is high, current limit starts operating, and this can lead to instability. When peak current becomes high, please adjust the coil inductance value and fully check the circuit operation. In addition, please calculate the peak current according to the following formula:Peak current: Ipk = (V IN - DC OUT ) x OnDuty / (2 x L x Fosc) + ID OUT8. When the peak current, which exceeds limit current flows within the specified time, the built-in driver transistor is turned off (the integral latch circuit). During the time until it detects limit current and before the built-in transistor can be turned off, the current for limit current flows; therefore, care must be taken when selecting the rating for the coil or the Schottky diode.9. When VI N is low, limit current may not be reached because of voltage falls caused by ON resistance or serialresistance of the coil.10. In the integral latch circuit, latch time may become longer and latch operation may not work when V IN is 3.0V ormore.11. Use of the IC at voltages below the recommended voltage range may lead to instability.12. This IC and the external components should be used within the stated absolute maximum ratings in order to preventdamage to the device.13. Since the DC/DC converter and the regulator of the XC9510 series are connected in series, the sum of the outputcurrent (ID OUT ) of the DC/DC and the output current (IR OUT ) of the VR makes the current flows inside the DC/DC converter. Please be careful of the power dissipation when in use. Please calculate power dissipation by using the following formula.Pd =PdDC/DC + PdVR DC/DC power dissipation (when in synchronous operation) : PdDC/DC = ID OUT 2 x RON VR power dissipation: PdVR=(DC OUT – VR OUT ) x IR OUTRON: ON resistance of the built-in driver transistor to the DC/DC (= 0.5Ω<TYP.>)RON=Rpon x P-chOnDuty / 100+ Rnon x (1 – P-chOnDuty / 100)14. The voltage detector circuit built-in the XC9510 series internally monitor the V DD pin voltage, the DC/DC output pinvoltage and VR output pin voltage. For the XC9510B/C/E/F/K/L series, which voltage detector circuit monitors the DC/DC output pin voltage and the VR output pin voltage, please determine the detect voltage value (VDF) by the following equation.VDF ≦(Setting voltage on both the DC OUT voltage and the VR OUT voltage)×85%** An assumed value of tolerance among the DC OUT voltage, the VR OUT voltage, and the VD release voltage (The VD detect voltage and hysteresis range).■NOTES ON USE (Continued)1366●Instructions on Pattern Layout1. In order to stabilize V IN 's voltage level, we recommend that a by-pass capacitor (CI N ) be connected as close aspossible to the V DD & AGND pins. This IC is the composite IC of the DC/DC converter and regulator. Fluctuation of the V IN 's voltage level causes mutual interference.2. Please mount each external component as close to the IC as possible.3. Wire external components as close to the IC as possible and use thick, short connecting traces to reduce the circuitimpedance.4. Make sure that the PCB GND traces are as thick as possible, as variations in ground potential caused by highground currents at the time of switching may result in instability of the DC/DC converter and have adverse influence on the regulator output.5. If using a Schottky diode, please connect the anode side to the AGND pin through C IN . Characteristicdegradation caused by the noise may occur depending on the arrangement of the Schottky diode.<SOP-8 Recommended pattern layout>■NOTES ON USE (Continued)。
CS5530中文资料
C9835资料
Low-EMI Clock Generator for Intel®Mobile 133-MHz/3 SO-DIMM Chipset SystemsC9835Features•Meets Intel’s Mobile 133.3MHz Chipset•Three CPU Clocks (66.6/100/133.3 MHz, 2.5V)•Six SDRAM Clocks, 1-DCLK (100/133.3 MHz, 3.3V)•Seven PCI Clocks (33MHz, 3.3V), one free running •Two IOAPIC clocks, synchronous to CPU clock (33.3 MHz, 2.5V)•One REF Clock•Two 48-MHz fixed non-SSCG clocks (USB and DOT)•Three 3V66 clocks (66.6 MHz, 3.3V) ICH, HUBLINK, and AGP memory•One selectable frequency for VCH video channel clock (48-MHz non-SSCG, 66.6-MHz CPU-SSCG, 3.3V)•Power management using power-down, CPU stop, and PCI stop pins•Three function select pins (include test-mode select)•Cypress Spread Spectrum for best electromagnetic interference (EMI) reduction •SMBUS support with readback•56-pin SSOP and TSSOP packagesNote:1.These are the frequencies that are selectable after power up using the SEL1 and SEL0 hardware pins. Other frequencies may be chosen using the devicesSMBUS interface. See the expanded frequency for a complete listing of all of the availible frequencies.2.Will be set to 133MHz, when SMBUS Byte3, Bit 0 is set to logic 1.Table 1.Function Table [1]TEST#SEL1SEL0CPU(0:2)SDRAM(0:5)DCLK3V66(0:2)PCIF(1:6)48M(0:1)REF IOAPIC(0:10)0X 0Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 0X 1TCLK/2TCLK/2TCLK/3TCLK/6TCLK/2TCLK TCLK/610066.6100.0[2]66.633.34814.31833.3101100.0100.0[2]66.633.34814.31833.3110133.3 133.366.633.34814.31833.3111133.3 100.0[2]66.633.34814.31833.3Note:3. A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin. If these bypass capacitors are not close to the pins theirhigh-frequency filtering characteristic will be cancelled by the lead inductance of the traces.Pin Description [3]Pin NamePWR Description1REF VDD 3.3V 14.318 MHz clock output3XIN VDD Oscillator buffer input . Connect to a crystal or to an external clock.4XOUT VDDOscillator buffer output . Connect to a crystal. Do not connect when an external clock is applied at X IN .49, 50, 52CPU(0:2)VDDC 2.5V Host bus clock outputs 7, 8, 93V66(0:2)VDD 3.3V Fixed 66.6 MHz clock outputs12PCI_FVDDP3.3V PCI clock output . This clock continues to run when PCI_STP# is at a logic low level.13, 15, 16, 18,19, 20PCI (1:6)VDDP 3.3V PCI clock outputs . These clocks synchronously stop in a low state whenPCI_STP# is brought to a logic low level. They synchronously resume runningwhen PCI_STP# is brought to a logic high state.25, 2648M(0,1) VDD 3.3V Fixed 48 MHz clock outputs36VCH_CLK VDD 3.3V selectable 66.6 MHz or 48 MHz clock output to VCH . Spread spectrum applies only when 66.6 MHz is selected. Select via SMBUS, byte 4 bit7.34CPU_STP#VDDCPU0 stop clock control input . Stops only CPU0 in a low state when asserted low. Using this pin to start and stop CPU0 clock insures synchronous (no short or long clocks) transitioning of this clock.11PCI_STP#VDDPCI stop clock control input . When this signal is at a logic low level (0), all PCI clocks (except PCI_F) stop at a logic low level. Using this pin to start and stop PCI clocks insures synchronous (no short or long clocks) transitioning of these clocks. This pin has no effect on the PCI_F clock.28, 29SEL(0,1)VDD3.3V LVTTL inputs for logic selection . These pins have Internal pull-ups, typically 250k (range 200k to 800k).30SDATA VDDSerial data input pin . Conforms to the SMBUS specification of a SlaveReceive/Transmit device. This pin is an input when receiving data. It is an open drain output when acknowledging or transmitting data. See 2-Wire SMBUS Control Interface on page 7.31SCLK VDD Serial clock input pin . Conforms to the SMBUS specification. See 2-Wire SMBUS Control Interface on page 7.32PD#VDD 3.3V LVTTL-compatible input . When held LOW, the device enters a power down mode. This pin has an Internal Pull-Up. See Power Management Functions on page 3.33TEST#VDD 3.3V LVTTL compatible input for selecting test mode . See Table 1.38DCLKVDDS3.3V SDRAM feedback clock output . See Table 1 for frequency selection. See Figure 4 for timing relationship.39, 40, 42, 43,45, 46SDRAM(0:5)VDDS 3.3V SDRAM clock outputs 54, 55IOAPIC(0,1)VDDI2.5V IOAPIC clock outputs. See Figure 4 for timing relationships.37, 44VDDS3.3V Power for SDRAM and DCLK clock output buffers 17VDDP 3.3V Power for PCI clock output buffers 53VDDI 2.5V Power for IOAPIC clock output buffers 51VDDC 2.5V Power for CPU clock output buffers 2, 10, 27, 35VDD 3.3V Common power supply 22AVDD Analog power 23AVSSAnalog ground 5, 6, 14, 21, 24,41, 47, 48, 56VSSCommon ground pinsPower Management FunctionsPower management on this device is controlled by the PD#,CPU_STP# and PCI_STP# pins. When PD# is high (default)the device is in normal running mode and all signals are active.The PD# signal is used to bring all clocks to a low level in an orderly fashion prior to power (all except AVDD) being removed from the part. When PD# is asserted (forced) low, the device transitions to a shutdown (power down) mode and all power supplies (3.3V and 2.5V except for AVDD) may then be removed. When PD# is sampled low by two consecutive rising edges of the CPU clock, then all affected clocks are stoppedin a low state on their next high-to-low transition. The REF and USB clocks are stopped in a low state as soon as possible.When in power down (and before power is removed), all outputs are synchronously stopped in a low state (see Figure 1), all PLLs are shut off, and the crystal oscillator is disabled. When the device is shutdown, the I ²C function is also disabled.At power-up, using the PD# select pin, all clocks are started in such a manner as to guarantee a glitch-free operation, no partial clock pulses.Notes:4.Extended frequencies are only available via SMBUS interface. They are accessable via SMBUS Byte 5 bits 0,1.5.48M(0,1) clocks are constant at 48 MHz and REF is constant at 14.31818 MHz for all table selections.6.Will be set to 133 MHz and boosted accordingly, when Byte3,Bit 0 is set to logic 1.Table 2.Expanded Frequency Selection (MHz)[4, 5, 6]TEST#ESEL ESEL SEL SEL CPU(0:2)SDRAM(0:5),DCLK3V66(0:2)PCI_F, PCI(1:6)Notes 1000066.7100[6]66.6330% extension (Default)0001100100[6]66.6330010133.3133.366.6330011133.3100[6]66.633010070105[6]70355% extension010*******[6]7035011014014070350111140105[6]7035100073.3110[6]73.336.610% extension1001110110[6]73.336.61010146.7146.773.336.61011146.7110[6]73.336.6110080120[6]804020% extension1101120120[6]8040111016016080401111160120[6]8040Power Management TimingWhen exiting the power-down mode, the application must supply power to the V DD pins a minimum of 200 ms before releasing the PD# pin high to insure that an orderly startup will occur and that the initial clocks that the device produces are full and correctly compliant with data sheet specified phase relationships.CPU_STP# TimingCPU_STP# is an input to the clock generator. CPU_STP# is asserted asynchronously by the external clock control logic and is internally synchronized to the external PCI_F output. All other clocks will continue to run while the CPU0 clock is disabled. The CPU0 is always stopped in a low state andstarted in such a manner as to guarantee that the high pulse width is a full pulse. Only one rising edge of PCI_F occurs after the clock control logic is switched for the CPU0 output to become enabled/disabled.PCI_STP# TimingPCI_STP# is an input to the clock generator and is made synchronous to the clock driver PCI_F output. It is used to turn off the PCI clocks for low power operation. PCI clocks are stopped in a low state and started such that a full high pulse width is guaranteed. ONLY one rising edge of PCI_F occurs after the clock control logic switched for the PCI outputs to become enabled/disabled.Note:7.All internal timing is referenced to the CPU clock.8.CPU_STP# signal is an input signal that is made synchronous to free-running PCI_F.9.Diagrams shown with respect to 133 MHz. Similar operation when CPU is 100 MHz.Table 3.Power Management CurrentConditionsMaximum 2.5V Current Consumption(V DDC = V DDI = 2.625)Maximum 3.3V Current Consumption(V DD = AV DD = V DDS = 3.465V)Power-down (PD# = LOW)≤ 1mA ≤ 1mA CPU = 66 MHz @ max loads 60 mA 295 mA CPU = 100 MHz @ max loads 75 mA 295 mA CPU = 133 MHz @ max loads90 mA295 mA0nsCPU 100 MHz3V66 66 MHzPCI 33 MHzIOAPIC 33 MHzPD#SDRAM 100 MHzREF 14.3 MHzFigure 1.Note:10.All the internal timing is referenced to the CPU clock11.PCI_STP# signal is an input signal that must be made synchronous to PCI_F output.12.All other clocks continue to run undisturbed.13.PD# is understood to in a high state.14.Diagrams shown with respect to 133 MHz. Similar operation when CPU is 100 MHzCPU(1,2)PCI_F CPU_STP#CPU0PCI_STP#(High)PWR_DWN#(High)PCI_STP#PCI_FClock PhaseTable 4.Group Timing Relationships and TolerancesCPU = 66.6 MHz, SDRAM = 100 MHzOffset (ns)Tolerance (ps)ConditionsCPU to SDRAM/DCLK 2.5500CPU to 3V667.5500180 degrees phase shift SDRAM/DCLK to 3V660500When rising edges line up 3V66 to PCI 1.5–3.55003V66 leadsPCI to IOAPIC 0100048M (0,1)Async N/ACPU = 100 MHz, SDRAM = 100 MHz Offset (ns)Tolerance (ps)ConditionsCPU to SDRAM/DCLK 5500180 degrees phase shift CPU to 3V665500CPU leadsSDRAM/DCLK to 3V660500When rising edges line up 3V66 to PCI 1.5–3.55003V66 leadsPCI to IOAPIC 0100048M (0,1)Async N/ACPU = 133.3 MHz, SDRAM = 100 MHzOffset(ns)Tolerance(ps)ConditionsCPU to SDRAM/DCLK 0500When rising edges line up CPU to 3V660500SDRAM/DCLK to 3V660500When rising edges line up 3V66 to PCI 1.5–3.55003V66 leadsPCI to IOAPIC 0100048M (0,1)AsyncN/AFigure 4.2-Wire SMBUS Control InterfaceThe 2-wire control interface implements a read/write slave only interface according to SMBus specification. (See Figure 5below). The device can be read back by using standard SMBUS command bytes. Sub addressing is not supported,thus all preceding bytes must be sent in order to change one of the control bytes. The 2-wire control interface allows each clock output to be individually enabled or disabled. 100 Kbits/s (standard mode) data transfer is supported.During normal data transfer, the SDATA signal only changes when the SCLK signal is low, and is stable when SCLK is high.There are two exceptions to this. A high to low transition on SDATA while SCLK is high is used to indicate the start of a data transfer cycle. A low to high transition on SDATA while SCLKis high indicates the end of a data transfer cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer cycle is an 8-bit address. The LSB address Byte = 0 in write mode.The device will respond to transfers of 10 bytes (max) of data.The device will generate an acknowledge (low) signal on SDATA following reception of each byte. Data is transferred MSB first at a max rate of 100kbits/s. This device will also respond to a D3 address which sets it in a read mode. It will not respond to any other control interface conditions, and previously set control registers are retained.When a clock driver is placed in power down mode, the SMBUS signals SDATA and SCLK must be tri-stated. In power down, the device retains all SMBUS programming information.CPU = 133.3MHz, SDRAM = 133.3MHzOffset(ns)Tolerance(ps)ConditionsCPU to SDRAM/DCLK 3.75500180 degrees phase shiftCPU to 3V660500SDRAM/DCLK to 3V66 3.755003V66 to PCI 1.5–3.55003V66 leadsPCI to IOAPIC 0100048M (0,1)AsyncN/ATable 4.Group Timing Relationships and Tolerances (continued)CPU = 66.6 MHz, SDRAM = 100 MHzFigure 5.SMBus Communications WaveformsSerial Control RegistersFollowing the acknowledge of the Address Byte, two additional bytes must be sent:1) “Command Code “byte2) “Byte Count” byte. Although the data (bits) in these two bytes are considered “don’t care,” they must be sent and will be acknowledged. After the Command Code and the Byte Count have been acknowl-edged, the sequence (Byte 0, Byte 1, and Byte 2) described below will be valid and acknowledged.Byte 0: CPU Clock Register (1 = Enable, 0 = Disable)Bit@Pup[15]Pin#[16]Description7136VCH_CLK6149CPU25150CPU14152CPU030–Spread Spectrum ( 1 = enabled)212648M1(DOT)112548M0(USB)00–Reserved. Set to 0Byte 1: SDRAM Clock Register (1 = Enable, 0 = Disable)Bit@Pup[15]Pin#[16]Description70–Reserved. Set to 060–Reserved. Set to 05139SDRAM54140SDRAM43142SDRAM32143SDRAM21145SDRAM10146SDRAM0Byte 2: 3C66 Clock Register (1 = Enable, 0 = Disable)Bit@Pup[15]Pin#[16]Description7193V66_2 (AGP)6183V66_15173V66_040–Reserved. Set to 030–Reserved. Set to 020–Reserved. Set to 010–Reserved. Set to 000–Reserved. Set to 0Byte 3: PCI Register (1 = Enable, 0 = Disable)Bit@Pup[17]Pin#[18]Description70–Reserved. Set to 06120PCI65119PCI54118PCI43116PCI32115PCI21113PCI100–SDRAM 133- MHz Mode Enable. Default is disabled = “0,” enabled = “1”Notes:15.The @Pup column gives the default state at power-up.16.The Pin# column lists the relevant pin number where applicable.Spread Spectrum Clock Generation (SSCG)Spread Spectrum is a modulation technique applied here for maximum efficiency in minimizing EMI radiation generated by repetitive digital signals, mainly clocks. A clock accumulates EM energy at the center frequency it is generating. Spread Spectrum distributes this energy over a small frequency bandwidth therefore distributing an even amount of energy over a wider spectrum. This technique is achieved by modulating the clock either down or around the center (see Figure 7 below) of its resting frequency by a certain percentage (which also determines the energy distribution bandwidth). In this device, Spread Spectrum is enabled by setting SMBUS Byte0,Bit3 = 1. The default of the device atpower up keeps the Spread Spectrum disabled, it is therefore,important to have SMBUS accessibility to turn-on the SpreadSpectrum function. Once the Spread Spectrum is enabled, the spread bandwidth option is selected by SST(0:2) in SMBUS Byte 5, bits 5, 6, and 7 . See Table 7 below.In Down Spread mode the center frequency is shifted down from its rested (non-spread) value by ½ of the total spread %(e.g., assuming the center frequency is 100 MHz in non-spread mode; when down spread of –0.5% is enabled,the center frequency shifts to 99.75 MHz.). In Center Spread Mode, the center frequency remains the same as in non-spread mode.Notes:17.The @Pup column gives the default state at power-up18.The Pin# column lists the relevant pin number where applicable.Byte 4: VCH Clock Register (1 = Enable, 0 = Disable)Bit @Pup [17]Pin#[18]Description7036VCH_CLK SSC Mode Enable “0” = 48 MHZ (non-SSCG)“1” = 66.6 MHz (SSCG applicable when Byte 0,Bit3 = 1)60–Reserved. Set to 050–Reserved. Set to 040–Reserved. Set to 030–Reserved. Set to 020–Reserved. Set to 01–Reserved. Set to 000–Reserved. Set to 0Byte 5: SSCG Control Register (1 = Enable, 0 = Disable)Bit @Pup [17]Pin#[18]Description70–Spread Mode (0 = down, 1 = center)60–Selects spread bandwidth. See Table 5.50–Selects spread bandwidth. See Table 5.40–Reserved. Set to 030–Reserved. Set to 020–Reserved. Set to 010–ESEL1 Expanded Freq. Selection MSB, See Table 2.0–ESEL0 Expanded Freq. Selection LSB, See Table 2.Figure 6.SMBUS Test Circuitry [19]Spread Spectrum Selection TablesNote:19.Buffer is 7407 with V CC @ 5.0V.DownspreadCenter SpreadFigure 7.Spread SpectrumTable 5.(I ²C BYTE 5 Bit 7=0), Down SpreadI ²C Byte 5Bit Spread %6500–0.501–0.710–1.011–1.5Table 6.(I ²C BYTE 5 Bit 7=0), Center SpreadI ²C Byte 5BitSpread %6500±0.2501±0.3510±0.511±0.75Maximum RatingsMaximum Input Voltage Relative to V SS :............ V SS – 0.3V Maximum Input Voltage Relative to V DD :.............V DD + 0.3V Storage Temperature:................................–65°C to + 150°C Operating Temperature:....................................0°C to +85°C Maximum ESD Protection..............................................2 KV Maximum Power Supply:................................................5.5VThis device contains circuitry that protects the inputs against damage due to high static voltages or electric field; however,precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit.For proper operation, V IN and V OUT should be constrained to the range:V SS < (V IN or V OUT ) < V DD .Unused inputs must always be tied to an appropriate logic voltage level (either V SS or V DD ).Notes:20.All outputs loaded per Table 7.21.Applicable to input signals : SEL(0:1), PD# (pull-up).22.Applicable to SDATA and SCLK.23.Internal pull-up and pull-down resistors affect this current.24.See Applications data that is presented later in this datasheet on crystal interfacing.DC Parameters V DD = V DDS = 3.3V ± 5%, V DDC = V DDI = 2.5V ± 5%, T A = 0°C to +70°C [20]Parameter DescriptionConditions Min.Typ.Max.Units VIL1Input Low Voltage Note 211.0V VIH1Input High Voltage 2.0V VIL2Input Low Voltage Note 221.0V VIH2Input High Voltage2.2V IIL1Input Low Current (@V IL = V SS )For internal pull-up resistors [23]–20µA IIH1Input High Current (@V IH =V DD )20µA Ioz Three-state leakage Current 10µA Idd3.3V Dynamic Supply Current295mA Idd2.5VDynamic Supply CurrentCPU @ 66 MHz 60mA CPU @ 100 MHz 75mA CPU @ 133 MHz90mA Ipd3.3V Power Down Supply Current PD# = “0”1mA Ipd2.5V Power Down Supply Current PD# = “0”1mA Cin Input pin capacitance 5pF Cout Output pin capacitance 6pF Lpin Pin inductance 7nH Cxtal Crystal pin capacitance Measured from Pin to Ground [24]343638pF V BIAS Crystal DC Bias Voltage 0.3V DDV DD /20.7V DD V TxsCrystal Startup timeFrom stable 3.3V power supply.40µsTable 7.Maximum Output LoadClock NameMax Load (in pF)CPU(0:2), IOAPIC(0:1), REF, 48M0 (USB), VCH_CLK 20PCI(0:6), SDRAM(0:5), DCLK, 3V66(0:2)3048M1 (DOT)15AC ParametersParameter Description 133 MHz Host100 MHz Host66 MHz HostUnits Min.Max.Min.Max.Min.Max.CPUTPeriod CPU(0:2) period[25,26]7.58.010.010.515.015.5ns THIGH CPU(0:2) high time[30] 1.87 3.0 5.2ns TLOW CPU(0:2) low time[31] 1.67 2.8 5.0ns Tr / Tf CPU(0:2) rise and fall times[27]0.4 1.60.4 1.60.4 1.6ns TSKEW CPU0 to any CPU Skew[26,29]150150150ps TCCJ CPU(0:2) Cycle to Cycle Jitter[26,29]250250250ps SDRAMTPeriod SDRAM(0:5) 100 MHz and DCLKperiod[25,26]10.010.510.010.510.010.5ns THIGH SDRAM(0:5) 100 MHz and DCLK hightime[30]3.0 3.0 3.0ns TLOW SDRAM(0:5) 100 MHz and DCLK lowtime[31]2.8 2.8 2.8ns Tr / Tf SDRAM(0:5) 100 MHz and DCLK rise andfall times[27]0.4 1.60.4 1.60.4 1.6ns TSKEW SDRAM(0:5) 100 MHzand DCLKSkew[26,29]250250250ps TCCJ SDRAM(0:5) 100 MHz, DCLK Cycle toCycle Jitter[26,29]250250250ps IOAPICTPeriod IOAPIC(0,1) period[25,26]30.030.030.0ns THIGH IOAPIC(0,1) high time[30]12.012.012.0ns TLOW IOAPIC(0,1) low time[31]12.012.0N/S12.0ns Tr / Tf IOAPIC(0,1) rise and fall times[27]0.4 1.60.4 1.60.4 1.6ns TSKEW IOAPIC(0,1) Skew[26,29]250250250ps TCCJ IOAPIC(0,1) Cycle to Cycle Jitter[26,29]500500500ps 3V66TPeriod3V66-(0:2) period[25,26]15.016.015.016.015.016.0ns THIGH3V66-(0:2) high time[30] 5.25 5.25 5.25ns TLOW3V66-(0:2) low time[31] 5.05 5.05 5.05ns Tr / Tf3V66-(0:2) rise and fall times[28]0.5 2.00.5 2.00.5 2.0ns TSKEW(Any 3V66) to (any 3V66) Skew[26,29]175175175ps TCCJ3V66-(0:2) Cycle to Cycle Jitter[26,29]500500500ps PCI_FTPeriod PCI(_F,1:6) period[25,26]30.030.030.0ns THIGH PCI(_F, 1:6) high time[30]12.012.012.0ns Notes:25.This parameter is measured as an average over 1us duration, with a crystal center frequency of 14.31818 MHz.26.All outputs loaded per Table6. Probes are placed on the pins and taken at 1.5V levels for 3.3V signals and at 1.25V for 2.5V signals (see Figure8).27.Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and between 0.4V and 2.0V for 2.5V signals (seeFigure8).28.Measured from when both SEL1 and SEL0 are switched to high (enable).29.This measurement is applicable with Spread ON or Spread OFF.30.Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals and at 2.0V for 2.5V signals (see Figure8).31.Probes are placed on the pins, and measurements are acquired at 0.4V.Notes:32.The time specified is measured from when all V DD ’s reach their respective supply rail (3.3V and 2.5V) till the frequency output is stable and operating within thespecifications.33.Measured from when both SEL1 and SEL0 are switched to low (disable).34.Device designed for Typical Duty Cycle of 50%.TLOW PCI(_F, 1:6) low time [31]12.012.012.0ns Tr / Tf PCI(_F, 1:6) rise and fall times [27]0.52.00.52.00.52.0ns TSKEW (Any PCI) to (Any PCI) Skew [26,29]500500500ps TCCJPCI(_F, 1:6) Cycle to Cycle Jitter [26,29]500500500ps DOT and USB TPeriod DOT and USB (48M[0,1]) period(conforms to +167 ppm max) [25,26]20.829920.833320.829920.833320.82920.833ns Tr / Tf DOT and USB rise and fall times [27] 1.04.0 1.04.0 1.04.0ns TCCJ DOT and USB Cycle to Cycle Jitter [26,29]500500500ps TCCJ VCH_CLK Cycle to Cycle Jitter [26]250250250ps REF TPeriod REF period [25,26]69.841371.069.841371.069.841371.0ns Tr / Tf REF rise and fall times [27] 1.04.0 1.0 4.0 1.04.0ns TCCJREF Cycle to Cycle Jitter [26]100010001000ps tpZL, tpZH Output enable delay (all outputs)[28] 1.010.0 1.010.0 1.010.0ns tpLZ, tpHZ Output disable delay (all outputs)[33] 1.010.0 1.010.0 1.010.0ns tstable All clock stabilization from power-up [32]333ms TdutyDuty cycle for all outputs [34]455545554555%AC Parameters (continued)Parameter Description133 MHz Host 100 MHz Host 66 MHz Host Units Min.Max.Min.Max.Min.Max.Output Buffer CharacteristicsTable 8.CPU, IOAPICParameter Description Conditions Min.Typ.Max.Units IOH1Pull-up Current Vout =VDDC - 0.5V (or VDDI –0.5V)–15–31–51mA IOH2Pull-up Current Vout = 1.2V–26–58–101mA IOL1Pull-down Current Vout = 0.4V122440mA IOL2Pull-down Current Vout = 1.2V275693mA Z0Output Impedance13.545ΩTable 9.PCI, 3V66, VCHParameter Description Conditions Min.Typ.Max.Units IOH1Pull-up Current Vout =VDD – 0.5V–20–25–33mA IOH2Pull-up Current Vout = 1. 5V–30–54–184mA IOL1Pull-down Current Vout = 0.4V9.41838mA IOL2Pull-down Current Vout = 1.5V2855148mA Z0Output Impedance1255ΩTable 10.48M0(USB), 481(DOT), REFParameter Description Conditions Min.Typ.Max.Units IOH1Pull-up Current Vout =VDD – 0.5V–12–16–28mA IOH2Pull-up Current Vout = 1. 5V–27–43–92mA IOL1Pull-down Current Vout = 0.4V91327mA IOL2Pull-down Current Vout = 1.5V263979mA Z0Output Impedance2060ΩTable 11.SDRAM (V DD = V DDS = 3.3V ± 5%, V DDC = V DDI = 2.5V ± 5%, T A = 0°C to 70°C)Parameter Description Conditions Min.Typ.Max.Units IOH1Pull-up Current Vout =VDD – 0.5V–28–40–60mA IOH2Pull-up Current Vout = 1. 5V–67–107–184mA IOL1Pull-down Current Vout = 0.4V233453mA IOL2Pull-down Current Vout = 1.5V6498159mAZ0Output Impedance1024ΩTest Measurement ConditionTo obtain the maximum accuracy, the total circuit loading capacitance should be equal to C XTAL. This loading capaci-tance is the effective capacitance across the crystal pins and includes the clock generating device pin capacitance (C FTG ),any circuit trace capacitance (C PCB ) and any onboard discrete load capacitance (C DISC ).The following formula and schematic illustrates the application of the loading specification of a crystal (C XTAL ) for a design.As an example and using a formula for this datasheet ’s device,a design that has no disrete loading capacitors (C DISC ) and each of the crystal to device PCB traces has a capacitance (C PCB ) to ground of 4pF (typical value) would calculate as:Where:C XTAL = the load rating of the crystal.C XOUTFTG ....= the clock generators XIN pin effective device internal capacitance to ground.C XOUTFTG = the clock generators XOUT pin effective device internal capacitance to ground.C XINPCB = the effective capacitance to ground of the crystal to device PCB trace.C XOUTPCB = the effective capacitance to ground of the crystal to device PCB trace.C XINDISC = any discrete capacitance that is placed between the X IN pin and ground.C XOUTDISC = any discrete capacitance that is placed between the X OUT pin and ground.Notes:35.For best performance and accurate frequencies from this device, it is recommended but not mandatory that the chosen crystal meets or exceeds thesespecifications.rger values may cause this device to to exhibit oscillator startup problems.Table 12.Suggested Oscillator Crystal Parameters Parameter DescriptionConditionsMin.Typ.Max.Units F o Frequency 14.1714.3181814.46MHz T C ToleranceNote 35±100PPM T S Frequency Stability Stability (T A – 10 to +60C)[35]±100PPMOperating Mode Parallel Resonant [35]C XTAL Load CapacitanceThe crystal ’s rated load [35]20pF R ESREffective Series Resistance (ESR)Note 3640OhmsFigure 8.C L = (C XINPCB + C XINFTG + C XINDISC ) X (C XOUTPCB + C XOUTFTG + C XOUTDISC )Therefore, to obtain output frequencies that are as close to this datasheets specified values as possible, in this designexample, you should specify a parallel cut crystal that is designed to work into a load of 20pF.Package DiagramsFigure 9.Ordering InformationPart NumberPackage TypeProduct Flow IMIC9835CY 56-pin Shrunk Small Outlie package (SSOP)Commercial, 0° to 70°C IMIC9835CYT 56-pin Shrunk Small Outlie package (SSOP)–Tape and Reel Commercial, 0° to 70°C IMIC9835CT 56-pin Thin Shrunk Small Outlie package (TSSOP)Commercial, 0° to 70°CIMIC9835CTT56-pin Thin Shrunk Small Outlie package (TSSOP)–Tape and Reel Commercial, 0° to 70°C51-85060-B56-lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56Package Diagrams (continued)I 2C Patent Rights to use these components in an I 2C system, provided that the system conforms to the I 2C Standard Specification as defined by Philips.Intel is a registered trademark of Intel Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.56-lead Shrunk Small Outline Package O56Document Title: C9835 Low-EMI Clock Generator for Intel® Mobile 133-MHz/3 SO-DIMM Chipset Systems Document Number: 38-07373REV.ECN NO.IssueDateOrig. ofChange Description of Change**11355605/28/02DMG New Data Sheet (converted from IMI format)。
FPGA可编程逻辑器件芯片XC3S2000-5CPG132C中文规格书
Section XII: I/O Peripheral ControllersChapter 69: I2C Controller7.Fill the data into the FIFO. Write the data to the Data register based on the count obtained instep 5.8.Wait for the data to be sent. Check that the ISR [COMP] bit is set.a.If writing further data, repeat steps 5, 6, and 8.b.If there is no further data, set Control [HOLD] bit = 0.9.Wait for the completion of transfer. Check that the ISR [COMP] register bit is set = 1.Slave Monitor ModeThe slave monitor mode helps to monitor when the slave is in the busy state. The slave readyinterrupt occurs only when the slave is not busy. This process can only be performed in master mode.1.Select slave monitor mode and clear the FIFOs. Write 60h to the Control register.2.Clear the interrupts. Read and write back the read value to the ISR status register.3.Enable the interrupts. Set the IER [SLV_RDY] bit = 1.4.Set the slave monitor delay. Write Fh to the Slave_Mon_Pause register.5.Write the slave address. Write the address to the Address register.6.Wait for the slave to be ready. Poll on ISR [SLV_RDY] status register bit until = 1.Programming SequencesThe flow diagram for the I2C controller programming sequence is shown in the following twofigures.Figure 86: I2C Master Interrupt Example FlowchartX23505-110619Figure 87: I2C Slave Polled Example FlowchartX23506-110619Software RoutinesResetTable 151: I2C ResetTask Register Register Field Bits Operation Abort StartIMR, 0x20All9:0Read operation Save interrupt maskregisterDisable all interrupts IDR, 0x28All9:0Write 2FFh。
FPGA可编程逻辑器件芯片XC3S1000-5FGG320C中文规格书
Table 328: Transmitter Configuration Comparison (cont'd)Feature Legacy XGEMAC10/25G High Speed Ethernet IP TX Preserve Preamble Enable mac_tx_configuration_vector[7]ctl_tx_custom_preamble_enable enablesthe use of a custom preamble.Tx_preamblein presents the custompreamble and rx_preambleout has thepreamble field from the received frame. TX Flow control Enable mac_tx_configuration_vector[5]ctl_tx_pause_enable[8:0]TX Jumbo Frame Enable mac_tx_configuration_vector[4]Not requiredTX In-band FCS enable mac_tx_configuration_vector[3]ctl_tx_fcs_ins_enableTX VLAN enable mac_tx_configuration_vector[2]Not requiredTX Enable mac_tx_configuration_vector[1]ctl_tx_enableTX Reset mac_tx_configuration_vector[0]tx_resetReceiver ConfigurationThe legacy XGEMAC used the rx_configuration_vector[95:0] for all RX configuration whereas the 10G/25G High Speed Ethernet IP core deploys various signals for the same purpose. The following table draws a comparison.Table 329: Receiver Configuration ComparisonFeature Legacy XGEMAC10/25G High Speed Ethernet IPRX Priority 7-0 Flow controlenablerx_configuration_vector[95:88]ctl_rx_pause_enable[8:0]Priority Flow Control Enable rx_configuration_vector[80]RX Pause Frame SA rx_configuration_vector[79:32]ctl_rx_pause_sa[47:0]RX MTU size rx_configuration_vector[30:16]Set using ctl_rx_max_packet_len andctl_rx_min_packet_len signals.RX MTU Enable rx_configuration_vector[14]Not required.Reconciliation Sublayer Fault Inhibit rx_configuration_vector[10]Design user logic to set ctl_tx_send_idle when RFI isreceived.Control Frame Length checkDisablerx_configuration_vector[9]Not availableRX Length/Type Error disable rx_configuration_vector[8]The length/type error cannot be disabled on the10/25G High Speed Ethernet IP core.RX preserve preamble enable rx_configuration_vector[7]ctl_rx_custom_preamble_enableRX Flow control enable rx_configuration_vector[5]ctl_rx_pause_enable[8:0]RX Jumbo Frame Enable rx_configuration_vector[4]Set using the ctl_rx_max_packet_len signal.RX in-band FCS enable rx_configuration_vector[3]ctl_rx_delete_fcsRX VLAN enable rx_configuration_vector[2]Up to the user logic to implement this functionality. RX enable rx_configuration_vector[1]ctl_rx_enableRX reset rx_configuration_vector[0]rx_resetTable 337: Pause Processing (cont'd)Address(Hex)Register Register Address (Hex)0x49C Priority 7 QuantaRegisterCONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG4 [31:16]0x00640x4A0Legacy Pause RefreshRegisterDoes not support Legacy PFCMDIO Control RegistersThe 10G/25G High Speed Ethernet IP does not provide an MDIO station master and thus does not have any of the MDIO control registers.Interrupt RegistersTypically interrupts are generated after an MDIO operation to indicate completion; because there is no MDIO master there are no interrupt registers.PCS/PMA MDIO register mapAgain, because there is no MDIO interface provided, there are no MDIO registers for the PCS/PMA interface.AXI4-Stream InterfaceThe 10G/25G High Speed Ethernet IP Subsystem provides both 64-bit and 32-bit AXI4-Stream interfaces for the datapath as does the Legacy 10G Ethernet IP Subsystem. Note the following difference in the use of tuser bits on the RX interface. The table below compares the definitions of the tuser signals on both TX and RX.Table 338: Comparison of the Definitions of the tuser Signals in Both TX and RX Signal Legacy XGEMAC10/25G High Speed Ethernet IPRX AXI4-Stream tuser m_axis_rx_tuserAXI4-Stream User Sideband interface.0 indicates a bad packet has beenreceived.1 indicates a good packet has beenreceived rx_axis_tuserAXI4-Stream User Sideband interface.1 indicates a bad packet has been received.0 indicates a good packet has beenreceived.TX AXI4-Stream tuser s_axis_tx_tuserAXI4-Stream user signal used to indicateexplicit underrun tx_axis_tuserAXI4-Stream User Sideband interface.1 indicates a bad packet has been received.0 indicates a good packet has beenreceived.Appendix A: Upgrading •Redesigned auto-negotiation and Link Training features with reduced utilization; all changes are transparent to the userFeature Updates for 25 Gb/s OperationRedesigned auto-negotiation and Link Training features with reduced utilization; all changes are transparent to the user.PortsPorts Added•stat_rx_status•axi_ctl_core_mode_switch_*•rx_mii_clk•tx_mii_clk•clkPorts Deletedtx_ptp_pcslane_outPort Changes•Added 32-bits to tx_axis_tdata_* and rx_axis_tdata_*•Updated bus sizes for many signals•Updated bus sizes of tx_axis_tdata_* and rx_axis_tdata_*.•Added 32/64-bit to tx_clk_out_* and tx_mii_out_*.•Added 32 bits to rx_serdes_data_out_* and tx_serdes_data_in_*.•Replaced "Ethernet MAC+PCS/PMA" with “Ethernet MAC+PCS/PMA-32/64-bit” in most of the signals in Core xci T op Level Port List.•Inserted "or Ethernet MAC" in most of the signals in Core xci T op Level Port List.•Updated descriptions of the following:○rx_axis_tdata[63 or 31:0]○rx_axis_tkeep[7 or 3:0]○ctl_rx_ignore_fcs○ctl_rx_max_packet_len[14:0]。
金士顿khx13c9b1rk2 4 4gb ddr3-1333 内存模块说明书
DESCRIPTIONKingston's KHX13C9B1RK2/4 is a kit of two 256M x 64-bit (2GB) DDR3-1333 CL9 SDRAM (Synchronous DRAM) 1Rx8memory modules, based on eight 256M x 8-bit DDR3 FBGA components per module. Total kit capacity is 4GB. The SPDs are programmed to JEDEC standard latency DDR3-1333 timing of 9-9-9 at 1.5V. Each 240-pin DIMM uses gold contact fingers and requires +1.5V. The JEDEC standard electrical and mechanical specifications are as follows:SPECIFICATIONSCL(IDD)9 cycles Row Cycle Time (tRCmin)49.5ns (min.)Refresh to Active/Refresh 160ns (min.)Command Time (tRFCmin)Row Active Time (tRASmin)36ns (min.)Maximum Operating Power 2.160 W* (per module)UL Rating94 V - 0Operating Temperature 0o C to 85o C Storage Temperature-55o C to +100o C*Power will vary depending on the SDRAM used.FEATURES •JEDEC standard 1.5V (1.425V ~ 1.575V) Power Supply •VDDQ = 1.5V (1.425V ~ 1.575V)•667MHz fCK for 1333Mb/sec/pin •8 independent internal bank•Programmable CAS Latency: 9, 8, 7, 6•Posted CAS•Programmable Additive Latency: 0, CL - 2, or CL - 1 clock •Programmable CAS Write Latency(CWL) = 7 (DDR3-1333)•8-bit pre-fetch•Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or write [either on the fly using A12 or MRS]•Bi-directional Differential Data Strobe•Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)•On Die Termination using ODT pin•Average Refresh Period 7.8us at lower than TCASE 85°C,3.9us at 85°C < TCASE < 95°C •Asynchronous Reset•PCB : Height 1.180” (30.00mm), single sided componentKHX13C9B1RK2/44GB (2GB 256M x 64-Bit x 2 pcs.)DDR3-1333 CL9 240-Pin DIMM KitContinued >>MODULE WITH HEAT SPREADERAll Kingston products are tested to meet our published specifications. Some motherboards or system configurations may not operate at the published HyperX memory speeds and timing settings. Kingston does not recommend that any user attempt to run their computers faster than the published speed. Overclocking or modifying your system timing may result in damage to computer components.FOR MORE INFORMATION, GO TO 18.8015.8011.008.000.000.054.7。
FPGA可编程逻辑器件芯片XC3S1000-5FTG256C中文规格书
The high-speed clock multiplexer controlled by TX_PROGCLK_SEL is set based on the application requirements:•00: The post TX phase interpolator (PI) clock path can be used to generate a parallel clock with a certain ppm offset created by the TX PI. In this use case, one transceiver PLL is shared for the datapath and clock generation path. The clock signal is interrupted if the channel or the source PLL is being reset.•01: The pre TX PI clock path can be used to generate a system clock to support applications where minimal or fixed latency is needed. In this use case, one transceiver PLL is shared for the datapath and clock generation path. The clock signal is interrupted only if the source PLL is being reset.•10: In applications where the LCPLL clock might be interrupted during reconfiguration, the bypass clock path provides the flexibility to use the RPLL to generate a stable parallel clock for the interconnect logic.TX DAPI and TX DAPI Bypass DividersThe TX delay align and phase interpolator (TX DAPI) shown in TX Fabric Clock Output Control can either be enabled or bypassed to provide the CH*_TXOUTCLK.TX_DA_BYP determines the clock path and is set based on application requirements:•0: The TX DAPI clock path is used to generate the CH*_TXOUTCLK. In this use case, the TX DAPI has a built-in divide-by-2 that is always present. The divider values for TX DA DIV should be left to the default values from the Wizard example design.•1: The clock path where TX DAPI is bypassed generates the CH*_TXOUTCLK. In this use case, the TX DAPI BYPASS DIV divider value should be left to the default values from the Wizard example design.Ports and AttributesThe following table defines the ports required for TX fabric clock output control.Table 62: TX Fabric Clock Output Control PortsPort Direction Clock Domain DescriptionCH[0/1/2/3]_TXOUTCLK Output CLOCK TXOUTCLK is the recommended clockoutput to the interconnect logic.CH[0/1/2/3]_TXPROGDIVRESET Input ASYNC This active-High port resets the dividersas well as theCH*_TXPROGDIVRESETDONE indicator. Areset must be performed whenever theinput clock source is interrupted.CH[0/1/2/3]_TXPROGDIVRESETDONE Output ASYNC When the input clock is stable and reset isperformed, this active-High signalindicates the reset is completed and theoutput clock is stable.Table 62: TX Fabric Clock Output Control Ports (cont'd)Port Direction Clock Domain DescriptionCH[0/1/2/3]_TXRATE[7:0]Input TXUSRCLK This port is used to perform rate changeon the Transceiver TX.The Wizard will preconfigure a list ofdesired line rates, and this port will beused to dynamically adjust the runningline rate based on the preconfigured list.Set this port to the matchingpreconfigured line rate option value toobtained the proper line rate.The following table defines the attributes required for TX fabric clock output control.。
七彩虹主板说明书C.D51K V20╱C.D41T V20 (Atom D510╱D410)
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第一章简介
感谢您购买七彩虹系列主板，该系列主板提供了非常优秀的性能和品质保 证。
1-1 主板特色
C.D51K V20/C.D41T V20 主板采用最新 Intel D510+NM10/Intel D410+NM10 芯 片组设计，集成 Atom D510/D410 处理器,支持 DDR2 667/800 类型模块内 存, 集成 GMA 3150 显示核心。 该板板载 6 声道声卡,集成千兆网卡(C.D41T V20 主板采用百兆网卡),该板提 供 1 个 PCI-Express x16 插槽、2 个 PCI 插槽、2 个 SATA2 接口、8 个高速 USB2.0 接口(2 个 USB 连接头可扩展至 4 个 USB 接口) , 1 个串行 COM 接口 和 VGA 接口, 1 个并行 LPT 打印机接口, 板载红外线 IR 连接头,板载 SPDIF 连接头,扩展模式丰富, 扩展性能强劲。 Atom D510 采用 45nm 工艺制造，双核心四线程，主频 1.66GHz，前端总 线 667MHz，一级缓存 2×24KB+2×32KB，二级缓存 2×512KB，支持 EM64T 技术。 Atom D410 则是单核心双线程版本，主频也是 1.66GHz。 注意：Atom D510/D410 内均集成了图形核心 GMA 3150，源于上代低端整 合芯片组 G31 的 GMA 3100，相比 945G 系列之中的 GMA 950 有所提升 英特尔® 凌动™ 处理器继续了在英特尔行业领先 45 纳米高 k 金属栅 极技术方面的创新。英特尔凌动处理器专门面向价格经济的上网本和上网 机，可支持基本的计算和互联网操作。 采用英特尔凌动处理器的上网本和上网机外形小巧，价格经济，并且非常 方便消费者使用。上网本和上网机可提供出色的互联网体验，是学习与娱
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Topr=25℃
UNITS CIRCUITμA1来自μA1μA
1
V
-
VDD-0.3
-
VDD
V
2
VDD-0.3
-
VDD
V
3
0.6
- VDD-1.2 V
3
VSS
-
0.25
V
3
- 0.1
-
0.1
μA
1
- 0.1
-
0.1
μA
1
●DC/DC Converter (2.2V product)
PARAMETER
SYMBOL
The XC9510 series consists of a step-down DC/DC converter and a high-speed LDO regulator connected in series with the DC/DC converter's output. A voltage detector is also built-in. A highly efficient, low noise output is possible since the regulator is stepped-down further from the DC/DC output. The DC/DC converter block incorporates a P-channel driver transistor and a synchronous N-channel switching transistor. With an external coil, diode and two capacitors, the XC9510 can deliver output currents up to 800mA at efficiencies over 90%. The XC9510 is designed for use with small ceramic capacitors. A choice of three switching frequencies are available, 300 kHz, 600 kHz, and 1.2 MHz. Output voltage settings for the DC/DC is set-up internally in 100mV steps within the range of 1.6V to 4.0V(±2.0%) and for the VR are set-up internally within the range of 0.9V to 4.0V (±2.0%). For the VD, the range is of 0.9V to 5.0V (±2.0%). The soft start time of the series is internally set to 5ms. With the built-in U.V.L.O. (Under Voltage Lock Out) function, the internal P-channel driver transistor is forced OFF when input voltage becomes 1.4 V or lower. The operational states of the DC/DC and the regulator blocks can be changed by inputting three kinds of voltage level via the CE/MODE pin. The functions of the MODE pin can be selected via the external control pin to switch the DC/DC control mode and the disable pin to shut down the regulator block.
CE/MODE Pin Voltage
Power Dissipation
SOP-8
Operating Temperature Range
Storage Temperature Range (*) When PC board mounted.
SYMBOL VDD DCOUT VROUT IROUT VDOUT IVD Lx ILx
(VOUT=2.8V)
High Ripple Rejection : 60dB @1kHz (VOUT=2.8V)
■TYPICAL APPLICATION CIRCUIT
■TYPICAL PERFORMANCE CHARACTERISTICS
1/36
元器件交易网
XC9510 Series
DC/DC: OFF VR: OFF VD: ON
VD SENSE PIN
VDD DCOUT VROUT
VDD DCOUT VROUT
VDD DCOUT VROUT
2/36
元器件交易网
■BLOCK DIAGRAM
XC9510
Series
* Diodes shown in the above circuit are protective diodes.
SYMBOL IDD1 IDD2 ISTB VIN
VCEH
CONDITIONS VIN=CE=DCOUT=5.0V VIN=CE=5.0V, DCOUT=0V VIN=6.5V, CE=0V
VCEH
VCEM VCEL ICEH ICEL
MIN. -
2.4
TYP. 250 300 3.0
-
MAX. 310 360 7.0 6.0
VD Output Analog Ground
VR Output DC/DC Output
Switch
■PRODUCT CLASSIFICATION
●Ordering Information
XC9510①②③④⑤⑥ The input for the voltage regulator block comes from the DC/DC.
Package
: SOP-8
<DC/DC Converter Block>
Output Voltage Range : 1.6V ~ 4.0V (Accuracy ±2%)
Output Current
: 800mA,
Controls
: PWM or PWM/PFM Selectable
Oscillation Frequency : 300kHz, 600kHz, 1.2MHz
DC/DC: ON VR: OFF VD: ON
PFM / PWM Automatic Switch
CE=”VCEM” LEVEL
-
DC/DC: ON VR: ON VD: ON
PWM Control
CE=”VCEL” LEVEL
DC/DC: OFF VR: OFF VD: ON
DC/DC: OFF VR: OFF VD: ON
DESIGNATOR
DESCRIPTION
SYMBOL
DESCRIPTION
① ②③
④ ⑤ ⑥
Control Methods And The VD Sense Pin Setting Voltage & Specifications
DC/DC Oscillation Frequency
Package
■APPLICATIONS
●CD-R / RW, DVD ●HDD ●PDAs, portable communication modem ●Cellular phones ●Palmtop computers ●Cameras, video recorders
■FEATURES
DC/DC Converter with Built-in LDO and VD Function
<Regulator Block>
Regulator Input
: Serial Input from DC/DC output
Output Voltage Range : 0.9V ~ 4.0V (Accuracy±2%)
Current Limit
: 600mA
Dropout Voltage
: 160mV @ IOUT=200mA
CONDITIONS
Supply Current 1 *XC9510D/E/F Supply Current 2 *XC9510D/E/F
■PIN CONFIGURATION
SOP-8 (TOP VIEW)
■PIN ASSIGNMENT
PIN NUMBER 1 2 3 4 5 6 7 8
PIN NAME PGND
CE/MODE VDD
VDOUT AGND VROUT DCOUT
LX
FUNCTION Power Ground Chip Enable / MODE Switch Power Supply
Input Voltage Range : 2.4V ~ 6.0V
Low ESR Capacitor : Ceramic capacitor compatible
VD Function
: Three Sensing Options for Either
VDD, DCOUT or VROUT
N-ch open drain output
Ta = 25℃ UNIT
V V V mA V mA V mA V mW ℃ ℃
3/36
元器件交易网
XC9510 Series
■ELECTRICAL CHARACTERISTICS