EVAL-AD7795中文资料
AD7790BRMZ;AD7790BRMZ-REEL;AD7790BRM;中文规格书,Datasheet资料
Low Power, 16-BitBuffered Sigma-Delta ADCAD7790 Rev.0Information furnished by Analog Devices is believed to be accurate and reliable.However, no responsibility is assumed by Analog Devices for its use, nor for anyinfringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: Fax: 781.326.8703© 2003 Analog Devices, Inc. All rights reserved.FEATURESPowerSupply: 2.5 V to 5.25 V operationNormal: 75 µA maximumPower-down: 1 µA maximumRMS noise: 1.1 µV at 9.5 Hz update rate16-bit p-p resolutionIntegral nonlinearity: 3.5 ppm typical Simultaneous 50 Hz and 60 Hz rejection Internal clock oscillatorProgrammable gain amplifierRail-to-rail input bufferV DD monitor channelTemperature range: –40°C to +105°C10-lead MSOPINTERFACE3-wire serialSPI®, QSPI™, MICROWIRE™, and DSP compatible Schmitt trigger on SCLKAPPLICATIONSSmart transmittersBattery applicationsPortable instrumentationSensor measurementTemperature measurementPressure measurementWeigh scales4 to 20 mA loops FUNCTIONAL BLOCK DIAGRAM03538-0-001Figure 1.GENERAL DESCRIPTIONThe AD7790 is a low power, complete analog front end for low frequency measurement applications. It contains a low noise 16-bit ∑-∆ ADC with one differential input that can be buffered or unbuffered along with a digital PGA, which allows gains of 1, 2, 4, and 8.The device operates from an internal clock. Therefore, the user does not have to supply a clock source to the device. The output data rate from the part is software programmable and can be varied from 9.5 Hz to 120 Hz, with the rms noise equal to1.1 µV at the lower update rate. The internal clock frequency can be divided by a factor of 2, 4, or 8, which leads to a reduc-tion in the current consumption. The update rate, cutoff frequency, and settling time will scale with the clock frequency. The part operates with a power supply from2.5 V to 5.25 V. When operating from a 3 V supply, the power dissipation for the part is 225 µW maximum. It is housed in a 10-lead MSOP.AD7790Rev. 0 | Page 2 of 20TABLE OF CONTENTSAD7790—Specifications..................................................................3 Timing Characteristics.....................................................................5 Absolute Maximum Ratings............................................................7 Pin Configuration and Function Descriptions.............................8 Typical Performance Characteristics.............................................9 On-Chip Registers..........................................................................10 Communications Register(RS1, RS0 = 0, 0).........................................................................10 Status Register(RS1, RS0 = 0, 0; Power-on/Reset = 0x88)...............................11 Mode Register(RS1, RS0 = 0, 1; Power-on/Reset = 0x02)...............................11 Filter Register(RS1, RS0 = 1, 0; Power-on/Reset = 0x04)...............................12 Data Register(RS1, RS0 = 1, 1; Power-on/Reset = 0x0000) (12)ADC Circuit Information..............................................................13 Overview.....................................................................................13 Noise Performance.....................................................................13 Reduced Current Modes...........................................................13 Digital Interface..........................................................................14 Single Conversion Mode.......................................................15 Continuous Conversion Mode.............................................15 Continuous Read Mode........................................................16 Circuit Description.........................................................................17 Analog Input Channel...............................................................17 Programmable Gain Amplifier.................................................17 Bipolar Configuration................................................................17 Data Output Coding..................................................................17 Reference Input...........................................................................17 V DD Monitor................................................................................18 Grounding and Layout..............................................................18 Outline Dimensions.. (19)REVISION HISTORYRevision 0: Initial VersionAD7790Rev. 0 | Page 3 of 20AD7790—SPECIFICATIONS 1Table 1. (V DD = 2.5 V to 5.25 V; REFIN(+) = 2.5 V; REFIN(–) = GND; CDIV1 = CDIV0 = 0; GND = 0 V; all specifications T MIN to T MAX , unless otherwise noted.)Parameter AD7790B Unit Test Conditions/CommentsADC C H ANNEL SPECIFICATIONOutput Update Rate 9.5 Hz min nom 120 Hz max nomADC C H ANNELNo Missing Codes 2 16 Bits min ±V REF Range, Update Rate ≤ 20 Hz Resolution 16 Bits p-p 9.5 Hz Update Rate Output Noise 1.1 µV rms typ Integral Nonlinearity ±15 ppm of FSR max 3.5 ppm typ Offset Error ±3 µV typ Offset Error Drift vs. Temperature ±10 nV/°C typFull-Scale Error 3±10 µV typ Gain Drift vs. Temperature ±0.5 ppm/°C typ Power Supply Rejection 90 dB min Input Range = ±REFIN, 100 dB typ ANALOG INPUTS Differential Input Voltage Ranges ±REFIN/GAIN V nom REFIN = REFIN(+) – REFIN(–); GAIN = 1, 2, 4, or 8Absolute AIN Voltage Limits 2GND + 100 mV V min Buffered Mode of Operation V DD – 100 mV V max Analog Input Current Buffered Mode of OperationAverage Input Current 2±1 nA max Average Input Current Drift ±5 pA/°C typAbsolute AIN Voltage Limits 2GND – 30 mV V min Unbuffered Mode of Operation V DD + 30 mV V max Analog Input Current Unbuffered Mode of OperationInput current varies with input voltage.Average Input Current ±400 nA/V typ Average Input Current Drift ±50 pA/V/°C typ Normal Mode Rejection 2 @ 50 Hz, 60 Hz 65 dB min 73 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[2:0] = 1004 @ 50 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, FS[2:0] = 1014 @ 60 Hz 80 dB min 90 dB typ, 60 ± 1 Hz, FS[2:0] = 0114 Common Mode Rejection Input Range = ±REFIN, AIN = 1 V @ DC 90 dB min 100 dB typ (FS[2:0] = 1004) @ 50 Hz, 60 Hz 2 100 dB min 50 ± 1 Hz (FS[2:0] = 1014), 60 ± 1 Hz (FS[2:0] = 0114) REFERENCE INPUT REFIN = REFIN(+) – REFIN(–) REFIN Voltage 2.5 V nomReference Voltage Range 20.1 V min V DDV max Absolute REFIN Voltage Limits 2GND – 30 mV V min V DD + 30 mV V max Average Reference Input Current 0.5 µA/V typ Average Reference Input Current Drift ±0.03 nA/V/°C typ1 Temperature Range –40°C to +105°C.2Specification is not production tested, but is supported by characterization data at initial product release. 3Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (V DD = 4 V). 4FS[2:0] are the three bits used in the filter register to select the output word rate.AD7790Rev. 0 | Page 4 of 20SPECIFICATIONS (continued)1Parameter AD7790B Unit Test Conditions/Comments REFERENCE INPUT (continued)Normal Mode Rejection 2@ 50 Hz, 60 Hz 65 dB min 73 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[2:0] = 1004 @ 50 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, FS[2:0] = 1014 @ 60 Hz 80 dB min 90 dB typ, 60 ± 1 Hz, FS[2:0] = 0114 Common Mode Rejection Input Range = ±2.5 V, AIN = 1 V @ DC 100 dB typ FS[2:0] = 1004 @ 50 Hz, 60 Hz 110 dB typ 50 ± 1 Hz (FS[2:0] = 1014), 60 ± 1 Hz (FS[2:0] = 0114) LOGIC INPUTS All Inputs Except SCLK 2 V INL , Input Low Voltage 0.8 V max V DD = 5 V 0.4 V max V DD = 3 VV INH , Input High Voltage 2.0 V min V DD = 3 V or 5 VSCLK Only (Schmitt-Triggered Input)2V T (+) 1.4/2 V min/V max V DD = 5 V V T (–) 0.8/1.4 V min/V max V DD = 5 V V T (+) – V T (–) 0.3/0.85 V min/V max V DD = 5 V V T (+) 0.9/2 V min/V max V DD = 3 V V T (–) 0.4/1.1 V min/V max V DD = 3 V V T (+) - V T (–) 0.3/0.85 V min/V max V DD = 3 V Input Currents ±1 µA max V IN = V DD or GND Input Capacitance 10 pF typ All Digital Inputs LOGIC OUTPUTSV OH , Output High Voltage 2V DD – 0.6 V min V DD = 3 V, I SOURCE = 100 µA V OL , Output Low Voltage 2 0.4 V max V DD = 3 V, I SINK = 100 µAV OH , Output High Voltage 24 V min V DD =5 V, I SOURCE = 200 µA V OL , Output Low Voltage 2 0.4 V max V DD = 5 V, I SINK = 1.6 mA Floating-State Leakage Current ±1 µA max Floating-State Output Capacitance 10 pF typ Data Output Coding Offset BinaryPOWER REQUIREMENTS 5Power Supply Voltage V DD – GND 2.5/5.25 V min/max Power Supply CurrentsI DD Current 675 µA max 65 µA typ, V DD = 3.6 V, Unbuffered Mode 145 µA max 130 µA typ, V DD = 3.6 V, Buffered Mode 80 µA max 73 µA typ, V DD = 5.25 V, Unbuffered Mode 160 µA max 145 µA typ, V DD = 5.25 V, Buffered ModeI DD (Power-Down Mode) 1 µA max5 Digital inputs equal to V DD or GND.6The current consumption can be further reduced by using the ADC in one of the low power modes (see Table 15).AD7790 TIMING CHARACTERISTICS1, 2Table 2. (V DD = 2.5 V to 5.25 V; GND = 0 V, REFIN(+) = 2.5 V, REFIN(–) = GND, CDIV1 = CDIV0 = 0, Input Logic 0 = 0 V,1 Sample tested during initial release to ensure compliance. All input signals are specified with t R = t F = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V.2 See Figure3 and Figure 4.3 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the V OL or V OH limits.4 SCLK active edge is falling edge of SCLK.5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.6RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read only once.Rev. 0 | Page 5 of 20AD7790Rev. 0 | Page 6 of 2003538-0-002DD = 5V,DD = 3V)µA WITH V DD = 5V,DD = 3V)1.6VTO OUTPUTPINFigure 2. Load Circuit for Timing CharacterizationCS (I)I = INPUT, O = OUTPUTFigure 3. Read Cycle Timing DiagramI = INPUT, O = OUTPUTSCLK (I)DIN (I)Figure 4. Write Cycle Timing DiagramAD7790Rev. 0 | Page 7 of 20ABSOLUTE MAXIMUM RATINGSTable 3. (T A = 25°C, unless otherwise noted.)Parameter Rating V DD to GND –0.3 V to +7 V Analog Input Voltage to GND –0.3 V to V DD + 0.3 V Reference Input Voltage to GND –0.3 V to V DD + 0.3 V Total AIN/REFIN Current (Indefinite) 30 mA Digital Input Voltage to GND –0.3 V to V DD + 0.3 V Digital Output Voltage to GND –0.3 V to V DD + 0.3 V Operating Temperature Range –40°C to +105°CStorage Temperature Range –65°C to +150°CMaximum Junction Temperature 150°CMSOP θJA Thermal Impedance 206°C/W θJC Thermal Impedance 44°C/WLead Temperature, Soldering (10 sec) 300°CIR Reflow, Peak Temperature 220°CStresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.AD7790Rev. 0 | Page 8 of 20PIN CONFIGURATION AND FUNCTION DESCRIPTIONS03538-0-005DIN DOUT/RDYV DD GNDREF(–)Figure 5. Pin ConfigurationAD7790Rev. 0 | Page 9 of 20TYPICAL PERFORMANCE CHARACTERISTICS03538-0-007–120–110–100–90–80–70–60–50–40–30–20–10040802060100120140d B1600FREQUENCY (Hz)Figure 6. Frequency Response for a 16.6 Hz Update Rate03538-0-0130.51.01.52.02.53.0 3.54.0 4.5R M S N O I S E (µV )5.0V REF (V)Figure 7. RMS Noise vs. Reference VoltageAD7790Rev. 0 | Page 10 of 20ON-CHIP REGISTERSThe ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise stated.COMMUNICATIONS REGISTER (RS1, RS0 = 0, 0)The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the com-munications register. The data written to the communications register determines whether the next operation is a read or write operation, and to which register this operation takes place. For read or write operations, once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the communications register. This is the default state of the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the communications regis-ter. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high returns the ADC to this default state by resetting the entire part. Table 5 outlines the bit designations for the communications register. CR0 through CR7 indi-cate the bit location, CR denoting the bits are in the communications register. CR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.Table 6. Register SelectionRS1 RS0 RegisterRegister Size0 0 Communications Registerduring a Write Operation8-Bit 0 0 Status Register during aRead Operation8-Bit 0 1 Mode Register 8-Bit 1 0 Filter Register 8-Bit 1 1 Data Register16-BitTable 7. Channel SelectionCH1 CH0 Channel 0 0 AIN(+) – AIN(–) 0 1 Reserved 1 0 AIN(–) – AIN(–) 1 1 V DD Monitor分销商库存信息:ANALOG-DEVICESAD7790BRMZ AD7790BRMZ-REEL AD7790BRM。
AD7799中文资料.
写入 01011100；当 RDY 变为低时，向通信寄存器中写入
01011000，退出连续可读模式。当在连续可读模式下，ADC
检测到 DIN 脚的有效活动，也会退出连续可读模式。另外，
如果在 DIN 管脚上连续输入 32 位的高电平，AD 被复位。因
此，当在连续读模式下 DIN 脚应被置为低电平直到一个新的
参考输入电压 GND
输入数字电压 GND
输出数字电压 GND
Rating −0.3 V to +7 V −0.3 V to +7 V −0.3 V to AVDD +
0.3 V −0.3 V to AVDD +
0.3 V −0.3 V to DVDD +
0.3 V −0.3 V to DVDD +
0.3 V
11.33
9.44 3.132
1.773
1.107பைடு நூலகம்
0.5
0.413
0.374
AD7799在2.5V参考电源下其典型分辨率（BIT）与增益和输出更新速率之间的关
系
更新速率Gain=1 Gain=2 Gain=3 Gain=4 Gain=5 Gain=6 Gain=7 Gain=8
4.17 Hz
23(20.5) 22(19.5) 22.5(20) 22.5(20) 22(19.5) 22(19.5) 21.5(19) 20.5(18)
应用
电子磅秤 压力测量 应变传感器 血气分析 工业过程控制 仪器仪表 便携式仪表 血液分析 智能变送器 液体/气体色谱 6 位数字电压表
概述：
AD7798/AD7799 适合在低功耗，低噪音，完成 模拟前端高精度测量应用。
采用AD7793 24位 Sigma-Delta ADC的热电偶测量系统(T型热电偶)
0.01µF 1kΩ –
0.01µF
COLD JUNCTION
THERMISTOR KTY81-110
1kΩ AT 25°C 2kΩ 0.1%
10ppm
0.1µF
DVDD AIN1(+)
AVDD
AD7793
AIN1(–)
IOUT2 IOUT1 AIN2(+)
AIN2(–) REFIN(+)
SCLK DIN
0
100
200
300
400
TEMPERATURE (°C)
图2. 热电偶电动势与温度的关系
Rev. 0 | Page 2 of 4
电路笔记
当系统处于室温时，热敏电阻应指示室温的值。热敏电 阻指示的是相对于冷结温度的相对温度，即冷结（热敏 电阻）与热电偶的温差。因此，在室温时，热电偶应指示 0°C。 如果将热电偶放在一个冰桶中，热敏电阻仍旧测量环境 （冷结）温度。热电偶应指示热敏电阻值的负值，使得总 温度等于0。 最后，对于16.7 Hz的输出数据速率和128倍的增益， AD7793的均方根噪声等于0.088 μV。峰峰值噪声等于：
6.6 × 均方根噪声 = 6.6 × 0.088 μV = 0.581 μV 如果热电偶的灵敏度恰好为40 μV/°C，则热电偶的温度测 量分辨率为：
0.581 μV ÷ 40 μV = 0.014°C 图3所示为实际的测试板。系统评估如下：分别在室温时以 及将热电偶放入冰桶的情况下，测量热敏电阻温度、热电 偶温度和分辨率。结果如表1所示。
电路评估与测试
测试数据利用图3所示测试板获得。该系统的完整文档位于 CN-0206设计支持包中： /CN0206-DesignSupport
AD779x_FAQ_Instru_Conv_cn
/sigma_deltaAD779x 仪表转换器常见问题解答一般常见问题Σ-Δ型ADC 有哪些优缺点？利用Σ-Δ技术实现高分辨率的代价是速度。
硬件必须以远大于最高信号带宽的过采样速率工作，因而需要非常复杂的数字电路。
由于这一限制，Σ-Δ型转换器传统上只能用于高分辨率、极低频率应用，最近才开始出现在语音、音频和中等速度(100 kHz 至1 MHz)应用中。
数字滤波器导致从采样周期开始到第一个有效数字输出之间有很长的延时；同样，之后在数字输出与对应的采样时间之间也有明显的迟滞。
这些特性会降低多路复用系统中的输出速率，因为从一个通道切换到另一个通道之后，数字滤波器需要许多时钟周期才能建立。
Σ-Δ型转换器中的多数电路都是数字电路，因此这些转换器可以采用各种IC 工艺制造。
这意味着，其性能不会随时间和温度的变化而发生显著漂移。
这种转换器本身具有单调性(即数字输出的变化始终与模拟输入的变化斜率相同)，这在闭环控制系统中尤为重要，因为如果误判所测量变量的变化方向，系统可能会变得不稳定。
此外，这种转换器本身还具有线性度，差分非线性度很小。
调制器中的模数转换具有高输入采样速率和低精度特性，因此无需外部采样保持电路(这些器件本身具有自采样保持功能)。
对模拟抗混叠滤波器的要求极低，大多数情况下，只需要一个简单的单极点RC 滤波器，因为目标带宽明显低于约在调制器频率出现的第一镜像。
相比之下，采用其它(非过采样)技术的中高分辨率应用所要求的滤波器则非常复杂，难以设计，并且尺寸较大、成本高昂。
主要应用有哪些？这些器件可提供完整的模拟前端，适合低频测量应用，包括便携式仪器、过程控制、智能发射器、电子秤、基于传感器的应用以及温度和压力测量系统。
例如，在压力和温度测量系统中，系统设计人员面对的任务是测量压力传感器、RTD(电阻式温度检测器)或热电偶所产生的小信号，并将其解析至16位或更高的分辨率。
主要设计任务包括：对传感器的输出信号进行信号调理，处理信号以达到所需的分辨率和精度，以及确保便携式应用的功耗足够低。
EVAL-AD7718EB资料
FUNCTIONAL BLOCK DIAGRAM
DVDD DGND REFIN2(+)/AIN9 REFIN1(+) REFIN2(–)/AIN10 REFIN1(–) XTAL1 XTAL2
OSC AND PLL AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AINCOM
POS BUF REFIN(+) MUX NEG BUF PGA REFIN(–) SERIAL INTERFACE AND CONTROL LOGIC AVDD DOUT DIN SCLK CS RDY RESET
⌺-⌬ ADC* *AD7708 16-BIT ADC *AD7718 24-BIT ADC
AD7708/AD7718
AVDD AGND
I/O PORT
P2
P1
SPI and QSPI are trademarks of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Corp. VREF Select is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 Fax: 781/326-8703 © Analog Devices, Inc., 2001
AD9952 Evaluation Board Datasheet说明书
功能框图图1.DC/PHASE CORRECTION DC/PHASE CORRECTIONC SS C L KS D I OSERIAL PORT INTERFACE15141323892325262838VPOS_3P3DECL1TO DECL4211119303136273340101VPOS_5VLDO VCOLDO 2.5VRFIN0RFIN12922POLYPHASE FILTERLOIN–REFINLOIN+I+I–Q–Q+QUAD DIVIDERPLL343935547611990-001Rev. ADocument FeedbackInformation furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Speci cations subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved. Technical Support 695 MHz 至2700 MHz 正交解调器，集成小数N 分频PLL 和VCOADRF6820产品特性集成小数N 分频PLL 的I/Q 解调器RF 输入频率范围：695 MHz 至2700 MHz 内部LO 频率范围：356.25 MHz 至2850 MHz 输入P1dB ：14.5 dBm (1900 MHz RF) 输入IP3：35 dBm (1900 MHz RF) 可编程HD3/IP3调整单刀双掷(SPDT) RF 输入开关RF 数字步进衰减范围：0 dB 至15 dB集成式RF 可调谐巴伦，支持单端50 Ω输入 多核集成式VCO解调1 dB 带宽：600 MHz 4个可选基带增益和带宽模式数字可编程LO 相位失调和直流零点可通过三线式串行端口接口(SPI)进行编程 40引脚、6 mm x 6 mm LFCSP 封装应用蜂窝W-CDMA/GSM/LTE 数字预失真(DPD)接收器 微波点对点无线电概述ADRF6820是一款高度集成的解调器和频率合成器，非常适合用于下一代通信系统中。
AD7792BRUZ;AD7793BRUZ;AD7792BRUZ-REEL;AD7793BRUZ-REEL;AD7792BRU;中文规格书,Datasheet资料
3-Channel, Low Noise, Low Power, 16-/24-Bit∑-ΔADC with On-Chip In-Amp and ReferenceAD7792/AD7793 Rev. BInformation furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, M A 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2004–2007 Analog Devices, Inc. All rights reserved.FEATURESUp to 23 bits effective resolutionRMS noise40 nV @ 4.17 Hz85 nV @ 16.7 HzCurrent: 400 μA typicalPower-down: 1 μA maximumLow noise programmable gain instrumentation amp Band gap reference with 4 ppm/°C drift typical Update rate: 4.17 Hz to 470 Hz3 differential inputsInternal clock oscillatorSimultaneous 50 Hz/60 Hz rejection Programmable current sourcesOn-chip bias voltage generatorBurnout currentsPower supply: 2.7 V to 5.25 V–40°C to +105°C temperature rangeIndependent interface power supply16-lead TSSOP packageInterface3-wire serialSPI®, QSPI™, MICROWIRE™, and DSP compatible Schmitt trigger on SCLKAPPLICATIONSThermocouple measurementsRTD measurementsThermistor measurementsGas analysisIndustrial process controlInstrumentationPortable instrumentationBlood analysisSmart transmittersLiquid/gas chromatography6-digit DVMFUNCTIONAL BLOCK DIAGRAM4Figure 1.GENERAL DESCRIPTIONThe AD7792/AD7793 are low power, low noise, complete analog front ends for high precision measurement applications. The AD7792/AD7793 contain a low noise 16-/24-bit ∑-Δ ADC with three differential analog inputs. The on-chip, low noise instrumentation amplifier means that signals of small ampli-tude can be interfaced directly to the ADC. With a gain setting of 64, the rms noise is 40 nV when the update rate equals 4.17 Hz.The devices contain a precision low noise, low drift internal band gap reference and can accept an external differential reference. Other on-chip features include programmable excitation current sources, burnout currents, and a bias voltage generator. The bias voltage generator sets the common-mode voltage of a channel to AV DD/2.The devices can be operated with either the internal clock or an external clock. The output data rate from the parts is software-programmable and can be varied from 4.17 Hz to 470 Hz. The parts operate with a power supply from 2.7 V to 5.25 V. They consume a current of 400 μA typical and are housed in a 16-lead TSSOP package.AD7792/AD7793Rev. B | Page 2 of 32TABLE OF CONTENTSFeatures..............................................................................................1 Applications.......................................................................................1 Functional Block Diagram..............................................................1 General Description.........................................................................1 Revision History...............................................................................2 Specifications.....................................................................................3 Timing Characteristics.....................................................................6 Timing Diagrams..........................................................................7 Absolute Maximum Ratings............................................................8 ESD Caution..................................................................................8 Pin Configuration and Function Descriptions.............................9 Output Noise and Resolution Specifications..............................11 External Reference......................................................................11 Internal Reference......................................................................12 Typical Performance Characteristics...........................................13 On-Chip Registers..........................................................................14 Communications Register.........................................................14 Status Register.............................................................................15 Mode Register.............................................................................15 Configuration Register..............................................................17 Data Register...............................................................................18 ID Register...................................................................................18 IO Register...................................................................................18 Offset Register............................................................................19 Full-Scale Register......................................................................19 ADC Circuit Information..............................................................20 Overview.....................................................................................20 Digital Interface..........................................................................21 Circuit Description.........................................................................24 Analog Input Channel...............................................................24 Instrumentation Amplifier........................................................24 Bipolar/Unipolar Configuration..............................................24 Data Output Coding..................................................................24 Burnout Currents.......................................................................25 Excitation Currents....................................................................25 Bias Voltage Generator..............................................................25 Reference.....................................................................................25 Reset.............................................................................................25 AV DD Monitor.............................................................................26 Calibration...................................................................................26 Grounding and Layout..............................................................26 Applications Information..............................................................28 Temperature Measurement using a Thermocouple...............28 Temperature Measurement using an RTD..............................29 Outline Dimensions.......................................................................30 Ordering Guide.. (30)REVISION HISTORY3/07—Rev. A to Rev. BUpdated Format..................................................................Universal Change to Functional Block Diagram...........................................1 Changes to Specifications Section..................................................3 Changes to Specifications Endnote 1.............................................5 Changes to Table 5, Table 6, and Table 7.....................................11 Changes to Table 8, Table 9, and Table 10...................................12 Changes to Table 16........................................................................16 Changes to Overview Section.......................................................20 Renamed Applications Section to Applications Information...29 Changes to Ordering Guide..........................................................30 4/05—Rev. 0 to Rev. AChanges to Absolute Maximum Ratings........................................8 Changes to Figure 17.......................................................................22 Changes to Data Output Coding Section.....................................24 Changes to Calibration Section.....................................................26 Changes to Ordering Guide...........................................................30 10/04—Revision 0: Initial VersionAD7792/AD7793Rev. B | Page 3 of 32SPECIFICATIONSAV DD = 2.7 V to 5.25 V; DV DD = 2.7 V to 5.25 V; GND = 0 V; all specifications T MIN to T MAX , unless otherwise noted. Table 1.Parameter AD7792B/AD7793B 1 Unit Test Conditions/Comments ADC CHANNEL Output Update Rate 4.17 to 470 Hz nom No Missing Codes 224 Bits min f ADC < 242 Hz, AD7793 16 Bits min AD7792 Resolution See Output Noise and Resolution Specifications Output Noise and Update Rates See Output Noise and Resolution Specifications Integral Nonlinearity ±15 ppm of FSR max Offset Error 3±1 μV typOffset Error Drift vs. Temperature 4±10 nV/°C typ Full-Scale Error 3, 5±10 μV typGain Drift vs. Temperature 4±1 ppm/°C typ Gain = 1 to 16, external reference ±3 ppm/°C typ Gain = 32 to 128, external reference Power Supply Rejection 100 dB min AIN = 1 V/gain, gain ≥ 4, external reference ANALOG INPUTS Differential Input Voltage Ranges ±V REF /Gain V nom V REF = REFIN(+) − REFIN(−) or internal reference,gain = 1 to 128Absolute AIN Voltage Limits 2 Unbuffered Mode GND – 30 mV V min Gain = 1 or 2 AV DD + 30 mV V max Buffered Mode GND + 100 mV V min Gain = 1 or 2 AV DD – 100 mV V max In-Amp Active GND + 300 mV V min Gain = 4 to 128 AV DD – 1.1 V max Common-Mode Voltage, V CM 0.5 V min V CM = (AIN(+) + AIN(−))/2, gain = 4 to 128 Analog Input Current Buffered Mode or In-Amp Active Average Input Current 2±1 nA max Gain = 1 or 2, update rate < 100 Hz ±250 pA max Gain = 4 to 128, update rate < 100 HzAverage Input Current Drift ±2 pA/°C typ Unbuffered Mode Gain = 1 or 2. Average Input Current ±400 nA/V typ Input current varies with input voltage Average Input Current Drift ±50 pA/V/°C typNormal Mode Rejection 2Internal Clock @ 50 Hz, 60 Hz 65 dB min 80 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 10106@ 50 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, FS[3:0] = 10016@ 60 Hz 90 dB min 100 dB typ, 60 ± 1 Hz, FS[3:0] = 10006External Clock @ 50 Hz, 60 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 10106@ 50 Hz 94 dB min 100 dB typ, 50 ± 1 Hz, FS[3:0] = 10016@ 60 Hz 90 dB min 100 dB typ, 60 ± 1 Hz, FS[3:0] = 10006Common-Mode Rejection @ DC 100 dB min AIN = 1 V/gain, gain ≥ 4@ 50 Hz, 60 Hz 2100 dB min 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 10106@ 50 Hz, 60 Hz 2100 dB min 50 ± 1 Hz (FS[3:0] = 1001)6, 60 ± 1 Hz(FS[3:0] = 1000)6AD7792/AD7793Rev. B | Page 4 of 32AD7792/AD77931 Temperature range is –40°C to +105°C. At the 19.6 Hz and 39.2 Hz update rates, the INL, power supply rejection (PSR), common-mode rejection (CMR), and normal mode rejection (NMR) do not meet the data sheet specification if the voltage on the AIN(+) or AIN(−) pins exceed AV DD − 16 V typically. When this voltage is exceeded, the INL, for example, is reduced to 18 ppm of FS typically while the PSR is reduced to 69 dB typically. Therefore, for guaranteed performance at these update rates, the absolute voltage on the analog input pins needs to be below AV DD − 1.6 V.2 Specification is not production tested, but is supported by characterization data at initial product release.3 Following a calibration, this error is in the order of the noise for the programmed gain and update rate selected.4 Recalibration at any temperature removes these errors.5 Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (AV DD = 4 V, gain = 1, T A = 25°C).6 FS[3:0] are the four bits used in the mode register to select the output word rate.7 Digital inputs equal to DV DD or GND with excitation currents and bias voltage generator disabled.Rev. B | Page 5 of 32AD7792/AD7793Rev. B | Page 6 of 32TIMING CHARACTERISTICSAV DD = 2.7 V to 5.25 V , DV DD = 2.7 V to 5.25 V , GND = 0 V , Input Logic 0 = 0 V , Input Logic 1 = DV DD , unless otherwise noted.1 Sample tested during initial release to ensure compliance. All input signals are specified with t R = t F = 5 ns (10% to 90% of DV DD ) and timed from a voltage level of 1.6 V. 2See Figure 3 and Figure 4. 3These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the V OL or V OH limits. 4SCLK active edge is falling edge of SCLK. 5These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. 6 RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read only once.04855-002DD = 5V,DD = 3V)DD = 5V,DD = 3V)1.6VTO OUTPUTPINAD7792/AD7793Rev. B | Page 7 of 32TIMING DIAGRAMS048CS (I)NOTES1. I = INPUT, O = OUTPUTFigure 3. Read Cycle Timing Diagram04855NOTES1. I = INPUT, O = OUTPUTCS (I)SCLK (I)DIN (I)Figure 4. Write Cycle Timing DiagramAD7792/AD7793Rev. B | Page 8 of 32ABSOLUTE MAXIMUM RATINGST A = 25°C, unless otherwise noted. Table 3.Parameter RatingsAV DD to GND −0.3 V to +7 V DV DD to GND−0.3 V to +7 VAnalog Input Voltage to GND −0.3 V to AV DD + 0.3 V Reference Input Voltage to GND −0.3 V to AV DD + 0.3 V Digital Input Voltage to GND −0.3 V to DV DD + 0.3 V Digital Output Voltage to GND −0.3 V to DV DD + 0.3 V AIN/Digital Input Current10 mAOperating Temperature Range −40°C to +105°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C TSSOPθJA Thermal Impedance 128°C/W θJC Thermal Impedance 14°C/W Lead Temperature, SolderingVapor Phase (60 sec) 215°C Infrared (15 sec)220°CStresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.ESD CAUTIONAD7792/AD7793Rev. B | Page 9 of 32PIN CONFIGURATION AND FUNCTION DESCRIPTIONS04855-005CLK CS IOUT1AIN2(+)AIN1(–)AIN1(+)SCLK DOUT/RDY DV DD AV DD REFIN(–)/AIN3(–)AIN2(–)REFIN(+)/AIN3(+)IOUT2GND DINAD7792/AD7793Rev. B | Page 10 of 32分销商库存信息:ANALOG-DEVICESAD7792BRUZ AD7793BRUZ AD7792BRUZ-REEL AD7793BRUZ-REEL AD7792BRU AD7793BRUEVAL-AD7792EBZ。
EVAL-ADUSB2EBUZ;中文规格书,Datasheet资料
AN-1006APPLICATION NOTE One Technology Way•P.O.Box9106•Norwood,MA02062-9106,U.S.A.•Tel:781.329.4700•Fax:781.461.3113•Using the EVAL-ADUSB2EBZby Brett GildersleeveINTRODUCTIONThe EV AL-ADUSB2EBZ features USB-to-I2C and SPI conversion. It is compatible with 1.8 V and 3.3 V target devices and allows for SigmaStudio™ integration for most SigmaDSP® processors. Its on-board power regulators are capable of supplying the target board, and it features a standard Aardvark-compatible programming header. The EV AL-UDSUB2EBZ provides SPI control of up to five slave devices with a low profile surface-mount USB miniature Type B connector, and it allows for plug-and-play operation.The EV AL-ADUSB2EBZ is ideal for downloading codeand register settings to SigmaDSP processors and codecswith SigmaStudio. It can also be used for real-time tuningof SigmaDSP production units with SigmaStudio. GENERAL DESCRIPTIONThe EV AL-ADUSB2EBZ, also known as the USBi, is a standalone communications interface and programmer for SigmaDSPsystems. It translates USB control commands from SigmaStudio to the I2C and SPI communications protocols. The USBi is powered over the USB cable; therefore, no external power supply is required. The ribbon cable and 10-pin header form a bridge to the target board to connect the communications signals to the target IC. The ribbon cable also carries 5 V power from the USB hub, which can be used to power the target board if desired.The on-board regulators enable both 1.8 V and 3.3 V IOVDD operation, allowing for increased compatibility with target devices.Up to five slave devices can be controlled by the USBi simulta-neously. To control multiple SPI devices, additional latch signals are provided, although they are not connected to the ribbon cable.The USBi can be used to control SigmaDSP systems in real time via SigmaStudio, and is capable of programming an EEPROM in self-boot systems. It is an ideal solution for in-circuit program-ming and tuning of prototype systems.The USBi only supports USB 2.0 interfaces; the USBi will not work with PCs that only support USB Version 1.0 and USB Version 1.1.FUNCTIONAL BLOCK DIAGRAMFigure 1.AN-1006 Application Note TABLE OF CONTENTSIntroduction (1)General Description (1)Functional Block Diagram (1)Using the USB Interface with SigmaStudio (3)Installing the Drivers (3)Adding the USBi to a SigmaStudio Project (4)Configuring the USBi to Communicate with an IC (4)Configuring the USBi to Communicate with Multiple ICs (4)Controlling the USBi (5)Monitoring the USBi (6)Using the USBi to Program a Self-Boot EEPROM (6)Warning (6)Circuit Schematics (7)USB Connector (7)Power Regulator (7)Cypress USB Interface (8)Crystal Oscillator Schematic (8)LEDs (9)EEPROM (9)Target Board Power Switch (9)Target Board Programming Header (9)Evaluation Board Schematics and Artwork (10)Schematics (10)Board Layout (12)Bill of Materials (13)REVISION HISTORY4/10—Rev. 0 to Rev. AChanges to General Description Section (1)Added Warning Section (6)5/09—Revision 0: Initial VersionApplication NoteAN-1006USING THE USB INTERFACE WITH SIGMASTUDIOINSTALLING THE DRIVERSSigmaStudio must be installed to use the USBi. OnceSigmaStudio has been properly installed, connect the USBi to an available USB port with the included USB cable. At this point, Windows® XP recognizes the device and prompts the user to install drivers.08093-002Figure 2. Found New Hardware NotificationSelect the Install from a list or specific location (Advanced) option and click Next >.08093-003Figure 3. Found New Hardware Wizard—InstallationClick Search for the best driver in these locations , then select Include this location in the search . Click Browse to find the SigmaStudio 3.0\USB drivers directory.08093-004Figure 4. Windows Found New Hardware Wizard—Search andInstallation OptionsWhen the warning about Windows Logo testing appears on the screen, click Continue Anyway .08093-005Figure 5. Windows Logo Testing WarningAN-1006Application NoteADDING THE USBi TO A SIGMASTUDIO PROJECTTo use the USBi in conjunction with SigmaStudio, first select it in the Communication Channels subsection of the toolbox in the Hardware Configuration tab, and add it to the project space.08093-006Figure 6. Adding the USBi Communication ChannelIf SigmaStudio cannot detect the USBi on the USB port of the computer, then the background of the USB label will be red. This may happen when the USBi is not connected or when the drivers are incorrectly installed.08093-007Figure 7. USBi Not Detected by SigmaStudioIf SigmaStudio detects the USBi on the USB port of the computer, the background of the USB label changes to orange.08093-008Figure 8. USBi Detected by SigmaStudioCONFIGURING THE USBi TO COMMUNICATE WITH AN ICTo use the USBi to communicate with the target IC, connect it by click-dragging a wire between the blue pin of the USBi and the green pin of the IC. The corresponding drop-down box of the USBi automatically fills with the default mode and channel for that IC.08093-009Figure 9. Connecting the USBi to an ICTo change the communication mode and channel, click the drop-down box and select the appropriate mode and channel from the list.08093-010Figure 10. Selecting the Communications Mode and ChannelCONFIGURING THE USBi TO COMMUNICATE WITH MULTIPLE ICSThe USBi can communicate with up to five ICs simultaneously. To communicate with more than one IC, add another IC to the project and connect it to the next available pin of the USBi.Multiple Address Operation with I2CThe USBi can support up to four identical devices on the same bus if the I 2C address pins of the target devices are indepen-dently set to four different addresses, matching the addresses in the drop-down box in the Hardware Configuration tab of SigmaStudio.08093-011Figure 11. Multiple Address Operation with I 2CApplication NoteAN-1006Multiple Address Operation with SPICombined Multiple Latch and Multiple Address Operation with SPIThe USBi can support up to two identical devices on the same SPI latch if the SPI address pins of the target devices are indepen-dently set to two different addresses, matching the addresses in the drop-down box in the Hardware Configuration tab ofSigmaStudio.A combination of multiple latch and multiple address schemes can be used, but the total number of devices cannot exceed five.CONTROLLING THE USBiThe USBi has several functions for controlling the target hardware. The control options are accessed in SigmaStudio by right-clicking on the USB Interface in the Hardware Configurationtab.08093-01208093-015Figure 15. USBi Control MenuFigure 12. Multiple Address Operation with SPICapture Output DataMultiple Latch Operation with SPIThis option accesses the Capture Window, which displays a log of all communication between the PC and the target IC (see Figure 1The USBi can support devices on five different SPI latches. When multiple latches are used, the additional SPI latch signals from the USBi that are not connected to the ribbon cable need to be manually wired to the target.7).Device Power On/OffThis option switches the line that supplies power to the target board. By default, the device power is on.08093-013Device Enable/DisableFor supported ICs, selecting this option switches the device to low power mode.Reset USB InterfaceThis function performs a software reset of the USB driver, and causes the Cypress USB microcontroller to reload its firmware.Figure 13. Multiple Latch Operation with SPIThe locations of extended SPI latch signals are shown in Figure 14.08093-014Figure 14. Extended SPI Latch Signal Pinout (Bottom View of Board)AN-1006Application NoteMONITORING THE USBiUsing the Capture Window , it is possible to view all outgoing communications transfers from the PC to the target IC. For each write, the write mode, time of write, cell name (if applica-ble), parameter name, address, value, data (in decimal and hexadecimal), and byte length are shown.For block writes where more than one memory location is written, only the first location is shown. The expand/collapse button in the leftmost column allows the user to view the full data write.USING THE USBi TO PROGRAM A SELF-BOOT EEPROMAfter compiling a project, the registers and RAM contents can be written to a target EEPROM for self-boot. To use this functionality, an EEPROM IC must be connected to the USBi in the Hardware Configuration window. After verifying that the EEPROM write protect pin is disabled on the target board, right-click the target IC (SigmaDSP), and select Write Latest Compilation to E2PROM .08093-017Figure 16. Writing to the Self-Boot EEPROMWARNINGThe USBi has an EEPROM on the I 2C bus at Address 0x51, which it uses to indicate its Vendor ID and Product ID to the PC, as well as boot its internal program. Y ou should avoid having any other EEPROMs in your system design at this address. This EEPROM is not write-protected; therefore, if you attempt to write to Address 0x51, you will overwrite the USBi's onboard EEPROM, and the USBi will cease to function. The USBi cannot bereprogrammed without returning the board to Analog Devices. Most EEPROMs are set to Address 0x51 by setting its pins A0 = 1 and A1 = A2 = 0.08093-016Figure 17. Output Capture WindowApplication NoteAN-1006CIRCUIT SCHEMATICSUSB CONNECTORThe connection between the host PC and the Cypress USB interface device is via a standard USB cable that carries D+ and D− signals for data communications, a 5 V power supply, and ground. The D+ and D− lines are a one-wire communication interface carried by half-duplex differential signals on a twisted pair. The clock is embedded in the data using the nonreturn-to-zero inverted (NRZI) line code. These signal lines connect directly to pins on the Cypress USB interface.A surface-mounted USB miniature Type B jack was selected for its low profile and increasing ubiquity in consumer electronics.J308093-018Figure 18. USB Connector SchematicPOWER REGULATORThe Cypress USB Interface I/O ports are capable of operating in both 1.8 V and 3.3 V modes, depending on the target device in the system. Two regulators, one for 5 V to 3.3 V regulation and the other for 5 V to 1.8 V regulation, run simultaneously when the board is powered. A switch (S1) is provided to easily switch the IOVDD supply between the two regulators. LED D4 provides visual feedback that the board is being supplied with 5 V power from the PC USB port.The position of switch S1 should not be changed when the board is connected to the USB bus.08093-019Figure 19. Power Regulator SchematicAN-1006Application NoteCYPRESS USB INTERFACEThe Cypress USB interface is the core of the system, including all of the necessary functionality to convert USB commands into corresponding I 2C or SPI read/write transfers, and acts as a FIFO to route data between the host PC and the target device.CRYSTAL OSCILLATOR SCHEMATICThe Cypress USB interface is its own clock master, and the board includes a crystal oscillator circuit with a 24 MHz piezoelectric crystal resonator to provide stability to the oscillator circuit. The crystal resonator is driven in parallel by the XTALOUT and XTALIN pins of the Cypress USB interface.112p F08093-021Figure 20. Crystal Oscillator Schematic08093-020Figure 21. Cypress USB Interface SchematicApplication NoteAN-1006LEDSThe LEDs provide feedback to the user about the status of the Cypress USB microcontroller.08093-022Figure 22. LEDs SchematicTable 1. LED FunctionsReferenceDesignator Color Functionality D1 Yellow I 2C mode is active D2 Blue GPIO LED, for firmware debug purposes D3 Yellow SPI mode is active D4 Red 5 V power being is supplied over the USB busEEPROMThe EEPROM is an important system element that identifies the board to the host PC and stores the firmware for theCypress USB Interface. The EEPROM is programmed during manufacturing via the J2 connector.8093-0230Figure 23. EEPROM SchematicTARGET BOARD POWER SWITCHThe USBi is capable of supplying power to the target board after the Cypress USB microcontroller has finished its boot up process. The USB_PWR_ON signal connects to the base of Q2 and turns on both transistors when driven high.This circuit also enables a software-controlled target reset from SigmaStudio.08093-024LOCAL FOR ADG721Figure 24. Target Power Switch SchematicTARGET BOARD PROGRAMMING HEADERTo properly boot the Cypress USB microcontroller from the EEPROM, it is necessary to remove all other devices from the I 2C bus. The ADG721BRMZ analog switch remains open, isolating the I 2C bus from the target, until the boot process has completed.13579246810111312142X5 CUSTOM RIBBONJ15V0DD_USBCTRL CTRL S1IN1D1U2-AADG721BRMZS2IN2D2U2-B ADG721BRMZC20.10uFSCLSDACDATA CLATCH1CCLK BRD_RESET COUT USB_CLK CLATCH2CLATCH3CLATCH4CLATCH5USB_PWR_ONUSB_PWR_ON3V3DD8093-025Figure 25. Target Board Programming Header SchematicAN-1006 Application Note EVALUATION BOARD SCHEMATICS AND ARTWORKSCHEMATICSLOCALFORFXLP34CCLDAVDD_USBUSB_PWR_893-028分销商库存信息: ANALOG-DEVICES EVAL-ADUSB2EBUZ。
一种基于AD7795模数转换器的低功耗PT100温度采集系统设计
图 １为温度探测系统框图，主要包括温度传感 器、无线通信模块、Ａ／Ｄ转换电路以及中央处理器。 该系统通过内部定时器来实现温度信号的定时采 集，同时根据固定数据格式将处理得到的数据存储 至内部存储器，之后由中央处理器以及 ＢＣ９５－Ｂ５ 模块按照每间隔 １ｈ的周期根据事先设定的格式把 数据传输至特定服务器内。系统选择电池作为电 源，供电电压为 ３．３Ｖ，考虑到实际温度探测期间应 尽量减少电池更换次数，因此要求该系统能够实现 低功耗的运行状态。
·９８·
工业仪表与自动化装置 ２０１９年第 １期
极大简化测试过程。 为了进一步提高温度探测精度，应选择性能稳
定、精度高以及温度响应速度快的 ＰＴ１００铂电阻作 为温度传感器。此外还应该尽量增加采集系统的精 度，以得到更高精度的测量结果。该文选择功耗小、 精度高且能够有效抑制噪声的 ２４位 ＡＤ７７９５作为 模 数 转 换 器，并 以 功 耗 小、稳 定 性 强 的 ８ 位 ＰＩＣ１８Ｆ２４Ｋ２２作为核心控制器，在控制器与模数转 换器之间采用 ＳＰＩ总线相连，使整个系统具备良好 的稳定 性。系 统 要 求 温 度 探 测 的 精 度 能 够 达 到 ０．０４℃，有效满足高精度的温度探测与数据采集的 要求。
向为电工电子技术和电力系统相关技术。 Ｅｍａｉｌ：ｈｕａｎｇｒｕｉｓｈｕａ８７４９６０＠１２６．ｃｏｍ
Hale Waihona Puke 进行监测，该方法因为需要监测者手持测温设备进 行温度探测与查看，同时手动记录测试得到的温度 值，需要耗费较多的时间与人力，而且实际测量误差 也比较大，无法实现实时探测温度的要求；二是通过 有线传输的方式进行温度监控，该方法需要为监测 系统布设大量传输线路，不利于监测设备的转移，遇 到恶劣的监测环境会导致测试结果的精度明显降 低；三是使用无线温度传感器进行温度监测，该方法 测试过程较为方便，设备可以灵活放置，能够达到实 时监控的目的。在实际应用中，因为温度采集过程 的环境通常都很复杂，此时选择无线探测方式可以
AD7794
低功耗24位∑—△模数转换器AD7794一、概述ADI公司生产的AD7794具有功耗低和完全模拟输入终端，可用在低频信号的测量中。
它克服了同类产品为低噪声牺牲低功耗，或者为低功耗牺牲低噪声的局限性，能够同时提供低噪声和低功耗。
该系列ADC采用2.7V ～ 5.25 V单电源供电，其功耗电流仅400 μA。
同时噪声只有40 nVrms，从而使其适合要求低功耗和高精度测量的应用。
它集成了六个差分传感通道的24位ADC，使其非常适合要求较多通道的应用。
片上还有低噪声的仪用放大器，这意味着幅度比较小的信号可以直接输入到ADC。
片上还集成了精密的低噪声、低漂移的内部参考电源用于测量绝对量。
如果要测量相对的量，可以加一个外部的参考。
另外，片上还集成了增益可调的激励电流源和用于温度测量的偏置电压发生器。
在压力测量和电子秤应用中，该系列ADC提供一个低功耗开关，用于切断转换之间的电桥以使系统功耗最小。
该芯片可以使用内部时钟，如果同步运行多个芯片时还可以使用外部时钟。
输出数据的速度是可以通过编程来调节的，可以在4Hz到500Hz之间变化，在16.6 Hz条件下它们能够提供同步抑制50 Hz和60 Hz干扰信号的功能。
AD7794主要具有以下一些特性：●6个模拟输入通道●低噪声可编程增益放大器●电源电压2.7V ～ 5.25 V●工作时的电流仅为400 μA●掉电模式的电流为0.1μA●更新速率4Hz到500Hz●同步抑制50 Hz和60 Hz●内部时钟晶振●片内参考电源●可编程电流源（10µA、200µA 或1mA）●片上偏置电压发生器●100nA的耗尽电流●低功耗开关●AVDD和DVDD独立●24脚TSSOP封装●三线串行传输●与SPI、QSPI、MICROWIRE及DSP兼容●SCLK为施密特触发使用AD7794时还应注意它的一些极限参数，下面在表1中给出一些AD7794对工作电压和温度等条件的极限范围，在使用AD7794时一定要让其在规定的条件下工作，如果超出这些极限条件就有可能会造成芯片永久性的损坏。
AD7715资料
1. The AD7715 consumes less than 450␣ µA in total supply current at 3 V supplies and 1␣ MHz master clock, making it ideal for use in low-power systems. Standby current is less than 10␣ µA. 2. The programmable gain input allows the AD7715 to accept input signals directly from a strain gage or transducer removing a considerable amount of signal conditioning. 3. The AD7715 is ideal for microcontroller or DSP processor applications with a three-wire serial interface reducing the number of interconnect lines and reducing the number of opto-couplers required in isolated systems. The part contains on-chip registers which allow software control over output update rate, input gain, signal polarity and calibration modes. 4. The part features excellent static performance specifications with 16-bits no missing codes, ± 0.0015% accuracy and low rms noise (<550␣ nV). Endpoint errors and the effects of temperature drift are eliminated by on-chip calibration options, which remove zero-scale and full-scale errors.
AD779资料
元器件交易网
a
FEATURES AC and DC Characterized and Specified (K, B, T
Grades) 128k Conversions per Second 1 MHz Full Power Bandwidth 500 kHz Full Linear Bandwidth 80 dB S/N+D (K, B, T Grades) Twos Complement Data Format (Bipolar Mode) Straight Binary Data Format (Unipolar Mode) 10 M⍀ Input Impedance 16-Bit Bus Interface (See AD679 for 8-Bit Interface) Onboard Reference and Clock 10 V Unipolar or Bipolar Input Range MIL-STD-883 Compliant Versions Available
2. SPECIFICATIONS: The AD779K, B and T grades provide fully specified and tested ac and dc parameters. The AD779J, A and S grades are specified and tested for ac parameters; dc accuracy specifications are shown as typicals. DC specifications (such as INL, gain and offset) are important in control and measurement applications. AC specifications (such as S/N+D ratio, THD and IMD) are of value in signal processing applications.
Ad7792和AD7793
AD7792来至Analog Device公司（自报家门）。
一、AD7792基础AD7792是一款AD转换芯片，负责采集模拟数据，并与主控芯片完成数据传输。
——位数：16位——数据输入模式：差分（AINX+, AINX-）——参考电压：外部电阻或外部输入(REFIN+, REFIN)——工作电压：2.7V—5.25V （适合3.3V和5V工作电压的单片机）——传输方式：三线式串行接口（CS, SCLK, DIN, DOUT）特色：——拥有恒流源（IOUT1, IOUT2）：电流输出，10uA, 210uA, 1mA——数字接口电源（DVDD）：该管脚与AVDD无关，串行接口引脚的逻辑电平与该电源有关。
管脚定义：庖丁解牛以后，芯片只剩下2和15两个管脚还未分析。
不用着急，休息，休息一会。
这是一款独立的芯片,需要起搏的心脏，CLK就是外界提供的时钟的入口，然而芯片集成了内部时钟，可以不使用此管脚。
但是芯片的设计不会留根阑尾，当多个AD芯片同步转换时，需要同一时钟驱动来实现，时钟的入口就是2这个管脚了。
AD转换一个重要的步骤是等待转化完成。
当管脚的电平为低时，表示已完成转换，准备读取数据。
由15管脚的第二功能负责。
二、芯片配置至此，芯片的基本概念介绍完成，需要深入了解，请大胆往下瞅。
LOOK, COME ON.芯片结构中有通道选择，增益等部分。
此类芯片工作套路就是先配置芯片，后开始命令，最后读取结果，如是而已。
各个寄存器功能：通信寄存器(8位)：老大，指定配置哪一寄存器，读还是写。
状态寄存器(8位)：芯片转换结束标志。
ADC转换时的通道号。
模式寄存器(16位)：工作模式。
芯片时钟的选择。
滤波器更新速率。
配置寄存器(16位)：单极限or双极限。
通道选择。
增益放大倍数。
数字寄存器(16位)：AD转换结果。
ID寄存器(8位)：识别号。
IO寄存器(8位)：恒流源电流流出口。
电流大小。
失调寄存器，满量程寄存器：休息中。
EVAL-AD7797EBZ资料
Low Power, 16-/24-Bit Sigma-Delta ADCfor Bridge SensorsAD7796/AD7797Rev. AInformation furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.FEATURESRMS noise: 65 nV Instrumentation amp Temperature sensor Internal clock oscillatorSimultaneous 50 Hz/60 Hz rejection Update rate: 4.17 Hz to 123 Hz Current: 250 μA typ Power-down: 1 μAPower supply: 2.7 V to 5.25 V–40°C to +85°C temperature range Independent interface power supply 16-lead TSSOPINTERFACE3-wire serialSPI®, QSPI™, MICROWIRE™, and DSP compatible Schmitt trigger on SCLKAPPLICATIONSWeigh scales Strain gagesIndustrial process control InstrumentationPortable instrumentationGENERAL DESCRIPTIONThe AD7796/AD7797 are complete, analog front ends for high precision, bridge sensor applications such as weigh scales. The AD7796/AD7797 contain a Σ-Δ ADC capable of 16-/24-bit resolution, respectively. The on-chip instrumentation amplifier has a fixed gain of 128, allowing small amplitude signals such as those from bridge sensors to be directly interfaced to the ADC. Each part has one differential input and contains a temperature sensor that is internally connected to the ADC. This sensor can be used to perform temperature compensation of the bridge. The devices can be operated with the internal clock or an external clock. The output data rate from the parts is software-programmable and can be varied from 4.17 Hz to 123 Hz. The AD7796/AD7797 operate with a power supply from 2.7 V to 5.25 V . Each part consumes a current of 250 μA typical and is housed in a 16-lead TSSOP .FUNCTIONAL BLOCK DIAGRAMDOUT/RDY AIN(+)AIN(–)AV 06083-001Figure 1.AD7796/AD7797Rev. A | Page 2 of 24TABLE OF CONTENTSFeatures..............................................................................................1 Interface.............................................................................................1 Applications.......................................................................................1 General Description.........................................................................1 Functional Block Diagram..............................................................1 Revision History...............................................................................2 Specifications.....................................................................................3 Timing Characteristics.....................................................................5 Timing Diagrams..........................................................................6 Absolute Maximum Ratings............................................................7 Thermal Resistance......................................................................7 ESD Caution..................................................................................7 Pin Configuration and Function Descriptions.............................8 RMS Noise and Resolution Specifications....................................9 Typical Performance Characteristics...........................................10 On-Chip Registers..........................................................................11 Communication Register..........................................................11 Status Register.............................................................................12 Mode Register.............................................................................12 Configuration Register..............................................................14 Data Register...............................................................................14 ID Register...................................................................................14 Offset Register............................................................................15 Full-Scale Register......................................................................15 ADC Circuit Information..............................................................16 Overview.....................................................................................16 Digital Interface..........................................................................17 Circuit Description.........................................................................20 Analog Input Channel...............................................................20 Bipolar/Unipolar Configuration..............................................20 Data Output Coding..................................................................20 Reference.....................................................................................20 Reset.............................................................................................21 Burnout Currents.......................................................................21 AV DD Monitor.............................................................................21 Temperature Monitor................................................................21 Calibration...................................................................................21 Grounding and Layout..............................................................22 Applications.....................................................................................23 Weigh Scales................................................................................23 Outline Dimensions.......................................................................24 Ordering Guide.. (24)REVISION HISTORY8/06—Rev. 0 to Rev. A.Changes to Table 1............................................................................3 Changes to Figure 5..........................................................................8 Changes to Table 14 (13)7/06—Revision 0: Initial VersionAD7796/AD7797Rev. A | Page 3 of 24SPECIFICATIONSAV DD = 2.7 V to 5.25 V , DV DD = 2.7 V to 5.25 V , GND = 0 V , all specifications T MIN to T MAX , unless otherwise noted. Table 1.Parameter AD7796B/AD7797B 1 Unit Test Conditions/Comments ADC CHANNEL Output Update Rate 4.17 to 123 Hz nomNo Missing Codes 224 Bits min AD7797 only 16 Bits min AD7796 only Resolution See Table 7 and Table 8 RMS Noise and Update Rates See Table 6 Integral Nonlinearity ±10 ppm of FSR typOffset Error 3, 4±1 μV typ Offset Error Drift vs. Temperature 4±10 nV/°C typFull-Scale Error 3, 4, 5±10 μV typ Gain Drift vs. Temperature 4±3 ppm/°C typ Power Supply Rejection 90 dB min AIN = 1 V/128 ANALOG INPUTS Differential Input Voltage Ranges ±V REF /128 V nom V REF = REFIN(+) – REFIN(–)Absolute AIN Voltage Limits 2GND + 300 mV V min AV DD − 1.1 V max Common-Mode Voltage, V CM 0.5 V min V CM = (AIN(+) + AIN(–))/2 Analog Input CurrentAverage Input Current 2±250 pA max Update rate < 100 Hz Average Input Current Drift ±2 pA/°C typ Normal Mode Rejection 2 Internal Clock @ 50 Hz, 60 Hz 65 dB min 80 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 10106@ 50 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, FS[3:0] = 10016@ 60 Hz 90 dB min 100 dB typ, 60 ± 1 Hz, FS[3:0] = 10006External Clock @ 50 Hz, 60 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 10106@ 50 Hz 94 dB min 100 dB typ, 50 ± 1 Hz, FS[3:0] = 10016@ 60 Hz 90 dB min 100 dB typ, 60 ± 1 Hz, FS[3:0] = 10006Common-Mode Rejection @ DC 90 dB min AIN = 7.81 mV @ 50 Hz, 60 Hz 290 dB min 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 10106@ 50 Hz, 60 Hz 290 dB min 50 ± 1 Hz (FS[3:0] = 10016), 60 ± 1 Hz,FS[3:0] = 10006REFERENCE External REFIN Voltage 2.5 V nom REFIN = REFIN(+) – REFIN(–)Reference Voltage Range 20.1 V min AV DD V maxAbsolute REFIN Voltage Limits 2GND − 30 mV V min AV DD + 30 mV V max Average Reference Input Current 400 nA/V typ Average Reference Input Current Drift ±0.03 nA/V/°C typ Normal Mode Rejection Same as for analog inputs Common-Mode Rejection 100 dB typ TEMPERATURE SENSOR Accuracy ±2 °C typ Applies if user calibrates the temperature sensor Sensitivity 0.81 mV/°C typAD7796/AD77971 Temperature range is –40°C to +85°C.2 Specification is not production tested, but is supported by characterization data at initial product release.3 Following a calibration, this error is in the order of the noise for the update rate selected.4 Recalibration at any temperature removes these errors.5 Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (AV DD = 4 V, T A = 25°C).6 FS[3:0] are the four bits used in the mode register to select the output word rate.7 Digital inputs equal to DV DD or GND.Rev. A | Page 4 of 24AD7796/AD7797Rev. A | Page 5 of 24TIMING CHARACTERISTICSAV DD = 2.7 V to 5.25 V , DV DD = 2.7 V to 5.25 V , GND = 0 V , Input Logic 0 = 0 V , Input Logic 1 = DV DD , unless otherwise noted.1 Sample tested during initial release to ensure compliance. All input signals are specified with t R = t F = 5 ns (10% to 90% of DV DD ) and timed from a voltage level of 1.6 V. 2See Figure 3 and Figure 4. 3These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the V OL or V OH limits. 4SCLK active edge is falling edge of SCLK. 5These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the parts and, as such, are independent of external bus loading capacitances. 6 RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high. Care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read only once.WITH DV DD =5V,DV DD =3V)WITH DV DD =5V,DV DD =3V)1.6VTO OUTPUTPIN06083-002Figure 2. Load Circuit for Timing CharacterizationAD7796/AD7797Rev. A | Page 6 of 24TIMING DIAGRAMSCS SCLK I = INPUT, O= OUTPUT06083-003Figure 3. Read Cycle Timing DiagramI = INPUTCS (I)SCLK (I)DIN (I)06083-004Figure 4. Write Cycle Timing DiagramAD7796/AD7797Rev. A | Page 7 of 24ABSOLUTE MAXIMUM RATINGST A = 25°C, unless otherwise noted. Table 3.Parameter RatingAV DD to GND −0.3 V to +7 V DV DD to GND−0.3 V to +7 VAnalog Input Voltage to GND −0.3 V to AV DD + 0.3 V Reference Input Voltage to GND −0.3 V to AV DD + 0.3 V Digital Input Voltage to GND −0.3 V to DV DD + 0.3 V Digital Output Voltage to GND −0.3 V to DV DD + 0.3 V AIN/Digital Input Current10 mAOperating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C Lead Temperature, SolderingVapor Phase (60 sec) 215°C Infrared (15 sec)220°CStresses above those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCEθJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4.Package Type θJA θJC Unit TSSOP 128 14 °C/WESD CAUTIONAD7796/AD7797Rev. A | Page 8 of 24PIN CONFIGURATION AND FUNCTION DESCRIPTIONSNC =NO CONNECT06083-005Figure 5. Pin ConfigurationAD7796/AD7797Rev. A | Page 9 of 24RMS NOISE AND RESOLUTION SPECIFICATIONSTable 6 shows the rms noise of the AD7796/AD7797 for some of the update rates. The numbers given are for the bipolar input range with an external 2.5 V reference. These numbers aretypical and are generated with a differential input voltage of 0 V . Table 7 and Table 8 show the effective resolution, while the output peak-to-peak (p-p) resolution is shown in brackets. It is important to note that the effective resolution is calculatedusing the rms noise, while the p-p resolution is based on the p-p noise. The p-p resolution represents the resolution for which there is no code flicker. These numbers are typical and are rounded to the nearest 0.5 LSB.Table 6. RMS Noise (μV) vs. Output Update Rate for the AD7796/AD7797 Using a 2.5 V ReferenceUpdate Rate (Hz) RMS Noise (μV) 4.17 0.065 6.25 0.07 8.33 0.08 10 0.09 12.5 0.1 16.7 0.12 33.2 0.17 50 0.21 62 0.23 1230.43Table 7. Typical Resolution (Bits) vs. Output Update Rate for the AD7797 Using a 2.5 V ReferenceUpdate Rate (Hz) Effective Bits (p-p) 4.17 19 (16.5) 6.25 19 (16.5) 8.33 19 (16) 10 18.5 (16) 12.5 18.5 (16) 16.7 18.5 (15.5) 33.2 18 (15) 50 17.5 (15) 62 17.5 (14.5) 12316.5 (13.5)Table 8. Typical Resolution (Bits) vs. Output Update Rate for the AD7796 Using a 2.5 V ReferenceUpdate Rate (Hz) Effective Bits (p-p) 4.17 16 (16) 6.25 16 (16) 8.33 16 (16) 10 16 (16) 12.5 16 (16) 16.7 16 (15.5) 33.2 16 (15) 50 16 (15) 62 16 (14.5) 12316 (13.5)AD7796/AD7797Rev. A | Page 10 of 24SAMPLES(µV )TYPICAL PERFORMANCE CHARACTERISTICS60–4001000 2.0–2.001000SAMPLES(µV )40200–2010020030040050060070080090006083-006Figure 6. AD7797 Noise (V REF = AV DD , Update Rate = 16.7 Hz)17.5083884858388744CODEO C C U R R E N C E15.012.510.07.55.02.5838855083886008388650838870006083-007Figure 7. AD7797 Noise Distribution Histogram(V REF = AV DD , Update Rate = 16.7 Hz) 1002003004005006007008009001.51.00.50–0.5–1.0–1.506083-008Figure 8. AD7797 Noise (V REF = AV DD , Update Rate = 4.17 Hz)35083885538388662CODEO C C U R R E N C E83885808388600838862083886403025201510506083-009Figure 9. AD7797 Noise Distribution Histogram(V REF = AV DD , Update Rate = 4.17 Hz)ON-CHIP REGISTERSThe ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following descriptions, set implies a Logic 1 State and cleared implies a Logic 0 State, unless otherwise stated. COMMUNICATION REGISTERRS2, RS1, RS0 = 0, 0, 0The communication register is an 8-bit write-only register. All communication to the part must start with a write operation to this register. The data written to the communication register determines whether the next operation is a read or write opera-tion, and selects the register where this operation takes place. Once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the communication register (this is the default state of the interface). On power-up or after a reset, the ADC is in this default state waiting for a write operation to the communication register. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high returns the ADC to this default state by resetting the entire part. Table 9 outlines the bit designations for the communication register. CR0 through CR7 indicate the bit location, with CR denoting that the bits are in the communication register. CR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.Table 10. Register SelectionRS2 RS1 RS0 Register Register Size0 0 0 Communication Register During a Write Operation 8 bits0 0 0 Status Register During a Read Operation 8 bits0 0 1 Mode Register 16 bits0 1 0 Configuration Register 16 bits0 1 1 Data Register 16 bits (AD7796), 24 bits (AD7797)1 0 0 ID Register 8 bits1 0 1 Reserved 8 bits1 1 0 Offset Register 16 bits (AD7796), 24 bits (AD7797) 1 1 1 Full-Scale Register 16 bits (AD7796), 24 bits (AD7797)Rev. A | Page 11 of 24STATUS REGISTERRS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communication register, select the next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 11 outlines the bit designations for the status register. SR0 through SR7 indicate the bit locations, with SR denoting that the bits are in the status register. SR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.MODE REGISTERRS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x000AThe mode register is a 16-bit read/write register. This register is used to select the operating mode, update rate, and clock source. Table 12 outlines the bit designations for this register. MR0 through MR15 indicate the bit locations, with MR denoting that the bits are in the mode register. MR15 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. Any write to the setup register resets the modulator and filter, and sets the RDY bit.MSB LSB MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 MD2(0) MD1(0) MD0(0) 0(0) 0(0) 0(0) 0(0) 0(0) CLK1(0) CLK0(0) 0(0) 0(0) FS3(1) FS2(0) FS1(1) FS0(0)Table 12. Mode Register Bit DesignationsBit Location Bit Name DescriptionMR15 to MR13 MD2 to MD0 Mode Select Bits. These bits select the operational mode of the AD7796/AD7797 (see Table 13).MR12 to MR8 0 These bits must be programmed with a Logic 0 for correct operation.MR7 to MR6 CLK1 to CLK0 These bits are used to select the clock source for the AD7796/AD7797. Either an on-chip 64 kHz clockor an external clock can be used. The ability to override using an external clock allows several AD7796/AD7797 devices to be synchronized. In addition, 50 Hz/60 Hz rejection is improved when an accurateexternal clock drives the AD7796/AD7797.CLK1 CLK0 ADC Clock Source0 0 Internal 64 kHz Clock. Internal clock is not available at the CLK pin.0 1 Internal 64 kHz Clock. This clock is made available at the CLK pin.1 0 External 64 kHz Clock Used. An external clock gives better 50 Hz/60 Hz rejection.See Table 1 for the external clock specifications.1 1 External Clock Used. The external clock is divided by2 within the AD7796/AD7797. MR5 to MR4 0 These bits must be programmed with a Logic 0 for correct operation.MR3 to MR0 FS3 to FS0 Filter Update Rate Select Bits (see Table 14).Rev. A | Page 12 of 24Table 14. Update Rates AvailableFS3 FS2 FS1 FS0 f ADC (Hz) t SETTLE (ms) Rejection @ 50 Hz/60 Hz (Internal Clock) 0 0 0 0 X X0 0 0 1 X X0 0 1 0 X X0 0 1 1 123 160 1 0 0 62 320 1 0 1 50 400 1 1 0 X X0 1 1 1 33.2 601 0 0 0 X X1 0 0 1 16.7 120 80 dB (50 Hz only)1 0 1 0 16.7 120 65 dB (50 Hz and 60 Hz)1 0 1 1 12.5 160 66 dB (50 Hz and 60 Hz)1 1 0 0 10 200 69 dB (50 Hz and 60 Hz)1 1 0 1 8.33 240 70 dB (50 Hz and 60 Hz)1 1 1 0 6.25 320 72 dB (50 Hz and 60 Hz)1 1 1 1 4.17 480 74 dB (50 Hz and 60 Hz)Rev. A | Page 13 of 24CONFIGURATION REGISTERRS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x0710The configuration register is a 16-bit read/write register. This register is used to configure the ADC for unipolar or bipolar mode, enable or disable the burnout currents, and select the analog input channel. Table 15 outlines the bit designations for the configuration register. CON0 through CON15 indicate the bit locations, with CON denoting that the bits are in the configuration register. CON15 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.DATA REGISTERRS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x0000 (AD7796)/0x000000 (AD7797)The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from this register, the RDY bit/pin is set.ID REGISTERRS2, RS1, RS0 = 1, 0, 0; Power-On/Reset = 0x5A (AD7796)/0x5B (AD7797)The identification number for the AD7796/AD7797 is stored in the ID register. This is a read-only register.Rev. A | Page 14 of 24OFFSET REGISTERRS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x8000 (AD7796)/0x800000 (AD7797)The analog input channel has an offset register that holds the offset calibration coefficient for the channel. This register is 16 bits wide on the AD7796 and 24 bits wide on the AD7797, and its power-on/reset value is 0x8000(00). The offset register is used in conjunction with the full-scale register to form a register pair. The power-on/reset value is automatically overwritten if an internal or system zero-scale calibration is initiated by the user. The offset register is a read/write register. However, the AD7796/AD7797 must be in idle mode or power-down mode when writing to this register.FULL-SCALE REGISTERRS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXX (AD7796)/0x5XXX00 (AD7797)The full-scale register is a 16-bit register on the AD7796 and a 24-bit register on the AD7797. The full-scale register holds the full-scale calibration coefficient for the ADC. The full-scale register is a read/write register. However, when writing to the full-scale register, the ADC must be placed in power-down mode or idle mode. The full-scale register is configured on power-on with the factory-calibrated full-scale calibration coefficient. Therefore, every device has a different default coefficient. The default value is automatically overwritten if a system full-scale calibration is initiated by the user, or if the full-scale register is written to.Rev. A | Page 15 of 24Rev. A | Page 16 of 24ADC CIRCUIT INFORMATIONOVERVIEWThe AD7796/AD7797 are low power ADCs that incorporate a Σ-Δ modulator, in-amp, and an on-chip digital filter intended for measuring wide dynamic range, low frequency signals, such as those in pressure transducers and weigh scales.Each part has one differential input that is buffered. Figure 10 shows the basic connections required to operate the part.DOUT/RDY06083-010Figure 10. Basic Connection DiagramThe output rate of the AD7796/AD7797 (f ADC ) is user-programmable. The allowable update rates, along with the corresponding settling times, are listed in Table 14. Normal mode rejection is the major function of the digital filter.Simultaneous 50 Hz and 60 Hz rejection is optimized when the update rate equals 16.7 Hz or less because notches are placed at both 50 Hz and 60 Hz with these update rates (see Figure 12). The AD7796/AD7797 use slightly different filter types, depending on the output update rate used to optimize the rejection of quantization noise and device noise. When the update rate is 4.17 Hz to 12.5 Hz, a Sinc 3 filter and an averaging filter are used. When the update rate is 16.7 Hz to 33.2 Hz, a modified Sinc 3 filter is used. This filter gives simultaneous 50 Hz/60 Hz rejection when the update rate equals 16.7 Hz. A Sinc 4 filter is used when the update rate is from 50 Hz to 123 Hz. Figure 11 to Figure 13 show the frequency response of the different filter types for some of the update rates.–20–40–60–80–1000110080604020FREQUENCY (Hz)(d B )2006083-011Figure 11. Filter Profile with Update Rate = 4.17 Hz–20–40–60–80–100218016014012010080604020FREQUENCY (Hz)(d B )0006083-012Figure 12. Filter Profile with Update Rate = 16.7 Hz–20–40–60–80–10001000900800700600500400300200100FREQUENCY (Hz)(d B )06083-013Figure 13. Filter Profile with Update Rate = 50 HzDIGITAL INTERFACEAs outlined in the On-Chip Registers section, the AD7796/AD7797 programmable functions are controlled by a set of on-chip registers. Data is written to these registers via the part’s serial interface and read access to the on-chip registers is also provided by this interface. All communication with the part must start with a write to the communication register. After power-on or reset, the device expects a write to its communication register. The data written to this register determines whether the next operation is a read or a write operation, and determines the register where this operation occurs. Therefore, write access to any of the other registers on the part begins with a write operation to the communication register followed by a write to the selected register. A read operation from any other register (except when continuous read mode is selected) starts with a write to the communication register followed by a read operation from the selected register. The serial interface of the AD7796/AD7797 consists of four signals: CS, DIN, SCLK, and DOUT/RDY. The DIN line is used to transfer data into the on-chip registers, while DOUT/RDY is used for accessing from the on-chip registers. SCLK is the serial clock input for the device, and all data transfers (either on DIN or DOUT/RDY) occur with respect to the SCLK signal. The DOUT/RDY pin also operates as a data-ready signal, that is, the line goes low when a new data-word is available in the output register. It is reset high when a read operation from the data register is complete. DOUT/RDY also goes high prior to the data register update to indicate when not to read from the device. This ensures that a data read is not attempted while the register is being updated. CS is used to select a device. It can be used to decode the AD7796/AD7797 in systems where several components are connected to the serial bus.Figure 3 and Figure 4 show timing diagrams for interfacing to the AD7796/AD7797 with CS being used to decode the part. Figure 3 shows the timing for a read operation from theAD7796/AD7797 output shift register, while Figure 4 shows the timing for a write operation to the input shift register. It is possible to read the same word from the data register several times, even though the DOUT/RDY line returns high after the first read operation. However, care must be taken to ensure that the read operations have been completed before the next output update occurs. In continuous read mode, the data register can be read only once.The serial interface can operate in 3-wire mode by tying CS low. In this case, the SCLK, DIN, and DOUT/RDY lines are usedto communicate with the AD7796/AD7797. The end of the conversion can be monitored using the RDY bit in the status register. This scheme is suitable for interfacing to micro-controllers. If CS is required as a decoding signal, it can be generated from a port pin. For microcontroller interfaces, it is recommended that SCLK idle high between data transfers. The AD7796/AD7797 can be operated with CS being used as a frame synchronization signal. This scheme is useful for DSP interfaces. In this case, the first bit (MSB) is effectively clocked out by CS because CS normally occurs after the falling edge of SCLK in DSPs. The SCLK can continue to run between data transfers, provided the timing numbers are obeyed.The serial interface can be reset by writing a series of 1s on the DIN input. If a Logic 1 is written to the AD7796/AD7797 DIN line for at least 32 serial clock cycles, the serial interface is reset. This ensures that the interface can be reset to a known state if the interface gets lost due to a software error or glitch in the system. Reset returns the interface to the state where it is expecting a write to the communication register. This operation resets the contents of all registers to their power-on values. Following a reset, the user should allow a period of 500 μs before addressing the serial interface.The AD7796/AD7797 can be configured to continuously convert or to perform a single conversion. See Figure 14 through Figure 16.Rev. A | Page 17 of 24。
EVAL-AD7798EB资料
Evaluation Board for the AD7798,16-Bit Low Power Σ−∆ ADC (3 Channels) Preliminary Technical Data EVAL-AD7798EBRev.Pr AInformation furnished by Analog Devices is believed to be accurate and reliable.However, no responsibility is assumed by Analog Devices for its use, nor for anyinfringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: Fax: 781.326.8703© 2004 Analog Devices, Inc. All rights reserved.FEATURESFull-Featured Evaluation Board for the AD7798Stand alone USB InterfaceVarious Linking OptionsPC Software for Control of AD7798INTRODUCTIONThis Technical Note describes the evaluation board for theAD7798 which is a Low Power, 16-Bit Sigma Delta ADC. The AD7798 is a complete analog front end for low frequency measurement applications. It contains three differential inputs and includes a low noise instrumentation amplifier, reference detect and a low side power switch. The update rate can be varied from 4.17 Hz to 500 Hz. It also has an on-board clock, eliminating the need for an external clock. It employs a sigma-delta conversion technique to realize up to 16 bits of no missing codes performance. The input signal is applied to an analog modulator. The modulator output is processed by an on-chip digital filter. The analog input channel of the AD7798 accepts analog input signals of +V REF/Gain, with Gain equal to 1 to 128. With a gain of 64 and the update rate programmed to 16.7 Hz, the rms noise is 65 nV. Simultaneous 50 Hz/ 60 Hz rejection is available at this data update rate also. Full data on the AD7798 is available in the AD7798 datasheet available from Analog Devices and should be consulted in conjunction with this Technical Note when using the evaluation board.The evaluation board interfaces to the USB port of an IBM compatible PC. Software is available with the evaluation board which allows the user to easily communicate with the AD7798. N.B.!! The AD7798 Evaluation Board Software should be installed BEFORE connecting the AD7798 Evaluation board to the PC.Other components on the AD7798 Evaluation Board include the ADP3303 which is a high precision, low power, 3.3V output, voltage regulator, which is used to power the USB/SPI interface . OPERATING THE AD7798 EVALUATION BOARDPower SuppliesThe board is powered via the 5V supply from the USB connector, J1. This 5V supply may be used to power theAD7798 directly or a 3.3V Regulated voltage from the on board ADP3303, high precision, low power, 3.3V output, voltage regulator may also be used. Alternatively, the AD7798 may be powered using an external 3V or 5V power supply via J3.FUNCTIONAL BLOCK DIAGRAMFigure 1. Functional Block DiagramEVAL-AD7798EBPreliminary Technical DataRev. Pr A | Page 2There are ten link options which must be set for the required operating setup before using the evaluation board. The functions of these link options are outlined below. Table 1.Evaluation Board Link SettingsSET-UP CONDITIONSCare should be taken before applying power and signals to the evaluation board to ensure that all link positions are as per the required operating mode. Table 1 shows the position in which all the links are set when the evaluation board is sent out.Table 2: Initial Link and Switch Positions Link No. Position FunctionLK1 - LK2 In AIN1(+) and AIN1(-) are shorted to the reference voltage LK3 – LK6 Out The demonstration circuit is disconnected from the AD7798 LK7 – LK8 In The reference voltage is set to 1.65V (3.3V/2) LK9 B The 3.3V supply is used as AV DD for the AD7798. LK10InLED D2 is connected to the Low Side Power Switch of the AD7798EVALUATION BOARD INTERFACINGInterfacing to the evaluation board is via a standard USB Connector, J1. J1 is used to connect the evaluation board to the USB port of a PC. A standard USB connector cable is included with the AD7798 evaluation board to allow the evaluation board to interface with the PC's USB port. As the board is powered via the USB connector, there is no need for an external power supply, although one may be connected if preferred via J3.Communication between the AD7798 and the PC is over the USB/SPI interface. The onboard USB controller (U2) controls thiscommunication. Remember, the AD7798 Evaluation Board Software should be installed (using the supplied AD7798 Evaluation Board CD ROM) BEFORE connecting the board to the PC.Link Default Description LK1, LK2 In These links are used to connect the AIN1(+) and AIN1(-) inputs to a reference voltage whichequals AV DD /2. With this configuration, a noise analysis can be performed. With these linksremoved, an external voltage may be applied to AIN1 using the SMB connectors.LK3, LK4, LK5, LK6OutThese links are used to connect the on board temperature demonstration circuit to the ADC, and must all be in place when attempting to measure ambient temperature.When LK3 and LK4 are inserted, the 1K Ω thermistor is connected to AIN2. With LK5 and LK6 in place, a 5K Ω precision resistor is used to generate the reference. This results in a ratiometric configuration.LK7, LK8 InA resistor divider network generates a voltage equal to AV DD /2 which can be used as the reference for the AD77998 With LK7 and LK8 in place, AV DD /2 is connected to REFIN(+) and REFIN(-) is connected to GND. To use another reference source, remove LK7 and LK8. LK9B LK9 is used to select the power source for AV DD on the AD7798. LK9 in position A selects anexternal power supply, supplied via J3. LK9 in position B selects the 3.3V regulated output from the onboard ADP3303 voltage regulator. LK9 in position C selects the 5V supply from the USB connector, J1.LK10 In LK10 is used to test the on chip low side power switch. With LK10 in place, enabling the low-side power switch in software by setting a bit in the configuration register turns on the LED, D2Clearing this bit turns off the LED.Preliminary Technical DataEVAL-AD7798EBRev. Pr A | Page 3After the AD7798 Evaluation Board Software has been installed, connect the board to the PC via J1 on the AD7798 Evaluation Board and the USB port on the PC using the supplied USB connector cable. The PC will automatically find the new USB device and will identify it as: AD7798 Evaluation Board. Follow the onscreen instructions that appear automatically. During the installation process if the following window appears:.Hit Continue Anyway in order to successfully complete the installation of the AD7798 Evaluation Board. SOCKETSThere are five sockets relevant to the operation of the AD7798 on this evaluation board. The functions of these sockets are outlined in Table 3.Table 3. Socket FunctionsSock t Function AIN1+ Sub-Miniature BNC (SMB) Connector. The analog input signal for the AIN1(+) input of the AD7798 isapplied to this socket.AIN1- Sub-Miniature BNC (SMB) Connector. The analog input signal for the AIN1(-) input of the AD7798 is applied to this socket.REFIN+Sub-Miniature BNC (SMB) Connector. This socket is used in conjunction with REFIN(-) to apply an external reference to the AD7798. The voltage for the REFIN(+) input of the AD7798 is applied to this socket.REFIN-Sub-Miniature BNC (SMB) Connector. This socket is used in conjunction with REFIN(+) to apply an external reference to the AD7798.The voltage for the REFIN(-) input of the AD7798 is applied to this socket.J234 Pin (2x16) pin Straight Heade r. This Socket is used in conjunction with the prototype area to interfaceany signal to the AD7798. It is specifically designed as a socket for a 34 pin header.。
半导体传感器AD7792BRUZ中文规格书
AD7741–SPECIFICATIONS(V DD = +4.75 V to +5.25 V; V REF = +2.5 V; f CLKIN = 6.144 MHz; all specifications T MIN toT MAX unless otherwise noted.)B and Y Version1Parameter2Min Typ Max Units Conditions/CommentsDC PERFORMANCEIntegral Nonlinearityf CLKIN = 200 kHz3±0.012% of Span4f CLKIN = 3 MHz3±0.012% of Spanf CLKIN = 6.144 MHz±0.024% of Span V DD > 4.8 VOffset Error±40mVGain Error0+0.8+1.6% of SpanOffset Error Drift3±30μV/°CGain Error Drift3±16ppm of Span/°CPower Supply Rejection Ratio3–63dBΔV DD = ±5%ANALOG INPUT5Input Current±50±100nAInput Voltage Range0V REF V+2.5 V REFERENCE (REFIN/OUT)REFINNominal Input Voltage 2.5VInput Impedance6N/AREFOUTOutput Voltage 2.38 2.50 2.60VOutput Impedance31kΩReference Drift3±50ppm/°CLine Rejection–60dBReference Noise (0.1 Hz to 10 Hz)3100μV p-pLOGIC OUTPUTOutput High Voltage, V OH 4.0V Output Sourcing 800 μA7Output Low Voltage, V OL0.4V Output Sinking 1.6 mA7 Minimum Output Frequency0.05 f CLKIN Hz V IN = 0 VMaximum Output Frequency0.45 f CLKIN Hz V IN = V REFLOGIC INPUTPD ONLYInput High Voltage, V IH 2.4VInput Low Voltage, V IL0.8VInput Current±100nAPin Capacitance610pFCLKIN ONLYInput High Voltage, V IH 3.5VInput Low Voltage, V IL0.8VInput Current±2μAPin Capacitance610pFCLOCK FREQUENCYInput Frequency 6.144MHz For Specified Performance POWER REQUIREMENTSV DD 4.75 5.25VI DD (Normal Mode)8mA Output UnloadedI DD (Power-Down)1535μAPower-Up Time330μs Coming Out of Power-Down ModeNOTES1Temperature ranges: B Version –40°C to +85°C: Y Version: –40°C to +105°C.2See Terminology.3Guaranteed by design and characterization, not production tested.4Span = Maximum Output Frequency–Minimum Output Frequency.5The absolute voltage on the input pin must not go more positive than VDD – 2.25 V or more negative than GND.6Because this pin is bidirectional, any external reference must be capable of sinking/sourcing 400 μA in order to overdrive the internal reference.7These logic levels apply to CLKOUT only when it is loaded with one CMOS load.Specifications subject to change without notice.REV. A–2–REV. AAD7741–6–AD7742 PIN FUNCTION DESCRIPTION Pin No.Mnemonic Function 1f OUT Frequency Output. This pin provides the output of the synchronous VFC.2VDD Power Supply Input. These parts can be operated from +4.75 V to +5.25 V and the supply should be adequately decoupled to GND.3GND Ground reference point for all circuitry on the part.4–5A1, A0Address Inputs used to select the input channel configuration.6CLKOUT External Clock Output. When the master clock for the device is a crystal, the crystal is connected be-tween CLKIN and CLKOUT. When an external clock is applied to CLKIN, the CLKOUT pinprovides an inverted clock signal. This clock should be buffered if it is to be used as a clock sourceelsewhere in the system.7CLKIN External Clock Input. The master clock for the device can be provided in the form of a crystal or anexternal clock. A crystal may be tied across the CLKIN and CLKOUT pins. Alternatively, the CLKINpin may be driven by a CMOS-compatible clock and CLKOUT left unconnected. The frequency of themaster clock may be as high as 6 MHz.8UNI/BIP Control input which determines whether the device operates with differential bipolar analog inputsignals or differential unipolar analog input signals.9REFOUT 2.5 V Voltage Reference Output. This can be tied directly to REFIN. It may also be used as a referenceto other parts of the system provided it is buffered first.10REFIN This is the Reference Input to the core of the VFC and defines the span of the VFC. A 2.5 V referenceis required at this pin. This may be provided by connecting it directly to REFOUT or by using a preci-sion external reference (e.g., REF192).11V IN 1Buffered Analog Input Channel 1. This is either a pseudo-differential input with respect to V IN 4 or it isthe positive input of a truly-differential input pair with respect to V IN 2.12V IN 2Buffered Analog Input Channel 2. This is either a pseudo-differential input with respect to V IN 4 or it isthe negative input of a truly-differential input pair with respect to V IN 1.13V IN 3Buffered Analog Input Channel 3. This is the positive input of a truly-differential input pair with re-spect to V IN 4.14V IN 4Buffered Analog Input Channel 4. This is either the common for pseudo-differential input with respectto V IN 1 or V IN 2 or it is the negative input of a truly-differential input pair with respect to V IN 3.15GAIN Gain Select input that controls whether the gain on the analog front-end is X1 or X2.16PDActive Low Power-Down pin. When this input is low, the part enters power-down mode where it typi-cally consumes 25 μA of current.PIN CONFIGURATIONf OUT PD V DD GAIN GND V IN 4A1V IN 3A0V IN 2CLKOUT V IN 1CLKIN REFIN UNI/BIP REFOUT。
AD7798,AD7799调试程序电路及pdf中文资料下载
AD7798,AD7799调试程序电路及pdf中文资料下载AD7798/AD7799均为适合高精度测量应用的低功耗、低噪声、完整模拟前端,内置一个低噪声16位/24位Σ-Δ型ADC,其中含有3个差分模拟输入,还集成了片内低噪声仪表放大器,因而可直接输入小信号。
当增益设置为64、更新速率为4.17 Hz时,AD7799的均方根（RMS）噪声为27 nV,AD7798的均方根（RMS）噪声为40 nV。
AD7798/A D7799片内特性包括一个低端电源开关、基准电压检测、可编程数字输出引脚、熔断电流控制和一个内部时钟振荡器。
输出数据速率可通过软件编程设置,可在4.17 Hz至470 Hz的范围内变化。
AD7798/AD 7799采用2.7 V至5.25 V电源供电,AD7798的典型功耗为300 μA,而AD7799的典型功耗为380 μA,两款器件均采用16引脚TSSOP封装。
AD7798,AD7799芯片的特性AD7798,AD7799芯片的概述AD7798,AD7799引脚图，采用16引脚TSSOP封装。
采用2.7V 至5.25V电源供电，AD7799的典型功耗为380μA。
AD7798,AD7799管脚功能介绍AD7798,AD7799 pdf中文资料下载：/f/AD7799_ad7798中文资料.pdf经历了四天的挣扎，AD7799终于调试成功啦说说我遇到的问题一、不判忙的状态下，读出数据是ffffff解决办法：设置CONFIGURATION REGISTER 的con5为1，然后检测STA TUS REGISTER 的NOREF位是否为1，如果为1说明内部基准低于0. 5v，也就是说没有基准。
我检测到NOREF位为1，用万用表检测ref +为2.5，不是虚焊。
检测来检测去没有问题，开始怀疑芯片，网上刚好也有说这个问题的，他说是芯片基准坏啦。
我没办法重新焊了一块板子，问题依旧。
没法硬着头皮看datasheet，最后发现还是设置的事。
关于AD7705的技术文档
关于AD7705模块的技术文档一、模块描述1、简介：D7705/7706 是应用于低频测量的2/3 通道的模拟前端。
该器件可以接受直接来自传感器的低电平的输入信号，然后产生串行的数字输出。
利用Σ-∆转换技术实现了16 位无丢失代码性能。
选定的输入信号被送到一个基于模拟调制器的增益可编程专用前端。
片内数字滤波器处理调制器的输出信号。
通过片内控制寄存器可调节滤波器的截止点和输出更新速率，从而对数字滤波器的第一个陷波进行编程。
2、产品性能参数及特点：�AD7705：2 个全差分输入通道的ADC�AD7706：3 个伪差分输入通道的ADC16位无丢失代码0.003%非线性�可编程增益前端增益：1～128�三线串行接口SPITM、QSPITM、MICROWIRETM和DSP 兼容�有对模拟输入缓冲的能力�2.7～3.3V或4.75～5.25V工作电压� 3V电压时，最大功耗为1mW�等待电流的最大值为8μA�16脚DIP、SOIC和TSSOP封3、产品应用场合：AD7705/7706 是用于智能系统、微控制器系统和基于DSP 系统的理想产品。
其串行接口可配置为三线接口。
增益值、信号极性以及更新速率的选择可用串行输入口由软件来配置。
该器件还包括自校准和系统校准选项，以消除器件本身或系统的增益和偏移误差。
二、模块原理图三、引脚功能四、校准1、自校准过向设置寄存器的MD1和MD0写入相应值（0，1），器件开始自校准。
在单极性输入信号范围内，用来确定校准系数的零标度点是用差分输入对的输入端在器件内部短路（即，对于AD7705，AIN(+)=AIN(-)=内部偏置电压；对于AD7706，AIN=COMMON=内部偏置电压）。
增益可编程放大器（PGA）设置为用于零标度校准转换时选定的增益（由通信寄存器内的G1和G0位设置）。
满标度标准转换是在一个内部产生的VREF电压和选定增益的条件下完成的。
校准持续时间是6×1/输出速率。
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Evaluation Board for the AD7795 16-Bit,Low Power Sigma-Delta ADC (6 Channels)EVAL-AD7795 Rev. 0Evaluation boards are only intended for device evaluation and not for production purposes.Evaluation boards are supplied “as is” and without warranties of any kind, express, implied, orstatutory including, but not limited to, any implied warranty of merchantability or fitness for aparticular purpose. No license is granted by implication or otherwise under any patents or otherintellectual property by application or use of evaluation boards. Information furnished by AnalogDevices is believed to be accurate and reliable. However, no responsibility is assumed by AnalogDevices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Analog Devices reserves the right to change devices or specifications at any time without notice. T rademarks and registered trademarks are the property of their respective owners. Evaluation boards are not authorized to be used in life support devices or systems. O ne Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.FEATURESFull-featured evaluation board for the AD7795 Standalone USB interfaceVarious linking optionsPC software for control of AD7795GENERAL DESCRIPTIONThis data sheet describes the evaluation board for the AD7795, a low power, 16-bit Σ-Δ ADC. The AD7795 is a complete analog front end for low frequency measurement applications. It contains six differential inputs and includes a low noise instrumentation amplifier, an embedded reference, as well as programmable current sources and a low-side power switch. The update rate can be varied from 4.17 Hz to 500 Hz. It also has an on-board clock, eliminating the need for an external clock. It employs a Σ-Δ conversion technique to realize up to 16 bits of no missing codes performance. The input signal is applied to an analog modulator. The modulator output is processed by an on-chip digital filter. The analog input channel of the AD7795 accepts analog input signals of ±V REF/gain, with gain equal to 1 to 128. With a gain of 64 and the update rate programmed to 16.7 Hz, the rms noise is 86 nV. Simultaneous 50 Hz/60 Hz rejection is also available at this data update rate. Full details on the AD7795 are available in the AD7795 data sheet, available from Analog Devices, Inc., and should be consulted in conjunction with this data sheet when using the evaluation board.The evaluation board interfaces to the USB port of an IBM-compatible PC. Software is available with the evaluation board, which allows the user to communicate easily with the AD7795. Note that the AD7795 evaluation board software must be installed before connecting the AD7795 evaluation board to the PC. Other components on the AD7795 evaluation board include the ADP3303 high precision, low power, 3.3 V output, voltage regulator, which is used to power the USB/SPI interface.FUNCTIONAL BLOCK DIAGRAMFigure 1.EVAL-AD7795Rev. 0 | Page 2 of 16TABLE OF CONTENTSFeatures .............................................................................................. 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Evaluation Board Hardware ............................................................ 3 Power Supplies .............................................................................. 3 L inks ............................................................................................... 3 Setup Conditions .......................................................................... 3 Sockets ........................................................................................... 3 Interfacing to the Evaluation Board ........................................... 4 Evaluation Board Software .............................................................. 5 Software Description.................................................................... 5 Installing the Software ..................................................................5 Using the Software ........................................................................5 Main Window Options .................................................................6 Registers ..........................................................................................7 Other Registers ..............................................................................8 Temp Demo ....................................................................................9 Evaluation Board Schematic and Artwork .................................. 10 Ordering Information .................................................................... 13 Bill of Materials ........................................................................... 13 Ordering Guide .......................................................................... 13 ESD Caution.. (13)REVISION HISTORY4/08—Revision 0: Initial VersionEVAL-AD7795Rev. 0 | Page 3 of 16EVALUATION BOARD HARDWAREPOWER SUPPLIESThe AD7795 evaluation board is powered via the 5 V supply from the USB connector, J1. This 5 V supply can be used to power the AD7795 directly. A 3.3 V regulated voltage from the on-board ADP3303, a high precision, low power, 3.3 V output, voltage regulator, can also be used. Alternatively, the AD7795 can be powered using an external 3 V or 5 V power supply via J3.LINKSThere are eight link options that must be set for the required operating setup before using the evaluation board. The functions of these link options are outlined in Table 1. SETUP CONDITIONSCare should be taken before applying power and signals to the evaluation board to ensure that all link positions are set per the required operating mode. Table 2 shows the position in which all the links are initially set.SOCKETSThere are five sockets relevant to the operation of the AD7795 on this evaluation board. The functions of these sockets are outlined in Table 3.Table 1. Evaluation Board Link SettingsTable 2. Initial Link and Switch PositionsLink No. Position DescriptionLK1 In AIN1(+) and AIN1(−) are shorted. LK2, LK3 Out Internal reference is used.LK4, LK5 Out AIN4(+) and AIN4(−) are not connected to the temperature demonstration circuit. LK6 Out IOUT2 is not connected to the temperature demonstration circuit. LK7 Out LED D1 is not connected to the low-side power switch of the AD7795. LK8BThe 3.3 V supply is used as AV DD for the AD7795.Table 3. Socket FunctionsLink DefaultPosition Description LK1 In This link is used to externally short AIN1(+) to AIN1(−). If V BIAS is enabled and directed to AIN1(−), a noiseanalysis in this configuration can be performed. With this link removed, an external voltage can be applied to AIN1(+)/AIN(−) using the SMB connectors.LK2, LK3 LK4, LK5, LK6 Out These links are used to connect the on-board temperature demonstration circuit to the ADC, and must all be in place when attempting to measure ambient temperature. With the on-board temperature demonstration circuit selected in the software, LK6, when inserted, allowscurrent from the on-chip current source of the AD7795 to flow through the temperature demonstration circuit. LK4 and LK5, when inserted, connect the 1 kΩ thermistor to AIN4(+)/AIN4(−), and with LK2 and LK3 inserted, the 5 kΩ precision resistor is used to generate the reference for the AD7795 so that a ratiometric configuration of the temperature demonstration circuit is achieved.LK7 Out LK7 is used to test the on-chip low-side power switch. If LK7 is in place, enabling the low-side power switchvia the PWR SW drop-down box in the Registers window (see Figure 4) turns on the LED, D2. Clearing this bit turns off the LED.LK8 B LK8 is used to select the power source for AV DD on the AD7795. LK8 in Position A selects an external powersupply, supplied via J3. LK8 in Position B selects the 3.3 V regulated output from the on-board ADP3303 voltage regulator. LK8 in Position C selects the 5 V supply from the USB connector, J1.Socket Description AIN1+ Subminiature BNC (SMB) connector. The analog input signal for the AIN1(+) input of the AD7795 is applied to this socket. AIN1− Subminiature BNC (SMB) connector. The analog input signal for the AIN1(−) input of the AD7795 is applied to this socket. REFIN1+ Subminiature BNC (SMB) connector. This socket is used in conjunction with REFIN1− to apply an external reference to theAD7795. The voltage for the REFIN1(+) input of the AD7795 is applied to this socket.REFIN1− Subminiature BNC (SMB) connector. This socket is used in conjunction with REFIN1− to apply an external reference to theAD7795.The voltage for the REFIN(−) input of the AD7795 is applied to this socket.J2 30-pin (2 × 15) straight header. This socket is used in conjunction with the prototype area to interface any signal to the AD7795.EVAL-AD7795Rev. 0 | Page 4 of 16INTERFACING TO THE EVALUATION BOARDInterfacing to the evaluation board is via a standard USB connec-tor, J1. J1 is used to connect the evaluation board to the USB port of a PC. A standard USB connector cable is included with the AD7795 evaluation board to allow the evaluation board to interface with the USB port of the PC. Because the board is powered via the USB connector, there is no need for an external power supply, although one can be connected if preferred, via J3. Communication between the AD7795 and the PC is via the USB/SPI interface. The on-board USB controller (U2) controls this communication.1. Install the AD7795 evaluation board software, using thesupplied AD7795 evaluation board CD-ROM, before connecting the board to the PC.2. When installation of the AD7795 evaluation board soft-ware is complete, use the supplied USB connector cable to connect the board to the PC via J1 on the AD7795 evaluation board and the USB port on the PC. The PC automatically detects the new USB device and identifies it as the AD779x Evaluation Board .3. Follow the onscreen instructions that appear automatically.During the installation process, if the Hardware Installation window appears (see Figure 2), click Continue Anyway to successfully complete the installation of the AD7795 evalua-tion board.07421-002Figure 2. Hardware InstallationEVAL-AD7795Rev. 0 | Page 5 of 16EVALUATION BOARD SOFTWARESOFTWARE DESCRIPTIONThe AD7795 evaluation board is shipped with a CD-ROM containing software that can be installed onto a standard PC to control the AD7795. The software uses the USB of the PC to communicate with the AD7795, via the cable that accompanies the board.The software allows you to configure the AD7795 and to read conversion data from the AD7795.Data can be read from the AD7795 and displayed or stored for later analysis. For further information, see the AD7795 data sheet available at .INSTALLING THE SOFTWARETo install the software1. Start Windows® and insert the CD-ROM.2. The installation software should launch automatically. If itdoes not, use Windows Explorer to locate the file setup.exe on the CD-ROM. Double-click this file to start the installation procedure.3. At the prompt, select a destination directory, which isC:\Program Files\Analog Devices\AD7795 by default.Once the directory is selected, the installation procedure copies the files into the relevant directories on the hard drive. The installation program creates a program group called Analog Devices with the subgroup AD7795 in the Start menu of the taskbar.4. Once the installation procedure is complete, double-clickthe AD7795 icon to start the program.USING THE SOFTWAREFigure 3 shows the main window that is displayed when the program starts. The Main Window Options section briefly describes the various menu and button options on the main window. The Registers, Other Registers, and Temp Demosections describe the most commonly used evaluation software windows.The data that has been read can be exported to other packages, such as MathCAD™ or Microsoft® Excel, for further analysis. On power-up, the AD7795 evaluation board software configures the device to have a gain of 64, the internal reference is selected,the AIN1(−)/AIN1(−) channel is selected, the bias voltage is enabled on AIN1(−), the update rate is set to 16.7 Hz, and chop is enabled.07421-004Figure 3. AD7795 Evaluation Software Main WindowEVAL-AD7795Rev. 0 | Page 6 of 16MAIN WINDOW OPTIONSMenu BarFile . Allows you to read previously stored data for display or analysis, write the current set of data to a file for later use, and exit the program.About . Provides information on the revision of software being used.ButtonsReset . Allows you to reset the AD7795 and set the registers to the power-up conditions as specified by the software(channel = AIN1(−)/AIN1(−), bias voltage generator enabled on AIN1(−), gain = 64, update rate = 16.7 Hz, internal reference, chop enabled).Exit. Allows you to exit the software. It serves the same purpose as the Quit option in the File drop-down menu. Sample . Allows you to read a number of samples from the AD7795. Noise analysis is then performed on the samples. These samples can be stored for further analysis. The sample size is entered in the Num Samples spin box. Continuous . Allows you to read a number of samples conti-nuously. The software gathers a number of samples as specified by Num Samples , performs noise analysis on the samples, and then gathers the next group of samples.Registers . Allows you to access the configuration register, mode register, and IO register.Other Registers . Allows you to access the ID register, status register, offset register, and full-scale register.Quick Analysis . Displays the Quick Analysis window. The Quick Analysis window gives you access to a subset of the AD7795 control bits: channel, update rate, gain, reference source, and chop. For access to all control bits, click the Registers button or the Other Registers button.T emp Demo . Allows you to access the temperature demonstration software.Samples/Analysis . Serves the same purpose as the Sample button. Waveform . The gathered conversions are displayed in graph form. Histogram . The gathered samples are used to generate a histogram.Codes . The gathered samples can be displayed in code or in voltage format. When the Codes button is clicked, the values are displayed as code and the Codes button changes to Volts . To display the information in volts, click the Volts button. Applied Reference . By default, the internal reference is used. To use an external reference, Reference in the Quick Analysis window should be set to REFIN1 if the external reference is applied between REFIN1(+) and REFIN1(−), or set to REFIN2 if the applied reference is applied between REFIN2(+) and REFIN2(−). The value of the external reference should be entered in the Applied Reference spin box.EVAL-AD7795Rev. 0 | Page 7 of 16REGISTERSTo access the configuration register, the mode register, and the IO register, click the Registers button (see Figure 4). Thiswindow allows you to change the update rate, the reference source, and the clock source, among other options. Consult the AD7795 data sheet for further details on the bit functions.07421-005Figure 4. AD7795 Evaluation Software Registers WindowEVAL-AD7795Rev. 0 | Page 8 of 16OTHER REGISTERST o access additional registers, click the Other Registers button (see Figure 5). This window displays the contents of the offset calibration register, the ID register, the full-scale calibration register, and the status register. To write to the offset calibration and full-scale calibration registers, you must place the AD7795 in power-down or idle mode using the Mode box in the Registers window (see Figure 4).07421-006Figure 5. AD7795 Evaluation Software Other Registers WindowEVAL-AD7795Rev. 0 | Page 9 of 16TEMP DEMOT o access the temperature demonstration window, click the Temp Demo button. The AD7795 evaluation board has a temperature demonstration included on the board. T o operate the temperature demonstration, LK2 to LK6 should be inserted and LK1 should be removed. With these links in place, the AD7795 excitation current is connected to a 1 kΩ thermistor, which is connected across the AIN4(+)/AIN4(−) pins. In series with the thermistor is a 5 kΩ precision resistor that is used to generate the reference voltage. The ratiometric configuration optimizes the system perfor-mance. The temperature demonstration software saves the values in the mode register, the configuration register, and the IO register. The software then configures the AD7795 to operate with a 210 μA excitation current, the AIN4(+)/AIN4(−) channel is selected as the analog input, the gain is set to 1, and the external reference REFIN1(+)/REFIN1(−) is selected. When the Run button is clicked, the software continuously reads the conver-sion from the AIN4(+)/AIN4(−) channel and converts the result to temperature using a lookup table.When Run is clicked again, the temperature demonstration execution is halted. To exit the temperature demonstration, click the Back button. The software sets the configurationregister, the mode register, and the I/O register to their pre-temperature demonstration values.07421-007Figure 6. AD7795 Temperature Demo WindowEVAL-AD7795EVALUATION BOARD SCHEMATIC AND ARTWORKFigure 7. AD7795 Evaluation Board SchematicRev. 0 | Page 10 of 1607420-009Figure 8. AD7795 Evaluation Board Component Side Artwork07420-008Figure 9. AD7795 Evaluation Board Solder Side Artwork07420-011Figure 10. AD7795 Evaluation Board Component Layout DiagramORDERING INFORMATIONBILL OF MATERIALSTable 4.Qty Reference Designator Description Manufacturer/Part No.CircuitsIntegrated3 U1, U5, U6 AD7795BRUZ Analog Devices1 U2 USB controller Cypress Semiconductor Corporation, CY7C68013A-56LFXC 1 U3 24LC64 Microchip Technology Inc., 24LC64-I/SNDevices1 U4 ADP3303ARZ-3.3 Analog1 Y1 24 MHz crystal AEL Crystals, X24M000000S2442 D1, D2 Green LED Fairchild Semiconductor, QTLP630C-41 L1 Ferrite bead Meggitt Sigma, BMB2A0300AN11 D3 Diode Micro Commercial Components Corp., DL4001-TPCapacitors19 C1 to C18, C44 Capacitors Not inserted1 C19 100 pF ceramic AVX Corporation, 06035A101JAT2A15 C20, C22, C27, C28, C32, C34 to C43 0.1 μF ± 10% ceramic AVX Corporation, CM105X7R104K16AT3 C21, C23, C26 10 μF tantalum AVX Corporation, TAJA106K010R2 C24, C25 1 μF ceramic Yageo Corporation, 2238 246 198631 C29 2.2 μF tantalum EPCOS AG, B45196E2225K1092 C30, C31 22 pF ceramic Yageo Corporation, 2238 867 152291 C33 47 μF tantalum AVX Corporation, TAJC476K016RResistors1 R1 1 kΩ thermistor EPCOS AG, B57620C102J621 R2 5 kΩ ± 0.1% Tyco International, Ltd., RN73C2A4K99BTG15 R3 to R16, R23 0 Ω resistor Multicomp, MC 0.063W 0603 0R4 R17 to R20 1 MΩ resistor Multicomp, MC 0.063W 0603 1% 1M2 R21, R22 100 kΩ resistor Multicomp, MC 0.063W 0603 1% 100K4 R24 to R27 10 kΩ resistor Multicomp, MC 0.063W 0603 1% 10K2 R28, R29 2.2 kΩ resistor Multicomp, MC 0.063W 0603 1% 2K22 R30, R31 1 kΩ resistor Multicomp, MC 0.063W 0603 1% 1KLinks8 LK1 to LK7 (2 × 1 way), LK8 (3 × 2 way) Pin headers Harwin Plc, M20-99836468 At LK1 to LK8 Shorting plugs Harwin Plc, M7566-05Connectors4 AIN1+, AIN1−, REFIN1+, REFIN1−, CLK SMB connector Not inserted1 J1 USB Mini-B connector Molex, 5657905761 J2 30-pin (2 × 15) header Harwin Plc, M20-99836461 J3 2-way terminal block Camden Electronics Ltd., CTB5000/2ESD CAUTIONORDERING GUIDEModel DescriptionEVAL-AD7795EB EvaluationBoardNOTESNOTESNOTES©2008 Analog Devices, Inc. All rights reserved. Trademarks andregistered trademarks are the property of their respective owners.EB07421-0-4/08(0)。