eetop[1].cn_[----]A linear high voltage 0.18um charge pump for MEMS applications

A Linear High Voltage Charge Pump For MEMS Applicationsin0.18µm CMOS TechnologyManuel Innocent∗,Piet Wambacq,St´e phane Donnay,Willy Sansen∗∗,and Hugo De Man∗∗∗IMEC,Kapeldreef75,Leuven,Belgium.∗Also Ph.D.student at Katholieke Universiteit Leuven.∗∗ESAT-MICAS,Katholieke Universiteit Leuven.∗∗∗Also professor at Katholieke Universiteit Leuven.Innocent@imec.beAbstractTunable MEMS components start to appear in wireless communication systems.They allow for new functionality such as tunable RFfilters or they improve performance like electrostatically tuned variable capacitors that are used in voltage-controlled oscillators.However,the re-quired tuning voltage for these capacitors is often much higher than the supply voltage of the deep sub-micron (Bi)CMOS technology which is typically used for these ap-plications.Therefore we designed a high-voltage charge pump that can generate an output voltage between-0.7V and+14.8V out of a1.8V power supply.It is built in a0.18µm CMOS technology,requires the same control signals as a regular charge pump and provides a constant output current of0.7µA over its complete voltage range. This high-voltage charge pump solves the problem of the high tuning voltage of MEMS variable capacitors at low power,at a small area cost and in a way which is com-pletely transparent to the system designer.1.IntroductionMEMS components like electrostatically tuned vari-able capacitors start to appear in RF circuits[1,2].Com-pared to other types of variable capacitors(MOS,PN-junction),these MEMS variable capacitors can e.g.im-prove the linearity of tunable RFfilters[3]or the phase noise of voltage controlled oscillators[4].However,the tuning voltage required by these devices is typically be-tween5V and50V,which is higher than the maximum supply voltage of a sub-micron CMOS technology.Al-though the required tuning voltage of these devices can be changed by design,it is unlikely to go below the rapidly decreasing supply voltage of scaled CMOS technologies. Moreover,there is a trade off between the required tun-ing voltage and other parameters like the mechanical res-onance frequency,the electrical losses and the linearity of the device.This implies that the MEMS control circuit has to generate voltages higher than the supply voltage of the rest of the system.For the output stage of this high voltage control circuit,we have two options.Thefirst op-tion is to put the complete high voltage supply over the output stage.This will either require a dedicated high voltage technology like Alcatel HBiMOS[5],or dedi-cated high voltage devices in an(almost)standard tech-nology[6].A dedicated high-voltage technology is often unwanted because of cost reasons.As an alternative,this paper presents a control circuit for a MEMS variable ca-pacitor that dynamically adjusts the power supply while putting only a limited voltage over the output stage.It does not require any dedicated technology or devices ex-cept for triple well,which is quite standard in nowadays CMOS processes with analog options.The output volt-age is in this case only limited by the N-well to substrate breakdown voltage.We call this system”power supply on demand”and its application to a high-voltage charge pump for use in a PLL with a MEMS variable capacitor is the main contribution of the work presented in this paper.Section2discusses the operation of a high voltage charge pump for use in a phase locked loop(PLL).Section 3shows the measurement results and section4presents the conclusions.2.A charge pump withpower supply on demandThe high voltage charge pump(HVCP)is designed for use as charge pump of a phase-locked loop[7,8].It has the same connections as a standard charge pump[8](up and down signals),so to the system designer it acts as a standard one.It has however a large output voltage range which is obtained by extending a standard charge pump with a”power supply on demand”.The HVCP(figure1)consists of two major parts:the core charge pump with sense amplifier latches and the high-voltage generator.These two parts are in separate power supply regions and together they form a closed con-trol loop.The goal of this loop is to keep the output of the core charge pump in the middle between it’s high and the low power supply rail(”high”and”low”infigure1).Both supply rails of the core charge pump region are adjusted,UpMEMScapacitor Figure1.High-voltage charge pump,consisting of the core charge pump(CP)(dashed,in the high power supply re-gion)and the high voltage generator(HVG)(solid lines,in the low supply region,with an external ground and1.8V sup-ply).Signals go from one region to another through a level converter(LC).charge pump and two sense amplifier latches(SA)which compare the output voltage with its upper and lower limit and request the high voltage generator to change supply of the high voltage region accordingly.When the HVCP is used in a PLL the Up and Down signals come from the phase frequency detector.but their difference is constant.This makes the charge pump very linear over a large voltage range because the voltage over the output transistors is constant.The output of the charge pump(figure2)is the ref-erence to which the other voltages of the system are ad-justed.It is buffered with two symmetrical OTAs and then compared to two reference voltages with sense amplifier latches[9].The references are at40%and60%between the high and the low supply rail of the core charge pump. An output voltage outside this range results in a request signal(HVGup,HVGdown)to adjust the supply.For ex-ample,if the output decreases below the lower reference voltage then the supply voltages of the core charge pump are decreased until the lower limit drops below the output again.Thus,an output which is out of range is not cor-rected by adjusting the output,but by adjusting the power supply.HighLowClkClkbHVGupHVGdownHVGupbHVGdownbC decoupleC decoupleC Nwell-subLeafUPLeafDOWNLeafUPLeafDOWNLeafUPLeafDOWNLeafUPLeafDOWNLeafUPFigure3.The high voltage generator(HVG)consists of 10identical stages that can pump charge either up or down. The last stage is permanently clocked to generate the supply of the high voltage region.OutInHVGupHVGdownHVGupbHVGdownbLeafUPLeafDOWNFigure4.Every stage of the high voltage generator consists of a cell that can pump charge up(top)and a cell that can pump charge down(bottom).The supply voltage of the core charge pump is provided by the high voltage generator(HVG)(figure3).This HVG can generate voltages much higher than its own supply voltage(typically1.8V for0.18µm CMOS).This is often realized similarly to the Dickson charge pump of 1976[10].However Dickson’s charge pump can only pump charge to higher voltages;it has no means to lower the voltage again.The”power supply on demand”re-quires that the output voltage can both be increased and decreased.That is why we use a basic cell with two in-verters like in[11].This cell can be connected in reverse to pump down the charge.Every stage(figure4)of the HVG consists of two basic cells connected in parallel;one to pump charge up and one to pump charge down.Each stage is located in a separate N-well which is charged to its own output voltage.The basic cell of the HVG consists of two capacitors and two inverters.The inverters are realized with stan-dard low voltage transistors as none of the voltages over these transistors exceed the supply voltage.The HVG is driven by two complementary clock signals.This simple two-phase clocking scheme allows a high clock frequency(>50MHz).All stages of the HVG except the last one,are conditionally clocked.The HVGup and HVG-down signals are the request signals coming from the core charge pump.The last stage is continuously clocked to generate the power supply of the high-voltage region.The voltage gain∆V over each stage has two contri-butions,as shown by:∆V=VddCfrequency C+R switch.(2)In thefirst part,the capacitance C is the coupling capaci-tance in the control lines(HVGup,HVGupb)and C par is parasitic capacitance at the internal nodes of the basic cell, not at the input and output nodes.Hence,the presence of the DOWN cell does not limit the voltage gain of the UP cell.However,the transistors of the UP cell themselves form a large part of the parasitic capacitance.This implies that these transistors should be small.The second part de-pends on the output current,so we have to differentiate between thefinal stage that generates the supply in high supply region and the stages that change the absolute volt-age of that region.Thefinal stage permanently supplies a current to the circuits in the high supply region,so R out has to be small enough to limit the voltage loss in this stage.This implies transistors with a small on-resistance and a large capacitor and/or high clock frequency.For the other stages the situation is different.If this charge pump is used to control an electrostatically tuned varicap then only the(dis)charge current of the varicap and the high supply region has to be delivered.There is no static cur-rentflowing which means that the maximum voltage is defined only by the capacitance ratio.This section explained in a top down way the operation principle of the high voltage charge pump,the next section presents the measurement results.3.MeasurementsOur high voltage charge pump is processed in a 0.18mathitµm CMOS technology.It has a pad-limited die size of700µm∗700µm,but the circuit area is only 300µm∗430µm.In this section we will show that the proposed circuit has a very large output voltage range and that it is a low power solution which it is scalable to future CMOS generations.We measured the high voltage charge pump with a load capacitance of22pF at the output and the oscilloscope connected to the low supply rail of the high voltage region. The input resistance of the oscilloscope is1MΩ,which is too low to connect directly to the charge pump output. Table1summarizes the measurement conditions.Figure5shows a transient measurement of the low sup-ply rail of the high voltage region.From the transient mea-surement we can calculate the charge pump output cur-Table1.Measurement conditionsSupply10+1Load50MHzUp and Down signals100kHzDuty cycle∆t DutyCycle,(3)The current consumption depends strongly on the op-erating regime.The maximum current of1mA is drawn when the output is limited by conduction or breakdown of the N-well to substrate junction.In normal operation this is also the maximum current that can occur during tran-sients.In steady state,with a50MHz clock signal,but without up or down pulses,the current is only85µA and the leakage current is so small that we could not measure a difference in output voltage after1second.In a PLL in lock,the up and down pulses are very small so that the current consumption will be very close to this85µA,so this can be regarded as a low power solution.When the clock is also turned off,the supply current drops to only a few nA.The high voltage generator has10+1stages and a sup-ply of1.8V,so the theoretical maximum output voltage (without parasitic capacitances)is19.8V.However,the measurement shows only13.2V at the”Low”node plus 1.6V over thefinal stage,which is only14.8V.This dif-ference is larger than what is expected based on the para-sitic capacitance,but it is explained by the characteristics of the N-well to substrate junction.The high supply volt-age region is inside an N-well which is charged to the high supply rail of this region.The highest possible voltage in the system is the breakdown voltage of the well to sub-−2024681012141618−0.01−0.0050.0050.01Voltage (V)C u r r e n t (A )Figure 6.Measured current through an N-well to substrate junction as a function of the bias voltage for 0.18µm CMOS.At negative voltage the diode conducts.At positive voltage it breaks down.These two voltages limit the output range of the high voltage charge pump.Table 2.Measurement resultsOutput current1.0mASupply current idle (50MHz clock)2.5nAV oltage range (at ”Low”node)−0.7V ...+14.8Vstrate junction which is 14.8V for the used technology (figure 6).Any attempt to charge the well to a higher volt-age results in charge flowing away to the substrate.As the breakdown voltage poses the fundamental limit on the output voltage we checked it for several technologies.The results are all in the same range e.g.16.2V for a 0.35µm BiCMOS technology and 17.5V and 18.5V volts for two flavors of 0.09µm CMOS technology.This shows that the circuit can be used in future technologies.Table 2summa-rizes the measurement results.4.ConclusionsThis paper presents a high voltage charge pump de-signed for use in a charge pump phase locked loop with a MEMS varicap based voltage controlled oscillator.The charge pump generates output voltages between −0.7V and +14.8V out of a 1.8V power supply.It delivers a constant output current over the complete voltage range.It is built in 0.18µm CMOS technology and it is scal-able to future CMOS generations.The output voltage is only limited by the (N-)well to substrate breakdown volt-age.This high voltage charge pump solves the problem of the high required tuning voltage of MEMS variable ca-pacitors at low power and at a small area cost.It requires the same control signals as a regular chargepump so it is completely transparent to the system designer.5.References[1] C.T.-C.Nguyen,L.P.B.Katehi and G.M.Rebeiz,“Micromachineddevices for wireless communications”,Proc.of the IEEE ,1998pp.1756-1768.[2]H.A.C.Tilmans,“MEMS components for wireless communica-tions”,Proceedings of EUROSENSORS XVI ,pp.1–34,Sep.2002.Figure 7.The high voltage charge pump chip is 700µm ∗700µm .The decoupling capacitors and the level converters are at the left side.The capacitors of the 10HVG stages are at the right side.[3]M.Innocent,P.Wambacq,S.Donnay,H.A.C.Tilmans,W.Sansenand H.De Man,“An analytic V olterra-series-based model for a MEMS variable capacitor,”IEEE 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