MEMORY存储芯片ADM485ANZ中文规格书

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MEMORY存储芯片MT48LC4M32B2TG-7 G中文规格书

Table 31: MPR Readout Serial Format (Continued)MPR Readout Parallel FormatParallel format implies that the MPR data is returned in the first data UI and then repea-ted in the remaining UIs of the burst, as shown in the table below. Data pattern location0 is the only location used for the parallel format. RD/RDA from data pattern locations1, 2, and 3 are not allowed with parallel data return mode. In this example, the patternprogrammed in the data pattern location 0 is 0111 1111. The x4 configuration only out-puts the first four bits (0111 in this example). For the x16 configuration, the same pat-tern is repeated on both the upper and lower bytes.Table 32: MPR Readout – Parallel Format4Gb: x4, x8, x16 DDR4 SDRAM Multipurpose RegisterTable 84: Command and Address Input Levels: DDR4-1600 Through DDR4-2400 (Continued)Notes: 1.For input except RESET_n. V REF = V REFCA(DC).2.V REF = V REFCA(DC).3.Input signal must meet V IL /V IH(AC) to meet t IS timings and V IL /V IH(DC) to meet t IH timings.4.The AC peak noise on V REF may not allow V REF to deviate from V REFCA(DC) by more than±1% V DD (for reference: approximately ±12mV).5.Refer to “Overshoot and Undershoot Specifications.”Table 85: Command and Address Input Levels: DDR4-2666Notes: 1.For input except RESET_n. V REF = V REFCA(DC).2.V REF = V REFCA(DC).3.Input signal must meet V IL /V IH(AC) to meet t IS timings and V IL /V IH(DC) to meet t IH timings.4.The AC peak noise on V REF may not allow V REF to deviate from V REFCA(DC) by more than±1% V DD (for reference: approximately ±12mV).5.Refer to “Overshoot and Undershoot Specifications.”Table 86: Command and Address Input Levels: DDR4-2933 and DDR4-3200Notes: 1.For input except RESET_n. V REF = V REFCA(DC).2.V REF = V REFCA(DC).3.Input signal must meet V IL /V IH(AC) to meet t IS timings and V IL /V IH(DC) to meet t IH timings.4.The AC peak noise on V REF may not allow V REF to deviate from V REFCA(DC) by more than±1% V DD (for reference: approximately ±12mV).5.Refer to “Overshoot and Undershoot Specifications.”4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Single-Ended Input Measurement Levels。

MEMORY存储芯片ADM3485EARZ-REEL中文规格书

Data SheetADM3491-1FEATURESOperates with 3.3 V supplyEIA RS-422 and RS-485 compliant over full CM range 19 kΩ input impedanceUp to 50 transceivers on bus 20 Mbps data rateShort-circuit protectionSpecified over full temperature range Thermal shutdownInteroperable with 5 V logic 840 μA supply current 2 nA shutdown currentAvailable in PDIP , SOIC, and TSSOP Meets IEC1000-4-4 (>1 kV) 8 ns skewUpgrade for MAX3491, SN75ALS180APPLICATIONSTelecommunications DTE–DCE interface Packet switching Local area networks Data concentration Data multiplexersIntegrated services digital network (ISDN) AppleTalkIndustrial controlsGENERAL DESCRIPTIONThe ADM3491-1 is a low power, differential line transceiver designed to operate using a single 3.3 V power supply. Low power consumption, coupled with a shutdown mode, makes it ideal for power-sensitive applications. It is suitable for commu-nication on multipoint bus transmission lines.The ADM3491-1 is intended for balanced data transmission and complies with both Electronic Industries Association (EIA) Standards RS-485 and RS-422. It contains a differential line driver and a differential line receiver, making it suitable for full-duplex data transfer.FUNCTIONAL BLOCK DIAGRAMABZY05234-001The input impedance is 19 kΩ, allowing up to 50 transceivers to be connected on the bus. A thermal shutdown circuit prevents excessive power dissipation caused by bus contention or byoutput shorting. This feature forces the driver output into a high impedance state if a significant temperature increase is detected in the internal driver circuitry during fault conditions. If the inputs are unconnected (floating), the receiver contains a fail-safe feature that results in a logic high output state. The ADM3491-1 is fabricated on BiCMOS, an advanced mixed technology process combining low power CMOS with fast switching bipolar technology.TIMING SPECIFICATIONSV CC = 3.3 V, T A = 25°C, unless otherwise noted.Table 2.Parameter Min Typ Max Unit Test Conditions/ CommentsDRIVERDifferential Output Delay, T DD 1 35 ns R L = 60 Ω, C L1 = C L2 = 15 pF, see Figure 18 Differential Output Transition Time 1 8 15 ns R L = 60 Ω, C L1 = C L2 = 15 pF, see Figure 18 Propagation Delay Input to Output, T PLH, T PHL7 22 35 ns R L = 27 Ω, C L1 = C L2 = 15 pF, see Figure 19Driver Output to Output, T SKEW8 ns R L = 54 Ω, C L1 = C L2 = 15 pF, see Figure 19ENABLE/DISABLEDriver Enable to Output Valid 45 90 ns R L = 110 Ω, C L = 50 pF, see Figure 16Driver Disable Timing 40 80 ns R L = 110 Ω, C L = 50 pF, see Figure 16Driver Enable from Shutdown 65 110 ns R L = 110 Ω, C L = 15 pF, see Figure 16RECEIVERTime to Shutdown 80 190 300 nsPropagation Delay Input to Output, T PLH, T PHL25 65 90 ns C L = 15 pF, see Figure 21Skew, T PLH – T PHL10 ns C L = 15 pF, see Figure 21ns C L = 15 pF, see Figure 17Receiver Enable, T EN25 50Receiver Disable, T DEN25 45 ns C L = 15 pF, see Figure 17Receiver Enable from Shutdown 500 ns C L = 15 pF, see Figure 17V CC = 3.3 V ± 0.3 V, T A = T MIN to T MAX, unless otherwise noted.Table 3.Parameter MinConditions/CommentsUnitTestTypMaxDRIVERDifferential Output Delay, T DD 1 70 ns R L = 60 Ω, C L1 = C L2 = 15 pF, see Figure 18 Differential Output Transition Time 2 8 15 ns R L = 60 Ω, C L1 = C L2 = 15 pF, see Figure 18 Propagation Delay Input to Output, T PLH, T PHL7 22 70 ns R L = 27 Ω, C L1 = C L2 = 15 pF, see Figure 19Driver Output to Output, T SKEW10 ns R L = 54 Ω, C L1 = C L2 = 15 pF, see Figure 19ENABLE/DISABLEDriver Enable to Output Valid 45 110 ns R L = 110 Ω, C L = 50 pF, see Figure 16Driver Disable Timing 40 110 ns R L = 110 Ω, C L = 50 pF, see Figure 16Driver Enable from Shutdown 65 110 ns R L = 110 Ω, C L = 15 pF, see Figure 16RECEIVERTime to Shutdown 50 190 500 nsPropagation Delay Input to Output, T PLH, T PHL25 65 115 ns C L = 15 pF, see Figure 21Skew, T PLH – T PHL20 ns C L = 15 pF, see Figure 21Receiver Enable, T EN25 50 ns C L = 15 pF, see Figure 17Receiver Disable, T DEN25 50 ns C L = 15 pF, see Figure 17Receiver Enable from Shutdown 600 ns C L = 15 pF, see Figure 17PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONSV CC V CC AB Z YNCNC = NO CONNECT05234-002Figure 2. 14-Lead PDIP and 14-Lead SOIC Pin ConfigurationNC = NO CONNECTNCRO RE NC DI DE V CC A B NC NCGNDNCY Z NC 05234-003Figure 3. 16-Lead TSSOP Pin ConfigurationTEST CIRCUITS05234-004Figure 14. Driver Voltage Measurement Test Circuit05234-006Figure 18. Driver Differential Output Delay Test CircuitTHEORY OF OPERATIONDIFFERENTIAL DATA TRANSMISSIONDifferential data transmission is used to reliably transmit data at high rates over long distances and through noisy environments. Differential transmission nullifies the effects of ground shifts and noise signals that appear as common-mode voltages on the line. The two main standards approved by the EIA specify the electrical characteristics of transceivers used in differential data transmission:∙RS-422 standard specifies data rates up to 10 MBaud and line lengths up to 4000 ft. A single driver can drive atransmission line with up to 10 receivers.∙RS-485 standard was defined to cater to true multipoint communications. This standard meets or exceeds all therequirements of RS-422, but also allows multiple driversand receivers to be connected to a single bus. An extended common-mode range of −7 V to +12 V is defined.The most significant differentiator of the RS-485 standard is that the drivers can be disabled, thereby allowing more than one to be connected to a single line. Only one driver should be enabled at a time, but the RS-485 standard contains additional specifications to guarantee device safety in the event of line contention.Table 6. Comparison of RS-422 and RS-485 Interface Standards Specification RS-422 RS-485 Transmission Type Differential Differential Maximum Cable Length 4000 ft. 4000 ft. Minimum Driver Output Voltage ±2 V ±1.5 V Driver Load Impedance 100 Ω 54 Ω Receiver Input Resistance 4 kΩ min 12 kΩ min Receiver Input Sensitivity ±200 mV ±200 mV Receiver Input Voltage Range −7 V to +7 V −7 V to +12 VCABLE AND DATA RATEThe transmission line of choice for RS-485 communications is a twisted pair. Twisted pair cable tends to cancel common-mode noise and also causes cancellation of the magnetic fields gener-ated by the current flowing through each wire, thereby reducing the effective inductance of the pair.The ADM3491-1 is designed for bidirectional data communica-tions on multipoint transmission lines. A typical application showing a multipoint transmission network is illustrated in Figure 26. Only one driver can transmit at a particular time, but multiple receivers can be enabled simultaneously. As with any transmission line, it is important that reflections be minimized. This can be achieved by terminating the extreme ends of the line using resistors equal to the characteristic impedance of the line. Stub lengths of the main line should also be kept as short as possible. A properly terminated transmission line appears purely resistive to the driver. RECEIVER OPEN-CIRCUIT FAIL-SAFE FEATUREThe receiver input includes a fail-safe feature that guarantees a logic high on the receiver when the inputs are open circuit or floating.5234-26 Figure 26. ADM3491-1 Full-Duplex Data Link。

MEMORY存储芯片MT48LC8M8A2P-75中文规格书

SRT versus ASRIf the normal T C limit of 85°C is not exceeded, then neither SRT nor ASR is required, andboth can be disabled throughout operation. However, if the extended temperature op-tion of 95°C is needed, the user is required to provide a 2x refresh rate during manualrefresh and to enable either the SRT or the ASR to ensure self refresh is performed at the2x rate.SRT forces the DRAM to switch the internal self refresh rate from 1x to 2x. Self refresh isperformed at the 2x refresh rate regardless of the case temperature.ASR automatically switches the DRAM’s internal self refresh rate from 1x to 2x. Howev-er, while in self refresh mode, ASR enables the refresh rate to automatically adjust be-tween 1x and 2x over the supported temperature range. One other disadvantage of ASRis the DRAM cannot always switch from a 1x to 2x refresh rate at an exact T C of 85°C.Although the DRAM will support data integrity when it switches from a 1x to 2x refreshrate, it may switch at a temperature lower than 85°C.Since only one mode is necessary, SRT and ASR cannot be enabled at the same time. Dynamic On-Die Termination (ODT)The dynamic ODT (R TT(WR)) feature is defined by MR2[10, 9]. Dynamic ODT is enabledwhen a value is selected for the dynamic ODT resistance R TT(WR). This new DDR3SDRAM feature enables the ODT termination resistance value to change without issu-ing an MRS command, essentially changing the ODT termination on-the-fly.With dynamic ODT (R TT(WR)) enabled, the DRAM switches from nominal ODT (R TT,nom)to dynamic ODT (R TT(WR)) when beginning a WRITE burst, and subsequently switchesback to normal ODT (R TT,nom) at the completion of the WRITE burst. If R TT,nom is disa-bled, the R TT,nom value will be High-Z. Special timing parameters must be adhered towhen dynamic ODT (R TT(WR)) is enabled: ODTLcnw, ODTLcwn4, ODTLcwn8, ODTH4,ODTH8, and t ADC.Dynamic ODT is only applicable during WRITE cycles. If normal ODT (R TT,nom) is disa-bled, dynamic ODT (R TT(WR)) is still permitted. R TT,nom and R TT(WR) can be used inde-pendent of one another. Dynamic ODT is not available during write leveling mode, re-gardless of the state of ODT (R TT,nom). For details on dynamic ODT operation, refer tothe Dynamic ODT section of the data sheet.Commands – Truth TablesTable 87: Truth Table – CommandNotes: mands are defined by the states of CS#, RAS#, CAS#, WE#, and CKE at the risingedge of the clock. The MSB of BA, RA, and CA are device-, density-, and configuration-dependent.。

MEMORY存储芯片MAX485CPA中文规格书

Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers12MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487500mV/div 20ns/div ABRO 2V/divV CC = 5V T A = +25°C 500mV/div 20ns/divAB RO2V/divV CC = 5V T A = +25°C500mV/div 400ns/div ABRO2V/div V CC = 5V T A = +25°C 500mV/div 400ns/divA B RO2V/div V CC = 5VT A = +25°CFigure 14. Receiver Propagation Delay Test CircuitFigure 15. MAX481/MAX485/MAX490/MAX491/MAX1487Receiver t PHL Figure 16. MAX481/MAX485/MAX490/MAX491/MAX1487Receiver t PLHPHL Figure 18. MAX483, MAX487–MAX489 Receiver t PLHLow-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers 8MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487__________Applications Information The MAX481/MAX483/MAX485/MAX487–MAX491 and MAX1487 are low-power transceivers for RS-485 and RS-422 communications. The MAX481, MAX485, MAX490,MAX491, and MAX1487 can transmit and receive at data rates up to 2.5Mbps, while the MAX483, MAX487,MAX488, and MAX489 are specified for data rates up to 250kbps. The MAX488–MAX491 are full-duplex trans-ceivers while the MAX481, MAX483, MAX485, MAX487,and MAX1487 are half-duplex. In addition, Driver Enable (DE) and Receiver Enable (RE ) pins are included on the MAX481, MAX483, MAX485, MAX487, MAX489,MAX491, and MAX1487. When disabled, the driver and receiver outputs are high impedance.MAX487/MAX1487:128 Transceivers on the Bus The 48k Ω, 1/4-unit-load receiver input impedance of the MAX487 and MAX1487 allows up to 128 transceivers on a bus, compared to the 1-unit load (12k Ωinput impedance) of standard RS-485 drivers (32 trans-ceivers maximum). Any combination of MAX487/MAX1487 and other RS-485 transceivers with a total of 32 unit loads or less can be put on the bus. The MAX481/MAX483/MAX485 and MAX488–MAX491 have standard 12k ΩReceiver Input impedance.Figure 2. MAX488/MAX490 Pin Configuration and Typical Operating Circuit Figure 3. MAX489/MAX491 Pin Configuration and Typical Operating Circuit。

MEMORY存储芯片MT48LC8M16A2B4-75中文规格书

Dynamic ODTIn certain application cases and to further enhance signal integrity on the data bus, it isdesirable that the termination strength of the device can be changed without issuing anMRS command. This requirement is supported by the dynamic ODT feature.Functional DescriptionDynamic ODT mode is enabled if bit A9 or A10 of MR2 is set to 1.•Three R TT values are available: R TT(NOM), R TT(WR), and R TT(Park).–The value for R TT(NOM) is preselected via bits MR1[10:8].–The value for R TT(WR) is preselected via bits MR2[11:9].–The value for R TT(Park) is preselected via bits MR5[8:6].•During operation without WRITE commands, the termination is controlled as fol-lows:–Nominal termination strength R TT(NOM) or R TT(Park) is selected.–R TT(NOM) on/off timing is controlled via ODT pin and latencies DODTLon andDODTLoff, and R TT(Park) is on when ODT is LOW.•When a WRITE command (WR, WRA, WRS4, WRS8, WRAS4, and WRAS8) is regis-tered, and if dynamic ODT is enabled, the termination is controlled as follows:–Latency ODTLcnw after the WRITE command, termination strength R TT(WR) is se-lected.–Latency ODTLcwn8 (for BL8, fixed by MRS or selected OTF) or ODTLcwn4 (forBC4, fixed by MRS or selected OTF) after the WRITE command, terminationstrength R TT(WR) is de-selected.One or two clocks will be added into or subtracted from ODTLcwn8 and ODTLcwn4,depending on write CRC mode and/or 2t CK preamble enablement.The following table shows latencies and timing parameters relevant to the on-die termi-nation control in dynamic ODT mode. The dynamic ODT feature is not supported inDLL-off mode. An MRS command must be used to set R TT(WR) to disable dynamic ODTexternally (MR2[11:9] = 000).Table 74: Dynamic ODT Latencies and Timing (1t CK Preamble Mode and CRC Disabled)4Gb: x4, x8, x16 DDR4 SDRAM Dynamic ODTFigure 161: READ (BC4: Fixed) to WRITE (BC4: Fixed) with 1t CK Preamble and Write CRC in Same or Different Bank GroupCommand DQ x4,BC = 4 (Fixed)CK_t CK_cDQS_t,DQS_cBank GroupAddress AddressDQ x8/X16,BC = 4 (Fixed)Notes: 1.BC = 4 (Fixed), RL = 11 (CL = 11, AL = 0), READ preamble = 1t CK, WL = 9 (CWL = 9, AL =0), WRITE preamble = 1t CK.2.DO n = data-out from column n , DI b = data-in from column b .3.DES commands are shown for ease of illustration; other commands may be valid atthese times.4.BC4 setting activated by MR0[1:0] = 10.5.CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,Write CRC = Enable.READ Operation with Command/Address Latency (CAL) EnabledFigure 162: Consecutive READ (BL8) with CAL (3t CK) and 1t CK Preamble in Different Bank GroupCommandw/o CS_nDQCK_tCK_cDQS_t,DQS_cBank GroupAddress Address CS_n Notes: 1.BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 1t CK.4Gb: x4, x8, x16 DDR4 SDRAM READ Operation。

MEMORY存储芯片ADM485ARZ-REEL中文规格书

ADM485FUNCTIONAL BLOCK DIAGRAMCC 00078-001FEATURESMeets EIA RS-485 standard 5 Mbps data rateSingle 5 V supply–7 V to +12 V bus common-mode range High speed, low power BiCMOS Thermal shutdown protection Short-circuit protectionDriver propagation delay: 10 ns typical Receiver propagation delay: 15 ns typical High-Z outputs with power off Superior upgrade for LTC485APPLICATIONSLow power RS-485 systems DTE/DCE interface Packet switchingLocal area networks (LNAs) Data concentration Data multiplexersIntegrated services digital network (ISDN)GENERAL DESCRIPTIONThe ADM485 is a differential line transceiver suitable for high speed bidirectional data communication on multipoint bus transmission lines. It is designed for balanced data transmission and complies with EIA standards RS-485 and RS-422. The part contains a differential line driver and a differential line receiver. Both the driver and the receiver can be enabled independently. When disabled, the outputs are three-stated.The ADM485 operates from a single 5 V power supply. Excessive power dissipation caused by bus contention or by output shorting is prevented by a thermal shutdown circuit. If during fault conditions, a significant temperature increase is detected in the internal driver circuitry, this feature forces the driver output into a high impedance state.Up to 32 transceivers can be connected simultaneously on a bus, but only one driver should be enabled at any time. It is important, therefore, that the remaining disabled drivers do not load the bus. To ensure this, the ADM485 driver features high output impedance when disabled and when powered down, which minimizes the loading effect when the transceiver is not being used. The high impedance driver output is maintained over the common-mode voltage range of −7 V to +12 V .Figure 1.The receiver contains a fail-safe feature that results in a logic high output state if the inputs are unconnected (floating). The ADM485 is fabricated on BiCMOS, an advanced mixed technology process combining low power CMOS with fast switching bipolar technology. All inputs and outputs contain protection against ESD; all driver outputs feature high source and sink current capability. An epitaxial layer is used to guard against latch-up.The ADM485 features extremely fast switching speeds. Minimal driver propagation delays permit transmission at data rates up to 5 Mbps while low skew minimizes EMI interference. The part is fully specified over the commercial and industrial temperature range and is available in 8-lead PDIP , 8-lead SOIC, and small footprint, 8-lead MSOP packages.ADM485Rev. F | Page 2 of 16ADM485SPECIFICATIONSV CC = 5 V ± 5%, all specifications T MIN to T MAX, unless otherwise noted.Rev. F | Page 3 of 16ADM485TIMING SPECIFICATIONSV CC = 5 V ± 5%, all specifications T MIN to T MAX, unless otherwise noted.1 Guaranteed by characterization.Rev. F | Page 4 of 16ADM485Rev. F | Page 5 of 16ABSOLUTE MAXIMUM RATINGST A = 25°C, unless otherwise noted.Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Table 4. TransmittingInputsOutputsDE DIB A 1 1 0 1 1 0 1 0 0X 1Z 2Z 21 X = don’t care.2Z = high impedance.1 X = don’t care.2Z = high impedance.ESD CAUTION。

MEMORY存储芯片MAX485EESA中文规格书

General Description The MAX481E, MAX483E, MAX485E, MAX487E–MAX491E, and MAX1487E are low-power transceivers for RS-485 and RS-422 communications in harsh environ-ments. Each driver output and receiver input is protected against ±15kV electro-static discharge (ESD) shocks, without latchup. These parts contain one driver and one receiver. The MAX483E, MAX487E, MAX488E, and MAX489E feature reduced slew-rate drivers that minimize EMI and reduce reflections caused by improperly termi-nated cables, thus allowing error-free data transmission up to 250kbps. The driver slew rates of the MAX481E, MAX485E, MAX490E, MAX491E, and MAX1487E are not limited, allowing them to transmit up to 2.5Mbps.These transceivers draw as little as 120µA supply cur-rent when unloaded or when fully loaded with disabled drivers (see Selector Guide). Additionally, the MAX481E, MAX483E, and MAX487E have a low-current shutdown mode in which they consume only 0.5µA. All parts oper-ate from a single +5V supply.Drivers are short-circuit current limited, and are protected against excessive power dissipation by thermal shutdown circuitry that places their outputs into a high-impedance state. The receiver input has a fail-safe feature that guar-antees a logic-high output if the input is open circuit.The MAX487E and MAX1487E feature quarter-unit-load receiver input impedance, allowing up to 128 trans-ceivers on the bus. The MAX488E–MAX491E are designed for full-duplex communications, while the MAX481E, MAX483E, MAX485E, MAX487E, and MAX1487E are designed for half-duplex applications. For applications that are not ESD sensitive see the pin-and function-compatible MAX481, MAX483, MAX485, MAX487–MAX491, and MAX1487.Applications Low-Power RS-485 TransceiversLow-Power RS-422 TransceiversLevel TranslatorsTransceivers for EMI-Sensitive ApplicationsIndustrial-Control Local Area NetworksNext-Generation Device Features ♦For Fault-Tolerant Applications:MAX3430: ±80V Fault-Protected, Fail-Safe, 1/4-Unit Load, +3.3V, RS-485 TransceiverMAX3080–MAX3089: Fail-Safe, High-Speed(10Mbps), Slew-Rate-Limited, RS-485/RS-422Transceivers♦For Space-Constrained Applications:MAX3460–MAX3464: +5V, Fail-Safe, 20Mbps,Profibus, RS-485/RS-422 TransceiversMAX3362: +3.3V, High-Speed, RS-485/RS-422Transceiver in a SOT23 PackageMAX3280E–MAX3284E: ±15kV ESD-Protected,52Mbps, +3V to +5.5V, SOT23, RS-485/RS-422True Fail-Safe ReceiversMAX3030E–MAX3033E: ±15kV ESD-Protected,+3.3V, Quad RS-422 Transmitters♦For Multiple Transceiver Applications:MAX3293/MAX3294/MAX3295: 20Mbps, +3.3V,SOT23, RS-485/RS-422 Transmitters♦For Fail-Safe Applications:MAX3440E–MAX3444E: ±15kV ESD-Protected,±60V Fault-Protected, 10Mbps, Fail-SafeRS-485/J1708 Transceivers♦For Low-Voltage Applications:MAX3483E/MAX3485E/MAX3486E/MAX3488E/MAX3490E/MAX3491E: +3.3V Powered, ±15kVESD-Protected, 12Mbps, Slew-Rate-Limited,True RS-485/RS-422 Transceivers±15kV ESD-Protected, Slew-Rate-Limited, Low-Power, RS-485/RS-422 TransceiversOrdering InformationOrdering Information continued at end of data sheet.Selector Guide appears at end of data sheet.±15kV ESD-Protected, Slew-Rate-Limited,Low-Power, RS-485/RS-422 Transceivers__________Function Tables (MAX481E/MAX483E/MAX485E/MAX487E/MAX1487E)Table 1. TransmittingTable 2. Receivingneers developed state-of-the-art structures to protect these pins against ESD of ±15kV without damage. The ESD structures withstand high ESD in all states: normal operation, shutdown, and powered down. After an ESD event, Maxim’s MAX481E, MAX483E, MAX485E, MAX487E–MAX491E, and MAX1487E keep working without latchup.ESD protection can be tested in various ways; the transmitter outputs and receiver inputs of this product family are characterized for protection to ±15kV using the Human Body Model.Other ESD test methodologies include IEC10004-2 con-tact discharge and IEC1000-4-2 air-gap discharge (for-merly IEC801-2).ESD Test ConditionsESD performance depends on a variety of conditions.Contact Maxim for a reliability report that documents test set-up, test methodology, and test results.Human Body ModelF igure 4 shows the Human Body Model, and F igure 5shows the current waveform it generates when dis-charged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of inter-est, which is then discharged into the test device through a 1.5k Ωresistor.IEC1000-4-2The IEC1000-4-2 standard covers ESD testing and per-formance of finished equipment; it does not specifically refer to integrated circuits (Figure 6).MAX481E/MAX483E/MAX485E/ MAX487E–MAX491E/MAX1487E__________Applications InformationThe MAX481E/MAX483E/MAX485E/MAX487E–MAX491E and MAX1487E are low-power transceivers for RS-485 and RS-422 communications. These “E” versions of the MAX481, MAX483, MAX485, MAX487–MAX491, and MAX1487 provide extra protection against ESD. The rugged MAX481E, MAX483E, MAX485E, MAX497E–MAX491E, and MAX1487E are intended for harsh envi-ronments where high-speed communication is important. These devices eliminate the need for transient suppres-sor diodes and the associated high capacitance loading.The standard (non-“E”) MAX481, MAX483, MAX485, MAX487–MAX491, and MAX1487 are recommended for applications where cost is critical.The MAX481E, MAX485E, MAX490E, MAX491E, and MAX1487E can transmit and receive at data rates up to 2.5Mbps, while the MAX483E, MAX487E, MAX488E, and MAX489E are specified for data rates up to 250kbps. The MAX488E–MAX491E are full-duplex transceivers, while the MAX481E, MAX483E, MAX487E, and MAX1487E are half-duplex. In addition, driver-enable (DE) and receiver-enable (RE) pins are included on the MAX481E, MAX483E, MAX485E, MAX487E, MAX489E, MAX491E, and MAX1487E. When disabled, the driver and receiver outputs are high impedance.±15kV ESD ProtectionAs with all Maxim devices, ESD-protection structures are incorporated on all pins to protect against electro-static discharges encountered during handling and assembly. The driver outputs and receiver inputs have extra protection against static electricity. Maxim’s engi-±15kV ESD-Protected, Slew-Rate-Limited,Low-Power, RS-485/RS-422 TransceiversFigure 6. IEC1000-4-2 ESD Test ModelFigure 8. Driver DC Test LoadFigure 7. IEC1000-4-2 ESD Generator Current WaveformFigure 9. Receiver Timing Test LoadFigure 4. Human Body ESD Test ModelFigure 5. Human Body Model Current WaveformMAX481E/MAX483E/MAX485E/ MAX487E–MAX491E/MAX1487E±15kV ESD-Protected, Slew-Rate-Limited,Low-Power, RS-485/RS-422 Transceiversdelay times. Typical propagation delays are shown in Figures 19–22 using Figure 18’s test circuit.The difference in receiver delay times, t PLH - t PHL , is typically under 13ns for the MAX481E, MAX485E,MAX490E, MAX491E, and MAX1487E, and is typically less than 100ns for the MAX483E and MAX487E–MAX489E.The driver skew times are typically 5ns (10ns max) for the MAX481E, MAX485E, MAX490E, MAX491E, and MAX1487E, and are typically 100ns (800ns max) for the MAX483E and MAX487E–MAX489E.Typical ApplicationsThe MAX481E, MAX483E, MAX485E, MAX487E–MAX491E, and MAX1487E transceivers are designed for bidirectional data communications on multipoint bus transmission lines. F igures 25 and 26 show typical net-work application circuits. These parts can also be used as line repeaters, with cable lengths longer than 4000 feet.To minimize reflections, the line should be terminated at both ends in its characteristic impedance, and stub lengths off the main line should be kept as short as possi-ble. The slew-rate-limited MAX483E and MAX487E–MAX489E are more tolerant of imperfect termination.Bypass the V CC pin with 0.1µF.Isolated RS-485For isolated RS-485 applications, see the MAX253 and MAX1480 data sheets.Line Length vs. Data RateThe RS-485/RS-422 standard covers line lengths up to 4000 feet. Figures 23 and 24 show the system differen-tial voltage for the parts driving 4000 feet of 26AWG twisted-pair wire at 110kHz into 100Ωloads.Figure 18. Receiver Propagation Delay Test CircuitIt takes the drivers and receivers longer to become enabled from the low-power shutdown state (t ZH(SHDN ), t ZL(SHDN)) than from the operating mode (t ZH , t ZL ). (The parts are in operating mode if the RE, DE inputs equal a logical 0,1 or 1,1 or 0, 0.)Driver Output ProtectionExcessive output current and power dissipation caused by faults or by bus contention are prevented by two mechanisms. A foldback current limit on the output stage provides immediate protection against short circuits over the whole common-mode voltage range (see Typical Operating Characteristics ). In addition, a thermal shut-down circuit forces the driver outputs into a high-imped-ance state if the die temperature rises excessively.Propagation DelayMany digital encoding schemes depend on the differ-。

MEMORY存储芯片NANDDBR4N5BZCC5EIF中文规格书

Figure 59: Consecutive WRITE-to-WRITECKCK#CommandAddressDQDQS, DQS#DMDon’t Care Transitioning Data t DQSS (NOM)Notes: 1.Subsequent rising DQS signals must align to the clock within t DQSS.2.DI b , etc. = data-in for column b , etc.3.Three subsequent elements of data-in are applied in the programmed order following DI b .4.Three subsequent elements of data-in are applied in the programmed order following DI n .5.Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.6.Each WRITE command may be to any bank.Figure 60: Nonconsecutive WRITE-to-WRITECKCK#CommandAddressT0T1T2T3T2n T4T5T4n T3n T5n T6T6nDQDQS, DQS#DM t Don’t CareTransitioning Data Notes: 1.Subsequent rising DQS signals must align to the clock within t DQSS.2.DI b (or n ), etc. = data-in for column b (or column n ).3.Three subsequent elements of data-in are applied in the programmed order following DI b .4.Three subsequent elements of data-in are applied in the programmed order following DI n .5.Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.6.Each WRITE command may be to any bank.2Gb: x4, x8, x16 DDR2 SDRAM WRITETable 28: AC Input Test Conditions (Continued)Notes: 1.All voltages referenced to V SS .2.Input waveform setup timing (t IS b ) is referenced from the input signal crossing at the V IH(AC) level for a rising signal and V IL(AC) for a falling signal applied to the device under test, as shown in Figure 32 (page 70).3.See Input Slew Rate Derating (page 59).4.The slew rate for single-ended inputs is measured from DC level to AC level, V IL(DC) to V IH(AC) on the rising edge and V IL(AC) to V IH(DC) on the falling edge. For signals referenced to V REF , the valid intersection is where the “tangent” line intersects V REF , as shown in Figure 25 (page 62), Figure 27 (page 63), Figure 29 (page 68), and Figure 31(page 69).5.Input waveform hold (t IH b ) timing is referenced from the input signal crossing at the V IL(DC) level for a rising signal and V IH(DC) for a falling signal applied to the device under test, as shown in Figure 32 (page 70).6.Input waveform setup timing (t DS) and hold timing (t DH) for single-ended data strobe is referenced from the crossing of DQS, UDQS, or LDQS through the Vref level applied to the device under test, as shown in Figure 34 (page 71).7.Input waveform setup timing (t DS) and hold timing (t DH) when differential data strobe is enabled is referenced from the cross-point of DQS/DQS#, UDQS/UDQS#, or LDQS/LDQS#, as shown in Figure 33 (page 70).8.Input waveform timing is referenced to the crossing point level (V IX ) of two input signals (V TR and V CP ) applied to the device under test, where V TR is the true input signal and V CP is the complementary input signal, as shown in Figure 35 (page 71).9.The slew rate for differentially ended inputs is measured from twice the DC level to twice the AC level: 2 × V IL(DC) to 2 × V IH(AC) on the rising edge and 2 × V IL(AC) to 2 ×V IH(DC) on the falling edge. For example, the CK/CK# would be –250mV to 500mV for CK rising edge and would be 250mV to –500mV for CK falling edge.2Gb: x4, x8, x16 DDR2 SDRAM AC Overshoot/Undershoot SpecificationFigure 5: Functional Block Diagram – 128 Meg x 162Gb: x4, x8, x16 DDR2 SDRAM Functional Block Diagrams。

MEMORY存储芯片MT48LC32M16A2P-75L中文规格书

PRECHARGEThe PRECHARGE command is used to deactivate the open row in a particular bank orthe open row in all banks. The bank(s) will be available for a subsequent row activationa specified time (t RP) after the PRECHARGE command is issued, except in the case ofconcurrent auto precharge, where a READ or WRITE command to a different bank is al-lowed as long as it does not interrupt the data transfer in the current bank and does notviolate any other timing parameters. After a bank has been precharged, it is in the idlestate and must be activated prior to any READ or WRITE commands being issued tothat bank. A PRECHARGE command is allowed if there is no open row in that bank (idlestate) or if the previously open row is already in the process of precharging. However,the precharge period will be determined by the last PRECHARGE command issued tothe bank.REFRESHREFRESH is used during normal operation of the DDR2 SDRAM and is analogous toCAS#-before-RAS# (CBR) REFRESH. All banks must be in the idle mode prior to issuinga REFRESH command. This command is nonpersistent, so it must be issued each timea refresh is required. The addressing is generated by the internal refresh controller. Thismakes the address bits a “Don’t Care” during a REFRESH command.SELF REFRESHThe SELF REFRESH command can be used to retain data in the DDR2 SDRAM, even ifthe rest of the system is powered down. When in the self refresh mode, the DDR2SDRAM retains data without external clocking. All power supply inputs (including Vref)must be maintained at valid levels upon entry/exit and during SELF REFRESH opera-tion.The SELF REFRESH command is initiated like a REFRESH command except CKE isLOW. The DLL is automatically disabled upon entering self refresh and is automaticallyenabled upon exiting self refresh.Mode Register (MR)The mode register is used to define the specific mode of operation of the DDR2 SDRAM.This definition includes the selection of a burst length, burst type, CAS latency, operat-ing mode, DLL RESET, write recovery, and power-down mode, as shown in Figure 36(page 79). Contents of the mode register can be altered by re-executing the LOADMODE (LM) command. If the user chooses to modify only a subset of the MR variables,all variables must be programmed when the command is issued.The MR is programmed via the LM command and will retain the stored information un-til it is programmed again or until the device loses power (except for bit M8, which isself-clearing). Reprogramming the mode register will not alter the contents of the mem-ory array, provided it is performed correctly.The LM command can only be issued (or reissued) when all banks are in the prechargedstate (idle state) and no bursts are in progress. The controller must wait the specifiedtime t MRD before initiating any subsequent operations such as an ACTIVATE com-mand. Violating either of these requirements will result in an unspecified operation.READ with auto precharge enabled/ WRITE with auto precharge enabled:The READ with auto precharge enabled or WRITE with auto pre-charge enabled states can each be broken into two parts: the ac-cess period and the precharge period. For READ with auto pre-charge, the precharge period is defined as if the same burst was executed with auto precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses all of the data in the burst. For WRITE with auto precharge, the pre-charge period begins when t WR ends, with t WR measured as if auto precharge was disabled. The access period starts with regis-tration of the command and ends where the precharge period (or t RP) begins. This device supports concurrent auto precharge such that when a READ with auto precharge is enabled or a WRITE with auto precharge is enabled, any command to other banks is allowed, as long as that command does not interrupt the read or write data transfer already in process. In either case, all other related limitations apply (contention between read da-ta and write data must be avoided).The minimum delay from a READ or WRITE command with auto precharge enabled toa command to a different bank is summarized in Table 40 (page 76).4.REFRESH and LOAD MODE commands may only be issued when all banks are idle.5.Not used.6.All states and sequences not shown are illegal or reserved.7.READs or WRITEs listed in the Command/Action column include READs or WRITEs withauto precharge enabled and READs or WRITEs with auto precharge disabled.8. A WRITE command may be applied after the completion of the READ burst.9.Requires appropriate DM.10.The number of clock cycles required to meet t WTR is either two or t WTR/t CK, whicheveris greater.Table 40: Minimum Delay with Auto Precharge EnabledDESELECTThe DESELECT function (CS# HIGH) prevents new commands from being executed bythe DDR2 SDRAM. The DDR2 SDRAM is effectively deselected. Operations already inprogress are not affected. DESELECT is also referred to as COMMAND INHIBIT.。

MEMORY存储芯片MT48LC64M8A2P-75E中文规格书

Asynchronous ODT ModeAsynchronous ODT mode is selected when the DRAM runs in DLL-off mode. In asyn-chronous ODT timing mode, the internal ODT command is not delayed by either addi-tive latency (AL) or the parity latency (PL) relative to the external ODT signal (R TT(NOM)).In asynchronous ODT mode, two timing parameters apply: t AONAS (MIN/MAX), and t AOFAS (MIN/MAX).R TT(NOM) Turn-on Time•Minimum R TT(NOM) turn-on time (t AONAS [MIN]) is when the device termination cir-cuit leaves R TT(Park) and ODT resistance begins to turn on.•Maximum R TT(NOM) turn-on time (t AONAS [MAX]) is when the ODT resistance has reached R TT(NOM).•t AONAS (MIN) and t AONAS (MAX) are measured from ODT being sampled HIGH.R TT(NOM) Turn-off Time•Minimum R TT(NOM) turn-off time (t AOFAS [MIN]) is when the device's termination circuit starts to leave R TT(NOM).•Maximum R TT(NOM) turn-off time (t AOFAS [MAX]) is when the on-die termination has reached R TT(Park).•t AOFAS (MIN) and t AOFAS (MAX) are measured from ODT being sampled LOW.Figure 208: Asynchronous ODT Timings with DLL Offdiff_CKCKEODTR TT T1T0T2T3T4T5T6Ti Ti + 1Ti + 2Ti + 3Ti + 4Ti + 5Ti + 6Ta TbTransitioningWRITE OperationWrite Timing DefinitionsThe write timings shown in the following figures are applicable in normal operation mode, that is, when the DLL is enabled and locked.Write Timing – Clock-to-Data Strobe RelationshipThe clock-to-data strobe relationship is shown below and is applicable in normal oper-ation mode, that is, when the DLL is enabled and locked.Rising data strobe edge parameters:•t DQSS (MIN) to t DQSS (MAX) describes the allowed range for a rising data strobe edge relative to CK.•t DQSS is the actual position of a rising strobe edge relative to CK.•t DQSH describes the data strobe high pulse width.•t WPST strobe going to HIGH, nondrive level (shown in the postamble section of the graphic below).Falling data strobe edge parameters:•t DQSL describes the data strobe low pulse width.•t WPRE strobe going to LOW, initial drive level (shown in the preamble section of the graphic below).4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation。

MEMORY存储芯片MT48LC16M16A2P-7EIT G中文规格书

If the DLL is enabled prior to entering self refresh mode, the DLL is automatically disa-bled when entering the SELF REFRESH operation and is automatically re-enabled and reset upon exit of the SELF REFRESH operation. If the DLL is disabled prior to entering self refresh mode, the DLL remains disabled, even upon exit of the SELF REFRESH oper-ation until it is re-enabled and reset.The DRAM is not tested to check—nor does Micron warrant compliance with—normal mode timings or functionality when the DLL is disabled. An attempt has been made to have the DRAM operate in the normal mode where reasonably possible when the DLL has been disabled; however, by industry standard, a few known exceptions are defined:•ODT is not allowed to be used.•The output data is no longer edge-aligned to the clock.•CL and CWL can only be six clocks.When the DLL is disabled, timing and functionality can vary from the normal operation specifications when the DLL is enabled (see DLL Disable Mode in Commands section of the data sheet for more information). Disabling the DLL also implies the need to change the clock frequency (see Input Clock Frequency Change section of the data sheet for de-tails).Output Drive StrengthThe DDR3 SDRAM uses a programmable impedance output buffer. The drive strength mode register setting is defined by MR1[5, 1]. RZQ/7 (34Ω [NOM]) is the primary output driver impedance setting for DDR3 SDRAM devices. To calibrate the output driver im-pedance, an external precision resistor (RZQ) is connected between the ZQ ball and V SSQ . The value of the resistor must be 240ΩThe output impedance is set during initialization. Additional impedance calibration up-dates do not affect device operation, and all data sheet timings and current specifica-tions are met during an update.To meet the 34Ω specification, the output drive strength must be set to 34Ω during initi-alization. To obtain a calibrated output driver impedance after power-up, the DDR3SDRAM needs a calibration command that is part of the initialization and reset proce-dure.OUTPUT ENABLE/DISABLEThe OUTPUT ENABLE/DISABLE function is defined by MR1[12] (see Figure 52(page 144)). When enabled (MR1[12] = 0), all outputs (DQ, DQS, DQS#) function when in the normal mode of operation. When disabled (MR1[12] = 1), all DDR3 SDRAM out-puts (DQ and DQS, DQS#) are High-Z. The output disable feature is intended to be used during I DD characterization of the READ current and during t DQSS margining (write leveling) only.TDQS ENABLETermination data strobe (TDQS) is a function of the x8 DDR3 SDRAM configuration that provides termination resistance R TT , and can be useful in some system configura-tions. TDQS is not supported in x4 or x16 configurations. When enabled via the mode register (MR1[11]), R TT applied to DQS and DQS# is also applied to TDQS and TDQS#.In contrast to the RDQS function of DDR2 SDRAM, DDR3’s TDQS provides the termina-tion resistance R TT only. The OUTPUT DATA STROBE function of RDQS is not provided2Gb: x4, x8, x16 DDR3L SDRAM Mode Register 1 (MR1)Figure 41: DLL Disable t DQSCKDon’t CareTransitioning Data CKCK#Command Address DQ BL8 DLL onDQS, DQS# DLL onDQ BL8 DLL disable DQS, DQS# DLL offDQ BL8 DLL disable DQS, DQS# DLL offTable 91: READ Electrical Characteristics, DLL Disable Mode。

MEMORY存储芯片MT48LC64M8A2P-7E中文规格书

Figure 76: hPPR WRA – Repair and ExitDon’t CarehPPR Row Repair – WR Initiated (REF Commands NOT Allowed)1.Issue an ACT command with failing BG and BA with the row address to be re-paired.2.Issue a WR command with BG and BA of failing row address.a.The address must be at valid levels, but the address is "Don't Care."3.All DQ of the target DRAM should be driven LOW for 4n CK (bit 0 through bit 7)after WL (WL = CWL + AL + PL) in order for hPPR to initiate repair.a.Repair will be initiated to the target DRAM only if all DQ during bit 0 through bit 7 are LOW.b.Repair will not be initiated to the target DRAM if any DQ during bit 0 through bit 7 is HIGH.1.JEDEC states: All DQs of target DRAM should be LOW for 4t CK. If HIGH is driven to all DQs of a DRAM consecutively for equal to or longer than2t CK, then DRAM does not conduct hPPR and retains data if REF com-mand is properly issued; if all DQs are neither LOW for 4t CK nor HIGHfor equal to or longer than 2t CK, then hPPR mode execution is un-known.c.DQS should function normally.4.REF commands may NOT be issued at anytime while in PPT mode.5.Issue PRE after t PGM time so that the device can repair the target row during t PGM time.a.Wait t PGM_Exit after PRE to allow the device to recognize the repaired target row address.6.Issue MR4[13] 0 command to hPPR mode disable.a.Wait t PGMPST for hPPR mode exit to complete.b.After t PGMPST has expired, any valid command may be issued.The entire sequence from hPPR mode enable through hPPR mode disable may be re-peated if more than one repair is to be done.After completing hPPR mode, MR0 must be re-programmed to a prehPPR mode state if the device is to be accessed.After hPPR mode has been exited, the DRAM controller can confirm if the target row was repaired correctly by writing data into the target row and reading it back.4Gb: x4, x8, x16 DDR4 SDRAM Post Package RepairDDR4 READ commands support bursts of BL8 (fixed), BC4 (fixed), and BL8/BC4 on-the-fly (OTF); OTF uses address A12 to control OTF when OTF is enabled:•A12 = 0, BC4 (BC4 = burst chop)•A12 = 1, BL8READ commands can issue precharge automatically with a READ with auto precharge command (RDA), and is enabled by A10 HIGH:•READ command with A10 = 0 (RD) performs standard read, bank remains active after READ burst.•READ command with A10 = 1 (RDA) performs read with auto precharge, bank goes in to precharge after READ burst.Figure 130: READ Burst Operation, RL = 11 (AL = 0, CL = 11, BL8)T0T1T2Ta1Ta0Ta2Ta3Ta4Ta5Ta6Ta7Ta8Ta9CommandDQCK_tCK_cDon’t CareTransitioning Data Bank GroupAddressDQS_tDQS_cAddress Notes: 1.BL8, RL = 0, AL = 0, CL = 11, Preamble = 1t CK.2.DO n = data-out from column n .3.DES commands are shown for ease of illustration; other commands may be valid at these times.4.BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ command at T0.5.CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.。

MEMORY存储芯片MT48LC32M8A2TG-75IT中文规格书

AC and DC Logic Input Measurement Levels for Single-Ended Signals Table 63: Single-Ended AC and DC Input Levels for CA and CS# InputsNotes: 1.For CA and CS# input-only pins. V REF = V REFCA(DC).2.See Overshoot and Undershoot Definition.3.The AC peak noise on V REFCA could prevent V REFCA from deviating more than ±1% V DDCAfrom V REFCA(DC) (for reference, approximately ±12mV).4.For reference, approximately V DDCA /2 ±12mV.Table 64: Single-Ended AC and DC Input Levels for CKENote: 1.See Overshoot and Undershoot Definition.Table 65: Single-Ended AC and DC Input Levels for DQ and DMNotes: 1.For DQ input-only pins. V REF = V REFDQ(DC).2.See Overshoot and Undershoot Definition.3.The AC peak noise on V REFDQ could prevent V REFDQ from deviating more than ±1% V DDQfrom V REFDQ(DC) (for reference, approximately ±12mV).4.For reference, approximately. V DDQ /2 ±12mV.Preliminary1Gb: x16, x32 Automotive Mobile LPDDR2 SDRAM AC and DC Logic Input Measurement Levels for Single-Ended SignalsFigure 61: MRR Command to Power-Down EntryCK#CKCKE 1CMD DQ DQS#DQSNote: 1.CKE can be registered LOW at (RL + RU(t DQSCK/t CK)+ BL/2 + 1) clock cycles after theclock on which the MRR command is registered.Figure 62: MRW Command to Power-Down Entry CK#CKCKE 1CMD Note: 1.CKE can be registered LOW t MRW after the clock on which the MRW command is regis-tered.Deep Power-DownDeep power-down (DPD) is entered when CKE is registered LOW with CS# LOW, CA0HIGH, CA1 HIGH, and CA2 LOW at the rising edge of the clock. The NOP command must be driven in the clock cycle following power-down entry. CKE must not go LOW while MRR or MRW operations are in progress. CKE can go LOW while other operations such as ACTIVATE, auto precharge, PRECHARGE, or REFRESH are in progress, however,deep power-down I DD specifications will not be applied until those operations com-plete. The contents of the array will be lost upon entering DPD mode.In DPD mode, all input buffers except CKE, all output buffers, and the power supply to internal circuitry are disabled within the device. V REFDQ can be at any level between 0and V DDQ , and V REFCA can be at any level between 0 and V DDCA during DPD. All power Preliminary1Gb: x16, x32 Automotive Mobile LPDDR2 SDRAM Deep Power-Down。

MEMORY存储芯片MT48LC8M32LFB5-8IT中文规格书

When write leveling is enabled, the rising edge of DQS samples CK, and the prime DQoutputs the sampled CK’s status. The prime DQ for a x4 or x8 configuration is DQ0 withall other DQ (DQ[7:1]) driving LOW. The prime DQ for a x16 configuration is DQ0 for thelower byte and DQ8 for the upper byte. It outputs the status of CK sampled by LDQSand UDQS. All other DQ (DQ[7:1], DQ[15:9]) continue to drive LOW. Two prime DQ on ax16 enable each byte lane to be leveled independently.The write leveling mode register interacts with other mode registers to correctly config-ure the write leveling functionality. Besides using MR1[7] to disable/enable write level-ing, MR1[12] must be used to enable/disable the output buffers. The ODT value, burstlength, and so forth need to be selected as well. This interaction is shown in Table 71. Itshould also be noted that when the outputs are enabled during write leveling mode, theDQS buffers are set as inputs, and the DQ are set as outputs. Additionally, during writeleveling mode, only the DQS strobe terminations are activated and deactivated via theODT ball. The DQ remain disabled and are not affected by the ODT ball.Table 71: Write Leveling MatrixNotes: 1.Expected usage if used during write leveling: Case 1 may be used when DRAM are on adual-rank module and on the rank not being leveled or on any rank of a module notbeing leveled on a multislot system. Case 2 may be used when DRAM are on any rank ofa module not being leveled on a multislot system. Case 3 is generally not used. Case 4 isgenerally used when DRAM are on the rank that is being leveled.2.Since the DRAM DQS is not being driven (MR1[12] = 1), DQS ignores the input strobe,and all R TT,nom values are allowed. This simulates a normal standby state to DQS.3.Since the DRAM DQS is being driven (MR1[12] = 0), DQS captures the input strobe, andonly some R TT,nom values are allowed. This simulates a normal write state to DQS.Figure 53: READ Latency (AL = 5, CL = 6)CKCK#CommandDQDQS, DQS#BC4Address busNote: 1.MR2[18, 15:11, 8, and 2:0] are reserved for future use and must all be programmed to 0.CAS WRITE Latency (CWL)CWL is defined by MR2[5:3] and is the delay, in clock cycles, from the releasing of the internal write to the latching of the first data in. CWL must be correctly set to the corre-sponding operating clock frequency (see Figure 54 (page 136)). The overall WRITE la-tency (WL) is equal to CWL + AL (Figure 52 (page 132)).Figure 55: CAS WRITE LatencyCKCK#CommandDQDQS, DQS#Don’t CareIndicates break in time scaleTransitioning Data AUTO SELF REFRESH (ASR)Mode register MR2[6] is used to disable/enable the ASR function. When ASR is disabled,the self refresh mode’s refresh rate is assumed to be at the normal 85°C limit (some-times referred to as 1x refresh rate). In the disabled mode, ASR requires the user to en-and t RP is met). When the MPR is enabled, any subsequent READ or RDAP commandsare redirected to the multipurpose register. The resulting operation when either a READor a RDAP command is issued, is defined by MR3[1:0] when the MPR is enabled (seeTable 74 (page 140)). When the MPR is enabled, only READ or RDAP commands are al-lowed until a subsequent MRS command is issued with the MPR disabled (MR3[2] = 0).Power-down mode, self refresh, and any other nonREAD/RDAP commands are not al-lowed during MPR enable mode. The RESET function is supported during MPR enablemode.Figure 57: Multipurpose Register (MPR) Block DiagramNotes: 1. A predefined data pattern can be read out of the MPR with an external READ com-mand.2.MR3[2] defines whether the data flow comes from the memory core or the MPR. Whenthe data flow is defined, the MPR contents can be read out continuously with a regularREAD or RDAP command.Table 73: MPR Functional Description of MR3 BitsMPR Functional DescriptionThe MPR JEDEC definition enables either a prime DQ (DQ0 on a x4 and a x8; on a x16,DQ0 = lower byte and DQ8 = upper byte) to output the MPR data with the remainingDQs driven LOW, or for all DQs to output the MPR data . The MPR readout supportsfixed READ burst and READ burst chop (MRS and OTF via A12/BC#) with regular READlatencies and AC timings applicable, provided the DLL is locked as required.ZQ CALIBRATION OperationThe ZQ CALIBRATION command is used to calibrate the DRAM output drivers (R ON )and ODT values (R TT ) over process, voltage, and temperature, provided a dedicated 240Ω (±1%) external resistor is connected from the DRAM’s ZQ ball to V SSQ .DDR3 SDRAM require a longer time to calibrate R ON and ODT at power-up initialization and self refresh exit, and a relatively shorter time to perform periodic calibrations.DDR3 SDRAM defines two ZQ CALIBRATION commands: ZQCL and ZQCS. An example of ZQ calibration timing is shown below.All banks must be precharged and t RP must be met before ZQCL or ZQCS commands can be issued to the DRAM. No other activities (other than issuing another ZQCL or ZQCS command) can be performed on the DRAM channel by the controller for the du-ration of t ZQinit or t ZQoper. The quiet time on the DRAM channel helps accurately cali-brate R ON and ODT. After DRAM calibration is achieved, the DRAM should disable the ZQ ball’s current consumption path to reduce power.ZQ CALIBRATION commands can be issued in parallel to DLL RESET and locking time.Upon self refresh exit, an explicit ZQCL is required if ZQ calibration is desired.In dual-rank systems that share the ZQ resistor between devices, the controller must not enable overlap of t ZQinit, t ZQoper, or t ZQCS between ranks.Figure 62: ZQ CALIBRATION Timing (ZQCL and ZQCS)Command Indicates break in time scaleT0T1Ta0Ta1Ta2Ta3Tb0Tb1Tc0Tc1Tc2AddressA10CKCK#Don’t CareDQODT CKE Notes:1.CKE must be continuously registered HIGH during the calibration procedure.2.ODT must be disabled via the ODT signal or the MRS during the calibration procedure.3.All devices connected to the DQ bus should be High-Z during calibration.。

MEMORY存储芯片MT48V8M32LFB5-10中文规格书

MRS (that is, persistent mode), the DRAM will not write bad data to the core when a CRC error is detected.DBI_n and CRC Both EnabledThe DRAM computes the CRC for received written data D[71:0]. Data is not inverted back based on DBI before it is used for computing CRC. The data is inverted back based on DBI before it is written to the DRAM core.DM_n and CRC Both EnabledWhen both DM and write CRC are enabled in the DRAM mode register, the DRAM cal-culates CRC before sending the write data into the array. If there is a CRC error, the DRAM blocks the WRITE operation and discards the data. The Nonconsecutive WRITE (BL8/BC4-OTF) with 2t CK Preamble and Write CRC in Same or Different Bank Group and the WRITE (BL8/BC4-OTF/Fixed) with 1t CK Preamble and Write CRC in Same or Different BankGroup figures in the WRITE Operation section show timing differences when DM is enabled.DM_n and DBI_n Conflict During Writes with CRC EnabledBoth write DBI_n and DM_n can not be enabled at the same time; read DBI_n and DM_n can be enabled at the same time.CRC and Write Preamble RestrictionsWhen write CRC is enabled:•And 1t CK WRITE preamble mode is enabled, a t CCD_S or t CCD_L of 4 clocks is not allowed.•And 2t CK WRITE preamble mode is enabled, a t CCD_S or t CCD_L of 6 clocks is not allowed.CRC Simultaneous Operation RestrictionsWhen write CRC is enabled, neither MPR writes nor per-DRAM mode is allowed.CRC PolynomialThe CRC polynomial used by DDR4 is the ATM-8 HEC, X 8 + X 2 + X 1 + 1.A combinatorial logic block implementation of this 8-bit CRC for 72 bits of data in-cludes 272 two-input XOR gates contained in eight 6-XOR-gate-deep trees.The CRC polynomial and combinatorial logic used by DDR4 is the same as used on GDDR5.The error coverage from the DDR4 polynomial used is shown in the following table.Table 53: CRC Error Detection Coverage4Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data FeatureCommand Address LatencyDDR4 supports the command address latency (CAL) function as a power savings fea-ture. This feature can be enabled or disabled via the MRS setting. CAL timing is defined as the delay in clock cycles (t CAL) between a CS_n registered LOW and its correspond-ing registered command and address. The value of CAL in clocks must be programmed into the mode register (see MR1 Register Definition table) and is based on the equation t CK(ns)/t CAL(ns), rounded up in clocks.Figure 26: CAL Timing DefinitionCLKCMD/ADDRCS_nCAL gives the DRAM time to enable the command and address receivers before a com-mand is issued. After the command and the address are latched, the receivers can be disabled if CS_n returns to HIGH. For consecutive commands, the DRAM will keep the command and address input receivers enabled for the duration of the command se-quence.Figure 27: CAL Timing Example (Consecutive CS_n = LOW)CLKCMD/ADDR CS_n4Gb: x4, x8, x16 DDR4 SDRAM Command Address Latency。

半导体传感器ADM4857ARZ中文规格书

ADuM1400/ADuM1401/ADuM1402 Data SheetELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V, 105°C OPERATION15 V/3 V operation: 4.5 V ≤ V DD1 ≤ 5.5 V, 2.7 V ≤ V DD2 ≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ V DD1 ≤ 3.6 V, 4.5 V ≤ V DD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at T A = 25°C; V DD1 = 3.0 V, V DD2 = 5 V or V DD1 = 5 V, V DD2 = 3.0 V. These specifications do not apply to ADuM1400W, ADuM1401W, and ADuM1402W automotive grade versions.Table 3.Parameter Symbol Min Typ Max Unit Test ConditionsDC SPECIFICATIONSInput Supply Current per Channel, Quiescent I DDI (Q)5 V/3 V Operation 0.50 0.53 mA3 V/5 V Operation 0.26 0.31 mAOutput Supply Current per Channel, Quiescent I DDO (Q)5 V/3 V Operation 0.11 0.14 mA3 V/5 V Operation 0.19 0.21 mAADuM1400 Total Supply Current, Four Channels2DC to 2 MbpsV DD1 Supply Current I DD1 (Q)5 V/3 V Operation 2.2 2.8 mA DC to 1 MHz logic signal freq.3 V/5 V Operation 1.2 1.9 mA DC to 1 MHz logic signal freq.V DD2 Supply Current I DD2 (Q)5 V/3 V Operation 0.5 0.9 mA DC to 1 MHz logic signal freq.3 V/5 V Operation 0.9 1.4 mA DC to 1 MHz logic signal freq.10 Mbps (BRW and CRW Grades Only)V DD1 Supply Current I DD1 (10)5 V/3 V Operation 8.6 10.6 mA 5 MHz logic signal freq.3 V/5 V Operation 4.5 6.5 mA 5 MHz logic signal freq.V DD2 Supply Current I DD2 (10)5 V/3 V Operation 1.4 2.0 mA 5 MHz logic signal freq.3 V/5 V Operation 2.6 3.5 mA 5 MHz logic signal freq.90 Mbps (CRW Grade Only)V DD1 Supply Current I DD1 (90)5 V/3 V Operation 70 100 mA 45 MHz logic signal freq.3 V/5 V Operation 37 65 mA 45 MHz logic signal freq.V DD2 Supply Current I DD2 (90)5 V/3 V Operation 11 15 mA 45 MHz logic signal freq.3 V/5 V Operation 18 25 mA 45 MHz logic signal freq.ADuM1401 Total Supply Current, Four Channels2DC to 2 MbpsV DD1 Supply Current I DD1 (Q)5 V/3 V Operation 1.8 2.4 mA DC to 1 MHz logic signal freq.3 V/5 V Operation 1.0 1.6 mA DC to 1 MHz logic signal freq.V DD2 Supply Current I DD2 (Q)5 V/3 V Operation 0.7 1.2 mA DC to 1 MHz logic signal freq.3 V/5 V Operation 1.2 1.8 mA DC to 1 MHz logic signal freq.10 Mbps (BRW and CRW Grades Only)V DD1 Supply Current I DD1 (10)5 V/3 V Operation 7.1 9.0 mA 5 MHz logic signal freq.3 V/5 V Operation 3.7 5.4 mA5 MHz logic signal freq.V DD2 Supply Current I DD2 (10)5 V/3 V Operation 2.2 3.0 mA 5 MHz logic signal freq.3 V/5 V Operation 4.1 5.0 mA 5 MHz logic signal freq.Rev. L | Page 8 of 31ADuM1400/ADuM1401/ADuM1402Data Sheet Rev. L | Page 12 of 31 ParameterSymbol Min Typ Max Unit Test Conditions ADuM1400WTRWZ /ADuM1401WTRWZ /ADuM1402WTRWZMinimum Pulse Width 3PW 100 ns C L = 15 pF, CMOS signal levels Maximum Data Rate 410 Mbps C L = 15 pF, CMOS signal levels Propagation Delay 5t PHL , t PLH 18 27 34 ns C L = 15 pF, CMOS signal levels Pulse Width Distortion, |t PLH − t PHL |5PWD 3 ns C L = 15 pF, CMOS signal levels Change vs. Temperature5 ps/°C C L = 15 pF, CMOS signal levels Propagation Delay Skew 6t PSK 15 ns C L = 15 pF, CMOS signal levels Channel-to-Channel Matching, Codirectional Channels 7t PSKCD 3 ns C L = 15 pF, CMOS signal levels Channel-to-Channel Matching, Opposing-Directional Channels 7t PSKOD 6 ns C L = 15 pF, CMOS signal levels For All ModelsOutput Disable Propagation Delay (High/Lowto High Impedance)t PHZ , t PLH 6 8 ns C L = 15 pF, CMOS signal levels Output Enable Propagation Delay (HighImpedance to High/Low)t PZH , t PZL 6 8 ns C L = 15 pF, CMOS signal levels Output Rise/Fall Time (10% to 90%)t R /t F 2.5 ns C L = 15 pF, CMOS signal levels Common-Mode Transient Immunity at Logic High Output 8|CM H | 25 35 kV/µs V Ix = V DD1/V DD2, V CM = 1000 V, transient magnitude = 800 V Common-Mode Transient Immunity at Logic Low Output 8|CM L | 25 35 kV/µs V Ix = 0 V, V CM = 1000 V, transient magnitude = 800 V Refresh Ratef r 1.2 Mbps Input Dynamic Supply Current per Channel 9I DDI (D) 0.19 mA/Mbps Output Dynamic Supply Current per Channel 9I DDO (D) 0.05 mA/Mbps 1All voltages are relative to their respective ground. 2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total V DD1 and V DD2 supply currents as a function of data rate for ADuM1400W /ADuM1401W /ADuM1402W channel configurations. 3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.5 t PHL propagation delay is measured from the 50% level of the falling edge of the V Ix signal to the 50% level of the falling edge of the V Ox signal. t PLH propagation delay is measured from the 50% level of the rising edge of the V Ix signal to the 50% level of the rising edge of the V Ox signal.6 t PSK is the magnitude of the worst-case difference in t PHL or t PLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.8 CM H is the maximum common-mode voltage slew rate that can be sustained while maintaining V O > 0.8 V DD2. CM L is the maximum common-mode voltage slew rate that can be sustained while maintaining V O < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.。

MEMORY存储芯片NANDBAR4N4AZBB5EIF中文规格书

DQ[7:0]-2 DQ[7:0]-2
N/A DQS-2
WP#-2 WP#-2
Package Target 1 LUN 1
LUN 2
Target 2 LUN 1
LUN 2
Target 3 LUN 1
LUN 2
Target 4 LUN 1
LUN 2
R/B# R/B2# R/B3# R/B4#
Note: 1. LGA devices do not support the synchronous interface.
16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Asynchronous Interface Timing Diagrams
Figure 84: PROGRAM PAGE Operation with CE# “Don’t Care”
CLE CE# WE#
0
Seating plane A 0.1 A
See Note 1
Detail B2 Not to scale
Terminal A1 ID
Substrate material: plastic laminate. Mold compound: epoxy novolac.
Terminal A1 ID
OA
OB
OC
13 12 10
A
CTR CTR CTR
2 TYP OD
OE
OF
A
B
C
D
E
FA
G
18 ±0.1
H
J
K
L
M2 N TYP
2 TYP 10 CTR 14 ±0.1

MEMORY存储芯片MAX485EPA中文规格书

Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers2MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487ABSOLUTE MAXIMUM RATINGSSupply Voltage (V CC ) (12V)Control Input Voltage (RE , DE)...................-0.5V to (V CC + 0.5V)Driver Input Voltage (DI).............................-0.5V to (V CC + 0.5V)Driver Output Voltage (A, B)...................................-8V to +12.5VReceiver Input Voltage (A, B).................................-8V to +12.5VReceiver Output Voltage (RO)....................-0.5V to (V CC + 0.5V)Continuous Power Dissipation (T A = +70°C)8-Pin Plastic DIP (derate 9.09mW/°C above +70°C)....727mW14-Pin Plastic DIP (derate 10.00mW/°C above +70°C)..800mW8-Pin SO (derate 5.88mW/°C above +70°C).................471mW 14-Pin SO (derate 8.33mW/°C above +70°C)...............667mW 8-Pin µMAX (derate 4.1mW/°C above +70°C)..............830mW 8-Pin CERDIP (derate 8.00mW/°C above +70°C).........640mW 14-Pin CERDIP (derate 9.09mW/°C above +70°C).......727mW Operating Temperature Ranges MAX4_ _C_ _/MAX1487C_ A...............................0°C to +70°C MAX4__E_ _/MAX1487E_ A.............................-40°C to +85°C MAX4__M_/MAX1487MJA.............................-55°C to +125°C Storage Temperature Range.............................-65°C to +160°C Lead Temperature (soldering, 10sec).............................+300°C DC ELECTRICAL CHARACTERISTICS(V CC = 5V ±5%, T A = T MIN to T MAX , unless otherwise noted.) (Notes 1, 2)Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.V V IN = -7V V IN = 12V V IN = -7V V IN = 12V Input Current (A, B)I IN2V TH k Ω48-7V ≤V CM ≤12V, MAX487/MAX1487R INReceiver Input Resistance -7V ≤V CM ≤12V, all devices exceptMAX487/MAX1487R = 27Ω(RS-485), Figure 40.4V ≤V O ≤2.4VR = 50Ω(RS-422)I O = 4mA, V ID = -200mV I O = -4mA, V ID = 200mV V CM = 0V -7V ≤V CM ≤12V DE, DI, REDE, DI, RE MAX487/MAX1487,DE = 0V, V CC = 0V or 5.25VDE, DI, RE R = 27Ωor 50Ω, Figure 4R = 27Ωor 50Ω, Figure 4R = 27Ωor 50Ω, Figure 4DE = 0V;V CC = 0V or 5.25V,all devices exceptMAX487/MAX1487CONDITIONS k Ω12µA ±1I OZR Three-State (high impedance)Output Current at Receiver V 0.4V OL Receiver Output Low Voltage3.5V OH Receiver Output High VoltagemV 70ΔV TH Receiver Input HysteresisV -0.20.2Receiver Differential ThresholdVoltage-0.2mA 0.25mA -0.81.01.55V OD2Differential Driver Output(with load)V 2V 5V OD1Differential Driver Output (no load)µA ±2I IN1Input Current V 0.8V IL Input Low VoltageV 2.0V IH Input High VoltageV 0.2ΔV OD Change in Magnitude of DriverCommon-Mode Output Voltagefor Complementary Output StatesV 0.2ΔV OD Change in Magnitude of DriverDifferential Output Voltage forComplementary Output StatesV 3V OC Driver Common-Mode OutputVoltageUNITS MIN TYP MAX SYMBOL PARAMETERGeneral DescriptionThe MAX481, MAX483, MAX485, MAX487–MAX491, andMAX1487 are low-power transceivers for RS-485 and RS-422 communication. Each part contains one driver and onereceiver. The MAX483, MAX487, MAX488, and MAX489feature reduced slew-rate drivers that minimize E MI andreduce reflections caused by improperly terminated cables,thus allowing error-free data transmission up to 250kbps.The driver slew rates of the MAX481, MAX485, MAX490,MAX491, and MAX1487 are not limited, allowing them totransmit up to 2.5Mbps.These transceivers draw between 120µA and 500µA ofsupply current when unloaded or fully loaded with disableddrivers. Additionally, the MAX481, MAX483, and MAX487have a low-current shutdown mode in which they consumeonly 0.1µA. All parts operate from a single 5V supply.Drivers are short-circuit current limited and are protectedagainst excessive power dissipation by thermal shutdowncircuitry that places the driver outputs into a high-imped-ance state. The receiver input has a fail-safe feature thatguarantees a logic-high output if the input is open circuit.The MAX487 and MAX1487 feature quarter-unit-loadreceiver input impedance, allowing up to 128 MAX487/MAX1487 transceivers on the bus. Full-duplex communi-cations are obtained using the MAX488–MAX491, whilethe MAX481, MAX483, MAX485, MAX487, and MAX1487are designed for half-duplex applications.________________________Applications Low-Power RS-485 Transceivers Low-Power RS-422 Transceivers Level Translators Transceivers for EMI-Sensitive Applications Industrial-Control Local Area Networks__Next Generation Device Features o For Fault-Tolerant Applications MAX3430: ±80V Fault-Protected, Fail-Safe, 1/4Unit Load, +3.3V, RS-485 Transceiver MAX3440E–MAX3444E: ±15kV ESD-Protected,±60V Fault-Protected, 10Mbps, Fail-Safe, RS-485/J1708 Transceivers o For Space-Constrained Applications MAX3460–MAX3464: +5V, Fail-Safe, 20Mbps,Profibus RS-485/RS-422 Transceivers MAX3362: +3.3V, High-Speed, RS-485/RS-422Transceiver in a SOT23 Package MAX3280E–MAX3284E: ±15kV ESD-Protected,52Mbps, +3V to +5.5V, SOT23, RS-485/RS-422,True Fail-Safe Receivers MAX3293/MAX3294/MAX3295: 20Mbps, +3.3V,SOT23, RS-485/RS-422 Transmitters o For Multiple Transceiver Applications MAX3030E–MAX3033E: ±15kV ESD-Protected,+3.3V, Quad RS-422 Transmitters o For Fail-Safe Applications MAX3080–MAX3089: Fail-Safe, High-Speed (10Mbps), Slew-Rate-Limited RS-485/RS-422Transceiverso For Low-Voltage ApplicationsMAX3483E/MAX3485E/MAX3486E/MAX3488E/MAX3490E/MAX3491E: +3.3V Powered, ±15kVESD-Protected, 12Mbps, Slew-Rate-Limited,True RS-485/RS-422 TransceiversMAX481/MAX483/MAX485/MAX487–MAX491/MAX1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers ______________________________________________________________Selection Table 19-0122; Rev 10; 9/14PARTNUMBERHALF/FULL DUPLEX DATA RATE (Mbps) SLEW-RATE LIMITED LOW-POWER SHUTDOWN RECEIVER/DRIVER ENABLE QUIESCENT CURRENT (μA) NUMBER OF RECEIVERS ON BUS PIN COUNT MAX481Half 2.5No Yes Yes 300328MAX483Half 0.25Yes Yes Yes 120328MAX485Half 2.5No No Yes 300328MAX487Half 0.25Yes Yes Yes 1201288MAX488Full 0.25Yes No No 120328MAX489Full 0.25Yes No Yes 1203214MAX490Full 2.5No No No 300328MAX491Full 2.5No No Yes 3003214MAX1487 Half 2.5No No Yes 2301288Ordering Information appears at end of data sheet.。

MEMORY存储芯片NANDBAR3N8AZBB5EIF中文规格书

Table 9: Feature Address 01h: Timing ModeNotes: 1.Asynchronous timing mode 0 is the default, power-on value.2.If the synchronous interface is active, a RESET (FFh) command will change the timing mode and data interface bits of feature address 01h to their default values. If the asyn-chronous interface is active, a RESET (FFh) command will not change the values of the timing mode or data interface bits to their default valued.Table 10: Feature Addresses 10h and 80h: Programmable Output Drive Strength 16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Configuration OperationsFigure 69: PROTECT OTP AREA (80h-10h) OperationCycle type DQ[7:0]R/B#Note: 1.OTP data is protected following a status confirmation.READ OTP PAGE (00h-30h)The READ OTP PAGE (00h-30h) command is used to read data from the pages in the OTP area. To read data in the OTP area, the target must be in OTP operation mode.To use the READ OTP PAGE (00h-30h) command, issue the 00h command. Issue five address cycles including the column address, the page address within the OTP page range, and a block address of 0. Next, issue the 30h command. The selected die (LUN)will go busy (RDY = 0, ARDY = 0) for t R as data is transferred.To determine the progress of the data transfer, the host can monitor the target's R/B#signal, or alternatively the READ STATUS (70h) command can be used. If the status op-erations are used to monitor the die’s (LUN's) status, when the die (LUN) is ready (RDY = 1, ARDY = 1) the host disables status output and enables data output by issuing the READ MODE (00h) command. When the host requests data output, it begins at the col-umn address specified.Additional pages within the OTP area can be read by repeating the READ OTP PAGE (00h-30h) command.The READ OTP PAGE (00h-30h) command is compatible with the CHANGE READ COL-UMN (05h-E0h) command. Use of the READ STATUS ENHANCED (78h) and CHANGEREAD COLUMN ENHANCED (06h-E0h) commands are prohibited.Figure 70: READ OTP PAGE (00h-30h) OperationCycle type DQ[7:0]R/B#16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND One-Time Programmable (OTP) OperationsFigure 31: Synchronous Command CycleCLKALECLEDQSDQ[7:0]CE#W/R#Note: 1.When CE# remains LOW, t CAD begins at the rising edge of the clock from which thecommand cycle is latched for subsequent command, address, data input, or data output cycle(s).Synchronous AddressesA synchronous address is written from DQ[7:0] to the address register on the rising edge of CLK when CE# is LOW, ALE is HIGH, CLE is LOW, and W/R# is HIGH.After an address is latched—and prior to issuing the next command, address, or data I/O —the bus must go to bus idle mode on the next rising edge of CLK, except when the clock period, t CK, is greater than t CAD.Bits not part of the address space must be LOW (see Device and Array Organization).The number of address cycles required for each command varies. Refer to the com-mand descriptions to determine addressing requirements.Addresses are typically ignored by die (LUNs) that are busy (RDY = 0); however, some addresses such as address cycles that follow the READ STATUS ENHANCED (78h) com-mand, are accepted by die (LUNs), even when they are busy.16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Bus Operation – Synchronous Interface。

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The receiver contains a fail-safe feature that results in a logic high output state if the inputs are unconnected (floating).
The ADM485 is fabricated on BiCMOS, an advanced mixed technology process combining low power CMOS with fast switching bipolar technology. All inputs and outputs contain protection against ESD; all driver outputs feature high source and sink current capability. An epitaxial layer is used to guard against latch-up.
RECEIVER Differential Input Threshold Voltage, VTH Input Voltage Hysteresis, ∆VTH Input Resistance Input Current (A, B)
CMOS Input Logic Threshold Low, VINL CMOS Input Logic Threshold High, VINH Logic Enable Input Current (RE) CMOS Output Voltage Low, VOL CMOS Output Voltage High, VOH Short-Circuit Output Current Three-State Output Leakage Current
FEATURES Meets EIA RS-485 Standard 5 Mbps Data Rate Single 5 V Supply –7 V to +12 V Bus Common-Mode Range High Speed, Low Power BiCMOS Thermal Shutdown Protection Short-Circuit Protection Driver Propagation Delay: 10 ns Receiver Propagation Delay: 15 ns High Z Outputs with Power Off Superior Upgrade for LTC485
APPLICATIONS Low Power RS-485 Systems DTE-DCE Interface Packet Switching Local Area Networks Data Concentration Data Multiplexers Integrated Services Digital Network (ISDN)
V
R = 27 Ω (RS-485), Test Circuit 1
V
VTST = –7 V to +12 V, Test Circuit 2
V
R = 27 Ω or 50 Ω, Test Circuit 1
V
R = 27 Ω or 50 Ω, Test Circuit 1
V
R = 27 Ω or 50 Ω
ADM485
FUNCTIONAL BLOCK DIAGRAM
ADM485
RO
R
RE
DE
DI
D
VCC B A GND
GENERAL DESCRIPTION The ADM485 is a differential line transceiver suitable for high speed bidirectional data communication on multipoint bus transmission lines. It is designed for balanced data transmission and complies with EIA Standards RS-485 and RS-422. The part contains a differential line driver and a differential line receiver. Both the driver and the receiver may be enabled independently. When disabled, the outputs are three-stated.
This minimizes the loading effect when the transceiver is not being used. The high impedance driver output is maintained over the entire common-mode voltage range from –7 V to +12 V.
10 15 ns
1
5 ns
8
15 ns
10 25 ns
10 25 ns
0
2 ns
0
2 ns
15 30 ns
5 ns
5
20 s
5
20 ns
1
ns
1
ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Test Circuit 3 RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Test Circuit 3 RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Test Circuit 3 RL = 110 Ω, CL = 50 pF, Test Circuit 4 RL = 110 Ω, CL = 50 pF, Test Circuit 4 RL = 110 Ω, CL = 50 pF, Test Circuit 4*
35
250
35
250
0.8
2.0
± 1.0
–0.2
+0.2
70
12
1
–0.8
0.8
2.0
±1
0.4
4.0
7
85
± 1.0
1.0 2.2 0.6 1
Unit Test Conditions/Comments
V
R = ∞, Test Circuit 1
V
VCC = 5 V, R = 50 Ω (RS-422), Test Circuit 1
POWER SUPPLY CURRENT ICC (Outputs Enabled) ICC (Outputs Disabled)
Specifications subject to change without notice.
Min Typ Max
5.0
2.0
5.0
1.5
5.0
1.5
5.0
0.2
3
0.2
Parameter
Min Typ Max Unit Test Conditions/Comments
DRIVER
Propagation Delay Input to Output tPLH, tPHL
2
Driver O/P to O/P, tSKEW
Driver Rise/Fall Time, tR, tF
Up to 32 transceivers may be connected simultaneously on a bus, but only one driver should be enabled at any time. It is important, therefore, that the remaining disabled drivers do not load the bus. To ensure this, the ADM485 driver features high output impedance when disabled and when powered down
Parameter
DRIVER Differential Output Voltage, VOD
VOD3 ∆|VOD| for Complementary Output States Common-Mode Output Voltage, VOC ∆|VOD| for Complementary Output States Output Short-Circuit Current (VOUT = High) Output Short-Circuit Current (VOUT = Low) CMOS Input Logic Threshold Low, VINL CMOS Input Logic Threshold High, VINH Logic Input Current (DE, DI)
RECEIVER
Propagation Delay Input to Output, tPLH, tPHL 8 Skew |tPLH – tPHL| Receiver Enable, tEN1 Receiver Disable, tEN2 Tx Pulse Width Distortion
Rx Pulse Width Distortion
Driver Enable to Output Valid
Driver Disable Timing
Matched Enable Switching
|tAZH – tBZL|, |tBZH – tAZL| Matched Disable Switching
|tAHZ – tBLZ|, |tBHZ – tALZ|
The ADM485 operates from a single 5 V power supply. Excessive power dissipation caused by bus contention or by output shorting is prevented by a thermal shutdown circuit. This feature forces the driver output into a high impedance state if during fault conditions a significant temperature increase is detected in the internal driver circuitry.