FPGA可编程逻辑器件芯片XC2V1000-6FGG456I中文规格书

Table 119: IBUFDS, IBUFDS_DIFF_OUT, IBUFDS_DIFF_OUT_INTERMDISABLE, and IBUFDS_INTERMDISABLE Ports (cont'd)
Port
I/O Description IB
Input Input port connection. Connect directly to top-level N-side port in the design.IBUFDISABLE Input IBUFDISABLE is not supported in HD IOB.
(IBUFDS_DIFF_OUT_INTERMDISABLE and IBUFDS_INTERMDISABLE only)Differential Bidirectional Buffer Primitives
Figure 69: Differential Bidirectional Buffer Primitives
IOBUFDS
T
I O
IO IOB IOBUFDS_INTERMDISABLE T I
O
IO IOB
INTERMDISABLE
IBUFDISABLE X21633-092318
Figure 70: Differential Bidirectional DIFF_OUT Buffer Primitives
IOBUFDS_DIFF_OUT
IO IOB
IOBUFDS_DIFF_OUT_INTERMDISABLE IO IOB
X21634-112818Chapter 7: HD IOB Resources
Table 120: IOBUFDS, IOBUFDS_DIFF_OUT, IOBUFDS_DIFF_OUT_INTERMDISABLE, and IOBUFDS_INTERMDISABLE Attributes
Attribute
Values Description SLEW
SLOW, FAST Specifies the drive strength of the output.IOSTANDARD
See HD IOB Supported Standards Assigns an I/O standard to the E_IBUFDISABLE FALSE IBUFDISABLE is not supported in HD IOB and must be set to FALSE.(IOBUFDS_INTERMDISABLE and IOBUFDS_DIFF_OUT_INTERMDISABLE only)Table 121: IOBUFDS, IOBUFDS_DIFF_OUT, IOBUFDS_DIFF_OUT_INTERMDISABLE, and IOBUFDS_INTERMDISABLE Ports
Port
I/O Description IO Inout Inout port connection. Connect directly to top-level P side port in the design.IOB
Inout Inout port connection. Connect directly to top-level N side port in the design. (IOBUFDS_DIFF_OUT, IOBUF_DIFF_OUT_INTERMDISABLE only)O
Output Output path of the buffer representing the input path to the device.OB
Output Complimentary buffer output representing the input path to the device.(IOBUFDS_DIFF_OUT, IOBUF_DIFF_OUT_INTERMDISABLE only)I
Input Input port connection. Connect directly to top-level P-side port in the design.T
Input
Tristate enable input signifying whether the buffer acts as an input or output. (IOBUFDS, IOBUFDS_INTERMDISABLE only)IBUFDISABLE
Input IBUFDISABLE is not supported in HD IOB. ( IOBUFDS_INTERMDISABLE,IOBUFDS_DIFF_OUT_INTERMDISABLE only)INTERMDISABLE Input Control to enable/disable DCI termination. This is generally used to reduce power in long periods of an idle state.(IOBUFDS_INTERMDISABLE, IOBUFDS_DIFF_OUT_INTERMDISABLE only)
TM Input Tristate enable input for the P-side or master side signifying whether the buffer acts as an input or output. This pin must be connected to the same signal as the TS input. (IOBUFDS_DIFF_OUT,IOBUFDS_DIFF_OUT_INTERMDISABLE only)
TS Input
Tristate enable input for the N-side or slave side signifying whether the buffer acts as an input or output. This pin must be connected to the
same signal as the TM input. (IOBUFDS_DIFF_OUT and IOBUFDS_DIFF_OUT_INTERMDISABLE only)Differential Output Buffer Primitives
Figure 71: Differential Output Buffer Primitives
I
O
OBUFTDS T OB
I O
OBUFDS
OB X21630-092318Chapter 7: HD IOB Resources
Appendix A: Additional Resources and Legal Notices
Appendix A Additional Resources and Legal Notices
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References
These documents provide supplemental material useful with this guide:。