XN4506中文资料

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HCNW4506中文资料

1-49HIntelligent Power Module andGate Drive Interface Optocouplers Technical DataFeatures• Performance Specified for Common IPM Applications over Industrial Temperature Range: -40°C to 100°C• Fast Maximum Propagation Delayst PHL = 400ns t PLH = 550ns• Minimized Pulse Width Distortion (PWD = 450 ns)• 15 kV/µs Minimum Common Mode Transient Immunity at V CM = 1500 V• CTR > 44% at I F = 10mA • Safety ApprovalUL Recognized - 2500V rms for 1 minute (5000V rms for 1 minute for HCNW4506 and HCPL-4506 Option 020) per UL1577CSA ApprovedVDE 0884 Approved -V IORM = 630 V peak for HCPL-4506 Option 060-V IORM = 1414 V peak for HCNW4506BSI Certified (HCNW4506)Applications• IPM Isolation• Isolated IGBT/MOSFET Gate Drive• AC and Brushless DC Motor Drives• Industrial InvertersDescriptionThe HCPL-4506 and HCPL-0466contain a GaAsP LED while the HCNW4506 contains an AlGaAs LED. The LED is opticallycoupled to an integrated high gain photo detector. Minimized propa-The connection of a 0.1 µF bypass capacitor between pins 5 and 8 is recommended.gation delay difference between devices make these optocouplers excellent solutions for improving inverter efficiency through reduced switching dead time.An on chip 20 k Ω output pull-up resistor can be enabled by short-ing output pins 6 and 7, thus eliminating the need for an external pull-up resistor incommon IPM applications. Speci-fications and performance plots are given for typical IPM applications.HCPL-4506HCPL-0466HCNW4506Functional DiagramTruth TableLED V O ON L OFFHNCANODECATHODE NC V CCV L V OGNDCAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.Selection GuideOperating TemperatureT A [°C]Single Channel Packages 8-Pin DIP Small OutlineWidebody Min.Max.(300 Mil)SO-8(400 Mil)Hermetic*-40100HCPL-4506HCPL-0466HCNW4506-55125HCPL-5300HCPL-5301*Technical data for these products are on separate HP publications.5965-3603E1-50(0.100)BSCDIMENSIONS IN MILLIMETERS (INCHES).LEAD COPLANARITY = 0.10 mm (0.004 INCHES).+ 0.076- 0.051+ 0.003)- 0.002)DIMENSIONS IN MILLIMETERS AND (INCHES).0.254+ 0.076- 0.051(0.010+ 0.003)- 0.002)* MARKING CODE LETTER FOR OPTION NUMBERS."L" = OPTION 020"V" = OPTION 060OPTION NUMBERS 300 AND 500 NOT MARKED.Package Outline DrawingsFigure 2. HCPL-4506 Gull Wing Surface Mount Option #300 Outline Drawing.Figure 1. HCPL-4506 Outline Drawing (Standard DIP Package).Ordering InformationSpecify Part Number followed by Option Number (if desired).Example:HCPL-4506#XXX020 = UL 5000 V rms/1 Minute Option*060 = VDE 0884 V IORM = 630 V peak Option*300 = Gull Wing Surface Mount Option†500 = Tape and Reel Packaging OptionOption data sheets are available. Contact your Hewlett-Packard sales representative or authorized distributor for information.*For HCPL-4506 only. Combination of Option 020 andOption 060 is not available.†Gull wing surface mount option applies to through hole parts only.1-511.78 ± 0.15BSC1.78 ± 0.15TYP.+ 0.076- 0.0051+ 0.003)- 0.002)(0.012)LEAD COPLANARITY = 0.10 mm (0.004 INCHES).Figure 3. HCPL-0466 Outline Drawing (8-Pin Small Outline Package).Figure 4a. HCNW4506 Outline Drawing (8-Pin Widebody Package).Pin Location (for reference only)Figure 4b. HCNW4506 Outline Drawing (8-Pin Widebody Package with Gull Wing Surface Mount Option 300).1-52Insulation and Safety Related Specifications8-Pin DIP Widebody (300 Mil)SO-8(400 Mil)Parameter Symbol ValueValue Value UnitsConditionsMinimum External L(101)7.14.99.6mmMeasured from input terminalsAir Gap (External to output terminals, shortest Clearance)distance through air.Minimum External L(102)7.4 4.810.0mmMeasured from input terminals Tracking (External to output terminals, shortest Creepage)distance path along body.Minimum Internal 0.080.08 1.0mmThrough insulation distance,Plastic Gapconductor to conductor, usually (Internal Clearance)the direct distance between the photoemitter and photodetector inside the optocoupler cavity.Minimum Internal NA NA 4.0mmMeasured from input terminals Tracking (Internal to output terminals, along Creepage)internal cavity.Tracking Resistance CTI200200200VoltsDIN IEC 112/VDE 0303 Part 1(Comparative Tracking Index)Isolation GroupIIIa IIIa IIIaMaterial Group(DIN VDE 0110, 1/89, Table 1)Option 300 - surface mount classification is Class A in accordance with CECC 00802.Regulatory InformationThe devices contained in this data sheet have been approved by the following organizations:ULRecognized under UL 1577,Component Recognition Program, File E55361.CSAApproved under CSA Component Acceptance Notice #5, File CA 88324.VDEApproved according to VDE 0884/06.92 (HCNW4506 and HCPL-4506 Option 060 only).BSICertification according to BS451:1994(BS EN60065:1994);BS EN60950:1992(BS7002:1992) andEN41003:1993 for Class IIapplications (HCNW4506 only).Note: Use of nonchlorine activated fluxes is recommended.240TIME – MINUTEST E M P E R A T U R E – °C220200180160140120100806040200260Solder Reflow Temperature ProfileVDE 0884 Insulation Related Characteristics(HCPL-4506 OPTION 060 ONLY)VDE 0884 Insulation Related Characteristics (HCNW4506 ONLY)*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE 0884), for a detailed description.Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.1-53Absolute Maximum Ratings*All typical values at 25°C, V CC = 15 V.†V F(off) = -3 V to 0.8 V for HCNW4506.1-54Switching Specifications (R L= 20 kΩ External)Over recommended operating conditions unless otherwise specified:T A = -40°C to +100°C, V CC = +4.5 V to 30 V, I F(on) = 10 mA to 20mA, V F(off) = -5 V to 0.8 V†Switching Specifications (R L = Internal Pull-up)Over recommended operating conditions unless otherwise specified:T A = -40°C to +100°C, V CC = +4.5 V to 30 V, I F(on) = 10 mA to 20mA, V F(off) = -5 V to 0.8 V†*All typical values at 25°C, V CC = 15 V.†V F(off) = -3 V to 0.8 V for HCNW4506.1-55Package CharacteristicsOver recommended temperature (T A = -40°C to 100°C) unless otherwise specified.*All typical values at 25°C, V CC = 15 V.†The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Related Characteristics Table (if applicable), your equipment level safety specification or HP Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage,” publication number 5963-2203E.Notes:1.Derate linearly above 90°C free-airtemperature at a rate of 0.8 mA/°C.2.Derate linearly above 90°C free-airtemperature at a rate of 1.6 mA/°C.3.Derate linearly above 90°C free-airtemperature at a rate of 3.0 mW/°C.4.Derate linearly above 90°C free-airtemperature at a rate of 4.2 mW/°C.5.CURRENT TRANSFER RATIO inpercent is defined as the ratio ofoutput collector current (I O) to theforward LED input current (I F) times100.6.Device considered a two-terminaldevice: Pins 1, 2, 3, and 4 shortedtogether and Pins 5, 6, 7, and 8shorted together.7.In accordance with UL 1577, eachoptocoupler is proof tested byapplying an insulation test voltage≥3000 V rms for 1 second (leakagedetection current limit, I I-O≤5 µA).This test is performed before the100% Production test shown in theVDE 0884 Insulation RelatedCharacteristics Table, if applicable.8. For option 020, in accordance withUL 1577, each optocoupler is prooftested by applying an insulation testvoltage ≥6000 V rms for 1 second(leakage detection current limit, I I-O≤5 µA). This test is performed beforethe 100% Production test for partialdischarge (method b) shown in theVDE 0884 Insulation RelatedCharacteristics Table, if applicable.9. Pulse: f = 20 kHz, Duty Cycle = 10%.10. The internal 20 kΩ resistor can beused by shorting pins 6 and 7together.11. Due to tolerance of the internalresistor, and since propagation delayis dependent on the load resistorvalue, performance can be improvedby using an external 20 kΩ 1% loadresistor. For more information onhow propagation delay varies withload resistance, see Figure 12.12. The R L = 20 kΩ, C L = 100 pF loadrepresents a typical IPM (IntelligentPower Module) load.13. See Option 020 data sheet for moreinformation.14. Use of a 0.1 µF bypass capacitorconnected between pins 5 and 8 canimprove performance by filteringpower supply line noise.15. The difference between t PLH and t PHLbetween any two devices under thesame test condition. (See IPM DeadTime and Propagation DelaySpecifications section.)16. Common mode transient immunity ina Logic High level is the maximumtolerable dV CM/dt of the commonmode pulse, V CM, to assure that theoutput will remain in a Logic Highstate (i.e., V O > 3.0 V).17. Common mode transient immunity ina Logic Low level is the maximumtolerable dV CM/dt of the commonmode pulse, V CM, to assure that theoutput will remain in a Logic Lowstate (i.e.,V O<1.0V).18. Pulse Width Distortion (PWD) isdefined as |t PHL - t PLH| for any givendevice.1-561-57Figure 8. HCPL-4506 and HCPL-0466Input Current vs. Forward Voltage.Figure 9. HCNW4506 Input Current vs. Forward Voltage.Figure 6. Normalized Output Current vs. Temperature.Figure 5. Typical Transfer Characteristics.Figure 7. High Level Output Current vs. Temperature.Figure 10. Propagation Delay Test Circuit.I O – O U T P U T C U R R E N T – m AI F – FORWARD LED CURRENT – mAN O R M A L I Z E D O U T P U T CU R R E N TT A – TEMPERATURE – °C I F – F O R W A R D C U R R E N T – m AV F – FORWARD VOLTAGE – VOLTS= 15 VI *TOTAL LOAD CAPACITANCEI F – I N P U T F O R W A R D C U R R E N T – m AV F – INPUT FORWARD VOLTAGE – VI O H – H I G H L E V E L O U T P U T C U R R E N T – µAT A – TEMPERATURE – °C1-58Figure 12. Propagation Delay with External 20 k Ω RL vs. Temperature.Figure 13. Propagation Delay with Internal 20 k Ω RL vs. Temperature.Figure 14. Propagation Delay vs. Load Resistance.Figure 11. CMR Test Circuit. Typical CMR Waveform.Figure 17. Propagation Delay vs. Input Current.Figure 15. Propagation Delay vs. Load Capacitance.Figure 16. Propagation Delay vs.Supply Voltage.CC = 15 VV FFt P– P R O P A G A T I O N D E L A Y – n sT A – TEMPERATURE – °Ct P – P R O P A G A T I O N D E L A Y – n sRL – LOAD RESISTANCE – K Ωt P – P RO P A G A T I O N D E L A Y – n sCL – LOAD CAPACITANCE – pFtP – P R O P A G A T I O N D E L A Y – n sV CC – SUPPLY VOLTAGE – V t P– P R O P A G A T I O N D E L A Y – n sI F – FORWARD LED CURRENT – mAt P – P R O P A G A T I O N D E L A Y – n sT A – TEMPERATURE – °C1-59Figure 20. Optocoupler Input to Output Capacitance Model for Unshielded Optocouplers.Figure 19. Recommended LED Drive Circuit.Figure 18. Thermal Derating Curve, Dependence of Safety Limiting Value with Case Temperature per VDE 0884.Figure 22. LED Drive Circuit with Resistor Connected to LED Anode (Not Recommended).Figure 21. Optocoupler Input to Output Capacitance Model for Shielded Optocouplers.CC = 15 VCC = 15 VO U T P U T P O W E R – P S , I N P U T C U R R E N T – I STS – CASE TEMPERATURE – °CO U T P U T P O W E R – P S , I N P U T C U R R E N T – I S0T S – CASE TEMPERATURE – °C 400600800200100300500700(230)Figure 23. AC Equivalent Circuit for Figure 22 During Common Mode Transients.CM1-60Figure 27. Recommended LED Drive Circuit for Ultra High CMR.Figure 24. AC Equivalent Circuit for Figure 19 During Common Mode Transients.Figure 25. Not Recommended Open Collector LED Drive Circuit.Figure 26. AC Equivalent Circuit for Figure 25 During Common Mode Transients.CMCMFigure 28. Typical Application Circuit.1-61Figure 30. Waveforms for Dead Time Calculation.Figure 29. Minimum LED Skew for Zero Dead Time.VV I (t PLH-t PHL ) MAX. = t PLH MAX. - t PHL MIN.I *PDD = PROPAGATION DELAY DIFFERENCENOTE: THE PROPAGATION DELAYS USED TO CALCULATE PDD ARE TAKEN AT EQUAL TEMPERATURES.VV I MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER)= (t PLH MAX. - t PLH MIN.) + (t PHL MAX. - t PHL MIN.)= (t PLH MAX. - t PHL MIN.) - (t PLH MIN. - t PHL MAX.)= PDD* MAX. - PDD* MIN.I *PDD = PROPAGATION DELAY DIFFERENCENOTE: THE PROPAGATION DELAYS USED TO CALCULATE THE MAXIMUM DEAD TIME ARE TAKEN AT EQUAL TEMPERATURES.LED Drive CircuitConsiderations for Ultra High CMR PerformanceWithout a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the opto-coupler, through the package, to the detector IC as shown in Figure 20. The HCPL-4506,HCPL-0466 and HCNW4506improve CMR performance by using a detector IC with an optic-ally transparent Faraday shield,which diverts the capacitively coupled current away from the sensitive IC circuitry. However,this shield does not eliminate the capacitive coupling between the LED and the optocoupler output pins and output ground as shown in Figure 21. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocoupler. The main design objective of a high CMR LED drive circuit becomes keep-ing the LED in the proper state (on or off) during common mode transients. For example, therecommended application circuit(Figure 19), can achieve 15kV/µs CMR while minimizing component complexity. Note that a CMOS gate is recommended in Figure 19to keep the LED off when the gate is in the high state.Another cause of CMR failure for a shielded optocoupler is direct coupling to the optocoupler output pins through C LEDO1 and C LEDO2 in Figure 21. Many factors influence the effect and magni-tude of the direct coupling includ-ing: the use of an internal or external output pull-up resistor,the position of the LED current setting resistor, the connection of the unused input package pins,and the value of the capacitor at the optocoupler output (C L ).Techniques to keep the LED in the proper state and minimize the effect of the direct coupling are discussed in the next two sections.CMR with the LED On (CMR L )A high CMR LED drive circuit must keep the LED on during common mode transients. This isachieved by overdriving the LED current beyond the inputthreshold so that it is not pulled below the threshold during a transient. The recommended minimum LED current of 10mA provides adequate margin over the maximum I TH of 5.0mA (see Figure 5) to achieve 15kV/µs CMR. Capacitive coupling is higher when the internal load resistor is used (due to C LEDO2)and an I F = 16mA is required to obtain 10kV/µs CMR.The placement of the LED current setting resistor effects the ability of the drive circuit to keep the LED on during transients and interacts with the direct coupling to theoptocoupler output. For example,the LED resistor in Figure 22 is connected to the anode. Figure 23shows the AC equivalent circuit for Figure 22 during common mode transients. During a +dVcm/dt in Figure 23, the current available at the LED anode (Itotal) is limited by the series resistor. The LED current (I F ) is reduced from its DC value by an amount equal to the current that flows through C LEDP and C LEDO1.The situation is made worsebecause the current through C LEDO1 has the effect of trying to pull the output high (toward a CMR failure) at the same time the LED current is being reduced. For this reason, the recommended LED drive circuit (Figure 19) places the current set-ting resistor in series with the LED cathode. Figure 24 is the AC equiv-alent circuit for Figure 19 during common mode transients. In this case, the LED current is not reduced during a +dVcm/dt tran-sient because the current flowing through the package capacitance is supplied by the power supply. During a -dVcm/dt transient, how-ever, the LED current is reduced by the amount of current flowing through C LEDN. But, better CMR performance is achieved since the current flowing in C LEDO1 during a negative transient acts to keep the output low.Coupling to the LED and output pins is also affected by the connec-tion of pins 1 and 4. If CMR is limited by perturbations in the LED on current, as it is for the recom-mended drive circuit (Figure 19), pins 1 and 4 should be connected to the input circuit common. However, if CMR performance is limited by direct coupling to the output when the LED is off, pins 1 and 4 should be left unconnected.CMR with the LED Off (CMR H)A high CMR LED drive circuit must keep the LED off (V F≤V F(OFF)) during common mode transients. For example, during a +dVcm/dt transient in Figure 24, the current flowing through C LEDN is supplied by the parallel combination of the LED and series resistor. As long as the voltage developed across the resistor is less than V F(OFF) the LED will remain off and no common mode failure will occur. Even if the LED momentarily turns on, the 100 pF capacitor from pins 6-5 will keep the output from dipping below the threshold. The recommended LED drive circuit (Figure 19) pro-vides about 10V of margin between the lowest optocoupler output voltage and a 3V IPM threshold during a 15kV/µs transient withV CM=1500V. Additional margincan be obtained by adding a diodein parallel with the resistor, asshown by the dashed line connec-tion in Figure 24, to clamp thevoltage across the LED belowV F(OFF).Since the open collector drive cir-cuit, shown in Figure 25, cannotkeep the LED off during a +dVcm/dt transient, it is not desirable forapplications requiring ultra highCMR H performance. Figure 26 isthe AC equivalent circuit for Figure25 during common modetransients. Essentially all thecurrent flowing through C LEDNduring a +dVcm/dt transient mustbe supplied by the LED. CMR Hfailures can occur at dV/dt rateswhere the current through the LEDand C LEDN exceeds the inputthreshold. Figure 27 is analternative drive circuit which doesachieve ultra high CMRperformance by shunting the LEDin the off state.IPM Dead Time andPropagation DelaySpecificationsThe HCPL-4506, HCPL-0466 andHCNW4506 include a PropagationDelay Difference specificationintended to help designers minimize“dead time” in their power inverterdesigns. Dead time is the timeperiod during which both the highand low side power transistors (Q1and Q2 in Figure 28) are off. Anyoverlap in Q1 and Q2 conductionwill result in large currents flowingthrough the power devices betweenthe high and low voltage motor rails.To minimize dead time the designermust consider the propagationdelay characteristics of the opto-coupler as well as the characteris-tics of the IPM IGBT gate drivecircuit. Considering only the delaycharacteristics of the optocoupler(the characteristics of the IPMIGBT gate drive circuit can beanalyzed in the same way) it isimportant to know the minimumand maximum turn-on (t PHL) andturn-off (t PLH) propagation delayspecifications, preferably over thedesired operating temperaturerange.The limiting case of zero dead timeoccurs when the input to Q1 turnsoff at the same time that the inputto Q2 turns on. This casedetermines the minimum delaybetween LED1 turn-off and LED2turn-on, which is related to theworst case optocoupler propagationdelay waveforms, as shown inFigure 29. A minimum dead time ofzero is achieved in Figure 29 whenthe signal to turn on LED2 isdelayed by (t PLH max - t PHL min) fromthe LED1 turn off. Note that thepropagation delays used to calcu-late PDD are taken at equal temper-atures since the optocouplers underconsideration are typically mountedin close proximity to each other.(Specifically, t PLH max and t PHL minin the previous equation are not thesame as the t PLH max and t PHL min,over the full operating temperaturerange, specified in the data sheet.)This delay is the maximum value forthe propagation delay differencespecification which is specified at450ns for the HCPL-4506, HCPL-0466 and HCNW4506 over anoperating temperature range of-40°C to 100°C.Delaying the LED signal by themaximum propagation delay dif-ference ensures that the minimumdead time is zero, but it does nottell a designer what the maximumdead time will be. The maximumdead time occurs in the highlyunlikely case where one optocoup-ler with the fastest t PLH and anotherwith the slowest t PHL are in thesame inverter leg. The maximumdead time in this case becomes thesum of the spread in the t PLH andt PHL propagation delays as shown inFigure 30. The maximum dead timeis also equivalent to the differencebetween the maximum and mini-mum propagation delay differencespecifications. The maximum deadtime (due to the optocouplers) forthe HCPL-4506, HCPL-0466 andHCNW4506 is 600ns (= 450ns -(-150ns)) over an operatingtemperature range of -40°C to100°C.1-62。

NX8567SAS541-CC中文资料

NEC's NX8567SA Series is an Electro-Absorption (EA) modu-lator and wavelength monitor integrated, 1 550 nm MultipleQuantum Well (MQW) structured Distributed Feed-Back (DFB) laser diode module. The module is capable of 2.5 Gb/s ap-plications of over 240 km, 360 km, 600 km ultralong-reach and available for Dense Wavelength Division Multiplexing (DWDM) wavelengths based on ITU-T recommendations, enabling a wide range of applicationsDESCRIPTION• INTEGRATED ELECTROABSORPTION MODULATOR • WAVELENGTH MONITOR FUNCTION(Etalon Þ lter, Wavelength monitor PD)• VERY LOW DISPERSION PENALTYNX8567SAS Series - over 240 km (4320 ps/nm) NX8567SAM Series - over 360 km (6480 ps/nm) NX8567SA Series - over 600 km (10800 ps/nm)• LOW MODULATION VOLTAGE• AVAILABLE FOR DWDM WAVELENGHT BASED ON ITU-T RECOMMENDATION (50 GHz grid, refer to ordering information)FEATURESCalifornia Eastern LaboratoriesPART NUMBERNX8567SA SERIESSYMBOLS PARAMETERS AND CONDITIONSUNITS MIN TYPMAX T SET Laser Set Temperature 1°C 2035I OP Operating CurrentmA 506080V center Modulation Center Voltage 2V -2.0–-0.5V mod Modulation Voltage 2V –23V FLD For w ard Voltage of LD, I FLD = I OP V –– 2.0I THThresh o ld CurrentmA–720P fOptical Output Power from Fiber,I FLD = I OP , Under modulation 2(NX8567SAM/SA Series)dBm-5-2–I FLD = I OP , Under modulation 2(NX8567SAS Series)0+1–λP Peak Emission Wavelength, I FLD = I OP , V EA = 0 V nm 1528 ITU-T 31564SMSR Side Mode Suppression Ratio, I FLD = I OP , V EA = 0 V dB 3040–ER Extinction Ratio, I FLD = I OP , Under modulation 2dB 1011–t f Rise Time, I FLD = I OP , 20-80%, Under modulation 2ps ––125t rRise Time, I FLD = I OP , 80-20%, Under modulation 2ps ––125ELECTRO-OPTICAL CHARACTERISTICS (T LD = Tset, T C = -5 to +70°C, unless otherwise speci Þ ed)Notes:1. Tset is a certain point between 20 and 35C for ITU-T grid wavelength2. 2.48832 Gb/s, PRBS 223 -1, V EA = V center ±1/2 Vmod, I FLD = I op , TLD = Tset, NEC Test System V center : a certain point between -2.0 and -0.5 V V mod : a certain point 3 V or below I op : a certain point between 50 and 80 mA3. Available for DWDM wavelenght based on ITU-T recommendation (100 GHz grid). Please refer to ORDERING INFORMATION.4. BER = 10-10, NX8567SAS: 240 km (4320 ps/nm) BER = 10-10, NX8567SAM: 360 km (6480 ps/nm) BER = 10-10, NX8567SA: 600 km (10800 ps/nm)NX8567SA SERIESELECTRO-OPTICAL CHARACTERISTICS (T LD = Tset, T C = -5 to +70°C, Unless otherwise speci Þ ed)PART NUMBERNX8567SA SERIESSYMBOLSPARAMETERS AND CONDITIONSUNITS MIN TYP MAX DPDispension Penalty, I FLD = I op , SMF Under modulation 2,4dB––2I S IsolationdB 23––S 11Input Return LossI FLD = I op , V EA = -1 V, 50 Ω130 MHz to 2 GHzdB––-8 I FLD = I op , V EA = -1 V, 50 Ω 2 GHz to 2.5 GHz––-5Notes:1. Tset is a certain point between 20 and 35C for ITU-T grid wavelength2. 2.48832 Gb/s, PRBS 223 -1, V EA = V center ±1/2 Vmod, I FLD = I op , TLD = Tset, NEC Test System V center : a certain point between -2.0 and -0.5 V V mod : a certain point 3 V or below I op : a certain point between 50 and 80 mA3. Available for DWDM wavelenght based on ITU-T recommendation (100 GHz grid). Please refer to ORDERING INFORMATION.4. BER = 10-10, NX8567SAS: 240 km(4320 ps/nm) BER = 10-10, NX8567SAM: 360 km (6480 ps/nm) BER = 10-10, NX8567SA: 600 km (10800 ps/nm)ELECTRO-OPTICAL CHARACTERISTICS (Applicable to Monitor PD, T LD = Tset, T C = -5 to +70°C, BOL)SYMBOLS PARAMETERS AND CONDITIONSUNITS MIN TYP MAX I m (Pf)Monitor Current (P f Monitor), V RPD = 5 V, I FLD = I opµA 10–200I m (λp)Monitor Current (λp Monitor), V RPD = 5 V, I FLD = I op , Locking point µA 5–100I m (λ)Operation Region%25–75|λ1-λ2|pm 90––ηλDiscrimination Slope 1, V RPD = 5 V, I FLD = I op , Locking point µA/pm 0.24––I D Dark Current, V RPD = 5 V, V EA = 0 VnA ––10C t Terminal Capacitance, V RPD = 5 V, f = 1 MHz pF ––15γ2Tracking Error, I m (Pf) = const.dB––0.5Note:1. Operating region, Discrimination slope, Slope assignmentI I m I m (λp I m I 1: I m I 2: Im Negative SlopeI m I m I m (λp I m I 2: I m I 1: I m (nm)Positive Slopeµmmset , T C = 25ûC, T C = –20 to +70ûCP P fγ = 10 log[dB]P f P op2. Tracking error: γNote:1.Operation in excess of any one of these parameters may result in permanent damage.ABSOLUTE MAXIMUM RATINGS 1SYMBOLSPARAMETERSUNITS RATINGSP f Optical Output Power from Fiber mW 10I FLD Forward Current of LD mA 150V RLD Reverse Voltage of LD V 2.0V Fm Forward Voltage of Modulator V 1V Rm Reverse Voltage of Modulator V 5I FPD Forward Current of PD mA 1V RPD Reverse Voltage of PD V 10I C Cooler Current A 1.5V C Cooler VoltageV 2.5T C Operating Case Temperature °C -5 to +70T STG Storage Temperature °C -40 to +85T SLDLead Soldering Temp. (3 s)°C350NX8567SA SERIESELECTRO-OPTICAL CHARACTERISTICS (Applicable to Thermistor and TEC, T C = -5 to +70°C)PART NUMBERNX8567SA SERIESSYMBOLS PARAMETERS AND CONDITIONSUNITSMINTYP MAX R Thermistor Resistance, T LD = 25°Ck Ω9.510.010.5B B ConstantK 335034503550I C Cooler Current, T LD = T set A 1.2V CCooler Voltage, T LD = T setV2.4ORDERING INFORMATION NX8567SA SERIES Wavelength CodeITU-T Wavelength *1(nm)Frequency (THz)Wavelength CodeITU-T Wavelength *1(nm)Frequency (THz)2871528.773196.104571545.720193.952911529.163196.054611546.119193.902951529.553196.004651546.518193.852991529.553195.954691546.917193.803031530.334195.904731547.316193.703071530.725195.854771547.715193.703111531.116195.804851548.515193.603151531.507195.754891548.915193.553181531.898195.704931549.315193.503221532.290195.654971549.715193.453261532.681195.605011550.116193.403301533.073195.555051550.517193.353341533.465195.505091550.918193.303381533.073195.455131551.319193.253421534.250195.405171551.721193.203461534.643195.355211552.122193.153501535.036195.305251552.524193.103541535.429195.255291552.926193.053581535.822195.205331553.329193.003621536.216195.155371553.731192.953661536.643195.105411554.134192.903701537.003195.055451554.537192.853731537.397195.005491554.940192.803771537.792194.955531555.343192.753811538.186194.905571555.747192.703851538.581194.855611556.151192.653891538.976194.805651556.555192.603931539.371194.755691556.959192.553971539.766194.705731557.363192.504011540.162194.655771557.768192.454051540.557194.605811558.173192.404091540.953194.555851558.578192.304131541.349194.505891558.983192.304171541.746194.455931559.389192.254211542.142194.405971559.794192.204251542.539194.356021560.200192.154291542.936194.306061560.606192.104331543.333194.256101561.013192.054371543.730194.206141561.419192.004411544.128194.156181561.826191.954451544.526194.106221562.233191.904491544.924194.056261562.640191.854531545.322194.006301563.047191.80TABLE A: DWDM wavelengths based on ITU-T recommendations (@ TLD = Tset)Note:1. λ monitor slope: Channel frequency for 191.80 THz + 2n × 0.05 THz is assigned on negative slope. Channel frequency for 191.80 THz + (2n + 1) × 0.05 THz is assigned on positive slope. n is a positive integer including zero.NX8567SA-CC : SC-UPC connector (standard) BC : FC-UPC connector (option)Wavelength code : Refer to Table A Without : 600 km (10800 ps/nm) M : 360 km (6480 ps/nm) S : 240 km (4320 ps/nm)OUTLINE DIMENSIONS (Units in mm)OPTICAL FIBER CHARACTERISTICSPARAMETERUNITS SPECIFICATIONMode Field Diameter µm 9.3±0.5Cladding Diameter µm 125±1Tight Buffer Diameter µm 900±100Cut-off Wavelenghtnm < 1270Attenuation 1525 to 1575 nm dB/km < 0.3Minimum Fiber Bending Radius mm 30Fiber Length mm1225 MINFlammabilityUL1581VW-107/29/2003Life Support ApplicationsThese NEC products are not intended for use in life support devices, appliances, or systems where the malfunction of these products can reasonably be expected to result in personal injury. The customers of CEL using or selling these products for use in such applications do so at their own risk and agree to fully indemnify CEL for all damages resulting from such improper use or sale.NX8567SA SERIES8.99±0.5 m m。

2N3506JS中文资料

O
Symbol VCEO VCBO VEBO IC PT PT
Hale Waihona Puke Rating 40 60 5 3 1 5.71 5 28.6 175 -65 to +200 -65 to +200
Unit Volts Volts Volts A W mW/°C W mW/°C °C/W °C °C
RθJA
TJ TSTG
Copyright 2002 Rev. E
Semicoa Semiconductors, Inc.
333 McCormick Avenue, Costa Mesa, California 92626 714.979.1900, FAX 714.557.4541 Page 1 of 2

2N3506
Silicon NPN Transistor
Data Sheet
ELECTRICAL CHARACTERISTICS
characteristics specified at TA = 25°C
Off Characteristics Parameter Collector-Base Breakdown Voltage Collector-Emitter Breakdown Voltage Emitter-Base Breakdown Voltage Collector-Emitter Cutoff Current Collector-Emitter Cutoff Current On Characteristics Parameter Symbol hFE1 hFE2 hFE3 hFE4 hFE5 VBEsat1 VBEsat2 VBEsat3 VCEsat1 VCEsat2 VCEsat3 Symbol |hFE| COBO CIBO td tr ts tf Test Conditions IC = 500 mA, VCE = 1 Volts IC = 1.5 A, VCE = 2 Volts IC = 2.5 A, VCE = 3 Volts IC = 3.0 A, VCE = 5 Volts IC = 500 mA, VCE = 1 Volts TA = -55°C IC = 500 mA, IB = 50 mA IC = 1.5 A, IB = 150 mA IC = 2.5 A, IB = 250 mA IC = 500 mA, IB = 50 mA IC = 1.5 A, IB = 150 mA IC = 2.5 A, IB = 250 mA Test Conditions VCE = 5 Volts, IC = 100 mA, f = 20 MHz VCB = 10 Volts, IE = 0 mA, 100 kHZ < f < 1 MHz VEB = 3 Volts, IC = 0 mA, 100 kHZ < f < 1 MHz IC = 1.5 A, IB1 = 150 mA IC = 1.5 A, IB1 = 150 mA IC = 1.5 A, IB1=IB2 = 150 mA IC = 1.5 A, IB1=IB2 = 150 mA Min 50 40 30 25 25 Typ Max 250 200 Units Symbol V(BR)CBO V(BR)CEO V(BR)EBO ICEX1 ICEX2 Test Conditions IC = 100 µA IC = 10 mA IE = 10 µA VCE = 40 Volts, VEB = 4 Volts VCE = 40 Volts, VEB = 4 Volts, TA = 150°C Min 60 40 5 1 1.5 Typ Max Units Volts Volts Volts µA mA

CNX62A中文资料

Input-output Isolation Resistance RISO 5x1010 Turn-on Time Turn-off Time Turn-on Time Turn-off Time ton toff ton toff 3 3 12 12
µs µs µs µs
Note 1 Note 2
150
Collector current I C (mA)
40 30
100
50
0 -30 0 25 50 75 100 125 Ambient temperature TA ( °C ) (V) Forward Current vs. Ambient Temperature 80 70 Forward current I F (mA) 60 50 40 30 20 10 0 -30 0 25 50 75 100 125 Ambient temperature TA ( °C ) Relative Current Transfer Ratio vs. Ambient Temperature 1.5 Relative current transfer ratio
IF = 10mA VCE = 0.4V
Collector-emitter saturation voltage V
CE(SAT)
2.4 2.0 1.6 1.2 0.8 0.4 0 1 2 VCE = 0.4V TA = 25°C 5 10 20 50
1.0
0.5
0 -30 0 25 50 75 Ambient temperature TA ( °C ) 100
0
2
4
6
8
10
Collector-emitter voltage VCE ( V ) Collector-emitter Saturation Voltage vs. Ambient Temperature 0.28 0.24 0.20 0.16 0.12 0.08 0.04 0 -30 0 25 50 75 100 Ambient temperature TA ( °C ) Relative Current Transfer Ratio vs. Forward Current 2.8 Relative current transfer ratio IF = 10mA IC = 4mA

4066中文资料

Sine
Wave
5
VDD = 15V
Distortion
0
Frequency
VC = VDD = 5V, VSS = −5V RL = 10 kΩ,
0.
Response-Switch VIS = 5Vp-p, f= 1 kHz, (Figure 4)
1
“ON” (Frequency VC = VDD = 5V, VSS = −5V, RL = 1 kΩ,
当模拟开关的电源电压采用双电源时，例如 =﹢5V， =﹣5V（均对地0V 而言），则输入电压对称于0V 的正、负信号电压（﹢5V～﹣5V）均能传输。这时要求控制信号 C=“1”为+5V，C=“0”为-5V，否则只能传输正极性的信号电压。
CD4066引脚功能图
内部方框图
Absolute Maximum Ratings 绝对最大额定值：
5
=50pF(Figure 6)
0
RL=1.0kΩ, CL=50pF, (Figure 7)VOS(f) = ½ VOS(1.0 kHz)
6. VDD = 5.0V
0
8. VDD = 10V
0
8. VDD = 15V
5
Signal
Input
CIS Capacitance 信号
8.
输入电容
0
Signal
20
80 240
320
0
Δ“ON”
RL = 10kΩ to (VDD − VSS/2) VCC = VDD, VIS = VSS to VDD
ΔRO Resistance
VDD = 10V
10
N Between Any 2

NFE61PTxxx资料

For High Speed Signal
For Standard (Low DC
Resistance Type)
For Standard
0603
For High Speed Signal (Sharp impedance characteristics)
* Please see P.58 "Derating of Rated Current".
60 (0.5A) 60 (3A)
50 (3A)
60 (6A)
33 (3A) 30 (1A)
30 (3A)
33 (6A)
22 22
10 10 10
10 10
555
mm 0603 1005 1608 2012 1005 1608 2012 1608 2012
EIA Code 0201 0402 0603 0805 0402 0603 0805 0603 0805
47 47
1800
1000 (1.5A) 1000
1000
1
600 (1.5A)
600
600
470 (2A)
470
390 (2A)
390
330 (1.5A)
330
220 (2A)
220
220
180 (1.5A)
180 (3A)
120 (2A)
120 (3A)
120
120
100
80 (1A)
75 (3A)
4516 1806
1005
1608
0402
0603
GHz Range Noise GHz Range Noise Suppression Type Suppression Type BLM15H/E BLM18H/E/G

MAX465中文资料

Devices offered in this series are as follows:
PART
DESCRIPΒιβλιοθήκη IONMAX463 MAX464 MAX465 MAX466 MAX467 MAX468 MAX469 MAX470
Triple RGB Switch & Buffer Quad RGB Switch & Buffer Triple RGB Switch & Buffer Quad RGB Switch & Buffer Triple Video Buffer Quad Video Buffer Triple Video Buffer Quad Video Buffer
Continuous Power Dissipation (TA = +70°C) 16-Pin Plastic DIP (derate 22.22mW/°C above +70°C) ....1778mW 16-Pin Wide SO (derate 20.00mW/°C above +70°C) .......1600mW
The MAX463–MAX470 series of two-channel, triple/quad buffered video switches and video buffers combines high-accuracy, unity-gain-stable amplifiers with high-performance video switches. Fast switching time and low differential gain and phase error make this series of switches and buffers ideal for all video applications. The devices are all specified for ±5V supply operation with inputs and outputs as high as ±2.5V when driving 150Ω loads (75Ω back-terminated cable).

XCS05XL-4VQ256I中文资料

© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at /legal.htm .All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.IntroductionThe Spartan ™ and the Spartan-XL families are a high-vol-ume production FPGA solution that delivers all the key requirements for ASIC replacement up to 40,000 gates.These requirements include high performance, on-chip RAM, core solutions and prices that, in high volume,approach and in many cases are equivalent to mask pro-grammed ASIC devices.The Spartan series is the result of more than 14 years of FPGA design experience and feedback from thousands of customers. By streamlining the Spartan series feature set,leveraging advanced process technologies and focusing on total cost management, the Spartan series delivers the key features required by ASIC and other high-volume logic users while avoiding the initial cost, long development cycles and inherent risk of conventional ASICs. The Spar-tan and Spartan-XL families in the Spartan series have ten members, as shown in T able 1.Spartan and Spartan-XL FeaturesNote: The Spartan series devices described in this data sheet include the 5V Spartan family and the 3.3V Spartan-XL family. See the separate data sheet for the 2.5V Spartan-II family.•First ASIC replacement FPGA for high-volume production with on-chip RAM•Density up to 1862 logic cells or 40,000 system gates •Streamlined feature set based on XC4000 architecture •System performance beyond 80MHz•Broad set of AllianceCORE ™ and LogiCORE ™ predefined solutions available •Unlimited reprogrammability •Low cost•System level features-Available in both 5V and 3.3V versions -On-chip SelectRAM ™ memory -Fully PCI compliant-Full readback capability for program verificationand internal node observability -Dedicated high-speed carry logic -Internal 3-state bus capability-Eight global low-skew clock or signal networks -IEEE 1149.1-compatible Boundary Scan logic -Low cost plastic packages available in all densities -Footprint compatibility in common packages•Fully supported by powerful Xilinx development system -Foundation Series: Integrated, shrink-wrapsoftware-Alliance Series: Dozens of PC and workstationthird party development systems supported-Fully automatic mapping, placement and routing Additional Spartan-XL Features• 3.3V supply for low power with 5V tolerant I/Os •Power down input •Higher performance •Faster carry logic•More flexible high-speed clock network•Latch capability in Configurable Logic Blocks •Input fast capture latch•Optional mux or 2-input function generator on outputs •12 mA or 24 mA output drive •5V and 3.3V PCI compliant •Enhanced Boundary Scan •Express Mode configuration •Chip scale packagingSpartan and Spartan-XL Families Field Programmable Gate ArraysDS060 (v1.6) September 19, 2001Product Specification T able 1: Spartan and Spartan-XL Field Programmable Gate Arrays1.Max values of Typical Gate Range include 20-30% of CLBs used as RAM.2DS060 (v1.6) September 19, 2001General OverviewSpartan series FPGAs are implemented with a regular, flex-ible, programmable architecture of Configurable Logic Blocks (CLBs), interconnected by a powerful hierarchy of versatile routing resources (routing channels), and sur-rounded by a perimeter of programmable Input/Output Blocks (IOBs), as seen in Figure 1. They have generous routing resources to accommodate the most complex inter-connect patterns.The devices are customized by loading configuration data into internal static memory cells. Re-programming is possi-ble an unlimited number of times. The values stored in thesememory cells determine the logic functions and intercon-nections implemented in the FPGA. The FPGA can either actively read its configuration data from an external serial PROM (Master Serial mode), or the configuration data can be written into the FPGA from an external device (Slave Serial mode).Spartan series FPGAs can be used where hardware must be adapted to different user applications. FPGAs are ideal for shortening design and development cycles, and also offer a cost-effective solution for production rates well beyond 50,000 systems per month.Figure 1: Basic FPGA Block DiagramSpartan series devices achieve high-performance, low-cost operation through the use of an advanced architecture and semiconductor technology. Spartan and Spartan-XL devices provide system clock rates exceeding 80MHz and internal performance in excess of150MHz. In contrast to other FPGA devices, the Spartan series offers the most cost-effective solution while maintaining leading-edge per-formance. In addition to the conventional benefit of high vol-ume programmable logic solutions, Spartan series FPGAs also offer on-chip edge-triggered single-port and dual-port RAM, clock enables on all flip-flops, fast carry logic, and many other features.The Spartan/XL families leverage the highly successful XC4000 architecture with many of that family’s features and benefits. T echnology advancements have been derived from the XC4000XLA process developments.Logic Functional DescriptionThe Spartan series uses a standard FPGA structure as shown in Figure1, page2. The FPGA consists of an array of configurable logic blocks (CLBs) placed in a matrix of routing channels. The input and output of signals is achieved through a set of input/output blocks (IOBs) forming a ring around the CLBs and routing channels.•CLBs provide the functional elements for implementing the user’s logic.•IOBs provide the interface between the package pins and internal signal lines.•Routing channels provide paths to interconnect the inputs and outputs of the CLBs and IOBs.The functionality of each circuit block is customized during configuration by programming internal static memory cells. The values stored in these memory cells determine the logic functions and interconnections implemented in the FPGA.Configurable Logic Blocks (CLBs)The CLBs are used to implement most of the logic in an FPGA. The principal CLB elements are shown in the simpli-fied block diagram in Figure2. There are three look-up tables (LUT) which are used as logic function generators, two flip-flops and two groups of signal steering multiplexers. There are also some more advanced features provided by the CLB which will be covered in the Advanced Features Description, page13.Function GeneratorsTwo 16x1 memory look-up tables (F-LUT and G-LUT) are used to implement 4-input function generators, each offer-ing unrestricted logic implementation of any Boolean func-tion of up to four independent input signals (F1 to F4 or G1 to G4). Using memory look-up tables the propagation delay is independent of the function implemented.A third 3-input function generator (H-LUT) can implement any Boolean function of its three inputs. Two of these inputs are controlled by programmable multiplexers (see box "A" of Figure2). These inputs can come from the F-LUT or G-LUT outputs or from CLB inputs. The third input always comes from a CLB input. The CLB can, therefore, implement cer-tain functions of up to nine inputs, like parity checking. The three LUTs in the CLB can also be combined to do any arbi-trarily defined Boolean function of five inputs.4DS060 (v1.6) September 19, 2001A CLB can implement any of the following functions:•Any function of up to four variables, plus any second function of up to four unrelated variables, plus any third function of up to three unrelated variablesNote: When three separate functions are generated, one of the function outputs must be captured in a flip-flop internal to the CLB. Only two unregistered function generator outputs are available from the CLB.•Any single function of five variables•Any function of four variables together with some functions of six variables•Some functions of up to nine variables.Implementing wide functions in a single block reduces both the number of blocks required and the delay in the signal path, achieving both increased capacity and speed. The versatility of the CLB function generators significantly improves system speed. In addition, the design-software tools can deal with each function generator independently.This flexibility improves cell usage.Flip-FlopsEach CLB contains two flip-flops that can be used to regis-ter (store) the function generator outputs. The flip-flops and function generators can also be used independently (see Figure 2). The CLB input DIN can be used as a direct input to either of the two flip-flops. H1 can also drive either flip-flop via the H-LUT with a slight additional delay.The two flip-flops have common clock (CK), clock enable (EC) and set/reset (SR) inputs. Internally both flip-flops are also controlled by a global initialization signal (GSR) which is described in detail in Global Signals: GSR and GTS ,page 20.Latches (Spartan-XL only)The Spartan-XL CLB storage elements can also be config-ured as latches. The two latches have common clock (K)and clock enable (EC) inputs. Functionality of the storage element is described in Table 2.Figure 2: Spartan/XL Simplified CLB Logic Diagram (some features not shown)Clock InputEach flip-flop can be triggered on either the rising or falling clock edge. The CLB clock line is shared by both flip-flops.However, the clock is individually invertible for each flip-flop (see CK path in Figure 3). Any inverter placed on the clock line in the design is automatically absorbed into the CLB. Clock EnableThe clock enable line (EC) is active High. The EC line is shared by both flip-flops in a CLB. If either one is left discon-nected, the clock enable for that flip-flop defaults to the active state. EC is not invertible within the CLB. The clock enable is synchronous to the clock and must satisfy the setup and hold timing specified for the device.Set/ResetThe set/reset line (SR) is an asynchronous active High con-trol of the flip-flop. SR can be configured as either set or reset at each flip-flop. This configuration option determines the state in which each flip-flop becomes operational after configuration. It also determines the effect of a GSR pulse during normal operation, and the effect of a pulse on the SR line of the CLB. The SR line is shared by both flip-flops. If SR is not specified for a flip-flop the set/reset for that flip-flop defaults to the inactive state. SR is not invertible within the CLB.CLB Signal Flow ControlIn addition to the H-LUT input control multiplexers (shown in box "A" of Figure 2, page 4) there are signal flow control multiplexers (shown in box "B" of Figure 2) which select the signals which drive the flip-flop inputs and the combinatorial CLB outputs (X and Y).Each flip-flop input is driven from a 4:1 multiplexer which selects among the three LUT outputs and DIN as the data source.Each combinatorial output is driven from a 2:1 multiplexer which selects between two of the LUT outputs. The X output can be driven from the F-LUT or H-LUT, the Y output from G-LUT or H-LUT .Control SignalsThere are four signal control multiplexers on the input of the CLB. These multiplexers allow the internal CLB control sig-nals (H1, DIN, SR, and EC in Figure 2 and Figure 4) to be driven from any of the four general control inputs (C1-C4 in Figure 4) into the CLB. Any of these inputs can drive any of the four internal control signals.T able 2: CLB Storage Element FunctionalityLegend:XDon ’t careRising edge (clock not inverted).SR Set or Reset value. Reset is default.0*Input is Low or unconnected (default value)1*Input is High or unconnected (default value)Figure 3: CLB Flip-Flop Functional Block Diagram6DS060 (v1.6) September 19, 2001The four internal control signals are:•EC: Enable Clock•SR: Asynchronous Set/Reset or H function generator Input 0•DIN: Direct In or H function generator Input 2•H1: H function generator Input 1.Input/Output Blocks (IOBs)User-configurable input/output blocks (IOBs) provide the interface between external package pins and the internal logic. Each IOB controls one package pin and can be con-figured for input, output, or bidirectional signals. Figure 6shows a simplified functional block diagram of the Spar-tan/XL IOB.IOB Input Signal PathThe input signal to the IOB can be configured to either go directly to the routing channels (via I1 and I2 in Figure 6) or to the input register. The input register can be programmed as either an edge-triggered flip-flop or a level-sensitive latch. The functionality of this register is shown in Table 3,and a simplified block diagram of the register can be seen in Figure 5.Figure 4: CLB Control Signal InterfaceFigure 5: IOB Flip-Flop/Latch Functional BlockDiagramTable 3: Input Register FunctionalityX Don ’t care.Rising edge (clock not inverted).SR Set or Reset value. Reset is default.0*Input is Low or unconnected (default value)1*Input is High or unconnected (default value)The register choice is made by placing the appropriate library symbol. For example, IFD is the basic input flip-flop (rising edge triggered), and ILD is the basic input latch (transparent-High). Variations with inverted clocks are also available. The clock signal inverter is also shown in Figure5 on the CK line.The Spartan IOB data input path has a one-tap delay ele-ment: either the delay is inserted (default), or it is not. The Spartan-XL IOB data input path has a two-tap delay ele-ment, with choices of a full delay, a partial delay, or no delay. The added delay guarantees a zero hold time with respect to clocks routed through the global clock buffers. (See Glo-bal Nets and Buffers, page12 for a description of the glo-bal clock buffers in the Spartan/XL families.) For a shorter input register setup time, with positive hold-time, attach a NODELAY attribute or property to the flip-flop.The output of the input register goes to the routing channels (via I1 and I2 in Figure6). The I1 and I2 signals that exit the IOB can each carry either the direct or registered input signal.The 5V Spartan input buffers can be globally configured for either TTL (1.2V) or CMOS (VCC/2) thresholds, using an option in the bitstream generation software. The Spartan output levels are also configurable; the two global adjust-ments of input threshold and output level are independent. The inputs of Spartan devices can be driven by the outputs of any 3.3V device, if the Spartan inputs are in TTL mode. Input and output thresholds are TTL on all configuration pins until the configuration has been loaded into the device and specifies how they are to be used. Spartan-XL inputs are TTL compatible and 3.3V CMOS compatible. Supported sources for Spartan/XL device inputs are shown in Table4.Spartan-XL I/Os are fully 5V tolerant even though the V CC is 3.3V. This allows 5V signals to directly connect to the Spar-tan-XL inputs without damage, as shown in Table4. In addi-tion, the 3.3V V CC can be applied before or after 5V signals are applied to the I/Os. This makes the Spartan-XL devices immune to power supply sequencing problems.Figure 6: Simplified Spartan/XL IOB Block Diagram8DS060 (v1.6) September 19, 2001Spartan-XL V CC ClampingSpartan-XL FPGAs have an optional clamping diode con-nected from each I/O to V CC . When enabled they clamp ringing transients back to the 3.3V supply rail. This clamping action is required in 3.3V PCI applications. V CC clamping is a global option affecting all I/O pins.Spartan-XL devices are fully 5V TTL I/O compatible if V CC clamping is not enabled. With V CC clamping enabled, the Spartan-XL devices will begin to clamp input voltages to one diode voltage drop above V CC . If enabled, TTL I/O com-patibility is maintained but full 5V I/O tolerance is sacrificed.The user may select either 5V tolerance (default) or 3.3V PCI compatibility. In both cases negative voltage is clamped to one diode voltage drop below ground.Spartan-XL devices are compatible with TTL, LVTTL, PCI 3V, PCI 5V and LVCMOS signalling. The various standards are illustrated in Table 5.Additional Fast Capture Input Latch (Spartan-XL only)The Spartan-XL IOB has an additional optional latch on the input. This latch is clocked by the clock used for the output flip-flop rather than the input clock. Therefore, two different clocks can be used to clock the two input storage elements.This additional latch allows the fast capture of input data,which is then synchronized to the internal clock by the IOB flip-flop or latch.T o place the Fast Capture latch in a design, use one of the special library symbols, ILFFX or ILFLX. ILFFX is a trans-parent-Low Fast Capture latch followed by an active High input flip-flop. ILFLX is a transparent Low Fast Capture latch followed by a transparent High input latch. Any of the clock inputs can be inverted before driving the library element,and the inverter is absorbed into the IOB.IOB Output Signal PathOutput signals can be optionally inverted within the IOB,and can pass directly to the output buffer or be stored in an edge-triggered flip-flop and then to the output buffer. The functionality of this flip-flop is shown in T able 6.T able 4: Supported Sources for Spartan/XL InputsT able 5: I/O Standards Supported by Spartan-XL FPGAsTable 6: Output Flip-Flop Functionality X Don ’t careRising edge (clock not inverted). SR Set or Reset value. Reset is default.0*Input is Low or unconnected (default value)1*Input is High or unconnected (default value)Z3-stateOutput Multiplexer/2-Input Function Generator (Spartan-XL only)The output path in the Spartan-XL IOB contains an addi-tional multiplexer not available in the Spartan IOB. The mul-tiplexer can also be configured as a 2-input function generator, implementing a pass gate, AND gate, OR gate, or XOR gate, with 0, 1, or 2 inverted inputs.When configured as a multiplexer, this feature allows two output signals to time-share the same output pad, effec-tively doubling the number of device outputs without requir-ing a larger, more expensive package. The select input is the pin used for the output flip-flop clock, OK.When the multiplexer is configured as a 2-input function generator, logic can be implemented within the IOB itself. Combined with a Global buffer, this arrangement allows very high-speed gating of a single signal. For example, a wide decoder can be implemented in CLBs, and its output gated with a Read or Write Strobe driven by a global buffer. The user can specify that the IOB function generator be used by placing special library symbols beginning with the letter "O." For example, a 2-input AND gate in the IOB func-tion generator is called OAND2. Use the symbol input pin labeled "F" for the signal on the critical path. This signal is placed on the OK pin — the IOB input with the shortest delay to the function generator. Two examples are shown in Figure7.Output BufferAn active High 3-state signal can be used to place the out-put buffer in a high-impedance state, implementing 3-state outputs or bidirectional I/O. Under configuration control, the output (O) and output 3-state (T) signals can be inverted. The polarity of these signals is independently configured for each IOB (see Figure6, page7). An output can be config-ured as open-drain (open-collector) by tying the 3-state pin (T) to the output signal, and the input pin (I) to Ground.By default, a 5V Spartan device output buffer pull-up struc-ture is configured as a TTL-like totem-pole. The High driver is an n-channel pull-up transistor, pulling to a voltage one transistor threshold below V CC. Alternatively, the outputs can be globally configured as CMOS drivers, with additional p-channel pull-up transistors pulling to V CC. This option, applied using the bitstream generation software, applies to all outputs on the device. It is not individually programma-ble.All Spartan-XL device outputs are configured as CMOS drivers, therefore driving rail-to-rail. The Spartan-XL outputs are individually programmable for 12mA or 24mA output drive.Any 5V Spartan device with its outputs configured in TTL mode can drive the inputs of any typical 3.3V device. Sup-ported destinations for Spartan/XL device outputs are shown in Table7.Three-State Register (Spartan-XL Only)Spartan-XL devices incorporate an optional register control-ling the three-state enable in the IOBs. The use of the three-state control register can significantly improve output enable and disable time.Output Slew RateThe slew rate of each output buffer is, by default, reduced, to minimize power bus transients when switching non-criti-cal signals. For critical signals, attach a FAST attribute or property to the output buffer or flip-flop.Spartan/XL devices have a feature called "Soft Start-up," designed to reduce ground bounce when all outputs are turned on simultaneously at the end of configuration. When the configuration process is finished and the device starts up, the first activation of the outputs is automatically slew-rate limited. Immediately following the initial activation of the I/O, the slew rate of the individual outputs is deter-mined by the individual configuration option for each IOB. Pull-up and Pull-down NetworkProgrammable pull-up and pull-down resistors are used fortying unused pins to V CC or Ground to minimize power con-sumption and reduce noise sensitivity. The configurablepull-up resistor is a p-channel transistor that pulls to V CC.The configurable pull-down resistor is an n-channel transis-tor that pulls to Ground. The value of these resistors is typi-cally 20KΩ − 100KΩ (See "Spartan DC Characteristics Figure 7: AND and MUX Symbols in Spartan-XL IOB10DS060 (v1.6) September 19, 2001Over Operating Conditions" on page 43.). This high value makes them unsuitable as wired-AND pull-up resistors.After configuration, voltage levels of unused pads, bonded or unbonded, must be valid logic levels, to reduce noise sensitivity and avoid excess current. Therefore, by default,unused pads are configured with the internal pull-up resistor active. Alternatively, they can be individually configured with the pull-down resistor, or as a driven output, or to be driven by an external source. To activate the internal pull-up, attach the PULLUP library component to the net attached to the pad. To activate the internal pull-down, attach the PULL-DOWN library component to the net attached to the pad.Set/ResetAs with the CLB registers, the GSR signal can be used to set or clear the input and output registers, depending on the value of the INIT attribute or property. The two flip-flops can be individually configured to set or clear on reset and after configuration. Other than the global GSR net, no user-con-trolled set/reset signal is available to the I/O flip-flops (Figure 5). The choice of set or reset applies to both the ini-tial state of the flip-flop and the response to the GSR pulse.Independent ClocksSeparate clock signals are provided for the input (IK) and output (OK) flip-flops. The clock can be independently inverted for each flip-flop within the IOB, generating eitherfalling-edge or rising-edge triggered flip-flops. The clock inputs for each IOB are mon Clock EnablesThe input and output flip-flops in each IOB have a common clock enable input (see EC signal in Figure 5), which through configuration, can be activated individually for the input or output flip-flop, or both. This clock enable operates exactly like the EC signal on the Spartan/XL CLB. It cannot be inverted within the IOB.Routing Channel DescriptionAll internal routing channels are composed of metal seg-ments with programmable switching points and switching matrices to implement the desired routing. A structured,hierarchical matrix of routing channels is provided to achieve efficient automated routing.This section describes the routing channels available in Spartan/XL devices. Figure 8 shows a general block dia-gram of the CLB routing channels. The implementation soft-ware automatically assigns the appropriate resources based on the density and timing requirements of the design.The following description of the routing channels is for infor-mation only and is simplified with some minor details omit-ted. For an exact interconnect description the designer should open a design in the FPGA Editor and review the actual connections in this tool.The routing channels will be discussed as follows;•CLB routing channels which run along each row and column of the CLB array.•IOB routing channels which form a ring (called a VersaRing) around the outside of the CLB array. It connects the I/O with the CLB routing channels.•Global routing consists of dedicated networks primarily designed to distribute clocks throughout the device with minimum delay and skew. Global routing can also be used for other high-fanout signals.CLB Routing ChannelsThe routing channels around the CLB are derived from three types of interconnects; single-length, double-length,and longlines. At the intersection of each vertical and hori-zontal routing channel is a signal steering matrix called a Programmable Switch Matrix (PSM). Figure 8 shows the basic routing channel configuration showing single-length lines, double-length lines and longlines as well as the CLBs and PSMs. The CLB to routing channel interface is shown as well as how the PSMs interface at the channel intersec-tions.T able 7: Supported Destinations for Spartan/XL OutputsNotes:1.Only if destination device has 5V tolerant inputs.CLB InterfaceA block diagram of the CLB interface signals is shown in Figure9. The input signals to the CLB are distributed evenly on all four sides providing maximum routing flexibility. In general, the entire architecture is symmetrical and regular. It is well suited to established placement and routing algo-rithms. Inputs, outputs, and function generators can freely swap positions within a CLB to avoid routing congestion during the placement and routing operation. The exceptions are the clock (K) input and CIN/COUT signals. The K input is routed to dedicated global vertical lines as well as four single-length lines and is on the left side of the CLB. The CIN/COUT signals are routed through dedicated intercon-nects which do not interfere with the general routing struc-ture. The output signals from the CLB are available to drive both vertical and horizontal channels.Programmable Switch MatricesThe horizontal and vertical single- and double-length lines intersect at a box called a programmable switch matrix (PSM). Each PSM consists of programmable pass transis-tors used to establish connections between the lines (see Figure10).For example, a single-length signal entering on the right side of the switch matrix can be routed to a single-length line on the top, left, or bottom sides, or any combination thereof, if multiple branches are required. Similarly, a dou-ble-length signal can be routed to a double-length line on any or all of the other three edges of the programmable switch matrix.Single-Length LinesSingle-length lines provide the greatest interconnect flexibil-ity and offer fast routing between adjacent blocks. There are eight vertical and eight horizontal single-length lines associ-ated with each CLB. These lines connect the switching matrices that are located in every row and column of CLBs. Single-length lines are connected by way of the program-mable switch matrices, as shown in Figure10. Routing con-nectivity is shown in Figure8.Single-length lines incur a delay whenever they go through a PSM. Therefore, they are not suitable for routing signals for long distances. They are normally used to conduct sig-nals within a localized area and to provide the branching for nets with fanout greater than one.Figure 8: Spartan/XL CLB Routing Channels and Interface Block DiagramFigure 9: CLB Interconnect Signals。

Z23S4407N中文资料(AEROVOX)中文数据手册「EasyDatasheet - 矽搜」

• 专利压力灭弧符合UL810
每个电容器填充有环氧化Soybeanoil
要求.
电介液.大豆油已被证明可靠性
•环防护专利非PCB
在几个过去几十年.大豆油是
环氧大豆油.
环防护和可生物降解.该
大豆油防护护金属化膜不受腐蚀,
认证证书
助剂传热,并有助于抑制降解
电晕效应,这可能导致否则prema-
UL和CUL文件编号E51176
所有AEROMET II电容都可以用时间和成本节约
EIA RS-186-3E状态测试要求.
AeroMount系统.触点厂家触点厂家对于需要reycled了解详细信息.
认证证书
EIA RS-186-2E湿度测试要求（TropiCAL条件）.
• UL文件号E51176
• CSA文件号058450
• VDE认证可用
电压编码电压第一个两位数
24 = 240 V交流 33 = 330 V交流 37 = 370 V交流 44 = 440 V交流 48 = 480 V交流 60 = 600 Vac
电容值
（μF额定值） 25 = 25 µF 03 = 3 µF)
工厂代码
AeroMet II 00 =单额定值 XX =μF价值
产品系列
M = AeroMet II Z = SuperMet & ZeMax TM
机箱样式
22 = 1½"圆 23 = 1.75"圆 24 = 2.0"圆 26 = 2½"圆
50 = 1.25"椭圆形 42 = 1½"椭圆形 64 = 1.75"椭圆形 62 = 2.0"椭圆形
注入
P = Supernol（M系列） S = SuperSoy（Z系列）

STM32F103x46参考手册详细简介中文版

数据手册
STM32F103x4
STM32F103x6
小容量增强型，32位基于ARM核心的带16或32K字节闪存的微控制器 USB、CAN、6个定时器、2个ADC 、6个通信接口
功能
■ 内核：ARM 32位的Cortex™-M3 CPU − 最高72MHz工作频率，在存储器的0等待周期访问时可达1.25DMips/MHz(Dhrystone 2.1) − 单周期乘法和硬件除法
■ 低功耗
− 睡眠、停机和待机模式 − VBAT为RTC和后备寄存器供电 ■ 2个12位模数转换器，1μs转换时间(多达16个输入通道)
− 转换范围：0至3.6V − 双采样和保持功能 − 温度传感器
■ DMA：
− 7通道DMA控制器 − 支持的外设：定时器、ADC、SPI、I2C和
USART
■ 多达80个快速I/O端口
− 26/37/51个I/O口，所有I/O口可以映像到16 个外部中断；几乎所有端口均可容忍5V信号
■ 调试模式 − 串行单线调试(SWD)和JTAG接口
■ 多达6个定时器
− 2个16位定时器，每个定时器有多达4个用于输入捕获/输出比较/PWM或脉冲计数的通道和增量编码器输入
− 1个16位带死区控制和紧急刹车，用于电机控制的PWM高级控制定时器
■ CRC计算单元，96位的芯片唯一代码
■ ECOPACK®封装
表1 器件列表
参考 STM32F103x4 STM32F103x6
基本型号
STM32F103C4、STM32F103R4、 STM32F103T4 STM32F103C6 、 STM32F103R6 、 STM32F103T6
本文档英文原文下载地址：/stonline/products/literature/ds/15060.pdf

XN4608中文资料

Common characteristics chart PT — Ta
500
Total power dissipation PT (mW)
400
300
200
100
0 0 40 80 120 160
Ambient temperature Ta (˚C)
2
元器件交易网
Composite Transistors
s Electrical Characteristics
q
Tr1
Parameter
Collector to base voltage Collector to emitter voltage Emitter to base voltage Collector cutoff current Forward current transfer ratio Collector to emitter saturation voltage Transition frequency Collector output capacitance
Characteristics charts of Tr1 IC — VCE
60 Ta=25˚C IB=160µA 50
XN4608
IB — VBE
1200 VCE=10V Ta=25˚C 1000
200 240
IC — VBE
VCE=10V
Collector current IC (mA)
Base current IB (µA)
–30 –10 –3 25˚C –1 –0.3 –0.1 –0.03 –0.01 –0.01 –0.03 –0.1 –0.3 Ta=–25˚C 75˚C
Collector current IC (A)

4046中文资料

锁相环 CD4046 应用介绍朗清锁相的意义是相位同步的自动控制，能够完成两个电信号相位同步的自动控制闭环系统叫做锁相环，简称PLL。

它广泛应用于广播通信、频率合成、自动控制及时钟同步等技术领域。

锁相环主要由相位比较器（PC）、压控振荡器（VCO）。

低通滤波器三部分组成，如图1所示。

广告：>>上建立起来的平均电压Ud大小决定。

施加于相位比较器另一个输入端的外部输入信号Ui与来自压控振荡器的输出信号Uo相比较，比较结果产生的误差输出电压UΨ正比于Ui和Uo两个信号的相位差，经过低通滤波器滤除高频分量后，得到一个平均值电压Ud。

这个平均值电压Ud朝着减小VCO输出频率和输入频率之差的方向变化，直至VCO输出频率和输入信号频率获得一致。

这时两个信号的频率相同，两相位差保持恒定（即同步）称作相位锁定。

当锁相环入锁时，它还具有“捕捉”信号的能力，VCO可在某一范围内自动跟踪输入信号的变化，如果输入信号频率在锁相环的捕捉范围内发生变化，锁相环能捕捉到输人信号频率，并强迫VCO锁定在这个频率上。

锁相环应用非常灵活，如果输入信号频率f1不等于VCO输出信号频率f2，而要求两者保持一定的关系，例如比例关系或差值关系，则可以在外部加入一个运算器，以满足不同工作的需要。

过去的锁相环多采用分立元件和模拟电路构成，现在常使用集成电路的锁相环，CD4046是通用的CMOS锁相环集成电路，其特点是电源电压范围宽（为3V－18V），输入阻抗高(约100MΩ)，动态功耗小，在中心频率f0为10kHz下功耗仅为600μW，属微功耗器件。

图2是CD4046的引脚排列，采用 16 脚双列直插式，各引脚功能如下：1脚相位输出端，环路人锁时为高电平，环路失锁时为低电平。

2脚相位比较器Ⅰ的输出端。

3脚比较信号输入端。

4脚压控振荡器输出端。

5脚禁止端，高电平时禁止，低电平时允许压控振荡器工作。

6、7脚外接振荡电容。

8、16脚电源的负端和正端。

AK4556资料

When PDN pin is “L”, BCLK pin outputs “L” in master mode.
Power-Down & Reset Mode Pin
17 PDN
I
“L”: Power-down and Reset, “H”: Normal operation
The AK4556 should be reset once by bringing PDN pin = “L”.
27.5mA 2.4V to 3.6V (Normal/Double Speed)
2.7V to 3.6V (Quad Speed) 20TSSOP
(6.5mm x 6.4mm, 0.65mm Pitch)
MS0559-E-00 -2-
2006/11
元器件交易网
ASAHI KASEI
Note: Do not allow digital input pins except analog input pins (LIN and RIN) to float.
Handling of Unused Pin
The unused I/O pin should be processed appropriately as below.
- Dynamic Range, S/N: 106dB@VA=3.0V
- S/(N+D): 90dB@VA=3.0V
- Digital de-emphasis for 32kHz, 44.1kHz and 48kHz sampling
Audio I/F format: MSB First, 2’s Complement - ADC: 24bit MSB justified or I2S compatible - DAC: 24bit MSB justified, 24bit LSB justified or I2S compatible

5962F0253601VXA资料

1/11May 2004s LOW DROPOUT VOLTAGEsEMBEDDED OVERTEMPERATURE,OVERCURRENT PROTECTIONSs ADJUSTABLE CURRENT LIMITATION sOUTPUT OVERLOAD MONITORING/SIGNALLINGs FIXED 2.5;3.3V;5.0V OUTPUT VOLTAGES sINHIBIT (ON/OFF)TTL COMPATIBLE CONTROLsPROGRAMMABLE OUTPUT SHORT CIRCUIT CURRENTs REMOTE SENSING OPERATIONsRADHARD:TESTED UP TO 300krad IN MIL 1019.5AND LOW DOSE RATE CONDITIONS sHEAVY IONS SEL,SEU FREE.SUSTAINS 2x1014proton/cm 2,AND 2x1014neutron/cm²DESCRIPTIONThe RHFL4913Fixed is a high performance Rad Hard Positive Voltage Regulator family.Available into various hermetic ceramic packages,it is specifically intended for Space and harshradiation environments.Input supply range is from 3to 12volts.RHFL4913Fixed is Qml-V Qualified,DSCC Smd are 5962F02534/02535/02536/02537.RHFL4913FIXED VERSIONRAD-HARD POSITIVE FIXEDVOLTAGEREGULATORSRHFL4913FIXED VERSION2/11Table 1:Absolute Maximum Ratings (Note 1)Note 1:Exceeding maximum ratings may damage the device.Table 2:Thermal DataFigure 1:Connection Diagram (Top view,Bottom view for SMD.5)Table 3:Pin DescriptionSymbol ParameterValue Unit V I DC Input Voltage,V I -V GROUND 14V I O Output CurrentRHFL4913S,ESY 3A RHFL4913KP2P D T C =25°C Power Dissipation 15W T stg Storage Temperature Range-65to +150°C T op Operating Junction Temperature Range -55to +150°CESDElectrostatic Discharge CapabilityClass 3Symbol ParameterFPC-16TO-257SMD.5Unit R thj-case Thermal Resistance Junction-case 8.38.38.3°C/W T soldMaximum soldering Temperature,10sec.300°CPIN N°FPC-16SMD.5TO-257V O 1,2,6,713V I 3,4,521GND 1332I SC 8OCM 10INHIBIT 14SENSE 16NC9,11,12,15RHFL4913FIXED VERSION3/11Table 4:Ordering CodesTable 5:Part Number -Smd EquivalenceNote:3V version is available on request.Table 6:Environmental CharacteristicsFPC-16SMD.5TO-257SOLDER DIPPINGOUTPUT VOLTAGE RHFL4913KP25-01V RHFL4913S25-03V RHFL4913ESY2505V GOLD 2.5V RHFL4913KP25-02V RHFL4913S25-04V RHFL4913ESY2506V SOLDER 2.5V RHFL4913KP30-01V RHFL4913S30-03V RHFL4913ESY3005V GOLD 3.0V RHFL4913KP30-02V RHFL4913S30-04V RHFL4913ESY3006V SOLDER 3.0V RHFL4913KP33-01V RHFL4913S33-03V RHFL4913ESY3305V GOLD 3.3V RHFL4913KP33-02V RHFL4913S33-04V RHFL4913ESY3306V SOLDER 3.3V RHFL4913KP50-01V RHFL4913S50-03V RHFL4913ESY5005V GOLD 5.0V RHFL4913KP50-02VRHFL4913S50-04VRHFL4913ESY5006VSOLDER5.0VST PART NUMBER SMD PART NUMBER RHFL4913KP25-01V 5962F0253401VXC RHFL4913KP25-02V 5962F0253401VXA RHFL4913KP33-01V 5962F0253501VXC RHFL4913KP33-02V 5962F0253501VXA RHFL4913KP50-01V 5962F0253601VXC RHFL4913KP50-02V 5962F0253601VXA RHFL4913S25-03V 5962F0253402VYC RHFL4913S25-04V 5962F0253402VYA RHFL4913S33-03V 5962F0253502VYC RHFL4913S33-04V 5962F0253502VYA RHFL4913S50-03V 5962F0253602VYC RHFL4913S50-04V 5962F0253602VYA RHFL4913ESY2505V 5962F0253402VZC RHFL4913ESY2506V 5962F0253402VZA RHFL4913ESY3305V 5962F0253502VZC RHFL4913ESY3306V 5962F0253502VZA RHFL4913ESY5005V 5962F0253602VZC RHFL4913ESY5006V5962F0253602VZAParameterConditionsTypical Unit Output Voltage thermal drift -55°C to 125°C40ppm/°C Output Voltage radiation drift from 0krad to 300krad at 0.55rad/sec 8ppm/krad Output Voltage radiation driftfrom 0krad to 300krad,Mil 1019.56ppm/kradRHFL4913FIXED VERSION4/11Table 7:Electrical Characteristics (T J =25°C,V I =V O +2.5V,C I =C O =1µF,unless otherwise speci-fied)(*)This value is guaranteed by design.For each application it’s strongly recommended to comply with the maximum current limit of the pack-age used.Symbol ParameterTest ConditionsMin.Typ.Max.Unit V I Operating Input Voltage I O =1AT J =-55to 125°C312V V O Output Voltage accuracy V I =V O +2.5V,I O =5mA-22%I SHORT Output Current Limit (*)Adjustable by mask/external resistor4.5A V O Operating Output Voltage I O =2A,2.5V output voltage 2.45 2.55V V O Operating Output Voltage I O =2A,3.3V output voltage 3.23 3.37V V OOperating Output Voltage I O =2A,5.0V output voltage4.95.1V ∆V O /∆V I Line Regulation V I =V O +2.5V to 12V,I O =5mA 0.35%∆V O /∆V O Load Regulation V I =V O +2.5V,I O =5mA to 400mA 0.3%V I =V O +2.5V,I O =5mA to 1A 0.5%Z OUT Output Impedance I O =100mA DC and 20mA rms 100m ΩI qQuiescent CurrentV I =V O +2.5V,I O =5mA On Mode 6mAV I =V O +2.5V,I O =30mA On Mode 8V I =V O +2.5V,I O =300mA On Mode 25V I =V O +2.5V,I O =1A On Mode 60V I =V O +2V,V INH =2.4VOff Mode1I qQuiescent CurrentV I =V O +2.5V,I O =5mA,T J =-55to 125°C 6mAV I =V O +2.5V,I O =30mA,T J =-55to 125°C 14V I =V O +2.5V,I O =300mA,T J =-55to 125°C 40V I =V O +2.5V,I O =1A,T J =-55to 125°C100V dDropout Voltage I O =400mAV O =2.5to 9V,(-55°C)300400V Dropout VoltageI O =400mAV O =2.5to 9V,(25°C)350450I O =1A V O =2.5to 9V,(25°C)650I O =2AV O =2.5to 9V,(25°C)900Dropout VoltageI O =400mAV O =2.5to 9V,(125°C)450550I O =1A V O =2.5to 9V,(125°C)800I O =2AV O =2.5to 9V,(125°C)950V INH(ON)Inhibit Voltage I O =5mA,T J =-55to 125°C 0.8V V INH(OFF)Inhibit Voltage I O =5mA,T J =-55to 125°C 2.4V SVR Supply Voltage Rejection V I =V O +2.5V ±0.5V,I O =5mA f =120Hz 6070dB f =33KHz3040I SH Shutdown Input Current V INH =5V15µA V OCM OCM Pin Voltage Sinked I OCM =10mA active low0.38V t PLH t PHL Inhibit Propagation Delay V I =V O +2.5V,V INH =2.4V,I O =400mA ON-OFF 20µS OFF-ON100µS eNOutput Noise VoltageB=10Hz to 100KHzI O =5mA to 2A40µVrmsRHFL4913FIXED VERSION5/11Figure 2:Application Diagram For Remote Sensins OperationDEVICE DESCRIPTIONThe RHFL4913Fixed Voltage contains a PNP type power element controlled by a signal resulting from amplified comparison between the internal temperature compensated Band-Gap cell and the fraction of the desired Output Voltage value.This fractional value is obtained from an internal-to-die resistor divider bridge set by STMicroelectronics.The device is protected by several functional blocks.Low pin count Package limitationsSome functions (INHIBIT,OCM,SENSE)are not available due to lack of pins.Corresponding die pads are by default connected inside silicon.SENSE pinThe Load voltage is applied by a Kelvin line connected to SENSE pin:Voltage feed-back comes from the internal divider resistor bridge.Therefore possible output voltages are set by manufacturer mask metal options.SENSE pin is not available in 3pin packages.INHIBIT ON-OFF ControlBy setting INHIBIT pin TTL-High,the Device switches off the Output Current and Voltage.The Device is ON when INHIBIT pin is set Low.Since INHIBIT pin is internally pulled down,it can be left floating in case Inhibit function is not utilized.INHIBIT pin is not available in 3pin packages.Overtemperature protectionA temperature detector internally monitors the power element junction temperature.The Device goes OFF at approx.175°C,returning to ON mode when back to approx.40°C.It is worth noting that when the internal temperature detector reaches 175°C,the active power element can be at 225°C:Device reliability cannot be granted in case of extensive operation under these conditions.Overcurrent protectionI SC pin.An internal non-fold back Short-Circuit limitation is set with I SHORT >3.8A (V O is 0V).This value can be reduced by an external resistor connected between I SC pin and V I pin,with a typical value range of 10k Ωto 200k Ω.This adjustment feature is not available in 3pin packages.To keep excellent V O regulation,it is necessary to set I SHORT 1.6times greater than the maximum desired application I O .When I O reaches I SHORT –300mA,the current limiter overrules Regulation and V O starts to drop and the OCM flag is risen.When no current limitation adjustment is required,I SC pin must be left unbiased (as it is in 3pin packages).OCM pinGoes Low when current limiter starts to be active,otherwise V OCM =V I .It is bufferized and can sink 10mA.OCM pin is internally pulled-up by a 5k Ωresistor.Not available in 3pinpackages.RHFL4913FIXED VERSIONAlternate toRHFL4913Fixed(&custom)Voltages replace all3-terminal Industry Devices,providing essential benefits -Lower Drop-Out-High radiation performance-Better SVR-Saving the high stability external setting resistors.APPLICATION INFORMATIONThe RHFL4913Fixed Voltage is functional as soon as V I-V O voltage difference is slightly above the power element saturation voltage.A minimum0.5mA I O ensures perfect“no-load”regulation.All available V I pins must always be externally interconnected,same thing for all available V O pins, otherwise Device stability and reliability cannot be granted.All NC pins can be connected to Ground.The INHIBIT function switches off the output current in an electronic way,that is very quickly.According to Lenz’s Law,external circuitry reacts with–LdI/dt terms which can be of high amplitude in case some series-inductance exists.The effect would be a large transient voltage developed on both Device terminals.It is necessary to protect the Device with Schottky diodes preventing negative voltage excursions.In the worst case,a14V Zener diode shall protect the Device Input.The Device has been designed for high stability and low drop out operation:Minimum1µF input and output tantalum capacitors are therefore mandatory.Capacitor ESR range is from0.5Ωto over20Ω. Such range turns out to be useful when ESR increases at low temperature.When large transient currents are expected,larger value capacitors are necessary.In case of high current operation with expected short-circuit events,caution must be considered relatively to capacitors.They must be connected as close as possible to device terminals.As some tantalum capacitors may permanently fail when submitted to high charge-up surge currents,it is recommended to decouple them with470nF polyester capacitors.Being RHFL4913Fixed Voltage manufactured with very high speed bipolar technology6GHz f T transistors),the PCB lay-out must be performed with extreme care,very low inductance,low mutually coupling lines,otherwise high frequency parasitic signals may be picked-up by the Device resulting into er’s benefit is a SVR performance extended to far higher frequencies.REMOTE SENSING OPERATIONIn case the Load is located far from the regulator,it is recommended to comply with the scheme below.To obtain the best regulation,it is in addition essential to care about:-The wire connecting R2to the Load end must not be crossed by the Load current(Kelvin sense).The noise captured by the wires between the Load and the chip could bring a noisy output voltage.In case this happens,it is recommended that shielded cables are used for these connections.The external wrap must be used for connecting the ground of the chip with the Load Ground.It is also recommended to place 1uF tantalum capacitors between Output and Ground close to the device and another next to the Load. 6/11RHFL4913FIXED VERSION7/11DIM.mm.inchMIN.TYPMAX.MIN.TYP.MAX.A 2.162.720.0850.107b 0.430.017c 0.130.005D 9.910.390E 6.910.272E2 4.320.170E30.760.030e 1.270.050L 6.720.265Q 0.66 1.140.0260.045S10.130.005ALN FPC-16 (MIL-STD-1835) MECHANICAL DATA7450901A1816eb cLE DS1QAE2E3LE39RHFL4913FIXED VERSION8/11DIM.mm.inchMIN.TYPMAX.MIN.TYP.MAX.A 3.000.118A10.380.015b7.260.286b1 5.720.225b2 2.410.095b3 3.050.120D10.160.400D10.760.030E7.520.296e 1.910.075SMD.5 MECHANICAL DATA7386434ARHFL4913FIXED VERSION9/11DIM.mm.inch MIN.TYP MAX.MIN.TYP.MAX.A 10.540.415B 10.540.415C 16.640.655D 4.75.330.1850.210E 1.020.40F 3.56 3.68 3.810.1400.1450.150G 13.510.532H 5.260.207I 0.760.030J 3.050.120K 2.540.100L 15.216.50.5980.650M 2.290.090N 0.710.028R1.650.065TO-257 MECHANICAL DATA0117268CRHFL4913FIXED VERSIONTable8:Revision HistoryDate Revision Description of Changes 05-May-20045Mistake in Pin description SMD.5on Table310/11RHFL4913FIXED VERSION Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.The ST logo is a registered trademark of STMicroelectronicsAll other names are the property of their respective owners© 2004 STMicroelectronics - All Rights ReservedSTMicroelectronics GROUP OF COMPANIESAustralia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.11/11。

TGA4506-SM中文资料

VALUE
5V -1.5 TO 0V 190 mA 6 mA 9 dBm 0.24W 117 0C 260 C -65 to 150 C
0 0
NOTES2/ຫໍສະໝຸດ 2/2/ 3/ 4/
These ratings represent the maximum operable values for this device. Combinations of supply voltage, supply current, input power, and output power shall not exceed PD. When operated at this bias condition with a package base plate temperature of 85, the median life i s 1E+6 hrs. Junction operating temperature will directly affect the device median time to failure (MTTF). For maximum life, it is recommended that junction temperatures be maintained at the lowest possible levels.
元器件交易网
Advance Product Information
November 14, 2005
TGA4506-SM
Measured Data
Bias Conditions: Vd = 3.5 V, Id =60 mA
18 17 16
Output Power (dBm)
元器件交易网

1804N104xxx资料

元器件交易网Multilayer Ceramic Chip Capacitors Products – NPO, X7R, Y5VHOW TO ORDER 0603 N 101 J 500 N T Packaging Code T = 7” reel/paper tape Termination N = Ag/Ni/SnPb B = Cu/Ni/SnPb B = Bulk L = Ag/Ni/Sn C = Cu/Ni/Sn 251 = 250V 501 = 500V 102 = 1000VVoltage (VDCW) 100 = 10V 500 = 50V 160 = 16V 101 = 100V 250 = 25V 201 = 200VAPPLICATIONS ∗ ∗ ∗ ∗ ∗ LC and RC tuned circuit Filtering, Timing, & Blocking Coupling & Bypassing Frequency discriminating DecouplingCapacitance Tolerance (EIA Code) B = ±0.1pF F = ±1% K = ±10% C = ±0.25pF G = ±2% M = ±20% Z = -20+80% D = ±0.50pF J = ±5% Capacitance Two significant digits followed by # of zeros (e.g. 101 = 100pF, 102 = 1000pF, 103 = 10nF) Dielectric N = COG (NPO) Size Code 0402 0805 0603 1206 B = X7R 1210 1804 F = Y5VSCHEMATICL WT1812EENPO ∗ ∗ ∗ ∗ ∗ Ultra-stable Low dissipation factor Tight tolerance available Good frequency performance No aging of capacitance ∗ ∗ ∗ ∗X7R Semi-stable High K High volumetric efficiency Highly reliable in high temp. applications High insulation resistanceY5V ∗ High volumetric efficiency ∗ Non-polar construction ∗ General purpose, High KDIMENSIONS Size Length (L) Width (W) Termination (E) 0402 .040±0.0002 1.00±0.05 0.020±0.002 0.50±0.05 .010+.002/-.004 0.25+0.05/-0.10 0603 0.063±0.004 1.60±0.10 0.03±0.004 0.80±0.07 0.015±0.006 0.40±0.15 0805 0.080±0.006 2.00±0.15 0.050±0.006 1.25±0.15 0.020±0.008 0.50±0.20 1206 0.125±0.006 3.20±0.15 0.063±0.006 1.60±0.15 0.025±0.008 0.60±0.20 1210 0.125±0.012 3.20±0.30 0.100±0.008 2.50±0.20 0.030±0.010 0.75±0.25 1808 0.180±0.015 4.50±0.40 0.081±0.010 2.03±0.25 0.030±0.010 0.75±0.25 1812 0.180±0.015 4.50±0.40 0.125±0.012 3.20±0.30 0.030±0.010 0.75±0.25ELECTRICAL RATING Dielectric Capacitance Range Capacitance Tolerance Dissipation Factor T.C.C. Test Parameters (@25°C) Operating Temperature Insulation Resistance ≤100pF >1000pF NPO (COG) 0.5pF ~ 10nF ±0.1pF, ±0.25pF, ±0.50pF ±1%, ±2%, ±5%, ±10% >30pF, 0.1% Max 0±30ppm/°C 1.0±0.2Vrms, 1MHz±10% 1.0±0.2Vrms, 1KHz±10% -55 ~ +125°C @ 25°C +25°C, 10GΩ min or 500Ω-F min, whichever is less X7R (BME) 100pF ~ 1µF ±5%, ±10%, ±20% 6.3V: 10V & 16V: 25V & 50V: 5.0% 3.5% 2.5% Y5V 10nF ~ 10µF ±20%, -20+80% 6.3V: 10V & 16V: 25V & 50V: 5.0% 3.5% 2.5%0±15ppm/°C 1.0±0.2Vrms, 1KHz±10% -55 ~ +125°C @ 25°C +25°C, 10GΩ min or 500Ω-F min, whichever is less+30%/-80%ppm/°C 1.0±0.2Vrms, 1KHz±10% -25 ~ +85°C @ 20°C +25°C, 10GΩ min or 500Ω-F min, whichever is less570 West Lambert Road, Suite M, Brea, CA 92821 TEL: 714-255-9186 FAX: 714-255-9291American Accurate Components, Inc.1元器件交易网10 Volts – 50 VoltsDIELECTRIC SIZE EIA Cap Code VDCW 0R5 0.5pF 1R0 1 1R2 1.2 1R5 1.5 1R8 1.8 2R2 2.2 2R7 2.7 3R3 3.3 3R9 3.9 4R7 4.7 5R6 5.6 6R8 6.8 8R2 8.2 100 10pF 120 12 150 15 180 18 220 22 270 27 330 33 390 39 470 47 560 56 680 68 820 82 101 100pF 121 120 151 150 181 180 221 220 271 270 331 330 391 390 471 470 561 560 681 680 821 820 102 1000pF 122 1200 152 1500 182 1800 222 2200 272 2700 332 3300 392 3900 472 4700 562 5600 682 6800 822 8200 103 .010µF 123 12000 153 15000 183 18000 223 22000 273 27000 333 33000 393 0.39µFMLCC Products – NPO TypeNPO 10 N N N N N N N N N N N N N N N N 0402 16 25 N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N 50 N N N N N N N N N N N N N N 10 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S 0603 16 25 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S 50 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S 10 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A B B B B B B B B B B D D D D D D D D 0805 16 25 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A B B B B B B B B B B B B B B B B B B B B D D D D D D D D D D D D 50 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A B B B B B B B B B B D D D 10 1206 16 25 50 10 1210 16 25 50 10 1812 16 25 50B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B C C D D D D D D D GB B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B C C D D D D D D D GB B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B C CB B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B C CC C C C C C C C C C C C C C C C C C C C C C C C C C C C C CC C C C C C C C C C C C C C C C C C C C C C C C C C C C C CC C C C C C C C C C C C C C C C C C C C C C C C C C C C C CC C C C C C C C C C C C C C C C C C C C C C C C C C C C C CD D D D D D D D D D D D DD D D D D D D D D D D D DD D D D D D D D D D D D DD D D D D D D D D D D D D* Variations of size, capacitance, voltage, and 13” reel are available upon request.570 West Lambert Road, Suite M, Brea, CA 92821 TEL: 714-255-9186 FAX: 714-255-9291American Accurate Components, Inc.2元器件交易网100 Volts – 3000 VoltsMLCC Products – NPO TypeDIELECTRIC NPO EIA SIZE 0603 0805 1206 1210 CODE VDCW 100 100 200 250 500 100 200 250 500 1000 2000 100 200 250 500 1000 2000 100 200 0R5 0.5pF S A A A A B B B B B B 1R0 1 S A A A A B B B B B B 1R2 1.2 S A A A A B B B B B B 1R5 1.5 S A A A A B B B B B B 1R8 1.8 S A A A A B B B B B B 2R2 2.2 S A A A A B B B B B B 2R7 2.7 S A A A A B B B B B B 3R3 3.3 S A A A A B B B B B B 3R9 3.9 S A A A A B B B B B B 4R7 4.7 S A A A A B B B B B B 5R6 5.6 S A A A A B B B B B B 6R8 6.8 S A A A A B B B B B B 8R2 8.2 S A A A A B B B B B B 100 10pF S A A A A B B B B B B C C C C C C D D 120 12 S A A A A B B B B B B C C C C C C D D 150 15 S A A A A B B B B B B C C C C C C D D 180 18 S A A A A B B B B B B C C C C C C D D 220 22 S A A A A B B B B B B C C C C C C D D 270 27 S A A A A B B B B B B C C C C C C D D 330 33 S A A A A B B B B B B C C C C C C D D 390 39 S A A A A B B B B B B C C C C C C D D 470 47 S A A A A B B B B B B C C C C C C D D 560 56 S A A A A B B B B B C C C C C C D D D 680 68 S A A A B B B B B B C C C C C C D D D 820 82 S A A A B B B B B B C C C C C D D D 101 100pF S A A A C B B B B C C C C C C D D D 121 120 S A C C C B B B B C C C C C C D D D 151 150 S A C C D B B B B C C C C C D D D 181 180 S A D D B B B B C C C C C D D D 221 220 S A B B B B C C C C C D D D 271 270 S A B B B C C C C C C D D 331 330 S A B B B C C C C C D D D 391 390 B B B B C C C C C D D D 471 470 B B C C C C C C D D D 561 560 B B C C C C D D 681 680 B C C C C D D 821 820 B C C C C D D 102 1000pF B C C C C D D 122 1200 B C D D D D 152 1500 C C D D D D 182 1800 C C D D D D 222 2200 C D D D D 272 2700 C D D D D 332 3300 C D 392 3900 D 472 4700 D 562 5600 682 6800 822 8200 103 .010µF * Variations of size, capacitance, voltage, and 13” reel are available upon request. TAPE/REEL PACKAGE TYPE, QUANTITY, AND AVAILABILITY Thickness in mm A = 0.65 + 0.05/-0.15 B = 0.85 + 0.5/-0.15 C = 1.00 + 0.05/-0.15 D = 1.2 + 0.15 G = 1.60 + 0.05/-0.15 K = 2.00 + 0.2 M = 2.5 + 0.3 N = 0.5 + 0.05 S = 0.8 + 0.07 0402 Type Qty Paper 10K 0603 Type Qty Paper 4K 0805 Type Qty Paper 4K Paper 4K Plastic 3K Plastic 3K 1206 Type Qty Paper 4K Paper 4K Plastic 3K Plastic 3K Plastic 2K -1812 1808 250 500 1000 2000 3000 1000 2000 3000D D D D D D D D D D D D D D D D D D D D D D D D D D D D D DD D D D D D D D D D D D D D D D D D D D D D D D D D D DD D D D D D D D D D D D D D D D D D D D D D D DD D D D D D D D D D D D D D D D D D D DD D D D DC C C C C C C C C C C C C K K K K K KC C C C C C C C C C C K K K K KC C C C C C C C C C C C C C1210 Type QtyPlastic Plastic Plastic Plastic Plastic -3K 3K 2K 2K 1K -1808 Type Qty Plastic 2K Plastic 2K Plastic 1K Plastic 1K -1812 Type Qty Plastic 1K Plastic 1K Plastic 1K Plastic 1K -570 West Lambert Road, Suite M, Brea, CA 92821 TEL: 714-255-9186 FAX: 714-255-9291American Accurate Components, Inc.3元器件交易网10 Volts – 50 VoltsMLCC Products – X7R TypeDIELECTRIC X7R SIZE 0402 0603 0805 EIA Cap Code VDCW 10 16 25 50 10 16 25 50 10 16 25 50 10 101 100pF N N N N S S S S B B B B 121 120 N N N N S S S S B B B B 151 150 N N N N S S S S B B B B 181 180 N N N N S S S S B B B B 221 220 N N N N S S S S B B B B B 271 270 N N N N S S S S B B B B B 331 330 N N N N S S S S B B B B B 391 390 N N N N S S S S B B B B B 471 470 N N N N S S S S B B B B B 561 560 N N N N S S S S B B B B B 681 680 N N N N S S S S B B B B B 821 820 N N N N S S S S B B B B B 102 1000pF N N N N S S S S B B B B B 122 1200 N N N N S S S S B B B B B 152 1500 N N N N S S S S B B B B B 182 1800 N N N N S S S S B B B B B 222 2200 N N N N S S S S B B B B B 272 2700 N N N S S S S B B B B B 332 3300 N N N S S S S B B B B B 392 3900 N N N S S S S B B B B B 472 4700 N N S S S S B B B B B 562 5600 N N S S S S B B B B B 682 6800 N N S S S S B B B B B 822 8200 N N S S S S B B B B B 103 N N S S S S B B B B B .010µF 123 .012 N N S S S S B B B B B 153 .015 N N S S S S B B B B B 183 .018 S S S S B B B B B 223 .022 S S S S B B B B B 273 .027 S S S S B B B B B 333 .033 S S S B B B B B 393 .039 S S S B B B B B 473 .047 S S S B B B B B 563 .056 S S S B B B B B 683 .068 S S S B B B B B 823 .082 S S B B B D B 104 S S B B B D B .100µF 154 .150 D D D C 184 .180 D D D C 224 .220 D D D C 334 .330 C 474 .470 684 .680 824 .820 105 1.00µF * Variations of size, capacitance, voltage, and 13” reel are available upon request. TAPE/REEL PACKAGE TYPE, QUANTITY, AND AVAILABILITY Thickness in mm A = 0.65 + 0.05/-0.15 B = 0.85 + 0.5/-0.15 C = 1.00 + 0.05/-0.15 D = 1.2 + 0.15 F = 1.40 + 0.05/-0.15 G = 1.60 + 0.05/-0.15 S = 0.8 + 0.07 N = 0.5 + 0.05 0402 – 0603 Type Quantity 0805 – 1206 Type Quantity Paper 4K/Reel Paper 4K/Reel Plastic 3K/Reel Plastic 3K/Reel Plastic 2K/Reel Plastic 2K/Reel Type 1210 Quantity Type 1808 Quantity Type 1812 Quantity1206 16 2550101210 16 2550101812 16 2550B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B C C C CB B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B C C C CB B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B C C CC C C C C C C C C C C C C C C C C C C C C C C C C C C C C C CC C C C C C C C C C C C C C C C C C C C C C C C C C C C C C CC C C C C C C C C C C C C C C C C C C C C C C C C C C C C C CC C C C C C C C C C C C C C C C C C C C C C C C C C C C C CD D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D DD D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D DD D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D DD D D D D D D D D D D D D D D D D D D D D D D D D D D D D D DPlastic Plastic Plastic Plastic3K/Reel 3K/Reel 2K/Reel 2K/ReelPlastic Plastic Plastic Plastic3K/Reel 3K/Reel 1K/Reel 1K/ReelPlastic Plastic Plastic1K/Reel 1K/Reel 1K/ReelPaper Paper4K/Reel 10K/Reel570 West Lambert Road, Suite M, Brea, CA 92821 TEL: 714-255-9186 FAX: 714-255-9291American Accurate Components, Inc.4元器件交易网100 Volts – 3000 VoltsMLCC Products – X7R TypeDIELECTRIC X7R EIA SIZE 0603 0805 1206 1210 1812 1808 CODE VDCW 100 100 200 250 500 100 200 250 500 1000 1000 2000 100 200 250 500 1000 100 200 250 500 1000 2000 1000 1500 3000 101 100pF S B B B B 121 120 S B B B B 151 150 S B B B B 181 180 S B B B B B B B B B B B 221 220 S B B B B B B B B B B B 271 270 S B B B B B B B B B B B 331 330 S B B B B B B B B B B B 391 390 S B B B B B B B B B B B 471 470 S B B B B B B B B B B B D D C C C 561 560 S B B B B B B B B B B C D D C C C 681 680 S B B B B B B B B B B C D D C C C 821 820 S B B B B B B B B B G G D D C C C 102 1000pF S B B B B B B B B B G G C C C C C D D D D D D C C K 122 1200 S B B B B B B B B B G G C C C C C D D D D D D C C K 152 1500 S B B B B B B B B B G C C C C C D D D D D D C C 182 1800 S B B B B B B B B B G C C C C C D D D D D D C C 222 2200 S B B B B B B B B C G C C C C C D D D D D D C C 272 2700 S B B B B B B B D G C C C C C D D D D D D C D 332 3300 S B B B B B B B G G C C C C D D D D D D D C D 392 3900 S B B B B B B B G G C C C C D D D D D D C 472 4700 S B B B B B B B G G C C C C D D D D D D C 562 5600 S B B B B B G C C C C D D D D D D C 682 6800 S B B B B B G C C C C D D D D D D C 822 8200 S B B B B C C C C C D D D D D D 103 S B B B B C C C C C D D D D D D .010µF 123 .012 S B B B B C C C C D D D D 153 .015 S B B C C C C C C D D D D 183 .018 B B C C C C C C D D D D 223 .022 B C C C C C D D D D D 273 .027 B C C C C C D D D D 333 .033 B C C C D D D D 393 0.39 B C C C D D D D 473 .047 B C D D D D D D 563 .056 B C D D D 683 .068 C C D D D 823 .082 C C D D D 104 D C D D D .100µF 124 .120 D C D D D 154 .150 C D 184 .180 C D 224 .220 C D 334 .330 D 474 .470 D 684 .680 824 .820 105 1.00µF * Variations of size, capacitance, voltage, and 13” reel are available upon request. TAPE/REEL PACKAGE TYPE, QUANTITY, AND AVAILABILITY Thickness in mm A = 0.65 + 0.05/-0.15 B = 0.85 + 0.5/-0.15 C = 1.00 + 0.05/-0.15 D = 1.2 + 0.15 F = 1.40 + 0.05/-0.15 G = 1.60 + 0.05/-0.15 K = 2.00 + 0.2 S = 0.8 + 0.07 N = 0.5 + 0.05 0603-0805-1206 Type Quantity Paper 4K/Reel Paper 4K/Reel Plastic 3K/Reel Plastic 3K/Reel Plastic 2K/Reel Plastic 2K/Reel Type 1210 Quantity Type 1808 Quantity Type 1812 QuantityPlastic Plastic Plastic Plastic3K/Reel 3K/Reel 2K/Reel 2K/ReelPlastic Plastic Plastic Plastic Plastic3K/Reel 3K/Reel 1K/Reel 1K/Reel 1K/ReelPlastic Plastic Plastic Plastic1K/Reel 1K/Reel 1K/Reel 1K/Reel570 West Lambert Road, Suite M, Brea, CA 92821 TEL: 714-255-9186 FAX: 714-255-9291American Accurate Components, Inc.5元器件交易网10 Volts – 50 VoltsMLCC Products – Y5V TypeDIELECTRIC Y5V SIZE 0402 0603 0805 EIA Cap Code VDCW 10 16 25 50 10 16 25 50 10 16 25 50 10 103 N N N S S S S A A A A B .010µF 123 .012 N N N S S S S A A A A B 153 .015 N N N S S S S A A A A B 183 .018 N N N S S S S A A A A B 223 .022 N N N S S S S A A A A B 273 .027 N N N S S S S A A A A B 333 .033 N N N S S S S A A A A B 393 .039 N N N S S S S A A A A B 473 .047 N N N S S S S A A A A B 563 .056 N N S S S S A A A A B 683 .068 N N S S S S A A A A B 823 .082 N N S S S S A A A A B 104 N N S S S S A A A A B .100µF 154 .150 S S S S A A A A B 224 .220 S S S A A A A B 334 .330 S S B B B B 474 .470 S S B B B B 684 .680 S B B B 105 S B B C 1.00µF 155 1.50 C 225 2.20 C 335 3.30 D 475 4.75 D 106 10µF * Variations of size, capacitance, voltage, and 13” reel are available upon request.1206 16 25 B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B C C C C C C D D D D50 B B B B B B B B B B B B B B B B B101210 16 2550101812 16 2550C C C C C C CC C C C C C CC C C C C C CC C C CD D D D D D DD D D D D D DD D D D D D DD D D D D D D100 Volts – 500 VoltsDIELECTRIC Y5V SIZE 0805 1206 1812 EIA Cap Code VDCW 100 200 250 500 100 200 250 500 100 200 250 103 B B B B B .010µF 123 .012 B B B B B 153 .015 B B B B B 183 .018 B B B B B 223 .022 B B B B B 273 .027 B B B B B 333 .033 B B B B B 393 .039 B B B B B 473 .047 B B B B 563 .056 B B B B 683 .068 B B B B 823 .082 B C C C 104 B C C C D D D .100µF 154 .150 C D D D 224 .220 C D D D 334 .330 D D D 474 .470 D D D * Variations of size, capacitance, voltage, and 13” reel are available upon request. TAPE/REEL PACKAGE TYPE, QUANTITY, AND AVAILABILITY Thickness in mm A = 0.65 + 0.05/-0.15 B = 0.85 + 0.5/-0.15 C = 1.00 + 0.05/-0.15 D = 1.2 + 0.15 F = 1.40 + 0.05/-0.15 G = 1.60 + 0.05/-0.15 K = 2.00+0.2mm S = 0.8 + 0.07 N = 0.5 + 0.05 0402 – 0603 Type Quantity 0805 – 1206 Type Quantity Paper 4K/Reel Paper 4K/Reel Plastic 3K/Reel Plastic 3K/Reel Plastic 2K/Reel Plastic 2K/Reel Type 1210 Quantity Type 1808 Quantity Type 1812 Quantity 500Plastic Plastic Plastic Plastic3K/Reel 3K/Reel 2K/Reel 2K/ReelPlastic Plastic Plastic Plastic3K/Reel 3K/Reel 1K/Reel 1K/ReelPlastic Plastic Plastic Plastic1K/Reel 1K/Reel 1K/Reel 1K/ReelPaper Paper4K/Reel 10K/Reel570 West Lambert Road, Suite M, Brea, CA 92821 TEL: 714-255-9186 FAX: 714-255-9291American Accurate Components, Inc.6元器件交易网MLCC Products – PackagingPACKAGING ON TAPE AND REEL Size 0603 0805 T (mm) 0.90~0.70 0.70~0.50 0.90~0.70 1.05~0.85 1.35~1.05 0.90~0.70 1.05~0.85 1.35~1.05 1.05~0.85 1.35~1.05 1.05~0.85 2.15~1.85 1.35~1.05 Tape Paper Tape Paper Tape Paper Tape Plastic Tape Plastic Tape Paper Tape Plastic Tape Plastic Tape Plastic Tape Plastic Tape Plastic Tape Plastic Tape Plastic Tape Quantity 4,000/Reel 4,000/Reel 4,000/Reel 3,000/Reel 3,000/Reel 4,000/Reel 3,000/Reel 3,000/Reel 3,000/Reel 3,000/Reel 3,000/Reel 1,000/Reel 1,000/ReelAREEL FOR TAPINGTaping is in accordance with EIA RS-481 or IEC 286-3TB* C N D1206 1210 1808 1812GUnit: mm Symbol DimensionA 178 ± 2.0N 50 minC 130 ± 0.5D 20 min.B 2.0±0.5G 10.0± 1.5T 14.9max1. PAPER TAPE DIMENSIONSt Feeding hole D A B Chip Capacitors Unlt:mm P P P Direction of FeedE2. PLASTIC TAPE DIMENSIONSChip pocket t Feeding hole D A B Chip Capacitors P Po PChip pocketEF WFWk Unlt:mmDirection of FeedPAPER TAPE W F E P1 P2 P0 ∅P t1 Dimensions in mm 8.0 ± 0.3 3.5 ± 0.05 1.75 ± 0.1 4.0 ± 0.1 2.0 ± 0.05 4.0 ± 0.1 1.5 + 0.1 –0 1.2 maximumPLASTIC TAPE W F E P1 P2 P0 ∅P t1 K Dimension in mm 8.0 ± 0.3 3.5 ± 0.05 1.75 ± 0.1 4.0 ± 0.1 2.0 ± 0.05 4.0 ± 0.1 1.5 + 0.1 –0 0.3 maximum 2.0 maximum570 West Lambert Road, Suite M, Brea, CA 92821 TEL: 714-255-9186 FAX: 714-255-9291American Accurate Components, Inc.7。

光耦a4506参考资料

Intelligent Power Module and Gate Drive Interface Optocouplers Technical DataFeatures• Performance Specified for Common IPM Applications over Industrial Temperature Range: -40°C to 100°C• Fast Maximum Propagation Delayst PHL = 480ns t PLH = 550ns• Minimized Pulse Width Distortion PWD = 450 ns• 15 kV/µs Minimum Common Mode Transient Immunity at V CM = 1500 V• CTR > 44% at I F = 10mA • Safety Approval UL Recognized-3750 V rms / 1 min. for HCPL-4506/0466/J456-5000 V rms / 1 min. for HCPL-4506 Option 020 and HCNW4506CSA ApprovedIEC/EN/DIN EN 60747-5-2Approved-V IORM = 560 Vpeak for HCPL-0466 Option 060-V IORM = 630 Vpeak for HCPL-4506 Option 060-V IORM = 891 Vpeak for HCPL-J456-V IORM = 1414 Vpeak for HCNW4506The connection of a 0.1 µF bypass capacitor between pins 5 and 8 is recommended.Applications• IPM Isolation• Isolated IGBT/MOSFET Gate Drive• AC and Brushless DC Motor Drives• Industrial InvertersHCPL-4506HCPL-J456HCPL-0466HCNW4506CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.Functional Diagram Truth TableLEDV O ON L OFFH87613SHIELD52420 k ΩNC ANODE CATHODE NC V CCV LV OGNDSelection GuideStandard White Mold Package 8-Pin DIP 8-Pin DIP Small OutlineWidebody Type (300 Mil)(300 Mil)SO8(400 Mil)Hermetic*Part HCPL-4506HCPL-J456HCPL-0466HCNW4506HCPL-5300NumberHCPL-5301IEC/EN/DIN V IORM = 630 Vpeak V IORM = 891 Vpeak V IORM = 560 Vpeak V IORM = 1414 Vpeak —EN 60747-(Option 060)(Option 060)5-2Approval*Technical data for these products are on separate Agilent publications.Ordering InformationSpecify Part Number followed by Option Number (if desired).Example:HCPL-4506#XXXX020 = UL 5000 V rms/1 minute Option** for HCPL-4506 Only.060 = IEC/EN/DIN EN 60747-5-2 Option** for HCPL-4506/0466.300 = Gull Wing Lead Option for HCPL-4506/J456, HCNW4506.500 = Tape and Reel Packaging Option XXXE = Lead Free OptionOption data sheets are available. Contact Agilent sales representative or authorized distributor for information.**Combination of Option 020 and Option 060 is not available.Remarks: The notation “#” is used for existing products, while (new) products launched since 15th July 2001 and lead free option will use “-”DescriptionThe HCPL-4506 and HCPL-0466contain a GaAsP LED while the HCPL-J456 and the HCNW4506contain an AlGaAs LED. The LED is optically coupled to an inte-grated high gain photo detector.Minimized propagation delaydifference between devices makes these optocouplers excellent solutions for improving inverter efficiency through reduced switching dead time.An on chip 20 k Ω output pull-up resistor can be enabled byshorting output pins 6 and 7, thus eliminating the need for an external pull-up resistor in common IPM applications.Specifications and performance plots are given for typical IPM applications.Package Outline DrawingsHCPL-4506 Outline DrawingHCPL-4506 Gull Wing Surface Mount Option 300 Outline Drawing0.254+ 0.076 - 0.051(0.010+ 0.003) - 0.002)DIMENSIONS IN MILLIMETERS AND (INCHES).* MARKING CODE LETTER FOR OPTION NUMBERS "L" = OPTION 020 "V" = OPTION 060OPTION NUMBERS 300 AND 500 NOT MARKED.NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.(0.025 ± 0.005)(0.100)BSCDIMENSIONS IN MILLIMETERS (INCHES).LEAD COPLANARITY = 0.10 mm (0.004 INCHES).+ 0.076 - 0.051+ 0.003) - 0.002)NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.Package Outline DrawingsHCPL-J456 Outline DrawingHCPL-J456 Gull Wing Surface Mount Option 300 Outline Drawing0.254+ 0.076 - 0.051(0.010+ 0.003) - 0.002)DIMENSIONS IN MILLIMETERS AND (INCHES).* MARKING CODE LETTER FOR OPTION NUMBERS "L" = OPTION 020 "V" = OPTION 060OPTION NUMBERS 300 AND 500 NOT MARKED.NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX.(0.025 ± 0.005)(0.100)BSCDIMENSIONS IN MILLIMETERS (INCHES).LEAD COPLANARITY = 0.10 mm (0.004 INCHES).+ 0.076 - 0.051+ 0.003) - 0.002)NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX.HCPL-0466 Outline Drawing (8-Pin Small Outline Package)HCNW4506 Outline Drawing (8-Pin Widebody Package)(0.012)MIN.5.207 ± 0.254 (0.205 ± 0.010) DIMENSIONS IN MILLIMETERS (INCHES).LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX. NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.*1.78 ± 0.15 NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.+ 0.076 - 0.0051+ 0.003) - 0.002)HCNW4506 Gull Wing Surface Mount Option 300 Outline Drawing1.78 ± 0.15MAX.BSCDIMENSIONS IN MILLIMETERS (INCHES).LEAD COPLANARITY = 0.10 mm (0.004 INCHES).NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.Pb-Free IR ProfileSolder Reflow Temperature ProfileTIME (SECONDS)T E M P E R A T U R E (°C )ROOMT T T 25T TIMET E M P E R A T U R NOTES:THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX. T smax = 200 °C, T smin = 150 °CInsulation and Safety Related SpecificationsValueParameterSymbol HCPL-4506HCPL-J456HCPL-0466HCNW4506UnitsConditionsMinimum External L(101)7.17.4 4.99.6mmMeasured from input Air Gap (External terminals to output Clearance)terminals, shortest distance through air.Minimum External L(102)7.48.0 4.810.0mmMeasured from input Tracking (External terminals to output Creepage)terminals, shortestdistance path along body.Minimum Internal 0.080.50.08 1.0mmThrough insulation Plastic Gapdistance, conductor to (Internal Clearance)conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity.Minimum Internal NA NA NA 4.0mmMeasured from input Tracking (Internal terminals to outputCreepage)terminals, along internal cavity.Tracking Resistance CTI≥175≥175≥175≥200VoltsDIN IEC 112/VDE 0303(Comparative Part 1Tracing Index)Isolation GroupIIIa IIIa IIIa IIIaMaterial Group (DINVDE 0110, 1/89, Table 1)Regulatory InformationThe devices contained in this data sheet have been approved by the following agencies:Agency/StandardHCPL-4506HCPL-J456HCPL-0466HCNW4506Underwriters Laboratories (UL) UL 1577 Recognized under UL 1577, ComponentRecognized Program, Category FPQU2, File E55361Canadian Standards Component Association (CSA) Acceptance File CA88324 Notice #5 Verband Deutscher DIN VDE 0884 Electrotechniker (VDE) (June 1992)IEC/EN/DIN EN 60747-5-2 Approved under:IEC 60747-5-2:1997 + A1:2002EN 60747-5-2:2001 + A1:2002DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01All Agilent data sheets report the creepage and clearance inherent to the optocoupler component itself. Thesedimensions are needed as a starting point for the equipment designer when determining the circuit insulation require-ments. However, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered. There are recom-mended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending on factors such as pollution degree and insulation level.IEC/EN/DIN EN 60747-5-2 Insulation Related CharacteristicsHCPL-0466HCPL-4506Description Symbol Option 060Option 060HCPL-J456HCNW4506Unit Installation classification perDIN VDE 0110/1.89, Table 1for rated mains voltage ≤150 V rms I-IV I-IV I-IV I-IVfor rated mains voltage ≤300 V rms I-III I-IV I-IV I-IVfor rated mains voltage ≤450 V rms I-III I-III I-IVfor rated mains voltage ≤600 V rms I-III I-IVfor rated mains voltage ≤1000 V rms I-IIIClimatic Classification55/100/2155/100/2155/100/2155/100/21 Pollution Degree2222(DIN VDE 0110/1.89)Maximum Working V IORM5606308911414V peak Insulation VoltageInput to Output Test Voltage,Method b* V IORM x 1.875 = V PR,100% Production Test with t m=V PR1050118116702652V peak 1 sec, Partial Discharge < 5pCInput to Output Test Voltage,Method a* V IORM x 1.5 = V PR,Type and Sample Test, t m = 60 sec,V PR84094513362121V peak Partial Discharge < 5pCHighest Allowable Overvoltage*V IOTM4000600060008000V peak (Transient Overvoltage, t ini = 10 sec)Safety Limiting Values – maximumvalues allowed in the event of a fail-ure, also see Thermal Derating curve.Case Temperature T S150175175150°C Input Current I S INPUT150230400400mA Output Power P S OUTPUT600600600700mW Insulation Resistance at T S,R S≥ 109≥109≥109≥109ΩV IO = 500 V*Refer to the optocoupler section of the Designer's Catalog, under regulatory information (IEC/EN/DIN EN 60747-5-2) for a detailed description of Method a and Method b partial discharge test profiles.Note: These optocouplers are suitable for "safe electrical isolation" only within the safety limit data. Maintenance of the safety data shall be ensured by means of protective circuits.Note: Insulation Characteristics are per IEC/EN/DIN EN 60747-5-2.Note: Surface mount classification is Class A in accordance with CECC 00802.Absolute Maximum RatingsRecommended Operating ConditionsParameter Symbol Min.Max.Units Power Supply Voltage V CC 4.530Volts Output Voltage V O030Volts Input Current (ON)I F(on)1020mA Input Voltage (OFF)V F(off)*-50.8V Operating Temperature T A-40100°C*Recommended V F(OFF) = -3 V to 0.8 V for HCPL-J456, HCNW4506.Electrical SpecificationsOver recommended operating conditions unless otherwise specified:T A = -40°C to +100°C, V CC = +4.5 V to 30 V, I F(on) = 10 mA to 20mA, V F(off) = -5 V to 0.8 V† Parameter Symbol Device Min.Typ.*Max.Units Test Conditions Fig.Note Current Transfer Ratio CTR4490%I F = 10 mA,5V O = 0.6 VLow Level Output Current I OL 4.49.0mA I F = 10 mA,1, 2V O = 0.6 VLow Level Output Voltage V OL0.30.6V I O = 2.4 mAInput Threshold Current I TH HCPL-4506 1.55mA V O = 0.8 V,116HCPL-0466I O = 0.75 mAHCNW4506HCPL-J4560.6High Level Output Current I OH550µA V F = 0.8 V3High Level Supply Current I CCH0.6 1.3mA V F = 0.8 V,16V O = OpenLow Level Supply Current I CCL0.6 1.3mA I F = 10 mA,16V O = OpenInput Forward Voltage V F HCPL-4506 1.5 1.8V I F = 10 mA4HCPL-0466HCPL-J456 1.2 1.6 1.955HCNW4506 1.6 1.85Temperature Coefficient∆V F/∆T A HCPL-4506-1.6mV/°C I F = 10 mAof Forward Voltage HCPL-0466HCPL-J456HCNW4506-1.3Input Reverse Breakdown BV R HCPL-45065V I R = 10 µAVoltage HCPL-0466HCPL-J4563I R = 100 µAHCNW4506Input Capacitance C IN HCPL-450660pF f = 1 MHz,HCPL-0466V F = 0 VHCPL-J45672HCNW4506Internal Pull-up Resistor R L142025kΩT A = 25°C12,13 Internal Pull-up Resistor∆R L/∆T A0.014kΩ/°CTemperature Coefficient*All typical values at 25°C, V CC = 15 V.†V F(off) = -3 V to 0.8 V for HCPL-J456, HCNW4506.Switching Specifications (R L= 20 kΩ External)Over recommended operating conditions unless otherwise specified:T A = -40°C to +100°C, V CC = +4.5 V to 30 V, I F(on) = 10 mA to 20mA, V F(off) = -5 V to 0.8 V†Parameter Symbol Min.Typ.*Max. Units Test Conditions Fig.Note Propagation Delay T PHL30200400ns C L = 100 pF I F(on) = 10 mA,6, 8,11, Time to Logic HCPL-J456480V F(off) = 0.8 V,10-14, Low at Output100C L = 10 pF V CC = 15.0 V,1316 Propagation Delay T PLH270400550ns C L = 100 pF V THLH = 2.0 V,Time to High V THHL = 1.5 VOutput Level130C L = 10 pFPulse Width PWD200450ns C L = 100 pF20 DistortionPropagation Delay t PLH-t PHL-150200450ns17 Difference BetweenAny 2 PartsOutput High Level|CM H|1530kV/µs I F = 0 mA,V CC = 15.0 V,718 Common Mode V O > 3.0 V C L = 100 pF,Transient Immunity V CM = 1500 V p-pOutput Low Level|CM L|1530kV/µs I F = 10 mA T A = 25°C19 Common Mode V O < 1.0 VTransient ImmunitySwitching Specifications (R L= Internal Pull-up)Over recommended operating conditions unless otherwise specified:T A = -40°C to +100°C, V CC = +4.5 V to 30 V, I F(on) = 10 mA to 20mA, V F(off) = -5 V to 0.8 V†Parameter Symbol Min.Typ.*Max.Units Test Conditions Fig.Note Propagation Delay t PHL20200400ns I F(on) = 10 mA, V F(off) = 0.8 V,6, 911-14, Time to Logic HCPL-J456485V CC = 15.0 V, C L = 100 pF,16 Low at Output V THLH = 2.0 V, V THHL = 1.5 VPropagation Delay Time t PLH220450650nsto High Output LevelPulse Width PWD250500ns20 DistortionPropagation Delay t PLH-t PHL-150250500ns17 Difference BetweenAny 2 PartsOutput High Level|CM H|30kV/µs I F = 0 mA,V CC = 15.0 V,718 Common Mode V O > 3.0 V C L = 100 pF,Transient Immunity V CM = 1500 V p-p,Output Low Level|CM L|30kV/µs I F = 16 mA,T A = 25°C19 Common Mode V O < 1.0 VTransient ImmunityPower Supply PSR 1.0V p-p Square Wave, t RISE, t FALL16 Rejection> 5 ns, no bypass capacitors*All typical values at 25°C, V CC = 15 V.†V F(off) = -3 V to 0.8 V for HCPL-J456, HCNW4506.Package CharacteristicsOver recommended temperature (T A = -40°C to 100°C) unless otherwise specified.Parameter Sym.Device Min.Typ.*Max.Units Test Conditions Fig.Note Input-Output Momentary V ISO HCPL-45063750V rms RH < 50%6,7,10 Withstand Voltage†HCPL-0466t = 1 min.HCPL-J4563750T A = 25°C6,8,10HCPL-450650006,9,Option02015HCNW450650006,9,10 Resistance R I-O HCPL-45061012V I-O = 500 Vdc6 (Input-Output)HCPL-J456ΩHCPL-0466HCNW450610121013Capacitance C I-O HCPL-45060.6pF f = 1 MHz6 (Input-Output)HCPL-0466HCPL-J4560.8HCNW45060.5Notes:1.Derate linearly above 90°C free-airtemperature at a rate of 0.8 mA/°C.2.Derate linearly above 90°C free-airtemperature at a rate of 1.6 mA/°C.3.Derate linearly above 90°C free-airtemperature at a rate of 3.0 mW/°C.4.Derate linearly above 90°C free-airtemperature at a rate of 4.2 mW/°C.5.CURRENT TRANSFER RATIO inpercent is defined as the ratio ofoutput collector current (I O) to theforward LED input current (I F) times100.6.Device considered a two-terminaldevice: Pins 1, 2, 3, and 4 shortedtogether and Pins 5, 6, 7, and 8shorted together.7.In accordance with UL 1577, eachoptocoupler is proof tested byapplying an insulation test voltage≥4500 V rms for 1 second (leakagedetection current limit, I I-O≤5 µA).8. In accordance with UL 1577, eachoptocoupler is proof tested byapplying an insulation test voltage ≥4500 V rms for 1 second (leakagedetection current limit, I i-o≤ 5 µA). 9. In accordance with UL 1577, eachoptocoupler is proof tested byapplying an insulation test voltage ≥6000 V rms for 1 second (leakagedetection current limit, I I-O≤ 5 µA).10. This test is performed before the100% Production test shown in theIEC/EN/DIN EN 60747-5-2 InsulationRelated Characteristics Table, ifapplicable.11. Pulse: f = 20 kHz, Duty Cycle = 10%.12. The internal 20 kΩ resistor can beused by shorting pins 6 and 7together.13. Due to tolerance of the internalresistor, and since propagation delayis dependent on the load resistorvalue, performance can be improvedby using an external 20 kΩ 1% loadresistor. For more information onhow propagation delay varies withload resistance, see Figure 8.14. The R L = 20 kΩ, C L = 100 pF loadrepresents a typical IPM (IntelligentPower Module) load.15. See Option 020 data sheet for moreinformation.16. Use of a 0.1 µF bypass capacitorconnected between pins 5 and 8 canimprove performance by filteringpower supply line noise.17. The difference between t PLH and t PHLbetween any two devices under thesame test condition. (See IPM DeadTime and Propagation DelaySpecifications section.)18. Common mode transient immunity ina Logic High level is the maximumtolerable dV CM/dt of the commonmode pulse, V CM, to assure that theoutput will remain in a Logic Highstate (i.e., V O > 3.0 V).19. Common mode transient immunity ina Logic Low level is the maximumtolerable dV CM/dt of the commonmode pulse, V CM, to assure that theoutput will remain in a Logic Lowstate (i.e.,V O<1.0V).20. Pulse Width Distortion (PWD) isdefined as |t PHL - t PLH| for any givendevice.*All typical values at 25°C, V CC = 15 V.†The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics Table (if applicable), your equipment level safety specification or Agilent Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage,” publication number 5963-2203E.Figure 4. HCPL-4506 and HCPL-0466Input Current vs. Forward Voltage.Figure 5. HCPL-J456 and HCNW4506Input Current vs. Forward Voltage.Figure 2. Normalized Output Current vs. Temperature.Figure 1. Typical Transfer Characteristics.Figure 3. High Level Output Current vs. Temperature.Figure 6. Propagation Delay Test Circuit.I O – O U T P U T C U R R E N T – m AI F – FORWARD LED CURRENT – mAN O R M A L I Z E D O U T P U T C U R R EN TT A – TEMPERATURE – °C I O H – H I G H L E V E L O U T P U T C U R R E N T– µAT A – TEMPERATURE – °CI F – F O R W A R D C U R R E N T – m AV F – FORWARD VOLTAGE – VOLTS I F – I N P U T F O RW A R D C U R R E N T – m AV F – INPUT FORWARD VOLTAGE – VHCPL-J456/HCNW4506= 15 VI *TOTAL LOAD CAPACITANCEt P – P R O P A G A T I O N D E L A Y – n sRL – LOAD RESISTANCE – k ΩFigure 8. Propagation Delay with External 20 k Ω RL vs. Temperature.Figure 9. Propagation Delay with Internal 20 k Ω RL vs. Temperature.Figure 10. Propagation Delay vs. Load Resistance.Figure 7. CMR Test Circuit. Typical CMR Waveform.Figure 13. Propagation Delay vs. Input Current.Figure 11. Propagation Delay vs. Load Capacitance.Figure 12. Propagation Delay vs.Supply Voltage.CC = 15 VV FFV OV OSWITCH AT A: I F = 0 mA SWITCH AT B: I F = 10 mAV CCV OLt P – P R O P A G A T I O N D E L A Y – n sT A – TEMPERATURE – °C tP – P R O P A G A T I O N D E L A Y – n sCL – LOAD CAPACITANCE – pFt P – P R O P A G A T I O N D E L A Y – n sV CC – SUPPLY VOLTAGE – Vt P – P R O P A G A T I O N D E L A Y – n sI F – FORWARD LED CURRENT – mAt P – P R O P A G A T I O N D E L A Y – n sT A – TEMPERATURE – °CFigure 16. Optocoupler Input to Output Capacitance Model for Unshielded Optocouplers.Figure 15. Recommended LED Drive Circuit.Figure 14. Thermal Derating Curve, Dependence of Safety Limiting Value with Case Temperature per IEC/EN/DIN EN 60747-5-2.Figure 18. LED Drive Circuit with Resistor Connected to LED Anode (Not Recommended).Figure 17. Optocoupler Input to Output Capacitance Model for Shielded Optocouplers.CC = 15 VCC = 15 VO U T P U T P O W E R – P S , I N P U T C U R R E N T – I S0T S – CASE TEMPERATURE – °C 400600800200100300500700(230)O U T P U T P O W E R – P S , I N P U T C U R R E N T – I ST S – CASE TEMPERATURE – °CFigure 23. Recommended LED Drive Circuit for Ultra High CMR.Figure 20. AC Equivalent Circuit for Figure 15 During Common Mode Transients.Figure 19. AC Equivalent Circuit for Figure 18 During Common Mode Transients.Figure 21. Not Recommended Open Collector LED Drive Circuit.Figure 22. AC Equivalent Circuit for Figure 21 During Common Mode Transients.CMCMCMFigure 24. Typical Application Circuit.Figure 26. Waveforms for Dead Time Calculation.Figure 25. Minimum LED Skew for Zero Dead Time.V V I (t PLH-t PHL ) MAX. = t PLH MAX. - t PHL MIN.I *PDD = PROPAGATION DELAY DIFFERENCENOTE: THE PROPAGATION DELAYS USED TO CALCULATE PDD ARE TAKEN AT EQUAL TEMPERATURES.V V I MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER)= (t PLH MAX. - t PLH MIN.) + (t PHL MAX. - t PHL MIN.) = (t PLH MAX. - t PHL MIN.) - (t PLH MIN. - t PHL MAX.) = PDD* MAX. - PDD* MIN.I *PDD = PROPAGATION DELAY DIFFERENCENOTE: THE PROPAGATION DELAYS USED TO CALCULATE THE MAXIMUM DEAD TIME ARE TAKEN AT EQUAL TEMPERATURES.LED Drive Circuit Considerations for Ultra High CMR Performance Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupl-ing from the input side of the optocoupler, through the package, to the detector ICas shown in Figure 16. The HCPL-4506 series improveCMR performance by using a detector IC with an optically transparent Faraday shield, which diverts the capacitively coupled current away from the sensitive IC circuitry. However, this shield does not eliminate the capacitive coupling between the LED and the optocoupler output pins and output ground as shown in Figure 17. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failuresfor a shielded optocoupler. The main design objective of a high CMR LED drive circuit becomes keeping the LED in the proper state (on or off) during common mode transients. For example, the recommended application circuit (Figure 15), can achieve 15kV/µs CMR while minimizing component complexity. Note that a CMOS gate is recommendedin Figure 15 to keep the LEDoff when the gate is in the high state.Another cause of CMR failure for a shielded optocoupler is direct coupling to the optocoupler output pins through C LEDO1 and C LEDO2 in Figure 17. Many factors influence the effect and magni-tude of the direct coupling including: the use of an internal or external output pull-up resistor, the position of the LED current setting resistor, the connection of the unused inputpackage pins, and the value of thecapacitor at the optocoupleroutput (C L).Techniques to keep the LED inthe proper state and minimize theeffect of the direct coupling arediscussed in the next twosections.CMR with the LED On(CMR L)A high CMR LED drive circuitmust keep the LED on duringcommon mode transients. This isachieved by overdriving the LEDcurrent beyond the inputthreshold so that it is not pulledbelow the threshold during atransient. The recommendedminimum LED current of 10mAprovides adequate margin overthe maximum I TH of 5.0mA (seeFigure 1) to achieve 15kV/µsCMR. Capacitive coupling ishigher when the internal loadresistor is used (due to C LEDO2)and an I F = 16mA is required toobtain 10kV/µs CMR.The placement of the LED currentsetting resistor effects the abilityof the drive circuit to keep theLED on during transients andinteracts with the direct couplingto the optocoupler output. Forexample, the LED resistor inFigure 18 is connected to theanode. Figure 19 shows the ACequivalent circuit for Figure 18during common mode transients.During a +dVcm/dt in Figure 19,the current available at the LEDanode (Itotal) is limited by theseries resistor. The LED current(I F) is reduced from its DC valueby an amount equal to the currentthat flows through C LEDP andC LEDO1. The situation is madeworse because the currentthrough C LEDO1 has the effect oftrying to pull the output high(toward a CMR failure) at thesame time the LED current isbeing reduced. For this reason,the recommended LED drivecircuit (Figure 15) places thecurrent setting resistor in serieswith the LED cathode. Figure 20is the AC equivalent circuit forFigure 15 during common modetransients. In this case, the LEDcurrent is not reduced during a+dVcm/dt transient because thecurrent flowing through thepackage capacitance is suppliedby the power supply. During a-dVcm/dt transient, however, theLED current is reduced by theamount of current flowingthrough C LEDN. But, better CMRperformance is achieved since thecurrent flowing in C LEDO1 during anegative transient acts to keep theoutput low.Coupling to the LED and outputpins is also affected by the con-nection of pins 1 and 4. If CMR islimited by perturbations in theLED on current, as it is for therecommended drive circuit(Figure 15), pins 1 and 4 shouldbe connected to the input circuitcommon. However, if CMRperformance is limited by directcoupling to the output when theLED is off, pins 1 and 4 should beleft unconnected.CMR with the LED Off(CMR H)A high CMR LED drive circuitmust keep the LED off(V F≤V F(OFF)) during commonmode transients. For example,during a +dVcm/dt transient inFigure 20, the current flowingthrough C LEDN is supplied by theparallel combination of the LEDand series resistor. As long as thevoltage developed across theresistor is less than V F(OFF) theLED will remain off and no common mode failure will occur. Even if the LED momentarily turns on, the 100 pF capacitor from pins 6-5 will keep the output from dipping below the threshold. The recommended LED drive circuit (Figure 15) provides about 10V of margin between the lowest optocoupler output voltage and a 3V IPM threshold duringa 15kV/µs transient withV CM=1500V. Additional margin can be obtained by adding a diode in parallel with the resistor, as shown by the dashed line con-nection in Figure 20, to clamp the voltage across the LED below V F(OFF).Since the open collector drive circuit, shown in Figure 21, cannot keep the LED off duringa +dVcm/dt transient, it isnot desirable for applications requiring ultra high CMR H performance. Figure 22 is the AC equivalent circuit for Figure 21 during common mode transients. Essentially all the current flowing through C LEDN during a +dVcm/dt transient must be supplied bythe LED. CMR H failures can occur at dV/dt rates where the current through the LED and C LEDN exceeds the input threshold. Figure 23 is an alternative drive circuit which does achieve ultra high CMR performance by shunting the LED in the off state.IPM Dead Time andPropagation DelaySpecificationsThe HCPL-4506 series includea Propagation Delay Differencespecification intended to helpdesigners minimize “dead time”in their power inverter designs.Dead time is the time periodduring which both the high andlow side power transistors (Q1and Q2 in Figure 24) are off. Anyoverlap in Q1 and Q2 conductionwill result in large currents flow-ing through the power devicesbetween the high and low voltagemotor rails.To minimize dead time thedesigner must consider the propa-gation delay characteristics of theoptocoupler as well as the charac-teristics of the IPM IGBT gatedrive circuit. Considering only thedelay characteristics of the opto-coupler (the characteristics of theIPM IGBT gate drive circuit canbe analyzed in the same way) it isimportant to know the minimumand maximum turn-on (t PHL) andturn-off (t PLH) propagation delayspecifications, preferably over thedesired operating temperaturerange.The limiting case of zero deadtime occurs when the input to Q1turns off at the same time that theinput to Q2 turns on. This casedetermines the minimum delaybetween LED1 turn-off and LED2turn-on, which is related to theworst case optocoupler propaga-tion delay waveforms, as shown inFigure 25. A minimum dead timeof zero is achieved in Figure 25when the signal to turn on LED2is delayed by (t PLH max - t PHL min)from the LED1 turn off. Note thatthe propagation delays used tocalculate PDD are taken at equaltemperatures since the opto-couplers under considerationare typically mounted in closeproximity to each other.(Specifically, t PLH max and t PHL minin the previous equation are notthe same as the t PLH max andt PHL min, over the full operatingtemperature range, specified inthe data sheet.) This delay is themaximum value for the propaga-tion delay difference specificationwhich is specified at 450ns forthe HCPL-4506 series over anoperating temperature range of-40°C to 100°C.Delaying the LED signal by themaximum propagation delay dif-ference ensures that the minimumdead time is zero, but it does nottell a designer what the maximumdead time will be. The maximumdead time occurs in the highlyunlikely case where one opto-coupler with the fastest t PLH andanother with the slowest t PHLare in the same inverter leg. Themaximum dead time in this casebecomes the sum of the spreadin the t PLH and t PHL propagationdelays as shown in Figure 26.The maximum dead time is alsoequivalent to the differencebetween the maximum and mini-mum propagation delay differencespecifications. The maximumdead time (due to the optocoup-lers) for the HCPL-4506 seriesis 600ns (= 450ns -(-150ns) )over an operating temperaturerange of -40°C to 100°C.。

XN04604资料

Parameter Tr1 Collector-base voltage (Emitter open) Collector-emitter voltage (Base open) Emitter-base voltage (Collector open) Collector current Peak collector current Tr2 Collector-base voltage (Emitter open) Collector-emitter voltage (Base open) Emitter-base voltage (Collector open) Collector current Peak collector current Overall Total power dissipation Junction temperature Storage temperature Symbol VCBO VCEO VEBO IC ICP VCBO VCEO VEBO IC ICP PT Tj Tstg Rating 25 20 12 0.5 1 −15 −10 −7 − 0.5 −1 300 150 −55 to +150 Unit V V V A A V
0.4±0.2
5˚
1
XN04604
■ Electrical Characteristics Ta = 25°C ± 3°C
• Tr1
Parameter Collector-base voltage (Emitter open) Collector-emitter voltage (Base open) Emitter-base voltage (Collector open) Collector-base cutoff current (Emitter open) Forward current transfer ratio *1 Collector-emitter saturation voltage *1 Base-emitter saturation voltage Transition frequency Collector output capacitance (Common base, input open circuited) ON resistance *2

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*1
(Ta=25˚C)
Symbol VCEO ICBO IEBO hFE VCE(sat) VBE fT Cob Ron*1
1kΩ
Conditions IC = 1mA, IB = 0 VCB = 50V, IE = 0 VEB = 25V, IC = 0 VCE = 2V, IC = 4mA IC = 30mA, IB = 3mA VCE = 2V, IC = 4mA VCB = 6V, IE = –4mA, f = 200MHz VCB = 10V, IE = 0, f = 1MHz
min 20
typ
0 to 0.05
0.1 to 0.3
0.8
max
0.16–0.06
+0.2
s Basic Part Number of Element
+0.1
1.45±0.1
s Features
0.5 –0.05
+0.1
+0.1
Unit V µA µA
0.1 0.1 500 2500 0.1 0.6 80 7 1.0
Marking Symbol: EN Internal Connection
6 5 4 Tr1 1 2 3
Tr2
s Electrical Characteristics
Parameter Collector to emitter voltage Collector cutoff current Emitter cutoff current Forward current transfer ratio Collector to emitter saturation voltage Base to emitter voltage Transition frequency Collector output capacitance ON Resistance
Collector current IC (mA)
Emitter current IE (mA)
Cob — VCB
20
Collector output capacitance Cob (pF)
f=1MHz Ta=25˚C
16
12
8
4
0 1 10 100
Collector to base voltage VCB (V)
1.9±0.1
+0.2
5
2
0.95
4
3
q
2SD1915(F) × 2 elements
1.1–0.1
0.4±0.2
s Absolute Maximum Ratings
Parameter Collector to base voltage Rating Collector to emitter voltage of Emitter to base voltage element Collector current Peak collector current Total power dissipation Overall Junction temperature Storage temperature Symbol VCBO VCEO VEBO IC ICP PT Tj Tstg
(Ta=25˚C)
Ratings 50 20 25 300 500 300 150 –55 to +150 Unit V V V mA mA mW ˚C ˚C
1 : Collector (Tr1) 2 : Base (Tr2) 3 : Emitter (Tr2)
4 : Collector (Tr2) 5 : Base (Tr1) 6 : Emitter (Tr1) EIAJ : SC–74 Mini Type Package (6–pin)
2
V V MHz pF Ω
Ron test circuit
IB=1mA f=1kHz V=0.3V
VB
VV
VA
Ron=
VB !1000(Ω) VA–VB
1
元器件交易网
Composite Transistors
PT — Ta
500
XN4506
IC — VCE
24 Ta=25˚C
VCE(sat) — IC
10
hFE — IC
IC/IB=10 2000 VCE=2V
fT — I E
200 VCB=6V Ta=25˚C
Collector to emitter saturation voltage VCE(sat) (V)
Forward current transfer ratio hFE
120 VCE=2V 100 25˚C
IC — VBE
Total power dissipation PT (mW)
Collector current IC (mA)
IB=10µA 16 8µA 12
Collector current IC (mA)
400
20
80
Ta=75˚C
300
–25˚C 60
+0.2 +0.25
1.5 –0.05
0.65±0.15 1
0.3 –0.05
2.9 –0.05
q q
Two elements incorporated into one package. Reduction of the mounting area and assembly cost by one half.
Transition frequency fT (MHz)
1600 25˚C 1200 –25˚C 800
1
Ta=75˚C
160
120
0.1 Ta=75˚C 25˚C 0.01 –25˚C
80
400
40
0.001 0.1
1
10
100
0 0.1
1
10
100
0 –0.1
–1
–10
–100
Collector current IC (mA)
6µA 4µA
200
8
40
100
4
2µA
20
0 0 40 80 120 160
0 0 2 4 6 8 10 12
0 0 0.2 0.4 0.6 0.8 1.0
Ambient temperature Ta (˚C)
Collector to emitter voltage VCE (V)
Base to emitter voltage VBE (V)
元器件交易网
Composite Transistors
XN4506
NPN epitaxial planer transistor
Unit: mm
For amplification of low frequency output
0.65±0.15 6 0.95
2.8 –0.3