FPGA可编程逻辑器件芯片EPM7032STI44-7中文规格书

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in the Stratix II GX Architecture chapter in volume 1 of the Stratix II GX Device Handbook.
Table 4–47. 1.8-V HSTL Class I and II Differential Specifications
VCCIO VREF VTT VIH (DC) VIL (DC) VIH (AC) VIL (AC) VOH VOL
Output supply voltage Input reference voltage Termination voltage DC high-level input voltage DC low-level input voltage AC high-level input voltage AC low-level input voltage High-level output voltage Low-level output voltage
VOX (AC) AC differential cross point voltage
Conditions
Minimum
1.71 0.2 0.78
0.4 0.68
Typical
1.80
Maximum Unit
1.89
V
V
1.12
V
V
0.9
V
Stratix II GX Device Handbook, Volume 1
1 1
1
1 1 1-2 1 1
1 1 1
1
1
Receiver Phase Comp FIFO
1-2
2-3
Receiver Sum
PIPE
(2)
- 14-17 1 21-25
2-3
1 13-16
1-2
- 19-23
1-2
- 10-12
1-2
-
7-9
1-2
-
6-7
1-2
-
6-7
1
-
8-9
1-2
-
8-10
Symbol
Parameter
VCCIO
I/O supply voltage
VDIF (DC) DC input differential voltage
VCM (DC) DC common mode input voltage
VDIF (AC) AC differential input voltage
VREF – 0.1 V V
VREF – 0.2 V V
0.4
V
Note to Table 4–46: (1) This specification is supported across all the programmable drive settings available for this I/O standard as shown
8B/10B Decoder
Receiver Byte
State
De-
Machine serializer
XAUI
2-2.5 2-2.5 5.5-6.5 0.5
1
1
×1, ×4, ×8 4-5
-
11-13
1
-
1
8-bit
channel
width
PIPE
×1, ×4, ×8 2-2.5 - 5.5-6.5 0.5
> 0.37
> 0.37
> 0.37
UI
Combined Deterministic and Random Jitter Tolerance (peak-to-peak)
Data Rate = 1.25, 2.5, 3.125 Gbps REFCLK = 125 MHz Pattern = CJPAT Equalizer Setting = 0 for 1.25 Gbps Equalizer Setting = 6 for 2.5 Gbps Equalizer Setting = 6 for 3.125 Gbps
Symbol/ Description
Conditions
-3 Speed Commercial Speed
Grade
-4 Speed Commercial and Industrial Speed
Grade
-5 Speed Commercial Speed
Grade
Unit
Min Typ Max Min Typ Max Min Typ Max
Conditions
IOH = 16 mA (1) IOH = –16 mA (1)
Minimum
1.71 0.85 0.85 VREF + 0.1 –0.3 VREF + 0.2
VCCIO – 0.4
Typical
1.80 0.90 0.90
Maximum Unit
1.89
V
0.95
V
0.95
V
V
-
1
16-bit
channel
width
GIGE
4-5
-
11-13
1
-
1
OC-12
6-7
-
-
1
-
1
SONET/ SDH
OC-48
3-3.5
-
-
0.5
-
1
OC-96 2-2.5 -
-
0.5
-
1
(OIF) CEI PHY
2.5
-
-
0.5
-
1
CPRI 614 Mbps, 4-5
-
-
1
-
1
(4)
1.228 Gbps
> 0.55
> 0.55
> 0.55
UI
Stratix II GX Device Handbook, Volume 1
DC and Switching Characteristics
Table 4–46. 1.8-V HSTL Class II Specifications
Symbol
Parameter
2.456 Gbps 4-5
-
-
1ห้องสมุดไป่ตู้
-
1
Serial 1.25 Gbps, 2-2.5 -
-
0.5
-
1
RapidIO 2.5 Gbps,
3.125 Gbps
SDI
HD
5
-
-
1
-
1
10-bit
channel
width
HD, 3G 2.5
-
-
0.5
-
1
20-bit
channel
width
Byte Order
1-2
-
6-7
1-2
-
9-10
1-2
-
6-7
Stratix II GX Device Handbook, Volume 1
DC and Switching Characteristics
Table 4–19. Stratix II GX Transceiver Block AC Specification Notes (1), (2), (3) (Part 6 of 19)
DC and Switching Characteristics
Table 4–22. PCS Latency (Part 1 of 3) Note (1)
Functional Mode
Configuration
Word Aligner
Deskew FIFO
Rate Matcher
(3)
Receiver PCS Latency
Serial RapidIO Receiver Jitter Tolerance (11)
Deterministic Jitter Tolerance (peak-to-peak)
Data Rate = 1.25, 2.5, 3.125 Gbps REFCLK = 125 MHz Pattern = CJPAT Equalizer Setting = 0 for 1.25 Gbps Equalizer Setting = 6 for 2.5 Gbps Equalizer Setting = 6 for 3.125 Gbps
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