SIMULTANEOUS REWRITE CONTROL SYSTEM FOR CACHE MEMO
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专利名称：SIMULTANEOUS REWRITE CONTROL SYSTEM FOR CACHE MEMORY
发明人：KITAHARA TAKESHI
申请号：JP21051090
申请日：19900810
公开号：JPH0498338A
公开日：
19920331
专利内容由知识产权出版社提供
摘要：PURPOSE:To make the maximum use of high speed being the merit of a copy-back system so as to improve the performance of a whole system by updating internal entries concerned without waiting for the end of a write-once-operation and answering to corresponding CPU. CONSTITUTION:When write requests for the same blocks in two cache memories (M1 and M2) are simultaneously generated, and the writing of data into the cache memory M1 is faster than the other cache memory M2 by accident, the cache memory M1 executes a firsts means P1 and a fifth means P5 (processing), and the cache memory M2 executes second, third and fourth means P2, P3 and P4 (processings). Thus, the cache memories M1 and M2 update the internal entries concerned without waiting for the end of the write-once-operation and an answer to corresponding CPU C1 and C2 ca be made. Thus, the high speed processing can be made the maximum use of and the performance of the whole system can be improved.
申请人：FUJITSU LTD
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