AA8632中文资料

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SGM8631中文资料

SGM8631 SGM8632 SGM8633 SGM8634470µA, 6MHz, Rail-to-Rail I/O CMOS Operational AmplifierShengbang Microelectronics Co, Ltd REV . BELECTRICAL CHARACTERISTICS :V S = +5V (At T A = +25℃,V CM = Vs/2,R L = 600Ω, unless otherwise noted)Specifications subject to change without notice.PACKAGE/ORDERING INFORMATIONMODEL ORDERNUMBER PACKAGEDESCRIPTION PACKAGEOPTIONMARKINGINFORMATIONSGM8631XC5/TR SC70-5 Tape and Reel, 3000 8631SGM8631XN5/TR SOT23-5 Tape and Reel, 3000 8631 SGM8631SGM8631XS/TR SO-8 Tape and Reel, 2500SGM8631XSSGM8632XMS/TR MSOP-8 Tape and Reel, 3000 SGM8632XMS SGM8632SGM8632XS/TR SO-8 Tape and Reel, 2500 SGM8632XSSGM8633XN6/TR SOT23-6 Tape and Reel, 3000 8633 SGM8633SGM8633XS/TR SO-8 Tape and Reel, 2500 SGM8633XSSGM8634XS/TR SO-16 Tape and Reel, 2500 SGM8634XS SGM8634SGM8634XTS TSSOP-16 Tape and Reel, 3000 SGM8634XTSABSOLUTE MAXIMUM RATINGS Supply Voltage, V+ to V- ............................................ 7.5 V Common-Mode Input Voltage.................................... (–V S) – 0.5 V to (+V S) +0.5V Storage Temperature Range..................... –65℃ to +150℃Junction Temperature.................................................160℃Operating Temperature Range.................–55℃ to +150℃Package Thermal Resistance @ T A = 25℃SC70-5, θJA................................................................ 333/W℃SOT23-5, θJA.............................................................. 190/W℃SOT23-6, θJA.............................................................. 190/W℃SO-8, θJA......................................................................125/W℃MSOP-8, θJA.............................................................. 216/W℃SO-16, θJA..................................................................... 82/W℃TSSOP-16, θJA............................................................ 105/W℃Lead Temperature Range (Soldering 10 sec).....................................................260℃ESD Susceptibility HBM.. (1500V)MM (400V)NOTES1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTIONThis integrated circuit can be damaged by ESD. Shengbang Micro-electronics recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.TYPICAL PERFORMANCE CHARACTERISTICSAt T A = +25℃,V CM = Vs/2, R L = 600Ω, unless otherwise noted.Positive Overload Recovery Negative Overload RecoveryTime(2µs/div) Time(500ns/div)Large-Signal Step Response Small-Signal Step ResponseTime(1µs/div) Time(1µs/div)0V 0VVs = ±2.5V V IN = 50mV R L = 10K Ω G = 1002.5V -50mV 0V 0V2.5V-50mVVs = ±2.5V V IN = 50mV R L = 10K Ω G = 100Vs = 5VG = +1 C L = 100pF R L = 10K ΩVs = 5V G = +1 C L = 100pF R L = 10K ΩV o l t a g e (1V /d i v )V o l t a g e (50m V /d i v )TYPICAL PERFORMANCE CHARACTERISTICS At T A = +25℃,V CM = Vs/2, R L = 600Ω, unless otherwise noted.TYPICAL PERFORMANCE CHARACTERISTICS At T A = +25℃,V CM = Vs/2, R L = 600Ω, unless otherwise noted.TYPICAL PERFORMANCE CHARACTERISTICSAt T A = +25℃,V CM = Vs/2, R L = 600Ω, unless otherwise noted.Large-Signal Step Response Small-Signal Step ResponseTime(1µs/div) Time(1µs/div)Vs=2.7VG=+1C L=100pFR L=10KΩVs=2.7VG=+1C L=100pFR L=10KΩVoltage(5mV/div)Voltage(5mV/div)TYPICAL PERFORMANCE CHARACTERISTICS At T A = +25℃,V CM = Vs/2, R L = 600Ω, unless otherwise noted.APPLICATION NOTESDriving Capacitive LoadsThe SGM863x can directly drive 1000pF in unity-gain without oscillation. The unity-gain follower (buffer) is the most sensitive configuration to capacitive loading. Direct capacitive loading reduces the phase margin of amplifiers and this results in ringing or even oscillation. Applications that require greater capacitive drive capability should use an isolation resistor between the output and the capacitive load like the circuit in Figure 1. The isolation resistor R ISO and the load capacitor C L form a zero to increase stability. The bigger the R ISO resistor value, the more stable V OUT will be. Note that this method results in a loss of gain accuracy because R ISO forms a voltage divider with the R LOAD.V IN V OUTFigure 1. Indirectly Driving Heavy Capacitive LoadAn improvement circuit is shown in Figure 2. It provides DC accuracy as well as AC stability. R F provides the DC accuracy by connecting the inverting signal with the output. C F and R Iso serve to counteract the loss of phase margin by feeding the high frequency component of the output signal back to the amplifier’s inverting input, thereby preserving phase margin in the overall feedback loop.V IN V OUTFigure 2. Indirectly Driving Heavy Capacitive Load with DC AccuracyFor no-buffer configuration, there are two others ways to increase the phase margin: (a) by increasing the amplifier’s gain or (b) by placing a capacitor in parallel with the feedback resistor to counteract the parasitic capacitance associated with inverting node. Power-Supply Bypassing and Layout The SGM863x family operates from either a single +2.5V to +5.5V supply or dual ±1.25V to ±2.75V supplies. For single-supply operation, bypass the power supply V DD with a 0.1µF ceramic capacitor which should be placed close to the V DD pin. For dual-supply operation, both the V DD and the V SS supplies should be bypassed to ground with separate 0.1µF ceramic capacitors. 2.2µF tantalum capacitor can be added for better performance.Good PC board layout techniques optimize performance by decreasing the amount of stray capacitance at the op amp’s inputs and output. To decrease stray capacitance, minimize trace lengths and widths by placing external components as close to the device as possible. Use surface-mount components whenever possible.For the operational amplifier, soldering the part to the board directly is strongly recommended. Try to keep the high frequency big current loop area small to minimize the EMI (electromagnetic interfacing).VnVpV SSVnV SS(GND)Figure 3. Amplifier with Bypass Capacitors GroundingA ground plane layer is important for SGM863x circuit design. The length of the current path speed currents in an inductive ground return will create an unwanted voltage noise. Broad ground plane areas will reduce the parasitic inductance.Input-to-Output CouplingTo minimize capacitive coupling, the input and output signal traces should not be parallel. This helps reduce unwanted positive feedback.Typical Application CircuitsDifferential AmplifierThe circuit shown in Figure 4 performs the difference function. If the resistors ratios are equal ( R4 / R3 = R2 / R1 ), then V OUT = ( Vp – Vn ) × R 2 / R 1 + Vref.Vn VpOUTFigure 4. Differential AmplifierInstrumentation AmplifierThe circuit in Figure 5 performs the same function as that in Figure 4 but with the high input impedance.VnVpV OUTFigure 5. Instrumentation AmplifierLow Pass Active FilterThe low pass filter shown in Figure 6 has a DC gain of (-R 2/R 1) and the –3dB corner frequency is 1/2πR 2C. Make sure the filter is within the bandwidth of the amplifier. The Large values of feedback resistors can couple with parasitic capacitance and cause undesired effects such as ringing or oscillation inhigh-speed amplifiers. Keep resistors value as low as possible and consistent with output loading consideration.V INV OUTFigure 6. Low Pass Active FilterSC70-5SOT23-5SOT23-6SO-8MSOP-8SO-16TSSOP-16REVISION HISTORYLocation Page 11/06— Data Sheet changed from REV.A to REV.BAdded SC70-5 PACKAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . Universal Changes to PRODUCT DESCRIPTION, FEATURES, and PIN CONFIGURATIONS . . . . . . . . . . .. . . . . . . . . . . . .. . 1 Updated PACKAGE/ORDERING INFORMATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. .3 Changes to ABSOLUTE MAXIMUM ATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 3Shengbang Microelectronics Co, LtdUnit 3, ChuangYe PlazaNo.5, TaiHu Northern Street, YingBin Road Centralized Industrial ParkHarbin Development Zone150078HeiLongJiangHarbin,ChinaP.R.Tel.: 86-451-84348461Fax: 86-451-84308461。

ET80960JA3V252中文资料

80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit MicroprocessorDatasheetProduct Featuress Code Compatible with all 80960Jx ProcessorssHigh-Performance Embedded Architecture —One Instruction/Clock Execution —Core Clock Rate is:1x the Bus Clock for 80960JA/JF/JS 2x the Bus Clock for 80960JD/JC 3x the Bus Clock for 80960JT —Load/Store Programming Model —Sixteen 32-Bit Global Registers—Sixteen 32-Bit Local Registers (8 sets)—Nine Addressing Modes—User/Supervisor Protection Model sTwo-Way Set Associative Instruction Cache—80960JA - 2Kbyte —80960JF/JD - 4Kbyte —80960JS/JC/JT - 16Kbyte —Programmable Cache-Locking MechanismsDirect Mapped Data Cache —80960JA - 1Kbyte —80960JF/JD - 2Kbyte —80960JS/JC/JT - 4Kbyte —Write Through Operation sOn-Chip Stack Frame Cache—Seven Register Sets May Be Saved —Automatic Allocation on Call/Return —0-7 Frames Reserved for High-Priority InterruptssOn-Chip Data RAM—1Kbyte Critical Variable Storage —Single-Cycle Access s3.3V Supply Voltage —5V Tolerant Inputs—TTL Compatible Outputs sHigh Bandwidth Burst Bus—32-Bit Multiplexed Address/Data—Programmable Memory Configuration —Selectable 8-, 16-, 32-Bit Bus Widths —Supports Unaligned Accesses—Big or Little Endian Byte Ordering sHigh-Speed Interrupt Controller —31 Programmable Priorities —Eight Maskable Pins plus NMI#—Up to 240 Vectors in Expanded Mode sTwo On-Chip Timers—Independent 32-Bit Counting —Clock Prescaling by 1, 2, 4 or 8—Internal Interrupt Sources s Halt Mode for Low Powers IEEE 1149.1 (JTAG) Boundary Scan Compatibility sPackages—132-Lead Pin Grid Array (PGA)—132-Lead Plastic Quad Flat Pack (PQFP)—196-Ball Mini Plastic Ball Grid Array (MPBGA)Order Number: 273159-006August 2004INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.Intel may make changes to specifications and product descriptions at any time, without notice.Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.The 80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling1-800-548-4725 or by visiting Intel’s website at .AlertVIEW, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, CT Connect, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, i386, i486, i960, iCOMP, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Create & Share, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel Play, Intel Play logo, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel Xeon, Intel XScale, IPLink, Itanium, LANDesk, LanRover, MCS, MMX, MMX logo, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, PDCharm, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, RemoteExpress, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside., The Journey Inside, TokenExpress, Trillium, VoiceBrick, Vtune, and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.*Other names and brands may be claimed as the property of others.Copyright © Intel Corporation, 2002, 2004Contents Contents1.0Introduction (7)2.080960Jx Overview (9)2.180960 Processor Core (10)2.2Burst Bus (11)2.3Timer Unit (11)2.4Priority Interrupt Controller (11)2.5Instruction Set Summary (12)2.6Faults and Debugging (12)2.7Low Power Operation (12)2.8Test Features (12)2.9Memory-Mapped Control Registers (13)2.10Data Types and Memory Addressing Modes (13)3.0Packaging Information (15)3.1Available Processors and Packages (15)3.2Pin Descriptions (16)3.2.1Functional Pin Definitions (16)3.2.280960Jx 132-Lead PGA Pinout (23)3.2.380960Jx 132-Lead PQFP Pinout (27)3.2.480960Jx 196-Ball MPBGA Pinout (30)4.0Electrical Specifications (35)4.1Absolute Maximum Ratings (35)4.2Operating Conditions (35)4.3Connection Recommendations (36)4.4VCC5 Pin Requirements (VDIFF) (36)4.5VCCPLL Pin Requirements (37)4.6 D.C. Specifications (38)4.7 A.C. Specifications (42)4.7.1 A.C. Test Conditions and Derating Curves (45)4.7.1.1Output Delay or Hold vs. Load Capacitance (46)4.7.1.2T LX vs. AD Bus Load Capacitance (47)4.7.1.3ICC Active vs. Frequency (49)4.7.2 A.C. Timing Waveforms (53)5.0Device Identification (59)5.180960JS/JC/JT Device Identification Register (60)5.280960JD Device Identification Register (61)5.380960JA/JF Device Identification Register (62)6.0Thermal Specifications (63)6.1Thermal Management Accessories (68)6.1.1Heatsinks (68)7.0Bus Functional Waveforms (69)7.1Basic Bus States (79)7.2Boundary-Scan Register (80)ContentsFigures180960Jx Microprocessor Package Options (7)280960Jx Block Diagram (10)3132-Lead Pin Grid Array Top View-Pins Facing Down (23)4132-Lead Pin Grid Array Bottom View-Pins Facing Up (24)5132-Lead PQFP - Top View (27)6196-Ball Mini Plastic Ball Grid Array Top View-Balls Facing Down (30)7196-Ball Mini Plastic Ball Grid Array Bottom View-Balls Facing Up (31)8VCC5 Current-Limiting Resistor (36)9VCCPLL Lowpass Filter (37)10 A.C. Test Load (45)11Output Delay or Hold vs. Load Capacitance–80960JS/JC/JT (3.3 V Signals) (46)12Output Delay or Hold vs. Load Capacitance–80960JS/JC/JT (5V Signals) (46)13Output Delay or Hold vs. Load Capacitance–80960JA/JF/JD (47)14T LX vs. AD Bus Load Capacitance–80960JS/JC/JT (3.3V Signals) (47)15T LX vs. AD Bus Load Capacitance–80960JS/JC/JT (5V Signals) (48)16T LX vs. AD Bus Load Capacitance–80960JA/JF/JD (48)17I CC Active (Power Supply) vs. Frequency–80960JA/JF (49)1880960JA/JF I CC Active (Thermal) vs. Frequency (49)1980960JD I CC Active (Power Supply) vs. Frequency (50)2080960JD I CC Active (Thermal) vs. Frequency (50)2180960JC I CC Active (Power Supply) vs. Frequency (51)2280960JC I CC Active (Thermal) vs. Frequency (51)2380960JS I CC Active (Power Supply) vs. Frequency (52)2480960JS I CC Active (Thermal) vs. Frequency (52)25CLKIN Waveform (53)26T OV1 Output Delay Waveform (53)27T OF Output Float Waveform (54)28T IS1 and T IH1 Input Setup and Hold Waveform (54)29T IS2 and T IH2 Input Setup and Hold Waveform (54)30T IS3 and T IH3 Input Setup and Hold Waveform (55)31T IS4 and T IH4 Input Setup and Hold Waveform (55)32T LX, T LXL and T LXA Relative Timings Waveform (56)33DT/R# and DEN# Timings Waveform (56)34TCK Waveform (57)35T BSIS1 and T BSIH1 Input Setup and Hold Waveforms (57)36T BSOV1 and T BSOF1 Output Delay and Output Float Waveform (57)37T BSOV2 and T BSOF2 Output Delay and Output Float Waveform (58)38T BSIS2 and T BSIH2 Input Setup and Hold Waveform (58)3980960JS/JC/JT Device Identification Register Fields (60)4080960JD Device Identification Register Fields (61)4180960JA/JF Device Identification Register Fields (62)42Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus (69)43Burst Read and Write Transactions Without Wait States, 32-Bit Bus (70)44Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus (71)45Burst Read and Write Transactions Without Wait States, 8-Bit Bus (72)46Burst Read and Write Transactions With 1, 0 Wait Statesand Extra Tr State on Read, 16-Bit Bus (73)47Double Word Read Bus Request, Misaligned One Byte FromQuad Word Boundary, 32-Bit Bus, Little Endian (74)Contents 48HOLD/HOLDA Waveform For Bus Arbitration (75)49Cold Reset Waveform (76)50Warm Reset Waveform (77)51Entering the ONCE State (78)52Bus States with Arbitration (80)53Summary of Aligned and Unaligned Accesses (32-Bit Bus) (84)54Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued) (85)Tables180960Jx 3.3-V Microprocessor Family (7)280960Jx Instruction Set (14)380960Jx Processors Available in 132-Pin PGA Package (15)480960Jx Processors Available in 132-Pin PQFP Package (15)580960Jx Processors Available in Extended Temperature (16)680960Jx Processors Available in 196-Ball MPBGA Package (16)7Pin Description Nomenclature (17)8Pin Description—External Bus Signals (18)9Pin Description—Processor Control Signals, Test Signals, and Power (21)10Pin Description—Interrupt Unit Signals (22)11132-Lead PGA Pinout—In Signal Order (25)12132-Lead PGA Pinout—In Pin Order (26)13132-Lead PQFP Pinout—In Signal Order (28)14132-Lead PQFP Pinout—In Pin Order (29)15196-Ball MPBGA Pinout—In Signal Order (32)16196-Ball MPBGA Pinout—In Pin Order (33)17Absolute Maximum Ratings (35)1880960Jx Operating Conditions (35)19VDIFF Parameters (37)2080960Jx D.C. Characteristics (38)2180960Jx I CC Characteristics (39)2280960Jx A.C. Characteristics (42)23Note Definitions for Table 22, 80960Jx AC Characteristics (45)2480960Jx Device Type and Stepping Reference (59)2580960JS/JC/JT Device ID Register Field Definitions (60)2680960JS/JC/JT Device ID Model Types (60)2780960JD Device ID Field Definitions (61)2880960JD Device ID Model Types (61)2980960JA/JF Device ID Field Definitions (62)3080960JA/JF Device ID Model Types (62)31Thermal Resistance for q CA and q JC Reference Table (63)32Maximum Ambient Temperature Reference Table (63)33132-Lead PGA Package Thermal Characteristics (64)3480960JA/JF/JD 196-Ball MPBGA Package Thermal Characteristics (64)3580960JS/JC/JT 196-Ball MPBGA Package Thermal Characteristics (65)36132-Lead PQFP Package Thermal Characteristics (65)37Maximum T A at Various Airflows in °C (80960JT) (66)38Maximum T A at Various Airflows in °C (80960JC) (66)39Maximum T A at Various Airflows in °C (80960JD) (67)40Maximum T A at Various Airflows in °C (80960JS) (67)41Maximum T A at Various Airflows in °C (80960JA/JF) (68)Contents42Boundary-Scan Register—Bit Order (81)43Natural Boundaries for Load and Store Accesses (81)44Summary of Byte Load and Store Accesses (82)45Summary of Short Word Load and Store Accesses (82)46Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4) (83)Revision HistoryDate Revision DescriptionSeptember 2002005Removed reference to A80960JF-16 from Table 3 on page15. Removed reference to NG80960JC-40, NG80960JC-33, NG80960JS-16,and NG80960JF-16 from Table 4 on page15.Removed reference to GD80960JC-40, GD80960JC-33, and 80960JS-16 in Table 6 on page16.Removed reference to 80960JC-40, 80960JC-33, 80960JS-16, and 80960JF-16 in Table 18 on page35.Removed reference to 80960JC-40, 80960JC-33, 80960JS-16, and 80960JF-16 from Table 21 on page39.Removed reference to 80960JC-40, 80960JC-33, 80960JS-16 and 80960JF-16 from Table 22 on page42.September 1999004Added new extended temp device offerings. See Table 5 on page16. Removed PGA package availability from JS/JC/JT processors. Changed AC timing parameter T OV1 (min) for extended temp devices only.See Table 22 on page42.June 1999003Merged the 80960JS/JC datasheet information into this datasheet (previously named 80960JA/JF/JD/JT 3.3V Embedded 32-Bit Microprocessor datasheet).Updated I CC values for the 80960JS/JC/JT processors. Increased TIH1 specification for the 80960JS/JC/JT processors. Updated MPBGA thermal specifications.December 1998002Corrected orientation of MPBGA package diagrams (Figure 6 on page30 and Figure 7 on page31).Added Figure 11 on page46,Figure 12 on page46,Figure 14 on page47, and Figure 15 on page48 to distinguish 80960JT 3.3-V and 5-V signal derating curves from the 80960JA/JF/JD derating curves.March 1998001This datasheet supersedes revisions to the following 80960Jx datasheets: #273109 (JT), #272971-002 (JD), and #276146-001 (JA/JF). In addition to combining the documents into one, the following content was changed: Figure 1 on page7: Added MPBGA package to diagram.Section 3.2.4, “80960Jx 196-Ball MPBGA Pinout” on page30: Added new Figures 6 and 7, Tables 10, 11 and 13.Figure 16 on page48: Added with the note that follows the figure.August 2004006To address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x".80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor1.0IntroductionThis document contains information for the 80960Jx microprocessors, including electrical characteristics and package pinout information. Detailed functional descriptions, other than parametric performance, are published in the i960® Jx Microprocessor Developer’s Manual(272483) and may be viewed online at /design/i960/Techinfo/80960JX/.Throughout this datasheet, references to ‘80960Jx’ indicate features that apply to the 3.3-V Jx processors only:Figure 1. 80960Jx Microprocessor Package Optionsi960®iM©19xxx80960JXXXXXXXXX SS132-Pin PQFPTable 1. 80960Jx 3.3-V Microprocessor FamilyProcessor Voltage Instruction Cache Data Cache Core Clock80960JA 3.3 V (5 V Tolerant) 2 Kbyte 1 Kbyte 1x 80960JF 3.3 V (5 V Tolerant) 4 Kbyte 2 Kbyte 1x 80960JD 3.3 V (5 V Tolerant) 4 Kbyte 2 Kbyte 2x 80960JS 3.3 V (5 V Tolerant)16 Kbyte 4 Kbyte 1x 80960JC 3.3 V (5 V Tolerant)16 Kbyte 4 Kbyte 2x 80960JT3.3 V (5 V Tolerant)16 Kbyte4 Kbyte3xNOTE: To address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x".This page intentionally left blank.80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor 2.080960Jx OverviewThe 80960Jx processor offers high performance to cost-sensitive 32-bit embedded applications.The 80960Jx is object code compatible with the 80960 core architecture and is capable of sustainedexecution at the rate of one instruction per clock. This processor’s features include generousinstruction cache, data cache, and data RAM. It also boasts a fast interrupt mechanism anddual-programmable timer units.The 80960Jx processor’s clock multiplication operates the processor core at two or three times thebus clock rate to improve execution performance without increasing the complexity of boarddesigns.Memory subsystems for cost-sensitive embedded applications often impose substantial wait statepenalties. The 80960Jx integrates considerable storage resources on-chip to decouple CPUexecution from the external bus.The 80960Jx rapidly allocates and de-allocates local register sets during context switches. Theprocessor must flush a register set to the stack only when it saves more than seven sets to its localregister cache.A 32-bit multiplexed burst bus provides a high-speed interface to system memory and I/O. A fullcomplement of control signals simplifies the connection of the 80960Jx to external components.The user programs physical and logical memory attributes through memory-mapped controlregisters (MMRs), an extension not found on the i960® Kx, Sx or Cx processors. Physical andlogical configuration registers enable the processor to operate with all combinations of bus widthand data object alignment. The processor supports a homogeneous byte ordering model.This processor integrates two important peripherals: a timer unit and an interrupt controller. Theseand other hardware resources are programmed through memory-mapped control registers, anextension to the familiar i960 processor architecture.The timer unit (TU) offers two independent 32-bit timers for use as real-time system clocks andgeneral-purpose system timing. These operate in either single-shot or auto-reload mode and maygenerate interrupts.The interrupt controller unit (ICU) provides a flexible, low-latency means for requesting interrupts.The ICU provides full programmability of up to 240 interrupt sources into 31 priority levels. TheICU takes advantage of a cached priority table and optional routine caching to minimize interruptlatency. Clock doubling on the 80960JD/JC processors reduces interrupt latency by 40% comparedto the 80960JA/JF, and clock tripling on the 80960JT reduces interrupt latency by 20% comparedto the 80960JD/JC. Local registers may be dedicated to high-priority interrupts to further reducelatency. Acting independently from the core, the ICU compares the priorities of posted interruptswith the current process priority, off-loading this task from the core. The ICU also supports theintegrated timer interrupts.The 80960Jx features a Halt mode designed to support applications where low power consumptionis critical. The halt instruction shuts down instruction execution, resulting in a power savings of upto 90 percent.The 80960Jx’s testability features, including ONCE (On-Circuit Emulation) mode and BoundaryScan (JTAG), provide a powerful environment for design debug and fault diagnosis.80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit MicroprocessorThe Solutions960® program features a wide variety of development tools which support the i960 processor family. Many of these tools are developed by partner companies; some are developed by Intel, such as profile-driven optimizing compilers. For more information on these products, contact your local Intel representative.2.180960 Processor CoreThe 80960Jx family is a scalar implementation of the 80960 core architecture. Intel designed this processor core as a very high performance device that is also cost-effective. Factors that contribute to the core ’s performance include:•Core operates at the bus speed with the 80960JA/JF/JS•Core operates at two or three times the bus speed with the 80960JD/JC and 80960JT,respectively•Single-clock execution of most instructions •Independent Multiply/Divide Unit•Efficient instruction pipeline minimizes pipeline break latency•Register and resource scoreboarding allow overlapped instruction execution •128-bit register bus speeds local register caching •Two-way set associative, integrated instruction cache •Direct-mapped, integrated data cache•1-Kbyte integrated data RAM delivers zero wait state program dataFigure 2. 80960Jx Block DiagramProgrammable Interrupt Controller Control Address/Instruction SequencerPhysical Region Configuration Interrupt Port1K Data RAMMemory Interface Execution Multiply UnitDivide UnitMemory-Mapped Register InterfaceData BusGlobal / Local Register FileSRC2DESTSRC1addressControleffective ConstantsGenerationUnitAddress 32-bit Address 32-bit DataBus Request Queuesand Two 32-BitTimers8-SetLocal Register CacheS R C 1S R C 2D E S TPLL, Clocks,Power MgmtBoundary Scan ControllerTAP 5CLKINS R C 1S R C 2D E S TS R C 1D E S T93232-bit buses address / data21Instruction Cache 80960JA - 2K 80960JF/JD - 4K80960JS/JC/JT - 16KDirect Mapped Data Cache 80960JA - 1K 80960JF/JD - 2K 80960JS/JC/JT -1283 Independent 32-Bit SRC1, SRC2, and DEST BusesBus Control Unit80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor2.2Burst BusA 32-bit high-performance Bus Controller Unit (BCU) interfaces the 80960Jx to external memoryand peripherals. The BCU fetches instructions and transfers data at the rate of up to four 32-bitwords per six clock cycles. The external address/data bus is multiplexed.Users may configure the 80960Jx’s bus controller to match an application’s fundamental memoryorganization. Physical bus width is register-programmed for up to eight regions. Byte ordering anddata caching are programmed through a group of logical memory templates and a defaults register.The BCU’s features include:•Multiplexed external bus to minimize pin count•32-, 16-, and 8-bit bus widths to simplify I/O interfaces•External ready control for address-to-data, data-to-data and data-to-next-address wait state types•Support for big or little endian byte ordering to facilitate the porting of existing program code•Unaligned bus accesses performed transparently•Three-deep load/store queue to decouple the bus from the coreUpon reset, the 80960Jx conducts an internal self-test. Then, before executing its first instruction, itperforms an external bus confidence test by performing a checksum on the first words of theinitialization boot record (IBR).2.3Timer UnitThe timer unit (TU) contains two independent 32-bit timers that are capable of counting at severalclock rates and generating interrupts. Each is programmed by use of the TU registers. Thesememory-mapped registers are addressable on 32-bit boundaries. The timers have a single-shotmode and auto-reload capabilities for continuous operation. Each timer has an independentinterrupt request to the 80960Jx’s interrupt controller. The TU may generate a fault whenunauthorized writes from user mode are detected. Clock prescaling is supported.2.4Priority Interrupt ControllerA programmable interrupt controller manages up to 240 external sources through an 8-bit externalinterrupt port. Alternatively, the interrupt inputs may be configured for individual edge- or level-triggered inputs. The interrupt unit (IU) also accepts interrupts from the two on-chip timer channelsand a single Non-Maskable Interrupt (NMI#) pin. Interrupts are serviced according to their prioritylevels relative to the current process priority.Low interrupt latency is critical to many embedded applications. As part of its highly flexibleinterrupt mechanism, the 80960Jx exploits several techniques to minimize latency:•Interrupt vectors and interrupt handler routines may be reserved on-chip.•Register frames for high-priority interrupt handlers may be cached on-chip.•The interrupt stack may be placed in cacheable memory space.•Interrupt microcode executes at two or three times the bus frequency for the 80960JD/JC and 80960JT, respectively.80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor2.5Instruction Set SummaryThe 80960Jx adds several new instructions to the i960 processor core architecture. The newinstructions are:•Conditional Move•Conditional Add•Conditional Subtract•Byte Swap•Halt•Cache Control•Interrupt ControlTable 2 identifies the instructions that the 80960Jx supports. Refer to the i960® Jx MicroprocessorDeveloper’s Manual (272483) for a detailed description of each instruction.2.6Faults and DebuggingThe 80960Jx employs a comprehensive fault model. The processor responds to faults by makingimplicit calls to a fault handling routine. Specific information collected for each fault allows thefault handler to diagnose exceptions and recover appropriately.The processor also has built-in debug capabilities. In software, the 80960Jx may be configured todetect as many as seven different trace event types. Alternatively, mark and fmark instructionsmay generate trace events explicitly in the instruction stream. Hardware breakpoint registers arealso available to trap on execution and data addresses.2.7Low Power OperationIntel fabricates the 80960Jx using an advanced sub-micron manufacturing process. The processor’ssub-micron topology provides the circuit density for optimal cache size and high operating speedswhile dissipating modest power. The processor also uses dynamic power management to turn offclocks to unused circuits.Users may program the 80960Jx to enter Halt mode for maximum power savings. In Halt mode,the processor core stops completely while the integrated peripherals continue to function, reducingoverall power requirements up to 90 percent. Processor execution resumes from internally orexternally generated interrupts.2.8Test FeaturesThe 80960Jx incorporates numerous features that enhance the user’s ability to test both theprocessor and the system to which it is attached. These features include ONCE (On-CircuitEmulation) mode and Boundary Scan (JTAG).80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor The 80960Jx provides testability features compatible with IEEE Standard Test Access Port andBoundary Scan Architecture (IEEE Std. 1149.1).One of the boundary scan instructions, HIGHZ, forces the processor to float all its output pins(ONCE mode). ONCE mode may also be initiated at reset without using the boundary scanmechanism.ONCE mode is useful for board-level testing. This feature allows a mounted 80960Jx toelectrically “remove” itself from a circuit board. This allows for system-level testing in which aremote tester, such as an in-circuit emulator, may exercise the processor system.The provided test logic does not interfere with component or circuit board behavior and ensuresthat components function correctly, connections between various components are correct, andvarious components interact correctly on the printed circuit board.The JTAG Boundary Scan feature is an attractive alternative to conventional “bed-of-nails” testing.It may examine connections that might otherwise be inaccessible to a test system.2.9Memory-Mapped Control RegistersThe 80960Jx, although compliant with the i960 processor core, has the added advantage ofmemory-mapped, internal control registers not found on the i960 Kx, Sx or Cx processors. Theseregisters give software the interface to easily read and modify internal control registers.Each of these registers is accessed as a memory-mapped, 32-bit register. Access is accomplishedthrough regular memory-format instructions. The processor ensures that these accesses do notgenerate external bus cycles.2.10Data Types and Memory Addressing ModesAs with all i960 processors, the 80960Jx instruction set supports several data types and formats:•Bit•Bit fields•Integer (8-, 16-, 32-, 64-bit)•Ordinal (8-, 16-, 32-, 64-bit unsigned integers)•Triple word (96 bits)•Quad word (128 bits)The 80960Jx provides a full set of addressing modes for C and assembly programming:•Two Absolute modes•Five Register Indirect modes•Index with displacement•IP with displacement。

SA8382中文资料

元器件交易网
SA828 Family
Three-Phase PWM Waveform Generator
DS4226 - 2.0 November 1996
The SA828 PWM generator has been designed to provide waveforms for the control of variable speed AC machines, uninterruptible power supplies and other forms of power electronic devices which require pulse width modulation as a means of efficient power control. The six TTL level PWM outputs (Fig. 2) control the six switches in a three-phase inverter bridge. This is usually via an external isolation and amplification stage. The SA828 is fabricated in CMOS for low power consumption. Information contained within the pulse width modulated sequences controls the shape, power frequency, amplitude, and rotational direction (as defined by the red-yellow-blue phase sequence) of the output waveform. Parameters such as the carrier frequency, minimum pulse width, and pulse delay time may be defined during the initialisation of the device. The pulse delay time (underlap) controls the delay between turning on and off the two power switches in each output phase of the inverter bridge, in order to accommodate variations in the turnon and turn-off times of families of power devices. The SA828 is easily controlled by a microprocessor and its fully-digital generation of PWM waveforms gives unprecedented accuracy and temperature stability. Precision pulse shaping capability allows optimum efficiency with any power circuitry. The device operates as a stand-alone microprocessor peripheral, reading the power waveform directly from an internal ROM and requiring microprocessor intervention only when operating parameters need to be changed. An 8-bit multiplexed data bus is used to receive addresses and data from the microprocessor/controller. This is a standard MOTELTM bus, compatible with most microprocessors/controllers. Rotational frequency is defined to 12 bits for high accuracy and a zero setting is included in order to implement DC injection braking with no software overhead. This family is pin and functionally compatible with the MA828 PWM generator . Two standard wave shapes are available to cover most applications. In addition, any symmetrical wave shape can be integrated on-chip to order.

AAT1102资料

R1 ) R2
3 4 5 6 7 8
SHDN GND SW VDD FREQ SS
Shutdown Control Pin. The Device Will Turn Off When SHDN is Low Ground Switch Pin Power Supply Pin Frequency Select Pin. Switch Oscillator Frequency to 640kHz When FREQ is Low, and 1.3MHz When FREQ is High Soft-Start Control Pin. No Soft-Start When the Pin is Left Open
SYMBOL
CONDITIONS
I LIM R ON
I SWOFF
VDD = 1V, Duty Cycle = 65% I SW = 1.2A
VSW = 12V
MIN 1.2
TYP MAX UNITS 1.6 2.3 A 0.23 0.50 Ω
0.01 20.00
µA
SOFT-START PARAMETER
The AAT1102’s versatility comes with a power-smart design. A soft-start programmed with an external capacitor that sets the input current ramp rate, reduces the current consumption to 0.1µA in shutdown mode. When operating, a mere 2.6V input yields an impressive output voltage as high as 12.5V. High switching frequency and economical design allow AAT1102 to be less than 1.1mm high. Its compact 8-pin MSOP package and superior performance make it an ideal part for biasing TFT displays.

MAX8632笔记本电脑内存供电控制芯片

MAX8632笔记本电脑内存供电控制芯片P O K 2P O K 1I L I MR E FO V P /U V PT O NS T B YＭＡＸ８６３２ＭＡＸ８６３２是笔记本电脑中常用的内存供电或芯片组供电控制芯片，内部集成了一路用于产生ＶＤＤＱ的同步降压ＰＷＭ控制器，一路用于产生ＶＴＴ电源输出和吸入电流的ＬＤＯ线性稳压器，另一路用于产生ＶＴＴＲ的１０ｍＡ基准输出缓冲器。

引脚号引脚名称引脚功能1TON 导通时间选择输入端。

该四电平逻辑输入用来设置额定DH 导通时间。

TON分别连接至GND、REF、AVDD及悬空时可选择不同额定开关频率2OVP/UVP 过压/欠压保护控制输入端。

该四电平逻辑输入用来使能/禁止过压/欠压保护。

过压门限值为额定输出电压的116%。

欠压门限值为额定输出电压的70%。

使能OVP的同时启动放电模式3REF +2.0V基准电压输出端。

用0.1μF电容旁路至GND。

REF 可为外部负载提供50μA电流。

可用于设置ILIM电压。

当SHDN为低电平，OUT<0.1V时，REF关断4ILIM Buck调节器的谷值限流门限调节端。

PGND与LX之间限流门限是ILIM端电压的0.1倍。

ILIM连接至REF和GND间的分压器，可将限流门限设置为25-200mV。

与之对应的ILIM 端电压范围为0.25-2V。

ILIM接至AVDD时限流门限为默认值50mV5POK1Buck电源就绪开漏输出端。

当buck输出电压比规定稳定电压高出或低出10%，或在软启动期间时，POK1为低电平。

当输出电压达到稳定器软启动电路停止工作时，POK1为高阻态。

关断模式下POK1为低电平6POK2LDO电源就绪开漏输出端。

在正常模式下，只要VTTR和VTTS电压中的任一个比额定稳压电压（通常为REFIN/2）高出或低出10%，POK2都为低电平。

待机模式下POK2仅对VTTR 输入响应。

关断模式下或当VREFIN小于0.8V时，POK2为低电平7STBY 待机控制端。

23226403中文资料

NTC Thermistors, Accuracy Line2322 640 3/4/6....Vishay BCcomponents For technical questions contact: nlr.europe@Document Number: 29049FEATURES• Accuracy over a wide temperature range • High stability over a long life • Excellent price/performance ratioAPPLICATIONS• Temperature sensing and controlThese thermistors have a negative temperature coefficient.元器件交易网2322 640 3/4/6....NTC Thermistors, Accuracy Line Vishay BCcomponents Document Number: 29049For technical questions contact: nlr.europe@ DERATING AND TEMPERATURE TOLERANCESDIMENSIONS in millimeters PHYSICAL DIMENSIONS FOR RELEVANT TYPEMARKINGThe thermistors are marked with coloured bands; seedimensions drawing and “Electrical data and orderinginformation”.MOUNTINGBy soldering in any position.2322 640 6.338 to 6.474.CODENUMBER2322 640.....B max dH1H2maxL P T maxMIN.MAX.6.338 to6.2215.00.6±0.061.0 4.0 6.024±1.52.54 4.06.331 to6.4743.3±0.50.6±0.06− 2.0±1.06.024±1.52.543.0Notes1.Dependent upon R25-tolerance, the band IV is coloured as follows:a)for R25±2%, band IV is coloured redb)for R25±3%, band IV is coloured orangec)for R25±5%, band IV is coloured goldd)for R25±10%, band IV is coloured silver.20003528 K ±0.5%4202620232022202red black red22003977 K ±0.75%4222622232222222red red red27003977 K ±0.75%4272627232722272red violet red33003977 K ±0.75%4332633233322332orange orange red47003977 K ±0.75%4472647234722472yellow violet red68003977 K ±0.75%4682668236822682blue grey red100003977 K ±0.75%4103610331032103brown black orange120003740 K ±2%4123612331232123brown red orange150003740 K ±2%4153615331532153brown green orange220003740 K ±2%4223622332232223red red orange330004090 K ±1.5%4333633333332333orange orange orange470004090 K ±1.5%4473647334732473yellow violet orange680004190 K ±1.5%4683668336832683blue grey orange1000004190 K ±1.5%4104610431042104brown black yellow1500004370 K ±2.5%4154615431542154brown green yellow2200004370 K ±2.5%4224622432242224red red yellow3300004570 K ±1.5%4334633433342334orange orange yellow4700004570 K ±1.5%4474647434742474yellow violet yellowR25(Ω)B25/85-VALUECATALOG NUMBER 2322 640 6....COLOR CODE(see dimensionsdrawing and note 1)R25 ±2%R25±3%R25 ±5%R25±10%I II III元器件交易网2322 640 3/4/6....Vishay BCcomponentsNTC Thermistors, Accuracy Line For technical questions contact: nlr.europe@Document Number: 29049TEMPERATURE DEVIATION AS A FUNCTION OF THE AMBIENT TEMPERATURE.TEMPERATURE DEVIATION AS A FUNCTION OF THE AMBIENT TEMPERATURE.TEMPERATURE DEVIATION AS A FUNCTION OF THE AMBIENT TEMPERATURE.TEMPERATURE DEVIATION AS A FUNCTION OF THE AMBIENT TEMPERATURE.TEMPERATURE DEVIATION AS A FUNCTION OF THE AMBIENT TEMPERATURE.TEMPERATURE DEVIATION AS A FUNCTION OF THE AMBIENT TEMPERATURE.元器件交易网2322 640 3/4/6....NTC Thermistors, Accuracy Line Vishay BCcomponents Document Number: 29049For technical questions contact: nlr.europe@ R T VALUE AND TOLERANCEThese thermistors have a narrow tolerance on the B-value,the result of which provides a very small tolerance on thenominal resistance value over a wide temperature range. Forthis reason the usual graphs of R = f(T) are replaced byResistance Values at Intermediate Temperatures Tables,together with a formula to calculate the characteristics with ahigh precision.FORMULAE TO DETERMINE NOMINALRESISTANCE VALUESThe resistance values at intermediate temperatures, or theoperating temperature values, can be calculated using thefollowing interpolation laws(extended “Steinhart and Hart”):(1)(2)where:A, B, C, D, A1, B1, C1 and D1 are constant valuesdepending on the material concerned; see table below.R ref is the resistance value at a reference temperature (inthis event 25 °C).T is the temperature in K.Formulae numbered (1) and (2) are interchangeable with anerror of max. 0.005 °C in the range 25 °C to 125 °C andmax. 0.015 °C in the range−40 °C to +25 °C.DETERMINATION OF THERESISTANCE/TEMPERATURE DEVIATIONFROM NOMINAL VALUEThe total resistance deviation is obtained by combining the‘R25-tolerance’ and the ‘resistance deviation due toB-tolerance’.When:X = R25-toleranceY = resistance deviation due to B-toleranceZ = complete resistance deviation,then: or Z ≈ X + Y.When:TC = temperature coefficient∆T = temperature deviation,then:The temperature tolerances are plotted in the graphs on theprevious page.Example: at 0 °C, assume X = 5%, Y = 0.89% andTC = 5.08%/K (see T able ), then:A NTC with a R25-value of 10 kΩ has a value of 32.56 kΩbetween −1.17 and +1.17 °C.R (T)R=ref e×A B T⁄C T2⁄D T3⁄+++()T (R) = A1B1RR ref---------ln C1ln2RR ref---------D1ln3RR ref---------+++⎝⎠⎛⎞1–Z1X100---------+⎝⎠⎛⎞1Y100---------+⎝⎠⎛⎞1–×= 100×%∆T ZTC-------=Z15100---------+10.89100-----------+1–×⎩⎭⎨⎬⎧⎫100%×=1.05 1.0089 1–×{} 100% 5.9345% 5.93%≈()=×˙=∆T ZTC-------5.935.08----------- 1.167 °C 1.17≈°C)(===Notes1.Temperature < 25 °C.2.Temperature ≥25 °C.2322 640 3/4/6....Vishay BCcomponentsNTC Thermistors, Accuracy Line For technical questions contact: nlr.europe@Document Number: 290492322 640 3/4/6....NTC Thermistors, Accuracy Line Vishay BCcomponents Document Number: 29049For technical questions contact: nlr.europe@ 5 2.0128 2.16−3.7120.1310 1.6767 1.59−3.6016.7715 1.4042 1.04−3.5014.0420 1.18210.51−3.3911.8225 1.00000.00−3.3010.00300.85000.50−3.208.50350.72590.98−3.117.26400.6226 1.44−3.03 6.23450.5363 1.89−2.94 5.36500.4639 2.33−2.86 4.64550.4029 2.75−2.78 4.03600.3512 3.16−2.71 3.51650.3073 3.56−2.64 3.07700.2698 3.95−2.57 2.70750.2377 4.32−2.50 2.38800.2101 4.69−2.43 2.10850.1864 5.04−2.37 1.86900.1658 5.38−2.31 1.66950.1479 5.72−2.25 1.481000.1323 6.05−2.20 1.321050.1187 6.36−2.14 1.191100.1068 6.67−2.09 1.071150.0964 6.98−2.040.961200.08717.27−1.990.871250.07907.56−1.940.791300.07177.84−1.900.721350.06538.11−1.850.651400.05968.37−1.810.601450.05458.63−1.770.551500.05008.89−1.730.50T oper(°C)R T/R25∆R DUE TOB-TOLERANCE(%)TC(%/K)R25(Ω)2322 640 .....; see note 1 at end of tables6.1092322 640 3/4/6....Vishay BCcomponentsNTC Thermistors, Accuracy Line For technical questions contact: nlr.europe@Document Number: 29049500.4470 2.37−3.00 6.70550.3856 2.80−2.92 5.78600.3339 3.21−2.84 5.01650.2903 3.62−2.76 4.35700.2533 4.01−2.69 3.80750.2218 4.39−2.62 3.33800.1948 4.77−2.56 2.92850.1717 5.13−2.50 2.58900.1518 5.48−2.44 2.28950.1346 5.82−2.38 2.021000.1196 6.15−2.32 1.791050.1067 6.47−2.27 1.601100.0954 6.79−2.22 1.431150.08557.09−2.17 1.281200.07687.39−2.12 1.151250.06917.69−2.07 1.041300.06247.97−2.030.941350.05658.25−1.980.851400.05128.52−1.940.771450.04658.78−1.900.701500.04239.04−.860.63T oper (°C)R T /R 25∆R DUE TO B-TOLERANCE(%)TC (%/K)R 25(Ω)2322 640 .....; see note 1 at end of tables6.1592322 640 3/4/6....NTC Thermistors, Accuracy Line Vishay BCcomponents Document Number: 29049For technical questions contact: nlr.europe@ 950.1346 6.00−2.38 2.961000.1196 6.34−2.32 2.631050.1067 6.68−2.27 2.351100.09547.00−2.22 2.101150.08557.32−2.17 1.881200.07687.62−2.12 1.691250.06917.93−2.07 1.521300.06248.22−2.03 1.371350.05658.50−1.98 1.241400.05128.78−1.94 1.131450.01659.06−1.90 1.021500.04239.32−1.860.93T oper(°C)R T/R25∆R DUE TOB-TOLERANCE(%)TC(%/K)R25(Ω)2322 640 .....; see note 1 at end of tables6.2292322 640 3/4/6....Vishay BCcomponentsNTC Thermistors, Accuracy Line For technical questions contact: nlr.europe@Document Number: 290491400.04079.49−2.07 1.34 1.91 2.771450.03689.79−2.02 1.21 1.73 2.501500.033310.08−1.981.101.562.26T oper (°C)R T /R 25∆R DUE TO B-TOLERANCE(%)TC (%/K)R 25(Ω)2322 640 .....; see note 1 at end of tables6.339 6.479 6.6892322 640 3/4/6....NTC Thermistors, Accuracy Line Vishay BCcomponents Document Number: 29049For technical questions contact: nlr.europe@ For technical questions contact: nlr.europe@Document Number: 29049−5 4.216 1.08 5.249.27511.3813.9119.8128.6742.160 3.2550.89 5.087.1628.79010.7415.3022.1432.565 2.5340.70 4.92 5.575 6.8428.36211.9117.2325.3410 1.9870.52 4.78 4.372 5.366 6.5589.34013.5119.8715 1.5700.34 4.64 3.454 4.239 5.1817.37810.6715.7020 1.2490.17 4.50 2.747 3.372 4.121 5.8698.49212.4925 1.0000.00 4.37 2.200 2.700 3.300 4.700 6.80010.00300.80590.16 4.25 1.773 2.176 2.660 3.788 5.4808.059350.65350.32 4.13 1.438 1.764 2.156 3.072 4.444 6.535400.53300.47 4.02 1.173 1.439 1.759 2.505 3.624 5.330450.43720.62 3.910.9618 1.180 1.443 2.055 2.972 4.372500.36050.77 3.800.79320.973 1.190 1.694 2.451 3.606550.29890.91 3.700.65750.8070.9863 1.405 2.032 2.989600.2490 1.05 3.600.54780.6720.8217 1.170 1.693 2.490650.2084 1.18 3.510.45860.5620.68790.9797 1.417 2.084700.1753 1.31 3.420.38570.4730.57850.8239 1.192 1.753750.1481 1.44 3.330.32580.3990.48870.6960 1.007 1.481800.1256 1.57 3.250.27640.3390.41460.59050.8544 1.256850.1070 1.69 3.160.23550.2890.35320.50310.7278 1.070900.09154 1.81 3.090.20140.2470.30210.43030.62250.9154950.07860 1.93 3.010.17290.2120.25940.36940.53450.78601000.06773 2.04 2.940.14900.1820.22350.31830.46070.67731050.05858 2.15 2.870.12890.1580.19330.27530.39830.58581100.05083 2.26 2.800.11180.1370.16770.23890.34570.50831150.04426 2.37 2.730.09740.11950.14610.20800.30100.44261200.03866 2.47 2.670.08510.10440.12760.18170.26290.38661250.03387 2.57 2.610.07450.09150.11180.15920.23030.33871300.02977 2.67 2.550.06550.08040.09820.13990.20240.29771350.02624 2.77 2.490.05770.07090.08660.12330.17840.26241400.02319 2.86 2.430.05100.06260.07650.10900.15770.23191450.02055 2.96 2.380.04520.05550.06780.09660.13980.20551500.018263.052.330.04020.04930.06030.08580.12420.1826T oper (°C)R T /R 25∆R DUE TO B-TOLERANCE(%)TC (%/K)R 25(k Ω)2322 640 .....; see note 1 at end of tables 6.222 6.272 6.332 6.472 6.682 6.103Document Number: 29049For technical questions contact: nlr.europe@350.67120.80 3.888.05410.0714.77400.5543 1.19 3.77 6.6528.31512.20450.4602 1.57 3.67 5.522 6.90310.12500.3839 1.94 3.57 4.607 5.7598.447550.3219 2.30 3.48 3.862 4.8287.081600.2710 2.65 3.39 3.252 4.067 5.963650.2293 2.99 3.30 2.751 3.439 5.044700.1947 3.33 3.22 2.337 2.921 4.284750.1661 3.66 3.14 1.993 2.492 3.654800.1422 3.98 3.06 1.707 2.134 3.129850.1223 4.29 2.99 1.467 1.834 2.690900.1055 4.60 2.92 1.266 1.583 2.321950.09135 4.90 2.85 1.096 1.370 2.0101000.07937 5.19 2.780.9524 1.190 1.7461050.06919 5.48 2.710.8302 1.038 1.5221100.06050 5.76 2.650.72600.9075 1.3311150.05307 6.04 2.590.63690.7961 1.1681200.04670 6.31 2.530.56040.7005 1.0271250.041216.572.470.49450.61810.9065T oper (°C)R T /R 25∆R DUE TO B-TOLERANCE(%)TC (%/K)R 25(k Ω)2322 640 .....; see note 1 at end of tables6.123 6.153 6.223 For technical questions contact: nlr.europe@Document Number: 290491050.05372 4.47 2.98 1.773 2.5251100.04635 4.70 2.92 1.530 2.1791150.04013 4.93 2.85 1.342 1.8861200.03485 5.15 2.79 1.150 1.6381250.03037 5.36 2.73 1.002 1.4271300.02654 5.57 2.670.8757 1.2471350.02326 5.78 2.610.7675 1.0931400.02044 5.98 2.550.67460.96081450.01802 6.18 2.500.59450.84681500.015926.372.440.52540.7483T oper (°C)R T /R 25∆R DUE TO B-TOLERANCE(%)TC (%/K)R 25(k Ω)2322 640 .....; see note 1 at end of tables 6.333 6.473Document Number: 29049For technical questions contact: nlr.europe@ For technical questions contact: nlr.europe@Document Number: 2904925 1.0000.00 4.95330.0470.0300.78250.37 4.82258.2367.8350.61630.74 4.70203.4289.6400.4883 1.09 4.59161.1229.5450.3892 1.44 4.47128.4182.9500.3120 1.77 4.36103.0146.7550.2515 2.10 4.2683.00118.2600.2038 2.43 4.1567.2695.80650.1660 2.74 4.0654.7978.03700.1359 3.05 3.9644.8663.88750.1118 3.35 3.8736.9052.55800.09240 3.64 3.7830.4943.43850.07670 3.93 3.6925.3136.05900.06395 4.21 3.6121.1030.06950.05354 4.48 3.5317.6725.161000.04501 4.75 3.4514.8521.151050.03798 5.01 3.3712.5317.851100.03218 5.27 3.3010.7015.121150.02736 5.52 3.239.02912.861200.02335 5.77 3.167.70410.971250.019996.013.096.5979.396T oper (°C)R T /R 25∆R DUE TO B-TOLERANCE(%)TC (%/K)R 25(k Ω)2322 640 .....; see note 1 at end of tables 6.334 6.474Document Number: 29049For technical questions contact: nlr.europe@900.08042 3.85 3.28 5.4698.042950.06837 4.10 3.21 4.649 6.8371000.05835 4.35 3.13 3.968 5.8351050.04998 4.59 3.06 3.399 4.9981100.04296 4.82 2.99 2.921 4.2961150.03705 5.05 2.92 2.519 3.7051200.03206 5.28 2.86 2.180 3.2061250.027835.502.801.8922.783T amb (°C)R T /R 25∆R DUE TO B-TOLERANCE(%)TC (%/K)R 25(k Ω)2322 640 .....; see note 1 at end of tables 6.683 6.104Note to Resistance Values At Intermediate Temperature Tables1.Replace dot in last 5 digits of catalog number by a number according to the following details and depending on tolerance onrequired R 25-value: 4 for a tolerance of ±2%; 6 for a tolerance of ±3%; 3 for a tolerance of ±5%; 2 for a tolerance of ±10%.PACKAGINGTAPE SPECIFICATIONSNote1.Taped products with H= 45±1, are available on request.2. D ≤5 max for 6404.338 to 221. For technical questions contact: nlr.europe@ Document Number: 29049Note1. D ≤5 max for 640 3. 338 to 640 4. 221.2.T ≤4 max for 6403. 338 to 6404. 221.Document Number: 29049For technical questions contact: nlr.europe@ Notes1.For R25≥ 100 kΩ the drift requirement is ∆R/R < 5%.2.For R25 from 2.2 kΩ to 10 kΩ, requirement is ±2% max. For technical questions contact: nlr.europe@ Document Number: 29049。

ATA5282资料

Features•Three Input Channels for 3D Antennas• 2.8mVPP Sensitivity Typically•Ultra Low Current Operation Consumption•2µA Standby Current Typically•4µA Active Current Typically•Power Supply 2V to 4.2V•Carrier Frequency Range from 100kHz to 150kHz •Wake-up Function for a Microcontroller •Header Detection•Baud Rate up to 4kbps (ASK Modulation)•Bi-directional Two-wire Interface•ESD According to Automotive Requirements Benefits•Digital RSSI for Field Strength Measurement•Coils Input Range from 2.8mVPP to 2.8V PP Typically•High SensitivityApplications•Passive Entry Go (PEG)/Car Access•Position Indicator•Home Access Control•RFID SystemsDescriptionThe ATA5282 is a 125-kHz ultra low power receiver IC with three input channels for Passive Entry Go applications. It includes all circuits for an LF wake-up channel. The three sensitive input stages of the IC amplifier demodulate and measure the input sig-nal from the antenna coils. The microcontroller interface of the IC outputs the data signal as well as the measured RSSI values. During standby mode, the header detec-tion unit monitors the incoming signal and generates a wake-up signal for the microcontroller if the IC receives a valid 125-kHz carrier signal.By combining the IC with an antenna coil, a microcontroller, an RF transmitter/trans-ceiver and a battery, it is possible to design a complete hands-free key for Passive Entry Go applications.2ATA5282[Preliminary]4694B–AUTO–06/04Figure 1. Block DiagramPin ConfigurationFigure 2. Pinning TSSOP 8LPin DescriptionPin Symbol Function1COIL1Input: Coil channel X 2COIL2Input: Coil channel Y 3COIL3Input: Coil channel Z 4VSS Circuit ground5TC Output: Current output for oscillator adjustment 6NSCL Input: Clock for serial interface (default high)7NDA TA Input/Output: I/O data for serial interface and field strength measurement/Wake-up function (default high)8VDDBattery voltage3ATA5282[Preliminary]4694B–AUTO–06/04Functional DescriptionThe ATA5282 is a 3-channel ASK receiver for 125-kHz carrier signals. Its three active input stages with very low power consumption and high input sensitivity allow to connect up to 3 antennas for direction-independent wake-up function and data transfer. Without a carrier signal the ATA5282 operates in standby listen mode. In this mode, it monitors the 3 Coil inputs with a very low current consumption. To activate the IC and the connected control unit, the transmitting end must send a preamble carrier burst and the header code. When a preamble has been detected, the IC activates the internal oscillator and the header check. The last gap at the end of a valid header enables the NDATA output.During data transfer, the NDATA pin outputs the demodulated and merged signal of the 3 input stages.To achieve data rates up to 4kbps for input signals from 2.8mV PP to 3.1V PP it is neces-sary to control the gain of the amplifiers. Each of the 3 input stages contain an amplifier with Automatic Gain Control (AGC). It is used to adapt the gain to the incoming signal strength, and is also used as RSSI for field strength measurements.The integrated synchronous serial interface uses the NSCL together with the NDATA pin as clock and data line. It allows to control several functions as well as read out the received signal field strength. Enabling only single coil inputs, freezing the actual status of the automatic gain control or resetting the complete circuit to the initial state at any time are built-in features.When communication is finished or a time out event occurs, the internal watchdog timer or reset command via the serial interface sets the IC to standby listen mode.4ATA5282[Preliminary]4694B–AUTO–06/04Functional State Diagram This diagram gives an overview of the major tasks performed by the ATA5282. Thedetailed function of the automatic gain control that is active during preamble check,header check and data transfer is not shown here.Figure 3. ATA5282 State Diagram5ATA5282[Preliminary]4694B–AUTO–06/04AGC AmplifierEach of the three input stages contain an AGC amplifier to amplify the input signal from the Coil. The gain is adjusted by the automatic gain control circuit if a preamble signal is detected. The high dynamic range of the AGC amplifier enables the IC to work with input signals from 2.8mV PP to 3.1V PP . After the AGC settling time has elapsed, the amplifier output delivers a 125-kHz signal with an amplitude adjusted for the following evaluation circuits (preamble detection, signal conditioner, wake-up).Automatic Gain ControlFor correct demodulation, the signal conditioner needs an appropriate internal signal amplitude. To control the input signal, the ATA5282 has a built-in digital AGC for each input channel. This gain control circuit regulates the internal signal amplitude to the ref-erence level (Ref2, Figure 4 on page 6). The gain control uses the signal of the input channel with the highest amplitude for the regulation as well as signal for the signal conditioner.During the preamble, each period of the carrier signal decreases the gain if the internal signal exceeds the reference level. If the signal does not achieve the reference level,each period increases the gain. After 192 preamble periods, the standard gain control mode is activated. In this mode, the gain is decreased every two periods if the internal signal exceeds the reference level and increased every eight periods if the reference level is not achieved. These measures assure that the input signal’s envelope deforma-tion will be minimized.During the gaps between signal bursts, the gain control is frozen to avoid that the gain be modified by noise signals.The tuning range of the AGC is subdivided into 256 regulator steps. The settling time for the full tuning range requires 320periods (192 + (2 × 64) periods) during a preamble phase. To accelerate the settling time, fast gain control mode can be activated via the serial interface. In this mode, the tuning range is subdivided into 128 steps and the set-tling time is two times faster.In standby listen mode, the gain is reset to the maximum value. A proper carrier signal activates the automatic gain control.The preamble (Figure 9 on page 10) with up to 320 periods of the 125kHz magnetic field is used to control the gain of the input amplifiers. To detect the starting point of the header, the start gap should not exceed 256µs (32 periods of 125kHz).6ATA5282[Preliminary]4694B–AUTO–06/04Figure 4. Automatic Gain Control7ATA5282[Preliminary]4694B–AUTO–06/04Field Strength RSSI (Received Signal Strength Indicator)The digital value of the AGC counter is used as an indicator for the corresponding field strength of the input signal. The digital value can be accessed by the microcontroller via the serial interface.Figure 5. Field Strength as a Function of Coil Input SignalThe characteristic gain control value versus the coil input signal (see Figure 5) can be calculated by using the following equation:RSSI_V = ROUND (32.36 × Ln(V CI )PP + 192.7)RSSI_V:Digital value of field strength Ln():Natural logarithm functionV CI :Coil input voltage With the variation of the gain the coil input impedance changes from high impedance tominimal 143k Ω (Figure 6). This impedance variation is an insignificant influence to the quality factor of the resonant circuits.Figure 6. Coil Input Impedance8ATA5282[Preliminary]4694B–AUTO–06/04Signal ConditionerThe signal conditioner operates on the demodulated output signal of all three channels. Figure 7. Function of Signal ConditionerThe AGC reduces the gain of all 3 channels with reference to the signal with the highest amplitude. This automatically reduces the gain of channels with medium or low input signal amplitudes which results in the suppression of further process of these channels.The logical combination of the 3 demodulated output signals mostly represents the sig-nal with the highest input amplitude.Preamble DetectionTo prevent the circuit from unintended operations in a noisy environment, the preamble is checked to consist of 192 periods minimum. Three consecutive periods missing do not disturb counting. With this check passed, the circuit starts the internal oscillator at the end of the preamble (Figure 11 on page 12). The AGC needs a maximum of 256steps for full range tuning of amplifiers.9ATA5282[Preliminary]4694B–AUTO–06/04Before data transmission occurs the IC remains in standby listen mode. To prevent the circuit from unintended operations in a noisy environment, the preamble detection circuit checks the input signal. A valid signal is detected by a counter circuit after 192 carrier periods without interrupts. Short interrupts which are suppressed by the signal condi-tioner are tolerated. If a valid carrier (preamble) has been found, the circuit starts the automatic gain control. It requires up to 256 carrier periods for settling. The complete preamble should have at least 320 carrier periods.Internal OscillatorIf the end of the preamble is detected, the internal oscillator starts operating. It works as a time base to generate the time windows for the header detection, the header time-out check, the 20-ms-no-signal check and the data transmission duration watchdog. An external resistor connected to TC selects the oscillators frequency and defines all inter-nal timings.Header Detection and Wake-upThe preamble needs to be followed by the specific header. This header ensures that the built-in header detection wakes up the controller only with a valid signal. One possible protocol used for wake-up and data transmission is shown in Figure 9 on page 10 and Figure 11 on page 12.The standard header information must be transferred in OOK-mode (On-Off-Keying)with a duty cycle of 50%. The header detection starts with the start gap. A valid header requires 8 consecutive samples of rising and falling edges before the NDATA pin switches from high to low.Figure 8. Standard HeaderIf no valid header has been detected within 2ms, beginning at the end of the preamble,the header time-out check stops the oscillator and resets the gain control as well as the header detection circuit to their initial state. The circuit then waits for the next preamble. In case of corrupted data or in a noisy environment, the controller also may use the serial interface to reset the ATA5282 to the initial state. This is performed by shifting a specific command into the internal command register.10ATA5282[Preliminary]4694B–AUTO–06/04Figure 9. Wake-up Protocol for 125-kHz ASK Modulation11ATA5282[Preliminary]4694B–AUTO–06/04Data OutputThe wake-up signal enables the data pin that delivers the received and demodulated data stream to the controller. Sampling and decoding has to be performed by the con-troller. An example for data coding is given in the "n Bit Data" field (Figure 9 on page 10). This kind of modulation requires an indication of the end of data, for example, by a burst that differs from the other transmitted bits. As the circuit does not check the received data (except the header), it is up to the base station which kind of modulation (pulse distance, Manchester, bi-phase...) is used.The data output signal is derived from the internal GAP detection. Table 1 describes how the timing depends on different conditions of the applied input signal. The Q-factor of the external LC-tank as well as the signal strength influence the pulse width of the output signal.Figure 10. Output Timing ConditonsTable 1. Typical Output Timing versus Signal Strength at 3.2 V Supply VoltageInput Signal a, c(Figure 10)b (Periods)d (Periods)no Q Q ≤ 14Q ≤ 20no Q Q ≤ 14Q ≤ 20Minimum, 2.8mV PP Depends on Q-factor2 to 43 to 54 to 6 2 to 4 3 to5 3 to 5Medium, V CI < 3.2V PP 2 to 4 3 to 5 4 to6 2 to 4 3 to 5 3 to 5Strong, V CI ≥ 3.2V PP2 to 42 to 42 to 42 to 43 to 53 to 512ATA5282[Preliminary]4694B–AUTO–06/04Current Profile and Reset FunctionAs long as the ATA5282 does not receive and recognize a valid preamble, it stays in alow-current listen mode with the gain control and the header detection reset to their ini-tial state. After the circuit has passed the preamble check, the internal oscillator and the watchdog (for a 360 ms interval) starts. This results in an increased current consump-tion. The target of the different reset sources is to reduce the current consumption as fast as possible back to the initial value.This can take place at the end of the header time-out check at the earliest. If no valid header has been detected within 2ms, the circuit switches back to the initial state.With wake-up activated, three further mechanism are available to control the reset. One under control of the connected microcontroller, one if no signal is received and one unconditional after a fixed time.The controller may shift the SOFTRES-command into the internal command register to force the circuit into the reset state. This may be useful if the controller detects that the received data are corrupted.The ATA5282 itself permanently checks for incoming signals. An interval of 20ms (no signal received) also leads to the reset state.If there is no valid signal within 20 ms, for example, in a noisy environment or due to customer protocol requirements, the watchdog forces the circuit into the reset state after a fixed time of 360ms at the latest.Figure 11. Current Profile and Reset Timing13ATA5282[Preliminary]4694B–AUTO–06/04Serial InterfaceGeneral DescriptionThe serial interface is an easy-to-handle 8-bit 2-wire interface. It always operates as a slave. The controller uses the NSCL input to shift a command into and data out of the internal shift register. The interface starts working with the first falling edge of NSCL.NDATA/NWAKEUP serves as bi-directional DATA I/O for command input and data out-put. The rising edge of NSCL is used to clock the command into the register of the ATA5282, while the falling edge is used to shift out the data. Data changes are always derived from the falling edge of NSCL. Two operating modes are implemented. One is the command mode that only requires an 8-bit input and does not prepare a data output.This mode is useful to control different operating modes of the ATA5282, as described on the following pages. The second mode is used to read out the current value of the AGC-counter that is related to the field strength of the input signal. The READ_FS com-mand starts an internal sequence to store the value of the AGC into the shift register and switches the DATA I/O to output mode. After t ACC , the controller must deliver another 8 shift clocks to clock out the information.Figure 12. Serial Interface14ATA5282[Preliminary]4694B–AUTO–06/04Command and Data RegisterThe 8-bit command register is organized as follows:Note:These commands, except FREEZE- and READ_FS, cause a reset of AGC to initial state.Note:The content of the data register is updated every time a READ_FS command is given via the interface.Table 2. Command RegisterMSB CommandLSB FunctionFREEZ ECH_SE L 1CH_SE L 2READ_FSSOFT_RESFGCnot usedTEST MOD Default value after reset: 00 hex0Application mode active1Test mode active XFor future use0Standard gain control active (AGC full range: 256 steps)1Fast gain control active (AGC full range: 128 steps)0No effect1Reset circuit to initial state 0Noeffect1Read AGC-counter (field strength)00Coil input 1, 2, 3 active 01Select Coil input 1 (disable 2 and 3)1Select Coil input 2 (disable 1 and 3)11Select Coil input 3 (disable 1 and 2)0Automatic Gain Control (AGC) active 1AGC stopped with actual valueTable 3. Data RegisterMSB Data LSB Function AGC7AGC6AGC5AGC4AGC3AGC2AGC1AGC0Default value ’00’hex15ATA5282[Preliminary]4694B–AUTO–06/04Command DescriptionNote:Every command except FREEZE- and READ_FS causes a reset of the AGC to its initial state.TEST_MOD Not for customer use, this mode is only used for production tests.FGCWith FGC set to 1, the time for a full-range control cycle of the AGC is 128 steps instead of 256 steps as in standard mode. This divides the AGC settling time by 2, compared to the standard mode.SOFT_RESIn addition to the internal hardware reset and watchdog functions, this bit allows the con-nected microcontroller to switch the circuit into the initial low-power state. All internal registers including the serial interface and the gain control counter are reset by this command.READ_FSAs long as this bit is kept at 0, the interface is in write mode and accepts 8-bit com-mands only. Setting Read_FS to 1 enables to read out the digital 8-bit value of the gain control counter (RSSI), thus requiring two 8-bit accesses. The distance between the two accesses (t ACC ) must be >50µs to allow proper operating and updating of the internal data register.CH_SEL0,1These two bits define the operation mode of the three channels. After reset, all channels are active. With the CH_SEL-bits, one of the three channels can be selected to be active, while the other two are disabled. The gain control is reset to the initial value if these bits are modified and operates only with the selected channel. This feature can be used for three-dimensional field strenght measurements or to suppress the influence of noise from disturbing channels.FREEZEWhen set to 1, this bit disables the automatic gain control and maintains the actual value for the gain of the input amplifiers. Even when changing the input amplitudes (for exam-ple, modulation through noise or movement), the gain is kept constant.ExampleThe example shows how to program the circuit to operate on channel 1 only and to measure the field strength of the Coil 1 input signal.Figure 13 shows the command entry which activates Coil 1 input only and also the fast gain control (FGC). The gain control counter is set to zero (highest sensitivity) by this command. The information is shifted into the ATA5282 with the rising edge of the shift clock.Figure 13. Select Coil Input 1 + FGC16ATA5282[Preliminary]4694B–AUTO–06/04Figure 14 shows the second step, the read-out of the actual field strength of the signal applied to Coil 1.When 128 steps have been passed, the gain control is finished and the value can be read out. This is performed by providing the command READ_FS with the information of the selected channel. 50µs later, the ATA5282 has updated and stored the information into the internal shift register. Now the microcontroller can read the actual information by generating the next 8 shift clock pulses. The information changes on the falling edge of the clock pulse.Figure 14. Read Field Strength of Channel 1Reset InterfaceTo prevent the system from hanging or running into a deadlock condition due to distur-bances on the NSCL line (hardware or software), a special function is provided to reset,the interface.Figure 15. Reset InterfaceSetting the NSCL to a low level and generating 4 clock pulses at the NDATA pin resets all interface-relevant registers and flip-flops, thus cancelling the deadlock condition and resynchronizing the interface.17ATA5282[Preliminary]4694B–AUTO–06/04ApplicationFigure 16 shows an application of the ATA5282. Combined with the antenna resonant circuit, the ATA5282 is used as wake-up receiver for the microcontroller. Additional to the antenna circuits the blocking filter - consisting of a RC element (R 1=100Ω,C 1=10nF) - is neccessary for the ATA5282. An additional resistor (R 2=2M Ω/1%)should be placed at TC for oscillator tuning (optional: a parallel capacitor C 2 with maxi-mum 10pF).Figure 16. Application Circuit18ATA5282[Preliminary]4694B–AUTO–06/04Figure 17. Pin Connection and Pin Protection19ATA5282[Preliminary]4694B–AUTO–06/04Absolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Parameters Symbol Value Unit Power supplyV DD -0.3 to +6.5V Input voltage (except coil inputs)V IN V SS - 0.3 < V IN < V DD + 0.3V Input current coil I CI ±10mA Input voltage coilV CI V DD - 3.5 < V CI < V DD + 3.5V ESD protection (human body)V ESD 4kV Operating temperature range T amb -40 to +85°C Storage temperature range T stg -40 to +130°C Soldering temperaturT sld 260°C Thermal resistance (TSSOP 8L)R thJA240k/WThermal ResistanceParametersSymbol Value Unit Thermal resistance junction-case R thJC 260°C Thermal resistance junction-ambientR thJC240°COperating RangeParameters Symbol Value Unit Power supply range V DD 2 to 4.2V Operating temperature rangeT OP-40 to +85°C20ATA5282[Preliminary]4694B–AUTO–06/04Electrical CharacteristicsV SS = 0 V , V DD = 3.2 V , T amb = 25°C unless otherwise specified No.Parameters Test ConditionsPin Symbol Min.Typ.Max.Unit Type*1Power Supply and Coil Limiter1.1Power supply 8V DD 23.24.2V A 1.2Supply current(initial state, AGC off)8I DD 24µA A 1.3Supply current (AGC active)8I DD 46µA A 1.4Power on reset threshold V POR 1 1.51.9V A 1.5Power up timeSwitch on V DD to circuit activeV PON 100ms C 1.6RESET reactivation caused bynegative spikes on V DD t BDN = 500ns7t RST10100µs C1.711.721.73Coil input voltage refered to V DD (Input Coil limiter for channels X, Y , Z)I CI = ±1mA V DD =2.0V V DD =3.2V V DD =4.2V 1, 2, 3V CI ±1.2±1.4±1.55V P V P V P A 1.8TC low current output V O_TC at 500mV5I TC 230250270nA A 1.9Carrier frequency range 1, 2, 3f CF 100150kHz D 2Amplifiers 2.1Wake-up sensitivity 125-kHz input signal 7V SENS 2.8 3.6mV PP A 2.2BandwithWithout Coil B W 200kHz C 2.3Upper corner frequency Without Coil f u 230kHz C 2.4Lower corner frequency Without Coil f o30kHz C 2.5Gain difference Channel to channel 1, 2, 3G DIFF ±20%A 2.6Input impedance V IN ≥ 2.8mV PP at 125kHz 1, 2, 3R IN 143k ΩA 2.7Input capacitance 1, 2, 3C IN10pF C 2.8Coils Input Range V CI = 2.8mV PP V CI = 2.8V PP1, 2, 360dBA3Digital3.1Oscillator frequency R EXT = 2M Ω and C EXT maximum 10pF f OSC8090100kHz A 3.2Preamble periods (not FGC)V CI ≥ 3.2V PP 1, 2, 3n PAM 320A3.3Header detection windows (L = long, S = short)see Figure 8 on page 9Tolerance included oscillator tolerancet ST ART_L 160182205µs A 3.4t END_L 315357400µs A 3.5t ST ART_S 405060µs A 3.6t END_S 200225255µs A 3.7Shift clock period 6t NSCL 10µs C 3.8Data access time t ACC 50µsA 3.9Data rate (Q < 20)125kHz ASK D RATE 4kbps A 3.10Delay time RF signal to data 125kHz ASK t ON 40µs A 3.11Delay time RF signal to data125kHz ASKt OFF40µsA*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter21ATA5282[Preliminary]4694B–AUTO–06/044Interface4.1NSCL input level LOW 6V IL_NSCL V SS 0.2 × V DDV A 4.2NSCL input level HIGH 6V IH_NSCL 0.8 × V DDV DD V A 4.3NSCL input leakage current LOWV NSCL = V SS 6I IL_NSCL -2000nA A 4.4NSCL input leakage current HIGHV NSCL = V DD 6I IH_NSCL 0+200nA A 4.5NDA T A input level LOW V NSCL = V SS 7V IL_NDAT V SS 0.2 × V DDV A 4.6NDA T A input level HIGHV NSCL = V SS7V IH_NDAT 0.8 × V DDV DD V A 4.7NDA T A input leakage current LOW V NDAT = V SS V NSCL = V SS 7I IL_NDAT -2000nA A 4.8NDA T A input leakage current HIGH V NDAT = V DD V NSCL = V SS 7I IH_NDA T 0+200nA A 4.9NDA T A output level LOW I NDAT = +100µAV NSCL = V DD 7V OL_NDAT V SS 0.2 × V DDV A 4.10NDA T A output level HIGHI NDAT = -100µA V NSCL = V DD7V OL_NDAT0.8×V DDV DDVAElectrical Characteristics (Continued)V SS = 0 V , V DD = 3.2 V , T amb = 25°C unless otherwise specified No.Parameters Test ConditionsPinSymbolMin.Typ.Max.UnitType**) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter22ATA5282[Preliminary]4694B–AUTO–06/04Ordering InformationPackage InformationFigure 18. Package TSSOP 8LExtended Type Number Package Remarks ATA5282TSSOP 8L–Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems.Atmel CorporationAtmel Operations2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 487-2600Regional HeadquartersEuropeAtmel SarlRoute des Arsenaux 41Case Postale 80CH-1705 Fribourg SwitzerlandTel: (41) 26-426-5555Fax: (41) 26-426-5500AsiaRoom 1219Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong KongTel: (852) 2721-9778Fax: (852) 2722-1369Japan9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JapanTel: (81) 3-3523-3551Fax: (81) 3-3523-7581Memory2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 436-4314Microcontrollers2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 436-4314La Chantrerie BP 7060244306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18Fax: (33) 2-40-18-19-60ASIC/ASSP/Smart CardsZone Industrielle13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00Fax: (33) 4-42-53-60-011150 East Cheyenne Mtn. Blvd.Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300Fax: 1(719) 540-1759Scottish Enterprise Technology Park Maxwell BuildingEast Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000Fax: (44) 1355-242-743RF/AutomotiveTheresienstrasse 2Postfach 353574025 Heilbronn, Germany Tel: (49) 71-31-67-0Fax: (49) 71-31-67-23401150 East Cheyenne Mtn. Blvd.Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300Fax: 1(719) 540-1759Biometrics/Imaging/Hi-Rel MPU/High Speed Converters/RF DatacomAvenue de Rochepleine BP 12338521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00Fax: (33) 4-76-58-34-80Literature Requests/literature4694B–AUTO–06/04© Atmel Corporation 2004. All rights reserved.Atmel ® and combinations thereof are the registered trademarks of Atmel Corporation or its subsidiaries.Other terms and product names may be the trademarks of others.。

三键电容式触控芯片XC2863 Datasheet

三通道电容式触摸键控制芯片XC2863目录1概述 (3)1.1 特性 (3)1.2 系统框图 (4)2管脚定义 (5)3功能描述 (6)4电气特性 (7)5关键特性 (8)5.1 环境自适应能力 (8)5.1.1环境漂移跟随 (8)5.1.2环境突变校准 (8)6应用指南 (9)7PCB设计 (10)7.1 触摸键设计 (10)7.1.1触摸键 (10)7.1.2触摸键的常用结构 (10)7.1.3触摸键设计 (11)7.2 PCB布线 (11)8封装 (12)1概述XC2863是一款支持宽工作电压范围的三输入三输出电容式触摸键控制芯片。

XC2863内部集成高分辨率触摸检测模块和专用信号处理电路，以保证芯片对环境变化具有灵敏的自动识别和跟踪功能，且内置特殊算法以实现防水、抗干扰等需求。

该芯片可满足用户在复杂应用中对稳定性、灵敏度、功耗、响应速度、防水、带水操作、抗震动、抗电磁干扰等方面的高体验要求。

XC2863为方便用户在应用中可对触摸键的灵敏度进行自主控制，特设置了灵敏度控制位。

用户只需在PCB设计中对这个管脚的逻辑电平值进行设置，就能自由选择在具体应用中芯片体现出的检测灵敏度。

XC2863还内置了上电复位及电源保护电路，在典型应用中可无需任何外部器件，也无需软件、程序或参数烧录。

芯片应用的开发过程非常简单，最大限度的降低了方案成本。

XC2863可广泛适用于遥控器、灯具调光、各类开关以及小家电和家用电器控制界面等应用中。

1.1特性工作电压：2.5V~5.5V三个高灵敏度的触摸检测通道无需进行参数烧录响应速度快抗电磁干扰能力强防水及带水操作功能独特的环境跟踪和自适应能力低功耗（典型工作电流< 25uA）内置上电复位（POR）和电源保护电路CMOS电平输出1.2系统框图XC2863包含PMU和Touch Key Core两个部分，其系统框图如图1所示。

图1 XC2863的系统框图2管脚定义XC2863采用SOP8封装，管脚分布如图2所示。

ADC0832CCN

±1 ±1
± 1⁄2 ±1 ± 1⁄2 ±1
Molded (N) Molded (N) SO(M) PCC (V) PCC (V) Molded (N) C0831/ADC0832/ADC0834/ADC0838
Absolute Maximum Ratings
+
15 mA 6.5V
Operating Ratings (Notes 1, 2)
Supply Voltage, VCC Temperature Range ADC0832/8CIWM ADC0834BCN, ADC0838BCV, ADC0831/2/4/8CCN, ADC0838CCV, ADC0831/2/4/8CCWM 0˚C to +70˚C 4.5 VDC to 6.3 VDC TMIN≤TA≤TMAX −40˚C to +85˚C
2)
(Notes 1,
Dual-In-Line Package (Plastic) Molded Chip Carrier Package Vapor Phase (60 sec.) Infrared (15 sec.) ESD Susceptibility (Note 5)
260˚C 215˚C 220˚C 2000V
Key Specifications
n n n n n Resolution Total Unadjusted Error Single Supply Low Power Conversion Time 8 Bits
± 1⁄2 LSB and ± 1 LSB
5 VDC 15 mW 32 µs
Features
General Description
The ADC0831 series are 8-bit successive approximation A/D converters with a serial I/O and configurable input multiplexers with up to 8 channels. The serial I/O is configured to comply with the NSC MICROWIRE™ serial data exchange standard for easy interface to the COPS™ family of processors, and can interface with standard shift registers or µPs. The 2-, 4- or 8-channel multiplexers are software configured for single-ended or differential inputs as well as channel assignment. The differential analog voltage input allows increasing the common-mode rejection and offsetting the analog zero input voltage value. In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution. n n n n n n n n n n Operates ratiometrically or with 5 VDC voltage reference No zero or full-scale adjust required 2-, 4- or 8-channel multiplexer options with address logic Shunt regulator allows operation with high voltage supplies 0V to 5V input range with single 5V power supply Remote operation with serial digital data link TTL/MOS input/output compatible 0.3" standard width, 8-, 14- or 20-pin DIP package 20 Pin Molded Chip Carrier Package (ADC0838 only) Surface-Mount Package

AOT9608中文资料

Continuous DrainParameter T =25°C Gate-Source Voltage Drain-Source Voltage Absolute Maximum Ratings T =25°C unless otherwise notedAOT10N60 / AOTF10N60DSDSSymbolMin Typ Max Units600V 700V BV DSS /∆T J 0.65V/ oC 110I GSS ±100nA V GS(th)345V R DS(ON)0.60.75Ωg FS 15S V SD 0.731V I S 10A I SM36A C iss 110013201600pF C oss 105130160pF C rss 7.59.311pF R g33.86ΩQ g 31.140nC Q gs 6.410nC Q gd 14.420nC t D(on)2835ns t r 6680ns t D(off)7695ns t f 6480ns t rr 290350ns Q rr3.94.7µC4.4THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. AOS DOES NOT ASSUME ANY LIABILITY ARISING OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. AOS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN,FUNCTIONS AND RELIABILITY WITHOUT NOTICE.V DS =480V, T J =125°C Breakdown Voltage Temperature CoefficientI D =250µA, V GS =0V Gate Threshold VoltageV DS =V GS , I D =250µA V DS =600V, V GS =0V V DS =0V, V GS =±30V Zero Gate Voltage Drain Current Gate-Body leakage current Body Diode Reverse Recovery TimeI D =250µA, V GS =0V, T J =25°C V GS =10V, I D =5A Reverse Transfer Capacitance I F =10A,dI/dt=100A/µs,V DS =100VV GS =0V, V DS =25V, f=1MHz SWITCHING PARAMETERS I DSS µA Maximum Body-Diode Pulsed CurrentElectrical Characteristics (T J =25°C unless otherwise noted)STATIC PARAMETERS Parameter Conditions Static Drain-Source On-Resistance Forward TransconductanceDiode Forward Voltage I S =1A, V GS =0V V DS =40V, I D =5ATurn-On Rise Time Turn-Off DelayTime V GS =10V, V DS =300V, I D =10A, R G =25ΩGate resistanceV GS =0V, V DS =0V, f=1MHzTurn-Off Fall TimeTotal Gate Charge V GS =10V, V DS =480V, I D =10AGate Source Charge Gate Drain Charge BV DSS Drain-Source Breakdown Voltage I D =250µA, V GS =0V, T J =150°C Body Diode Reverse Recovery Charge I F =10A,dI/dt=100A/µs,V DS =100VMaximum Body-Diode Continuous Current Input Capacitance Output Capacitance Turn-On DelayTime DYNAMIC PARAMETERS A: The value of R θJA is measured with the device in a still air environment with T A =25°C.B. The power dissipation P D is based on T J(MAX)=150°C, using junction-to-case thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsinking is used.C: Repetitive rating, pulse width limited by junction temperature T J(MAX)=150°C.D. The R θJA is the sum of the thermal impedence from junction to case R θJC and case to ambient.E. The static characteristics in Figures 1 to 6 are obtained using <300 µs pulses, duty cycle 0.5% max.F. These curves are based on the junction-to-case thermal impedence which is measured with the device mounted to a large heatsink, assuming a maximum junction temperature of T J(MAX)=150°C.G. L=60mH, I AS =4.4A, V DD =50V, R G =25Ω, Starting T J =25°CRev 0. July 2008VdsC ha rgeG ate Charge Test Circuit & W av eformResistiv e Switching Test Circuit & W av eformsVddVdsI dVgsB V I Unclamped Inductive Switching (UIS) Test Circuit & W av eformsARDSS2E = 1/2 LI VddARAR。

A43L2616AV-6中文资料

Preliminary 1M X 16 Bit X 4 Banks Synchronous DRAMDocument Title1M X 16 Bit X 4 Banks Synchronous DRAMRevision HistoryDate Remark Rev. No. History Issue issue November 30, 2004 Preliminary0.0 InitialA43L2616APreliminary1M X 16 Bit X 4 Banks Synchronous DRAMFeatureJEDEC standard 3.3V power supplyLVTTL compatible with multiplexed address Four banks / Pulse RAS MRS cycle with address key programs - CAS Latency (2,3)- Burst Length (1,2,4,8 & full page) - Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Clock Frequency: 166MHz @ CL=3 143MHz @ CL=3Burst Read Single-bit Write operationDQM for masking Auto & self refresh 64ms refresh period (4K cycle) Commercial Temperature Operation : 0°C~70°C Industrial Temperature Operation : -40°C~85°C for –U grade 54 Pin TSOP (II) and 54 Balls CSP (8mm x 8mm)General DescriptionThe A43L2616A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 X 1,048,576 words by 16 bits, fabricated with AMIC’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock.I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.Pin ConfigurationTSOP (II)V S SD Q 15V S S QD Q 14D Q 13V D D QD Q 12D Q 11V S S QD Q 10D Q 9V D D QD Q 8V S SU D Q MC KC K EN CA 9A 8A 7A 6A 5A 4V S SV D DD Q 0V D D QD Q 1D Q 2V S S QD Q 3D Q 4V D D QD Q 5D Q 6V S S QD Q 7V D DL D Q MW EC A SR A SC SA 10/A PB S 1B S 0A 0A 1A 2A 3V D DA 11N CPin Configuration (continued)54 Balls CSP (8 mm x 8 mm)Top ViewBlock DiagramCLKADDDQiPin DescriptionsAbsolute Maximum Ratings*Voltage on any pin relative to VSS (Vin, Vout ) . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +4.6V Voltage on VDD supply relative to VSS (VDD, VDDQ ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to +4.6V Storage Temperature (T STG ) . . . . . . . . . . -55°C to +150°C Soldering Temperature X Time (T SLODER ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C X 10sec Power Dissipation (P D ) . . . . . . . . . . . . . . . . . . . . . . . . .1W Short Circuit Current (Ios) . . . . . . . . . . . . . . . . . . . . 50mA *CommentsPermanent device damage may occur if “Absolute Maximum Ratings” are exceeded.Functional operation should be restricted to recommended operating condition.Exposure to higher than recommended voltage for extended periods of time could affect device reliability.Capacitance (T A =25°C, f=1MHz)DC Electrical CharacteristicsRecommend operating conditions (Voltage referenced to VSS = 0V, T A = 0ºC to +70ºC or T A = -40ºC to +85ºC)Parameter Symbol Min Typ Max Unit NoteSupply Voltage VDD,VDDQ 3.0 3.3 3.6 VInput High Voltage V IH 2.0 3.0 VDD+0.3 VInput Low Voltage V IL -0.3 0 0.8 V Note 1 Output High Voltage V OH 2.4 --V I OH = -2mAOutput Low Voltage V OL - - 0.4 V I OL = 2mA Input Leakage Current I IL -5 - 5 µA Note 2 Output Leakage Current I OL -5 - 5 µANote 3Output Loading ConditionSee Figure 1Note: 1. V IL (min) = -1.5V AC (pulse width ≤ 5ns).2. Any input 0V ≤ VIN ≤ VDD + 0.3V, all other pins are not under test = 0V3. Dout is disabled, 0V ≤ Vout ≤ VDDDecoupling Capacitance Guide LineRecommended decoupling capacitance added to power line at board.Parameter Symbol Value UnitDecoupling Capacitance between VDD and VSS C DC1 0.1 + 0.01 µF Decoupling Capacitance between VDDQ and VSSQC DC20.1 + 0.01µFNote: 1. VDD and VDDQ pins are separated each other.All VDD pins are connected in chip. All VDDQ pins are connected in chip. 2. VSS and VSSQ pins are separated each otherAll VSS pins are connected in chip. All VSSQ pins are connected in chip.DC Electrical Characteristics(Recommended operating condition unless otherwise noted, T A = 0°C to 70°C T A = -40ºC to +85ºC) Note: 1. Measured with outputs open. Addresses are changed only one time during t CC (min).2. Refresh period is 64ms. Addresses are changed only one time during t CC (min).3. I CC6 normal version: A43L2616AV-6, A43L2616AV-7.4. I CC6 low self refresh current version: A43L2616AV-6V, A43L2616AV-7V.AC Operating Test Conditions(VDD = 3.3V ±0.3V, T A = 0°C to +70°C or T A = -40ºC to +85ºC)Parameter ValueAC input levelsV IH /V IL = 2.4V/0.4V Input timing measurement reference level 1.4VInput rise and all time (See note3)tr/tf = 1ns/1ns Output timing measurement reference level 1.4V Output load conditionSee Fig.2Output(Fig. 1) DC Output Load Circuit ΩTT =1.4V (Fig. 2) AC Output Load CircuitAC Characteristics(AC operating conditions unless otherwise noted)-6 -7Symbol Parameter CAS Latency Min Max Min MaxUnit Notet CC CLK cycle time 6 1000 7 1000 ns 1t SACCLK to valid Output delay- 5 - 5.4 ns 1,2 t OH Output data hold time 2.5-2.7-ns2t CH CLK high pulse width 32.5 - 2.5 - ns 3 t CL CLK low pulse width 2.5 - 2.5 - ns 3 t SS Input setup time 2 - 2 - ns 3 t SH Input hold time 1 - 1 - ns 3 t SLZ CLK to output in Low-Z 1-1-ns2t SHZCLK to output In Hi-Z3- 5.5 - 6 ns*All AC parameters are measured from half to half.Note : 1. Parameters depend on programmed CAS latency.2. If clock rising time is longer than 1ns, (tr/2-0.5) ns should be added to the parameter.3. Assumed input rise and fall time (tr & tf) = 1ns.If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.Operating AC Parameter(AC operating conditions unless otherwise noted)Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer.2. Minimum delay is required to complete write.Simplified Truth Table(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low) Note : 1. OP Code: Operand CodeA0~A11, BS0, BS1: Program keys. (@MRS)2. MRS can be issued only at both banks precharge state.A new command can be issued after 2 clock cycle of MRS.3. Auto refresh functions as same as CBR refresh of DRAM.The automatical precharge without Row precharge command is meant by “Auto”.Auto/Self refresh can be issued only at both precharge state.4. BS0, BS1 : Bank select address.If both BS1 and BS0 are “Low” at read, write, row active and precharge, bank A is selected.If both BS1 is “Low” and BS0 is “High” at read, write, row active and precharge, bank B is selected.If both BS1 is “High” and BS0 is “Low” at read, write, row active and precharge, bank C is selected.If both BS1 and BS0 are “High” at read, write, row active and precharge, bank D is selected.If A10/AP is “High” at row precharge, BS1 and BS0 is ignored and all banks are selected.5. During burst read or write with auto precharge, new read write command cannot be issued.Another bank read write command can be issued at every burst length.6. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0) butmasks the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)Mode Register Filed Table to Program ModesRegister Programmed with MRS AddressBS0, BS1A11, A10A9A8A7A6A5A4A3A2A1A0FunctionRFURFU W.B.L TM CAS Latency BT Burst Length(Note 1)(Note 2)Test ModeCAS LatencyBurst TypeBurst LengthA8 A7TypeA6 A5 A4Latency A3TypeA2A1 A0 BT=0BT=10 0 Mode Register Set0 0 0Reserved0Sequential 00 0 1 1 0 1 0 0 1- 1Interleave 00 1 2 2 1 0 0 1 0 2 0 1 0 4 4 1 1Vendor Use Only0 1 1 3 0 1 188 Write Burst Length 1 0 0Reserved 10 0 Reserved Reserved A9 Length 1 0 1Reserved10 1 ReservedReserved0 Burst 1 1 0Reserved 1 1 0 Reserved Reserved 1 Single Bit 1 1 1Reserved11 1 256(Full)ReservedPower Up Sequence1. Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at inputs.2. Maintain stable power, stable clock and NOP input condition for a minimum of 200µs.3. Issue precharge commands for all banks of the devices.4. Issue 2 or more auto-refresh commands.5. Issue a mode register set command to initialize the mode register. cf.) Sequence of 4 & 5 may be changed.The device is now ready for normal operation.Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.Burst Sequence (Burst Length = 4)Initial addressSequential Interleave A1 A00 0 0 1 2 3 0 1 2 30 1 1 2 3 0 1 0 3 21 023 0 1 2 3 0 11 1 3 0 123 2 1 0Burst Sequence (Burst Length = 8)Initial addressSequential Interleave A2 A1 A00 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 70 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 60 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 50 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 41 0 0 4 5 6 7 0 1234567 0 1 2 31 0 1 5 6 7 0 12345 4 76 1 0 3 21 1 0 6 7 0 1234567 4 5 2 3 0 11 1 1 7 0 1234567 6 5 4 3 2 1 0Device OperationsClock (CLK)The clock input is used as the reference for all SDRAM operations. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between V IL and V IH. During operation with CKE high all inputs are assumed to be in valid state (low or high) for the duration of set up and hold time around positive edge of the clock for proper functionality and ICC specifications.Clock Enable (CLK)The clock enable (CKE) gates the clock onto SDRAM. If CKE goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock is suspended form the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When both banks are in the idle state and CKE goes low synchronously with clock, the SDRAM enters the power down mode form the next clock cycle. The SDRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at least “t SS + 1 CLOCK” before the high going edge of the clock, then the SDRAM becomes active from the same clock edge accepting all the input commands.Bank Select (BS0, BS1)This SDRAM is organized as 4 independent banks of 1,048,576 words X 16 bits memory arrays. The BS0, BS1 inputs is latched at the time of assertion of RAS and CASto select the bank to be used for the operation. The bank select BS0, BS1 is latched at bank activate, read, write mode register set and precharge operations.Address Input (A0 ~ A11)The 20 address bits required to decode the 262,144 word locations are multiplexed into 12 address input pins (A0~A11). The 12 bit row address is latched along with RAS, BS0 and BS1 during bank activate command. The 8 bit column address is latched along with CAS, WE, BS0 and BS1during read or write command.NOP and Device DeselectWhen , CAS and WE are high, the SDRAM performs no operation (NOP). NOP does not initiate any new operation, but is needed to complete operations which require more than single clock like bank activate, burst read, auto refresh, etc. The device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS, CAS and WE, and all the address inputs are ignored.Power-UpThe following sequence is recommended for POWER UP 1. Power must be applied to either CKE and DQM inputs topull them high and other pins are NOP condition at the inputs before or along with VDD (and VDDQ) supply.The clock signal must also be asserted at the same time.2. After VDD reaches the desired voltage, a minimumpause of 200 microseconds is required with inputs in NOP condition.3. Both banks must be precharged now.4. Perform a minimum of 2 Auto refresh cycles to stabilizethe internal circuitry.5. Perform a MODE REGISTER SET cycle to program theCAS latency, burst length and burst type as the default value of mode register is undefined.At the end of one clock cycle from the mode register set cycle, the device is ready for operation.When the above sequence is used for Power-up, all the out-puts will be in high impedance state. The high impedance of outputs is not guaranteed in any other power-up sequence.cf.) Sequence of 4 & 5 may be changed.Mode Register Set (MRS)The mode register stores the data for controlling the various operation modes of SDRAM. It programs the CAS latency, addressing mode, burst length, test mode and various vendor specific options to make SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SDRAM. The mode register is written by asserting low on CS,RAS, CAS,(The SDRAM should be in active mode with CKE already high prior to writing the mode register). The state of address pins A0~A11, BS0 and BS1 in the same cycle as CS,,CAS,WE going low is the data written in the mode register. One clock cycle is required to complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as both banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length field uses A0~A2, burst type uses A3, addressing mode uses A4~A6, A7~A8, A11, BS0 and BS1 are used for vendor specific options or test mode. And the write burst length is programmed using A9. A7~A8, A11, BS0 and BS1 must be set to low for normal SDRAM operation.Refer to table for specific codes for various burst length, addressing modes and CAS latencies.Device Operations (continued)Bank ActivateThe bank activate command is used to select a random row in an idle bank. By asserting low on RAS and CS with desired row and bank addresses, a row access is initiated. The read or write operation can occur after a time delay of t RCD(min) from the time of bank activation. t RCD(min) is an internal timing parameter of SDRAM, therefore it is dependent on operating clock frequency. The minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing t RCD(min) with cycle time of the clock and then rounding off the result to the next higher integer. The SDRAM has two internal banks on the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of both banks immediately. Also the noise generated during sensing of each bank of SDRAM is high requiring some time for power supplies recover before the other bank can be sensed reliably. t RRD(min) specifies the minimum time required between activating different banks. The number of clock cycles required between different bank activation must be calculated similar to t RCD specification. The minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by t RAS(min) specification before a precharge command to that active bank can be asserted. The maximum time any bank can be in the active state is determined by t RAS(max). The number of cycles for both t RAS(min) and t RAS(max) can be calculated similar to t RCD specification.Burst ReadThe burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The burst read command is issued by asserting low on CS and CAS with WE being high on the positive edge of the clock. The bank must be active for at least t RCD(min) before the burst read command is issued. The first output appears CAS latency number of clock cycles after the issue of burst read command. The burst length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed. The burst read can be initiated on any column address of the active row. The address wraps around if the initial address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in the mode register. The output goes into high-impedance at the end of the burst, unless a new burst read was initiated to keep the data output gapless. The burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. The burst stop command is valid at every page burst length. Burst WriteThe burst write command is similar to burst read command, and is used to write data into the SDRAM consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. By asserting low on CS,CAS and WE with valid column address, a write burst is initiated. The data inputs are provided for the initial address in the same clock cycle as the burst write command. The input buffer is deselected at the end of the burst length, even though the internal writing may not have been completed yet. The writing can not complete to burst length. The burst write can be terminated by issuing a burst read and DQM for blocking data inputs or burst write in the same or the other active bank. The burst stop command is valid only at full page burst length where the writing continues at the end of burst and the burst is wrap around. The write burst can also be terminated by using DQM for blocking data and precharging the bank “t RDL” after the last data input to be written into the active row. See DQM OPERATION also.DQM OperationThe DQM is used to mask input and output operation. It works similar to OE during read operation and inhibits writing during write operation. The read latency is two cycles from DQM and zero cycle for write, which means DQM masking occurs two cycles later in the read cycle and occurs in the same cycle during write cycle. DQM operation is synchronous with the clock, therefore the masking occurs for a complete cycle. The DQM signal is important during burst interrupts of write with read or precharge in the SDRAM. Due to asynchronous nature of the internal write, the DQM operation is critical to avoid unwanted or incomplete writes when the complete burst write is not required.PrechargeThe precharge operation is performed on an active bank by asserting low on CS,RAS,WE and A10/AP with valid BA of the bank to be precharged. The precharge command can be asserted anytime after t RAS(min) is satisfied from the bank activate command in the desired bank. “t RP” is defined as the minimum time required to precharge a bank. The minimum number of clock cycles required to complete row precharge is calculated by dividing “t RP” with clock cycle time and rounding up to the next higher integer. Care should be taken to make sure that burst write is completed or DQM is used to inhibit writing before precharge command is asserted. The maximum time any bank can be active is specified by t RAS(max). Therefore, each bank has to be precharged within t RAS(max) from the bank activate command. At the end of precharge, the bank enters the idle state and is ready to be activated again.Entry to Power Down, Auto refresh, Self refresh and Mode register Set etc, is possible only when both banks are in idle state.Device Operations (continued)Auto PrechargeThe precharge operation can also be performed by usingauto precharge. The SDRAM internally generates thetiming to satisfy t RAS(min) and “t RP” for the programmedburst length and CAS latency. The auto prechargecommand is issued at the same time as burst read or burstwrite by asserting high on A10/AP. If burst read or burstwrite command is issued with low on A10/AP, the bank isleft active until a new command is asserted. Once autoprecharge command is given, no new commands arepossible to that particular bank until the bank achieves idlestate.Four Banks PrechargeBoth banks can be precharged at the same time by using Precharge all command. Asserting low on CS,RAS and WE with high on A10/AP after both banks have satisfied t RAS(min) requirement, performs precharge on both banks.At the end of tRP after performing precharge all, bothbanks are in idle state.Auto RefreshThe storage cells of SDRAM need to be refreshed every64ms to maintain data. An auto refresh cycle accomplishesrefresh of a single row of storage cells. The internalcounter increments automatically on every auto refreshcycle to refresh all the rows. An auto refresh command is issued by asserting low on CS,RAS and CAS with high on CKE and WE. The auto refresh command can only be asserted with both banks being in idle state and the deviceis not in power down mode (CKE is high in the previouscycle). The time required to complete the auto refresh operation is specified by “t RC(min)”. The minimum number of clock cycles required can be calculated by driving “t RC” with clock cycle time and then rounding up to the next higher integer. The auto refresh command must be followed by NOP’s until the auto refresh operation is completed. Both banks will be in the idle state at the end of auto refresh operation. The auto refresh is the preferred refresh mode when the SDRAM is being used for normal data transactions. The auto refresh cycle can be performed once in 15.6us or a burst of 4096 auto refresh cycles once in 64ms.Self RefreshThe self refresh is another refresh mode available in the SDRAM. The self refresh is the preferred refresh mode for data retention and low power operation of SDRAM. In self refresh mode, the SDRAM disables the internal clock and all the input buffers except CKE. The refresh addressing and timing is internally generated to reduce power consumption.The self refresh mode is entered from all banks idle state by asserting low on CS,RAS,CAS and CKE with high on WE. Once the self refresh mode is entered, only CKE state being low matters, all the other inputs including clock are ignored to remain in the self refresh.The self refresh is exited by restarting the external clock and then asserting high on CKE. This must be followed by NOP’s for a minimum time of “t RC” before the SDRAM reaches idle state to begin normal operation. If the system uses burst auto refresh during normal operation, it is recommended to used burst 4096 auto refresh cycles immediately after exiting self refresh.Basic feature And Function Descriptions1. CLOCK SuspendNote: CLK to CLK disable/enable=1 clock2. DQM Operation* Note : 1. DQM makes data out Hi-Z after 2 clocks which should masked by CKE “L”.2. DQM masks both data-in and data-out.3. CAS Interrupt (I)Note : 1. By “Interrupt”, It is possible to stop burst read/write by external command before the end of burst.By “CAS Interrupt”, to stop burst read/write by CAS access; read, write and block write.2. t CCD : CAS to CAS delay. (=1CLK)3. t CDL : Last data in to new column address delay. (= 1CLK).4. CAS Interrupt (II) : Read Interrupted Write & DQM* Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.2. To prevent bus contention, DQM should be issued which makes a least one gap between data in and data out.5. Write Interrupted by Precharge & DQMNote : 1. To inhibit invalid write, DQM should be issued.2. This precharge command and burst write command should be of the same bank, otherwise it is not prechargeinterrupt but only another bank precharge of dual banks operation.6. Precharge7. Auto Precharge* Note : 1. The row active command of the precharge bank can be issued after t RP from this point.The new read/write command of other active bank can be issued from this point.At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.8. Burst Stop & Interrupted by Precharge9. MRSNote : 1. t RDL : 1CLK 2. t BDL : 1CLK; Last data in to burst stop delay.Read or write burst stop command is valid at every burst length.3. Number of valid output data after row precharge or burst stop: 1,2 for CAS latency = 2, 3 respectively.4. PRE: All banks precharge if necessary.MRS can be issued only when all banks are in precharged state.10. Clock Suspend Exit & Power Down Exit11. Auto Refresh & Self Refresh* Note : 1. Active power down : one or more bank active state.2. Precharge power down : both bank precharge state.3. The auto refresh is the same as CBR refresh of conventional DRAM.No precharge commands are required after Auto Refresh command.During t RC from auto refresh command, any other command can not be accepted.4. Before executing auto/self refresh command, both banks must be idle state.5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.6. During self refresh mode, refresh interval and refresh operation are performed internally.After self refresh entry, self refresh mode is kept while CKE is LOW.During self refresh mode, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.During t RC from self refresh exit command, any other command can not be accepted.Before/After self refresh mode, burst auto refresh cycle (4K cycles ) is recommended.12. About Burst Type ControlSequential counting At MRS A3=”0”. See the BURST SEQUENCE TABE.(BL=4,8) BL=1,2,4,8 and full page wrap around.BasicMODEInterleave counting At MRS A3=” 1”. See the BURST SEQUENCE TABE.(BL=4,8) BL=4,8 At BL=1,2 Interleave Counting = Sequential CountingRandom MODE Random column Accesst CCD = 1 CLKEvery cycle Read/Write Command with random column address can realizeRandom Column Access.That is similar to Extended Data Out (EDO) Operation of convention DRAM.13. About Burst Length ControlPower On Sequence & Auto RefreshCKECSRASCASADDRBS0, BS1A10/APWEDQMDQ(A-Bank)Single Bit Read-Write-Read Cycles (Same Page) @CAS Latency=3, Burst Length=1CLOCKCKECSRASCASADDRBS0, BS1A10/APWEDQMDQ* Note : 1. All inputs can be don’t care when CS is high at the CLK high going edge.2. Bank active & read/write are controlled by BS0, BS1.BS1 BS0 Active & Read/WriteA0 0 BankB0 1 BankC1 0 BankD1 1 Bank3. Enable and disable auto precharge function are controlled by A10/AP in read/write command.A10/AP BS1 BS0Operation0 0 Disable auto precharge, leave bank A active at end of burst.0 1 Disable auto precharge, leave bank B active at end of burst.1 0 Disable auto precharge, leave bank C active at end of burst.1 1 Disable auto precharge, leave bank D active at end of burst.0 0 Enable auto precharge, precharge bank A at end of burst.0 1 Enable auto precharge, precharge bank B at end of burst.11 0 Enable auto precharge, precharge bank C at end of burst.1 1 Enable auto precharge, precharge bank D at end of burst.4. A10/AP and BS0, BS1 control bank precharge when precharge command is asserted.A10/AP BS1 BS0 PrechargeA0 0 0 BankB0 0 1 BankC0 1 0 BankD0 1 1 BankBanks1 X X All。

DS8632NST用户使用手册

视频监控系统操作手册目录一、开关机 (1)1.1开机 (1)1.2关机/重启 (2)二、向导 (3)三、权限认证 (3)四、系统时间配置 (4)五、网络配置 (4)六、硬盘初始化 (5)七、快速添加IP通道 (6)八、录像配置 (6)九、IP 通道配置 (8)9.1 快捷添加 (8)9.2IP通道常规添加 (10)十、一键快捷录像配置 (11)十一、回放 (11)11.1 即时回放 (11)11.2通道回放 (11)十二、备份 (12)十三、常见问题解答 (12)一、开关机1.1开机注意➢请确认接入的电压与NVR的要求相匹配，并保证NVR接地端接地良好。

➢电源供电不正常时，会导致NVR不能正常工作，甚至损坏NVR，建议使用稳压电源进行供电。

说明在开机前，请确保有显示器与设备的视频输出口相连接。

具体开机步骤如下：1、插上电源。

2、轻按后面板电源“开关键”。

设备开始启动，弹出“开机”界面，如图说明➢设备启动后，DS-8632N-ST系列设备电源指示灯呈蓝色常亮，其他系列设备电源指示灯呈绿色常亮。

➢设备启动后，可通过开机向导进行简单配置，使设备正常工作。

1.2关机/重启注意系统提示“系统正在关闭中…”时，请不要按电源“开关键”。

设备运行时（特别是正在录像时），请勿强制关机（即直接断开电源）。

具体关机/重启步骤如下：1、选择“主菜单→设备关机”。

进入“设备关机”界面。

2、单击“关机/重启”，弹出提示窗口。

3、单击“是”，设备关机/重启。

二、向导➢设备启动后，可通过开机向导进行密码修改、系统时间配置、网络配置、硬盘初始化、IP通道添加等一些简单操作，使设备能够正常工作。

具体操作步骤如下：1、确认下次开机时是否再启用向导2、单击“下一步”。

三、权限认证1、输入管理员密码2、选择“修改管理员密码”➢若不修改管理员密码，则不选择“修改管理员密码”，直接单击“下一步”。

➢管理员密码出厂默认为12345。

3、输入新密码与确认密码。

A3212中文规格书-Datasheet资料

A3212中文规格书-Datasheet资料DFN (EH)Micropower, UltrasensitiveHall-Ef f ect SwitchesA3211 and A3212 DFN (EL)This device includes on a single silicon chip a Hall-voltage gen-erator, small-signal amplifier, chopper sta b i l i z a t ion, a latch, and a MOSFET output. Advanced CMOS processing is used to take advantage of low-voltage and low-power requirements, compo-nent matching, very low input-offset errors, and small component geometries.Four package styles provide magnetically op t i m ized solutions for most ap p li c a t ions. Miniature low-profile surface-mount package types EH and EL (0.75 and 0.50 mm nominal height) are leadless, LH is a 3-pin low-profile SMD, and UA is a three-pin SIP for through-hole mount i ng. Packages are lead (Pb) free (suffix, –T )with 100% matte tin plated leadframes.Description (continued)Absolute Maximum RatingsCharacteristicSymbol NotesRating Units Supply Voltage V DD 5V Magnetic Flux Density B UnlimitedG Output Off Voltage V OUT 5V Output CurrentI OUT 1mA Operating Ambient Temperature T A Range E –40 to 85oC Range L–40 to 150oC Maximum Junction T emperature T J (max)165oC Storage TemperatureT stg–65 to 170oCSelection GuidePart Number Packing 1PackageAmbient TemperatureT A (°C)State in Magnetic FieldA3211EEHLT–T 23000 pieces per reel 2 mm x 3 mm, 0.75 mm nominal height DFN –40 to 85OffA3211EELLT–T 23000 pieces per reel 2 mm x 2 mm, 0.50 mm nominal height DFN A3211ELHLT–T 3000 pieces per reel 3-pin surface mount SOT23WA3212EEHLT–T 23000 pieces per reel 2 mm x 3 mm, 0.75 mm nominal height DFN –40 to 85OnA3212EELLT–T 23000 pieces per reel 2 mm x 2 mm, 0.50 mm nominal height DFN A3212ELHLT–T 3000 pieces per reel 3-pin surface mount SOT23W A3212EUA–T 500 pieces per bulk bag SIP-3 through holeA3212LLHLT–T 3000 pieces per reel 3-pin surface mount SOT23W –40 to 150A3212LUA–T500 pieces per bulk bagSIP-3 through hole1Contact Allegro for additional packaging and handlingoptions.2Allegro products sold in DFN package types are not intended for automotive applications.Package Suffix ‘UA’ Pinning(SIP)Package Suffix ‘LH’ Pinning(SOT23W)Dwg. PH-016-1S U P P L YG R O U N DO U T P U TELECTRICAL CHARACTERISTICS over operating voltage and temperature range (unless otherwise specified).Characteristic Symbol Test ConditionsLimitsMin.Typ.*Max.UnitsSupply Voltage Range V DD Operating 2.5 2.75 3.5V Output Leakage Current I OFF V OUT = 3.5 V, Output off–<1.0 1.0μA Output On Voltage V OUT I OUT = 1 mA, V DD = 2.75 V–100300mV Awake Time t awake–4590μs Period t period–4590ms Duty Cycle d.c.–0.1–% Chopping Frequency f C–340–kHz Supply Current I DD(EN)Chip awake (enabled)––2.0mA I DD(DIS)Chip asleep (disabled)––8.0μAI DD(AVG)V DD = 2.75 V–5.110μAV DD = 3.5 V–6.710μA* Typical data is at T A = 25°C and V DD = 2.75 V, and is fordesign information only.A3211 MAGNETIC CHARACTERISTICS over operating voltage range (unless otherwise specified)Characteristic Symbol Test ConditionsLimitsMin.Typ.Max.UnitsOver Temperature Range E: T A = –40°C to 85°COperate Points B OPS South pole to branded side; B > B OP, V OUT = High (Output Off)–3755G B OPN North pole to branded side; B > B OP, V OUT = High (Output Off)–55–40–GRelease Points B RPS South pole to branded side; B < B RP, V OUT = Low (Output On)1031–G B RPN North pole to branded side; B < B RP, V OUT = Low (Output On)––34–10GHysteresis B HYS|B OPx - B RPx|– 5.9–G NOTES: 1. Negative flux densities are defined as less than zero (algebraic convention),i.e., -50 G is less than +10 G.2.B OPx = operate point (output turns off); B RPx = release point (output turns on).3. Typical Data is at T A = +25°C and V DD = 2.75 V and is for design information only.4. 1 gauss (G) is exactly equal to 0.1 millitesla (mT).Characteristic Symbol Test ConditionsLimitsMin.Typ.Max.UnitsOver Temperature Range E: T A = –40°C to 85°COperate Points B OPS South pole to branded side; B > B OP, V OUT = Low (Output On)–3755G B OPN North pole to branded side; B > B OP, V OUT = Low (Output On)–55–40–GRelease Points B RPS South pole to branded side; B < B RP, VOUT = High (Output Off)1031–G B RPN North pole to branded side; B < B RP, V OUT = High (Output Off)––34–10GHysteresis B HYS|B OPx - B RPx|–5.9–G Over Temperature Range L: T A = –40°C to 150°COperate Points B OPS South pole to branded side; B > B OP, V OUT = Low (Output On)–3765G B OPN North pole to branded side; B > B OP, V OUT = Low (Output On)–65–40–GRelease Points B RPS South pole to branded side; B < B RP, V OUT = High (Output Off)1031–G B RPN North pole to branded side; B < B RP, V OUT = High (Output Off)––34–10GHysteresis B HYS|B OPx - B RPx|– 5.9–G NOTES: 1. Negative flux densities are defined as less than zero (algebraic convention),i.e., -50 G is less than +10 G.2.B OPx = operate point (output turns on); B RPx = release point (output turns off).3. Typical Data is at T A = +25°C and V DD = 2.75 V and is for design information only.4. 1 gauss (G) is exactly equal to 0.1 millitesla (mT).A3212 MAGNETIC CHARACTERISTICS over operating voltage range (unless otherwise specified)SUPPLY CURRENTFUNCTIONAL DESCRIPTIONChopper-Stabilized Technique. The Hall element can be considered as a resistor array similar to a Wheatstone bridge. A large portion of the offset is a result of the mismatching of theseresistors. These devices use a proprietary dynamic offset cancel-lation technique, with an internal high-frequency clock to reduce the residual offset voltage of the Hall element that is normally caused by device overmolding, temperature de p en d en c ies, and thermal stress. The chopper-stabilizing technique cancels the mismatching of the resistor circuit by changing the direction of the current flowing through the Hall plate using CMOS switches and Hall voltage measurement taps, while maintaing the Hall-voltage signal that is induced by the external magnetic flux. The signal is then captured by a sample-and-hold circuit and further processed using low-offset bipolar circuitry. This technique produces devices that have an extremely stable quiescent Hall output voltage, are immune to thermal stress, and have precise recoverability after temperature cycling. A relatively high sam-pling frequency is used for faster signal processing capability can be processed.More detailed descriptions of the circuit operation can be found in: Technical Paper STP 97-10, Monolithic Magnetic Hall Sensing Using Dynamic Quadrature Offset Cancellation and Technical Paper STP 99-1, Chopper-Stabilized Amplifiers With A Operation. The output of the A3212 switches low (turns on)the operate point B OPS (or is less than B OPN output is capable of sinking up to 1 mA and the output voltage is V OUT(ON). When the magnetic field is reduced below the release point B RPS (or increased above B RPN switches high (turns off). The dif f er e and release points is the hysteresis (B hys ) of the device. This built-in hysteresis allows clean switching of the output even in the presence of external mechanical vibration andelectrical to the right.As used here, negative flux densities are defined as less than zero (algebraic convention), i.e., -50 G is less than +10 G.Applications. Allegro's pole-independent processing tech-nique allows for operation with either a north pole or south pole magnet orientation, enhancing the manufacturability of the device. The state-of-the-art technology provides the same output polarity for either pole face.It is strongly recommended that an external bypass ca p ac i t or be con n ect e d (in close proximity to the Hall element) between the supply and ground of the device to reduce both external noise and noise generated by the chopper-sta b i l i z a t ion tech n ique. This is especially true due to the relatively high im p ed a nce of battery supplies.The sim p lest form of magnet that will op e r a te these devices is a bar magnet with either pole near the branded surface of the device. Many oth e r meth o ds of operation are possible. Ex t en- s ive applications information for Hall-effect devices is available in:Hall-Effect IC Applications Guide , Application Note 27701;? Hall-Effect Devices: Soldering, Gluing, Potting, En c ap s ul at-i ng, and Lead Forming , Application Note 27703.1;? Soldering of Through-Hole Hall-Sensing Dervices , Application Note 27703; andSoldering of Surface-Mount Hall-Sensing Devices , Application Note 27703.2. All are provided at/doc/fa769bda541810a6f524ccbff121 dd36a32dc4f8.htmlFUNCTIONAL DESCRIPTION (cont'd)0+B0-B5 V MAXO U T P U T V O L T A G EMAGNETIC FLUXPackage EH, 6-Contact DFNA Terminal #1 mark areaB Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion)For Reference Only, not for tooling use (reference DWG-2861;reference JEDEC MO-229WCED, Type 1)Dimensions in millimetersExact case and lead configuration at supplier discretion within limits shown CReference land pattern layout;All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) Hall Element (not to scale); U.S. customary dimensions controlling Branding scale and appearance at supplier discretion EF Active Area Depth, 0.32 mm NOMGG 1.042+0.100–0.150DCoplanarity includes exposed thermal pad and terminals Standard Branding Reference View Y = Last two digits of year of manufacture W = Week of manufacture L = Lot number N = Last two digits of device part numberYWW LLL NN1Package EL, 3-Contact DFN–0.15A Terminal #1 mark areaB Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion)For Reference Only, not for tooling use (reference DWG-2865; reference JEDEC MO-229UCCD)Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown C Reference land pattern layout (reference IPC7351);All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) Hall Element (not to scale)D Coplanarity includes exposed thermal pad and terminalsBranding scale and appearance at supplier discretionEF GActive Area Depth, 0.18 mm NOM分销商库存信息:ALLEGROA3212EELLT-T A3212ELHLT-T A3211EELLT-T A3211EEHLT-T A3211ELHLT-T A3212EUA-T A3212EEHLT-T A3212LLHLT-T A3212LUA-T A3212EEHLT A3212LLHLT A3212LUAA3211EUA-T。

AA3020MBC中文资料

Packdimensions are in millimeters (inches). 2. Tolerance is ±0.25(0.01") unless otherwise noted. 3.Specifications are subject to change without notice.
Description
The Blue source color devices are made with GaN on SiC Light Emitting Diode. Static electricity and surge damage the LEDS. It is recommended to use a wrist band or anti-electrostatic glove when handling the LEDs. All devices, equipment and machinery must be electrically grounded.
3.0MM X 2.0MM, 1.4MM HIGH, ONLY MINIMUM SPACE REQUIRED. SUITABLE FOR COMPACT OPTOELECTRONIC APPLICATIONS. LOW POWER CONSUMPTION. PACKAGE : 2000PCS / REEL. RoHS COMPLIANT.
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3.0x2.0mm SURFACE MOUNT LED LAMP
ATTENTION
OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC DISCHARGE SENSITIVE DEVICES
AA3020MBC

HB288320A6资料

3
HB2881000/800/640/448/320/256/192/160/128/096/064/032A6
Memory card mode Pin No. 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Signal name GND GND -CD1 D11 D12 D13 D14 D15 -CE2 -VS1 -IORD -IOWR — — — — — VCC — — — — -CSEL -VS2 RESET -WAIT -INPACK -REG BVD2 BVD1 D8 D9 D10 -CD2 GND I/O — — O I/O I/O I/O I/O I/O I O I I — — — — — — — — — — I O I O O I I/O I/O I/O I/O I/O O — I/O card mode Signal name GND GND -CD1 D11 D12 D13 D14 D15 -CE2 -VS1 -IORD -IOWR — — — — — VCC — — — — -CSEL -VS2 RESET -WAIT -INPACK -REG -SPKR -STSCHG D8 D9 D10 -CD2 GND I/O — — O I/O I/O I/O I/O I/O I O I I — — — — — — — — — — I O I O O I I/O I/O I/O I/O I/O O — True IDE mode Signal name GND GND -CD1 D11 D12 D13 D14 D15 -CE2 -VS1 -IORD -IOWR — — — — — VCC — — — — -CSEL -VS2 -RESET IORDY -INPACK -REG -DASP -PDIAG D8 D9 D10 -CD2 GND I/O — — O I/O I/O I/O I/O I/O I O I I — — — — — — — — — — I O I O O I I/O I/O I/O I/O I/O O —

1963696资料

Accessories Item Marking 0804853 SK 2,54/2,8:FORTL.ZAHLEN Marker card, printed horizontally, self-adhesive, 10-section marker strip, 14 identical decades marked 1-10, 11-20 etc. up to 91-100, sufficient for 140 terminal blocks Designation Description
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MC 0,5/ 7-G-2,5 THT R44 Order No.: 1963696
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Direction of the arrow = feeding direction
PHOENIX CONTACT GmbH & Co. KG http://www.phoenixcontact.de
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元器件交易网
MC 0,5/ 7-G-2,5 THT R44 Order No.: 1963696
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ExtracC 0,5/ 7-G-2,5 THT R44
Order No.: 1963696
http://eshop.phoenixcontact.de/phoenix/treeViewClick.do?UID=1963696