2928wifi规格书
MEMORY存储芯片MT29F4G08ABADAWP-ITD中文规格书
NAND Flash MemoryMT29F4G08ABADAH4, MT29F4G08ABADAWP, MT29F4G08ABBDAH4, MT29F4G08ABBDAHC, MT29F4G16ABADAH4, MT29F4G16ABADAWP, MT29F4G16ABBDAH4, MT29F4G16ABBDAHC, MT29F8G08ADADAH4,MT29F8G08ADBDAH4, MT29F8G16ADADAH4, MT29F8G16ADBDAH4, MT29F16G08AJADAWPFeatures•Open NAND Flash Interface (ONFI) 1.0-compliant1•Single-level cell (SLC) technology •Organization–Page size x8: 2112 bytes (2048 + 64 bytes)–Page size x16: 1056 words (1024 + 32 words)–Block size: 64 pages (128K + 4K bytes)–Plane size: 2 planes x 2048 blocks per plane–Device size: 4Gb: 4096 blocks; 8Gb: 8192 blocks 16Gb: 16,384 blocks•Asynchronous I/O performance–t RC/t WC: 20ns (3.3V), 25ns (1.8V)•Array performance–Read page: 25µs 3–Program page: 200µs (TYP: 1.8V, 3.3V)3–Erase block: 700µs (TYP)•Command set: ONFI NAND Flash Protocol •Advanced command set–Program page cache mode4–Read page cache mode 4–One-time programmable (OTP) mode–Two-plane commands 4–Interleaved die (LUN) operations–Read unique ID–Block lock (1.8V only)–Internal data move•Operation status byte provides software method for detecting–Operation completion–Pass/fail condition–Write-protect status•Ready/Busy# (R/B#) signal provides a hardware method of detecting operation completion•WP# signal: Write protect entire device •First block (block address 00h) is valid when ship-ped from factory with ECC. For minimum required ECC, see Error Management.•Block 0 requires 1-bit ECC if PROGRAM/ERASE cy-cles are less than 1000•RESET (FFh) required as first command after pow-er-on•Alternate method of device initialization (Nand_In-it) after power up (contact factory)•Internal data move operations supported within the plane from which data is read•Quality and reliability–Data retention: 10 years–Endurance: 100,000 PROGRAM/ERASE cycles •Operating voltage range–V CC: 2.7–3.6V–V CC: 1.7–1.95V•Operating temperature:–Commercial: 0°C to +70°C–Industrial (IT): –40ºC to +85ºC•Package–48-pin TSOP type 1, CPL2–63-ball VFBGANotes: 1.The ONFI 1.0 specification is available at2.CPL = Center parting line.3.See Program and Erase Characteristics fort R_ECC and t PROG_ECC specifications.4.These commands supported only with ECCdisabled.Figure 78: TWO-PLANE BLOCK ERASERE#CE#ALECLE I/Ox R/B#WE#Figure 79: TWO-PLANE/MULTIPLE-DIE READ STATUS CycleCE#CLE ALE RE#I/Ox4Gb, 8Gb, 16Gb: x8, x16 NAND Flash MemoryTwo-Plane OperationsInterleaved Die (Multi-LUN) OperationsIn devices that have more than one die (LUN) per target, it is possible to improve per-formance by interleaving operations between the die (LUNs). An interleaved die (multi-LUN) operation is one that is issued to an idle die (LUN) (RDY = 1) while another die (LUN) is busy (RDY = 0).Interleaved die (multi-LUN) operations are prohibited following RESET (FFh), identifi-cation (90h, ECh, EDh), and configuration (EEh, EFh) operations until ARDY =1 for all of the die (LUNs) on the target.During an interleaved die (multi-LUN) operation, there are two methods to determine operation completion. The R/B# signal indicates when all of the die (LUNs) have finish-ed their operations. R/B# remains LOW while any die (LUN) is busy. When R/B# goes HIGH, all of the die (LUNs) are idle and the operations are complete. Alternatively, the READ STATUS ENHANCED (78h) command can report the status of each die (LUN) in-dividually.If a die (LUN) is performing a cache operation, like PROGRAM PAGE CACHE (80h-15h),then the die (LUN) is able to accept the data for another cache operation when status register bit 6 is 1. All operations, including cache operations, are complete on a die when status register bit 5 is 1.During and following interleaved die (multi-LUN) operations, the READ STATUS (70h)command is prohibited. Instead, use the READ STATUS ENHANCED (78h) command to monitor status. This command selects which die (LUN) will report status. When two-plane commands are used with interleaved die (multi-LUN) operations, the two-plane commands must also meet the requirements in Two-Plane Operations.See Command Definitions for the list of commands that can be issued while other die (LUNs) are busy.During an interleaved die (multi-LUN) operation that involves a PROGRAM series (80h-10h, 80h-15h) operation and a READ operation, the PROGRAM series operation must be issued before the READ series operation. The data from the READ series opera-tion must be output to the host before the next PROGRAM series operation is issued.This is because the 80h command clears the cache register contents of all cache regis-ters on all planes.4Gb, 8Gb, 16Gb: x8, x16 NAND Flash MemoryInterleaved Die (Multi-LUN) OperationsError ManagementEach NAND Flash die (LUN) is specified to have a minimum number of valid blocks(NVB) of the total available blocks. This means the die (LUNs) could have blocks thatare invalid when shipped from the factory. An invalid block is one that contains at leastone page that has more bad bits than can be corrected by the minimum required ECC.Additional blocks can develop with use. However, the total number of available blocksper die (LUN) will not fall below NVB during the endurance life of the product.Although NAND Flash memory devices could contain bad blocks, they can be usedquite reliably in systems that provide bad block management and error-correction algo-rithms. This type of software environment ensures data integrity.Internal circuitry isolates each block from other blocks, so the presence of a bad blockdoes not affect the operation of the rest of the NAND Flash array.NAND Flash devices are shipped from the factory erased. The factory identifies invalidblocks before shipping by attempting to program the bad block mark into every loca-tion in the first page of each invalid block. It may not be possible to program every loca-tion with the bad block mark. However, the first spare area location in each bad block isguaranteed to contain the bad block mark. This method is compliant with ONFI FactoryDefect Mapping requirements. See the following table for the first spare area locationand the bad block mark.System software should check the first spare area location on the first page of eachblock prior to performing any PROGRAM or ERASE operations on the NAND Flash de-vice. A bad block table can then be created, enabling system software to map aroundthese areas. Factory testing is performed under worst-case conditions. Because invalidblocks could be marginal, it may not be possible to recover this information if the blockis erased.Over time, some memory locations may fail to program or erase properly. In order toensure that data is stored properly over the life of the NAND Flash device, the followingprecautions are required:•Always check status after a PROGRAM or ERASE operation•Under typical conditions, use the minimum required ECC (see table below)•Use bad block management and wear-leveling algorithmsThe first block (physical block address 00h) for each CE# is guaranteed to be validwith ECC when shipped from the factory.Table 21: Error Management DetailsTable 21: Error Management Details (Continued)。
3028技术参数
固定端口 管理端口24 个 10/100Base-T 以太网端口 4 个 1000Base-X SFP 端口 1 个 Console 口 AC 电源电源额定电压范围:120V~240V ;50/60Hz 额定电压范围:100V~265V ;50/60Hz最大功耗 体系结构 交换容量 包转发率 交换模式 广播控制22W 基于高性能 ASIC 芯片技术 12.8Gbps 9.6Mpps 存储转发(Store and Forward) 支持抑制广播风暴,达到临界点时即停止发送 支持 IEEE802.3x 流控(全双工)端口特性基于端口速率百分比的广播, DLF , 组播风暴抑制 基于端口 pps 的广播风暴抑制 ; 支持 8KMAC 地址表容量MAC 地址支持 MAC 地址过滤 支持手工配置老化时间 支持静态 MAC 地址配置 支持手工聚合 支持基于源 MAC/目的 MAC 负载均衡端口汇聚支持静态/动态 LACP 最大支持 4 个聚合组 FE 汇聚组最大支持 8 个 FE 接口 支持基于端口的 VLAN(4K 个)VLAN 特性三层 VLAN 数量 1 个 支持 VLAN 过滤 支持 PVLAN DHCP ServerDHCPDHCP Snooping DHCP Relay 支持无状态地址自动配置 支持重复地址检测 (DAD)IPv6 协议支持邻居发现 (ND) 支持 ICMPv6 支持路由器发现生成树协议 组播支持 STP,RSTP,MSTP 支持 IGMP Snooping,MLD snooping, 支持未知组播丢弃功能 支持 N:1 端口镜像 支持数据流镜像镜像支持本地端口镜像(LSPAN) 支持基于 VLAN、ACL、端口的镜像(LSPAN) 支持远程端口镜像(RSPAN)支持 rate-limit 对物理接口 output 双向方向限速 支持基于源 MAC 地址、目的 MAC 地址、源 IP 地址、目的 IP 地址和源端口、目的端口的分流 支持基于协议号、802.1p、IP Precedence、DSCP Input interface 的分流 支持 TOS/DSCP 标记 支持报文的 802.1p、IP Precedence、DSCP 重新标记 支持 CAR 限速 QoS 支持报文重定向 支持基于 Police 的限速 支持基于 CLASS-MAP 的限速 支持流量整形 每端口的输出队列数量最大 8 个 支持丰富的端口队列调度模式 支持基于源 MAC 地址、目的 MAC 地址 ACL 支持基于源 IP 地址、目的 IP 地址 ACL 支持基于源端口、目的端口 ACL 支持基于协议号 ACL 支持基于 VLAN 的 ACL ACL 支持基于时间段(Time Range)的 ACL 支持基于支持非法帧过滤 支持在 Ingress 方向和 Egress 方向的 ACL 加载 支持基于 VLAN 加载 ACL 支持基于 Switch port 加载 ACL 用户分级管理和口令保护 SSH2.0 支持 IEEE802.1x 认证,在未认证前可访问指定的网络 支持 MAC 自动学习绑定并可手动设置端口 MAC 学习绑定的个数 支持动态 arp 检测(DAI: Dynamic ARP Inspection),Dhcp 报文检测,Nd 报文检测 基于 DHCP-Snooping 的 ARP 攻击防御 Dhcpv6 报文检测 支持 TCP 并发连接数限制(CP) 安全特性 MAC+IP+PORT 绑定(自动/手动) MAC+IP+PORT+VLAN 绑定(自动/手动) 支持 IEEE 802.1X 认证、AAA 认证、Radius 认证 支持 TCP SYN Flood 攻击防御 支持授权用户 telnet 登录管理 支持端口隔离 支持定向广播转发抑制功能 支持带源路由选项报文转发抑制功能 支持 MSTP BPDU Guard、Loop Guard、Root Guard、PBDU Skewing 功能 支持 WindROSE 图形化网管系统 支持 FTP/ TFTP 加载升级和 Xmodem 加载升级 管理与维护 支持命令行接口(CLI),Telnet,Console 口配置 RMON 网管 支持网络诊断命令:PING、 支持 SNMP v1/v2、SNMP v3 支持 NTP 客户端和服务器端支持 NTP 协议 支持 RMON (Remote Monitoring)1,2,3,9 组 MIB 本地 SYSlog:系统日志,分级告警,调试配置信息输出 远程 SYSlog:系统日志,分级告警,调试配置信息输出电源 功耗 液晶面板 液晶板尺寸 显示方式 显示器像素 镜头100-240V 交流电,50/60Hz 365W(节能待机模式 下为 0.3W,普通待机模式下为 11.5W)*116.0mm(0.63 英寸)对角线(4:3 宽高比) 透射式液晶面板(×3, R/G/B) 786,432(1,024x768)x 3, 共计 2,359,296 像素 手动 1.6 倍变焦(1.18-1.90:1), 手动对焦 F 1.60–2.12, f 15.30–24.64mm灯泡280W x 1, 灯泡更换周期(灯泡功率:普通/节能模式):2,500 小时/4.000 小时*2投影画面尺寸(对 0.76-7.62m(30-300 英寸),4:3 宽高比 角线) 亮度*35,000 流明(灯泡功率:普通模式)*3均匀性 对比度 分辨率85% 4,000:1(全开/全关,灯泡功率:自动模式,lris:开) 1,024×768 像素*4*3扫描频率 HDMI RGB(模拟) fH: 25-80 kHz,fV: 50-85 Hz,点时钟:162 MHz 或更低 fH: 15-100 kHz, fV: 50-100 Hz, 点时钟:140 MHz 或更低 (信号超出 140 MHz 点时钟率时重采样) YPBPR(YCBCR) fH: 15.75 kHz, fV: 60 Hz [480i(525i)] fH: 15.63 kHz, fV: 50 Hz [576i(625i)] fH: 31.50 kHz, fV: 60 Hz [480p(525p)] fH: 31.25 kHz, fV: 50 Hz [576p(625p)] fH: 45.00 kHz, fV: 60 Hz [720(750)/60p] fH: 37.50 kHz, fV: 50 Hz [720(750)/50p] fH: 33.75 kHz, fV: 60 Hz [1080(1125)/60i] fH: 28.13 kHz, fV: 50 Hz [1080(1125)/50i] 视频/S-视频 fH: 15.75 kHz,fV: 60 Hz [NTSC/NTSC4.43/PAL-M/PAL60], fH: 15.63 kHz, fV: 50 Hz [PAL/PAL-N/SECAM] 光轴移动范围 梯形校正范围(约) 安装方式 终端接口 HDMI 输入 HDMI 19-pin × 1(兼容 HDCP) 480p, 576p, 720/60p, 720/50p, 1080/60i, 1080/50i, 1080/60p, 1080/50p, VGA (640 x 480)-WUXGA (1,920 x 1,200)*5, 只与逐行信号兼容, 点时钟: 25 -146.25 MHz 电脑 1 输入 D-Sub HD 15-pin(雌头) × 1(RGB/YPBPR/YCBCR × 1) 垂直:+40% 垂直:± (梯形校正范围内为± ) 30° 20° 吊装/平放,正投/背投电脑 2 输入/输出 D-Sub HD 15-pin(雌头) × 1(RGB × 1)(使用屏幕上的菜单选择输入/输出) (当电脑 2 选择监控器输出时, 输出的信号是电脑 1 输入的信号) 视频输入 S-视频输入 音频输入 RCA × 1(复合视频) Mini DIN 4-pin × 1(S-视频) RCA pin x 2(L-R x 1)用于视频/S-视频输入电脑音频输入 1 M3(L, R) × 1 电脑音频输入 2 M3(L, R) × 1, 为音频输入或麦克风连接用(可变) (麦克风输入) 音频输出 串行输入 局域网 内置扬声器 噪音水平 机身材料 尺寸(宽×高×长) 重量 运行环境 随机附件 M3 x 1(L-R x 1) 为输出用(可变) D-sub 9-pin(雌头) × 1, 用于外部控制(与 RS-232C 相容) RJ-45x1(网络连接用, 10Base-T/100Base-TX, 适用于 PJ Link ) 4 cm 圆形 x 1, 输出功率: 10W(单声道) 37dB(灯泡功率: 普通模式), 29dB(灯泡功率: 节能模式) 树脂成型品 379x107x305mm(含支撑脚最短, 不包含凸出部分) 约 4.8 kg 运行温度: 0° C–40° C*6, 运行湿度: 20%-80%(无结霜) 电源线 x 1, 电源线固定支架 x 1, 无线遥控器, 遥控器电池(AAA/R03/LR03 type x 2), 携带软包 x 1,RGB 电缆(1.8 m, 用于 VGA) x 1, 软件 CD-ROM(Logo 传送软件, 多台投影机监控软件)TM产品型号 单元组成 额定阻抗 额定功率 最大功率 频响范围 灵敏度 净重 毛重OT55 5 " x 5 80 hms 250 W 450 W 100 Hz - 150 KHz 92 dB±3dB 8 kg / pair 10 kg / pair基本规格产品类型:超 5 类双绞线网络 产品适用:布线网络 最大单段长度:100 米 纠错 传输速率:1000Mbps 包装长度:305 米外观参数 产品特性 产品特性 1:提供基于 100MHZ 带宽环境下的数据传输支持 Ethernet 和快速 Ethern 622Mbps 的 ATM. 符合 CSA,ETL,经 UL 认证主要规格 类型:网络服务器机柜 容量:42U标准:符合 ANSI/EIA RS-310-D、IEC297-2、DIN41491;PART1、DIN41494;P GB/T3047.2-92 标准;兼容 ETSI 标准门及门锁:高通风率六角弧形网孔前门(专利)、双开六角网孔后门及三段侧门;月光 门锁 纠错材料及工艺:SPCC 优质冷扎钢板制作;厚度:方孔条 2.0mm,托盘 2.0mm,安装 其他 1.2mm;表面处理:脱脂、酸洗、磷化、静电喷塑附加功能:外观高贵典雅,工艺精湛、尺寸精密,媲美国际最高档网络服务器机柜, 机房工程形象;可方便地安装图腾机柜集中配电单元(专利)外观参数 高度:1999mm 宽度:600mm 深度:1000mm型号 产品类型 线材 干扰功能 主要参数超 5 类 24 口配线架(0-0406330-1)有奖找错 线架 超5类 非屏蔽型 非屏蔽超 5 类 24 口配线架基本参数 固定端口 管理端口 电源 最大功耗 体系结构 交换容量 包转发率 交换模式 广播控制 端口特性 24 个 10/100Base-T 以太网端口 4 个 1000Base-X SFP 端口 1 个 Console 口 AC 电源 额定电压范围:120V~240V ;50/60Hz 额定电压范围:100V~265V ;50/60Hz 22W 基于高性能 ASIC 芯片技术 12.8Gbps 9.6Mpps 存储转发(Store and Forward) 支持抑制广播风暴,达到临界点时即停止发送 支持 IEEE802.3x 流控(全双工) 基于端口速率百分比的广播, DLF , 组播风暴抑制 基于端口 pps 的广播风暴抑制 ; 支持 8KMAC 地址表容量 支持 MAC 地址过滤 支持手工配置老化时间 支持静态 MAC 地址配置 支持手工聚合 支持基于源 MAC/目的 MAC 负载均衡 支持静态/动态 LACP 最大支持 4 个聚合组 FE 汇聚组最大支持 8 个 FE 接口 支持基于端口的 VLAN(4K 个) 三层 VLAN 数量 1 个 支持 VLAN 过滤 支持 PVLAN DHCP Server DHCP Snooping DHCP Relay 支持无状态地址自动配置 支持重复地址检测 (DAD) 支持邻居发现 (ND) 支持 ICMPv6 支持路由器发现 支持 IGMP Snooping,MLD snooping, 支持未知组播丢弃功能 支持 N:1 端口镜像 支持数据流镜像 支持本地端口镜像(LSPAN) 支持基于 VLAN、ACL、端口的镜像(LSPAN)MAC 地址端口汇聚VLAN 特性DHCPIPv6 协议生成树协议 支持 STP,RSTP,MSTP 组播镜像支持远程端口镜像(RSPAN) 支持 rate-limit 对物理接口 output 双向方向限速 支持基于源 MAC 地址、目的 MAC 地址、源 IP 地址、目的 IP 地址和源端口、 目的端口的分流 支持基于协议号、802.1p、IP Precedence、DSCP Input interface 的分流 支持 TOS/DSCP 标记 支持报文的 802.1p、IP Precedence、DSCP 重新标记 支持 CAR 限速 支持报文重定向 支持基于 Police 的限速 支持基于 CLASS-MAP 的限速 支持流量整形 每端口的输出队列数量最大 8 个 支持丰富的端口队列调度模式 支持基于源 MAC 地址、目的 MAC 地址 ACL 支持基于源 IP 地址、目的 IP 地址 ACL 支持基于源端口、目的端口 ACL 支持基于协议号 ACL 支持基于 VLAN 的 ACL 支持基于时间段(Time Range)的 ACL 支持基于支持非法帧过滤 支持在 Ingress 方向和 Egress 方向的 ACL 加载 支持基于 VLAN 加载 ACL 支持基于 Switch port 加载 ACL 用户分级管理和口令保护 SSH2.0 支持 IEEE802.1x 认证,在未认证前可访问指定的网络 支持 MAC 自动学习绑定并可手动设置端口 MAC 学习绑定的个数 支持动态 arp 检测(DAI: Dynamic ARP Inspection),Dhcp 报文检测,Nd 报 文检测 基于 DHCP-Snooping 的 ARP 攻击防御 Dhcpv6 报文检测 支持 TCP 并发连接数限制(CP) MAC+IP+PORT 绑定(自动/手动) MAC+IP+PORT+VLAN 绑定(自动/手动) 支持 IEEE 802.1X 认证、AAA 认证、Radius 认证 支持 TCP SYN Flood 攻击防御 支持授权用户 telnet 登录管理 支持端口隔离 支持定向广播转发抑制功能 支持带源路由选项报文转发抑制功能 支持 MSTP BPDU Guard、Loop Guard、Root Guard、PBDU Skewing 功能QoSACL安全特性支持 WindROSE 图形化网管系统 管理与维护 支持 FTP/ TFTP 加载升级和 Xmodem 加载升级 支持命令行接口(CLI),Telnet,Console 口配置 RMON 网管支持网络诊断命令:PING、 支持 SNMP v1/v2、SNMP v3 支持 NTP 客户端和服务器端 支持 NTP 协议 支持 RMON (Remote Monitoring)1,2,3,9 组 MIB 本地 SYSlog:系统日志,分级告警,调试配置信息输出 远程 SYSlog:系统日志,分级告警,调试配置信息输出基本参数 电源 功耗 液晶板尺寸 显示方式 显示器像素 镜头 100-240V 交流电,50/60Hz 365W(节能待机模式 下为 0.3W,普通待机模式下为 11.5W) 16.0mm(0.63 英寸)对角线(4:3 宽高比) 透射式液晶面板(×3, R/G/B) 786,432(1,024x768)x 3, 共计 2,359,296 像素 手动 1.6 倍变焦(1.18-1.90:1), 手动对焦 F 1.60–2.12, f 15.30–24.64mm 280W x 1, 灯泡更换周期(灯泡功率:普通/节能模式):2,500 小时/4.000 小时 0.76-7.62m(30-300 英寸),4:3 宽高比 5,000 流明(灯泡功率:普通模式)*3 *2 *1灯泡 投影画面尺寸 亮度*3均匀性 对比度 分辨率85% 4,000:1(全开/全关,灯泡功率:自动模式,lris:开) 1,024×768 像素*4 fH: 25-80 kHz,fV: 50-85 Hz,点时钟:162 MHz 或更低 fH: 15-100 kHz, fV: 50-100 Hz, 点时钟:140 MHz 或更低 (信号超出 140 MHz 点时钟率时重采样) fH: 15.75 kHz, fV: 60 Hz [480i(525i)] fH: 15.63 kHz, fV: 50 Hz [576i(625i)]*3HDMI RGB(模拟)YPBPR(YCBCR)fH: 31.50 kHz, fV: 60 Hz [480p(525p)] fH: 31.25 kHz, fV: 50 Hz [576p(625p)] fH: 45.00 kHz, fV: 60 Hz [720(750)/60p] fH: 37.50 kHz, fV: 50 Hz [720(750)/50p] fH: 33.75 kHz, fV: 60 Hz [1080(1125)/60i] fH: 28.13 kHz, fV: 50 Hz [1080(1125)/50i]视频/S-视频 光轴移动范围 梯形校正范围(约) 安装方式 终端接口 HDMI 输入fH: 15.75 kHz,fV: 60 Hz [NTSC/NTSC4.43/PAL-M/PAL60], fH: 15.63 kHz, fV: 50 Hz [PAL/PAL-N/SECAM] 垂直:+40% 垂直:± (梯形校正范围内为± ) 30° 20° 吊装/平放,正投/背投HDMI 19-pin × 1(兼容 HDCP)480p, 576p, 720/60p, 720/50p, 1080/60i, 1080/50i, 1080/60p, 1080/50p, VGA (640 x 480)-WUXGA (1,920 x 1,200)*5, 只与逐行信号兼容, 点时钟: 25 -146.25 MHz 电脑 1 输入 电脑 2 输入/输出 视频输入 S-视频输入 音频输入 电脑音频输入 1 电脑音频输入 2 (麦克风输入) 音频输出 串行输入 局域网 内置扬声器 噪音水平 机身材料 尺寸(宽×高×长) 重量 运行环境 D-Sub HD 15-pin(雌头) × 1(RGB/YPBPR/YCBCR × 1) D-Sub HD 15-pin(雌头) × 1(RGB × 1)(使用屏幕上的菜单选择输入/输出) (当电脑 2 选择监控器输出时, 输出的信号是电脑 1 输入的信号) RCA × 1(复合视频) Mini DIN 4-pin × 1(S-视频) RCA pin x 2(L-R x 1)用于视频/S-视频输入 M3(L, R) × 1 M3(L, R) × 1, 为音频输入或麦克风连接用(可变) M3 x 1(L-R x 1) 为输出用(可变) D-sub 9-pin(雌头) × 1, 用于外部控制(与 RS-232C 相容) RJ-45x1(网络连接用, 10Base-T/100Base-TX, 适用于 PJ Link ) 4 cm 圆形 x 1, 输出功率: 10W(单声道) 37dB(灯泡功率: 普通模式), 29dB(灯泡功率: 节能模式) 树脂成型品 379x107x305mm(含支撑脚最短, 不包含凸出部分) 约 4.8 kg 运行温度: 0° C–40° C*6, 运行湿度: 20%-80%(无结霜) 电源线 x 1, 电源线固定支架 x 1, 无线遥控器, 遥控器电池(AAA/R03/LR03 type x 随机附件 2), 携带软包 x 1,RGB 电缆(1.8 m, 用于 VGA) x 1, 软件 CD-ROM(Logo 传送软件, 多 台投影机监控软件) 基本参数 单元组成 额定阻抗 额定功率 最大功率 频响范围 灵敏度 净重 5 " x 5 80 hms 150 W 350 W 100 Hz - 150 KHz 92 dB±3dB 8 kg / pairTM。
2928系列教育专用交换机
产品简介Cisco ® Catalyst ® 2928系列教育专用交换机Cisco ® Catalyst ® 2928系列交换机,是为中国校园网络定制的高安全和高性价比的二层百兆接入交换机。
该系列采用以太网供电 (Power Over Ethernet – PoE) 或非PoE 配置,可提供桌面快速以太网连接,可为校园网接入提供统一的有线和无线安全解决方案。
Catalyst 2928系列采用先进的硬件和软件技术,并结合第三方的认证管理系统,实现基于身份的网络部署,大幅度提高校园网络的安全。
简单易行的认证模式,自由定制化的认证界面,高度集成的安全特性,性能卓越的系统硬件,稳定可靠的软件和高性价比,这些都将使Catalyst 2928成为校园网接入交换机的理想选择。
Cisco Catalyst 2928软件镜像是一组丰富的智能服务,包括高级认证 、ACL 和IPv4管理。
基于SFP 的千兆以太网端口可兼容多种不同的SFP 模块。
以下是Catalyst 2928 各种型号Catalyst 2928系列交换机所能提供给校园网用户的主要特点:• 有线无线统一解决方案在统一的上层管理软件平台上,有线与无线进行一致的认证,结合第三方的软件实现完整的安 全解决方案• 强大的安全特性可实现用户特征的7元素组合绑定,最大限度的保证网络的接入侧安全一键式安全开启实现ARP 防御,DHCP 欺骗,端口安全等安全防御策略 • 创新的认证方式基于WEB 的终端认证模式,实现跨平台跨浏览器的接入认证,同时提供可定制化的认证界面,保证信息的准确传递 • 中国化的产品专为中国教育行业定制的交换机,无论是面板还是管理界面都采用中文描述,大大缩短用户用户熟悉设备的时间有线无线统一的安全解决方案该方案使用catalyst 2928交换机的独特特性再加上第三方的上层管理软件将为安全校园网的建设提供安全,可靠,易用的整体解决方案。
MEMORY存储芯片MT29F8G08ABABAWP-ITB中文规格书
Status OperationsEach die (LUN) provides its status independently of other die (LUNs) on the same targetthrough its 8-bit status register.After the READ STATUS (70h) or READ STATUS ENHANCED (78h) command is issued,status register output is enabled. The contents of the status register are returned on I/O[7:0] for each data output request.When the asynchronous interface is active and status register output is enabled,changes in the status register are seen on I/O[7:0] as long as CE# and RE# are LOW; it isnot necessary to toggle RE# to see the status register update.While monitoring the status register to determine when a data transfer from the Flasharray to the data register (t R) is complete, the host must issue the READ MODE (00h)command to disable the status register and enable data output (see Read Operations).The READ STATUS (70h) command returns the status of the most recently selected die(LUN). To prevent data contention during or following an interleaved die (multi-LUN)operation, the host must enable only one die (LUN) for status output by using the READSTATUS ENHANCED (78h) command (see Interleaved Die (Multi-LUN) Operations).With internal ECC enabled, a READ STATUS command is required after completion ofthe data transfer (t R_ECC) to determine whether an uncorrectable read error occurred. Table 18: Status Register DefinitionNotes: 1.Status register bit 6 is 1 when the cache is ready to accept new data. R/B# follows bit 6.Read OperationsThe READ PAGE (00h-30h) command, when issued by itself, reads one page from theNAND Flash array to its cache register and enables data output for that cache register.During data output the following commands can be used to read and modify the data inthe cache registers: RANDOM DATA READ (05h-E0h) and RANDOM DATA INPUT (85h).Read Cache OperationsTo increase data throughput, the READ PAGE CACHE series (31h, 00h-31h) commandscan be used to output data from the cache register while concurrently copying a pagefrom the NAND Flash array to the data register.To begin a read page cache sequence, begin by reading a page from the NAND Flash ar-ray to its corresponding cache register using the READ PAGE (00h-30h) command.R/B# goes LOW during t R and the selected die (LUN) is busy (RDY = 0, ARDY = 0). Aftert R (R/B# is HIGH and RDY = 1, ARDY = 1), issue either of these commands:•READ PAGE CACHE SEQUENTIAL (31h) – copies the next sequential page from theNAND Flash array to the data register•READ PAGE CACHE RANDOM (00h-31h) – copies the page specified in this commandfrom the NAND Flash array to its corresponding data registerAfter the READ PAGE CACHE series (31h, 00h-31h) command has been issued, R/B#goes LOW on the target, and RDY = 0 and ARDY = 0 on the die (LUN) for t RCBSY whilethe next page begins copying data from the array to the data register. After t RCBSY,R/B# goes HIGH and the die’s (LUN’s) status register bits indicate the device is busywith a cache operation (RDY = 1, ARDY = 0). The cache register becomes available andthe page requested in the READ PAGE CACHE operation is transferred to the data regis-ter. At this point, data can be output from the cache register, beginning at column ad-dress 0. The RANDOM DATA READ (05h-E0h) command can be used to change the col-umn address of the data output by the die (LUN).After outputting the desired number of bytes from the cache register, either an addi-tional READ PAGE CACHE series (31h, 00h-31h) operation can be started or the READPAGE CACHE LAST (3Fh) command can be issued.If the READ PAGE CACHE LAST (3Fh) command is issued, R/B# goes LOW on the target,and RDY = 0 and ARDY = 0 on the die (LUN) for t RCBSY while the data register is copiedinto the cache register. After t RCBSY, R/B# goes HIGH and RDY = 1 andARDY = 1, indicating that the cache register is available and that the die (LUN) is ready.Data can then be output from the cache register, beginning at column address 0. TheRANDOM DATA READ (05h-E0h) command can be used to change the column addressof the data being output.For READ PAGE CACHE series (31h, 00h-31h, 3Fh), during the die (LUN) busy time,t RCBSY, when RDY = 0 and ARDY = 0, the only valid commands are status operations(70h, 78h) and RESET (FFh). When RDY = 1 and ARDY = 0, the only valid commandsduring READ PAGE CACHE series (31h, 00h-31h) operations are status operations (70h,78h), READ MODE (00h), READ PAGE CACHE series (31h, 00h-31h), RANDOM DATAREAD (05h-E0h), and RESET (FFh).Two-Plane Read OperationsTwo-plane read page operations improve data throughput by copying data from more than one plane simultaneously to the specified cache registers. This is done by pre-pending one or more READ PAGE TWO-PLANE (00h-00h-30h) commands in front of the READ PAGE (00h-30h) command.When the die (LUN) is ready, the RANDOM DATA READ TWO-PLANE (06h-E0h) com-mand determines which plane outputs data. During data output, the following com-mands can be used to read and modify the data in the cache registers: RANDOM DATA READ (05h-E0h) and RANDOM DATA INPUT (85h).Two-Plane Read Cache OperationsTwo-plane read cache operations can be used to output data from more than one cache register while concurrently copying one or more pages from the NAND Flash array to the data register. This is done by prepending READ PAGE TWO-PLANE (00h-00h-30h) commands in front of the PAGE READ CACHE RANDOM (00h-31h) command.To begin a two-plane read page cache sequence, begin by issuing a READ PAGE TWO-PLANE operation using the READ PAGE TWO-PLANE (00h-00h-30h) and READ PAGE (00h-30h) commands. R/B# goes LOW during t R and the selected die (LUN) is busy (RDY = 0, ARDY = 0). After t R (R/B# is HIGH and RDY = 1, ARDY = 1), issue either of these commands:•READ PAGE CACHE SEQUENTIAL (31h) – copies the next sequential pages from the previously addressed planes from the NAND Flash array to the data registers.•READ PAGE TWO-PLANE (00h-00h-30h) [in some cases, followed by READ PAGE CACHE RANDOM (00h-31h)] – copies the pages specified from the NAND Flash array to the corresponding data registers.After the READ PAGE CACHE series (31h, 00h-31h) command has been issued, R/B# goes LOW on the target, and RDY = 0 and ARDY = 0 on the die (LUN) for t RCBSY while the next pages begin copying data from the array to the data registers. After t RCBSY,R/B# goes HIGH and the LUN’s status register bits indicate the device is busy with a cache operation (RDY = 1, ARDY = 0). The cache registers become available and the pa-ges requested in the READ PAGE CACHE operation are transferred to the data registers. Issue the RANDOM DATA READ TWO-PLANE (06h-E0h) command to determine which cache register will output data. After data is output, the RANDOM DATA READ TWO-PLANE (06h-E0h) command can be used to output data from other cache registers. Af-ter a cache register has been selected, the RANDOM DATA READ (05h-E0h) command can be used to change the column address of the data output.After outputting data from the cache registers, either an additional TWO-PLANE READ CACHE series (31h, 00h-31h) operation can be started or the READ PAGE CACHE LAST (3Fh) command can be issued.If the READ PAGE CACHE LAST (3Fh) command is issued, R/B# goes LOW on the target, and RDY = 0 and ARDY = 0 on the die (LUN) for t RCBSY while the data registers are cop-ied into the cache registers. After t RCBSY, R/B# goes HIGH and RDY = 1 and ARDY = 1, indicating that the cache registers are available and that the die (LUN) is ready. Issue the RANDOM DATA READ TWO-PLANE (06h-E0h) command to determine which cache register will output data. After data is output, the RANDOM DATA READ TWO-PLANE (06h-E0h) command can be used to output data from other cache registers. After a cache register has been selected, the RANDOM DATA READ (05h-E0h) command can be used to change the column address of the data output.output begins at the column address last specified in the READ PAGE (00h-30h) com-mand. The RANDOM DATA READ TWO-PLANE (06h-E0h) command is used to enabledata output in the other cache registers.Figure 38: READ PAGE (00h-30h) OperationCycle typeI/O[7:0]RDYFigure 39: READ PAGE (00h-30h) Operation with Internal ECC EnabledRDYSR bit 1 = 0 READ errorREAD PAGE CACHE SEQUENTIAL (31h)The READ PAGE CACHE SEQUENTIAL (31h) command reads the next sequential pagewithin a block into the data register while the previous page is output from the cacheregister. This command is accepted by the die (LUN) when it is ready(RDY = 1, ARDY = 1). It is also accepted by the die (LUN) during READ PAGE CACHE(31h, 00h-31h) operations (RDY = 1 and ARDY = 0).To issue this command, write 31h to the command register. After this command is is-sued, R/B# goes LOW and the die (LUN) is busy (RDY = 0, ARDY = 0) for t RCBSY. Aftert RCBSY, R/B# goes HIGH and the die (LUN) is busy with a cache operation(RDY = 1, ARDY = 0), indicating that the cache register is available and that the specifiedpage is copying from the NAND Flash array to the data register. At this point, data canbe output from the cache register beginning at column address 0. The RANDOM DATAREAD (05h-E0h) command can be used to change the column address of the data beingoutput from the cache register.The READ PAGE CACHE SEQUENTIAL (31h) command can be used to cross blockboundaries. If the READ PAGE CACHE SEQUENTIAL (31h) command is issued after thelast page of a block is read into the data register, the next page read will be the next logi-cal block in which the 31h command was issued. Do not issue the READ PAGE CACHESEQUENTIAL (31h) to cross die (LUN) boundaries. Instead, issue the READ PAGECACHE LAST (3Fh) command.。
RG-S2928G-S安全智能千兆交换机产品(V1.2)
RG-S2928G-S安全智能千兆交换机产品V1.2目录1产品概述 (1)2产品特性 (2)3技术参数 (4)4典型应用 (6)5订购信息 (7)1 产品概述RG-S2928G-S交换机产品,是锐捷网络基于网络安全和易用好管理的理念推出的新一代安全智能交换机,充分融合了网络发展需要的高性能、高安全、多业务、易用性特点,为用户提供全新的技术特性和解决方案。
RG-S2928G-S不但提供诸如防ARP欺骗、防网络攻击、防非法DHCP、防网络环路等各项安全功能,同时更提供简单易用的WEB管理界面,在保有复杂安全技术的同时,提供简单易用的用户体验。
RG-S2928G-S采用绿色节能的无风扇设计,不但提供全静音的用户体验,更是完全消除了风扇带来设备故障,极大提高了设备的稳定性和使用寿命。
2 产品特性全面的安全控制策略●硬件实现端口与MAC地址和用户IP地址的灵活绑定,严格限定端口上的用户接入;●通过将端口设为保护端口即可简单方便地隔离用户之间信息互通,保障了信息安全,同时不必占用VLAN资源;●专用的硬件防范ARP网关和ARP主机欺骗功能,有效遏制了网络中日益泛滥的ARP网关欺骗和ARP主机欺骗的现象,保障了用户的正常上网;●支持DHCP snooping,可只允许信任端口的DHCP响应,防止未经管理员许可私自架设DHCP Server,扰乱IP地址的分配和管理,影响用户的正常上网;并在DHCP监听的基础上,通过动态监测ARP和检查源IP,可有效防范DHCP动态分配IP环境下的ARP主机欺骗和源IP地址的欺骗;●基于源IP地址控制的Telnet和Web设备访问控制,增强了设备网管的安全性,避免黑客恶意攻击和控制设备;●SSH(Secure Shell)和SNMPv3可以通过在Telnet和SNMP进程中加密管理信息,保证管理设备信息的安全性,防止黑客攻击和控制设备,保护网络免遭干扰和窃听;●通过内在的多种安全机制可有效防止和控制病毒传播和网络流量攻击,控制非法用户使用网络,保证合法用户合理化使用网络,如端口静态和动态的安全绑定、端口隔离、多种类型的硬件ACL控制、基于数据流的带宽限速、用户安全接入控制的多元素绑定等,满足企业网、校园网加强对访问者进行控制、限制非授权用户通信的需求。
MEMORY存储芯片MT29F128G08CFABAWP_B中文规格书
READ LOCK REGISTERThe device is first selected by driving chip select (S#) LOW. The command code for theREAD LOCK REGISTER command is followed by a 3-byte address (A23-A0) pointing toany location inside the concerned sector (or subsector). Each address bit is latched-induring the rising edge of serial clock (C). Then the value of the lock register is shiftedout on serial data output (DQ1), each bit being shifted out at a maximum frequency f C during the falling edge of C.The READ LOCK REGISTER command is terminated by driving S# HIGH at any timeduring data output.Figure 17: READ LOCK REGISTER Command SequenceDQ[0]CDQ1Don’t CareAny READ LOCK REGISTER command issued while an ERASE, PROGRAM, or WRITEcycle is in progress is rejected without any effect on the cycle that is in progress.Values of b1 and b0 after power-up are defined in the table below.Table 14: Lock Register OutPAGE ERASEThe PAGE ERASE command sets to 1 (FFh) all bits inside the chosen page. Before thePAGE ERASE command can be accepted, a WRITE ENABLE command must have beenexecuted previously. After the WRITE ENABLE command has been decoded, the devicesets the write enable latch (WEL) bit.The PAGE ERASE command is entered by driving chip select (S#) LOW, followed by thecommand code, and three address bytes on serial data input (DQ0). Any address insidethe sector is a valid address for the PAGE ERASE command. S# must be driven LOW forthe entire duration of the sequence.S# must be driven HIGH after the eighth bit of the last address byte has been latched in.Otherwise the PAGE ERASE command is not executed. As soon as S# is driven HIGH,the self-timed PAGE ERASE cycle is initiated; the cycle's duration is t PE. While the PAGEERASE cycle is in progress, the status register may be read to check the value of the writein progress (WIP) bit. The WIP bit is 1 during the self-timed PAGE ERASE cycle, and is 0when the cycle is completed. At some unspecified time before the cycle is completed,the WEL bit is reset.A PAGE ERASE command applied to a page that is hardware or software protected is notexecuted.A PAGE ERASE command while an ERASE, PROGRAM, or WRITE cycle is in progress isrejected without having any effects on the cycle that is in progress.If RESET# is driven LOW while a PAGE ERASE cycle is in progress, the PAGE ERASE cycleis interrupted and the programmed data may be corrupted. On RESET going LOW, thedevice enters the reset mode and a time of t RHSL is then required before the device canbe reselected by driving Chip Select (S#) LOW.Figure 21: PAGE ERASE Command SequenceCDQ0Notes: 1.Address bits A23-A18 are don't care in the M25PE20. Address bits A23-A17 are don'tcare in the M25PE10.2.Address bits A23-A19 are don't care.3.Address bits A23-A20 are don't care.SUBSECTOR ERASEThe SUBSECTOR ERASE command sets to 1 (FFh) all bits inside the chosen subsector.Before the SUBSECTOR ERASE command can be accepted, a WRITE ENABLE com-mand must have been executed previously. After the WRITE ENABLE command has been decoded, the device sets the write enable latch (WEL) bit.The SUBSECTOR ERASE command is entered by driving chip select (S#) LOW, followed by the command code, and three address bytes on serial data input (DQ0). Any address inside the subsector is a valid address for the SUBSECTOR ERASE command. S# must be driven LOW for the entire duration of the sequence.S# must be driven HIGH after the eighth bit of the last address byte has been latched in.Otherwise the SUBSECTOR ERASE command is not executed. As soon as S# is driven HIGH, the self-timed SUBSECTOR ERASE cycle is initiated; the cycle's duration is t SSE .While the SUBSECTOR ERASE cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The WIP bit is 1 during the self-timed SUBSECTOR ERASE cycle, and is 0 when the cycle is completed. At some unspecified time before the cycle is complete, the WEL bit is reset.A SUBSECTOR ERASE command issued to a sector that is hardware or software protec-ted is not executed.Any SUBSECTOR ERASE command issued while an ERASE, PROGRAM, or WRITE cycle is in progress is rejected without any effect on the cycle that is in progress.If RESET# is driven LOW while a SUBSECTOR ERASE cycle is in progress, the SUBSEC-TOR ERASE cycle is interrupted and data may not be erased correctly. On RESET# going LOW, the device enters the RESET mode and a time of t RHSL is then required before the device can be reselected by driving S# LOW.Figure 22: SUBSECTOR ERASE Command SequenceDQ0CS#2134567892930310Notes: 1.Address bits A23-A18 are don't care in the M25PE20. Address bits A23-A17 are don'tcare in the M25PE10.2.Address bits A23-A19 are don't care .3.Address bits A23-A20 are don't care .SECTOR ERASEThe SECTOR ERASE command sets to 1 (FFh) all bits inside the chosen sector. Before the SECTOR ERASE command can be accepted, a WRITE ENABLE command must have been executed previously. After the WRITE ENABLE command has been decoded, the device sets the write enable latch (WEL) bit.The SECTOR ERASE command is entered by driving chip select (S#) LOW, followed by the command code, and three address bytes on serial data input (DQ0). Any address in-side the sector is a valid address for the SECTOR ERASE command. S# must be driven LOW for the entire duration of the sequence.S# must be driven HIGH after the eighth bit of the last address byte has been latched in.Otherwise the SECTOR ERASE command is not executed. As soon as S# is driven HIGH,the self-timed SECTOR ERASE cycle is initiated; the cycle's duration is t SE . While the SECTOR ERASE cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The WIP bit is 1 during the self-timed SECTOR ERASE cycle, and is 0 when the cycle is completed. At some unspecified time before the cycle is completed, the WEL bit is reset.A SECTOR ERASE command applied to a sector that contains a page that is hardware protected is not executed.Any SECTOR ERASE command while an ERASE, PROGRAM, or WRITE cycle is in pro-gress is rejected without having any effects on the cycle that is in progress.If RESET# is driven LOW while a SECTOR ERASE cycle is in progress, the SECTORERASE cycle is interrupted and the programmed data may be corrupted. On RESET go-ing LOW, the device enters the reset mode and a time of t RHSL is then required before the device can be reselected by driving Chip Select (S#) LOW.Figure 23: SECTOR ERASE Command SequenceCDQ0S#2134567892930310Notes: 1.Address bits A23-A18 are don't care in the M25PE20. Address bits A23-A17 are don'tcare in the M25PE10.2.Address bits A23-A19 are don't care .3.Address bits A23-A20 are don't care .。
Gazelle S2028i(A) 模块化网管型二层工业以太网交换机 文档指南(Rel_03)
文档指南
对产品文档体系进行概要描述。 介绍了产品文档的组成、使用方 法、获取和反馈方式。
读者角色
网络规划工程师 硬件安装工程师 安装调测工程师 现场维护工程师 网络监控工程师 系统维护工程师 数据配置工程师
2-2
瑞斯康达科技发展股份有限公司
瑞斯康达 Gazelle S2028i(A)文档指南
2 产品文档使用方法
网络规划工程师硬件安装工程师安装调测工程师现场维护工程师网络监控工程师系统维护工程师数据配置工程师gazelles2028ia文档指南产品文档使用方法瑞斯康达科技发展股份有限公司23文档名称文档内容读者角色产品描述从产品整体角度出发进行简单且清晰地介绍包括
Gazelle S2028i(A) 模块化网管型二层工业以 太网交换机 文档指南 (Rel_03)
图1-1 Gazelle S2028i 产品文档组成
瑞斯康达科技发展股份有限公司
1-1
瑞斯康达 Gazelle S2028i(A)文档指南
2 产品文档使用方法
2 产品文档使用方法
2.1 分阶段使用文档
本节列举了不同阶段、不同任务内容所需要参考的主要文档和辅助文档。用户通过阅 读本章可以根据需求,找出所需要的文档,为设备的使用提供帮助。产品使用阶段对 应的文档请参见表 2-1。
配置指南(CLI) 配置指南(Web) 命令参考
瑞斯康达科技发展股份有限公司
2-1
2 产品文档使用方法
瑞斯康达 Gazelle S2028i(A)文档指南
2.2 分角色使用文档
2.2.1 角色划分说明
这里的角色划分可能会与读者实际角色有所不同,读者可根据提供的角色定义进行对 应。角色划分说明请参见表 2-2。
华为随行WiFi 2 系列参数表(包含包装盒尺寸 包装清单)
内置LTE/UMTS天线; 内置WLAN天线
SSID 广播和隐藏; None( Open)、 WPA2-PSK、 WPA/WPA2-PSK 加密方式; 速率自动调整; STA 状态显示; Wi-Fi 自动关闭; MAC 地址过滤 主机x1(产品内充电电池不可拆卸) USB线x1 挂绳 x1 (集成充电线) 快速入门x1 保修卡x1 电源适配器x1 TYPE C转接头x1
产品名称 产品尺寸(长×宽×高) 包装盒尺寸(长×宽×高) 产品重量 产品整机重量(含包装) 运营商网络制式 工作频段 Wi-Fi 标准 无线
接口类型
显示屏 电池容量
易用性 天线 加密方式
包装清单
华为随行 WiFi 2 Pro 112.0mm×69.2mm×23mm 156mm x 111mm x 69mm 约195g(含电池) 约533g 中国移动4G / 中国电信4G /中国联通4G /中国联通3G LTE FDD:B1/B2/B3/B4/B5/B7/B8/B20/B19 LTE TDD:B38/B40/B41(2555-2655MHz) UMTS:B1/B2/B4/B5/B6/B8/B19 GSM:B2/B3/B8/B5
802.11 ac/n/b/g标准,支持2.4G和5G品充电接口) 1个标准USB接口(对外充电接口) 1个标准micro SD卡槽 1个micro-SIM卡接口 1个自适应网口:RJ45
OLED-LCD 6400mAh(典型值)充电宝,支持对外充电,挂绳集成充电线(Micro USB接口) 工作时长25小时,待机时长1600小时
TL-R4238_R4239_R4299G用户手册
本手册所提到的产品规格和资讯仅供参考,如有内容更新,恕不另行通知。除非有特殊约定,本手 册仅作为使用指导,本手册中的所有陈述、信息等均不构成任何形式的担保。
目录
物 品 清 单 ........................................................................................................1 第 1 章 用户手册简介 ..................................................................................................................2
3.1.1 前面板................................................................................................................5 3.1.2 后面板................................................................................................................6 3.2 系统需求 .........................................................................................................................7 3.3 安装环境 .........................................................................................................................7 3.4 硬件安装步骤 ..................................................................................................................7 第 4 章 快速安装指南 ..................................................................................................................9 4.1 建立正确的网络设置........................................................................................................9 4.2 快速安装指南 ................................................................................................................10 第 5 章 配置指南 .......................................................................................................................13 5.1 启动和登录....................................................................................................................13 5.2 运行状态 .......................................................................................................................14 5.3 设置向导 .......................................................................................................................15 5.4 网络参数 .......................................................................................................................15 5.4.1 LAN口设置.......................................................................................................15 5.4.2 WAN口设置 .....................................................................................................16
WiLink 8 Pmod 适配器说明书
WiLink™ 8 Pmod Adaptor(Wi-Fi & Bluetooth interface board) Hardware User GuideVersion 1.0Page 1Document ControlDocument Version: 1.0Document Date:12/15/2014Version Date Comment1.0 12/15/2014 Initial ReleasePage 2Contents1Introduction (4)1.1Features (4)1.2Interfaces (4)1.3Pmod-PS (SDIO based WLAN Interface) (6)1.4Pmod-PL (UART based BT/BLE Interface) (6)1.5COM8 100 pin Wireless Module Connector (7)1.6Power (8)1.6.1 Power Input (8)1.6.2 Voltage Regulator (8)1.6.3 Bypassing/Decoupling (8)2Mechanical (9)2.1Dimensions (9)2.2Weight (9)Page 31 IntroductionThe TI WiLink™ 8 Pmod Adaptor is used to interface WiLink™ 8 Wi-Fi and Bluetooth/BLE evaluation boards from Texas Instruments via a Pmod compatible interface to “Zed-series” Avnet boards (MicroZed, Zedboard, PicoZed).At this time, the following two boards from TI are supported:WL1835MODCOM8B (2.4 GHz) andWL1837MODCOM8I (2.4 GHz/5.0 GHz, Industrial temperature grade)The WiLink™ 8 boar d provides the necessary voltage level translations to and from Pmod compatible interfaces.1.1 FeaturesThe WiLink™8 Adaptor facilitates the use of TI’s WL1835MODCOM8B Wi-Fi and BT/BLE module.Features of this wireless solution include the following:–WLAN, Bluetooth, BLE on a module board–WLAN 2.4 GHz SISO (20- and 40-MHz channels), 2.4-GHz MIMO (20-MHz channels)–Support for BLE dual mode–Seamless integration with Xilinx Zynq, TI Sitara and other application processors–Can be used with Avnet Zynq based boards or TI AM335X general-purpose EVM–WLAN and Bluetooth, BLE cores are software and hardware compatible with prior WL127x, WL128x and CC256x offerings, facilitating an easy migration to device.–Shared HCI transport for Bluetooth and BLE over UART and SDIO for WLAN.–Wi-Fi / Bluetooth single antenna co-existence–Built-in chip antenna as well as U.FL RF connectors for optional external 2.4-GHz band antenna–Bidirectional 3.3V & 1.8V voltage level translation on each Pmod connector.–VCCPmod power input – 3.3VDC on each Pmod connector–On board 1.8V Linear LDO regulator ensures reliable VIO voltage, current and noise margins.1.2 Interfaces–Two Pmod male headers connections J1 and J3.–J2 surface mount WL1835 COM module interface connector.Page 4Figure 1 –TI WiLink™ 8 Block DiagramFigure 2 –TI WiLink™ 8 Module with TI WL module attachedPage 51.3 Pmod-PS (SDIO based WLAN Interface)–SDIO 4-lane interface routed via Zynq MIO pins– 3.3V logic levels, signal names at the Pmod connectors as shown below are suffixed with an “_X” (as they connect to Xilinx device)Table 1 – Pmod-PS Interface Connections1.4 Pmod-PL (UART based BT/BLE Interface)–UART interface routed via Zynq EMIO pins– 3.3V logic levels, signal names are suffixed with “_X” (as they connect to Xilinx device)Table 2 – Pmod-PS Interface ConnectionsPage 61.5 COM8 100 pin Wireless Module Connector–Edge-Connector with 2x50 contacts (2-100 on component side, 1-99 on underside)–Only a subset of these signals are required to be routed on the Adaptor for full functionality.Table 3 – Pmod-PS Interface ConnectionsPage 71.6 Power1.6.1 Power InputThe board is powered via the Pmod J1 and Pmod J3 connector. Both 3.3V rails are joined onone VCCPmod plane.1.6.2 Voltage RegulatorThe 1.8V precision LDO regulator is a TI TPS73618DBVR SOT23-5 IC. This part features avery low drop out voltage (200mV max at full current) and a high current source capability(400mA) for its form factor. The device also features a 1% output precision under all line, loadand thermal conditions. For further device information please see the TI datasheet.The table below shows the minimum required voltage rails, currents, and tolerances.Table 3 – Voltage Rails w/ Current Estimates1.6.3 Bypassing/DecouplingThe TI WiLink™ 8 follows the recommended decoupling techniques pereach manufacturer’s datasheet.Page 82 Mechanical2.1 DimensionsFigure 5: TI WiLink-8 Dimensions (mils)2.2 WeightThe weight of the WiLink™ 8 adaptor is 8 grams (~0.25 ounces) standalone and15 grams (~0.5 oz) with a TI Wi-Fi module inserted.Page 9。
MEMORY存储芯片MT29F8G08ABACAWP-ITC中文规格书
READ with auto precharge enabled/ WRITE with auto precharge enabled:The READ with auto precharge enabled or WRITE with auto pre-charge enabled states can each be broken into two parts: the ac-cess period and the precharge period. For READ with auto pre-charge, the precharge period is defined as if the same burst was executed with auto precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses all of the data in the burst. For WRITE with auto precharge, the pre-charge period begins when t WR ends, with t WR measured as if auto precharge was disabled. The access period starts with regis-tration of the command and ends where the precharge period (or t RP) begins. This device supports concurrent auto precharge such that when a READ with auto precharge is enabled or a WRITE with auto precharge is enabled, any command to other banks is allowed, as long as that command does not interrupt the read or write data transfer already in process. In either case, all other related limitations apply (contention between read da-ta and write data must be avoided).The minimum delay from a READ or WRITE command with auto precharge enabled toa command to a different bank is summarized in Table 40 (page 77).4.REFRESH and LOAD MODE commands may only be issued when all banks are idle.5.Not used.6.All states and sequences not shown are illegal or reserved.7.READs or WRITEs listed in the Command/Action column include READs or WRITEs withauto precharge enabled and READs or WRITEs with auto precharge disabled.8. A WRITE command may be applied after the completion of the READ burst.9.Requires appropriate DM.10.The number of clock cycles required to meet t WTR is either two or t WTR/t CK, whicheveris greater.Table 40: Minimum Delay with Auto Precharge EnabledDESELECTThe DESELECT function (CS# HIGH) prevents new commands from being executed bythe DDR2 SDRAM. The DDR2 SDRAM is effectively deselected. Operations already inprogress are not affected. DESELECT is also referred to as COMMAND INHIBIT.Table 44: Truth Table – CKENotes: 1.CKE (n) is the logic state of CKE at clock edge n; CKE (n - 1) was the state of CKE at theprevious clock edge.2.Current state is the state of the DDR2 SDRAM immediately prior to clock edge n.mand (n) is the command registered at clock edge n, and action (n) is a result ofcommand (n).4.The state of ODT does not affect the states described in this table. The ODT function isnot available during self refresh (see ODT Timing (page 130) for more details and spe-cific restrictions).5.Power-down modes do not perform any REFRESH operations. The duration of power-down mode is therefore limited by the refresh requirements.6.“X” means “Don’t Care” (including floating around V REF) in self refresh and power-down. However, ODT must be driven high or low in power-down if the ODT function isenabled via EMR.7.All states and sequences not shown are illegal or reserved unless explicitly describedelsewhere in this document.8.Valid commands for power-down entry and exit are NOP and DESELECT only.9.On self refresh exit, DESELECT or NOP commands must be issued on every clock edge oc-curring during the t XSNR period. READ commands may be issued only after t XSRD (200clocks) is satisfied.10.Valid commands for self refresh exit are NOP and DESELECT only.11.Power-down and self refresh can not be entered while READ or WRITE operations,LOAD MODE operations, or PRECHARGE operations are in progress. See SELF REFRESH(page 118) and SELF REFRESH (page 79) for a list of detailed restrictions.12.Minimum CKE high time is t CKE = 3 × t CK. Minimum CKE LOW time is t CKE = 3 × t CK.This requires a minimum of 3 clock cycles of registration.13.Self refresh mode can only be entered from the all banks idle state.14.Must be a legal command, as defined in Table 37 (page 73).Figure 71: READ-to-Power-Down or Self Refresh EntryCKCK#CommandDQDQS, DQS#Don’t CareTransitioning DataAddressA10CKE Power-down or self refresh entryNotes:1.In the example shown, READ burst completes at T5; earliest power-down or self refreshentry is at T6.2.Power-down or self refresh entry may occur after the READ burst completes.Figure 72: READ with Auto Precharge-to-Power-Down or Self Refresh EntryCKCK#CommandDQDQS, DQS#Don’t CareTransitioning DataAddressA10CKEPower-down or self refresh 2 entry Notes:1.In the example shown, READ burst completes at T5; earliest power-down or self refreshentry is at T6.2.Power-down or self refresh entry may occur after the READ burst completes.ODT TimingOnce a 12ns delay (t MOD) has been satisfied, and after the ODT function has been ena-bled via the EMR LOAD MODE command, ODT can be accessed under two timing cate-gories. ODT will operate either in synchronous mode or asynchronous mode, depend-ing on the state of CKE. ODT can switch anytime except during self refresh mode and afew clocks after being enabled via EMR, as shown in Figure 81 (page 131).There are two timing categories for ODT—turn-on and turn-off. During active mode(CKE HIGH) and fast-exit power-down mode (any row of any bank open, CKE LOW,MR[12 = 0]), t AOND, t AON, t AOFD, and t AOF timing parameters are applied, as shown inFigure 83 (page 132).During slow-exit power-down mode (any row of any bank open, CKE LOW, MR[12] = 1)and precharge power-down mode (all banks/rows precharged and idle, CKE LOW),t AONPD and t AOFPD timing parameters are applied, as shown in Figure 84 (page 133).ODT turn-off timing, prior to entering any power-down mode, is determined by the pa-rameter t ANPD (MIN), as shown in Figure 85 (page 133). At state T2, the ODT HIGH sig-nal satisfies t ANPD (MIN) prior to entering power-down mode at T5. When t ANPD(MIN) is satisfied, t AOFD and t AOF timing parameters apply. Figure 85 (page 133) alsoshows the example where t ANPD (MIN) is not satisfied because ODT HIGH does not oc-cur until state T3. When t ANPD (MIN) is not satisfied, t AOFPD timing parameters apply.ODT turn-on timing prior to entering any power-down mode is determined by the pa-rameter t ANPD, as shown in Figure 86 (page 134). At state T2, the ODT HIGH signal sat-isfies t ANPD (MIN) prior to entering power-down mode at T5. When t ANPD (MIN) issatisfied, t AOND and t AON timing parameters apply. Figure 86 (page 134) also showsthe example where t ANPD (MIN) is not satisfied because ODT HIGH does not occur un-til state T3. When t ANPD (MIN) is not satisfied, t AONPD timing parameters apply.ODT turn-off timing after exiting any power-down mode is determined by the parame-ter t AXPD (MIN), as shown in Figure 87 (page 135). At state Ta1, the ODT LOW signalsatisfies t AXPD (MIN) after exiting power-down mode at state T1. When t AXPD (MIN) issatisfied, t AOFD and t AOF timing parameters apply. Figure 87 (page 135) also shows theexample where t AXPD (MIN) is not satisfied because ODT LOW occurs at state Ta0.When t AXPD (MIN) is not satisfied, t AOFPD timing parameters apply.ODT turn-on timing after exiting either slow-exit power-down mode or precharge pow-er-down mode is determined by the parameter t AXPD (MIN), as shown in Figure 88(page 136). At state Ta1, the ODT HIGH signal satisfies t AXPD (MIN) after exiting pow-er-down mode at state T1. When t AXPD (MIN) is satisfied, t AOND and t AON timing pa-rameters apply. Figure 88 (page 136) also shows the example where t AXPD (MIN) is notsatisfied because ODT HIGH occurs at state Ta0. When t AXPD (MIN) is not satisfied,t AONPD timing parameters apply.。
2928交换机的基本操作
实验一2928交换机的基本操作1.1 知识准备了解交换机的基本知识,了解交换机的基本原理。
阅读《ZXR10 2928(V1.0)接入交换机用户手册》。
1.2 实验目的通过本实验,能够学会通过串口操作交换机,并对交换机的端口进行基本配置;能够查看所配置的内容;学会如何重新设置密码,包括enable密码以及Telnet的用户名和密码;如何在交换机上查看日志内容。
通过本实验,对2928交换机基本了解,能够对2928交换机进行基本配置。
1.3 实验内容通过串口线连接到2928交换机,对2928交换机进行配置,配置2928交换机端口以及察看配置信息,设置2928交换机密码,包括enable密码以及Telnet的用户名和密码,察看日志。
1.4 实验设备2928 一台PC 一台串口线一条平行网线一条1.5 网络拓扑Console口串口PC1.6 配置步骤1.6.1 串口操作配置ZXR10 2928的调试配置一般是通过Console口连接的方式进行,Console口连接配置采用VT100终端方式,下面以Windows操作系统提供的超级终端工具配置为例进行说明。
1.将PC机与ZXR10 2928进行正确连线之后,点击系统的[开始→程序→附件→通讯→超级终端],进行超级终端连接,如错误!未找到引用源。
所示。
图1.6-1 超级终端连接2.在出现错误!未找到引用源。
时,按要求输入有关的位置信息:国家/地区代码、地区电话号码编号和用来拨外线的电话号码。
图1.6-2 位置信息3.弹出[连接说明]对话框时,为新建的连接输入名称并为该连接选择图标。
如错误!未找到引用源。
所示。
图1.6-3 新建连接4.根据配置线所连接的串行口,选择连接串行口为COM1(依实际情况选择PC机所使用的串口)。
如错误!未找到引用源。
所示。
图1.6-4 连接配置资料5.设置所选串行口的端口属性端口属性的设置主要包括以下内容:波特率“9600”,数据位“8”,奇偶校验“无”,停止位“1”,数据流控制“无”,如错误!未找到引用源。
(最新整理)WLAN参数设置规范--上海贝尔(阿德利亚)
(完整)WLAN参数设置规范--上海贝尔(阿德利亚)编辑整理:尊敬的读者朋友们:这里是精品文档编辑中心,本文档内容是由我和我的同事精心编辑整理后发布的,发布之前我们对文中内容进行仔细校对,但是难免会有疏漏的地方,但是任然希望((完整)WLAN参数设置规范--上海贝尔(阿德利亚))的内容能够给您的工作和学习带来便利。
同时也真诚的希望收到您的建议和反馈,这将是我们进步的源泉,前进的动力。
本文可编辑可修改,如果觉得对您有帮助请收藏以便随时查阅,最后祝您生活愉快业绩进步,以下为(完整)WLAN参数设置规范--上海贝尔(阿德利亚)的全部内容。
WLAN参数设置规范—上海贝尔(阿德利亚)目录一、瘦AC参数配置 (5)1。
1 常用配置 (5)1.1.1 AC访问帐号配置 (5)1.1.2 用户带宽限制配置 (6)1.1.3 用户闲置下线时间设置 (7)1.1。
4 配置计费间隔时间 (8)1。
1.5 添加AP分组及分组关联 (8)1。
1.6 配置用户的地址池 (10)1。
1。
7 配置 AP的地址池 (11)1。
1.8 配置热点NAS ID (13)1。
1。
9 WLAN访问控制配置 (14)1。
2 开局配置 (15)1.2。
1 配置AC设备名称 (15)1。
2.2 配置AC NAME (15)1.2.3 配置 AC 的公网IP地址和默认路由 (16)1。
2.4 配置NAS IP (19)1.2。
5 开启DHCP,设置DHCP服务器地址 (19)1.2.6 配置Portal页面推送 (20)1.2.7 配置RADIUS服务器 (20)1。
2.8 配置基于SSID推送一级/二级PORTAL (21)1。
2。
9 配置AC白名单 (22)1。
2。
10 配置VRRP心跳线 (24)1.2。
11 配置热备份的VRRP 通告间隔 (25)1.2.12 开启VRRP热备抢占模式 (26)1.2.13 添加AP版本信息 (26)1.2.14 AC隧道模式 (27)1.2。
Catalyst 2928交换机入门指南说明书
美洲总部 :© 2010 Cisco Systems, Inc.版权所有。
Cisco Systems, Inc., 170 West Tasman Drive, San Jose, CA 95134-1706USACatalyst 2928 交换机入门指南•关于本指南,第 1 页•箱内所含物品,第 2 页•运行 Express Setup ,第 3 页•管理交换机,第 6 页•安装交换机,第 8 页•故障排除,第 13 页•获取文档和提交服务请求,第 14 页关于本指南本指南提供如何使用 Express Setup 对 Catalyst 交换机进行初始配置的说明。
本指南还包括交换机管理选项、机架安装基本步骤、端口和模块连接、电源连接步骤和故障排除帮助。
有关 Catalyst 2928 交换机的其他安装信息和配置信息,请参阅 上提供的 Catalyst 2928 文档。
有关系统要求、重要注意事项、限制、待解决和已解决错误,以及最新文档更新的相关信息,也请访问 ,参阅版本说明。
使用在线出版物时,请参阅与交换机上运行的 Cisco IOS 软件版本相匹配的文档。
软件版本号位于交换机后面板上的 Cisco IOS 标签上。
箱内所含物品注意Catalyst 2928 交换机入门指南运行 Express Setup 注意Catalyst 2928 交换机入门指南运行 Express SetupCatalyst 2928 交换机入门指南运行 Express Setup第 8 步请在网络设置字段中输入以下信息:注意所有条目均须为中文字符和数字。
•管理界面 (VLAN ID)字段中,默认值为1。
注意我们建议您使用默认的 VLAN 值。
在运行 Express Setup 期间,VLAN 1 是交换机上唯一的 VLAN。
通过管理界面您可以管理交换机,如果您想更改管理界面,请输入新的 VLAN ID。
VLAN ID 范围为 1 至 1001。
MEMORY存储芯片MT29F1G08ABADAWP_D中文规格书
Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB, 32KB, 64KB, Sector EraseMT25QL128ABAFeatures•SPI-compatible serial bus interface•Single and double transfer rate (STR/DTR)•Clock frequency–133 MHz (MAX) for all protocols in STR–90 MHz (MAX) for all protocols in DTR•Dual/quad I/O commands for increased through-put up to 90 MB/s•Supported protocols in both STR and DTR–Extended I/O protocol–Dual I/O protocol–Quad I/O protocol•Execute-in-place (XIP)•PROGRAM/ERASE SUSPEND operations •Volatile and nonvolatile configuration settings •Software reset•Additional reset pin for selected part numbers •Dedicated 64-byte OTP area outside main memory –Readable and user-lockable–Permanent lock with PROGRAM OTP command •Erase capability–Bulk erase–Sector erase 64KB uniform granularity–Subsector erase 4KB, 32KB granularity •Security and write protection–Volatile and nonvolatile locking and software write protection for each 64KB sector–Nonvolatile configuration locking–Password protection–Hardware write protection: nonvolatile bits (BP[3:0] and TB) define protected area size–Program/erase protection during power-up–CRC detects accidental changes to raw data •Electronic signature–JEDEC-standard 3-byte signature (BA18h)–Extended device ID: two additional bytes identify device factory options•JESD47H-compliant–Minimum 100,000 ERASE cycles per sector–Data retention: 20 years (TYP)Options Marking •Voltage– 2.7–3.6V L •Density–128Mb128•Device stacking–Monolithic A •Device generation B •Die revision A •Pin configuration–RESET# and HOLD#8•Sector Size–64KB E •Packages – JEDEC-standard, RoHS-compliant–16-pin SOP2, 300 mils body width(SO16W)SF–8-pin SOP2, 208 mils body width(SO8W)SE–24-ball T-PBGA, 05/6mm x 8mm(TBGA24)12–24-ball T-PBGA 05/6mm x 8mm (4 x6 array)14–W-PDFN-8 8mm x 6mm (MLP8 8mmx 6mm)W9–W-PDFN-8 6mm x 5mm (MLP8 6mmx 5mm)W7•Standard security0•Special options–Standard S–Automotive A •Operating temperature range–From –40°C to +85°C IT–From –40°C to +105°C ATNonvolatile Configuration RegisterThis register is read from and written to using the READ NONVOLATILE CONFIGURA-TION REGISTER and the WRITE NONVOLATILE CONFIGURATION REGISTER com-mands, respectively. A register download is executed during power-on or after reset,overwriting the internal configuration register settings that determine device behavior. Table 6: Nonvolatile Configuration RegisterNotes: 1.The number of cycles must be set to accord with the clock frequency, which varies by thetype of FAST READ command (See Supported Clock Frequencies table). Insufficient dum-my clock cycles for the operating frequency causes the memory to read incorrect data.2.When bits 2 and 3 are both set to 0, the device operates in quad I/O protocol.Volatile Configuration RegisterThis register is read from and written to by the READ VOLATILE CONFIGURATIONREGISTER and the WRITE VOLATILE CONFIGURATION REGISTER commands, respec-tively. A register download is executed after these commands, overwriting the internal configuration register settings that determine device memory behavior.Table 7: Volatile Configuration RegisterNotes:1.The number of cycles must be set according to and sufficient for the clock frequency,which varies by the type of FAST READ command, as shown in the Supported Clock Fre-quencies table. An insufficient number of dummy clock cycles for the operating frequen-cy causes the memory to read incorrect data.2.See the Sequence of Bytes During Wrap table.Table 8: Sequence of Bytes During WrapEnhanced Volatile Configuration RegisterThis register is read from and written to using the READ ENHANCED VOLATILE CON-FIGURATION REGISTER and the WRITE ENHANCED VOLATILE CONFIGURATIONREGISTER commands, respectively. A register download is executed after these com-mands, overwriting the internal configuration register settings that determine devicememory behavior.Table 11: Enhanced Volatile Configuration RegisterNote: 1.When bits 6 and 7 are both set to 0, the device operates in quad I/O protocol. When ei-ther bit 6 or 7 is set to 0, the device operates in dual I/O or quad I/O respectively. When abit is set, the device enters the selected protocol immediately after the WRITE EN-HANCED VOLATILE CONFIGURATION REGISTER command. The device returns to the de-fault protocol after the next power-on or reset. Also, the rescue sequence or anotherWRITE ENHANCED VOLATILE CONFIGURATION REGISTER command will return the de-vice to the default protocol.。
2908 说明书
d. 根据您选择的模式,点击“下一步”进入相应的无线参数设置, 设置完成后点击“确定”,系统稍后会连接到相应的网络。
③.您可以在此页面设置无线SSID和加密方式,加密方 式可选择WEP,WPA-PSK/WPA2-PSK等,加密后的网卡端也 需要输入密码;建议选择WPA-PSK/WPA2-PSK加密方式。
3.检查笔记本电脑的无线网卡服务是否开启。 方法如下:(以windows XP 为例),右键点击桌面上
的“我的电脑”,选择“管理”,在计算机管理中选择“ 服务和应用程序”,再在“服务”页面里查看“Wireless Zero Configuration”的状态。如果状态未启动,请右键
点击“Wireless Zero Configuration”选中启动,如果启 动类型显示已禁用,请点击右键选中属性,将启动类型改 为自动,然后再将状态改为启动。
b. 双击Internet协议版本4(TCP/IPv4);
2. 无线网络连接 a. 网卡安装完成后,桌面右下角出现图标 ,点击该图标;
b. 在弹出的网络列表中选择要进行连接的无线网络,点击“连 接”按钮;
c. 当画面显示“已连接”时,表示电脑已经成功连接网络。
b. 进入路由器设置向导模式的画面,您就可以按提示对路由器进 行相应的配置;
登陆AP管理界面
a. 将电脑的IP设为192.168.2.X(X为2-253间任一整数), 子网掩码为255.255.255.0,点击“确定”;
b. 打开IE浏览器,在地址栏是输入http://192.168.2.1, 并按回车键;在弹出的登陆窗口输入用户名:admin; 密码: admin;然后单击“确定”;
注:默认无线连接未开启无线加密,建议您启用加密后建立安全 网络连接。
E18系列产品规格书说明书
E18系列产品规格书CC25302.4GHz ZigBee3.0无线模块目录第一章产品概述 (3)1.1产品简介 (3)1.2特点功能 (4)1.3应用场景 (5)第二章规格参数 (6)2.1射频参数 (6)2.2电气参数 (6)2.3硬件参数 (6)2.4网络系统参数 (7)第三章机械尺寸与引脚定义 (8)第四章硬件设计 (11)第五章软件设计 (11)第六章常见问题 (13)6.1传输距离不理想 (13)6.2模块易损坏 (13)6.3误码率太高 (13)第七章焊接作业指导 (7)7.1回流焊温度 (7)7.2回流焊曲线图 (7)第八章相关型号 (8)第九章天线指南 (8)第十章产品包装图 (8)修订历史 (9)关于我们 (9)第一章产品概述1.1产品简介E18系列是亿佰特设计生产的2.4GHz频段的ZigBee通信协议转串口无线模块,贴片型,PCB板载天线或IPEX-1接口,引脚间距1.27mm,出厂自带自组网固件,到手即用,适用于多种应用场景(尤其智能家居)。
E18系列模块采用美国德州仪器公司原装进口CC2530射频芯片,芯片内部集成了8051单片机及无线收发器,部分模块型号内置PA功率放大器增加通信距离。
出厂自带固件基于ZigBee3.0协议实现的串口数据透传,支持ZigBee3.0协议下各种指令命令。
经实测,对市面上大多数ZigBee3.0产品有着非常良好的兼容性。
1.2ZigBee 3.0优势E18系列模块固件基于Z-Stack3.0.2协议栈(ZigBee 3.0),该版本为CC2530/CC2538系列芯片最优协议栈,因此我司也此基础上做了许多优化,确保系统长期稳定运行。
ZigBee3.0与早前版本的应用方式区别:1.组网方式发生变化:ZigBee 3.0取缔了一上电就组网的方式,而是根据实际需要进行组网。
任何设备在出厂状态下是无网络状态,协调器需要运行“formation”(调用bdb_StartCommissioning(BDB_COMMISSIONING_MODE_NWK_FORMATION))来新建网络,然后再运行"Steering"(调用bdb_StartCommissioning(BDB_COMMISSIONING_MODE_NWK_STEERING))打开网络,打开网络默认时间180秒,可通过广播"ZDP_MgmtPermitJoinReq"的方式将打开网络提前关闭。
极限网络 QSFP28 100Gb 以太网传输器和线缆产品概述说明书
Data SheetExtremeSwitching TM100Gb Ethernet QSFP28 Transceivers and CablesProduct OverviewThe Extreme Networks Quad Small Factor Pluggable 28 (QSFP28)portfolio for supporting 100Gb Ethernet provides a wide range of flexible connectivity options for high performance data center and LAN networking. Fiber optic transceivers for multi-mode fiber (MMF) and single mode fiber (SMF) as well as an array of cost effective direct attach solutions using active optical and passive copper technologies are offered. Options to breakout QSFP28 interfaces to 4 x 25Gb Ethernet and 2 x 50Gb Ethernet provide high density aggregation solutions using the compact, high performance QSFP28 interface.100Gb Ethernet QSFP28 SR4 MMF• 100GBASE-SR4 optical transceiver for use on OM3 or OM4 multi-mode fiber • Up to 70m with OM3 and up to 100m with OM4 MMF• QSFP28 transceiver with male (pinned) MPO (8 fiber) connector • 100Gb Ethernet over parallel multi- mode fiber and 100Gb Ethernet to 4 x 25Gb Ethernet applications • 10332 MPO to 4 x duplex LC breakout OM4 MMF patch cord can be used for 4 x 25Gb Ethernet breakout applications100Gb Ethernet QSFP28 SWDM4 MMF• 100Gb SWDM4 short wavelength division multiplex opticaltransceiver for use on duplex (2 fiber) OM3, OM4, or OM5 wide band multi-mode fiber • Up to 75m with OM3, up to 100m with OM4, up to 150m with OM5 MMF • QSFP28 transceiver with duplex LC (2 fiber) connectorHighlights• Compact Quad Small Form-factorPluggable (QSFP28) products for high density 100Gb Ethernet applications • Hot swappable, field serviceable modular interfaces for Extreme Networks switches with 100Gb QSFP28 ports• Compatible with industry Multi-Source Agreements for QSFP28 pluggable modules• Flexible solutions to adapt to a wide range of connectivity requirements • 100Gb connectivity options for data center, high performance computing, and enterprise LAN• Wide range of media typessupported including multi-mode fiber and single mode fiber for high performance 100Gb solutions • Direct attach cable solutions for passive copper and active optical applications• Parallel fiber options for high density 25Gb Ethernet and 50Gb Ethernet aggregation solutions over both multi-mode and single mode fiber infrastructures• Cost effective 100Gb connectivity solutions ranging from 0.5m to 10km • H ighest quality transceivertechnology to ensure long life cycle and reliability• T ested for reliability in Extreme Networks switches• Standards compliant and optical interoperability withcompliant devices100Gb Ethernet QSFP28 LR4 10km SMF• 100GBASE-LR4 4 lane wave division multiplex optical transceiver for use with single mode fiber• Up to 10km reach using G.652 single mode fiber• QSFP28 transceiver with duplex LC (2 fiber) connector 100Gb Ethernet QSFP28 CWDM4, 2km SMF• 100Gb QSFP28 CWDM4 optical transceiver for use with single mode fiber• 100Gb QSFP28 4 Lane wave division multiplex transceiver compatible with the CWDM4 Consortiumspecification for CWDM4 optical transceivers• Up to 2km reach with G.652 SMF• QSFP28 transceiver with duplex LC (2 fiber) connector 100Gb Ethernet QSFP28 CWDM4-Lite, 500m SMF • 100Gb QSFP28 CWDM4-Lite 4 Lane wave division multiplex transceiver• Reduced transceiver operating temperature range 15° – 55° C• Up to 500m reach with G.652 SMF• QSFP28 transceiver with duplex LC (2 fiber) connector 100Gb Ethernet QSFP28 Parallel Single Mode (PSM4), 2km SMF• 100Gb, Parallel Single Mode PSM4, 2km SMF, QSFP28, MPO (8 fiber)• Integrated 3m SMF pigtail cable with male (pinned) MPO (8 fiber) connector• 100Gb Ethernet over parallel single mode fiber and 100Gb Ethernet to 4 x 25Gb Ethernet applications• 10327 MPO to 4 x duplex LC breakout SMFpatch cord can be used for 4 x 25Gb Ethernetbreakout applications 100Gb Ethernet QSFP28 Active Optical Cables (AOC)• Active optical direct attach cables with integrated 100Gb Ethernet QSFP28 transceivers• 100Gb AOC cable lengths from 5m to 20m100Gb Ethernet Passive Copper Direct Attach Cables (DAC)• Passive copper direct attach cables with integrated 100Gb Ethernet QSFP28 transceivers• 100Gb DAC cable lengths from 0.5m to 5m100Gb Ethernet QSFP28 – 4 x 25Gb SFP28 Ethernet AOC• Active optical direct attach cables (AOC) with integrated 100Gb Ethernet QSFP28 transceiver and 4 x SFP28 25Gb Ethernet transceivers• 100Gb to 4 x 25Gb AOC cable lengths from 5m to 20m 100Gb Ethernet QSFP28 – 4 x 25Gb SFP28 Ethernet Passive Copper DAC• Passive copper direct attach cables with integrated 100Gb Ethernet QSFP28 transceiver and 4 x SFP2825Gb Ethernet transceivers100Gb Ethernet QSFP28 – 2 x 50Gb QSFP28 Ethernet Passive Copper DAC• Passive copper direct attach cables with integrated 100Gb Ethernet QSFP28 transceiver and 2 x QSFP2850Gb (two lane) Ethernet transceivers100Gb Ethernet QSFP28 – 2 x 50Gb QSFP28 Ethernet Active Optical Cable (AOC)• Active optical direct attach cables with integrated 100Gb Ethernet QSFP28 transceiver and 2 x QSFP2850Gb (two lane) Ethernet transceivers• 100Gb to 2 x 50Gb AOC cable lengths from 5m to 20mFigure 2: 100Gb Ethernet QSFP28 – 4 x 25Gb Ethernet SFP28 AOCFigure 1: 100Gb Ethernet Parallel Single Mode (PSM4), 2km, SMFFigure 3: 100Gb Ethernet QSFP28 – 2 x 50Gb Ethernet QSFP28 AOCProduct Specifications* Transmission distance is provided as a nominal guide only. T o determine achievable distances, refer to the device optical specifications and the specifications of your fiber installationStandards and Compliance IEEE802.3 100GBASE-LR4802.3 100GBASE-SR4802.3 100GBASE-CR4Multi-Source Agreements (MSA)SFF-8436 QSFP+ 10 Gbps 4x Pluggable Transceiver SFF-8636 Common Management InterfaceSFF-8665 QSFP28 Pluggable Transceiver Solution SFF-8679 QSFP28 Base Electrical Specification CWDM4 MSA T echnical Specification100G SWDM4 MSA T echnical Specifications Operating Conditions0° – 70° C (Case T emperature)15° – 55° C (Case T emperature) for CWDM4-Lite Optical SafetyFDA/CDRH Class 1 laser productEN60825-1:2007 Class 1 Safety of laser products Environmental ComplianceEU RoHS 2011/65/EUEU WEEE 2012/19/EUChina RoHS SJ/T 11262-2006T aiwan RoHS CNS 15663(2013.7)EMI/EMC StandardsNorth American EMC for ITEFCC CFR 47 part 15 Class A (USA)ICES-003 Class A (Canada)European EMC StandardsEN 55032:2015 Class AEN 55024:2010EN 61000-3-2,2014 (Harmonics)EN 61000-3-3 2013 (Flicker)EN 300 386 v1.6.1 (EMC T elecommunications)2014/30/EU EMC DirectiveInternational EMC CertificationsCISPR 32:2015, Class A (International Emissions)AS/NZS CISPR32:2015CISPR 24:2010 Class A (International Immunity)IEC 61000-4-2:2008/EN 61000-4-2:2009 Electrostatic Discharge, 8kV Contact, 15 kV Air, Criteria AIEC 61000-4-3:2010/EN 61000-4-3:2006 +A1:2008+A2:2010 Radiated Immunity 10V/m, Criteria AIEC 61000-4-4:2012. / EN 61000-4-4:2012 Transient Burst, 1 kV, Criteria AIEC 61000-4-5:2014 /EN 61000-4-5:2014 Surge, 2 kV L-L, 2 kV L-G, Level 3, Criteria AIEC 61000-4-6:2013/EN 61000-4-6:2014 Conducted Immunity, 0.15-80 MHz, 10V/m unmod. RMS, Criteria AIEC/EN 61000-4-11:2004 Power Dips & Interruptions, >30%, 25 periods, Criteria CNote: QSFP28 products meet the above specifications when installed in Extreme Networks equipment./contact Phone +1-408-579-2800©2018 Extreme Networks, Inc. All rights reserved. Extreme Networks and the Extreme Networks logo are trademarks or registered trademarks of Extreme Networks, Inc. inthe United States and/or other countries. All other names are the property of their respective owners. For additional information on Extreme Networks Trademarks please see /company/legal/trademarks. Specifications and product availability are subject to change without notice. 12381-0618-25 WarrantyQSFP28 transceiver products have a one year hardware warranty - For warranty details, visit /go/warranty.Ordering Information*10424 100Gb DAC passive copper DAC breakout cable can also be used for 40Gb Ethernet to 4 x 10Gb Ethernet breakout.See the ExtremeXOS Hardware/Software Compatibility andRecommendation Matrices document for a full list of supported devices and ExtremeXOS recommendations.。
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深圳信诺山通信技术有限公司Shenzhen Signalsen Telecom Technology Co,.Ltd
规格书
喜瑞得(2928)
料号:W19-1Y90A-F
1. 项目图片
项目图片如下:
2.测试制具
目的:尽可能准确地测试天线的无源参数。
制作方法:手机制具是用一根50欧姆的同轴电缆,一端连在手机主板的匹配电路后端(射频测试孔前端)的测试点上,另一端连接SMA接头。
示意图如下:
3. 匹配电路
原匹配无更改。
4. S11测试
4.0 S11测试方法说明
测试设备:网络分析仪(HP 8753E)
测试方法:用一根50欧姆CABLE电缆从仪器测试端口导出,使用校准件校准后连接射频治具的SMA接头,记录相关频点对应的回波损耗和驻波比。
测试示意图如下:
测试示意图4.1S11参数
驻波:
8. 结构图纸。