Hardware Accelerated Rendering of Emissive Volumes

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Tektronix MDO3000 Series 数字多功能作业仪用户指南说明书

Tektronix MDO3000 Series 数字多功能作业仪用户指南说明书

19StandardMath ToolsDisplay up to four math function traces (F1-F4). The easy-to-use graphical interface simplifies setup of up to two operations on each function trace;and function traces can be chained together to perform math-on-math.absolute value integralaverage (summed)invert (negate)average (continuous)log (base e)custom (MATLAB) – limited points product (x)derivativeratio (/)deskew (resample)reciprocaldifference (–)rescale (with units)enhanced resolution (to 11 bits vertical)roof envelope (sinx)/x exp (base e)square exp (base 10)square root fft (power spectrum, magnitude, phase,sum (+)up to 50 kpts) trend (datalog) of 1000 events floorzoom (identity)histogram of 1000 eventsMeasure ToolsDisplay any 6 parameters together with statistics, including their average,high, low, and standard deviations. Histicons provide a fast, dynamic view of parameters and wave-shape characteristics.Pass/Fail TestingSimultaneously test multiple parameters against selectable parameter limits or pre-defined masks. Pass or fail conditions can initiate actions including document to local or networked files, e-mail the image of the failure, save waveforms, send a pulse out at the rear panel auxiliary BNC output, or (with the GPIB option) send a GPIB SRQ.Jitter and Timing Analysis Software Package (WRXi-JTA2)(Standard with MXi-A model oscilloscopes)•Jitter and timing parameters, with “Track”graphs of •Edge@lv parameter (counts edges)• Persistence histogram, persistence trace (mean, range, sigma)Software Options –Advanced Math and WaveShape AnalysisStatistics Package (WRXi-STAT)This package provides additional capability to statistically display measurement information and to analyze results:• Histograms expanded with 19 histogram parameters/up to 2 billion events.• Persistence Histogram• Persistence Trace (mean, range, sigma)Master Analysis Software Package (WRXi-XMAP)(Standard with MXi-A model oscilloscopes)This package provides maximum capability and flexibility, and includes all the functionality present in XMATH, XDEV, and JTA2.Advanced Math Software Package (WRXi-XMATH)(Standard with MXi-A model oscilloscopes)This package provides a comprehensive set of WaveShape Analysis tools providing insight into the wave shape of complex signals. Includes:•Parameter math – add, subtract, multiply, or divide two different parameters.Invert a parameter and rescale parameter values.•Histograms expanded with 19 histogram parameters/up to 2 billion events.•Trend (datalog) of up to 1 million events•Track graphs of any measurement parameter•FFT capability includes: power averaging, power density, real and imaginary components, frequency domain parameters, and FFT on up to 24 Mpts.•Narrow-band power measurements •Auto-correlation function •Sparse function• Cubic interpolation functionAdvanced Customization Software Package (WRXi-XDEV)(Standard with MXi-A model oscilloscopes)This package provides a set of tools to modify the scope and customize it to meet your unique needs. Additional capability provided by XDEV includes:•Creation of your own measurement parameter or math function, using third-party software packages, and display of the result in the scope. Supported third-party software packages include:– VBScript – MATLAB – Excel•CustomDSO – create your own user interface in a scope dialog box.• Addition of macro keys to run VBScript files •Support for plug-insValue Analysis Software Package (WRXi-XVAP)(Standard with MXi-A model oscilloscopes)Measurements:•Jitter and Timing parameters (period@level,width@level, edge@level,duty@level, time interval error@level, frequency@level, half period, setup, skew, Δ period@level, Δ width@level).Math:•Persistence histogram •Persistence trace (mean, sigma, range)•1 Mpts FFTs with power spectrum density, power averaging, real, imaginary, and real+imaginary settings)Statistical and Graphical Analysis•1 Mpts Trends and Histograms •19 histogram parameters •Track graphs of any measurement parameterIntermediate Math Software Package (WRXi-XWAV)Math:•1 Mpts FFTs with power spectrum density, power averaging, real, and imaginary componentsStatistical and Graphical Analysis •1 Mpts Trends and Histograms •19 histogram parameters•Track graphs of any measurement parameteramplitude area base cyclescustom (MATLAB,VBScript) –limited points delay Δdelay duration duty cyclefalltime (90–10%, 80–20%, @ level)firstfrequency lastlevel @ x maximum mean median minimumnumber of points +overshoot –overshoot peak-to-peak period phaserisetime (10–90%, 20–80%, @ level)rmsstd. deviation time @ level topΔ time @ levelΔ time @ level from triggerwidth (positive + negative)x@ max.x@ min.– Cycle-Cycle Jitter – N-Cycle– N-Cycle with start selection – Frequency– Period – Half Period – Width– Time Interval Error – Setup– Hold – Skew– Duty Cycle– Duty Cycle Error20WaveRunner WaveRunner WaveRunner WaveRunner WaveRunner 44Xi-A64Xi-A62Xi-A104Xi-A204Xi-AVertical System44MXi-A64MXi-A104MXi-A204MXi-ANominal Analog Bandwidth 400 MHz600 MHz600 MHz 1 GHz 2 GHz@ 50 Ω, 10 mV–1 V/divRise Time (Typical)875 ps500 ps500 ps300 ps180 psInput Channels44244Bandwidth Limiters20 MHz; 200 MHzInput Impedance 1 MΩ||16 pF or 50 Ω 1 MΩ||20 pF or 50 ΩInput Coupling50 Ω: DC, 1 MΩ: AC, DC, GNDMaximum Input Voltage50 Ω: 5 V rms, 1 MΩ: 400 V max.50 Ω: 5 V rms, 1 MΩ: 250 V max.(DC + Peak AC ≤ 5 kHz)(DC + Peak AC ≤ 10 kHz)Vertical Resolution8 bits; up to 11 with enhanced resolution (ERES)Sensitivity50 Ω: 2 mV/div–1 V/div fully variable; 1 MΩ: 2 mV–10 V/div fully variableDC Gain Accuracy±1.0% of full scale (typical); ±1.5% of full scale, ≥ 10 mV/div (warranted)Offset Range50 Ω: ±1 V @ 2–98 mV/div, ±10 V @ 100 mV/div–1 V/div; 50Ω:±400mV@2–4.95mV/div,±1V@5–99mv/div,1 M Ω: ±1 V @ 2–98 mV/div, ±10 V @ 100 mV/div–1 V/div,±10 V @ 100 mV–1 V/div±**********/div–10V/div 1 M Ω: ±400 mV @ 2–4.95 mV/div, ±1 V @5–99 mV/div, ±10 V @ 100 mV–1 V/div,±*********–10V/divInput Connector ProBus/BNCTimebase SystemTimebases Internal timebase common to all input channels; an external clock may be applied at the auxiliary inputTime/Division Range Real time: 200 ps/div–10 s/div, RIS mode: 200 ps/div to 10 ns/div, Roll mode: up to 1,000 s/divClock Accuracy≤ 5 ppm @ 25 °C (typical) (≤ 10 ppm @ 5–40 °C)Sample Rate and Delay Time Accuracy Equal to Clock AccuracyChannel to Channel Deskew Range±9 x time/div setting, 100 ms max., each channelExternal Sample Clock DC to 600 MHz; (DC to 1 GHz for 104Xi-A/104MXi-A and 204Xi-A/204MXi-A) 50 Ω, (limited BW in 1 MΩ),BNC input, limited to 2 Ch operation (1 Ch in 62Xi-A), (minimum rise time and amplitude requirements applyat low frequencies)Roll Mode User selectable at ≥ 500 ms/div and ≤100 kS/s44Xi-A64Xi-A62Xi-A104Xi-A204Xi-A Acquisition System44MXi-A64MXi-A104MXi-A204MXi-ASingle-Shot Sample Rate/Ch 5 GS/sInterleaved Sample Rate (2 Ch) 5 GS/s10 GS/s10 GS/s10 GS/s10 GS/sRandom Interleaved Sampling (RIS)200 GS/sRIS Mode User selectable from 200 ps/div to 10 ns/div User selectable from 100 ps/div to 10 ns/div Trigger Rate (Maximum) 1,250,000 waveforms/secondSequence Time Stamp Resolution 1 nsMinimum Time Between 800 nsSequential SegmentsAcquisition Memory Options Max. Acquisition Points (4 Ch/2 Ch, 2 Ch/1 Ch in 62Xi-A)Segments (Sequence Mode)Standard12.5M/25M10,00044Xi-A64Xi-A62Xi-A104Xi-A204Xi-A Acquisition Processing44MXi-A64MXi-A104MXi-A204MXi-ATime Resolution (min, Single-shot)200 ps (5 GS/s)100 ps (10 GS/s)100 ps (10 GS/s)100 ps (10 GS/s)100 ps (10 GS/s) Averaging Summed and continuous averaging to 1 million sweepsERES From 8.5 to 11 bits vertical resolutionEnvelope (Extrema)Envelope, floor, or roof for up to 1 million sweepsInterpolation Linear or (Sinx)/xTrigger SystemTrigger Modes Normal, Auto, Single, StopSources Any input channel, External, Ext/10, or Line; slope and level unique to each source, except LineTrigger Coupling DC, AC (typically 7.5 Hz), HF Reject, LF RejectPre-trigger Delay 0–100% of memory size (adjustable in 1% increments, or 100 ns)Post-trigger Delay Up to 10,000 divisions in real time mode, limited at slower time/div settings in roll modeHold-off 1 ns to 20 s or 1 to 1,000,000,000 events21WaveRunner WaveRunner WaveRunner WaveRunner WaveRunner 44Xi-A 64Xi-A 62Xi-A104Xi-A 204Xi-A Trigger System (cont’d)44MXi-A64MXi-A104MXi-A204MXi-AInternal Trigger Level Range ±4.1 div from center (typical)Trigger and Interpolator Jitter≤ 3 ps rms (typical)Trigger Sensitivity with Edge Trigger 2 div @ < 400 MHz 2 div @ < 600 MHz 2 div @ < 600 MHz 2 div @ < 1 GHz 2 div @ < 2 GHz (Ch 1–4 + external, DC, AC, and 1 div @ < 200 MHz 1 div @ < 200 MHz 1 div @ < 200 MHz 1 div @ < 200 MHz 1 div @ < 200 MHz LFrej coupling)Max. Trigger Frequency with400 MHz 600 MHz 600 MHz 1 GHz2 GHzSMART Trigger™ (Ch 1–4 + external)@ ≥ 10 mV@ ≥ 10 mV@ ≥ 10 mV@ ≥ 10 mV@ ≥ 10 mVExternal Trigger RangeEXT/10 ±4 V; EXT ±400 mVBasic TriggersEdgeTriggers when signal meets slope (positive, negative, either, or Window) and level conditionTV-Composite VideoT riggers NTSC or PAL with selectable line and field; HDTV (720p, 1080i, 1080p) with selectable frame rate (50 or 60 Hz)and Line; or CUSTOM with selectable Fields (1–8), Lines (up to 2000), Frame Rates (25, 30, 50, or 60 Hz), Interlacing (1:1, 2:1, 4:1, 8:1), or Synch Pulse Slope (Positive or Negative)SMART TriggersState or Edge Qualified Triggers on any input source only if a defined state or edge occurred on another input source.Delay between sources is selectable by time or eventsQualified First In Sequence acquisition mode, triggers repeatedly on event B only if a defined pattern, state, or edge (event A) is satisfied in the first segment of the acquisition. Delay between sources is selectable by time or events Dropout Triggers if signal drops out for longer than selected time between 1 ns and 20 s.PatternLogic combination (AND, NAND, OR, NOR) of 5 inputs (4 channels and external trigger input – 2 Ch+EXT on WaveRunner 62Xi-A). Each source can be high, low, or don’t care. The High and Low level can be selected independently. Triggers at start or end of the patternSMART Triggers with Exclusion TechnologyGlitch and Pulse Width Triggers on positive or negative glitches with widths selectable from 500 ps to 20 s or on intermittent faults (subject to bandwidth limit of oscilloscope)Signal or Pattern IntervalTriggers on intervals selectable between 1 ns and 20 sTimeout (State/Edge Qualified)Triggers on any source if a given state (or transition edge) has occurred on another source.Delay between sources is 1 ns to 20 s, or 1 to 99,999,999 eventsRuntTrigger on positive or negative runts defined by two voltage limits and two time limits. Select between 1 ns and 20 sSlew RateTrigger on edge rates. Select limits for dV, dt, and slope. Select edge limits between 1 ns and 20 s Exclusion TriggeringTrigger on intermittent faults by specifying the normal width or periodLeCroy WaveStream Fast Viewing ModeIntensity256 Intensity Levels, 1–100% adjustable via front panel control Number of Channels up to 4 simultaneouslyMax Sampling Rate5 GS/s (10 GS/s for WR 62Xi-A, 64Xi-A/64MXi-A,104Xi-A/104MXi-A, 204Xi-A/204MXi-A in interleaved mode)Waveforms/second (continuous)Up to 20,000 waveforms/secondOperationFront panel toggle between normal real-time mode and LeCroy WaveStream Fast Viewing modeAutomatic SetupAuto SetupAutomatically sets timebase, trigger, and sensitivity to display a wide range of repetitive signalsVertical Find ScaleAutomatically sets the vertical sensitivity and offset for the selected channels to display a waveform with maximum dynamic range44Xi-A 64Xi-A 62Xi-A104Xi-A 204Xi-A Probes44MXi-A 64MXi-A104MXi-A 204MXi-AProbesOne Passive probe per channel; Optional passive and active probes available Probe System; ProBus Automatically detects and supports a variety of compatible probes Scale FactorsAutomatically or manually selected, depending on probe usedColor Waveform DisplayTypeColor 10.4" flat-panel TFT-LCD with high resolution touch screenResolutionSVGA; 800 x 600 pixels; maximum external monitor output resolution of 2048 x 1536 pixelsNumber of Traces Display a maximum of 8 traces. Simultaneously display channel, zoom, memory, and math traces Grid StylesAuto, Single, Dual, Quad, Octal, XY , Single + XY , Dual + XY Waveform StylesSample dots joined or dots only in real-time mode22Zoom Expansion TracesDisplay up to 4 Zoom/Math traces with 16 bits/data pointInternal Waveform MemoryM1, M2, M3, M4 Internal Waveform Memory (store full-length waveform with 16 bits/data point) or store to any number of files limited only by data storage mediaSetup StorageFront Panel and Instrument StatusStore to the internal hard drive, over the network, or to a USB-connected peripheral deviceInterfaceRemote ControlVia Windows Automation, or via LeCroy Remote Command Set Network Communication Standard VXI-11 or VICP , LXI Class C Compliant GPIB Port (Accessory)Supports IEEE – 488.2Ethernet Port 10/100/1000Base-T Ethernet interface (RJ-45 connector)USB Ports5 USB 2.0 ports (one on front of instrument) supports Windows-compatible devices External Monitor Port Standard 15-pin D-Type SVGA-compatible DB-15; connect a second monitor to use extended desktop display mode with XGA resolution Serial PortDB-9 RS-232 port (not for remote oscilloscope control)44Xi-A 64Xi-A 62Xi-A104Xi-A 204Xi-A Auxiliary Input44MXi-A 64MXi-A104MXi-A 204MXi-ASignal Types Selected from External Trigger or External Clock input on front panel Coupling50 Ω: DC, 1 M Ω: AC, DC, GND Maximum Input Voltage50 Ω: 5 V rms , 1 M Ω: 400 V max.50 Ω: 5 V rms , 1 M Ω: 250 V max. (DC + Peak AC ≤ 5 kHz)(DC + Peak AC ≤ 10 kHz)Auxiliary OutputSignal TypeTrigger Enabled, Trigger Output. Pass/Fail, or Off Output Level TTL, ≈3.3 VConnector TypeBNC, located on rear panelGeneralAuto Calibration Ensures specified DC and timing accuracy is maintained for 1 year minimumCalibratorOutput available on front panel connector provides a variety of signals for probe calibration and compensationPower Requirements90–264 V rms at 50/60 Hz; 115 V rms (±10%) at 400 Hz, Automatic AC Voltage SelectionInstallation Category: 300 V CAT II; Max. Power Consumption: 340 VA/340 W; 290 VA/290 W for WaveRunner 62Xi-AEnvironmentalTemperature: Operating+5 °C to +40 °C Temperature: Non-Operating -20 °C to +60 °CHumidity: Operating Maximum relative humidity 80% for temperatures up to 31 °C decreasing linearly to 50% relative humidity at 40 °CHumidity: Non-Operating 5% to 95% RH (non-condensing) as tested per MIL-PRF-28800F Altitude: OperatingUp to 3,048 m (10,000 ft.) @ ≤ 25 °C Altitude: Non-OperatingUp to 12,190 m (40,000 ft.)PhysicalDimensions (HWD)260 mm x 340 mm x 152 mm Excluding accessories and projections (10.25" x 13.4" x 6")Net Weight7.26kg. (16.0lbs.)CertificationsCE Compliant, UL and cUL listed; Conforms to EN 61326, EN 61010-1, UL 61010-1 2nd Edition, and CSA C22.2 No. 61010-1-04Warranty and Service3-year warranty; calibration recommended annually. Optional service programs include extended warranty, upgrades, calibration, and customization services23Product DescriptionProduct CodeWaveRunner Xi-A Series Oscilloscopes2 GHz, 4 Ch, 5 GS/s, 12.5 Mpts/ChWaveRunner 204Xi-A(10 GS/s, 25 Mpts/Ch in interleaved mode)with 10.4" Color Touch Screen Display 1 GHz, 4 Ch, 5 GS/s, 12.5 Mpts/ChWaveRunner 104Xi-A(10 GS/s, 25 Mpts/Ch in interleaved mode)with 10.4" Color Touch Screen Display 600 MHz, 4 Ch, 5 GS/s, 12.5 Mpts/Ch WaveRunner 64Xi-A(10 GS/s, 25 Mpts/Ch in interleaved mode)with 10.4" Color Touch Screen Display 600 MHz, 2 Ch, 5 GS/s, 12.5 Mpts/Ch WaveRunner 62Xi-A(10 GS/s, 25 Mpts/Ch in interleaved mode)with 10.4" Color Touch Screen Display 400 MHz, 4 Ch, 5 GS/s, 12.5 Mpts/Ch WaveRunner 44Xi-A(25 Mpts/Ch in interleaved mode)with 10.4" Color Touch Screen DisplayWaveRunner MXi-A Series Oscilloscopes2 GHz, 4 Ch, 5 GS/s, 12.5 Mpts/ChWaveRunner 204MXi-A(10 GS/s, 25 Mpts/Ch in Interleaved Mode)with 10.4" Color Touch Screen Display 1 GHz, 4 Ch, 5 GS/s, 12.5 Mpts/ChWaveRunner 104MXi-A(10 GS/s, 25 Mpts/Ch in Interleaved Mode)with 10.4" Color Touch Screen Display 600 MHz, 4 Ch, 5 GS/s, 12.5 Mpts/Ch WaveRunner 64MXi-A(10 GS/s, 25 Mpts/Ch in Interleaved Mode)with 10.4" Color Touch Screen Display 400 MHz, 4 Ch, 5 GS/s, 12.5 Mpts/Ch WaveRunner 44MXi-A(25 Mpts/Ch in Interleaved Mode)with 10.4" Color Touch Screen DisplayIncluded with Standard Configuration÷10, 500 MHz, 10 M Ω Passive Probe (Total of 1 Per Channel)Standard Ports; 10/100/1000Base-T Ethernet, USB 2.0 (5), SVGA Video out, Audio in/out, RS-232Optical 3-button Wheel Mouse – USB 2.0Protective Front Cover Accessory PouchGetting Started Manual Quick Reference GuideAnti-virus Software (Trial Version)Commercial NIST Traceable Calibration with Certificate 3-year WarrantyGeneral Purpose Software OptionsStatistics Software Package WRXi-STAT Master Analysis Software Package WRXi-XMAP (Standard with MXi-A model oscilloscopes)Advanced Math Software Package WRXi-XMATH (Standard with MXi-A model oscilloscopes)Intermediate Math Software Package WRXi-XWAV (Standard with MXi-A model oscilloscopes)Value Analysis Software Package (Includes XWAV and JTA2) WRXi-XVAP (Standard with MXi-A model oscilloscopes)Advanced Customization Software Package WRXi-XDEV (Standard with MXi-A model oscilloscopes)Spectrum Analyzer and Advanced FFT Option WRXi-SPECTRUM Processing Web Editor Software Package WRXi-XWEBProduct Description Product CodeApplication Specific Software OptionsJitter and Timing Analysis Software Package WRXi-JTA2(Standard with MXi-A model oscilloscopes)Digital Filter Software PackageWRXi-DFP2Disk Drive Measurement Software Package WRXi-DDM2PowerMeasure Analysis Software Package WRXi-PMA2Serial Data Mask Software PackageWRXi-SDM QualiPHY Enabled Ethernet Software Option QPHY-ENET*QualiPHY Enabled USB 2.0 Software Option QPHY-USB †EMC Pulse Parameter Software Package WRXi-EMC Electrical Telecom Mask Test PackageET-PMT* TF-ENET-B required. †TF-USB-B required.Serial Data OptionsI 2C Trigger and Decode Option WRXi-I2Cbus TD SPI Trigger and Decode Option WRXi-SPIbus TD UART and RS-232 Trigger and Decode Option WRXi-UART-RS232bus TD LIN Trigger and Decode Option WRXi-LINbus TD CANbus TD Trigger and Decode Option CANbus TD CANbus TDM Trigger, Decode, and Measure/Graph Option CANbus TDM FlexRay Trigger and Decode Option WRXi-FlexRaybus TD FlexRay Trigger and Decode Physical Layer WRXi-FlexRaybus TDP Test OptionAudiobus Trigger and Decode Option WRXi-Audiobus TDfor I 2S , LJ, RJ, and TDMAudiobus Trigger, Decode, and Graph Option WRXi-Audiobus TDGfor I 2S LJ, RJ, and TDMMIL-STD-1553 Trigger and Decode Option WRXi-1553 TDA variety of Vehicle Bus Analyzers based on the WaveRunner Xi-A platform are available.These units are equipped with a Symbolic CAN trigger and decode.Mixed Signal Oscilloscope Options500 MHz, 18 Ch, 2 GS/s, 50 Mpts/Ch MS-500Mixed Signal Oscilloscope Option 250 MHz, 36 Ch, 1 GS/s, 25 Mpts/ChMS-500-36(500 MHz, 18 Ch, 2 GS/s, 50 Mpts/Ch Interleaved) Mixed Signal Oscilloscope Option 250 MHz, 18 Ch, 1 GS/s, 10 Mpts/Ch MS-250Mixed Signal Oscilloscope OptionProbes and Amplifiers*Set of 4 ZS1500, 1.5 GHz, 0.9 pF , 1 M ΩZS1500-QUADPAK High Impedance Active ProbeSet of 4 ZS1000, 1 GHz, 0.9 pF , 1 M ΩZS1000-QUADPAK High Impedance Active Probe 2.5 GHz, 0.7 pF Active Probe HFP25001 GHz Active Differential Probe (÷1, ÷10, ÷20)AP034500 MHz Active Differential Probe (x10, ÷1, ÷10, ÷100)AP03330 A; 100 MHz Current Probe – AC/DC; 30 A rms ; 50 A rms Pulse CP03130 A; 50 MHz Current Probe – AC/DC; 30 A rms ; 50 A rms Pulse CP03030 A; 50 MHz Current Probe – AC/DC; 30 A rms ; 50 A peak Pulse AP015150 A; 10 MHz Current Probe – AC/DC; 150 A rms ; 500 A peak Pulse CP150500 A; 2 MHz Current Probe – AC/DC; 500 A rms ; 700 A peak Pulse CP5001,400 V, 100 MHz High-Voltage Differential Probe ADP3051,400 V, 20 MHz High-Voltage Differential Probe ADP3001 Ch, 100 MHz Differential Amplifier DA1855A*A wide variety of other passive, active, and differential probes are also available.Consult LeCroy for more information.Product Description Product CodeHardware Accessories*10/100/1000Base-T Compliance Test Fixture TF-ENET-B †USB 2.0 Compliance Test Fixture TF-USB-B External GPIB Interface WS-GPIBSoft Carrying Case WRXi-SOFTCASE Hard Transit CaseWRXi-HARDCASE Mounting Stand – Desktop Clamp Style WRXi-MS-CLAMPRackmount Kit WRXi-RACK Mini KeyboardWRXi-KYBD Removable Hard Drive Package (Includes removeable WRXi-A-RHD hard drive kit and two hard drives)Additional Removable Hard DriveWRXi-A-RHD-02* A variety of local language front panel overlays are also available .† Includes ENET-2CAB-SMA018 and ENET-2ADA-BNCSMA.Customer ServiceLeCroy oscilloscopes and probes are designed, built, and tested to ensure high reliability. In the unlikely event you experience difficulties, our digital oscilloscopes are fully warranted for three years, and our probes are warranted for one year.This warranty includes:• No charge for return shipping • Long-term 7-year support• Upgrade to latest software at no chargeLocal sales offices are located throughout the world. Visit our website to find the most convenient location.© 2010 by LeCroy Corporation. All rights reserved. Specifications, prices, availability, and delivery subject to change without notice. Product or brand names are trademarks or requested trademarks of their respective holders.1-800-5-LeCroy WRXi-ADS-14Apr10PDF。

爱特梅尔maXTouch解决方案助力ASUS Eee Pad Transformer平板电脑触摸屏

爱特梅尔maXTouch解决方案助力ASUS Eee Pad Transformer平板电脑触摸屏
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介绍全息技术英语作文

介绍全息技术英语作文

介绍全息技术英语作文Holographic technology is a cutting-edge innovationthat has revolutionized the way we perceive and interact with visual content. It creates three-dimensional images using light, and has a wide range of applications in various industries, including entertainment, healthcare, education, and more.One of the most exciting aspects of holographic technology is its potential to transform the entertainment industry. With holographic displays, performers can create stunning visual effects and immersive experiences for their audiences. This technology has the power to bring virtual characters and worlds to life in a way that was previously unimaginable.In the field of healthcare, holographic technology is being used to revolutionize medical imaging and training. Doctors can now use holographic images to better understand complex medical conditions, plan surgeries, and educatepatients about their treatment options. This has the potential to improve patient care and outcomes significantly.In the education sector, holographic technology is being used to create immersive learning experiences for students. By using holographic images and simulations, educators can bring abstract concepts to life and make learning more engaging and interactive. This can help students better understand and retain information, leading to improved academic performance.Another exciting application of holographic technology is in the field of design and engineering. Engineers and designers can use holographic images to visualize and manipulate 3D models of their projects, allowing them to make more informed decisions and streamline the design process. This has the potential to improve the efficiency and quality of their work significantly.Overall, holographic technology has the potential to revolutionize the way we interact with visual content invarious industries. Its ability to create immersive and interactive experiences makes it a powerful tool for entertainment, healthcare, education, design, and more. As the technology continues to advance, we can expect to see even more exciting applications and innovations in the future.。

NVIDIA显卡架构简介

NVIDIA显卡架构简介

An Introduction to Modern GPU ArchitectureAshu RegeDirector of Developer TechnologyAgenda•Evolution of GPUs•Computing Revolution•Stream Processing•Architecture details of modern GPUsEvolution of GPUs(1995-1999)•1995 –NV1•1997 –Riva 128 (NV3), DX3•1998 –Riva TNT (NV4), DX5•32 bit color, 24 bit Z, 8 bit stencil •Dual texture, bilinear filtering•2 pixels per clock (ppc)•1999 –Riva TNT2 (NV5), DX6•Faster TNT•128b memory interface•32 MB memory•The chip that would not die☺Virtua Fighter (SEGA Corporation)NV150K triangles/sec 1M pixel ops/sec 1M transistors16-bit color Nearest filtering1995(Fixed Function)•GeForce 256 (NV10)•DirectX 7.0•Hardware T&L •Cubemaps•DOT3 –bump mapping •Register combiners•2x Anisotropic filtering •Trilinear filtering•DXT texture compression • 4 ppc•Term “GPU”introducedDeus Ex(Eidos/Ion Storm)NV1015M triangles/sec 480M pixel ops/sec 23M transistors32-bit color Trilinear filtering1999NV10 –Register CombinersInput RGB, AlphaRegisters Input Alpha, BlueRegistersInputMappingsInputMappingsABCDA op1BC op2DAB op3CDRGB FunctionABCDABCDAB op4CDAlphaFunctionRGBScale/BiasAlphaScale/BiasNext Combiner’sRGB RegistersNext Combiner’sAlpha RegistersRGB Portion Alpha Portion(Shader Model 1.0)•GeForce 3 (NV20)•NV2A –Xbox GPU •DirectX 8.0•Vertex and Pixel Shaders•3D Textures •Hardware Shadow Maps •8x Anisotropic filtering •Multisample AA (MSAA)• 4 ppcRagnarok Online (Atari/Gravity)NV20100M triangles/sec 1G pixel ops/sec 57M transistors Vertex/Pixel shadersMSAA2001(Shader Model 2.0)•GeForce FX Series (NV3x)•DirectX 9.0•Floating Point and “Long”Vertex and Pixel Shaders•Shader Model 2.0•256 vertex ops•32 tex+ 64 arith pixel ops •Shader Model 2.0a•256 vertex ops•Up to 512 ops •Shading Languages •HLSL, Cg, GLSLDawn Demo(NVIDIA)NV30200M triangles/sec 2G pixel ops/sec 125M transistors Shader Model 2.0a2003(Shader Model 3.0)•GeForce 6 Series (NV4x)•DirectX 9.0c•Shader Model 3.0•Dynamic Flow Control inVertex and Pixel Shaders1•Branching, Looping, Predication, …•Vertex Texture Fetch•High Dynamic Range (HDR)•64 bit render target•FP16x4 Texture Filtering and Blending 1Some flow control first introduced in SM2.0aFar Cry HDR(Ubisoft/Crytek)NV40600M triangles/sec 12.8G pixel ops/sec 220M transistors Shader Model 3.0 Rotated Grid MSAA 16x Aniso, SLI2004Far Cry –No HDR/HDR ComparisonEvolution of GPUs (Shader Model 4.0)• GeForce 8 Series (G8x) • DirectX 10.0• • • • Shader Model 4.0 Geometry Shaders No “caps bits” Unified ShadersCrysis(EA/Crytek)• New Driver Model in Vista • CUDA based GPU computing • GPUs become true computing processors measured in GFLOPSG80 Unified Shader Cores w/ Stream Processors 681M transistorsShader Model 4.0 8x MSAA, CSAA2006Crysis. Images courtesy of Crytek.As Of Today…• • • • GeForce GTX 280 (GT200) DX10 1.4 billion transistors 576 mm2 in 65nm CMOS• 240 stream processors • 933 GFLOPS peak • 1.3GHz processor clock • 1GB DRAM • 512 pin DRAM interface • 142 GB/s peakStunning Graphics RealismLush, Rich WorldsCrysis © 2006 Crytek / Electronic ArtsHellgate: London © 2005-2006 Flagship Studios, Inc. Licensed by NAMCO BANDAI Games America, Inc.Incredible Physics EffectsCore of the Definitive Gaming PlatformWhat Is Behind This Computing Revolution?• Unified Scalar Shader Architecture• Highly Data Parallel Stream Processing • Next, let’s try to understand what these terms mean…Unified Scalar Shader ArchitectureGraphics Pipelines For Last 20 YearsProcessor per functionVertex Triangle Pixel ROP MemoryT&L evolved to vertex shadingTriangle, point, line – setupFlat shading, texturing, eventually pixel shading Blending, Z-buffering, antialiasingWider and faster over the yearsShaders in Direct3D• DirectX 9: Vertex Shader, Pixel Shader • DirectX 10: Vertex Shader, Geometry Shader, Pixel Shader • DirectX 11: Vertex Shader, Hull Shader, Domain Shader, Geometry Shader, Pixel Shader, Compute Shader • Observation: All of these shaders require the same basic functionality: Texturing (or Data Loads) and Math Ops.Unified PipelineGeometry(new in DX10)Physics VertexFutureTexture + Floating Point ProcessorROP MemoryPixelCompute(CUDA, DX11 Compute, OpenCL)Why Unify?Vertex ShaderPixel ShaderIdle hardwareVertex ShaderIdle hardwareUnbalanced and inefficient utilization in nonunified architectureHeavy Geometry Workload Perf = 4Pixel Shader Heavy Pixel Workload Perf = 8Why Unify?Unified ShaderVertex WorkloadPixelOptimal utilization In unified architectureUnified ShaderPixel WorkloadVertexHeavy Geometry Workload Perf = 11Heavy Pixel Workload Perf = 11Why Scalar Instruction Shader (1)• Vector ALU – efficiency varies • • 4 MAD r2.xyzw, r0.xyzw, r1.xyzw – 100% utilization • • 3 DP3 r2.w, r0.xyz, r1.xyz – 75% • • 2 MUL r2.xy, r0.xy, r1.xy – 50% • • 1 ADD r2.w, r0.x, r1.x – 25%Why Scalar Instruction Shader (2)• Vector ALU with co-issue – better but not perfect • DP3 r2.x, r0.xyz, r1.xyz } 100% • 4 ADD r2.w, r0.w, r1.w • • 3 DP3 r2.w, r0.xyz, r1.xyz • Cannot co-issue • 1 ADD r2.w, r0.w, r2.w • Vector/VLIW architecture – More compiler work required • G8x, GT200: scalar – always 100% efficient, simple to compile • Up to 2x effective throughput advantage relative to vectorComplex Shader Performance on Scalar Arch.Procedural Perlin Noise FireProcedural Fire5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 7900GTX 8800GTXConclusion• Build a unified architecture with scalar cores where all shader operations are done on the same processorsStream ProcessingThe Supercomputing Revolution (1)The Supercomputing Revolution (2)What Accounts For This Difference?• Need to understand how CPUs and GPUs differ• Latency Intolerance versus Latency Tolerance • Task Parallelism versus Data Parallelism • Multi-threaded Cores versus SIMT (Single Instruction Multiple Thread) Cores • 10s of Threads versus 10,000s of ThreadsLatency and Throughput• “Latency is a time delay between the moment something is initiated, and the moment one of its effects begins or becomes detectable”• For example, the time delay between a request for texture reading and texture data returns• Throughput is the amount of work done in a given amount of time• For example, how many triangles processed per second• CPUs are low latency low throughput processors • GPUs are high latency high throughput processors•GPUs are designed for tasks that can tolerate latency•Example: Graphics in a game (simplified scenario):•To be efficient, GPUs must have high throughput , i.e. processing millions of pixels in a single frame CPUGenerateFrame 0Generate Frame 1Generate Frame 2GPU Idle RenderFrame 0Render Frame 1Latency between frame generation and rendering (order of milliseconds)•CPUs are designed to minimize latency•Example: Mouse or keyboard input•Caches are needed to minimize latency•CPUs are designed to maximize running operations out of cache •Instruction pre-fetch•Out-of-order execution, flow control• CPUs need a large cache, GPUs do not•GPUs can dedicate more of the transistor area to computation horsepowerCPU versus GPU Transistor Allocation•GPUs can have more ALUs for the same sized chip and therefore run many more threads of computation•Modern GPUs run 10,000s of threads concurrentlyDRAM Cache ALU Control ALUALUALUDRAM CPU GPUManaging Threads On A GPU•How do we:•Avoid synchronization issues between so many threads?•Dispatch, schedule, cache, and context switch 10,000s of threads?•Program 10,000s of threads?•Design GPUs to run specific types of threads:•Independent of each other –no synchronization issues•SIMD (Single Instruction Multiple Data) threads –minimize thread management •Reduce hardware overhead for scheduling, caching etc.•Program blocks of threads (e.g. one pixel shader per draw call, or group of pixels)•Any problems which can be solved with this type of computation?Data Parallel Problems•Plenty of problems fall into this category (luckily ☺)•Graphics, image & video processing, physics, scientific computing, …•This type of parallelism is called data parallelism•And GPUs are the perfect solution for them!•In fact the more the data, the more efficient GPUs become at these algorithms •Bonus: You can relatively easily add more processing cores to a GPU andincrease the throughputParallelism in CPUs v. GPUs•CPUs use task parallelism•Multiple tasks map to multiplethreads•Tasks run different instructions•10s of relatively heavyweight threadsrun on 10s of cores•Each thread managed and scheduledexplicitly•Each thread has to be individuallyprogrammed •GPUs use data parallelism•SIMD model (Single InstructionMultiple Data)•Same instruction on different data•10,000s of lightweight threads on 100sof cores•Threads are managed and scheduledby hardware•Programming done for batches ofthreads (e.g. one pixel shader pergroup of pixels, or draw call)Stream Processing•What we just described:•Given a (typically large) set of data (“stream”)•Run the same series of operations (“kernel”or“shader”) on all of the data (SIMD)•GPUs use various optimizations to improve throughput:•Some on-chip memory and local caches to reduce bandwidth to external memory •Batch groups of threads to minimize incoherent memory access•Bad access patterns will lead to higher latency and/or thread stalls.•Eliminate unnecessary operations by exiting or killing threads•Example: Z-Culling and Early-Z to kill pixels which will not be displayedTo Summarize•GPUs use stream processing to achieve high throughput •GPUs designed to solve problems that tolerate high latencies•High latency tolerance Lower cache requirements•Less transistor area for cache More area for computing units•More computing units 10,000s of SIMD threads and high throughput•GPUs win ☺•Additionally:•Threads managed by hardware You are not required to write code for each thread and manage them yourself•Easier to increase parallelism by adding more processors•So, fundamental unit of a modern GPU is a stream processor…G80 and GT200 Streaming ProcessorArchitectureBuilding a Programmable GPU•The future of high throughput computing is programmable stream processing•So build the architecture around the unified scalar stream processing cores•GeForce 8800 GTX (G80) was the first GPU architecture built with this new paradigmG80 Replaces The Pipeline ModelHost Input Assembler Setup / Rstr / ZCull Geom Thread Issue Pixel Thread Issue128 Unified Streaming ProcessorsSP SP SP SPVtx Thread IssueSPSPSPSPSPSPSPSPSPSPSPSPTFTFTFTFTFTFTFTFL1L1L1L1L1L1L1L1L2 FB FBL2 FBL2 FBL2 FBL2 FBL2Thread ProcessorGT200 Adds More Processing PowerHost CPU System MemoryHost Interface Input Assemble Vertex Work Distribution Geometry Work Distribution Viewport / Clip / Setup / Raster / ZCull Pixel Work Distribution Compute Work DistributionGPUInterconnection Network ROP L2 ROP L2 ROP L2 ROP L2 ROP L2 ROP L2 ROP L2 ROP L2DRAMDRAMDRAMDRAMDRAMDRAMDRAMDRAM8800GTX (high-end G80)16 Stream Multiprocessors• Each one contains 8 unified streaming processors – 128 in totalGTX280 (high-end GT200)24 Stream Multiprocessors• Each one contains 8 unified streaming processors – 240 in totalInside a Stream Multiprocessor (SM)• Scalar register-based ISA • Multithreaded Instruction Unit• Up to 1024 concurrent threads • Hardware thread scheduling • In-order issueTPC I-Cache MT Issue C-CacheSP SP SP SP SP SP SP SPSFU SFU• 8 SP: Thread Processors• IEEE 754 32-bit floating point • 32-bit and 64-bit integer • 16K 32-bit registers• 2 SFU: Special Function Units• sin, cos, log, exp• Double Precision Unit• IEEE 754 64-bit floating point • Fused multiply-add DPShared Memory• 16KB Shared MemoryMultiprocessor Programming Model• Workloads are partitioned into blocks of threads among multiprocessors• a block runs to completion • a block doesn’t run until resources are available• Allocation of hardware resources• shared memory is partitioned among blocks • registers are partitioned among threads• Hardware thread scheduling• any thread not waiting for something can run • context switching is free – every cycleMemory Hierarchy of G80 and GT200• SM can directly access device memory (video memory)• Not cached • Read & write • GT200: 140 GB/s peak• SM can access device memory via texture unit• Cached • Read-only, for textures and constants • GT200: 48 GTexels/s peak• On-chip shared memory shared among threads in an SM• important for communication amongst threads • provides low-latency temporary storage • G80 & GT200: 16KB per SMPerformance Per Millimeter• For GPU, performance == throughput• Cache are limited in the memory hierarchy• Strategy: hide latency with computation, not cache• Heavy multithreading • Switch to another group of threads when the current group is waiting for memory access• Implication: need large number of threads to hide latency• Occupancy: typically 128 threads/SM minimum • Maximum 1024 threads/SM on GT200 (total 1024 * 24 = 24,576 threads)• Strategy: Single Instruction Multiple Thread (SIMT)SIMT Thread Execution• Group 32 threads (vertices, pixels or primitives) into warps• Threads in warp execute same instruction at a time • Shared instruction fetch/dispatch • Hardware automatically handles divergence (branches)TPC I-Cache MT Issue C-CacheSP SP SP SP SP SP SP SPSFU SFU• Warps are the primitive unit of scheduling• Pick 1 of 24 warps for each instruction slot• SIMT execution is an implementation choice• Shared control logic leaves more space for ALUs • Largely invisible to programmerDPShared MemoryShader Branching Performance• G8x/G9x/GT200 branch efficiency is 32 threads (1 warp) • If threads diverge, both sides of branch will execute on all 32 • More efficient compared to architecture with branch efficiency of 48 threadsG80 – 32 pixel coherence 48 pixel coherence 16 14 number of coherent 4x4 tiles 12 10 8 6 4 2 0% 20% 40% 60% 80% 100% 120% PS Branching EfficiencyConclusion:G80 and GT200 Streaming Processor Architecture• Execute in blocks can maximally exploits data parallelism• Minimize incoherent memory access • Adding more ALU yields better performance• Performs data processing in SIMT fashion• Group 32 threads into warps • Threads in warp execute same instruction at a time• Thread scheduling is automatically handled by hardware• Context switching is free (every cycle) • Transparent scalability. Easy for programming• Memory latency is covered by large number of in-flight threads• Cache is mainly used for read-only memory access (texture, constants).。

HARDWARE-ACCELERATED

HARDWARE-ACCELERATED

Revolutionary Visual Computing SolutionsHardware-Accelerated Pixel Read-Back Ultra-fast pixel read-back performance delivers massive host throughput, more than 10x the performance of previous generations of graphics systems.GPU ComputingNVIDIA CUDA provides a C languageenvironment and tool suite that unleashes new capabilities to solve complex, visualization challenges such as real-time ray tracing and interactive volume rendering.1NVIDIA PureVideo TechnologyNVIDIA PureVideo ™ technology is the combination of high-definition video processors and software that deliversunprecedented picture clarity, smooth video, accurate color, and precise image scaling for SD and HD video content. Featuresinclude, high-quality scaling, spatial temporal de-interlacing, inverse telecine, and high quality HD video playback from DVD.Features and BenefitsFull 128-Bit Precision Graphics Pipeline Enables mathematical computations to maintain high accuracy, resulting in unmatched visual quality.High-Quality Full-Scene Antialiasing (FSAA)Up to 32x FSAA dramatically reduces visual aliasing artifacts or “jaggies” at resolutions up to 2560 x 1600, resulting in highly realistic scenes. New rotated-grid FSAA algorithm (RG FSAA) delivers unprecedented quality and performance.High Precision, High Dynamic Range Imaging (HDR)Sets new standards for image clarity and quality through floating point capabilities in shading, filtering, texturing, and blending. Enables unprecedented quality of rendered images for visual effects processing.NVIDIA Unified ArchitectureIndustry’s first unified architecture designed to dynamically allocate geometry, shading, pixel, and compute processing power to deliver optimized GPU performance.1Dual Dual-Link Digital Display Connectors Dual dual-link TMDS transmitters support ultra-high-resolution panels (up to 2560 x 1600 @ 60Hz on each panel) − which result in amazing image quality producing detailed photorealistic images.3Essential for Microsoft Windows Vista Offering an enriched 3D user interface,increased application performance, and the highest image quality, NVIDIA Quadro graphics boards and NVIDIA ® OpenGL ICD drivers are optimized for 32- and 64-bit architectures to enable the best Windows ® Vista ™ experience.Technical SpecificationsNVIDIA QUADRO WORKSTATION GPU > 12-bit subpixel precision > Up to 128 textures per pass > Eight (8) multiple render targets > Fast 3D texture support > Jumbo (8K) texture support> Hardware-accelerated antialiased points and lines> Hardware OpenGL overlay planes> Hardware-accelerated two-sided lighting > Hardware-accelerated clipping planes > Third-generation occlusion culling > OpenGL quad-buffered stereo (3-pin sync connector)> Hardware-accelerated pixel read-back NEXT-GENERATION SHADING ARCHITECTURE> Full Shader Model 4.0 (OpenGL and DirectX 10) o Vertex Shader 4.0 o Geometry Shader 4.0 o Pixel Shader 4.0> Unlimited Shader Lengths> FP32 texture filtering and blending > Non-power-of-two texture supportNVIDIA CUDA Software Development Tools > C language compiler, profiler and emulation mode for debugging> Standard numerical libraries for FFT (Fast Fourier Transform) and BLAS (Basic Linear Algegra Subroutines)HIGH-LEVEL SHADER LANGUAGES > Optimized compilers for Cg, OpenGLSL, and Microsoft HLSL > OpenGL 2.1 and DirectX 10 support > Open source compilerHIGH-RESOLUTION ANTIALIASING > Up to 32x full-scene antialiasing (FSAA), up to 2560 x 1600> Rotated-grid FSAA significantly increases color accuracy and visual quality for edges, while maintaining performance UNIFIED DRIVER ARCHITECTURE > Single driver supports all products SUPPORTED PLATFORMS> Microsoft Windows ® Vista, XP, 2000 > Linux—Full OpenGL implementation, complete with NVIDIA and ARBextensions (complete XFree 86 drivers)> AMD64, Intel EM64TPROFESSIONAL CERTIFICATIONS Computer-Aided Design (CAD) /Computer-Aided Manufacturing (CAM) /Computer-Aided Engineering (CAE) Applications > AutoCAD > CATIA > DeltaGen > Inventor > PDMS > PLM> Pro / ENGINEER > Revit> Solid Edge > SolidWorks> and many more…Digital Content Creation (DCC) and Broadcast > 3ds Max > After Effects > Houdini > Illustrator > Lightwave > Maya> Premiere Pro > Softimage | XSI > and many more…Energy> Landmark> Paradigm GEO > Schlumberger Medical/Life Sciences > Accelyris > Tripos> Vital Images1 Available on NVIDIA Quadro FX 5600, 4700 X2, 3700, 1700, 570, 370, 3600M, 1600M, 570M, and 360M.2 Available on NVIDIA Quadro FX 5600, 5500, 4700 X2, 4600, 4500, 3700, 3500, and 3450.3 Available on NVIDIA Quadro FX 5600, 5500, 4700 X2, 4600, 3700, 3500, 1700, and 1500.For more information about NVIDIA Quadro, visit © 2007 NVIDIA Corporation. All rights reserved. NVIDIA, the NVIDIA logo, NVIDIA Quadro, Cuda, and SLI are trademarks and/or registered trademarks of NVIDIA Corporation.All company and product names are trademarks or registered trademarks of the respective owners with which they are associated. Features, pricing, availability, and specifications are all subject to change without notice. Images courtesy of Right Hemisphere, Landmark, UVPHACTORY, NVIDIA Corporation, and Vital Images,The industry’s leading workstation applications leverage these solutions to enable hardware-accelerated features not found in any other professional graphics solution.The Quadro professional products include a set of industry specialtysolutions that have been architected to enable advanced imaging visualization and broadcast applications - from multi-system scalability andsynchronization to uncompressed 12-bit HD-SDI video output.The NVIDIA Quadro ® family of professional solutionstakes the leading professional applications to a new level of interactivity by enabling unprecedented capabilities.Images courtesy of Right Hemisphere, Landmark, a brand of the Halliburton Drilling, Evaluation and Digital Solutions, UVPHACTORY, and Vital Images, Volvo Image Copyright © 2006 MFX / Percival Productions. www.mfx.se.NVIDIA Quadro Family | Sep 2007Ground-breaking Unified Architecture Delivers Unprecedented Performance The latest NVIDIA Quadro architecture takes application performance tonew levels by featuring the industry’sfirst unified architecture1. Designed to dynamically allocate geometry, shading, pixel, and compute processing power, the latest NVIDIA Quadro graphics boards deliver optimized Graphics Processing Unit (GPU) performance. The GPU pipeline efficiency is further multipliedby fast 3D and large texture transfers, NVIDIA’s crossbar memory architecture, enabling occlusion culling, lossless depth Z-buffer, and color compression. These elements combine to achieveunprecedented 3D performance: blazinggeometry performance, lightening-fastline performance and massive fill ratespowered by a dynamically configurablearray of thread processors. With ultra-fast pixel read-back performance,massive host throughput gains can beachieved for professional applications.However, the true measure of power isapplication performance and the newNVIDIA Quadro architecture doubles theperformance of the previous generation.Advanced ProgrammabilityEmpowers a New Classof ApplicationsThe latest NVIDIA Quadro FX graphicssolutions are the reference standard forShader Model 4.0 and next generationoperating systems enabling breakthroughultra-realistic, real-time visualizationapplications. Styling and productionrendering are integral functions of thedesign workflow and NVIDIA QuadroFX provides professionals the toolsto shorten the production processand enable faster time to market.The major CAD and DCC applicationvendors can take full advantage of theprogrammable NVIDIA Quadro architectureby enabling sophisticated shaders tosimulate a virtually unlimited range ofphysical characteristics, such as lightingeffects (dispersion, reflection, refraction,BRDF models) and even physical surfaceproperties (casting effects, porosity,molded surfaces). Real-time shaders allowaccurately matching visual images.All images have a smoother, moreappealing variation in color density, whichincreases visual realism and generatesphotorealistic rendered images.Certified for the HighestQuality Experience withthe Most DemandingWorkstation ApplicationsThe performance and power of theNVIDIA Quadro architecture arebuilt on a solid foundation of qualityengineering. This engineering excellenceis exemplified by the NVIDIA UnifiedDriver Architecture (UDA), which iscertified for quality by the entire spectrumof CAD and DCC applications.these effects to be combined and modifiedinteractively, something that is impossiblewith simple 2D static texture maps.Full 128-bit Floating PointPrecision Delivers the Industry’sHighest Workstation QualitySophisticated real-time effects typicallyinvolve multiple mathematical operations thatdemand high precision to maintain imagequality. The NVIDIA Quadro architecturefeatures true 128-bit IEEE floating pointprecision (32-bit fp per component),resulting in the highest level of accuracyand the ultimate in visual quality.The NVIDIA Quadro family delivers true16-bit and 32-bit floating point formats forThe Definition of Performance. The Standard for Quality.uncompromisedprofessional graphics to goThe NVIDIA Quadro FX professional solutions for mobile workstations deliver the fastest application performanceand the highest quality graphics. The NVIDIA Quadro FX mobile solutions enable the leading CAD, DCC, and visualization applications to solve the most complex professional visual computing challenges in a mobile form factor.integrated graphics to video solutionThe NVIDIA Quadro SDI solutions are ideal foron-air broadcast professionals across manyapplications, including virtual-set, sports, andweather news systems. The NVIDIA Quadro SDIsolution is the industry’s only fully integratedgraphics to video out product, and will compositelive video footage onto virtual backgrounds andsend the result to live video for TV broadcast. Thesolution also allows film production and post-production professionals to preview the results of3D compositing, editing, and color grading in realtime on HD broadcast monitors.c programming environmentfor the gpuThe NVIDIA CUDA™software development kitprovides a C language environment and toolssuite that unleashes new capabilities to solvecomplex, visualization challenges such asreal-time ray tracing and interactive volumerendering.1revolutionizingadvanced visualizationThe NVIDIA Quadro G-Sync deliversframe and genlock functionality tounprecedented levels of industrialrealism, visualization, and collaborativecapabilities. The NVIDIA Quadro G-Sync IIoption can be combined with the QuadroFX 5600 or 4600, and G-Sync I can becombined with the FX 5500 to provideadvanced multi-system visualizationand external signal synchronization.a quantum leap in visual computingThe NVIDIA Quadro Plex is a dedicatedvisual computing system (VCS) enablingbreakthrough levels of capability andproductivity for professionals ranging frommanufacturing designers and stylists toearth scientists to digital content creators.NVIDIA Quadro Plex provides the flexibility tobe deployed with any certified PCI Express®x16 platform. NVIDIA Quadro Plex achievesunmatched compute density, can bedeployed in a wide range of environments,and scales to meet the most demandingprofessional applications requirements.HP Mobile Workstation courtesy HP - image on screen courtesy ProE2000. Racetrack image © Sam Sharpe / The Sharpe Image / Corbis. Inside right page: Geographic imagery courtesy Landmark, a brand of the Halliburton Drilling, Evaluation and Digital Solutions. Video Wall image courtesy ORNL.scalable graphics performance NVIDIA Quadro graphics solutions feature NVIDIA® SLI™ multi-GPU technology2.A revolutionary platform innovation,SLI technology enables professional users to dynamically scale graphics performance, enhance image quality, and expand display real estate by combining multiple NVIDIA Quadro graphics solutions in a single system.Available NVIDIA Quadro Solutions Ultra-High-EndNVIDIA Quadro FX 5600 NVIDIA Quadro FX 5500 NVIDIA Quadro FX 4700 X2 High-EndNVIDIA Quadro FX 4600 NVIDIA Quadro FX 3700 NVIDIA Quadro FX 3500Mid-RangeNVIDIA Quadro FX 3450 NVIDIA Quadro FX 1700 NVIDIA Quadro FX 1500 Entry-LevelNVIDIA Quadro FX 570 NVIDIA Quadro FX 560 NVIDIA Quadro FX 550 NVIDIA Quadro FX 370 SpecialtyNVIDIA Quadro Plex VCS NVIDIA Quadro SDINVIDIA Quadro G-Sync MobileNVIDIA Quadro FX 3600M NVIDIA Quadro FX 1600M NVIDIA Quadro FX 570M NVIDIA Quadro FX 360M。

graphic device

graphic device

graphic deviceGraphic DeviceIntroduction:In today's digital world, graphic devices play a crucial role in various industries, including gaming, entertainment, design, and advertising. Graphic devices are hardware components that enable the transformation of digital instructions into meaningful visual output. They are responsible for creating and rendering images, videos, animations, and various graphical elements. This document provides a comprehensive overview of graphic devices, discussing their types, functionalities, and importance in modern technology.Types of Graphic Devices:Graphic devices come in different forms and serve diverse purposes. The following are some commonly used types of graphic devices:1. Graphics Processing Unit (GPU):The Graphics Processing Unit, commonly known as GPU, is an essential component in computers, gaming consoles, and smartphones. Its primary function is to process and render graphical data. A GPU comprises several cores and is highly specialized in performing complex mathematical and geometric calculations. With the evolution of GPUs, real-time rendering and advanced visual effects have become possible in various applications.2. Video Card:Also known as a display adapter, a video card is an expansion card that generates and outputs visual data to a display device, such as a monitor or a projector. It connects to the computer's motherboard and processes the graphical instructions received from the CPU. The video card utilizes its built-in GPU to render the visual content, which is then transmitted to the display device for user interaction.3. Integrated Graphics:Integrated graphics refers to the graphical processing capabilities integrated into the computer's central processing unit (CPU). Unlike discrete graphic devices like GPUs or video cards, integrated graphics are a part of the overall CPU architecture. They are generally less powerful than dedicated graphic devices but can handle basic graphics tasks, such as web browsing, office applications, and light gaming.Functionalities of Graphic Devices:Graphic devices offer various functionalities that are vital for creating and presenting visually appealing content. Some of the key functionalities are as follows:1. Rendering:Rendering is the process of generating visual output from digital data. Graphic devices, especially GPUs, excel at rendering complex graphics, 3D models, and simulations. They perform calculations to determine the position, color, texture, and lighting effects of each pixel, resulting in realistic and immersive visuals.2. Image Processing:Graphic devices also have image processing capabilities. They can manipulate digital images by applying filters, adjusting brightness, contrast, and color levels. Image processing techniques are widely used in photography, video editing, and special effects creation.3. Video Playback and Encoding:Graphic devices are responsible for smooth video playback on various devices. They decode video files and display them on the screen in real-time. Additionally, graphic devices assist in video encoding, converting video files into different formats or compressing them for efficient storage and transmission.4. Gaming Support:One of the primary uses of graphic devices is in gaming. They handle complex calculations and render high-quality visuals, enabling immersive gaming experiences. With features like real-time ray tracing and advanced shading techniques, modern graphic devices greatly enhance the realism and detail in games.Importance of Graphic Devices:Graphic devices have revolutionized the way we interact with technology and consume visual content. Their significance can be highlighted through the following points:1. Enhanced Visual Experience:From high-definition videos to lifelike game graphics, graphic devices are instrumental in creating immersive visualexperiences. They bring digital content to life, making it more engaging and enjoyable for users.2. Productivity and Creativity:Graphic devices empower professionals in various industries by providing tools for advanced design, 3D modeling, and video editing. These devices enable efficient workflows and allow individuals to unleash their creative potential.3. Real-Time Performance:The computing power of graphic devices, particularly GPUs, allows for real-time rendering and quick response times. This is crucial in applications like virtual reality (VR), simulations, and live event graphics.4. Technological Advancements:Graphic devices continue to advance at a rapid pace, driving innovation in several areas. The development of high-performance GPUs has paved the way for breakthroughs in artificial intelligence, machine learning, and cryptocurrency mining.Conclusion:In conclusion, graphic devices are indispensable components of modern technology. Their ability to generate, process, and render visual content revolutionizes industries such as gaming, entertainment, design, and advertising. With their advanced functionalities and constantly improving performance, graphic devices continue to shape the way we perceive and interact with the digital world.。

用于低功耗、非刚性平面应用的柔性AMOLED器件

用于低功耗、非刚性平面应用的柔性AMOLED器件
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NVIDIA Quadro K5200 8GB 图形卡说明书

NVIDIA Quadro K5200 8GB 图形卡说明书

NVIDIA Quadro K5200 8GB GraphicsNVIDIA Quadro K5200 8GB Graphics J3G90AA INTRODUCTIONThe NVIDIA Quadro K5200 gives you amazing application performance and capability, making it faster and easier toaccelerate 3D models, render complex scenes, and simulate large datasets. 8 GB of GDDR5 GPU memory with ultra-fast bandwidth allows you to create and render large, complex models and compute massive datasets. Plus, there’s the all-new display engine that drives up to four displays natively with DisplayPort 1.2 support for ultra-high resolutions likeadvantage of SDI video input/output support.The NVIDIA Quadro K5200 is set to take on the most demanding workflows whether in product development, high end styling, near real-time photorealistic rendering, media and entertainment creations, and simulations/analysis. PERFORMANCE AND FEATURES∙Amazing graphics and rendering performance delivered by the highest end Kepler based GPU technology∙8GB GDDR5 ultra-fast memory supporting a wide memory path to minimize memory access performance penalties∙New display engine drives up to four displays natively with DisplayPort 1.2 support for ultra-high resolutions like 4096x2160 @ 60 Hz with 30-bit color∙NVIDIA SYNC allows multiple displays to be frame-locked together and supports SDI video input/output∙Support for large-scale, ultra-high resolution visualization using the NVIDIA® SVS platform which includes NVIDIA® Mosaic, NVIDIA® Sync and NVIDIA® Warp/Blend technologies∙2304 CUDA parallel processing cores well suited to accelerate demanding parallel computing workloads using CUDA∙Comes complete with all necessary ISV application certificationsCOMPATIBILITYThe NVIDIA Quadro K5200 is supported in the following HP Z Workstations:- Z440, Z640, Z840SERVICE AND SUPPORTThe NVIDIA Quadro K5200 has a one-year limited warranty or the remainder of the warranty of the HP product in which it is installed. Technical support is available seven days a week, 24 hours a day by phone, as well as online support forums.Parts and labor are available on-site within the next business day. Telephone support is available for parts diagnosis and installation. Certain restrictions and exclusions apply.TECHNICAL SPECIFICATIONSForm Factor Dimensions: 4.376” H x 10.5” LDual Slot, Full HeightCooling: ActiveWeight: 880 grams (without extender)Graphics Controller NVIDIA Quadro K5200GPU: GK110-850-B1 with 2304 CUDA coresPower: 150 WattsBus Type PCI Express 3.0 x16Memory Size: 8GB GDDR5Memory bandwidth: 192GB/sMemory Width: 256-bitConnectors 1 DVI-I1 DVI-D2 DisplayPort 1.2aFactory configured option: No adapter included with card.After market option kit: No adaptor included with card.Additional DVI to VGA, DisplayPort to VGA, DisplayPort to DVI, and DisplayPort to Dual-Link DVIadapters available as accessoriesMaximum Resolution DisplayPort:- up to 4096 x 2160 x 30 bpp @ 60Hz- supports High Bit Rate 2 (HBR2) and Multi-Stream Transport (MST)DL-DVI(I) output:- up to 2560 x 1600 x 32 bpp @ 60HzSingle Link-DVI(I) output:- up to 1920 x 1200 x 32 bpp @ 60HzVGA (via adapter cable):- 2048 × 1536 × 32 bpp at 85 HzImage Quality Features 10-bit internal display processing (hardware support for 10-bit scanout for both windoweddesktop and full screen, only available on Windows with Aero disabled and Linux).NVIDIA® 3D Vision™ technology, 3D DLP, Interleaved, and other 3D stere o format support.Full OpenGL quad buffered stereo support.Support for NVIDIA® Quadro® Mosaic, NVIDIA® nView® multi-display technology, NVIDIA®Enterprise Management Tools.Support for large-scale, ultra-high resolution visualization using the NVIDIA® SVS platform whichincludes NVIDIA® Mosaic, NVIDIA® Sync and NVIDIA® Warp/Blend technologies.Display Output Maximum number of displays- 4 direct attached monitors- 4 using DP 1.2a with MST and HBR2 enabled monitorsMaximum number of DisplayPort displays possible (may require MST and/or HBR2):- 4 1920x1200- 4 2560x1600- 2 4096x2160Maximum number of monitors across all available Quadro K5200 outputs is 4.Shading Architecture Shader Model 5.0Supported Graphics APIs OpenGL 4.4DirectX 11API su pport for NVIDIA’s CUDA™ C, CUDA C++, DirectCompute 5.0, OpenCL, Java, Python, Fortran Available Graphics Drivers Microsoft Windows 8.1Microsoft Windows 8Microsoft Windows 7Linux - Full OpenGL implementation, complete with NVIDIA and ARB extensionsHP qualified drivers may be preloaded or available from the HP support Web site:/country/us/en/support.htmlNotes 1. Factory configured Quadro K5200 does not include a video cable adapter. Video cable adaptersmust be ordered separately.2. A total maximum of 4 active monitors are supported across all display output types. This maybe accomplished by using daisy chained DisplayPort 1.2 displays (displays must support MST andHBR2).3.Configurations of a single Quadro K5200 graphics card in HP Z440 Workstation require the HPZ440 Fan and Front Card Guide Kit, configurable from the factory (CTO PN: G8T99AV) or as anAftermarket Option (AMO PN: J9P80AA).Summary of ChangesDate of change: Version History: Description of change:Sept 15, 2014 Version 1 Added Migrate to current template, add product photo December 3, 2014 From v1 to v2 Added Note for Z440 configurations.May 1, 2015 From v2 to v3 Changed Notes for Technical Specification section© Copyright 2015 Hewlett-Packard Development Company, L.P.The only warranties for HP products and services are set forth in the express warranty statements accompanying such products and services. Nothing herein should be construed as constituting an additional warranty. HP shall not be liable for technical or editorial errors or omissions contained herein. The information contained herein is subject to change without notice.。

阿利亚罗K-0169 Rev B 12通道多功能板说明书

阿利亚罗K-0169 Rev B 12通道多功能板说明书

12 Channels Multi-Function Board with AMPAL-1010 with AMP for SLSCThis document describes the SLSC AL-1010 with AMP for National Instruments SLSC-12001 chassis.OverviewThe AL-1010 is a 12-channel multi-function module to be connected between the Device Under Test (DUT) and the instrumentation part of the test system.The board is recommended for systems requiring high flexibility on the pin configurations.AL-1010 is made for National Instruments (NI) Switch Load Signal Conditioning (SLSC) system. The board is made to interface with NI PXI and/or Compact-RIO instrumentation devices for the purposes of test and validation of Electronic Control Unit (ECU) software and hardware. Custom device for VeriStand is included for Hardware-In-the-Loop applications.For larger applications, Aliaro Configurator is recommended for channel configuration. Contact Aliaro for additional information.C ontents Overview (1)Description (3)Features (3)Detailed description (4)Installation (5)Electromagnetic Compatibility (5)Unpacking the module (5)Hardware Installation (6)Maintenance (7)Safety (7)Before using the AL-1010 (7)System Check (7)Calibration (7)Specification (8)Definition and conditions (8)Environmental Characteristics (8)Physical characteristics (8)Front connectors (J1 & J2) (9)General specification (10)Fault Insertion (10)Signal conditioning (All channels) (10)Digital I/O (10)Analogue Out – Amplifier (10)Functions (11)LabVIEW (11)Veristand (11)Configuration and Accessories (12)RTI Backplane (12)AL-1010 RTI Terminal Block (14)Safety Guidelines (15)Product Certifications and Declarations (15)CE Compliance (15)Electromagnetic Compatibility Standards (15)Environmental Management (16)Waste Electrical and Electronic Equipment (WEEE) (16)DescriptionThe AL-1010 provide multiple functions for fault insertion, signal conditioning and digital I/O, including pulsed (PWM) signals. The AL-1010 is fitted in pair through the RTI-backplane AL-1010-RTI.The AL-1010 RTI backplane is needed to reach fully flexibility and enables easy connection to NI PXIe and/or Compact-RIO instrumentation devices. Additional with add-on boards the functionality can be expanded further.Features960V, 10A per channel912 independent and isolated channels in three banks9Two common buses per bank with switches to each channel9Brake up switch for each channel9Programmable level threshold on each channel9Parallel connection possibility for high current signals9LabVIEW driver is available.9Custom Device is available.Detailed descriptionFigure 1, AL-1010 Block diagramThe AL-1010 board provides fault insertion, signal conditioning and digital I/O.Fault insertion functions:- Open circuit (DUT to Load)- Short to + and – (DUT to AUX 1 or AUX2)Signal conditioning functions:- Digital input (from DUT) signal conditioning using adjustable threshold (-28 - +28V) - Analogue signal (to DUT) with amplification (4 channels)- Analogue signal (from DUT)Digital I/O functions:- Read digital status (from DUT) using adjustable threshold- Read PWM signals (from DUT) using adjustable threshold (Frequency and duty cycle) - Generate digital signals (to DUT) using AUX1 (+) and AUX2 (-)- Generate PWM signals (To DUT) using AUX1 (+) and AUX2 (-)InstallationElectromagnetic CompatibilityThis product is intended for use in industrial locations. However, harmful interference may occur in some installations, when the product is connected to a peripheral device or test object, or if the product is used in residential or commercial areas. To minimize interference with radio and television reception and prevent unacceptable performance degradation, install, and use this product in strict accordance with the instructions in the product documentation. Furthermore, any modifications to the product not expressly approved by Aliarocould void your authority to operate it under your local regulatory rules.C aution To ensure the specified EMC performance, operate this product only withShielded cables and accessories.Unpacking the moduleCarefully inspect the shipping container and the module for damage.Check for visible damage to the exterior and interior of the damage.If damage appears to have been caused during shipment file a claim with the carrier.Retain the packing material for possible inspection and/or reshipment.If the chassis is damaged, do not install it and contact Aliaro.Hardware InstallationTo set up and use the module you need the following items:Hardwarex SLSC-12001 chassisx SLSC AL-1010 module(s)x SLSC AL-1010 RTIx SLSC AL-1010 RTI CBx Power cablex Power input connectorx Grounding wirex Grounding lugToolsx Screwdriver as needed for your applicationx Wire stripperDocumentationSLSC-12001 Chassis Getting Started Guide and SpecificationsC aution:Do not touch the contacts or remove the I/O boards or cables while the systemis energized.The SLSC chassis and the AL-1010 do not support hot plug-in. The entirechassis must be powered off when a module is inserted or removed.Procedure:1.Power off the main DC power source or disconnect the power source from the chassisbefore installing any modules or RTIs.2.Ensure that the chassis is powered off. The POWER LED should be off. If thePOWER LED is not off, do not proceed until it is off.3.Loosen the screws on the upper rear panel of the chassis.4.Position the RTI backplane at the desired slot and insert the securing screws, but do notfully tighten them.5.Insert a AL-1010 module into the same slot as its corresponding RTI while firmly holdingthe RTI in place until the RTI is firmly connected to the module.6.Repeat steps 4 and 5 for all required RTIs.7.Fully tighten the screws for all RTIs and the upper rear panel of the chassis. Note Waitinguntil all RTIs and modules are installed to fully tighten the screws ensures properalignment for future connections between modules and RTIs.8.Fully tighten the two module mounting screws on each newly installed module.9.Power on the SLSC chassisMaintenanceSafetyC aution Observe all instructions and cautions in the user documentation. Using themodel in a manner not specified can damage the model and compromise the built-insafety protection. Return damaged models to Aliaro for repair.Before using the AL-1010All input characteristics are DC, ACrms, or a combination unless otherwise specified. Maximum switching voltage (any polarity) 1100Vpeak. Every card provides a fully capable fault insertion with external control during simulations or testing. Relays can be configured with Aliaro Configurator, VeriStand and LabVIEWNote Steady state voltages applied to the AL-1010between any two I/O connector pins in excess of the maximum switching voltage specification may damage the module Note Signal connections through the AL-1010are intended to go through the DUTn pin connections. Signal paths that do not use the DUTn pin connections bypass the internal overcurrent limiting features and may exceed the module's thermal capabilities.System CheckThis chapter requires LabVIEW development and installation of LabVIEW drivers.To identify and control that the cards are inserted and work properly with the right firmware, LabVIEW provides basic VI scripts to check SLSC cards mounted in chassis1.Open LabVIEW and select “Help” in the top menu bar and press “FindExamples…” (This opens a new window with pre-built VI (Virtual Instruments) for different applications).2.Switch to the “Search” tab and enter keyword “SLSC” and double click.3.In the new filtered table (to the right) find and select VI called “Configuration.vi”.This VI can located every card(s) that is online in SLSC chassis.4.To find the newly inserted cards look for the SLSC chassis IP-address (in thetable to the right).Count the showing card(s) in the table and make up that there are as manymounted in the SLSC chassis as there are in the VI table for that specific IPaddress. (Can be 1 up to 11 cards per SLSC chassis)CalibrationRecommended warm-up time30 minCalibration interval Not required, recommended on system levelSpecificationDefinition and conditionsWarranted specifications describe the performance of a model under stated operating conditions and are covered by the model warranty.The following characteristic specifications describe values that are relevant to the use of the model under stated operating conditions but are not covered by the model warranty.x Typical specifications describe the performance met by most models.x Nominal specifications describe an attribute that is based on design, conformance testing, or supplemental testing.Specifications are Typical unless otherwise noted.Specifications are valid under the following conditions unless otherwise noted.The AL-1010 module is mounted in an SLSC chassis with the recommended cooling clearances and using a power supply that meets the specifications provided in the chassis user guide. For the entire temperature range of the chassis.Note These specifications only apply to the product as provided by Aliaro. Modifications to the module may invalidate these. Be certain to verify the performance of modifiedmodules.Caution Observe all instructions and cautions in the user documentation. Using themodel in a manner not specified can damage the model and compromise the built-insafety protection. Return damaged models to Aliaro for repair.Environmental CharacteristicsTemperatur e an d HumidityOperating temperature0 °C to 40 °CStorage temperature range-40 °C to 85 °COperating relative humidity range10% to 90%, noncondensingStorage relative humidity range5% to 95%, noncondensingPhysical characteristicsCategory Condition ValueModule Dimensions Excluding front handle144.32mm x 30.48mm x 281 mm(H x W x D)Front Panel Connector1x female Weidmuller 32 highdensityFront connectors (J1 & J2)See fig 1 for description of the functions.C autionThe pins are not indestructible, ports and pins will tare if not treated with care.PinDUT(J1) LOA D (J2) 1DUT Ch 1Load Ch 12DUT Ch 2Load Ch 23DUT Ch 3Load Ch 34DUT Ch 4Load Ch 45DUT Ch 5Load Ch 56DUT Ch 6Load Ch 67DUT Ch 7Load Ch 78DUT Ch 8Load Ch 89DUT Ch 9Load Ch 910DUT Ch 10Load Ch 1011DUT Ch 11Load Ch 1112DUT Ch 12Load Ch 1213DUT_GND AUX 1C 14ISO_GND AUX 2A 15AUX 1A AUX 2B 16AUX 1B AUX 2C(J1)(J2)General specificationC ategory C ondition V alueNo of channels 12No of banks 3Power supply 24VDC, +/-5%Channel to channel isolation (50Ω/100kHz) 40dBMax. Operating Voltage Any pin + 60VMin. Operating Voltage Any pin - 60VFault InsertionCategory Condition Specified value Typical valueMax. continuously current DUT to LoadDUT to AUX 1 /2All other pins 10 A (40A using parallel channels) 10 A (40A using parallel channels)100 mAMax peak current (<100 ms, 25 °C)DUT to LoadDUT to AUX 1/240A/50ms40A/50ms*Notice Exceeding the maximum pulsed current can damage the module. Signal conditioning (All channels)Category ValueThreashold, range -28- +28VThreashold, resolution 0,1VThreshold, bandwidth 20 kHzDigital I/OCategory ValuePWM frequency range 100-65 000 μs (15 hz -10 kHz) PWM frequency resolution 1 usPWM frequency accuracy +/- 25 ppmPWM duty cycle range 10-90 %PWM duty cycle resolution 1 usAnalogue Out – AmplifierCategory ValueNo of channels 4 (DUT ch 1-4)Power supply(Separate isolated supply)24VDC, +/-5%Current drive 200mA per channelFunctionsLabVIEWContact Aliaro Team for separate LabVIEW drivers.(Equal functions to the custom device in Veristand, see below)VeristandThe custom device provides following functions for the AL-1010 board:Parameter Description Unit RangeLoad Connect/disconnect selected channelto Aux 1 (Off/On) 0; 1Aux1 Connect/disconnect selected channelto Aux 1 (Off/On) 0; 1selectedchannelAux2 Connect/disconnectto Aux 2 (Off/On) 0; 1Threshold Sets the digital threshold of selected-28,0+28,0–(V)channel VoltDI Reads the logic value of the channelbased upon the threshold settings (Off/On) 0; 1Amplifier functions (Ch 1-4)Amp-Enable Enables the amplifier function (Off/On) 0; 1foramplificationtheGain Defineseach channel (Off/On) 0; 1PWM functionsPWM_Aux1 Enables PWM function using Aux1for selected channel (Off/On) 0; 1PWM_Aux2 Enables PWM function using Aux1for selected channel (Off/On) 0; 1PWM_Load Enables PWM function using Aux1for selected channel (Off/On) 0; 1PWM_Period Sets period for selected channel Time [μs] 100-65 000 μsDI-PWM_DutyCycle Sets duty cycle when using PWMfor selected channel % 10-100%Configuration and AccessoriesFor most applications, the AL-1010 needs to be configured with a backplane (AL-1010 RTI) combined with a connection block (AL-1010 RTI CB). The AL-1010 provides 2 expansion slots for add-on boards such as customized functionalities needed for the customer’s project.RTI BackplaneThe AL-1010 RTI is used to connect to two (2) SLSC modules (Left and Right) on the same board.Connector pinoutsJ1:1J1:4J1:2J1:3J1:6J1:5J2J3J4J3 Left board / J4 Right board (ERNI 064004 connector)P in S ignal T e rminal P in S ignal T erm i na l A1 Digital in, channel 1 J4:1 B1 Digital in, channel 7 J6:1A2 Digital in, channel 2 J4:2 B2 TS GND J8:4A3 Digital in, channel 3 J4:3 B3 Digital in, channel 8 J6:2A4 Digital in, channel 4 J4:4 B4 TS GND J8:4A5 Digital in, channel 5 J4:5 B5 Digital in, channel 9 J6:3A6 Digital in, channel 6 J4:6 B6 DUT GND J8:3A7 Analog in, channel 7 J2:1 B7 Digital in, channel 10 J6:4A8 Analog in, channel 8 J2:2 B8 DUT GND J8:3A9 Analog in, channel 9 J2:3 B9 Digital in, channel 11 J6:5A10 Analog in, channel 10 J2:4 B10 DUT Ref J8:1A11 Analog in, channel 11 J2:5 B11 Digital in, channel 12 J6:6A12 Analog in, channel 12 J2:6 B12 DUT Ref J8:1A13 DUT Reference J8:1 B13 Analog out, channel 7 J7:1A14 Analog in, channel 1 J3:1 B14 DUT Ref J8:1A15 Analog in, channel 2 J3:2 B15 Analog out, channel 8 J7:2A16 Analog in, channel 3 J3:3 B16 DUT Ref J8:1A17 Analog in, channel 4 J3:4 B17 Analog out, channel 9 J7:3A18 Analog in, channel 5 J3:5 B18 DUT GND J8:1A19 Analog in, channel 6 J3:6 B19 Analog out, channel 10 J7:4A20 Analog out, channel 1 J5:1 B20 TS GND J8:4A21 Analog out, channel 2 J5:2 B21 Analog out, channel 11 J7:5A22 Analog out, channel 3 J5:3 B22 TS GND J8:4A23 Analog out, channel 4 J5:4 B23 Analog out, channel 12 J7:6A24 Analog out, channel 5 J5:5 B24 NC (Internal use) J8:5A25 Analog out, channel 6 J5:6 B25 NC (Internal use) J8:6AL-1010 RTI Terminal BlockThe AL-1010 RTI Terminal Block is used to connect to two (2) SLSC modules (Left and Right) on the same board.System Overview of AL-1010 RTI and Terminal BlocksAL-1010 Terminal block Kadro-B037 AL1010 RTI TBSafety GuidelinesC autionsEnsure that hazardous voltage wiring is performed only by qualified personnel adhering to local electrical standards.Do not mix hazardous voltage circuits and human-accessible circuits on the same module. When device terminals are hazardous voltage LIVE, you must ensure that devices and circuits connected to the device are properly insulated from human contact.All wiring must be insulated for the highest voltage used.Product Certifications and DeclarationsRefer to the product Declaration of Conformity (DoC) for additional regulatory compliance information.To obtain product certifications and the DoC for Aliaro products, visit / certification.CE ComplianceThis product meets the essential requirements of applicable European Directives, as follows: x2014/35/EU; Low-Voltage Directive (safety)x2014/30/EU; Electromagnetic Compatibility Directive (EMC)x2011/65/EU; Restriction of Hazardous Substances (RoHS)Electromagnetic Compatibility StandardsThis product meets the requirements of the following EMC standards for electrical equipment for measurement, control, and laboratory use:x EN 55011-2009 Industrial, scientific and medical equipment - Radio-frequency disturbance characteristics - Limits and methods of measurement CISPR 11:2009x EN 55032:2012 Electromagnetic compatibility of multimedia equipment - Emission requirements CISPR 32:2012x EN 61326-1-2013 Electrical equipment for measurement, control and laboratory use - EMC requirements - Part 1: General requirements IEC 61326-1:2012Environmental ManagementAliaro is committed to designing and manufacturing products in an environmentally responsible manner. Aliaro recognizes that eliminating certain hazardous substances from our products is beneficial to the environment and to Aliaro customers. For additional environmental information, refer to the Minimize Our Environmental Impact web page at /environment.This page contains the environmental regulations and directives with which Aliaro complies, as well as other environmental information not included in this document.Waste Electrical and Electronic Equipment (WEEE)EU Customers At the end of the product life cycle, all Aliaro products must be disposed of according to local laws and regulations.For more information about how to recycle Aliaro products in your region, visit/environment/weee。

NVIDIA ConnectX-7 商品说明书

NVIDIA ConnectX-7 商品说明书

Accelerate Software-Defined Networking Provide Security from Edge to CoreNVIDIA ASAP2 technology accelerates software-defined networking, delivering line-rate performance with no CPU penalty.Hardware engines in ConnectX-7 offload and accelerate security, with in-line encryption/decryption of TLS, IPsec, and MACsec.Enhance Storage Performance Enable Precision TimingConnectX-7 enables high-performance storage and data access with RoCE and GPUDirect Storage and accelerates NVMe-oF over both RoCE and TCP.ConnectX-7 provides extremely accurate time synchronization for data-center applications and timing-sensitive infrastructures.NVIDIA CONNECTX-7 400G ETHERNETSMART ACCELERATION FOR CLOUD, DATA-CENTER AND EDGEACCELERATED NETWORKING AND SECURITY FOR THE MOST ADVANCED CLOUD AND AI WORKLOADSThe NVIDIA® ConnectX®-7 SmartNIC is optimized to deliver accelerated networking for modern cloud, artificial intelligence, and traditional enterprise workloads. ConnectX-7 provides a broad set of software-defined, hardware accelerated networking, storage, and security capabilities which enable organizations to modernize and secure their IT infrastructures.Extending the tradition of NVIDIA’s industry leading innovation for networking, ConnectX-7, is available in 1, 2, or 4-port configurations and delivers up to 400Gb/s of bandwidth. With features such as NVIDIA ASAP2 - Accelerated Switching and Packet Processing®, advanced RoCE, NVIDIA GPUDirect® Storage, and in-line hardware acceleration for TLS/IPsec/MACsec encryption/decryption, ConnectX-7 empowers agile and high-performance solutions from edge to core data centers to clouds, all while enhancing network security and reducing the total cost of ownership.Available in PCIe card and OCP3.0 form factors, ConnectX-7 empowers solutions for cloud, hyperscale, and enterprise networking.PRODUCT SPECIFICATIONSMaximum TotalBandwidth400GbESupported EthernetSpeeds10/25/40/50/100/200/400GbE Number ofNetwork Ports1/2/4Network InterfaceTechnologiesNRZ (10/25G) / PAM4(50/100G)Host Interface PCIe Gen5.0 x16/ x32Cards Form Factors PCIe FHHL/ HHHL,OCP3.0 SFF Network Interfaces SFP56, QSFP56,QSFP56-DD,QSFP112, SFP112NVIDIA CONNECTX-7 | DATASHEET | APR21Network Interface>Up to 4 network ports supporting NRZ, PAM4 (50G and 100G), in various ports configurations:>1 x 10/25/40/50/100/200/400GbE>2 x 10/25/40/50/100/200/400GbE>4 x 10/25/40/50/100/200GbE>Up to 400Gb/s total bandwidthHost Interface>32 lanes of PCIe Gen 5.0, compatible with PCIe Gen 2/3/4>Integrated PCI switch>NVIDIA Multi-Host™ (up to 8 hosts)and NVIDIA Socket Direct™>MSI/MSI-X mechanisms>Advanced PCIe capabilities Networking>RoCE, Zero Touch RoCE>ASAP² - Accelerated Switch and Packet>Processing® for SDN and VNF acceleration >Single Root I/O Virtualization (SR-IOV)>VirtIO acceleration>Overlay network acceleration:VXLAN, GENEVE, NVGRE>Programmable flexible parser:user-defined classification>Connection tracking (L4 firewall)>Flow mirroring, sampling and statistics>Header rewrite>Hierarchical QoS>Stateless TCP offloadsVNF Acceleration>Hardware offload programmable pipeline:>Packet classification on network layersL2 to L4 and tunneled traffic such as GTPand VXLAN>Packet dispatching to multiple cores>Multi-threaded API for concurrent updateof offloaded rules>ASAP2 accelerations/actions: counters,QoS, NAT, aging, mirroring, sampling,flow tag>Hairpin flow for full hardware offload>Highly-scalable number of classificationsand actions>Application access to hardware statistics>Application access to crypto offloadsCyber Security>IInline hardware IPsec encryptionand decryption>AES-GCM 128/256-bit key>IPsec over RoCE>Inline hardware TLS encryptionand decryption>AES-GCM 128/256-bit key>Inline hardware MACsec encryption anddecryption>AES-GCM 128/256-bit key>AES-GCM-XPN 128/256-bit key>Data-at-rest AES-XTS encryptionand decryption>AES-XTS 256/512-bit key>Platform security>Secure boot with hardware root-of-trust>Secure firmware update>On-board flash encryptionAdvanced Timing andSynchronization>Advanced PTP>IEEE 1588v2 (any profile)>Meets G.8273.2 Class C standard>PTP hardware clock (PHC) (UTC format)>12 nanosecond accuracy>Line-rate hardware timestamp(UTC format)>SyncE>Meets G.8262.1 (eEEC)>Configurable PPS In and configurablePPS Out>Time-triggered scheduling>PTP-based packet pacing>Time-based SDN acceleration (ASAP2)Storage Accelerations>NVMe™ over Fabrics (NVMe-oF) storagetarget offloads>NVMe-oF™ over TCP/RoCE acceleration>Storage protocols: iSER, NFSoRDMA, SMBDirect, NVMe-oF™, and moreHPC / AI>All-to-All engine>NVIDIA GPUDirect>NVIDIA GPUDirect StorageManagement and Control>SMBus 2.0>Network Controller SidebandInterface (NC-SI)>NC-SI, MCTP over SMBus and MCTPover PCIe - Baseboard ManagementController interface>PLDM for Monitor and Control DSP0248>PLDM for Firmware Update DSP026>I2C interface for device controland configuration>General Purpose I/O pins>SPI interface to flash>JTAG IEEE 1149.1 and>IEEE 1149.6Remote Boot>Remote boot over Ethernet>Remote boot over iSCSI>UEFI support for x86 and Arm servers>PXE bootForm Factors and Options>PCIe HHHL/FHHL>OCP 3.0 SFFFEATURESTo learn more about the NVIDIA ConnectX SmartNICs visit /en-us/networking/ethernet-adapters/© 2021 NVIDIA Corporation. All rights reserved. NVIDIA, the NVIDIA logo, ConnectX, ConnectX-7, GPUDirect, Multi-Host, Socket Direct, and ASAP2 - Accelerated Switch and Packet Processing are trademarks and/or registered trademarks of NVIDIA Corporation in the U.S. and other countries. Other company and product names may be trademarks of the respective companies with which they are associated. MAY21.。

KSZ9021RN to KSZ9031RNX Migration Guide

KSZ9021RN to KSZ9031RNX Migration Guide

KSZ9021RN to KSZ9031RNXMigration GuideRev. 1.1IntroductionThis document summarizes the hardware pin and software register differences for migrating from an existing board design using the KSZ9021RN PHY to a new board design using the KSZ9031RNX PHY. For hardware and software details, consult reference schematic and data sheet of each respective device.Data sheets and support documentations can be found on Micrel’s web site at: .Differences SummaryTable 1 summarizes the supported device attribute differences between KSZ9021RN and KSZ9031RNX PHY devices.Device Attribute KSZ9021RN KSZ9031RNXReduced Gigabit Media Independent Interface (RGMII) RGMII Version 1.3 (power-up default) using off-chip data-to-clock delays with register options to:•Set on-chip (RGMII Version 2.0) delays•Make adjustments and corrections to TXand RX timing pathsRGMII Version 2.0 (power-up default) using on-chip data-to-clock delays with register options to:•Set off-chip (RGMII Version 1.3) delays•Make adjustments and corrections to TXand RX timing pathsTransceiver (AVDDH)Voltage3.3V only 3.3V or 2.5V (commercial temperature only)Digital I/O (DVDDH)Voltage3.3V or 2.5V 3.3V, 2.5V or 1.8VIndirect Register Access Proprietary (Micrel defined) –Extended Registers IEEE defined –MDIO Manageable Device (MMD) RegistersEnergy-Detect Power-Down (EDPD) Mode Not Supported Supported for further power consumptionreduction when cable is disconnected; Disabledas the power-up default and enable using MMDregisterIEEE 802.3azEnergy Efficient Ethernet (EEE) Mode Not Supported Supported with:•Low Power Idle (LPI) mode for1000Base-T and 100Base-TX•Transmit Amplitude reduction for10Base-T (10Base-Te)•Associated MMD registers for EEEWake-on-LAN (WOL) Not Supported Supported with:•Wake-up using detection of Link Status,Magic Packet, or Custom-Packet•PME_N interrupt output signal•Associated MMD registers for WOL Table 1. Summary of Device Attribute Differences between KSZ9021RN and KSZ9031RNXPin DifferencesTable 2 summarizes the pin differences between KSZ9021RN and KSZ9031RNX PHY devices. Pin #KSZ9021RNKSZ9031RNXPin NameType Pin FunctionPin NameTypePin Function1 AVDDH P 3.3V analog V DD AVDDH P 3.3V/2.5V (commercial temp only) analog V DD 12 AVDDH P 3.3V analog V DD AVDDH P 3.3V/2.5V (commercial temp only) analog V DD 13VSS_PSGndDigital groundNC–No connectThis pin is not bonded and can be connected to digital ground for footprint compatibility with the Micrel KSZ9021RN Gigabit PHY.16 DVDDH P3.3V / 2.5V digital V DD DVDDH P 3.3V, 2.5V, or 1.8V digital V DD_I/O 17 LED1 /PHYAD0I/OLED Output:Programmable LED1 OutputConfig Mode:The pull-up/pull-down value is latched as PHYAD[0] during power-up / reset.LED1 /PHYAD0 /PME_N1I/O LED1 output:Programmable LED1 outputConfig mode:The voltage on this pin issampled and latched during the power-up/reset process to determine the value of PHYAD[0].PME_N output:Programmable PME_N output (pin option 1). This pin function requires an external pull-up resistor to DVDDH (digital V DD_I/O ) in a range from 1.0k Ω to 4.7k Ω. When asserted low, this pin signals that a WOL event has occurred.When WOL is not enabled, this pin function behaves as per the KSZ9021RN pin definition.This pin is not an open-drain for all operating modes.34 DVDDH P3.3V / 2.5V digital V DD DVDDH P 3.3V, 2.5V, or 1.8V digital V DD_I/O38 INT_N O Interrupt OutputThis pin provides aprogrammable interrupt output and requires an external pull-up resistor to DVDDH in the range of 1K to 4.7K ohms for active low assertion.INT_N/O Interrupt OutputThis pin provides aprogrammable interrupt output and requires an external pull-up resistor to DVDDH in the range of 1K to 4.7K ohms for active low assertion.This pin is an open-drain.PME_N2 PME_N output: Programmable PME_N output (pin option 2). When asserted low, this pin signals that a WOL event has occurred.When WOL is not enabled, this pin function behaves as per the KSZ9021RN pin definition. This pin is not an open-drain for all operating modes.40 DVDDH P 3.3V / 2.5V digital V DD DVDDHP3.3V, 2.5V, or 1.8V digitalV DD_I/O47 AVDDH P 3.3V analog V DD NC–NoconnectThis pin is not bonded and canbe connected to AVDDH powerfor footprint compatibility withthe Micrel KSZ9021RN GigabitPHY.48 ISET I/O Set transmit output levelConnect a 4.99KΩ 1%resistor to ground on thispin. ISET I/O Set the transmit output levelConnect a 12.1kΩ 1% resistorto ground on this pin.Table 2. Pin Differences between KSZ9021RN and KSZ9031RNXStrapping Option DifferencesThere is no strapping pin difference between KSZ9021RN and KSZ9031RNX.Register Map DifferencesThe register space within the KSZ9021RN and KSZ9031RNX consists of direct-access registers and indirect-access registers.Direct-access RegistersThe direct-access registers comprise of IEEE-Defined Registers (0h – Fh) and Vendor-Specific Registers (10h – 1Fh). Between the KSZ9021RN and KSZ9031RNX, the direct-access registers and their bits have the same definitions, except for the following registers in Table 3.Direct-access RegisterKSZ9021RN KSZ9031RNXName Description Name Description3h PHYIdentifier2 Bits [15:10] (part of OUI) – same asKSZ9031RNXBits [9:4] (model number) – unique forKSZ9021RNBits [3:0] (revision number) – uniquedepending on chip revision PHY Identifier 2 Bits [15:10] (part of OUI) – same asKSZ9021RNBits [9:4] (model number) – unique forKSZ9031RNXBits [3:0] (revision number) – uniquedepending on chip revisionBh ExtendedRegister –Control Indirect Register AccessSelect read/write control andpage/address of Extended RegisterReserved ReservedDo not change the default value ofthis registerCh ExtendedRegister –Data Write Indirect Register AccessValue to write to Extended RegisterAddressReserved ReservedDo not change the default value ofthis registerDh ExtendedRegister –Data Read Indirect Register AccessValue read from Extended RegisterAddressMMD Access –ControlIndirect Register AccessSelect read/write control and MMDdevice addressEh Reserved ReservedDo not change the default value ofthis register MMD Access –Register/DataIndirect Register AccessValue of register address/data for theselected MMD device address1Fh, bit [1] Software Reset 1 = Reset chip, except all registers0 = Disable resetReserved ReservedTable 3. Direct-access Register Differences between KSZ9021RN and KSZ9031RNXIndirect-access RegistersThe indirect register mapping and read/write access are completely different for the KSZ9021RN (uses Extended Registers) and KSZ9031RNX (uses MMD Registers). Refer to respective devices’ data sheets for details.Indirect registers provide access to the following commonly used functions:•1000Base-T link-up time control (KSZ9031RNX only)• Pin strapping status• Pin strapping override•Skew adjustments for RGMII clocks, control signals, and datao Resolution of skew steps are different between KSZ9021RN and KSZ9031RNX•Energy-Detect Power-Down Mode enable/disable (KSZ9031RNX only)•Energy Efficient Ethernet function (KSZ9031RNX only)•Wake-on-LAN function (KSZ9031RNX only)Revision HistoryRevision Date Summary of ChangesMigration Guide created1.0 12/7/121.1 6/7/13 Indicate PME_N1 (pin 17) for KSZ9031RNX is not an open-drain.Indicate INT_N (pin 38) is an open-drain for KSZ9021RN, but is not an open-drain for KSZ9031RNX.Indicate direct-access register 1Fh, bit [1] difference.。

罗格斯公司XtremeSpeed RO1200系列极低损耗数字电路板材料说明书

罗格斯公司XtremeSpeed RO1200系列极低损耗数字电路板材料说明书

XtremeSpeed™ RO1200™ extremely low loss digital circuit materials are ceramic-filled laminates reinforced with woven fiberglass. These materials are engineered to offer exceptional electrical performance and mechanical stability for the most demanding high speed applications.XtremeSpeed RO1200 series laminates combine the surface smoothness of a non-woven PTFE laminate, for finer line etching tolerances, with the rigidity of a woven-glass PTFE laminate. These materials can be fabricated into printed circuit boards using standard PTFE circuit board processing techniques as described in the application note, XtremeSpeed RO1200 Extremely Low Loss Digital Laminate Quick Reference Processing Guide. Features and Benefits:Superior signal integrity• Low dielectric constant• Low dissipation factor• Low profile copper for reducedinsertion lossExcellent thermal/mechanical performance characteristics• Ideal for high layer count structures • Suitable for lead free processing • Td: 500°C (TGA)• Low CTEWoven glass reinforcement• Improved rigidity for ease ofhandling• Spread glass for reduced signal skewThe information in this data sheet is intended to assist you in designing with Rogers’ circuit materials. It is not intended to and does not create any warranties express or implied, including any warranty of merchantability or fitness for a particular purpose or that the results shown on this data sheet will be achieved by a user for a particular purpose. The user should determine the suitability of Rogers’ circuit materials for each application.The Rogers’ logo, Helping power, protect, connect our World, XtremeSpeed and RO1200 are trademarks of Rogers Corporation or one of its subsidiaries. © 2022 Rogers Corporation, Printed in U.S.A., All rights reserved. Revised 1588 080122 Publication 92-173NOTE:[1] The design Dk is an average number from several different tested lots of material and on the most common thickness/s. If more detailed information is required*Contact Customer Service or Sales Engineering to inquire about additional available product configurations。

NVIDIA ConnectX-6DX智能网络接口卡数据手册说明书

NVIDIA ConnectX-6DX智能网络接口卡数据手册说明书

NVIDIA CONNECTX-6DX ETHERNET SMARTNIC | DATASHEET | OCT21 | 1† For illustration only. Actual products may vary.Advanced Networking and Security for the Most Demanding Cloud and Data Center WorkloadsNVIDIA ® ConnectX ®-6 Dx is a highly secure and advanced smart network interface card (SmartNIC) that accelerates mission-critical cloud and data center applications, including security, virtualization, SDN/NFV, big data, machine learning, and storage. ConnectX-6 Dx provides up to two ports of 100Gb/s or a single port of 200Gb/sEthernet connectivity and is powered by 50Gb/s (PAM4) or 25/10 Gb/s (NRZ) SerDes technology.ConnectX-6 Dx features virtual switch (vSwitch) and virtual router (vRouter) hardware accelerations delivering orders-of-magnitude higher performance than software-based solutions. ConnectX-6 Dx supports a choice of single-root I/O virtualization (SR-IOV) and VirtIO in hardware, enabling customers to best address their application needs. By offloading cloud networking workloads, ConnectX-6 Dx frees up CPU cores for business applications while reducing total cost-of-ownership.In an era where data privacy is key, ConnectX-6 Dx provides built-in inline encryption/decryption, stateful packet filtering, and other capabilities, bringing advanced security down to every node with unprecedented performance and scalability. Built on the solid foundation of NVIDIA’s ConnectX line of SmartNICs, ConnectX-6 Dx offers best-in-class RDMA over Converged Ethernet (RoCE) capabilities, enabling scalable, resilient, and easy-to-deploy RoCE solutions. For data storage, ConnectX-6 Dx optimizes a suite of storage accelerations, bringing NVMe-oF target and initiator offloads.SOLUTIONS>Cloud-native, web 2.0, hyperscale >Enterprise data centers >Cybersecurity >Big data analytics>Scale-out compute and storage infrastructure>Telco and network function virtualization (NFV) >Cloud storage>Machine learning and AI >Media and entertainmentPRODUCT SPECIFICATIONSMaximum total bandwidth200Gb/sSupported Ethernet speeds10/25/40/50/100/ 200GbE Number of network ports1/2Network interface technologies NRZ/PAM4 Host interfacePCIe Gen4.0 x16, with NVIDIA Multi-Host ™ technology DPDK message rate Up to 215Mpps Platform securityHardware root-of-trust and secure firmware update Form factors PCIe HHHL, OCP2, OCP3.0 SFF Network interfacesSFP+, QSFP+, DSFPPCIe x16 HHHL Card †OCP 3.0 Small Form Factor †OCP 2.0 Form Factor†DATASHEETNVIDIA CONNECTX-6 DXEthernet SmartNICNetwork Interface>Dual ports of 10/25/40/50/100 GbE, or a single port of 200GbEHost Interface>16 lanes of PCIe Gen4, compatible with PCIe Gen2/Gen3>Integrated PCI switch>NVIDIA Multi-Host and NVIDIA Socket Direct™Virtualization/Cloud Native>SR-IOV and VirtIO acceleration>Up to 1K virtual functions per port>8 physical functions>Support for tunneling>Encap/decap of VXLAN, NVGRE, Geneve,and more>Stateless offloads for overlay tunnels NVIDIA ASAP2 Accelerated Switching & Packet Processing>SDN acceleration for:>Bare metal>Virtualization>Containers>Full hardware offload for OVS data plane>Flow update through RTE_Flow orTC_Flower>Flex-parser: user-defined classification>Hardware offload for:>Connection tracking (Layer 4 firewall)>NAT>Header rewrite>Mirroring>Sampling>Flow aging>Hierarchical QoS>Flow-based statistics Cybersecurity>Inline hardware IPsec encryption anddecryption>AES-GCM 128/256-bit key>RoCE over IPsec>Inline hardware TLS encryption anddecryption>AES-GCM 128/256-bit key>Data-at-rest AES-XTS encryption anddecryption>AES-XTS 256/512-bit key>Platform security>Hardware root-of-trust>Secure firmware updateStateless Offloads>TCP/UDP/IP stateless offload>LSO, LRO, checksum offload>Receive side scaling (RSS) also on encapsulatedpacket>Transmit side scaling (TSS)>VLAN and MPLS tag insertion/stripping>Receive flow steeringStorage Offloads>Block-level encryption: XTS-AES 256/512-bit key>NVMe over Fabrics offloads for target machine>T10 DIF signature handover operation at wirespeed, for ingress and egress traffic>Storage protocols: SRP, iSER, NFS RDMA,SMB Direct, NVMe-oFAdvanced Timing and Synchronization>Advanced PTP>IEEE 1588v2 (any profile)>PTP hardware clock (PHC) (UTC format)>Nanosecond-level accuracy>Line rate hardware timestamp (UTCformat)>PPS in and configurable PPS out>Time-triggered scheduling>PTP-based packet pacing>Time-based SDN acceleration (ASAP2)>Time-sensitive networking (TSN)>Dedicated precision timing card optionRDMA over Converged Ethernet(RoCE)>RoCE v1/v2>Zero-touch RoCE: no ECN, no PFC>RoCE over overlay networks>Selective repeat>Programmable congestion control interface>GPUDirect®Management and Control>NC-SI, MCTP over SMBus and MCTP overPCIe—Baseboard Management Controllerinterface, NCSI over RBT in Open ComputeProject (OCP) 2.0/3.0 cards>PLDM for Monitor and Control DSP0248>PLDM for Firmware Update DSP0267>I2C interface for device control andconfigurationRemote Boot>Remote boot over Ethernet>Remote boot over iSCSI>UEFI and PXE support for x86 and ArmserversFeatures(*)Ordering InformationFor NVIDIA ordering information, please contact your NVIDIA sales representative or visit the online ConnectX-6 Dx user manuals: PCIe HHHL form factor,OCP 3.0 form factor and OCP 2.0 form factor.*This section describes hardware features and capabilities.Please refer to the driver and firmware release notes for feature availability.。

部件关键性评估(CCA)标准实际操作程序.docx

部件关键性评估(CCA)标准实际操作程序.docx

+\部件关键性评估(CCA)标准操作规程责任人部门姓名签字日期Responsible person Department Name Signature Date 起草人Drafted by审核人Reviewed by审核人Reviewed by审核人Reviewed by批准人Approved by1.目的:部件关键性评估是评估直接影响系统中各部件的关键程度。

对判定为关键性的部件进行风险评估用于确定出所有的潜在危险及其对产品的影响。

本项工作能够有效的缩小确认工作的范围,从而对关键性部件进行调试和确认,对非关键性部件仅需进行调试。

它还规定出了验证/ 确认过程中所需进行的活动、操作过程中的建议措施等。

2.适用范围:本文件规定了进行部件关键性评估的方法和程序。

仅对直接影响系统进行部件关键性评估。

3.职责:3.1.使用部门:在评估之前成立评估工作小组,对直接影响系统的部件关键性进行评估。

3.2.系统 / 设备涉及的部门:负责审核部件关键性评估报告。

3.3.质量总监:负责批准部件关键性评估报告。

4.术语 Terminology :+\4.1.部件关键性评估( CCA):通过对直接影响系统的关键性部件进行风险评估,确定其在整个系统中的风险程度,并建议控制措施降低其风险。

4.2.失效模式和效果分析 (FMEA):是确定某个产品或工艺的潜在故障模式、评定这些故障模式所带来的风险、根据影响的重要程度予以分类并且制定和实施各种改进和补偿措施的设计方法。

4.3.关键性部件:系统的某个部件,其运行、接触、数据、控制、报警或故障会对产品的质量参数(功效、特性、安全、纯度、质量)有直接的影响。

4.4.非关键性部件:系统的某个部件,其运行、接触、数据、控制、报警或故障会对产品的质量参数(功效、特性、安全、纯度、质量)有间接的影响或没有影响。

4.5.风险:伤害出现的可能性及其严重性的复合体。

4.6.风险评估( RA):在风险管理过程中,对用于支持风险决定的信息进行组织的系统化流程。

MIAOW_Architecture_Whitepaper

MIAOW_Architecture_Whitepaper

MIAOW WhitepaperHardware Description and Four Research Case StudiesAbstractGPU based general purpose computing is developing as a viable alternative to CPU based computing in many do-mains.Today’s tools for GPU analysis include simulators like GPGPU-Sim,Multi2Sim and Barra.While useful for modeling first-order effects,these tools do not provide a detailed view of GPU microarchitecture and physical design.Further,as GPGPU research evolves,design ideas and modifications de-mand detailed estimates of impact on overall area and power. Fueled by this need,we introduce MIAOW,an open source RTL implementation of the AMD Southern Islands GPGPU ISA,ca-pable of running unmodified OpenCL-based applications.We present our design motivated by our goals to create a realistic,flexible,OpenCL compatible GPGPU capable of emulating a full system.Wefirst explore if MIAOW is realistic and then use four case studies to show that MIAOW enables the following: physical design perspective to“traditional”microarchitecture, new types of research exploration,validation/calibration of simulator-based characterization of hardware.Thefindings and ideas are contributions in their own right,in addition to MIAOW’s utility as a tool for others’research.1.IntroductionThere is active and widespread ongoing research on GPU architecture and more specifically on GPGPU architecture. Tools are necessary for such explorations.First,we compare and contrast GPU tools with CPU tools.On the CPU side,tools span performance simulators,em-ulators,compilers,profiling tools,modeling tools,and more recently a multitude of RTL-level implementations of micro-processors-these include OpenSPARC[39],OpenRISC[38], Illinois Verilog Model[56],LEON[18],and more recently FabScalar[11]and PERSim[7].In other efforts,clean slate CPU designs have been built to demonstrate research ideas. These RTL-level implementations allow detailed microarchi-tecture exploration,understanding and quantifying effects of area and power,technology-driven studies,prototype building studies on CPUs,exploring power-efficient design ideas that span CAD and microarchitecture,understanding the effects of transient faults on hardware structures,analyzing di/dt noise,and hardware reliability analysis.Some specific exam-ple research ideas include the following:Argus[30]showed–with a prototype implementation on OpenRISC how to build lightweight fault detectors;Blueshift[19]and power bal-anced pipelines[46]consider the OpenRISC and OpenSPARC pipelines for novel CAD/microarchitecture work.On the GPU side,a number of performance simula-tors[5,2,12,28],emulators[53,2],compilers[29,13,54],GPUs;ii)Flexible:it should beflexible to accommodate research studies of various types,the exploration of forward-looking ideas,and form an end-to-end open source tool;iii) Software-compatible:It should use standard and widely avail-able software stacks like OpenCL or CUDA compilers to en-able executing various applications and not be tied to in-house compiler technologies and languages.portion of the CU denotes the registerfile and SRAM stor-age as indicated in Figure1(b)).First,observe that in all three designs,the registerfiles need some special treatment besides writing Verilog RTL.A full ASIC design results in reducedflexibility,long design cycle and high cost,and makes it a poor research platform,since memory controller IP and hard macros for SRAM and registerfiles may not be redis-tributable.Synthesizing for FPGA sounds attractive,but there are several resource constraints that must be accommodated tigate case studies along the three perspectives.Section8 1MIAOW was not designed to be a replica of existing commercial GPG-PUs.Building a model that is an exact match of an industry implementation requires reverse engineering of low level design choices and hence was not our goal.The aim when comparing MIAOW to commercial designs was to show that our design is reasonable and that the quantitative results are in similar range.We are not quantifying accuracy since we are defining a new microarchitecture and thus there is no reference to compare to.Instead we compare to a nearest neighbor to show trends are similar.Direction Research idea MIAOW-enabledfindingsTraditional µarch Thread-blockcompaction◦Implemented TBC in RTL◦Significant design complexity◦Increase in critical path lengthNew directions Circuit-failureprediction(Aged-SDMR)◦Implemented entirely inµarch◦Idea works elegantly in GPUs◦Small area,power overheads Timingspeculation(TS)◦Quantified TS error-rate on GPU◦TS framework for future studiesValidation of sim-ulator studiesTransient faultinjection◦RTL-level fault injection◦More gray area than CPUs(dueto large RegFile)◦More silent structuresTable2:Case studies summaryconcludes.The authors have no affiliation with AMD or GPU manufacturers.All information about AMD products used and described is either publicly available(and cited)or reverse-engineered by authors from public documents.2.MIAOW ArchitectureThis section describes MIAOW’s ISA,processor organization, microarchitecture of compute units and pipeline organization, and provides a discussion of design choices.2.1.ISAMIAOW implements a subset of the Southern Islands ISA which we summarize below.The architecture state and regis-ters defined by MIAOW’s ISA includes the program counter, execute mask,status registers,mode register,general purpose registers(scalar s0-s103and vector v0-v255),LDS,32-bit memory descriptor,scalar condition codes and vector con-dition codes.Program control is defined using predication and branch instructions.The instruction encoding is of vari-able length having both32-bit and64-bit instructions.Scalar instructions(both32-bit and64-bit)are organized in5for-mats[SOPC,SOPK,SOP1,SOP2,SOPP].Vector instructions come in4formats of which three[VOP1,VOP2,VOPC]use 32-bit instructions and one[VOP3]uses64-bit instructions to address3operands.Scalar memory reads(SMRD)are 32-bit instructions involved only in memory read operations and use2formats[LOAD,BUFFER_LOAD].Vector memory instructions use2formats[MUBUF,MTBUF],both being 64-bits wide.Data share operations are involved in reading and writing to local data share(LDS)and global data share (GDS).Four commonly used instruction encodings are shown in Table4.Two memory addressing modes are supported-base+offset and base+register.Of a total of over400instructions in SI,MIAOW’s instruc-tion set is a carefully chosen subset of95instructions and the generic instruction set is summarized in Table4.This subset was chosen based on benchmark profiling,the type of operations in the data path that could be practically im-plemented in RTL by a small design team,and elimination of graphics-related instructions.In short,the ISA defines a processor which is a tightly integrated hybrid of an in-order core and a vector core all fed by a single instruction supply and memory supply with massive multi-threading capabil-ity.The complete SI ISA judiciously merges decades of re-search and advancements within each of those designs.From a historical perspective,it combines the ideas of two classical machines:the Cray-1vector machine[45]and the HEP multi-threaded processor[49].The recent Maven[27]design is most closely related to MIAOW and is arguably moreflexible and includes/explores a more diverse design space.From a practical standpoint of exploring GPU architecture,we feel it falls short on realism and software compatibility.2.2.MIAOW Processor Design OverviewFigure1shows a high-level design of a canonical AMD South-ern Islands compliant GPGPU.The system has a host CPU that assigns a kernel to the GPGPU,which is handled by the GPU’s ultra-threaded dispatcher.It computes kernel assign-ments and schedules wavefronts to CUs,allocating wavefront slots,registers and LDS space.The CUs shown in Figure1(b) execute the kernels and are organized as scalar ALUs,vector ALUs,a load-store unit,and an internal scratch pad memory (LDS).The CUs have access to the device memory through the memory controller.There are L1caches for both scalar data accesses and instructions and a unified L2cache.The MIAOW GPGPU adheres to this design and consists of a simple dispatcher,a configurable number of compute units, memory controller,OCN,and a cached memory hierarchy2. MIAOW allows scheduling up to40wavefronts on each CU.2.3.MIAOW Compute Unit MicroarchitectureFigure3shows the high-level microarchitecture of MIAOW with details of the most complex modules and Figure4shows the pipeline organization.Below is a brief description of the functionalities of each microarchitectural component–further details are deferred to an accompanying technical report. Fetch(Fig.3b)Fetch is the interface unit between the Ultra-Threaded Dispatcher and the Compute Unit.When a wave-front is scheduled on a Compute Unit,the Fetch unit receives the initial PC value,the range of registers and local memory which it can use,and a unique identifier for that wavefront. The same identifier is used to inform the Dispatcher when execution of the wavefront is completed.It also keeps track of the current PC for all executing wavefronts.Wavepool(Fig.3b)The wavepool unit serves as an instruc-tion queue for all fetched instructions.Up to40wavefronts–supported by40independent queues–can be resident in the compute unit at any given time.The wavepool works closely with the fetch unit and the issue unit to keep instructionsflow-ing through the compute unit.Decode This unit handles instruction decoding.It also col-lates the two32-bit halves of64-bit instructions.The Decode Unit decides which unit will execute the instruction based on the instruction type and also performs the translation of logical register addresses to physical addresses.2The reference design includes a64KB GDS,which we omitted in our design since it is rarely used in performance targeted benchmarksSI Term nVidia term DescriptionCompute Unit(CU)SM A compute unit is the basic unit of computation and contains computation resources,architectural storage resources(registers),and local memory.Workitem Thread The basic unit of computation.It typically represents one input data point.Sometimesreferred to as a’thread’or a’vector lane’.Wavefront Warp A collection of64work-items grouped for efficient processing on the compute unit.Eachwavefront shares a single program counter.Workgroup Thread-block A collection of work-items working together,capable of sharing data and synchronizingwith each other.Can comprise more than one wavefront,but is mapped to a single CU.Local data store(LDS)Sharedmemory Memory space that enables low-latency communication between work-items within a work-group,including between work-items in a wavefront.Size:32kb limit per workgroup.Global data share(GDS)Global memory Storage used for sharing data across multiple workgroups.Size:64KB. Device memory Device memory Off-chip memory provided by DRAM possibly cached in other on-chip storage.Table3:Definition of Southern Islands ISA terms and correspondence to NVIDIA/CUDA terminologyBase0Instr Q WF0++VTail | Head | Tail+ance which uses evaluation content in Section4.In short,our design choices lead to a realistic and balanced design. Fetch bandwidth(1)We optimized the design assuming instruction cache hits and single instruction fetch.In contrast, the GCN specification has fetch bandwidth on the order of16 or32instructions per fetch,presumably matching a cache-line. It includes an additional buffer between fetch and wavepool to buffer the multiple fetched instructions for each wavefront. MIAOW’s design can be changed easily by changing the inter-face between the Fetch module and Instruction memory. Wavepool slots(6)Based on the back-of-the-envelope anal-ysis of load balance,we decided on6wavepool slots.Our design evaluations show that all6slots of the wavepool are filled50%of the time-suggesting that this is a reasonable and balanced estimate considering our fetch bandwidth.We ex-pect the GCN design has many more slots to accommodate the wider fetch.The number of queue slots is parameterized and can be easily changed.Since this pipeline stage has smaller area,it has less impact on area and power.Issue bandwidth(1)We designed this to match the fetch bandwidth and provide a balanced machine as confirmed in our evaluations.Increasing the number of instructions issued per cycle would require changes to both the issue stage and the register read stage,increasing register read pared to our single-issue width,GCN’s documentation suggests an issue bandwidth of5.For GCN this seems an unbalanced de-sign because it implies issuing4vector and1scalar instruction every cycle,while each wavefront is generally composed of 64threads and the vector ALU being16wide.We suspect the actual issue width for GCN is lower.#of integer&floating point functional units(4,4)We incorporate four integer and fourfloating point vector func-tional units to match industrial designs like the GCN and the high utilization by Rodinia benchmarks indicate the number is justified.These values are parameterizable in the top level module and these are major contributors to area and power. #of register ports(1,5)We use two registerfile designs. Thefirst design is a single ported SRAM based registerfile generated using synopsys design compiler which is heavily banked to reduce contention.In simulations,we observed that there was contention on less then1%of the accesses and hence we are using a behavioral module.This deci-sion will result in a model with a small under-estimation of area and power and over-estimation of performance.This design,however,is likely to be similar to GCN and we report the power/area/performance results based on this registerfile. Since it includes proprietary information and the configuration cannot be distributed,we have a second verison-aflip-flop based registerfile design which hasfive ports.While we have explored these two registerfile designs,many register compil-ers,hard macros,and modeling tools like CACTI are available providing a spectrum of accuracy andfidelity for MIAOW’s users.Researchers can easily study various configurations[4] by swapping out our module.#of slots in Writeback Queue per functional unit(1)To simplify implementation we used one writeback queue slot, which proved to be sufficient in design evaluation.The GCN design indicates a queuing mechanism to arbitrate access to a banked registerfile.Our design choice here probably impacts realism significantly.The number of writeback queue slots is parameterized and thus providesflexibility.The area and power overhead of each slot is negligible.Types of functional units GCN and other industry GPUs have more specialized FUs to support graphic computations. This choice restricts MIAOW’s usefulness to model graph-ics workloads.It has some impact on realism andflexibility depending on the workloads studied.However this aspect is extendable by creating new datapath modules.3.ImplementationIn this section wefirst describe MIAOW’s hybrid implementa-tion strategy of using synthesizable RTL and behavioral mod-els and the tradeoffs introduced.We then briefly describe our verification strategy,physical characteristics of the MIAOW prototype,and a quantitative characterization of the prototype.3.1.Implementation summaryFigure2(c)shows our implementation denoting components implemented in synthesizable RTL vs.PLI or C/C++models. Compute Unit,Ultra-threaded dispatcher As described in AMD’s specification for SI implementations,“the heart of GCN is the new Compute Unit(CU)”and so we focus our attention to the CU which is implemented in synthesizable Verilog RTL.There are two versions of the ultra threaded dis-patcher,a synthesizable RTL module and a C/C++model.The C/C++model can be used in simulations where dispatcher area and power consumption are not relevant,saving simulation time and easing the development process.The RTL design can be used to evaluate complexity,area and power of different scheduling policies.OCN,L2-cache,Memory,Memory Controller Simpler PLI models are used for the implementation of OCN and mem-ory controller.The OCN is modeled as a cross-bar between CUs and memory controllers.To provideflexibility we stick to a behavioral memory system model,which includes device memory(fixed delay),instruction buffer and LDS.This mem-ory model handles coalescing by servicing diverging memory requests.We model a simple and configurable cache which is non-blocking(FIFO based simple MSHR design),set asso-ciative and write back with a LRU replacement policy.The size,associativity,block size,and hit and miss latencies are programmable.A user has the option to integrate more sophis-ticated memory sub-system techniques[48,20].3.2.Verification and Physical DesignWe followed a standard verificationflow of unit tests and in-house developed random program generator based regres-sion tests with architectural trace comparison to an instruction emulator.Specifically,we used Multi2sim as our referenceinstruction emulator and enhanced it in various ways with bug-fixes and to handle challenges in the multithreaded nature and out-of-order retirement of wavefronts.We used the AMD OpenCL compiler and device drivers to generate binaries. Physical design was relatively straight-forward using Syn-opsys Design Compiler for synthesis and IC Compiler for place-and-route with Synopsys32nm library.Based on De-sign Compiler synthesis,our CU design’s area is15mm2and it consumes on average1.1W of power across all benchmarks. We are able to synthesize the design at an acceptable clock period range of4.5ns to8ns,and for our study we have chosen yout introduces challenges because of the dominant usage of SRAM and registerfiles and automaticflat layout withoutfloorplanning fails.While blackboxing these produceda layout,detailed physical design is future work.3.3.FPGA ImplementationIn addition to software emulation,MIAOW was successfully synthesized on a state-of-art very large FPGA.This variant, dubbed Neko,underwent significant modifications in order tofit the FPGA technology process.We used a Xilinx Vir-tex7XC7VX485T,which has303,600LUTs and1,030block RAMs,mounted on a VC707evaluation boardDesign Neko is composed of a MIAOW compute unit at-tached to an embedded Microblaze softcore processor via the AXI interconnect bus.The Microblaze implements the ultra-threaded dispatcher in software,handles pre-staging of data into the registerfiles,and serves as an intermediary for access-ing memory(Neko does not interface directly to a memory controller).Due to FPGA size limits,Neko’s compute unit has a smaller number of ALUs(one SIMD and SIMF)than a standard MIAOW compute unit which has four SIMD and four SIMF units for vector integer andfloating point operations respectively.The consequence of this is that while Neko can perform any operation a full compute unit can,its throughput is lower due to the fewer computational resources.Mapping the ALUs to Xilinx provided IP cores(or DSP slices)may help infitting more onto the FPGA as the SIMD and especially SIMF units consume a large proportion of the LUTs.This however changes the latencies of these significantly(multi-plication using DSP slices is a6stage pipeline,while using 10DSPs can create a1stage pipeline)and will end up re-quiring modifications to the rest of the pipeline and takes away from ASIC realism.We defer this for future work.One other difference is Neko’s registerfile architecture.Mapping MIAOW’s registerfiles naively toflip-flops causes excessive usage and routing difficulties considering,especially with the vector ALU registerfile which ing block RAMs is not straight-forward either,they only support two ports each,fewer than what the registerfiles need.This issue was ultimately resolved by banking and double-clocking the BRAMs to meet port and latency requirements.Resource Utilization and Use Case Table6presents break-downs of resource utilization by the various modules of theModule LUT Count#BRAMs Module LUT Count#BRAMs Decode3474-SGPR6478Exec8689-SIMD36890-Fetch222901SIMF55918-Issue36142-VGPR2162128SALU1240-Wavepool27833-Total195285137Table6:Resource utilizationMIAOW does not aim to be an exact match of any industry implementation.To check if quantitative results of the afore-mentioned metrics follow trends similar to industry GPGPU designs,we compare MIAOW with the AMD Tahiti GPU, which is also a SI GPU.In cases where the relevant data is not available for Tahiti,we use model data,simulator data,or data from NVIDIA GPUs.Table7summarizes the methodology and key results and show MIAOW is realistic.For performance studies we choose six OpenCL bench-marks that are part of the Multi2sim environment,which we list along with three characteristics–#work groups,#wave-fronts per workgroup,and#compute-cycles per work group: BinarySearch(4,1,289),BitonicSort(1,512,97496),Matrix-Transpose(4,16,4672),PrefixSum(1,4,3625),Reduction (4,1,2150),ScanLargeArrays(2,1,4).MIAOW can also run four Rodinia[9]benchmarks at this time–kmeans,nw, backprop and gaussian.We use these longer benchmarks for the case studies in Section5onward3.5.Physical Design PerspectiveDescription:Fung et al.proposed Thread Block Com-paction(TBC)[16].which belongs in a large body of work 3Others don’t run because of they use instructions outside MIAOW’s subset.Area analysisGoal◦Is MIAOW’s total area and breakdown across modules representative of industry designs?Method◦Synthesized with Synopsys1-ported register-file◦For release,5-portedflip-flop based regfile.◦Compare to AMD Tahiti(SI GPU)implemented at28nm;scaled to32nm for absolute comparisonsKey results◦Area breakdown matches intuition;30%in functional units &54%in registerfiles.◦Total area using1-port Synopsys RegFile9.31mm2com-pared to6.92mm2for Tahiti CU◦Higher area is understandable:our design is not mature, designers are not as experienced,our functional units are quite inefficient(from ),and not optimized as indus-try functional units would be.Power analysisGoal◦Is MIAOW’s total power and breakdown across modules representative of industry designs?Method◦Synopsys Power Compiler runs with SAIF activityfile generated by running benchmarks through VCS.◦Compared to GPU power models of NVIDIA GPU[22].Breakdown and total power for industry GPUs not publiclyavailable.Key results◦MIAOW breakdown:FQDS:13.1%,RF:16.9%FU:69.9%◦NVIDIA breakdown:FQDS:36.7%,RF:26.7%FU:36.7%◦Compared to model more power in functional units(likely because of MIAOW’s inefficient FUs);FQDS and RF roughly similar contributions in MIAOW and model.◦Total power is1.1Watts.No comparison reference avail-able.But we feel this is low.Likely because Synopsys32nm technology library is targeted to low power design(1.05V, 300MHz typical frequencyPerformance analysisGoal◦Is MIAOW’s performance realistic?Method◦Failed in comparing to AMD Tahiti performance using AMD performance counters(bugs in vendor drivers).◦Compared to similar style NVIDIA GPU Fermi1-SM GPU.◦Performance analysis done by obtaining CPI for each classof instructions across benchmarks.◦Performed analysis to evaluate balance and sizingKeyresults◦CPI breakdown across execution units is below.CPI DMin DMax BinS BSort MatT PSum Red SLA Scalar13333333Vector16 5.4 2.1 3.1 5.5 5.4 5.5 Memory110014.1 3.8 4.6 6.0 6.8 5.5 Overall1100 5.1 1.2 1.7 3.6 4.4 3.0 NVidia1_20.5 1.9 2.18 4.77.5◦MIAOW is close on3benchmarks.◦On another three,MIAOW’s CPI is2×lower,the reasonsfor which are many:i)the instructions on the NVIDIA GPUare PTX-level and not native assembly;ii)cycle measurementitself introduces noise;and iii)microarchitectures are different,so CPIs will be different.◦CPIs being in similar range shows MIAOW’s realism◦The#of wavepool queue slots was rarely the bottleneck:in50%of the cycles there was at least one free slot available(with2available in20%of cycles).◦The integer vector ALUs were all relatively fully occupiedacross benchmarks,while utilization of the3rd and4th FPvector ALU was less than10%.◦MIAOW seems to be a balanced design.Table7:Summary of investigations of MIAOW’s realism on warp scheduling[31,44,16,43,35,25,24],any of which we could have picked as a case study.TBC,in particular,aims to increase functional unit utilization on kernels with irregular controlflow.The fundamental idea of TBC is that,whenever a group of wavefronts face a branch that forces its work-items to follow the divergent program paths,the hardware should dy-namically reorganize them in new re-formed wavefronts that contain only those work-items following the same path.Thus, we replace the idle work-items with active ones from other wavefronts,reducing the number of idle SIMD lanes.Groups of wavefronts that hit divergent branches are also forced to run in similar paces,reducing even more work-item level diversion on such kernels.Re-formed wavefronts are formed observing the originating lane of all the work-items:if it occupies the lane0in wavefront A,it must reoccupy the same lane0in re-formed wavefront B.Wavefront forming mechanism is com-pletely local to the CU,and it happens without intervention from the ultra-threaded dispatcher.In this study we investigate the level of complexity involved in the implementation of such microarchitecture innovations in RTL.Infrastructure and Methodology We follow the imple-mentation methodology described in[16].In MIAOW,the modules that needed significant modifications were:fetch, wavepool,decode,SALU,issue and the vector registerfile. The fetch and wavepool modules had to be adapted to support the fetching and storage of instructions from the re-formed wavefronts.We added two instructions to the decode mod-ule:fork and join which are used in SI to explicitly indicate divergent branches.We added the PC stack(for recovery after reconvergence)and modified the wavefront formation logic in the SALU module,as it was responsible for handling branches. Although this modification is significant,it does not have a huge impact on complexity,as it does not interfere with any other logic in the SALU apart from the branch unit.The issue and VGPR modules suffered more drastic modifi-cations,shown infigure6.In SI,instructions provide register addresses as an offset with the base address being zero.When a wavefront is being dispatched to the CU,the dispatcher allo-cates registerfile address space and calculates the base vector and scalar registers.Thus,wavefronts access different register spaces on the same registerfile.Normally,all work-items in the wavefront access the same register but different pages of the registerfile as shown in the upper-left corner of6,and the register absolute address is calculated during decode.But with TBC,this assumption does not hold anymore.In a re-formed wavefront all the work-items may access registers with the same offset but different base values(from different originat-ing wavefronts).This leads to modifications in the issue stage, now having to maintain information about register occupancy by offset for each re-formed wavefront,instead of absolute global registers.In the worst case scenario,issue has to keep track of256registers for each re-formed wavefront in contrast to1024for the entire CU in the original implementation.In figure6,the baseline issue stage observed in the lower-leftcorner and in the lower-right are the modifications for TBC, adding a level of dereference to the busy table search.In VGPR,we now must maintain a table with the base registers from each work-item within a re-formed wavefront and reg-ister address is calculated for each work-item in access time. Thus,there are two major sources of complexity overheads in VGPR,the calculation and the routing of different addresses to each register page as shown in the upper-right corner of6. We had to impose some restrictions to our design due to ar-chitectural limitations:first,we disallowed the scalar register file and LDS accesses during divergence,and therefore,wave-front level synchronization had to happen at GDS.We also were not able to generate code snippets that induced the SI compiler to use fork/join instructions,therefore we used hand-written assembly resembling benchmarks in[16].It featured a loop with a divergent region inside,padded with vector instruc-tions.We controlled both the number of vector instructions in the divergent region and the level of diversion.Our baseline used post-denominator stack-based reconver-gence mechanism(PDOM)[33],without any kind of wave-front formation.We compiled our tests and ran them on two versions of MIAOW:one with PDOM and other with TBC. Quantitative results The performance results obtained matched the results from[16]:Similar performance was ob-served when there was no divergence and a performance in-crease was seen for divergent workloads.However,our most important results came from synthesis.We observed that the modifications made to implement TBC were mostly in the regions in the critical paths of the design.The implementation of TBC caused an increase of32%in our critical path delay from8.00ns to10.59ns.We also observed that the issue stage area grew from0.43mm2to1.03mm2.Analysis Our performance results confirm the ones obtained by Fung et al.,however,the RTL model enabled us to imple-ment TBC in further detail and determine that critical path delay increases.In particular,we observed that TBC affects the issue stage significantly where most of the CU control state is present dealing with major microarchitectural events.TBC reinforces the pressure over the issue stage making it harder to track such events.We believe that the added complexity suggests that a microarchitectural innovation may be needed involving further design refinements and re-pipelining,not just implementation modifications.The goal of this case study is not to criticize the TBC work or give afinal word on its feasibility.Our goal here is to show that,by having a detailed RTL model of a GPGPU,one can better evaluate the complexity of any proposed novelties. 6.New types of research exploration6.1.Sampling DMR on GPUsDescription:Balasubramanian et al.proposed a novel tech-nique of unifying the circuit failure prediction and detection in CPUs using Virtually Aged Sampling DMR[6](Aged-SDMR).They show that Aged-SDMR provides low design complexity,low overheads,generality(supporting various types of wearout including soft and hard breakdown)and high accuracy.The key idea was to“virtually”age a processor by reducing its voltage.This effectively slows down the gates, mimicking the effect of wearout and exposes the fault,and Sampling-DMR is used to detect the exposed fault.They show that running in epochs and by sampling and virtually aging1%of the epochs provides an effective system.Their design(shown in Figure7)is developed in the context of multi-core CPUs and requires the following:i)operating system involvement to schedule the sampled threads,ii)some kind of system-level checkpoints(like Revive[41],ReviveIO[34], Safetynet[51])at the end of every epoch,iii)some system and microarchitecture support for avoiding incoherence be-tween the sampled threads[50],iv)some microarchitecture support to compare the results of the two cores,and v)a subtle but important piece,gate-level support to insert a clock-phase shifting logic for fast paths.Because of these issues Aged-SDMR’s ideas cannot directly be implemented for GPUs to achieve circuit failure prediction.With reliability becoming important for GPUs[10],having this capability is desirable. Our Design:GPUs present an opportunity and problem in adapting these ideas.They do not provide system-level check-points nor do they lend themselves to the notion of epochs making(i),(ii)and(iii)hard.However,the thread-blocks(or workgroups)of compute kernels are natural candidates for a piece of work that is implicitly checkpointed and whose gran-ularity allows it to serve as a body of work that is sampled and run redundantly.Furthermore,the ultra-threaded dispatcher can implement all of this completely in the microarchitecture without any OS support.Incoherence between the threads can be avoided by simply disabling global writes from the sampled thread since other writes are local to a workgroup/compute-unit anyway.This assumption will break and cause correctness issues when a single thread in a wavefront does read-modify-writes to a global address.We have never observed this in our workloads and believe programs rarely do pari-sion of results can be accomplished by looking at the global stores instead of all retired instructions.Finally,we reuse the clock-phase shifting circuit design as it is.This overall design, of GPU-Aged-SDMR is a complete microarchitecture-only solution for GPU circuit failure prediction.Figure7shows the implemenation mechanism of GPU-Aged-SDMR.Sampling is done at a workgroup granularity with the ultra-threaded dispatcher issuing a redundant work-group to two compute units(checker and checked compute units)at a specified sampling rate,i.e for a sampling rate of1%,1out of100work groups are dispatched to another compute unit called checker.This is run under the stressed conditions and we disable the global writes so that it does not affect the normal execution of the workgroups in the checked CU.We could use a reliability manager module that compares all retired instructions or we can compute a checksum of the retiring stores written to global memory from the checker and。

终止设计的惯性——宏暮Aspire 8920G笔记本电脑

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超越独立显卡C51/C61“完美计划”

超越独立显卡C51/C61“完美计划”

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CPC分类号在OLED显示结构领域专利检索中的应用

CPC分类号在OLED显示结构领域专利检索中的应用

31第2卷 第8期产业科技创新 2020,2(8):31~32Industrial Technology Innovation CPC分类号在OLED显示结构领域专利检索中的应用杨丹丹(国家知识产权局专利局专利审查协作广东中心,广东 广州 510555)摘要:近年来OLED显示技术的快速发展,涉及材料、结构、驱动、封装和工艺等OLED显示技术的专利申请量大幅增长。

为了准确快速地开展专利检索,针对OLED显示结构领域的特点,结合实质审查过程中的具体案例,探讨了CPC分类号在OLED显示结构领域专利检索中的实际应用,表明CPC分类体系相对于传统的IPC分类系统更能明显提高专利检索的效率,避免关键词难扩展、噪声大的不足,对同类案例具有借鉴和参考意义。

关键词:CPC分类号;OLED显示结构领域;专利检索中图分类号:F416.6 文献标志码:A 文章编号:2096-6164(2020)08-0031-02OLED是有机电致发光二极管(Organic Light Emitting Diode)的简称,具有自发光的性质,可以被制备成非常薄的显示器,由于其视角广、相应快、效率高等优点[1],逐渐成为继液晶显示器后的第三代显示技术,成为近年来发展非常活跃的一个领域。

作为一种新兴的显示器件,围绕OLED的研究涉及到材料、结构、驱动、封装和工艺等各个方面,有关OLED的专利申请数量也在持续增长。

国内的OLED显示企业(如华星光电、京东方、天马微电子、云谷(固安)、昆山国显)等虽然起步较晚,但是近十年来的专利申请量大幅度增长,企业也抓紧专利布局,掌握了大量核心专利。

日本、韩国等的OLED企业(如三星、乐金显示、夏普株式会社、索尼等)起步更早,技术更成熟,相应的专利文献量也更大,这也促使OLED显示领域细分的CPC分类号的诞生。

CPC (Cooperative Patent Classification)是由欧洲专利局和美国专利商标局合作开发的一套分类体系。

触摸芯片介绍英文作文

触摸芯片介绍英文作文

触摸芯片介绍英文作文下载温馨提示:该文档是我店铺精心编制而成,希望大家下载以后,能够帮助大家解决实际的问题。

文档下载后可定制随意修改,请根据实际需要进行相应的调整和使用,谢谢!并且,本店铺为大家提供各种各样类型的实用资料,如教育随笔、日记赏析、句子摘抄、古诗大全、经典美文、话题作文、工作总结、词语解析、文案摘录、其他资料等等,如想了解不同资料格式和写法,敬请关注!Download tips: This document is carefully compiled by theeditor. I hope that after you download them,they can help yousolve practical problems. The document can be customized andmodified after downloading,please adjust and use it according toactual needs, thank you!In addition, our shop provides you with various types ofpractical materials,such as educational essays, diaryappreciation,sentence excerpts,ancient poems,classic articles,topic composition,work summary,word parsing,copyexcerpts,other materials and so on,want to know different data formats andwriting methods,please pay attention!Touch chips are really cool. They can make our devices more sensitive and responsive. You just touch the screen or a specific area, and things happen. It's like magic!These chips are very important in today's technology. They are used in phones, tablets, and other electronic gadgets. They make it easy for us to interact with our devices.The technology behind touch chips is amazing. It allows for precise control and quick reactions. You don't even have to think about it, it just works.And they keep getting better and better. Newer versions are more accurate and can do more things. It's exciting to think about what they will be able to do in the future.。

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介绍一个电子设备英语作文

介绍一个电子设备英语作文In the realm of cutting-edge electronic devices, the Apple iPad Pro stands as an exemplar of technological prowess and design elegance. This multifaceted device transcends the boundaries of conventional tablets, offering a seamless blend of power, versatility, and user-centricity. This essay provides a comprehensive analysis of the iPad Pro, delving into its design aesthetics, hardware specifications, software capabilities, and its role in modern-day digital lifestyles.Design-wise, the iPad Pro embodies Apple's signature minimalist philosophy. The sleek, all-aluminum unibody construction exudes sophistication and durability. Its thin profile, weighing merely 1.03 pounds for the 11-inch model and 1.41 pounds for the 12.9-inch variant, ensures unparalleled portability. The Liquid Retina display, with its edge-to-edge design and True Tone technology, delivers stunning visuals with accurate color reproduction and adaptive brightness, enhancing the viewing experience across various environments. The inclusion of Face ID,replacing the traditional home button, adds a layer of security and convenience to the device's interface.Underneath its elegant exterior lies a powerhouse of hardware. The iPad Pro is powered by Apple's M1 chip, the same groundbreaking processor found in the latest Mac computers. This transition to desktop-class architecture enables lightning-fast performance, seamless multitasking, and support for demanding professional applications. Paired with up to 16GB of RAM and up to 2TB of storage, it can handle even the most memory-intensive tasks with ease. The device also features a Thunderbolt port, a first for iPads, allowing for high-speed data transfer, external monitor connectivity, and compatibility with a wide range of accessories.The true strength of the iPad Pro lies in its software ecosystem. Running on iPadOS, a derivative of iOS specifically optimized for larger screens, it offers a rich, intuitive, and highly customizable user experience. The App Store houses millions of apps designed specifically for the iPad, ranging from productivity tools like Microsoft Office and Adobe Creative Suite to immersive gaming experiences and educational resources. The introduction offeatures like Scribble (handwriting recognition) and Apple Pencil integration further extends its functionality, particularly for artists, designers, and note-takers.In the context of contemporary digital lifestyles, the iPad Pro has emerged as a versatile tool that caters to diverse user needs. For professionals, it serves as a powerful mobile workstation, enabling them to work remotely, create multimedia content, and present ideas with clarity. Students and educators find it invaluable for interactive learning, research, and digital note-taking. For casual users, it offers an immersive entertainment platform, be it for streaming movies, reading e-books, or playing games. Furthermore, its compatibility with accessories like the Magic Keyboard and Apple Pencil transforms it into a viable laptop alternative for many.In conclusion, the Apple iPad Pro is a testament to the harmonious fusion of aesthetics, hardware innovation, and software excellence. It pushes the boundaries of what a tablet can achieve, redefining the role of electronic devices in our lives. With its unparalleled performance, versatility, and user-centric design, it continues to set the benchmark for premium tablets in the market,solidifying its position as an indispensable tool for work, creativity, and leisure in the digital age.。

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d] = max( max ( z2(0;d] z ]);
0]):
The scale factor converts the ux density per unit length z ] to a ux density . Maximum projection rendering is particularly useful for any application in which a strong signal is produced over a small volume, and might be obscured by low-level background noise produced over a much larger volume. In the following we rst review and discuss a recent algorithm for hardware accelerated rendering of volumes based on texture mapping. Then we describe a novel approach which only uses at shaded polygons to render the volumes, and thus overcomes the performance penalties of texture mapping on low-end machines. Finally we show how volumes and surfaces can be combined into one image with our approach, and conclude with some results and performance measurements.
0
1.1 Emissive Volumes
1 Introduction
Volume rendering is concerned with the generation of images that reveal the internal structures of volume data sets obtained by simulations or measurements. Volume rendering achieves this goal by interpreting the values in the data set as coe cients for the emission and absorption of light at a given point in 3-D space. These data points are treated as discrete samples of continuous volumetric functions (~ ) and (~ ). The data x x set can therefore be rendered by tracing rays from a given camera position through the volume, and integrating the intensities along these rays. This is done using the emission/absorption integral 5]: Z d Rd Rd d] = e? z ]d z ]dz + e? 0 z]dz 0]: 0 (1)
Abstract
Traditional volume rendering is computationally expensive and can therefore only be performed at low frame rates. In recent years algorithms have been developed that are speci cally tailored towards the use of graphics hardware for volume rendering. On systems equipped with the appropriate hardware, these algorithms are capable of rendering volumes at interactive rates. Unfortunately, existing algorithms rely on advanced graphics features like texture mapping, which are not available on contemporary lowend systems. In this paper we describe a novel approach for the hardware based rendering of emissive volumes, which only requires very basic support by the graphics hardware, such as at shaded polygons, depth cueing and depth bu er. Therefore the algorithm is capable of exploiting low-end graphics hardware without support for texture mapping and other advanced features.
The value d] is the ux density reaching the image plane at z = d, and 0] de nes a background intensity at z = 0. (~ ) denotes the linx ear absorption coe cient of the medium, while (~ ) represents the ux density per unit length x emitted towards the image plane by suspended particles. By manipulating the way in which the values of the original volume data are interpreted as absorptive (~ ) and emissive (~ ) properties, varix x ous e ects can be achieved, including iso-surfaces 7, 8] and apparently opaque objects. Often, the data sets to be visualized only contain a single scalar value for every point in the volume. This is for example true for most medical data sets, like MRA or ultrasound data. In this case, it is natural to directly map this scalar value to either the absorption (~ ) or the emission (~ ), x x respectively, and to set the other coe cient to zero. In the latter case, where (~ ) = 0, the x volume is called purely emissive and the integral in (1) reduces to Zd z ] dz + 0]; (2) d] =
rendering". For every pixel in the image, it directly evaluates the integral from Equation 2 over all the voxels along the projection ray corresponding to this pixel. Another commonly used projection operator is \maximum projection rendering", which assigns to every pixel the maximum emission of all voxels along the projection ray corresponding to this pixel. This is characterized by the following projection formula:
On high-end machines supporting hardware texture mapping, this approach to volume rendering can be extremely fast. The rendering performance only depends on the number of slices blended together, and not on the size of the volume, as long as the volume completely ts into the texture memory. If, however, the size of this memory is exceeded, the volume has to be broken down into smaller sub-volumes, called \bricks", and these have to be swapped in and out of the texture memory for every frame. As a consequence, the rendering performance will usually be limited by the bandwidth of the bus used to transfer the bricks into texture memory. On low-end machines without hardware texture mapping support, the performance penalties for this approach are even more striking. Usually bus bandwidth is not a problem on these platforms, since the volume resides in main memory and thus does not have to be transferred over a bus continuously. However, the CPU load imposed by rendering several hundred large texturemapped polygons with tri-linear interpolation is so high, that even on the most modern CPUs the frame rate degrades to one frame every few seconds. In this paper we describe a novel approach for volume rendering, which is purely based on rendering at shaded polygons without texture mapping, and thus scales well with both the size of the data set and the available graphics hardware.
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