EP4CE30
VGA显示控制
基于FPGA 的VGA显示控制摘要VGA（Video Graphics Array）即视频图形阵列，是IBM公司1987年推出的一种传输标准，具有分辨率高、显示速率快、颜色丰富等优点，在彩色显示器领域得到了广泛应用。
本次课程设计是基于FPGA和主芯片为 EP4CE30F23C8N的ALTER公司的开发板Cyclone IV来实现的。
数字图像信息在VGA接口显示器正确、完整地显示,涉及到时序的构建和数字图像信息的模拟化两方面,提出一种能够广泛应用的VGA显示接口方案,详细阐述了数字图像数据DA转化并输出到VGA接口显示器显示的方法,其中包括接口的硬件设计、视频DA转换器的使用方法、通过FPGA构造VGA时序信号的方法等等。
方案可以应用于各种仪器,数字视频系统、高分辨率的彩色图片图像处理、视频信号再现等。
课设主要用到的芯片是ADV7123，它是一款高速、高精度数模转换芯片。
拥有三路十位D/A转换器，能够将代表颜色的数据锁存到数据寄存器中，然后通过D/A 转换器转换成模拟信号输出，得到我们要的色彩。
VGA显示的硬件设计和原理1.1 FPGA主芯片课程设计所用开发板的主芯片是EP4CE30F23C8N——Cyclone IV，其由Altera公司开发，值得注意的是该开发板所支持的QUARTUS II的版本较高，并且11.0的版本较12.0的版本编译好的程序更好下载。
图-11.2 ADV7123实现VGA的控制显示主要用到的芯片就是ADV7123，ADV7123由完全独立的三个I0位高速D/A转换器组成,RGB（红绿蓝）视频数据分别从R9~R0、G9~G0、B9~B0输入，在时钟CLOCK的上升沿锁存到数据寄存器中，然后经告诉D/A转换器转换成模拟信号。
三个独立的视频D/A转换器都是电流型输出，可以接成差分输出，也可以接成单端输出。
DE2-115上按单端输出，在模拟输出端用75欧姆电阻接地，以满足工业标准。
FPGA可编程逻辑器件芯片EP4CE10F17C8N中文规格书
P IPELINED V ISION P ROCESSOR (PVP)PVP F UNCTIONAL D ESCRIPTIONThe angle φ is calculated to five bits of resolution (11.25°) and an accuracy of ±0.25°. Mathematically, the angle is a signed value. However, since the angle is always zero-extended when output to 16-bit or 32-bit buses, it can also be interpret as an unsigned binning value.Figure 30-17:PMA Angle BinningThe PMA sets the angle to 0x08 (+90°) if the x input value is 0 and the y input is a positive value and to 0x18 (-90°) if the y input is negative. If both, x and y are zero, the PMA outputs 0x1F by convention.Other than data flow configuration, the PMA block does not have any control or status registers. Both of its inputs can be individually configured to receive data from any of the convolution blocks or from either input formatter.NOTE :Care is required in that both inputs are timed consistently and are not subject to non-matchinglatency in up front pipeline configuration.The PMA block has three output ports. If PMA is enabled, all three 32-bit ports are always active as follows. •Port 0 drives the 16-bit unsigned magnitude. The upper 16 bits are always driven as zeros.•Port 1 drives the 5-bit angle value. The upper 27 bits are always driven as zeros.•Port 2 drives a combined format. The lower 16 bits contain the magnitude, bits 16 to 20 drive the angle,and the upper ones are always zero. The Port 2 signal is not only good for being streamed to system memory. The PEC block and THCn blocks have special functionality to deal with this format.The table and figure show the PMA block data flow and PVP block connections. For a graphical overview of all PVP block interconnections, see Configuring Pipe Structure.Table 30-33:CNV2 Block ConnectivityCNV2 Block I/O Data Format PVP Block ConnectSelections Port ConnectInput 0 s16 IPF0IPF1CNV0CNV1CNV30, 1, 2 0, 1, 2 0Input 1 n/a n/a n/a Output 0s32 (Result)CNV0, CNV1, CNV3,PMA, ACU, PEC, THC0,THC1, IIM0, IIM1.OPF0, OPF1, OPF2,OPF3n/aOutput 1 n/a n/a n/a Output 2 n/a n/a n/aTable 30-34:CNV3 Block ConnectivityCNV3 Block I/O Data Format PVP Block ConnectSelections Port ConnectInput 0 s16 IPF0IPF1CNV0CNV1CNV20, 1, 2 0, 1, 2 0Input 1 n/a n/a n/a Output 0s32 (Result)CNV0, CNV1, CNV2,PMA, ACU, PEC, THC0,THC1, IIM0, IIM1.OPF0, OPF1, OPF2,OPF3n/aOutput 1 n/a n/a n/a Output 2 n/a n/a n/aFigure 30-12:CNV RCCC Received From SensorWhen CNV1 receives a Bayer or a RCCC data stream, red pixel substitution performs convolution/correlation, shift and saturate operation only on the red pixel. The blue and green pixels (the clear pixels) are passed to the output without modification. In this mode, the PVP_CNVn_CTL.SAT32 control bit must be set to zero. Only then can accumulation results saturate to 16 bits and match the data range of the unmodified 16-bit clear pixels. All pixels are sign-extended to 32 bits on the output.Figure 30-13:CNV RCCC Convolution Kernel FlowThe red pixel substitution mode is enabled by the PVP_CNVn_CTL.RFRMT0 bit. The PVP_CNVn_CTL.RFRMT1 bit distinguishes between Bayer Type 1 or Type 2 configuration.There are multiple strategies for substituting the red pixel in an RCCC data stream. The CNV1 blockallows for many types of mean value generation that interpolate the missing clear value (in place of the red pixel). The following figure provides an overview of the most prominent convolution kernels.*OQVU$POWPMVUJPO,FSOFM 4I J G U F S 4B U V S B U J P O 3$$@5:1& @&/"#-& CJU3$$@5:1& @&/"#-& CJU 0VUQVU5PHHMF 'MJQ 'MPQT GPS 3PX BOE $PMVNO。
Cyclone IV FPGA 器件系列概述
30
高速收发器 ( 注释 6)
2
4
4
4
8
8
8
8
收发器最大数据速率 (Gbps)
2.5
2.5
2.5
3.125
3.125
3.125
3.125
3.125
PCIe(PIPE) 硬核 IP 模 块
1
1
1
1
1
1
1
1
用户 I/O 块
9
9
9
11
11
11
11
11
( 注释 7) ( 注释 7) ( 注释 7) ( 注释 8) ( 注释 8) ( 注释 8) ( 注释 8) ( 注释 8)
? 1?:Cyclone IV FPGA 器件系列概述
封装矩阵
Altera 公司 2011 年 11 月
封装矩阵
表 1-3 列出了 Cyclone IV E 器件封装产品。
表 1-3. Cyclone IV E 器件系列的封装产品 ( 注释 1)
封装
E144
M164
尺寸 ( 毫米 )
22 × 22
资源
逻辑单元 (LE)
6,272 10,320 15,408 22,320 28,848 39,600 55,856 75,408 114,480
嵌入式存储器 (Kbits)
270
414
504
594
594 1,134 2,340 2,745 3,888
嵌入式 18 × 18 乘法器 15
23
56
66
ISO 9001:2008 Registered
Cyclone IV 器件手册， 卷1 2011 年 11 月
ALINX822用户手册REV1.0
视频处理开发板用户手册ALINX822芯驿电子科技（上海）有限公司黑金动力社区目录功能简介 (3)功能实现 (5)FPGA核心板 (7)(一)简介 (7)(二)DDR2引脚分配 (9)(三)FPGA供电电源 (10)(四)扩展口 (12)(五)电源接口 (15)(六)JTAG接口 (15)(七)外部晶振 (16)(八)复位按键 (17)(九)LED (18)扩展板 (19)(一)简介 (19)(二)VGA接口 (20)(三)HDMI接口 (22)(四)视频输出接口 (24)(五)视频输入接口 (26)(六)ARM控制器 (28)1)实时时钟 (29)2)EEPROM (30)3)LED (31)4)串口 (32)(七)扩展口 (32)(八)SD卡 (34)专业级FPGA视频图像处理开发平台（型号：ALINX822）正式发布了，为了让您对此开发平台可以快速了解，我们编写了此用户手册。
这款FPGA视频图像处理开发平台是根据本公司一个视频图像处理项目进行改进衍生而来，不管硬件设计还是软件程序的编写，都出自产品研发工程师之手，因此，这款开发平台可以堪称“专业级”，贴近产品，贴近研发的第一线。
这样的一款产品非常适合即将从事或者正在从事FPGA视频图像处理的学生、工程师等群体。
简介在这里，对这款FPGA开发平台进行简单的功能介绍。
开发板的整个结构，继承了我们一贯的核心板+扩展板的模式来设计的。
核心板主要由FPGA+两片DDR2构成，承担视频图像处理的核心算法，充分利用了FPGA并行处理的能力，加上两片DDR2构建32bit总线，整个系统的带宽高达10Gb/s；两片DDR2容量高达2Gbit，满足视频处理过程中对高缓冲区的需求。
我们选用的FPGA为ALTERA公司CYCLONE IV系列的EP4CE30F23C6N这款高速的FPGA芯片。
我们选用CYCLONE IV系列中速度级别最高的C6级别，可以实现FPGA和DDR2之间的时钟频率达到200M，DDR2内部400M，充分满足了四路1080p视频处理的需求。
FPGA可编程逻辑器件芯片EP4CE30F23C6中文规格书
SWU_IDn
ID Register n
SWU_CNTn
Count Register n
SWU_TARGn
Target Register n
SWU_HISTn
Bandwidth History Register n
SWU_CURn
Current Register n
ADSP-BF60x SWU Interrupt List
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SYSTEM WATCHPOINT UNIT (SWU) SWU FUNCTIONAL DESCRIPTION
SWU Flow Diagram
The following diagram shows the logical program flow of the SWU.
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采购清单请申请人在可以供货的采购品目明细所对应的是否
8分辨率D/A转换集成芯片DAC0832
208
DIP64芯片座
DIP64
209
FC接头
FC1400-1U-AC
210
FPGA模块—EPF10K10
EPF10K10
211
QFP144芯片座
IC51-1444-1354-7
212
QFP48芯片座
QFP48
213
RF遥测模块
T021A
214
TL712高速比较器芯片
239
iTOP4412开发板
240
索尼VMC-15MHD 高清音频视频线
索尼VMC-15MHD
241
Freescale iMX27开发板
Freescale iMX27
242
130W像素CMOS摄像头
130W像素
243
锂电池模块
244
VGA/TV转接板
245
USB转串口线
246
罗技Pro C920 1080P全高清网络摄像头
139
焊接加工工具
140
焊锡丝
141
红外激光二极管
142
开关电源
143
滤光片
144
软性电路板
145
摄像模组
146
视频线缆
147
万用表
148
稳压电源
149
显示模组
150
专业微距镜头
151
反相缓冲器
74AHCT1G04
152
运算放大器
AD623
153
单轴加速度计
ADXL103
154
两轴加速度计
ADXL203
94
FPGA可编程逻辑器件芯片EP4CE10F17C7N中文规格书
P IPELINED V ISION P ROCESSOR (PVP)PVP F UNCTIONAL D ESCRIPTIONFigure 30-5:Color Separation and PortsInput Formatters Using PPI and PVPIf IPF0 is receiving data from any of the PPIs in camera pipe mode, the settings of the two modules need to partner for reception of reasonable data formats. The following tables list the supported combinations of settings for the PPI and PVP.NOTE:An “X” entry for a field value in the table indicates that the control bit field is not used for the described transfer.Table 30-10:PPI and PVP Settings for RGB 8-Bit (YCbCr 4:4:4) with 8 Bits per PIXCLK PPI/PVP Control Bit Fields Field Value (Description)PPI settings EPPI_CTL.XFRTYPE0x3 (Non-ITU656 Mode, GP Mode)EPPI_CTL.DLEN0x0 (8-bit data length)EPPI_CTL.SPLTWRD0x0 (PPI_DATA has DLEN-1 bits of Y or Cr or Cb) EPPI_CTL.SPLTEO0x0 (Do Not Split Samples)EPPI_CTL.PACKEN0x0 (Disable)0x1 (Enable) EPPI_CTL.DMACFG XEPPI_CTL.SUBSPLTODD XTable 30-12:RGB 16-Bit (YCbCr 4:4:4) with 10, 12, or 16 Bits per PIXCLKTable 30-13:RGB 565 (YCbCr 4:4:4) with 16 Bits per PIXCLKPPI/PVP Setting Value/InformationPPI settings EPPI_CTL.XFRTYPE0x3 (Non-ITU656 Mode, GP Mode)EPPI_CTL.DLEN0x4 (16-bit data length)EPPI_CTL.SPLTWRD0x0 (PPI_DATA has DLEN-1 bits of Y or Cr or Cb) EPPI_CTL.SPLTEO0x0 (Do Not Split Samples)EPPI_CTL.PACKEN0x0 (Disable)0x1 (Enable) EPPI_CTL.DMACFG XEPPI_CTL.SUBSPLTODD XTable 30-15:Bayer Format Type-1 and Bayer Format Type-2Table 30-16:YCbCr 4:2:2 8-Bit Type 1 (CrYCbY) with 8 Bits per PIXCLKPPI/PVP Setting Value/InformationPPI settings EPPI_CTL.XFRTYPE0x0, 0x1, or 0x2 (ITU656 Modes); or 0x3 (Non-ITU656 Mode, GPMode)EPPI_CTL.DLEN0x0 (8-bit data length)EPPI_CTL.SPLTWRD0x0 (PPI_DATA has DLEN-1 bits of Y or Cr or Cb)EPPI_CTL.SPLTEO0x0 (Do Not Split Samples)EPPI_CTL.PACKEN0x0 (Disable)0x1 (Enable)EPPI_CTL.DMACFG XEPPI_CTL.SUBSPLTODD X。
FPGA可编程逻辑器件芯片EP4CE10F17C6中文规格书
P IPELINED V ISION P ROCESSOR (PVP)PVP F UNCTIONAL D ESCRIPTIONInput Formatters Receiving Unsigned DataTypically, the IPFn blocks receive video data that is 8-, 10-, 12-, or 14-bits wide, which is zero extended to 16-bit values. This typical pixel data can always be positive values, whether the data is processed by signed- or unsigned-computation engines. If the IPFn blocks receive data that is 16 bits wide (without extension) or that is 32 bits wide, correct operation requires that the PVP blocks process the signed- or unsigned-data input with operations that are appropriate for the data type.Data processing related conflicts can occur when:•The IPFn receives data is unsigned 16- or 32-bit data, AND•The IPFn forwards the unsigned data to PVP blocks that can only operate on signed data.The affected PVP blocks are:•CNVn blocks and PMA block, which require signed 16-bit data•ACU block, which requires signed 32-bit dataTo avoid these conflicts, use the PVP_IPFn_CTL.QFRMT bit to instruct the IPFn to right shift the incoming data by one bit position and to zero fill the most significant bit. This operation directs the PVP to interpret the input as a positive value for the signed computation engines. The output formatter (OPFn) blocks provide the counterpart functionality, which shifts the result back to the left by one bit position. Thisapproach avoids conflicts due to signed bits (at the cost of losing one bit of input accuracy).Input Formatters with Color ExtractionThe PVP blocks process data in monochrome format. Often, the IPFn blocks’ data inputs have to probe color data streams. To support this data, the IPFn blocks include features for extracting luminance or chro-matic values from composite colored data streams. These features include:•Extraction of Y (luma) values out of YCrCb streams•Extraction of G (green) values out of RGB streams•Extraction of G (green) values out of Bayer streams•Extraction of R (red) values out of Bayer streamsThe PVP_IPFn_CTL.CFRMT bit field defines the color format being used by the incoming data. The mono-chrome and color video formats table provides the overview of transfers operations, where each cell shows two consecutive 32-bit words that follow the conventions shown below. This table refers to data sent by the EPPI or PIXC in case of IPF0 and data stored in memory (and fetched by DMA) for IPF1.1st word MS byte1st word byte 21st word byte 11st word LS byte2nd word MS byte2nd word byte 22nd word byte 12nd word LS byteADSP-BF60X B LACKFIN P ROCESSOR H ARDWARE R EFERENCEP IPELINED V ISION P ROCESSOR (PVP)PVP F UNCTIONAL D ESCRIPTIONTable 30-8:Supported Monochrome and Color Video Formats (Continued)ADSP-BF60X B LACKFIN P ROCESSOR H ARDWARE R EFERENCEP IPELINED V ISION P ROCESSOR (PVP)PVP F UNCTIONAL D ESCRIPTIONTable 30-9:Supported Bayer PatternsIf the PVP_IPFn_CTL.EXTRED bit =0, the IPFn blocks extract the green components of the Bayer matrix.The output frame has half the horizontal resolution of the input frame. If the PVP_IPFn_CTL.EXTRED bit =1, the IPFn blocks extract the red component, dividing horizontal and vertical resolution.In Bayer extraction mode, the input values can be 10, 12, or 16 bits wide. An 8-bit format is not supported.The PPI’s EPPI_CTL.SWAPEN bit must be cleared in this mode.The Bayer concepts can also apply to red-clear-clear-clear (RCCC) data. This is similar to Bayer format, except that the green and blue pixels have monochrome (clear filter) values. For extraction on RCCC data, programs have the following options:•Extract the red pixels as in Bayer extraction mode.•Extract one clear pixel by swapping type 1 versus type 2 and setting the PVP_IPFn_CTL.EXTRED bit.•Extract the diagonal clear pixels that correspond to the green pixels in Bayer format.•Use the odd/even mechanism and only process the clear columns.•Ignore the fact that red pixels are special and low-pass them using convolution blocks.ADSP-BF60X B LACKFIN P ROCESSOR H ARDWARE R EFERENCE。
FPGA可编程逻辑器件芯片EP4CE10E22C8N中文规格书
Table 30-1:ADSP-BF60x PVP Register List (Continued)Name DescriptionPVP_PEC_D2TH1PEC Strong Zero Crossing Threshold PVP_IIMn_CFG IIMn ConfigurationPVP_IIMn_CTL IIMn ControlPVP_IIMn_SCALE IIMn Scaling ValuesPVP_IIMn_SOVF_STAT IIMn Signed Overflow StatusPVP_IIMn_UOVF_STAT IIMn Unsigned Overflow StatusPVP_ACU_CFG ACU ConfigurationPVP_ACU_CTL ACU ControlPVP_ACU_OFFSET ACU SUM ConstantPVP_ACU_FACTOR ACU PROD ConstantPVP_ACU_SHIFT ACU Shift ConstantPVP_ACU_MIN ACU Lower Sat Threshold MinPVP_ACU_MAX ACU Upper Sat Threshold MaxPVP_UDS_CFG UDS ConfigurationPVP_UDS_CTL UDS ControlPVP_UDS_OHCNT UDS Output HCNTPVP_UDS_OVCNT UDS Output VCNTPVP_UDS_HAVG UDS HAVGPVP_UDS_VAVG UDS V AVGPVP_IPF0_CFG IPF0 (Camera Pipe) ConfigurationPVP_IPFn_PIPECTL IPFn (Camera/Memory Pipe) Pipe Control PVP_IPFn_CTL IPFn (Camera/Memory Pipe) ControlTable 30-1:ADSP-BF60x PVP Register List (Continued)Name Description PVP_CNVn_C40C41CNVn Coefficients 4,0 and 4,1 PVP_CNVn_C42C43CNVn Coefficients 4,2 and 4,3 PVP_CNVn_C44CNVn Coefficient 4,4PVP_CNVn_SCALE CNVn Scaling FactorPVP_THCn_CFG THCn ConfigurationPVP_THCn_CTL THCn ControlPVP_THCn_HFCNT THCn Histogram Frame Count PVP_THCn_RMAXREP THCn Max RLE ReportsPVP_THCn_CMINVAL THCn Min Clip ValuePVP_THCn_CMINTH THCn Clip Min ThresholdPVP_THCn_CMAXTH THCn Clip Max ThresholdPVP_THCn_CMAXVAL THCn Max Clip ValuePVP_THCn_TH0THCn Threshold Value 0PVP_THCn_TH1THCn Threshold Value 1PVP_THCn_TH2THCn Threshold Value 2PVP_THCn_TH3THCn Threshold Value 3PVP_THCn_TH4THCn Threshold Value 4PVP_THCn_TH5THCn Threshold Value 5PVP_THCn_TH6THCn Threshold Value 6PVP_THCn_TH7THCn Threshold Value 7PVP_THCn_TH8THCn Threshold Value 8PVP_THCn_TH9THCn Threshold Value 9P IPELINED V ISION P ROCESSOR (PVP)PVP F UNCTIONAL D ESCRIPTIONADSP-BF60x PVP Interrupt List PVP_THCn_HCNT7_STATTHCn Histogram Counter Value 7PVP_THCn_HCNT8_STATTHCn Histogram Counter Value 8PVP_THCn_HCNT9_STATTHCn Histogram Counter Value 9PVP_THCn_HCNT10_STATTHCn Histogram Counter Value 10PVP_THCn_HCNT11_STATTHCn Histogram Counter Value 11PVP_THCn_HCNT12_STATTHCn Histogram Counter Value 12PVP_THCn_HCNT13_STAT THCn Histogram Counter Value 13PVP_THCn_HCNT14_STATTHCn Histogram Counter Value 14PVP_THCn_HCNT15_STATTHCn Histogram Counter Value 15PVP_THCn_RREP_STATTHCn Number of RLE Reports PVP_PMA_CFG PMA ConfigurationTable 30-2:ADSP-BF60x PVP Interrupt List Interrupt List Description Interrupt ID DMA Channel Sensitivity PVP0 Camera Pipe DataOut B DMA Channel11138LEVEL PVP0 Camera Pipe DataOut C DMA Channel11239LEVEL PVP0 Camera Pipe StatusOut DMA Channel 11340LEVEL PVP0 Camera Pipe Control In DMA Channel 11441LEVELPVP0 Status 0115LEVEL PVP0 Memory Pipe DataOut DMA Channel 11642LEVELTable 30-1:ADSP-BF60x PVP Register List (Continued)Name Description。
FPGA可编程逻辑器件芯片EP4CE115F29C7中文规格书
When the bits settings are EPPI_CTL.SPLTEO =1, EPPI_CTL.SUBSPLTODD =1 and EPPI_CTL.DMACFG =0, note that although the second Chroma component (U0U1U2U3 in the tables above) sent over the DMA bus is completely packed before the Luma component (Y4Y5Y6Y7 in the tables above), it is intentionally held until that previous word is moved out. This allows the separation of Luma and Chroma values into individual buffers when using 2D-DMA.Table 31-27:8-bit Split Receive Mode with SKIPEN = 0 and SWAPEN = 1 Pin Data (8 bits)SPLTEO=1SUBSPLTODD=0SW APEN=1SKIPEN=0SKIPEO=XSPLTEO=1SUBSPLTODD=1SW APEN=1SKIPEN=0SKIPEO=X DMACFG=1DMACFG=0DMACFG=1DMACFG=0PRIMARY DMA CHANNEL SECONDARY DMA CHANNELPRIMARYDMACHANNEL PRIMARY DMA CHANNEL SECONDARY DMA CHANNEL PRIMARY DMA CHANNEL V 0Y 0U 0Y 1V 1Y 2U 1V 0U 0V 1U 1 V 0U 0V 1U 1 Y 3Y 0Y 1Y 2Y 3Y 0Y 1Y 2Y 3 Y 0Y 1Y 2Y 3Y 0Y 1Y 2Y 3V 2Y 4U 2Y 5V 3V 0V 1V 2V 3 V 0V 1V 2V 3 Y 6U 3V 2U 2V 3U 3 V 2U 2V 3U 3U 0U 1U 2U 3 Y 7Y 4Y 5Y 6Y 7Y 4Y 5Y 6Y 7 Y 4Y 5Y 6Y 7Y 4Y 5Y 6Y 7 V 4 U 0U 1U 2U 3Configuring 16-Bit Split Receive Mode with SPLTWRD=1For 16-bit split receive mode, the EPPI_CTL.PACKEN bit is not valid. The EPPI always packs two 16-bit words into one 32-bit word. The EPPI_CTL.SPLTWRD bit is only valid when the EPPI_CTL.DLEN bit=16 bits.Y 0U 0V 0U 0V 0U 0 Y 1Y 0Y 1Y 0Y 1Y 0Y 1Y 0Y 1 V 1V 0V 1V 0V 1 Y 2U 1V 1U 1V 1U 1U 0U 1 Y 3Y 2Y 3Y 2Y 3Y 2Y 3Y 2Y 3 V 2 U 0U 1 Table 31-30:16-bit Split Receive Mode with SPLTWRD = 1, SKIPEN = 0 and SWAPEN = 0Pin Data(16 bits)SPLTEO=1SUBSPLTODD=0SW APEN=0SKIPEN=0SKIPEO=XSPLT_EVEN_ODD=1SUBSPLTODD=1SW APEN=0SKIPEN=0SKIPEO=X DMACFG=1DMACFG=0DMACFG=1DMACFG=0Primary DMA Channel Secondary DMA Channel Primary DMA Channel Primary DMA Channel Secondary DMA Channel Primary DMA Channel V 0Y 0U 0Y 1V 1Y 2U 1Y 3 Y 3Y 2Y 1Y 0 U 1V 1U 0V 0 Y 3Y 2Y 1Y 0 Y 3Y 2Y 1Y 0Y 3Y 2Y 1Y 0Table 31-29:16-bit Split Receive Mode with SPLTWRD = 0, SKIPEN = 0 and SWAPEN = 1 (Continued)Pin Data (16 bits)SPLTEO=1SUBSPLTODD=0SW APEN=1SKIPEN=0SKIPEO=XSPLTEO=1SUBSPLTODD=1SW APEN=1SKIPEN=0SKIPEO=X DMACFG=1DMACFG=0DMACFG=1DMACFG=0PRIMARY DMA CHANNEL SECONDARY DMA CHANNELPRIMARYDMACHANNEL PRIMARY DMA CHANNEL SECONDARY DMA CHANNEL PRIMARY DMA CHANNELE NHANCED P ARALLEL P ERIPHERAL I NTERFACE (EPPI)EPPI P ROGRAMMING M ODELConfiguring 10/12/14-Bit Transmit ModesFor 10, 12, or 14-bit non-split transmit modes, if the EPPI_CTL.PACKEN bit=1, the DMA is a 32-bit DMA and the EPPI unpacks the 32-bit word from memory into two 16-bit data words, then transmits therequired LSBs from each. The EPPI transmits either the most significant word or the least significant word as the first data, depending on the EPPI_CTL.SWAPEN bit setting. If EPPI_CTL.PACKEN =0, the DMA is a 16-bit DMA and the EPPI transmits the required LSBs. The EPPI_CTL.SWAPEN bit has no effect when the EPPI_CTL.PACKEN bit=0.Configuring 16-Bit Transmit ModeFor 16-bit non-split transmit mode, if the EPPI_CTL.PACKEN bit=1, the DMA is a 32-bit DMA and the EPPI unpacks the 32-bit word from memory into two 16-bit data words to transmit. The EPPI transmits either the MSBs or the LSBs as the first data, depending on the EPPI_CTL.SWAPEN bit setting. If the EPPI_CTL.PACKEN bit=0, the DMA is a 16-bit DMA and the EPPI transmits the data as is. The EPPI_CTL.SWAPEN has no effect when EPPI_CTL.PACKEN bit=0.Table 31-32:Data Sent in 8-bit Transmit Mode with Packing Disabled DMA Data (16 bits)Pin Data SW APEN=X 0x12340x340x23450x450x34560x56Table 31-33:10-bit Transmit Mode with Packing EnabledDMA Data (32 bits)Pin Data when SW APEN=0Pin Data when SW APEN=10x1111 22220x2220x1110x3333 44440x1110x2220x0440x3330x3330x044Table 31-34:10-bit Transmit Mode with Packing DisabledDMA Data (16 bits)Pin Data SW APEN=X 0x12340x2340x23450x3450x34560x0560x45670x167。
工作环境下PSD系统精度测定
收稿日期：２０２００９１７ 基金项目：国家自然科学基金资助项目（５１４０５４１６）；山东省自然科学基金资助项目 （ＺＲ２０１４ＥＥＱ０２４）；烟台市科技发展
计划（２０１３ＺＨ０８５）。 通信作者：董言治（ｄｏｎｇｙａｎｚｈｉ＠ｙｔｕ．ｅｄｕ．ｃｎ），副教授，博士，主要研究方向为嵌入式系统和光电工程。
ｚ＝ 槡ｘ２ ＋ｙ２
（７）
即可代表光点到坐标原点的距离，更为准确。
２２ 测量数据处理流程
整理实测数据时，往往会遇到数据中少数几个
偏差过大的可疑数据，可能由于过失误差引起，这些
数据称为坏值［１０］。在计算精度之前，需要将坏值剔
除，使测试获得的数据规律更为准确。使用拉依达
准则（也称 ３σ准则）剔除坏值，这是 １个经典的方
工作环境下 ＰＳＤ系统精度测定
高晨峻，王凯丽，尉 懿，惠富豪，董言治
（烟台大学光电信息科学技术学院，山东 烟台 ２６４００５）
摘要：利用基于 ＰＳＤ的远距离定位光靶标识别系统在实际环境下获得的大量实际测量数 据，对 ＰＳＤ系统精度测定方法进行了完善。实测的数据首先进行预处理，剔除坏值，随后 给出相关图像并基于统计学方法进行了综合处理与分析检验。精度测定算法均用 ｐｙｔｈｏｎ 进行了编程实现，结果表明，这种方法可以实现 ＰＳＤ测量精度的有效标定，同时也为 ＰＳＤ 实测结果的数据处理提供了有价值的算法参考。 关键词：ＰＳＤ；光靶标识别；数据处理；精度测定 中图分类号：ＴＮ２１５ 文献标志码：Ａ
表 １ 测试 １镜头对准光源 Ｔａｂ．１ Ｔｅｓｔ１Ｌｅｎｓｉｓｆａｃｉｎｇｔｈｅｌｉｇｈｔｓｏｕｒｃｅ
ＰＳＤ位置
光源正对
光源平移 ３ｃｍ
平均值 ／ｍｍ
０．８４７
０．９４１
FPGA可编程逻辑器件芯片EP4CE40F29C8N中文规格书
Arria II Device Handbook Volume 1: Device Interfaces and Integration December 20104.DSP Blocks in Arria II DevicesThis chapter describes how the dedicated high-performance digital signal processing (DSP) blocks in Arria II device are optimized to support DSP applications requiring high data throughput, such as finite impulse response (FIR) filters, infinite impulse response (IIR) filters, fast Fourier transform (FFT) functions, and encoders. You can configure the DSP blocks to implement one of several operational modes to suit your application. The built-in shift register chain, multipliers, and adders/subtractors minimize the amount of external logic to implement these functions, resulting in efficient resource utilization and improved performance and data throughput for DSP applications.These DSP blocks are the fourth generation of hardwired, fixed-function silicon blocks dedicated to maximizing signal processing capability and ease-of-use at the lowest silicon cost.Many complex systems, such as WiMAX, 3GPP WCDMA, high-performance computing (HPC), voice over Internet protocol (VoIP), H.264 video compression, medical imaging, and HDTV, use sophisticated DSP techniques. Arria II devices are ideally suited for these systems because the DSP blocks consist of a combination of dedicated elements that perform multiplication, addition, subtraction, accumulation, summation, and dynamic shift operations.Along with the high-performance Arria II soft logic fabric and memory structures, you can configure DSP blocks to build sophisticated fixed-point and floating-point arithmetic functions. These can be manipulated easily to implement common, larger computationally intensive subsystems such as FIR filters, complex FIR filters, IIR filters, FFT functions, and discrete cosine transform (DCT) functions.This chapter contains the following sections:■“DSP Block Overview” on page4–2■“Simplified DSP Operation” on page4–4■“Operational Modes Overview” on page4–7■“DSP Block Resource Descriptions” on page4–8■“Arria II Operational Mode Descriptions” on page4–14■“Software Support for Arria II Devices” on page4–31Chapter 3:Memory Blocks in Arria II DevicesMemory Modes Arria II Device Handbook Volume 1: Device Interfaces and IntegrationTable 3–7 lists the possible M9K block mixed-port width configurations in true dual-port mode.Table 3–8 lists the possible M144K block mixed-port width configurations in true dual-port mode.In true dual-port mode, M9K and M144K blocks support separate write-enable and read-enable signals. You can save power by keeping the read-enable signal low(inactive) when not reading. Read-during-write operations to the same address can either output “new data” at that location or “old data”.In true dual-port mode, you can access any memory location at any time from either port. When accessing the same memory location from both ports, you must avoid possible write conflicts. A write conflict happens when you attempt to write to the same address location from both ports at the same time. This results in unknown data being stored to that address location. Conflict resolution circuitry is not built into the Arria II memory blocks. You must handle address conflicts external to the RAM block.Table 3–7.M9K Block Mixed-Width Configuration (True-Dual Port Mode)Read PortWrite Port 8K ×14K ×22K ×41K ×8512×161K ×9512×188K ×1v v v v v ——4K ×2v v v v v ——2K ×4v v v v v ——1K ×8v v v v v ——512×16v v v v v ——1K ×9—————v v 512×18—————v v Table 3–8.M144K Block Mixed-Width Configurations (True Dual-Port Mode)Read PortWrite Port16K ×88K ×164K ×3216K ×98K ×184K ×3616K ×8v v v ———8K ×16v v v ———4K ×32v v v ———16K ×9———v v v 8K ×18———v v v 4K ×36———v v vChapter 2:Logic Array Blocks and Adaptive Logic Modules in Arria II DevicesLogic Array Blocks Arria II Device Handbook Volume 1: Device Interfaces and Integration LAB InterconnectsThe LAB local interconnect drives the ALMs in the same LAB using column and row interconnects and the ALM outputs in the same LAB. The direct link connection feature minimizes the use of row and column interconnects, providing higherperformance and flexibility. Adjacent LABs/MLABs, memory blocks, or DSP blocks from the left or right can also drive the LAB’s local interconnect through the direct link connection. Each LAB can drive 30 ALMs through fast local and direct link interconnects. Ten ALMs are in any given LAB and ten ALMs are in each of the adjacent LABs.Figure 2–3 shows the direct link connection, which connects adjacent LABs, memory blocks, DSP blocks, or I/O element (IOE) outputs.Figure 2–3.Direct Link ConnectionsDirect link interconnect to rightDirect link interconnect from right LAB, memory b lock, DSP b lock, or IOE o u tp u tDirect link interconnect fromDirect linkinterconnectto left。
操作教程1_Quartus软件使用流程.
实训1：按键控制LED电路的FPGA实现实验目的：初步了解Quartus编程环境，熟悉开发板的基本使用方法实验内容：定义开发板上的一个按键为输入，一个LED灯为输出，使用按键控制LED灯的亮灭。
实验步骤：1.打开Quartus 11.0软件，选择菜单“File”—“New Project Wizard”，设置如下：点击“Next”，进入下一步填写项目名称和保存路径。
系统默认保存在安装目录下，请修改至D盘或者其他位置：路径中不能有中文和乱码，定义项目的名称为“LED_KEY”，注意下划线和大小写，不能以数字开头，这里的项目名必须要与代码中的模块名称一致。
添加文件，暂时无，按“Next”在器件设置页，在Family栏选择Cyclone IV E，右边Package处选择“FBGA”，然后在列表中找到需要的EP4CE30F23C8器件。
指定仿真方式，暂时无，直接“Next”。
点击“Finish”完成新建项目。
2.新建verilog文件。
点击“File”—“New”，在弹出菜单中选择“Verilog HDL file”，按“OK”，如下所示。
输入代码如下：这里项目名称为LED_KEY，所以模块名称也必须为LED_KEY，注意大小写和下划线。
输入完成后点击保存，保存时注意其默认路径是安装文件夹下，不要保存在那。
修改路径，保存到你所建项目的目录下，保存路径不能有中文和乱码。
3.编译代码点击“Processing”——“Start Compilation”，或者点击工具栏上的快捷按钮，如下图所示。
编译完成后应该不存在错误，但会有一些警告，不用理会。
如下图所示，编译结束，代码，没有问题。
4.分配引脚参看开发板原理图“E40+用户手册”，得知按键PB0的连接到的管脚为R2，上拉，没有按下时为高电平1，按键按下为0。
LED0连接到的管脚为J2，输出为1时，灯亮。
因此，在代码中加入一个“非”操作，使按键按下时，LED亮。
FPGA可编程逻辑器件芯片EP4CE10F17C8L中文规格书
P IPELINED V ISION P ROCESSOR (PVP)PVP F UNCTIONAL D ESCRIPTIONWhen the configuration DMA is granted, the input formatters fetch BCL words until the PVP_IPF0_CFG.START or PVP_IPF1_CFG.START bit is set. The PVP assumes that the BCL describes a valid pipe configu-ration and writes a 1 to the PVP_xxx_CFG.START bits of all involved blocks. The START bit can be seen asa self-clearing block enable bit. The self-clearing nature of this bit ensures that software does not need toperform garbage collection at or after pipe re-configuration. Blocks that are no longer used are automati-cally disabled.The PVP_IPF0_CFG.START and PVP_IPF1_CFG.START bits of the input formatters have additionalpurpose --- to enable the entire camera or memory pipe. While the order of BCSs inside a BCL does not matter, only the very last BCS writes into the PVP_IPF1_CFG register.After the PVP_IPF0_CFG.START or PVP_IPF1_CFG.START bit has been written, the IPF0 starts accepting data from the video sub-system (PPIs or PIXC), and the camera pipe starts processing. Or, IPF1 starts requesting data from data input DMA, and the memory pipe starts processing.For a more detailed description of pipeline operations and functionality, see the Programming Model. Output Formatters (OPFn)The output formatters collect the data results of PVP processing blocks, apply final formatting, andforward the results to the DMA channels. The OPF0, OPF1, and OPF2 formatters serve the camera pipes.The OPF3 formatter serves the memory pipe. Each OPF is associated with a specific DMA channel. The input to each output formatter is selectable from the output of the PVP blocks, as shown in the following tables. For a graphical overview of PVP block connectivity, see Configuring Pipe Structure.Table 30-27:OPF0, OPF1, and OPF2 (Camera Pipe) Block ConnectivityOPF0/1/2 Block I/O Data Format PVP Block ConnectSelections Port ConnectInput 0 s16, u16, s32, u32 IPF0CNV0CNV1CNV2CNV3PMAACUPECTHC0THC1IIM0IIM10, 1, 2 00 0, 1, 2 0Input 1 n/a n/a n/a Output 0 s16, u16, s32, u32DMA n/a Output 1 n/a n/a n/aOPFn_CTL.IUP16 bit determines whether the OPFn blocks latch the lower 16 bits or the upper 16 bits from their 32-bit input.The PVP_OPFn_CTL.ISIZE =2 setting instructs the OPFn block to accepts 8-bit bytes from the data source. To pack values to a 32-bit output, set PVP_OPFn_CTL.OSIZE =0 and set DMA_CFG.PSIZE =2. To only pack two values into a 16-bit output, set PVP_OPFn_CTL.OSIZE =1 and set DMA_CFG.PSIZE =1. To disable packing, set PVP_OPFn_CTL.OSIZE =2 and set DMA_CFG.PSIZE = 0. The PVP_OPFn_CTL.IUP16 bit selects between bits [7:0] and bits [23:16] on the inputs.The PVP_OPFn_CTL.ISIZE =3 setting instructs the OPF to accept 4-bit nibbles from the data source. Nibbles must always be packed to 8-, 16-, or 32-bit entities as described in the OPFn data packing options table. This packing results in dual, quad or octal nibble groups per DMA transfer. The PVP_OPFn_CTL. IUP16 bit selects between bits [3:0] and bits [19:16] on the inputs.NOTE:Data packing has requirements for the horizontal size of data frames, which must be a multiple of the packing ratio.The following table summarizes the OPFn data packing options.Table 30-29:OPFn Data Packing OptionsPVP_OPFn_ CTL.ISIZE PVP_OPFn_CTL.OSIZEDMA_CFG.PSIZEPVP_OPFn_CTL.IUP1632-bit DMA word0020D0[31:0]11100, D0[15:0]10, D0[31:16]020D1[15:0], D0[15:0]1D1[31:16], D0[31:16]22000, 0, 0, D0[7:0]10, 0, 0, D0[23:16]1100, 0, D1[7:0], D0[7:0]10, 0, D1[23:16], D0[23:16]020D3[7:0], D2[7:0], D1[7:0], D0[7:0]1D3[23:16], D2[23:16], D1[23:16], D0[23:16]NOTE :The OPF3 block has a relatively small FIFO, because the memory pipe has been designed to neveroverflow.The OPFn blocks support finish signaling to the DMA. For more information about this feature, see Finish Commands .Threshold-Histogram-Compression (THCn)The PVP features two threshold-histogram-compression blocks. These blocks implement a collection of statistical and range reduction signal processing functions. The input to the THC blocks can be one of the following described in the following table. For a graphical overview of all PVP block interconnections, see Configuring Pipe Structure .The figure gives the detailed overview of a THCn block.Table 30-30:THCn Block Connectivity THC0/1 Block I/O Data Format PVP Block Connect Selections Port Connect Input 0 s32 IPF0IPF1PMACNV0CNV1CNV2CNV3ACUPEC0,1, 20, 1, 21, 2000002 Input 1n/a n/a n/a Output 0s32 (result)IIM0, IIM1, OPF0, OPF1, OPF2, OPF3n/a Output 1n/a n/a n/a Output 2 n/a n/a n/a。
Altera(Intel)FPGA全系列芯片选型手册
逻辑元 LAB/C 总 RAM I/O 件/单元 LB 数 位数 数 数 392 72 291 291 288 392 72 288 321 321 288 291 288 6272 276480 576 2910 2910 12288 59904 59904
291 321 6 423936 6272 276480 576 12288
4608 119808 4608 119808
Cyclone® IV E ACEX-1K® Cyclone® Cyclone® Cyclone® III Cyclone® Cyclone® II Cyclone® Cyclone®
100-TQFP 256-LBGA
100-TQFP EP1C3T100I7N （14x14） EP3C5F256C8N EP4CE6F17C7N
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256-FBGA （17x17） 256-FBGA 256-LBGA （17x17） 144-TQFP 144-LQFP （20x20） 208-PQFP 208-BFQFP （28x28） 208-BFQFP
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144-TQFP EP1K30TC144-3N 下载 （20x20） 144-TQFP EP1C6T144C8N 下载 （20x20） 100-TQFP EP1C3T100I7 （14x14） 256-UBGA （14x14） 144-TQFP （20x20） 144-TQFP （20x20） 324-FBGA （19x19） 144-TQFP （20x20） EP3C5U256C8N EP1C3T144C6N EP2C8T144C8N EP1C4F324C8N EP1C6T144C8 下载 下载 下载 下载 下载 下载
Altera Corporation 产品说明书
EP4CGX15BF14C8N© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified astrademarks or service marks are the property of their respective holders as described at /common/legal.html . Altera warrants performance of itssemiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products andservices at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or servicedescribed herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.Cyclone IV Device Handbook,Volume 1November 2011SubscribeISO 9001:2008 Registered 1.Cyclone IV FPGA Device FamilyOverviewAltera’s new Cyclone ®IV FPGA device family extends the Cyclone FPGA series leadership in providing the market’s lowest-cost, lowest-power FPGAs, now with a transceiver variant. Cyclone IV devices are targeted to high-volume, cost-sensitive applications, enabling system designers to meet increasing bandwidth requirements while lowering costs.Built on an optimized low-power process, the Cyclone IV device family offers the following two variants:■Cyclone IV E—lowest power, high functionality with the lowest cost ■Cyclone IV GX—lowest power and lowest cost FPGAs with 3.125Gbps transceivers 1Cyclone IV E devices are offered in core voltage of 1.0V and 1.2V .f For more information, refer to the Power Requirements for Cyclone IV Deviceschapter.Providing power and cost savings without sacrificing performance, along with a low-cost integrated transceiver option, Cyclone IV devices are ideal for low-cost, small-form-factor applications in the wireless, wireline, broadcast, industrial, consumer, and communications industries.Cyclone IV Device Family FeaturesThe Cyclone IV device family offers the following features:■Low-cost, low-power FPGA fabric:■6K to 150K logic elements■Up to 6.3Mb of embedded memory■Up to 360 18 × 18 multipliers for DSP processing intensive applications ■Protocol bridging applications for under 1.5W total power1–2Chapter 1:Cyclone IV FPGA Device Family OverviewCyclone IV Device Family FeaturesCyclone IV Device Handbook,November 2011Altera CorporationVolume 1■Cyclone IV GX devices offer up to eight high-speed transceivers that provide:■Data rates up to 3.125 Gbps ■8B/10B encoder/decoder■8-bit or 10-bit physical media attachment (PMA) to physical coding sublayer (PCS) interface■Byte serializer/deserializer (SERDES)■Word aligner ■Rate matching FIFO■TX bit slipper for Common Public Radio Interface (CPRI)■Electrical idle■Dynamic channel reconfiguration allowing you to change data rates and protocols on-the-fly■Static equalization and pre-emphasis for superior signal integrity ■150 mW per channel power consumption■Flexible clocking structure to support multiple protocols in a single transceiver block■Cyclone IV GX devices offer dedicated hard IP for PCI Express (PIPE) (PCIe) Gen 1:■×1, ×2, and ×4 lane configurations ■End-point and root-port configurations ■Up to 256-byte payload ■One virtual channel ■ 2 KB retry buffer ■4 KB receiver (Rx) buffer■Cyclone IV GX devices offer a wide range of protocol support:■PCIe (PIPE) Gen 1 ×1, ×2, and ×4 (2.5 Gbps)■Gigabit Ethernet (1.25 Gbps)■CPRI (up to 3.072Gbps)■XAUI (3.125 Gbps)■Triple rate serial digital interface (SDI) (up to 2.97Gbps)■Serial RapidIO (3.125 Gbps)■Basic mode (up to 3.125 Gbps)■V-by-One (up to 3.0Gbps)■DisplayPort (2.7Gbps)■Serial Advanced Technology Attachment (SATA) (up to 3.0Gbps)■OBSAI (up to 3.072Gbps)Chapter 1:Cyclone IV FPGA Device Family Overview 1–3Device ResourcesNovember 2011Altera CorporationCyclone IV Device Handbook,Volume 1■Up to 532 user I/Os■LVDS interfaces up to 840Mbps transmitter (Tx), 875Mbps Rx ■Support for DDR2 SDRAM interfaces up to 200MHz ■Support for QDRII SRAM and DDR SDRAM up to 167MHz■Up to eight phase-locked loops (PLLs) per device ■Offered in commercial and industrial temperature gradesDevice ResourcesTable 1–1 lists Cyclone IV E device resources.Table 1–1.Resources for the Cyclone IV E Device FamilyResources E P 4C E 6E P 4C E 10E P 4C E 15E P 4C E 22E P 4C E 30E P 4C E 40E P 4C E 55E P 4C E 75E P 4C E 115Logic elements (LEs)6,27210,32015,40822,32028,84839,60055,85675,408114,480Embedded memory (Kbits)2704145045945941,1342,3402,7453,888Embedded 18 × 18 multipliers1523566666116154200266General-purpose PLLs 224444444Global Clock Networks 101020202020202020User I/O Banks888888888Maximum user I/O (1)179179343153532532374426528Note to Table 1–1:(1)The user I/Os count from pin-out files includes all general purpose I/O, dedicated clock pins, and dual purpose configuration pins. Transceiverpins and dedicated configuration pins are not included in the pin count.1–4Chapter 1:Cyclone IV FPGA Device Family OverviewDevice ResourcesCyclone IV Device Handbook,November 2011Altera CorporationVolume 1Table 1–2 lists Cyclone IV GX device resources.Table 1–2.Resources for the Cyclone IV GX Device FamilyResourcesE P 4C G X 15E P 4C G X 22E P 4C G X 30(1)E P 4C G X 30(2)E P 4C G X 50(3)E P 4C G X 75(3)E P 4C G X 110(3)E P 4C G X 150(3)Logic elements (LEs)14,40021,28029,44029,44049,88873,920109,424149,760Embedded memory (Kbits)5407561,0801,0802,5024,1585,4906,480Embedded 18 × 18 multipliers 0408080140198280360General purpose PLLs 122 4 (4) 4 (4) 4 (4) 4 (4) 4 (4)Multipurpose PLLs 2 (5) 2 (5) 2 (5) 2 (5) 4 (5) 4 (5) 4 (5) 4 (5)Global clock networks 2020203030303030High-speed transceivers (6)24448888Transceiver maximum data rate (Gbps)2.5 2.5 2.53.125 3.125 3.125 3.125 3.125PCIe (PIPE) hard IP blocks11111111User I/O banks 9 (7)9 (7)9 (7)11 (8)11 (8)11 (8)11 (8)11 (8)Maximum user I/O (9)72150150290310310475475Notes to Table 1–2:(1)Applicable for the F169 and F324 packages.(2)Applicable for the F484 package.(3)Only two multipurpose PLLs for F484 package.(4)Two of the general purpose PLLs are able to support transceiver clocking. For more information, refer to the Clock Networks and PLLs inCyclone IV Devices chapter.(5)You can use the multipurpose PLLs for general purpose clocking when they are not used to clock the transceivers. For more information, referto the Clock Networks and PLLs in Cyclone IV Devices chapter.(6)If PCIe 1, you can use the remaining transceivers in a quad for other protocols at the same or different data rates.(7)Including one configuration I/O bank and two dedicated clock input I/O banks for HSSI reference clock input.(8)Including one configuration I/O bank and four dedicated clock input I/O banks for HSSI reference clock input.(9)The user I/Os count from pin-out files includes all general purpose I/O, dedicated clock pins, and dual purpose configuration pins. Transceiverpins and dedicated configuration pins are not included in the pin count.Chapter 1:Cyclone IV FPGA Device Family Overview 1–7Cyclone IV Device Family Speed GradesNovember 2011Altera CorporationCyclone IV Device Handbook,Volume 1Cyclone IV Device Family Speed GradesTable 1–5 lists the Cyclone IV GX devices speed grades.Table 1–6 lists the Cyclone IV E devices speed grades.Table 1–5.Speed Grades for the Cyclone IV GX Device FamilyDevice N148F169F324F484F672F896EP4CGX15C7, C8, I7C6, C7, C8, I7————EP4CGX22—C6, C7, C8, I7C6, C7, C8, I7———EP4CGX30—C6, C7, C8, I7C6, C7, C8, I7C6, C7, C8, I7——EP4CGX50———C6, C7, C8, I7C6, C7, C8, I7—EP4CGX75———C6, C7, C8, I7C6, C7, C8, I7—EP4CGX110———C7, C8, I7C7, C8, I7C7, C8, I7EP4CGX150———C7, C8, I7C7, C8, I7C7, C8, I7Table 1–6.Speed Grades for the Cyclone IV E Device Family (1),(2)Device E144M164U256F256U484F484F780EP4CE6C8L, C9L, I8L C6, C7, C8, I7, A7—I7NC8L, C9L, I8L C6, C7, C8, I7, A7———EP4CE10C8L, C9L, I8L C6, C7, C8, I7, A7—I7N C8L, C9L, I8L C6, C7, C8, I7, A7———EP4CE15C8L, C9L, I8L C6, C7, C8, I7I7N I7N C8L, C9L, I8L C6, C7, C8, I7, A7—C8L, C9L, I8L C6, C7, C8, I7, A7—EP4CE22C8L, C9L, I8L C6, C7, C8, I7, A7—I7N C8L, C9L, I8L C6, C7, C8, I7, A7———EP4CE30—————C8L, C9L, I8LC6, C7, C8,I7, A7C8L, C9L, I8LC6, C7, C8, I7EP4CE40————I7N C8L, C9L, I8LC6, C7, C8,I7, A7C8L, C9L, I8LC6, C7, C8, I7EP4CE55————I7N C8L, C9L, I8L C6, C7, C8, I7C8L, C9L, I8L C6, C7, C8, I7EP4CE75————I7N C8L, C9L, I8L C6, C7, C8, I7C8L, C9L, I8L C6, C7, C8, I7EP4CE115—————C8L, C9L, I8L C7, C8, I7C8L, C9L, I8L C7, C8, I7Notes to Table 1–6:(1)C8L, C9L, and I8L speed grades are applicable for the 1.0-V core voltage.(2)C6, C7, C8, I7, and A7 speed grades are applicable for the 1.2-V core voltage.1–8Chapter 1:Cyclone IV FPGA Device Family OverviewCyclone IV Device Family ArchitectureCyclone IV Device Family ArchitectureThis section describes Cyclone IV device architecture and contains the followingtopics:■“FPGA Core Fabric”■“I/O Features”■“Clock Management”■“External Memory Interfaces”■“Configuration”■“High-Speed Transceivers (Cyclone IV GX Devices Only)”■“Hard IP for PCI Express (Cyclone IV GX Devices Only)”FPGA Core FabricCyclone IV devices leverage the same core fabric as the very successful Cyclone seriesdevices. The fabric consists of LEs, made of 4-input look up tables (LUTs), memoryblocks, and multipliers.Each Cyclone IV device M9K memory block provides 9 Kbits of embedded SRAMmemory. You can configure the M9K blocks as single port, simple dual port, or truedual port RAM, as well as FIFO buffers or ROM. They can also be configured toimplement any of the data widths in Table1–7.Table1–7.M9K Block Data Widths for Cyclone IV Device FamilyMode Data Width ConfigurationsSingle port or simple dual port ×1, ×2, ×4, ×8/9, ×16/18, and ×32/36True dual port ×1, ×2, ×4, ×8/9, and ×16/18The multiplier architecture in Cyclone IV devices is the same as in the existingCyclone series devices. The embedded multiplier blocks can implement an 18 × 18 ortwo 9 × 9 multipliers in a single block. Altera offers a complete suite of DSP IPincluding finite impulse response (FIR), fast Fourier transform (FFT), and numericallycontrolled oscillator (NCO) functions for use with the multiplier blocks. TheQuartus®II design software’s DSP Builder tool integrates MathWorks Simulink andMATLAB design environments for a streamlined DSP design flow.f For more information, refer to the Logic Elements and Logic Array Blocks in Cyclone IVDevices, Memory Blocks in Cyclone IV Devices, and Embedded Multipliers in Cyclone IVDevices chapters.Cyclone IV Device Handbook,November 2011Altera Corporation Volume 1Chapter 1:Cyclone IV FPGA Device Family Overview 1–9Cyclone IV Device Family ArchitectureNovember 2011Altera CorporationCyclone IV Device Handbook,Volume 1I/O FeaturesCyclone IV device I/O supports programmable bus hold, programmable pull-up resistors, programmable delay, programmable drive strength, programmableslew-rate control to optimize signal integrity, and hot socketing. Cyclone IV devices support calibrated on-chip series termination (Rs OCT) or driver impedance matching (Rs) for single-ended I/O standards. In Cyclone IV GX devices, the high-speedtransceiver I/Os are located on the left side of the device. The top, bottom, and right sides can implement general-purpose user I/Os.Table 1–8 lists the I/O standards that Cyclone IV devices support.The LVDS SERDES is implemented in the core of the device using logic elements.f For more information, refer to the I/O Features in Cyclone IV Devices chapter.Clock ManagementCyclone IV devices include up to 30 global clock (GCLK) networks and up to eight PLLs with five outputs per PLL to provide robust clock management and synthesis. You can dynamically reconfigure Cyclone IV device PLLs in user mode to change the clock frequency or phase.Cyclone IV GX devices support two types of PLLs: multipurpose PLLs and general-purpose PLLs:■Use multipurpose PLLs for clocking the transceiver blocks. You can also use them for general-purpose clocking when they are not used for transceiver clocking.■Use general purpose PLLs for general-purpose applications in the fabric andperiphery, such as external memory interfaces. Some of the general purpose PLLs can support transceiver clocking.f For more information, refer to the Clock Networks and PLLs in Cyclone IV Deviceschapter.External Memory InterfacesCyclone IV devices support SDR, DDR, DDR2 SDRAM, and QDRII SRAM interfaces on the top, bottom, and right sides of the device. Cyclone IV E devices also support these interfaces on the left side of the device. Interfaces may span two or more sides of the device to allow more flexible board design. The Altera ® DDR SDRAM memory interface solution consists of a PHY interface and a memory controller. Altera supplies the PHY IP and you can use it in conjunction with your own custom memorycontroller or an Altera-provided memory controller. Cyclone IV devices support the use of error correction coding (ECC) bits on DDR and DDR2 SDRAM interfaces.Table 1–8.I/O Standards Support for the Cyclone IV Device FamilyTypeI/O StandardSingle-Ended I/O LVTTL, LVCMOS, SSTL, HSTL, PCI, and PCI-XDifferential I/OSSTL, HSTL, LVPECL, BLVDS, LVDS, mini-LVDS, RSDS, and PPDSCyclone IV Device Family Architecturef For more information, refer to the External Memory Interfaces in Cyclone IV Deviceschapter.ConfigurationCyclone IV devices use SRAM cells to store configuration data. Configuration data isdownloaded to the Cyclone IV device each time the device powers up. Low-costconfiguration options include the Altera EPCS family serial flash devices andcommodity parallel flash configuration options. These options provide the flexibilityfor general-purpose applications and the ability to meet specific configuration andwake-up time requirements of the applications.Table1–9 lists which configuration schemes are supported by Cyclone IV devices.Table1–9.Configuration Schemes for Cyclone IV Device FamilyDevices Supported Configuration SchemeCyclone IV GX AS, PS, JTAG, and FPP (1)Cyclone IV E AS, AP, PS, FPP, and JTAGNote to Table1–9:(1)The FPP configuration scheme is only supported by the EP4CGX30F484 and EP4CGX50/75/110/150 devices.IEEE 1149.6 (AC JTAG) is supported on all transceiver I/O pins. All other pinssupport IEEE 1149.1 (JTAG) for boundary scan testing.f For more information, refer to the JTAG Boundary-Scan Testing for Cyclone IV Deviceschapter.For Cyclone IV GX devices to meet the PCIe 100ms wake-up time requirement, youmust use passive serial (PS) configuration mode for the EP4CGX15/22/30 devicesand use fast passive parallel (FPP) configuration mode for the EP4CGX30F484 andEP4CGX50/75/110/150 devices.f For more information, refer to the Configuration and Remote System Upgrades inCyclone IV Devices chapter.The cyclical redundancy check (CRC) error detection feature during user mode issupported in all Cyclone IV GX devices. For Cyclone IV E devices, this feature is onlysupported for the devices with the core voltage of 1.2V.f For more information about CRC error detection, refer to the SEU Mitigation inCyclone IV Devices chapter.High-Speed Transceivers (Cyclone IV GX Devices Only)Cyclone IV GX devices contain up to eight full duplex high-speed transceivers thatcan operate independently. These blocks support multiple industry-standardcommunication protocols, as well as Basic mode, which you can use to implementyour own proprietary protocols. Each transceiver channel has its own pre-emphasisand equalization circuitry, which you can set at compile time to optimize signalintegrity and reduce bit error rates. Transceiver blocks also support dynamicreconfiguration, allowing you to change data rates and protocols on-the-fly.Cyclone IV Device Handbook,November 2011Altera Corporation Volume 1Cyclone IV Device Family ArchitectureFigure1–1 shows the structure of the Cyclone IV GX transceiver.Figure1–1.Transceiver Channel for the Cyclone IV GX Devicef For more information, refer to the Cyclone IV Transceivers Architecture chapter.Hard IP for PCI Express (Cyclone IV GX Devices Only)Cyclone IV GX devices incorporate a single hard IP block for ×1, ×2, or ×4 PCIe(PIPE)in each device. This hard IP block is a complete PCIe(PIPE) protocol solution thatimplements the PHY-MAC layer, Data Link Layer, and Transaction Layerfunctionality. The hard IP for the PCIe (PIPE) block supports root-port and end-pointconfigurations. This pre-verified hard IP block reduces risk, design time, timingclosure, and verification. You can configure the block with the Quartus II software’sPCI Express Compiler, which guides you through the process step by step.f For more information, refer to the PCI Express Compiler User Guide.November 2011Altera Corporation Cyclone IV Device Handbook,Volume 1Reference and Ordering InformationCyclone IV Device Handbook,November 2011Altera CorporationVolume 1Reference and Ordering InformationFigure 1–2 shows the ordering codes for Cyclone IV GX devices.Figure 1–3 shows the ordering codes for Cyclone IV E devices.Figure 1–2.Packaging Ordering Information for the Cyclone IVGX DeviceFigure 1–3.Packaging Ordering Information for the Cyclone IVE DeviceDocument Revision HistoryNovember 2011Altera CorporationCyclone IV Device Handbook,Volume 1Document Revision HistoryTable 1–10 lists the revision history for this chapter.Table 1–10.Document Revision HistoryDateVersion ChangesNovember 20111.5■Updated “Cyclone IV Device Family Features” section.■Updated Figure 1–2 and Figure 1–3.December 2010 1.4■Updated for the Quartus II software version 10.1 release.■Added Cyclone IV E new device package information.■Updated Table 1–1, Table 1–2, Table 1–3, Table 1–5, and Table 1–6.■Updated Figure 1–3.■Minor text edits.July 2010 1.3Updated Table 1–2 to include F484 package information.March 20101.2■Updated Table 1–3 and Table 1–6.■Updated Figure 1–3.■Minor text edits.February 2010 1.1■Added Cyclone IV E devices in Table 1–1, Table 1–3, and Table 1–6 for the Quartus II software version 9.1 SP1 release.■Added the “Cyclone IV Device Family Speed Grades” and “Configuration” sections.■Added Figure 1–3 to include Cyclone IV E Device Packaging Ordering Information.■Updated Table 1–2, Table 1–4, and Table 1–5 for Cyclone IV GX devices.■Minor text edits.November 2009 1.0Initial release.Document Revision History Cyclone IV Device Handbook,November 2011Altera Corporation Volume 1EP4CGX15BF14C8N。
Cyclone IV FPGA 器件系列概述
资源
逻辑单元 (LE)
14,400 21,280 29,440 29,440 49,888 73,920 109,424 149,760
嵌入式存储器 (Kbit)
540
756
1,080
1,080
2,502
4,158
5,490
6,480
嵌入式 18 × 18 乘法器
0
40
80
80
140
198
280
360
章节。 (5) 当多用 PLL 未用于同步收发器时，可将它们用于通用时钟。有关详细信息，请参阅 Clock Networks and PLLs in
Cyclone IV Devices 章节。 (6) 如果 PCIe ×1, 您可以将该象限中其它收发器用于相同或者不同的数据速率下的其他协议。 (7) 包括用于 HSSI 参考时钟输入的一个配置 I/O 块和两个专用的时钟输入 I/O 块。
■ 每器件中高达 8 个锁相环 (PLLs) ■ 支持商业与工业温度等级
器件资源
表 1-1 列出了 Cyclone IV E 器件资源。
表 1-1. Cyclone IV E 器件系列资源
EP4CE6 EP4CE10 EP4CE15 EP4CE22 EP4CE30 EP4CE40 EP4CE55 EP4CE75 EP4CE115
8×8
间距 ( 毫米 )
0.5
0.5
U256 14 × 14
0.8
F256 17 × 17
1.0
U484 19 × 19
0.8
F484 23 × 23
1.0
F780 29 × 29
Cyclone IV 器件手册， 卷1
Verilog入门训练4—三人表决器
实训3：三人表决器的设计与实现问题提出：表决器既是多数通过事件，三个人参与表决，大于或等于二人即为通过。
请设计一个数字组合逻辑电路，实现上述三人表决功能。
1.逻辑抽象假设参与表决的三人分别为A、B、C，表决结果为F。
当三人中有两人或以上同意，即A、B、C三个输入中有两个或以上为1时，F=1。
在FPGA开发板上，同样可以定义三个拨动开关分别代表A、B和C，一个LED灯代表F，表决通过时，灯亮，否则灯灭。
2.列出真值表得到：F=AB+BC+ AC3.使用Quartus 8.0建立项目，建立过程和注意事项见前两周的实验指导，选择器件时随便指定一个。
这里的项目名称为voter3。
（切记项目保存路径和实验过程中新建的文件保存路径都不要出现中文）4.项目建好后，新建Verilog文件并输入代码选择“File”——“New”——“Verilog HDL file”。
第1种方法：直接根据逻辑表达式写出代码，即数据流描述方式。
如下所示。
保存文件，文件名同为voter3。
5.编译项目。
“Processing”——“Start Compilation”6.功能仿真编译通过后，新建波形仿真文件：“File”——“New”，选择“Vector Waveform File”，如下图所示：在出现的编辑界面左侧右键，选择如下：在“Insert Node or Bus”里选择“Node Finder…”在弹出来的“Node Finder”中，首先在“Filter”中选择“Pins：Unassigned”，然后点击“list”，在“Nodes Found”中会列出所有的引脚，第三步选择全部引脚（鼠标拉），点击“>>”，最后点击“OK”即可。
在回到的“Insert Node or Bus”界面点击“OK”。
这时候会看到所有的引脚会列出来，如下所示，三个输入默认为低电平，输出F状态未知。
由实验原理可知，为了得到A、B、C三个信号不同的组合，设置A为10ns周期信号，B为20ns周期信号，C为40ns周期信号。
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H8 J8
J5 DQ0L K6 H5 L8 K8 J7 K7 DQ1L DQ1L
DQ0L
DQ1L
DQ1L
DQ0L
DQ1L
DQ1L
J4 H2 H1 J3 J2 J1
DQS0L/CQ1L,DPCLK0 DQ0L
DQS0L/CQ1L,DPCLK0 DQ1L
DQS0L/CQ1L,DPCLK0 DQ1L
DQS0L/CQ1L,DPCLK0 DQ0L E5 E4 G6 G5 H4 H3 J5 G7 E3 F3 F5 F4 L5 G4 G3 E2 J6 E1 J7 F2 F1 K4 K3 K7 L6 L8 L7 M8 M7 L4 L3 H6 H5 J4 J3 M6 N8 G2 G1 M3 K1 N4 N3 M4 K2 L2 L1 M5 M2 M1 P2 P1 P3 N7 P4 P7 P5 P8 P6 R8 J1 Y2 Y1 R2
Bank Number B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREFB Group Pin Name / Function VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 VREFB2N3 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) DIFFIO_L26n DIFFIO_L27p DIFFIO_L27n DIFFIO_L28p DIFFIO_L28n DIFFIO_L29p DIFFIO_L29n DIFFIO_L30p DIFFIO_L30n VREFB2N0 DIFFIO_L31p DIFFIO_L31n DIFFIO_L32p DIFFIO_L32n DIFFIO_L33p DIFFIO_L33n DIFFIO_L34p DIFFIO_L34n DIFFIO_L35p DIFFIO_L35n DIFFIO_L36p DIFFIO_L36n DIFFIO_L37p DIFFIO_L37n DIFFIO_L38p DIFFIO_L38n DIFFIO_L39p DIFFIO_L39n DIFFIO_L40p DIFFIO_L40n VREFB2N1 DIFFIO_L41p DIFFIO_L41n DIFFIO_L42p DIFFIO_L42n DIFFIO_L43p DIFFIO_L43n DIFFIO_L44p DIFFIO_L44n DIFFIO_L45p DIFFIO_L45n DIFFIO_L46p DIFFIO_L46n DIFFIO_L47p DIFFIO_L47n DIFFIO_L48p DIFFIO_L48n VREFB2N2 DIFFIO_L49p DIFFIO_L49n DIFFIO_L50p DIFFIO_L50n DIFFIO_L51p DIFFIO_L51n RUP1 RDN1 DIFFIO_L52p DIFFIO_L52n Configuration Function F780 R1 U3 U2 R3 R6 R4 R7 T4 T3 T8 U4 R5 U1 V4 V3 V2 V9 AB2 AB1 V1 W2 W1 W3 W4 V6 U5 Y5 Y6 V5 U6 AA7 AA6 T7 AA8 Y7 Y4 Y3 T9 AC2 W8 AC1 V7 AC3 AD2 AD1 AB3 AA4 W9 AB7 AC7 V8 AE1 AE2 AA5 AF2 AB6 AB5 AA3 U7 U8 AC4 AD3 AD4 AE3 AB4 AB8 AC5 AD5 AE4 AF3 F484 M6 M2 M1 M4 M3 N2 N1 L7 M5 DQ1L DQ1L DQ1L DQ1L DQS1L/CQ1L#,DPCLK1 DQ1L DQ1L DM1L/BWS#1L DQ3L DQ3L DQ3L DQ3L DQS1L/CQ1L#,DPCLK1 DQ3L DQ3L DM3L/BWS#3L DQ1L DQ1L DQ1L DQ1L DQS1L/CQ1L#,DPCLK1 DQ1L DQ1L DM1L/BWS#1L DQS for X8/X9 in 780 FBGA DQS for X16/X18 in 780 FBGA DQS for X32/X36 in 780 FBGA DQS for X8/X9 in 484 FBGA DQ1L DM1L/BWS#1L DQ3L DQ3L DQ3L DQ1L DM1L/BWS#1L DQ1L DQ1L DQ1L DQ0L DQ0L DM0L DQ1L DQ1L DQ1L DQS for X16/X18 in 484 FBGA DQS for X32/X36 in 484 FBGA DQ1L DQ1L DQ1L DM1L/BWS#1L DQ3L DQ3L DQ3L DQ1L DQ1L DQ1L DM1L/BWS#1L DQ1L DQ1L DQ1L
DQ2L DQ2L DQ2L
DQ1L DQ1L DQ1L
DQ1L DQ1L DQ1L DQ2L DQ2L DQ1L DQ1L DQ1L DQ1L
E4 E3
DQ2L DQ2L
DQ1L DQ1L
DQ1L DQ1L
DQ2L DQ2L
DQ1L DQ1L
DQ1L DQ1L
C2 C1 D2 D1 H7 H6 J6 E2 E1
DQS2L/CQ3L,CDPCLK0 DQ2L DQ2L
DQS2L/CQ3L,CDPCLK0 DQ1L DQ1L
DQS2L/CQ3L,CDPCLK0 DQ1L DQ1L
DQS2L/CQ3L,CDPCLK0 DQ2L DQ2L
DQS2L/CQ3L,CDPCLK0 DQ1L DQ1L
DQS2L/CQ3L,CDPCLK0 DQ1L DQ1L
DQS0L/CQ1L,DPCLK0 DQ1L DQ1L DQ1L DQ1L
DQS0L/CQ1L,DPCLK0 DQ1L DQ1L DQ1L DQ1L
DQ0L DQ0L
DQ1L DQ1L
DQ1L DQ1L
K2 K1 K5 L5 L2 L1 L4 L3 G1 T2 T1 L6
DQ0L
DQ1L
DQ1L
DQ0L
DQ2L
DQ1L
DQ1L
DQ2L DQ2L
DQ1L DQ1L DQ1L
DQ1L DQ1L DQ1L
DQ1L F2 F1 DM2L DQ0L DM1L/BWS#1L DQ1L
DQ1L DM1L/BWS#1L DQ1L DM2L DQ0L DM1L/BWS#1L DQ1L DM1L/BWS#1L DQ1L
Pin Information for the Cyclone® IV EP4CE30 Device Version 1.0 Notes (1), (2)
Bank Number B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B2 B2 B2 VREFB Group Pin Name / Function VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB1N3 VREFB2N0 VREFB2N0 VREFB2N0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO nSTATUS IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO DCLK IO nCONFIG TDI TCK TMS TDO nCE CLK1 CLK2 CLK3 IO Optional Function(s) DIFFIO_L1p DIFFIO_L1n DIFFIO_L2p DIFFIO_L2n VREFB1N0 DIFFIO_L3p DIFFIO_L3n DIFFIO_L4p DIFFIO_L4n DIFFIO_L5p DIFFIO_L5n DIFFIO_L6p DIFFIO_L6n DIFFIO_L7p DIFFIO_L7n DIFFIO_L8p DIFFIO_L8n VREFB1N1 DIFFIO_L9p DIFFIO_L9n DIFFIO_L10p DIFFIO_L10n DIFFIO_L11p DIFFIO_L11n DIFFIO_L12p DIFFIO_L12n DIFFIO_L13p DIFFIO_L13n DIFFIO_L14p DIFFIO_L14n DIFFIO_L15p DIFFIO_L15n DIFFIO_L16p DIFFIO_L16n DIFFIO_L17p DIFFIO_L17n DIFFIO_L18p DIFFIO_L18n DIFFIO_L19p DIFFIO_L19n VREFB1N2 DIFFIO_L20p DIFFIO_L20n DIFFIO_L21p DIFFIO_L21n DIFFIO_L22p DIFFIO_L22n Configuration Function F780 F484 G4 G3 B2 B1 G5 DQS for X8/X9 in 780 FBGA DQS for X16/X18 in 780 FBGA DQS for X32/X36 in 780 FBGA DQS for X8/X9 in 484 FBGA DQS for X16/X18 in 484 FBGA DQS for X32/X36 in 484 FBGA