MBM29LV160TM90PBT中文资料

MAX2990资料

General DescriptionThe MAX2990 power line communication (PLC) base-band modem delivers a cost-effective, reliable, half-duplex asynchronous data communication over AC power lines at speeds up to 100kbps. The MAX2990 is a highly integrated system-on-chip (SoC) that combines the physical (PH Y) and media access control (MAC)layers using Maxim’s 16-bit MAXQ microcontroller core.The MAX2990 utilizes OFDM modulation techniques to enable robust data communication using the same electrical network that supplies power to all other devices on the network.The MAX2990 includes the MAXQ microcontroller core.The MAXQ is a 16-bit RISC microcontroller with 32kB flash memory, 5.12kB of ROM, and 8kB SRAM, of which 4kB that can be simultaneously accessed by the MCU and the PHY. The MAX2990 is integrated with modules for serial communication (SPI™, I 2C, UART) and a real-time clock (RTC) for time stamping, in addition to standard blocks such as timers, GPIO, and external interrupts.The MAX2990 transceiver is based on an orthogonal frequency division multiplexing (OFDM) technique that allows robust data transmission over poor channel con-ditions specifically for environments with impulsive noise. OFDM with binary phase shift key (BPSK) and forward error correcting (FEC) blocks are used because of their inherent adaptability in the presence of frequency selective channels without the use of equal-izers, resilience to jammer signals, robust communica-tions in the presence of group delay spread, and robustness to impulsive noise. The MAX2990 features jammer cancellation that removes constant sinusoidal interference signals for FCC and ARIB bands. Privacy is provided by DES encryption.The MAX2990 is available in a 64-pin LQFP package and is specified over the -40°C to +85°C extended tem-perature range.ApplicationsFeatures♦Combines the Physical Layer (PHY) and Media Access Controller (MAC)♦Integrated Microcontroller with 32kB Password-Protected Flash Memory and 8kB SRAM♦Maximum Effective Data Rate in Normal Mode32kbps at 10kHz to 95kHz and 100kbps at 10kHz to 490kHz ♦Complies withCENELEC A (10kHz to 95kHz)CENELEC B (95kHz to 120kHz)CENELEC C (120kHz to 140kHz)FCC (10kHz to 490kHz)ARIB (10kHz to 450kHz)♦Includes Forward Error Correction (FEC)Mechanism and CRC16♦Includes Fast DES Engine as theEncryption/Decryption Coprocessor and CRC32♦Jammer Cancellation for FCC and ARIB ♦User-Configured Start and End Operating Frequency♦Carrier Sense Multiple Access/Collision Avoidance (CSMA/CA) Channel Access Arbitration♦Automatic Repeat Request (ARQ) to Enhance Error Detection and Improve Data Reliability ♦Supports SPI, I 2C, and UART Interfaces ♦Real-Time Clock (RTC)♦PWM Counters♦Built-In Test Mode Engine for Identifying Channel ConditionsMAX299010kHz to 490kHz OFDM-Based Power Line Communication Modem________________________________________________________________Maxim Integrated Products1Ordering Information19-4116; Rev 0; 4/08For pricing, delivery, and ordering information,please contact Maxim Direct at 1-888-629-4642,or visit Maxim’s website at .Automatic Meter Reading Home Automation Heating Ventilation and Air Conditioning (HVAC)Building Automation Industrial Automation Lighting ControlSensor Control and Data AcquisitionRemote Monitoring and ControlVoice-Over-Powerline Security Systems/KeylessEntryPin Configuration appears at end of data sheet.Typical Application Circuit appears at end of data sheet.SPI is a trademark of Motorola, Inc.ABRIDGED DATA SHEETM A X 299010kHz to 490kHz OFDM-BasedPower Line Communication Modem Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.24____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600©2008 Maxim Integrated Productsis a registered trademark of Maxim Integrated Products, Inc.Typical Application CircuitPin ConfigurationABRIDGED DATA SHEET。

MBM29LV160TM90资料

(FPT-48P-M19)
(BGA-48P-M20)
* : MirrorFlashTM is a trademark of Fujitsu Limited. Notes : • Programming in byte mode ( × 8) is prohibited. • Programming to the address that already contains data is prohibited (It is mandatory to erase data prior to overprogram on the same address) .
2
元器件交易网
MBM29LV160TM/BM90
s FEATURES
• 0.23 µm Process Technology • Single 3.0 V read, program and erase Minimizes system level power requirements • Industry-standard pinouts 48-pin TSOP (1) (Package suffix: TN - Normal Bend Type) 48-ball FBGA (Package suffix: PBT) • Minimum 100,000 program/erase cycles • High performance 90 ns maximum access time • Sector erase architecture One 16K bytes, two 8K bytes, one 32K bytes, and thirty-one 64K bytes sectors in byte mode One 8K words, two 4K words, one 16K words, and thirty-one 32K words sectors in word mode Any combination of sectors can be concurrently erased. Also supports full chip erase • Boot Code Sector Architecture T = Top sector B = Bottom sector • Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM* Algorithms Automatically program and verifies data at specified address • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic sleep mode When addresses remain stable, automatically switches themselves to low power mode • Program Suspend/Resume Suspends the program operation to allow a read in another address • Low VCC write inhibit ≤ 2.5 V • Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device • Sector Protection Hardware method disables any combination of sectors from program or erase operations • Sector Protection Set function by Extended sector protect command • Fast Programming Function by Extended Command • Temporary sector unprotection Temporary sector unprotection via the RESET pin This feature allows code changes in previously locked sectors • In accordance with CFI (Common Flash Memory Interface)

29LV160B中文资料

MX29LV160BT/BB16M-BIT [2Mx8/1Mx16] CMOS SINGLE VOLTAGE3V ONLY FLASH MEMORYerase operation completion.•- Provides a hardware method of detecting program or erase operation completion.•Sector protection- Hardware method to disable any combination of sectors from program or erase operations- Temporary sector unprotect allows code changes in previously locked sectors.•CFI (Common Flash Interface) compliant- Flash device parameters stored on the device and provide the host system to access•100,000 minimum erase/program cycles•Latch-up protected to 100mA from -1V to VCC+1V •Boot Sector Architecture - T = Top Boot Sector - B = Bottom Boot Sector•Low VCC write inhibit is equal to or less than 1.4V •Package type:- 44-pin SOP - 48-pin TSOP - 48-ball CSP•Compatibility with JEDEC standard- Pinout and software compatible with single-power supply Flash•10 years data retentionFEATURES•Extended single - supply voltage range 2.7V to 3.6V •2,097,152 x 8/1,048,576 x 16 switchable •Single power supply operation- 3.0V only operation for read, erase and program operation•Fully compatible with MX29LV160A device •Fast access time: 70/90ns •Low power consumption- 30mA maximum active current - 0.2uA typical standby current •Command register architecture- Byte/word Programming (9us/11us typical)- Sector Erase (Sector structure 16K-Bytex1,8K-Bytex2, 32K-Bytex1, and 64K-Byte x31)•Auto Erase (chip & sector) and Auto Program- Automatically erase any combination of sectors with Erase Suspend capability.- Automatically program and verify data at specified address•Erase Suspend/Erase Resume- Suspends sector erase operation to read data from,or program data to, any sector that is not being erased,then resumes the erase.•Status Reply- Data polling & Toggle bit for detection of program andGENERAL DESCRIPTIONThe MX29L V160BT/BB is a 16-mega bit Flash memory organized as 2M bytes of 8 bits or 1M words of 16 bits.MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29L V160BT/BB is packaged in 44-pin SOP , 48-pin TSOP and 48-ball CSP . It is designed to be reprogrammed and erased in system or in standard EPROM programmers.The standard MX29LV160BT/BB offers access time as fast as 70ns, allowing operation of high-speed micropro-cessors without wait states. To eliminate bus conten-tion, the MX29LV160BT/BB has separate chip enable (CE) and output enable (OE) controls.MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29LV160BT/BB uses a command register to man-age this functionality. The command register allows for100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility.MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cy-cling. The MX29LV160BT/BB uses a 2.7V~3.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms.The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up pro-tection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V .RPIN CONFIGURATIONSPIN DESCRIPTIONSYMBOL PIN NAME A0~A19Address Input Q0~Q14Data Input/OutputQ15/A-1Q15(Word mode)/LSB addr(Byte mode)CE Chip Enable Input WE Write Enable Input BYTE Word/Byte Selection inputRESET Hardware Reset Pin/Sector Protect Unlock OE Output Enable Input RY/BY Ready/Busy OutputVCC Power Supply Pin (2.7V~3.6V)GNDGround Pin48 TSOP (Standard Type) (12mm x 20mm)44 SOP(500 mil)A B C D E F GH6A13A12A14A15A16BYTE Q15/A-1GND 5A9A8A10A11Q7Q14Q13Q64WE RESET NC A19Q5Q12VCC Q43RY/BY NC A18NC Q2Q10Q11Q32A7A17A6A5Q0Q8Q9Q11A3A4A2A1A0CEOEGND48-Ball CSP 6mm x 8mm (Ball Pitch=0.8mm) Top View, Balls Facing Down234567891011121314151617181920212244434241403938373635343332313029282726252423RESETA18A17A7A6A5A4A3A2A1A0CE GND OE Q0Q8Q1Q9Q2Q10Q3Q11WE A19A8A9A10A11A12A13A14A15A16BYTE GND Q15/A-1Q7Q14Q6Q13Q5Q12Q4VCCM X 29L V 160B T /B BA15A14A13A12A11A10A9A8A19NC WE RESETNC NC RY/BY A18A17A7A6A5A4A3A2A1123456789101112131415161718192021222324A16BYTE GND Q15/A-1Q7Q14Q6Q13Q5Q12Q4VCC Q11Q3Q10Q2Q9Q1Q8Q0OE GND CE A0484746454443424140393837363534333231302928272625MX29LV160BT/BBBLOCK STRUCTURETable 1: MX29LV160BT SECTOR ARCHITECTURESector Sector Size Address range Sector Address Byte Mode Word Mode Byte Mode(x8) Word Mode(x16)A19A18A17A16A15A14A13A12 SA064Kbytes32Kwords000000-00FFFF00000-07FFF00000X X X SA164Kbytes32Kwords010000-01FFFF08000-0FFFF00001X X X SA264Kbytes32Kwords020000-02FFFF10000-17FFF00010X X X SA364Kbytes32Kwords030000-03FFFF18000-1FFFF00011X X X SA464Kbytes32Kwords040000-04FFFF20000-27FFF00100X X X SA564Kbytes32Kwords050000-05FFFF28000-2FFFF00101X X X SA664Kbytes32Kwords060000-06FFFF30000-37FFF00110X X X SA764Kbytes32Kwords070000-07FFFF38000-3FFFF00111X X X SA864Kbytes32Kwords080000-08FFFF40000-47FFF01000X X X SA964Kbytes32Kwords090000-09FFFF48000-4FFFF01001X X X SA1064Kbytes32Kwords0A0000-0AFFFF50000-57FFF01010X X X SA1164Kbytes32Kwords0B0000-0BFFFF58000-5FFFF01011X X X SA1264Kbytes32Kwords0C0000-0CFFFF60000-67FFF01100X X X SA1364Kbytes32Kwords0D0000-0DFFFF68000-6FFFF01101X X X SA1464Kbytes32Kwords0E0000-0EFFFF70000-77FFF01110X X X SA1564Kbytes32Kwords0F0000-0FFFFF78000-7FFFF01111X X X SA1664Kbytes32Kwords100000-10FFFF80000-87FFF10000X X X SA1764Kbytes32Kwords110000-11FFFF88000-8FFFF10001X X X SA1864Kbytes32Kwords120000-12FFFF90000-97FFF10010X X X SA1964Kbytes32Kwords130000-13FFFF98000-9FFFF10011X X X SA2064Kbytes32Kwords140000-14FFFF A0000-A7FFF10100X X X SA2164Kbytes32Kwords150000-15FFFF A8000-AFFFF10101X X X SA2264Kbytes32Kwords160000-16FFFF B0000-B7FFF10110X X X SA2364Kbytes32Kwords170000-17FFFF B8000-BFFFF10111X X X SA2464Kbytes32Kwords180000-18FFFF C0000-C7FFF11000X X X SA2564Kbytes32Kwords190000-19FFFF C8000-CFFFF11001X X X SA2664Kbytes32Kwords1A0000-1AFFFF D0000-D7FFF11010X X X SA2764Kbytes32Kwords1B0000-1BFFFF D8000-DFFFF11011X X X SA2864Kbytes32Kwords1C0000-1CFFFF E0000-E7FFF11100X X X SA2964Kbytes32Kwords1D0000-1DFFFF E8000-EFFFF11101X X X SA3064Kbytes32Kwords1E0000-1EFFFF F0000-F7FFF11110X X X SA3132Kbytes16Kwords1F0000-1F7FFF F8000-FBFFF111110X X SA328Kbytes4Kwords1F8000-1F9FFF FC000-FCFFF11111100 SA338Kbytes4Kwords1FA000-1FBFFF FD000-FDFFF11111101 SA3416Kbytes8Kwords1FC000-1FFFFF FE000-FFFFF1111111XNote: Byte mode: address range A19:A-1, word mode:address range A19:A0.Table 2: MX29LV160BB SECTOR ARCHITECTURESector Sector Size Address range Sector Address Byte Mode Word Mode Byte Mode (x8)Word Mode (x16)A19A18A17A16A15A14A13A12 SA016Kbytes8Kwords000000-003FFF00000-01FFF0000000X SA18Kbytes4Kwords004000-005FFF02000-02FFF00000010 SA28Kbytes4Kwords006000-007FFF03000-03FFF00000011 SA332Kbytes16Kwords008000-00FFFF04000-07FFF000001X X SA464Kbytes32Kwords010000-01FFFF08000-0FFFF00001X X X SA564Kbytes32Kwords020000-02FFFF10000-17FFF00010X X X SA664Kbytes32Kwords030000-03FFFF18000-1FFFF00011X X X SA764Kbytes32Kwords040000-04FFFF20000-27FFF00100X X X SA864Kbytes32Kwords050000-05FFFF28000-2FFFF00101X X X SA964Kbytes32Kwords060000-06FFFF30000-37FFF00110X X X SA1064Kbytes32Kwords070000-07FFFF38000-3FFFF00111X X X SA1164Kbytes32Kwords080000-08FFFF40000-47FFF01000X X X SA1264Kbytes32Kwords090000-09FFFF48000-4FFFF01001X X X SA1364Kbytes32Kwords0A0000-0AFFFF50000-57FFF01010X X X SA1464Kbytes32Kwords0B0000-0BFFFF58000-5FFFF01011X X X SA1564Kbytes32Kwords0C0000-0CFFFF60000-67FFF01100X X X SA1664Kbytes32Kwords0D0000-0DFFFF68000-6FFFF01101X X X SA1764Kbytes32Kwords0E0000-0EFFFF70000-77FFF01110X X X SA1864Kbytes32Kwords0F0000-0FFFFF78000-7FFFF01111X X X SA1964Kbytes32Kwords100000-10FFFF80000-87FFF10000X X X SA2064Kbytes32Kwords110000-11FFFF88000-8FFFF10001X X X SA2164Kbytes32Kwords120000-12FFFF90000-97FFF10010X X X SA2264Kbytes32Kwords130000-13FFFF98000-9FFFF10011X X X SA2364Kbytes32Kwords140000-14FFFF A0000-A7FFF10100X X X SA2464Kbytes32Kwords150000-15FFFF A8000-AFFFF10101X X X SA2564Kbytes32Kwords160000-16FFFF B0000-B7FFF10110X X X SA2664Kbytes32Kwords170000-17FFFF B8000-BFFFF10111X X X SA2764Kbytes32Kwords180000-18FFFF C0000-C7FFF11000X X X SA2864Kbytes32Kwords190000-19FFFF C8000-CFFFF11001X X X SA2964Kbytes32Kwords1A0000-1AFFFF D0000-D7FFF11010X X X SA3064Kbytes32Kwords1B0000-1BFFFF D8000-DFFFF11011X X X SA3164Kbytes32Kwords1C0000-1CFFFF E0000-E7FFF11100X X X SA3264Kbytes32Kwords1D0000-1DFFFF E8000-EFFFF11101X X X SA3364Kbytes32Kwords1E0000-1EFFFF F0000-FFFFF11110X X X SA3464Kbytes32Kwords1F0000-1FFFFF F8000-FFFFF11111X X XNote: Byte mode:address range A19:A-1, word mode:address range A19:A0.AUTOMATIC PROGRAMMINGThe MX29LV160BT/BB is byte/word programmable us-ing the Automatic Programming algorithm. The Auto-matic Programming algorithm makes the external sys-tem do not need to have time out sequence nor to verify the data programmed. The typical chip programming time at room temperature of the MX29LV160BT/BB is less than 18 sec (byte)/12 sec (word). AUTOMATIC PROGRAMMING ALGORITHM MXIC's Automatic Programming algorithm requires the user to only write program set-up commands (including 2 unlock write cycle and A0H) and a program command (program data and address). The device automatically times the programming pulse width, provides the pro-gram verification, and counts the number of sequences.A status bit similar to DA TA polling and a status bit tog-gling between consecutive read cycles, provide feed-back to the user as to the status of the programming operation. Refer to write operation status, table 7, for more information on these status bits. AUTOMATIC CHIP ERASEThe entire chip is bulk erased using 10 ms erase pulses according to MXIC's Automatic Chip Erase algorithm. T ypical erasure at room temperature is accomplished in less than 25 second. The Automatic Erase algorithm automatically programs the entire array prior to electri-cal erase. The timing and verification of electrical erase are controlled internally within the device. AUTOMATIC SECTOR ERASEThe MX29LV160BT/BB is sector(s) erasable using MXIC's Auto Sector Erase algorithm. The Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase. The timing and verification of electrical erase are controlled inter-nally within the device. An erase operation can erase one sector, multiple sectors, or the entire device. AUTOMATIC ERASE ALGORITHMMXIC's Automatic Erase algorithm requires the user to write commands to the command register using stan-dard microprocessor write timings. The device will auto-matically pre-program and verify the entire array. Then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecu-tive read cycles provides feedback to the user as to the status of the erasing operation.Register contents serve as inputs to an internal state-machine which controls the erase and programming cir-cuitry. During write cycles, the command register inter-nally latches address and data needed for the program-ming and erase operations. During a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of WE or CE, whichever hap-pens first.MXIC's Flash technology combines years of EPROM experience to produce the highest levels of quality, reli-ability, and cost effectiveness. The MX29LV160BT/BB electrically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes are programmed by us-ing the EPROM programming mechanism of hot elec-tron injection.During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the device stays in read mode. After the state machine has completed its task, it will allow the command regis-ter to respond to its full command set. AUTOMATIC SELECTThe automatic select mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on Q7~Q0. This mode is mainly adapted for programming equipment on the de-vice to be programmed with its programming algorithm. When programming by high voltage method, automatic select mode requires VID (11.5V to 12.5V) on address pin A9. Other address pin A6, A1 and A0 as referring to T able 3. In addition, to access the automatic select codes in-system, the host can issue the automatic select com-mand through the command register without requiring VID, as shown in table 5.To verify whether or not sector being protected, the sec-tor address must appear on the appropriate highest or-der address bit (see Table 1 and Table 2). The rest ofaddress bits, as shown in T able 3, are don't care. Onceall necessary bits have been set as required, the pro-gramming equipment may read the corresponding iden-tifier code on Q7~Q0.TABLE 3. MX29LV160BT/BB AUTO SELECT MODE BUS OPERATION (A9=VID)A19A11A9A8A6A5A1A0Description Mode CE OE WE RESET | | | |Q15~Q0A12A10A7A2Read Silicon ID L L H H X X VID X L X L L C2H Manufacture CodeDevice ID Word L L H H X X VID X L X L H22C4H (Top Boot Block)Byte L L H H X X VID X L X L H XXC4H Device ID Word L L H H X X VID X L X L H2249H (Bottom Boot Block)Byte L L H H X X VID X L X L H XX49HXX01HSector Protection L L H H SA X VID X L X H L(protected) Verification XX00H(unprotected) NOTE: SA=Sector Address, X=Don't Care, L=Logic Low, H=Logic HighQUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODEMX29LV160BT/BB is capable of operating in the CFI mode. This mode all the host system to determine the manufacturer of the device such as operating param-eters and configuration. Two commands are required in CFI mode. Query command of CFI mode is placed first, then the Reset command exits CFI mode. These are described in T able 4.The single cycle Query command is valid only when the device is in the Read mode, including Erase Suspend, Standby mode, and Automatic Select mode; however, it is ignored otherwise.The Reset command exits from the CFI mode to the Read mode, or Erase Suspend mode, or Automatic Se-lect mode. The command is valid only when the device is in the CFI mode.Table 4-1. CFI mode: Identification Data Values(All values in these tables are in hexadecimal)Description Address Address Data(Byte Mode)(Word Mode) Query-unique ASCII string "QRY"201000512211005224120059 Primary vendor command set and control interface ID code2613000228140000 Address for primary algorithm extended query table2A1500402C160000 Alternate vendor command set and control interface ID code (none)2E17000030180000 Address for secondary algorithm extended query table (none)32190000341A0000 Table 4-2. CFI Mode: System Interface Data Values(All values in these tables are in hexadecimal)Description Address Address Data(Byte Mode)(Word Mode) VCC supply, minimum (2.7V)361B0027 VCC supply, maximum (3.6V)381C0036 VPP supply, minimum (none)3A1D0000 VPP supply, maximum (none)3C1E0000 Typical timeout for single word/byte write (2N us)3E1F0004 Typical timeout for Minimum size buffer write (2N us) (not supported)40200000 Typical timeout for individual sector erase (2N ms)4221000A Typical timeout for full chip erase (2N ms)44220000 Maximum timeout for single word/byte write times (2N X Typ)46230005 Maximum timeout for buffer write times (2N X Typ)48240000 Maximum timeout for individual sector erase times (2N X Typ)4A250004 Maximum timeout for full chip erase times (not supported)4C260000Table 4-3. CFI Mode: Device Geometry Data Values(All values in these tables are in hexadecimal)Description Address Address Data(Byte Mode)(Word Mode) Device size (2N bytes)4E270015 Flash device interface code (x8/x16 async.)5028000252290000 Maximum number of bytes in multi-byte write (not supported)542A0000562B0000 Number of erase sector regions582C0004 Erase sector region 1 information (refer to the CFI publication 100)5A2D00005C2E00005E2F004060300000 Erase sector region 2 information62310001643200006633002068340000 Erase sector region 3 information6A3500006C3600006E37008070380000 Erase sector region 4 information7239001E743A0000763B0000783C0001 Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values(All values in these tables are in hexadecimal)Description Address Address Data(Byte Mode)(Word Mode) Query-unique ASCII string "PRI"804000508241005284420049 Major version number, ASCII86430031 Minor version number, ASCII88440030 Address sensitive unlock (0=required, 1= not required)8A450000 Erase suspend (2= to read and write)8C460002 Sector protect (N= # of sectors/group)8E470001 Temporary sector unprotect (1=supported)90480001 Sector protect/chip unprotect scheme92490004 Simultaneous R/W operation (0=not supported)944A0000 Burst mode type (0=not supported)964B0000 Page mode type (0=not supported)984C0000in the improper sequence will reset the device to the read mode. Table 5 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress.COMMAND DEFINITIONSDevice operations are selected by writing specific ad-dress and data sequences into the command register.Writing incorrect address and data values or writing themFirst Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus CommandBusCycleCycleCycleCycleCycle CycleCycle AddrData Addr Data Addr Data Addr DataAddrData Addr DataReset 1XXXH F0H Read1RARDRead Silicon IDWord 4555H AAH 2AAH 55H 555H 90H ADI DDI Byte4AAAH AAH 555H 55H AAAH 90H ADI DDI Sector Protect Word4555H AAH 2AAH55H555H90H (SA)XX00H Verifyx02HXX01H Byte4AAAH AAH 555H55HAAAH90H (SA)00H x04H01H Program Word 4555H AAH 2AAH 55H 555H A0H PA PD Byte4AAAH AAH 555H 55H AAAH A0H PAPDChip Erase Word 6555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H Byte6AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H AAAH 10H Sector Erase Word 6555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H Byte6AAAH AAH 555H 55HAAAH80H AAAH AAH555H 55HSA30HSector Erase Suspend 1XXXH B0H Sector Erase Resume 1XXXH 30H CFI QueryWord 155H 98ByteAAHTABLE 5. MX29LV160BT/BB COMMAND DEFINITIONSNote:1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacturer code,A1=0, A0 = 1 for device code. A2-A19=do not care. (Refer to table 3)DDI = Data of Device identifier : C2H for manufacture code, C4H/49H (x8) and 22C4H/2249H (x16) for device code. X = X can be VIL or VIHRA=Address of memory location to be read. RD=Data to be read at location RA.2.PA = Address of memory location to be programmed. PD = Data to be programmed at location PA. SA = Address of the sector to be erased.3.The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or 555H to Address A10~A-1 in byte mode.Address bit A11~A19=X=Don't care for all address commands except for Program Address (P A) and Sector Address (SA). Write Sequence may be initiated with A11~A19 in either state.4. For Sector Protect Verify operation: If read out data is 01H, it means the sector has been protected. If read out data is 00H,it means the sector is still not being protected.5. Any number of CFI data read cycles are permitted.TABLE 6. MX29LV160BT/BB BUS OPERATIONADDRESS Q8~Q15 DESCRIPTION CE OE WE RESET A19A11A9A8A6A5A1A0Q0~Q7BYTE BYTEA12A10A7A2=VIH=VIL Read L L H H AIN Dout Dout Q8~Q14=High ZQ15=A-1 Write L H L H AIN DIN(3)DINReset X X X L X High Z High Z High Z Temporary sector unlock X X X VID AIN DIN DIN High Z Output Disable L H H H X High Z High Z High Z Standby Vcc±X X Vcc±X High Z High Z High Z0.3V0.3VSector Protect L H L VID SA X X X L X H L DIN X X Chip Unprotect L H L VID X X X X H X H L DIN X X Sector Protection Verify L L H H SA X VID X L X H L CODE(5)X XNOTES:1.Manufacturer and device codes may also be accessed via a command register write sequence. Refer to T able 4.2. VID is the high voltage, 11.5V to 12.5V.3.Refer to T able 5 for valid Data-In during a write operation.4.X can be VIL or VIH.5.Code=00H/XX00H means unprotected.Code=01H/XX01H means protected.6.A19~A12=Sector address for sector protect.7.The sector protect and chip unprotect functions may also be implemented via programming equipment.REQUIREMENTS FOR READING ARRAY DATAT o read array data from the outputs, the system must drive the CE and OE pins to VIL. CE is the power control and selects the device. OE is the output control and gates array data to the output pins. WE should remain at VIH.The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory con-tent occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid address on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. WRITE COMMANDS/COMMAND SEQUENCESTo program data to the device or erase sectors of memory, the system must drive WE and CE to VIL, and OE to VIH.An erase operation can erase one sector, multiple sec-tors, or the entire device. T able 1 and T able 2 indicate the address space that each sector occupies. A "sector ad-dress" consists of the address bits required to uniquely select a sector. The Writing specific address and data commands or sequences into the command register ini-tiates device operations. Table 5 defines the valid regis-ter command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. Section has de-tails on erasing a sector or the entire chip, or suspend-ing/resuming the erase operation.After the system writes the "read silicon-ID" and "sector protect verify" command sequence, the device enters the "read silicon-ID" and "sector protect verify" mode. The system can then read "read silicon-ID" and "sector protect verify" codes from the internal register (which is separate from the memory array) on Q7-Q0. Standard read cycle timings apply in this mode. Refer to the "read silicon-ID" and "sector protect verify" Mode and "read silicon-ID" and "sector protect verify" Command Se-quence section for more information.ICC2 in the DC Characteristics table represents the ac-tive current specification for the write mode. The "AC Characteristics" section contains timing specification table and timing diagrams for write operations. STANDBY MODEWhen using both pins of CE and RESET, the device enter CMOS Standby with both pins held at Vcc ± 0.3V. If CE and RESET are held at VIH, but not within the range of VCC ± 0.3V, the device will still be in the standby mode, but the standby current will be larger. During Auto Algorithm operation, Vcc active current (ICC2) is required even CE = "H" until the operation is completed. The de-vice can be read with standard access time (tCE) from either of these standby modes, before it is ready to read data.OUTPUT DISABLEWith the OE input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins to be in a high impedance state.RESET OPERATIONThe RESET pin provides a hardware method of reset-ting the device to reading array data. When the RESET pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write com-mands for the duration of the RESET pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be re-initiated once the device is ready to accept another com-mand sequence, to ensure data integrity.Current is reduced for the duration of the RESET pulse. When RESET is held at VSS±0.3V, the device draws CMOS standby current (ICC4). If RESET is held at VIL but not within VSS±0.3V, the standby current will be greater.The RESET pin may be tied to system reset circuitry. A system reset would that also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.If RESET is asserted during a program or erase opera-READ/RESET COMMANDThe read or reset operation is initiated by writing the read/reset command sequence into the command reg-ister. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register contents are altered.If program-fail or erase-fail happen, the write of F0H will reset the device to abort the operation. A valid com-mand must then be written to place the device in the desired state.SILICON-ID READ COMMANDFlash memories are intended for use in applications where the local CPU alters memory contents. As such, manu-facturer and device codes must be accessible while the device resides in the target system. PROM program-mers typically access signature codes by raising A9 to a high voltage (VID). However, multiplexing high volt-age onto address lines is not generally desired system design practice.The MX29LV160BT/BB contains a Silicon-ID-Read op-eration to supple traditional PROM programming meth-odology. The operation is initiated by writing the read silicon ID command sequence into the command regis-ter. Following the command write, a read cycle with A1=VIL, A0=VIL retrieves the manufacturer code of C2H/ 00C2H. A read cycle with A1=VIL, A0=VIH returns the device code of C4H/22C4H for MX29LV160BT, 49H/ 2249H for MX29LV160BB.The system must write the reset command to exit the "Silicon-ID Read Command" code.AUTOMATIC CHIP ERASE COMMANDSChip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command 80H. Two more "unlock" write cy-cles are then followed by the chip erase command 10H. The device does not require the system to entirely pre-program prior to executing the Automatic Chip Erase. Upon executing the Automatic Chip Erase, the device will automatically program and verify the entire memory for an all-zero data pattern. When the device is auto-matically verified to contain an all-zero pattern, a self-timed chip erase and verify begin. The erase and verify operations are completed when the data on Q7 is "1" at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations.When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required).If the Erase operation was unsuccessful, the data on Q5 is "1" (see Table 8), indicating the erase operation exceed internal timing limit.The automatic erase begins on the rising edge of the last WE or CE pulse, whichever happens first in the command sequence and terminates when either the data on Q7 is "1" at which time the device returns to the Read mode or the data on Q6 stops toggling for two consecutive read cycles at which time the device re-turns to the Read mode.tion, the RY/BY pin remains a "0" (busy) until the inter-nal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY to determine whether the reset op-eration is complete. If RESET is asserted when a pro-gram or erase operation is completed within a time of tREADY (not during Embedded Algorithms). The sys-tem can read data tRH after the RESET pin returns to VIH.Refer to the AC Characteristics tables for RESET parameters and to Figure 22 for the timing diagram.。

am29LV160B芯片简介

3.3 自动睡眠模式
自动睡眠模式最小化了Flash器件的功耗,当地址稳定时间超过tACC+30ns (tACC为器件的典型访问时间,概述中已经介绍过)时,器件自动进入该模式,在该模式下,输出数据被锁存在外总线上,可以被系统使用.
3.4 复位
系统复位后,器件回到读数据模式下,复位可以用硬件和软件两种方法实现,软件实现方法如前面表格中所示,在后面指令中还要介绍,硬件实现通过/RESET引脚实现.
当把器件的/RESET引脚置于低电平时,器件会立即终止所有的操作,所有的数据输出成为高阻态,而且忽略此期间内所有的读写操作请求.与备用模式类似的,当/RESET引脚置于 VSS±0.3V时,器件电流被拉至CMOS备用电流, 而当/RESET引脚置于VIL时,也将被拉至备用电流,但是要比上述情况下大.
4.4 字/字节编程命令序列
该序列跟在解锁操作后,包含4个总线周期操作.在相应地址写入数据后,期间将自动返回到读状态下,地址将不再被锁存.在器件内部依据编程指令进行编程操作时,除硬件复位外的其它指令都将被忽略.硬件复位可以立即终止器件的任何操作,将器件复位到读状态.
需要注意的是,存储器里的任何一位数据都不能通过编程的方法从’0’变为’1’.试图这样做将会引起操作的中止,并将DQ5置为‘1’,或者引起器件内部的轮询结果显示”操作已成功完成”的结果,然而,接着读这个单元的内容将会发现,该位数据依然为’0’.只有擦除操作可以将’0’变为’1’.
3.5 扇区保护/解除保护
出厂时,所有扇区都是未加保护的.保护的建立和解除可以用两种方法实现.基本方法就是将/RESET引脚置于VID,这可以在系统或用编程器件实现. 具体的操作方法见操作流程图3-1.图3-2显示的是其时序图.

AM29LV160DB中文数据手册

Am29LV160D16 Megabit (2 M x 8-Bit/1 M x 16-Bit)CMOS 3.0 V olt-only Boot Sector Flash Memory鲜明的特点1.单电源工作--全电压范围：2.7至3.6伏特，电池供电应用的读写操作--稳压范围：3.0到3.6伏读取和写入操作，并与高性能的3.3伏微处理器兼容2.0.23μ微米制造工艺技术--0.32微米AM29LV160B装置完全兼容3.高性能--快速存取时间为70纳秒4.超低功耗（5MHz的典型值）--自动睡眠模式电流为200 nA--待机模式电流为200 nA--9毫安的读出电流--20毫安程序/擦除电流5．灵活的部门架构--一个16千字节，两个8千字节，32千字节，31个64千字节扇区（字节模式）--一个8 kword的，两个4 kword的，一个16 kword的，和三十一个32 kword的扇区（字模式）--支持全芯片擦除--扇区保护功能：一种硬件方法锁定一个扇区，以防止任何程序或擦除操作在该部门的部门可以被锁定在系统或通过编程设备临时机构撤消功能允许在以前的代码更改锁定扇区6.解锁绕道程序命令--发出多个程序的命令序列时降低了总体规划7.顶部或底部启动块配置8.嵌入式算法--嵌入式擦除算法自动预编程和擦除整个芯片或指定部门的任何组合--嵌入式程序算法自动写入和验证数据在指定的地址9.至少1000000写周期保证每扇区10.20年的数据保存在125°C--系统的寿命运行可靠11.封装选项-- 48 balld的FBGA-- 48针的TSOP--44针的SO12.CFI（通用闪存接口）兼容--为系统提供设备特定信息，允许主机软件，轻松地配置不同的闪存设备13.与JEDEC标准兼容--引脚与单电源闪存软件兼容--优越的无意的写保护14.数据＃轮询和切换位--提供一个检测程序或擦除操作完成的软件方法15. 准备/繁忙＃引脚（RY / BY＃）--提供一个检测的程序或擦除周期完成硬件的方法（不适用44引脚SO）16.擦除暂停/删除恢复--挂起擦除操作来读取数据，数据或程序，一个扇区不被擦除，然后恢复擦除操作17.硬件复位引脚（RESET＃）--硬件方法重置设备读数数组数据。

PM-160说明书

Serial/PROFIBUS-DP 网关 PM-160 产品手册
REV 3.7
上海泗博自动化技术有限公司
SiboTech Automation Co., Ltd.
技术支持热线:021-3126 5138 E-mail: .................................................................................................................................................... 3 1.1 产品功能 ................................................................................................................................................. 3 1.2 产品特点 ................................................................................................................................................. 3 1.3 技术指标 ................................................................................................................................................. 3 1.4 电磁兼容性能........................................................................................................................................ 5 1.4.1 高频干扰试验(GB/T15153.1 classⅢ) .................................................................................. 5 1.4.2 快速瞬变脉冲群试验(GB/T17626.4 classⅢ) .................................................................... 5 1.4.3 静电放电干扰(GB/T 17626.2 classⅢ) ................................................................................. 5 1.4.4 辐射电磁场(GB/T 17626.3 classⅢ) ..................................................................................... 5

AM29LV400B芯片中文资料整理

AM29LV400B4兆位（512 K x8-Bit/256 K×16位）CMOS3.0伏特-只引导扇区闪存特点：●. 单电源操作- 全电压范围：2.7至3.6伏的读取和写入操作电池供电的应用- 稳压电压范围：3.0至3.6伏读和写入操作，并与高性能的3.3伏的微处理器兼容●0.35微米工艺技术制造- 兼容0.5μ米Am29LV400设备●高性能- 全电压范围：尽可能快的访问时间为80 ns的- 稳压范围：访问时间尽可能快70纳秒●超低功耗（典型值5兆赫）- 200 nA的自动休眠模式电流- 200 nA的待机模式电流- 7 mA的读取电流- 15毫安编程/擦除电流●灵活的部门架构- 一个16KB，2个8 KB的，一个32KB，和7个64 KB的部门（字节模式）- 一个8 K字，两个4 K字，一个16 K字，和7个32 K字部门（字模式）- 支持整片擦除- 扇区保护功能：一个硬件锁定一个区段，以防止对任何区段进行编程或擦除的硬件保护。

区段可以锁定在系统或通过编程设备中，临时区段撤消功能允许在先前锁定的扇区中的代码更改。

●解锁旁路编程命令-当发出多个程序的命令序列时，降低了整个编程的时间。

●顶部或底部的引导块配置可用●嵌入式算法- 嵌入式擦除算法自动进行预先编程和擦除整个芯片或指定部门的任何组合- 嵌入式程序算法自动在指定的地址信息进行数据的写入和验证。

●保证每个区段最低100万次的写周期。

●封装选项- 48球FBGA- 48引脚TSOP- 44引脚SO●符合JEDEC标准的兼容性- 管脚和软件兼容的单电源闪存- 高级无心写保护●数据＃轮询和触发位- 提供了一个软件的检测方法●就绪/忙＃引脚（RY/ BY＃）- 提供硬件检测方法编程或擦除周期完成●擦除暂停/擦除恢复-暂停擦除操作来读取数据，或将数据编程到一个不被擦除的区段，然后恢复擦除操作。

● 硬件复位引脚（RESET ＃）- 器件复位到读阵列数据的硬件方法一般说明AM29LV400B 是4兆，3.0伏闪烁存储器，大小为524,288字节或262,144字节，提供的设备是在48球FBGA ，44引脚SO 和48引脚TSOP 封装。

am29LV160B芯片简介(共48张)

3.4 复位(fùwèi)
系统复位后,器件回到读数据模式下,复位可以用硬件和软件两种方法实现,软件实现方法如前面表格中所示,在后面指令中还要介绍,硬件实现通过/RESET引脚实现.
当把器件的/RESET引脚置于低电平时,器件会立即终止所有的操作,所有的数据输出成为高阻态,而且忽略此期间内所有的读写操作请求.与备用模式类似的, 当/RESET引脚置于VSS±0.3V时,器件电流被拉至 CMOS备用电流,而当/RESET引脚置于VIL时,也将被拉至备用电流,但是要比上述情况下大.
第13页，共48页。
3.5 扇区保护 /解除保护 (bǎohù)
(bǎohù)
出厂时,所有扇区都是未加保护的.保护的建立和解除可以用两种方法实现.基本方法就是将/RESET引脚置于VID,这可以在系统或用编程器件实现. 具体的操作方法见操作流程图3-1.图3-2显示的是其时序图.
另外一种方法必须用编程器件实现,需要将A9和/OE两引脚均置于VID.
第11页，共48页。
3.3 自动睡眠模式 (shuìmián)
自动睡眠模式最小化了Flash器件的功耗,当地址稳定时间超过tACC+30ns (tACC为器件的典型访问时间,概述中已经介绍过)时,器件自动进入该模式,在该模式下,输出数据被锁存在外总线上,可以被系统使用.
第12页，共48页。
从自由选择模式下退出或者当器件处于 DQ5=‘1’的状态下时,必须使用复位命令使器件返回读数据状态.
图4-3为其时序图.
第25页，共48页。
图4-3
第26页，共48页。
4.3 自动选择命令序列 (mìng lìng)
该命令序列是使器件进入自动选择工作模式的软件方法.该序列应该跟在解锁(解除扇区保护)操作之后.进入自动选择模式后,系统就可以依据不同地址获取想要的信息了.自动选择模式在前面已经介绍过.

Am29LV160

Am29LV160B16 兆(2 M × 8位/ 1 M × 16位）CMOS 3.0 伏安只引导扇区闪存单电源操作—全电压范围：2.7 到3.6 伏—调节电压范围：3.0 到3.6 伏阅读和写入操作，并同兼容性高性能 3.3 伏微处理器s关于0.35 µm工艺制造s支持常见的闪存接口(CFI) s高性能—全电压范围：快速存取时间为纳秒90—调节电压范围：访问S作为时代的80 纳秒快速超低功耗（在5 兆赫典型值）— 200 nA的自动休眠模式电流— 200 nA的待机模式电流— 9 毫安电流阅读— 20 硕士班/擦除当前灵活的部门架构— 16 一个字节，2 8 字节，1 32 字节，和31 64 Kbyte的部门（字节的模式）— 8 kword的一，二4 kword的，一16 kword的，和31 32 kword的部门（字模式）—支持全芯片擦除—扇区保护功能：A 锁定一个部门防止任何程序或擦除该部门行业可以被锁定在系统或通过编程设备临时机构撤消特色操作硬件方法允许在代码改变先前锁定部门s解锁绕道程序命令—降低总体规划时多个程序发出的命令序列，顶部或底部启动块配置提供嵌入式算法—嵌入擦除算法自动预先把和擦除整个芯片或任何指定的部门组合—嵌入式程序算法自动写入和验证在指定地址资料程序中s每写周期的最低1,000,000部门保证s包选项— 48球FBGA— 48针TSOP— 44针SOsCFI （通用闪存接口）兼容—提供设备的具体资料系统，使主机软件轻松重新配置为不同的闪存器件S与JEDEC 标准—引脚和软件兼容性与单电源闪存—高级无意中写保护相适应的活动数据＃投票和切换位—提供一个检测编程或擦除操作完成软件方法的探讨就绪/忙＃引脚(RY/BY#)—提供一个检测编程或擦除周期结束（不44引脚SO)s擦除挂起硬件方法/擦除简历—挂起一擦除操作读取数据，数据或程序，一个不被抹去部门，然后恢复擦除操作s硬件复位引脚(RESET#)—硬件的方法来重置设备概述描述介绍Am29LV160B是16 兆位，3.0 伏只闪存2,097,152 字节或字1,048,576 组织。

MX29LV800BBTC-90中文资料

MX29LV800BT/BB8M-BIT [1Mx8/512K x16] CMOS SINGLE VOLTAGE3V ONLY FLASH MEMORYand erase operation completion.•Ready/Busy# pin (RY/BY#)- Provides a hardware method of detecting program or erase operation completion.•Sector protection- Hardware method to disable any combination of sectors from program or erase operations- Temporary sector unprotected allows code changes in previously locked sectors.•CFI (Common Flash Interface) compliant- Flash device parameters stored on the device and provide the host system to access•100,000 minimum erase/program cycles•Latch-up protected to 100mA from -1V to VCC+1V •Boot Sector Architecture - T = Top Boot Sector - B = Bottom Boot Sector •Package type:- 44-pin SOP - 48-pin TSOP - 48-pin CSP•Compatibility with JEDEC standard- Pinout and software compatible with single-power supply Flash•10 years data retentionFEATURES•Extended single - supply voltage range 2.7V to 3.6V •1,048,576 x 8/524,288 x 16 switchable •Single power supply operation- 3.0V only operation for read, erase and program operation•Fast access time: 70/90ns •Low power consumption- 20mA maximum active current - 0.2uA typical standby current •Command register architecture- Byte/word Programming (9us/11us typical)- Sector Erase (Sector structure 16K-Bytex1,8K-Bytex2, 32K-Bytex1, and 64K-Byte x15)•Fully compatible with MX29LV800T/B device •Auto Erase (chip & sector) and Auto Program- Automatically erase any combination of sectors with Erase Suspend capability.- Automatically program and verify data at specified address•Erase suspend/Erase Resume- Suspends sector erase operation to read data from,or program data to, any sector that is not being erased,then resumes the erase.•Status Reply- Data# polling & Toggle bit for detection of programGENERAL DESCRIPTIONThe MX29L V800BT/BB is a 8-mega bit Flash memory organized as 1M bytes of 8 bits or 512K words of 16bits. MXIC's Flash memories offer the most cost-effec-tive and reliable read/write non-volatile random access memory. The MX29L V800BT/BB is packaged in 44-pin SOP , 48-pin TSOP , and 48-ball CSP . It is designed to be reprogrammed and erased in system or in standard EPROM programmers.The standard MX29LV800BT/BB offers access time as fast as 70ns, allowing operation of high-speed micropro-cessors without wait states. To eliminate bus conten-tion, the MX29LV800BT/BB has separate chip enable (CE#) and output enable (OE#) controls.MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29LV800BT/BB uses a command register to man-age this functionality. The command register allows for100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility.MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cy-cling. The MX29LV800BT/BB uses a 2.7V~3.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms.The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up pro-tection is proved for stresses up to 100 milliamperes on address and data pin from -1V to VCC + 1V.MX29LV800BT/BBPIN CONFIGURATIONSPIN DESCRIPTIONSYMBOL PIN NAME A0~A18Address Input Q0~Q14Data Input/OutputQ15/A-1Q15(Word mode)/LSB addr(Byte mode)CE#Chip Enable Input WE#Write Enable Input BYTE#Word/Byte Selection input RESET#Hardware Reset Pin OE#Output Enable Input RY/BY#Ready/Busy OutputVCC Power Supply Pin (2.7V~3.6V)GNDGround Pin48 TSOP (Standard Type) (12mm x 20mm)48-Ball CSP Ball Pitch = 0.8 mm, Top View, Balls Facing Down44 SOP(500 mil)A B C D E F GH6A13A12A14A15A16BYTE#Q15/A-1GND 5A9A8A10A11Q7Q14Q13Q64 WE#RESET#NCNC Q5Q12Vcc Q43RY/BY#NC A18NC Q2Q10Q11Q32A7A17A6A5Q0Q8Q9Q11A3A4A2A1A0CE#OE#GND234567891011121314151617181920212244434241403938373635343332313029282726252423RY/BY#A18A17A7A6A5A4A3A2A1A0CE#GND OE#Q0Q8Q1Q9Q2Q10Q3Q11RESET#WE#A8A9A10A11A12A13A14A15A16BYTE#GND Q15/A-1Q7Q14Q6Q13Q5Q12Q4VCCM X 29L V 800B T /B BA15A14A13A12A11A10A9A8NC NC WE#RESET#NC NC RY/BY#A18A17A7A6A5A4A3A2A1123456789101112131415161718192021222324A16BYTE#GND Q15/A-1Q7Q14Q6Q13Q5Q12Q4VCC Q11Q3Q10Q2Q9Q1Q8Q0OE#GND CE#A0484746454443424140393837363534333231302928272625MX29LV800BT/BBMX29LV800BT/BBBLOCK STRUCTURETABLE 1: MX29LV800BT SECTOR ARCHITECTURENote: Byte mode:address range A18:A-1, word mode:address range A18:A0.Sector Sector SizeAddress range Sector AddressByte Mode Word ModeByte Mode (x8)Word Mode (x16)A18A17A16A15A14A13A12SA064Kbytes 32Kwords 00000h-0FFFFh 00000h-07FFFh 0000X X X SA164Kbytes 32Kwords 10000h-1FFFFh 08000h-0FFFFh 0001X X X SA264Kbytes 32Kwords 20000h-2FFFFh 10000h-17FFFh 0010X X X SA364Kbytes 32Kwords 30000h-3FFFFh 18000h-1FFFFh 0011X X X SA464Kbytes 32Kwords 40000h-4FFFFh 20000h-27FFFh 0100X X X SA564Kbytes 32Kwords 50000h-5FFFFh 28000h-2FFFFh 0101X X X SA664Kbytes 32Kwords 60000h-6FFFFh 30000h-37FFFh 0110X X X SA764Kbytes 32Kwords 70000h-7FFFFh 38000h-3FFFFh 0111X X X SA864Kbytes 32Kwords 80000h-8FFFFh 40000h-47FFFh 1000X X X SA964Kbytes 32Kwords 90000h-9FFFFh 48000h-4FFFFh 1001X X X SA1064Kbytes 32Kwords A0000h-AFFFFh 50000h-57FFFh 1010X X X SA1164Kbytes 32Kwords B0000h-BFFFFh 58000h-5FFFFh 1011X X X SA1264Kbytes 32Kwords C0000h-CFFFFh 60000h-67FFFh 1100X X X SA1364Kbytes 32Kwords D0000h-DFFFFh 68000h-6FFFFh 1101X X X SA1464Kbytes 32Kwords E0000h-EFFFFh 70000h-77FFFh 1110X X X SA1532Kbytes 16Kwords F0000h-F7FFFh 78000h-7BFFFh 11110X X SA168Kbytes 4Kwords F8000h-F9FFFh 7C000h-7CFFFh 1111100SA178Kbytes 4Kwords FA000h-FBFFFh 7D000h-7DFFFh 1111101SA1816Kbytes8KwordsFC000h-FFFFFh7E000h-7FFFFh111111XMX29LV800BT/BBTABLE 2: MX29LV800BB SECTOR ARCHITECTURESector Sector Size Address range Sector Address Byte Mode Word Mode Byte Mode (x8)Word Mode (x16)A18A17A16A15A14A13A12 SA016Kbytes8Kwords00000h-03FFFh00000h-01FFFh000000X SA18Kbytes4Kwords04000h-05FFFh02000h-02FFFh0000010 SA28Kbytes4Kwords06000h-07FFFh03000h-03FFFh0000011 SA332Kbytes16Kwords08000h-0FFFFh04000h-07FFFh00001X X SA464Kbytes32Kwords10000h-1FFFFh08000h-0FFFFh0001X X X SA564Kbytes32Kwords20000h-2FFFFh10000h-17FFFh0010X X X SA664Kbytes32Kwords30000h-3FFFFh18000h-1FFFFh0011X X X SA764Kbytes32Kwords40000h-4FFFFh20000h-27FFFh0100X X X SA864Kbytes32Kwords50000h-5FFFFh28000h-2FFFFh0101X X X SA964Kbytes32Kwords60000h-6FFFFh30000h-37FFFh0110X X X SA1064Kbytes32Kwords70000h-7FFFFh38000h-3FFFFh0111X X X SA1164Kbytes32Kwords80000h-8FFFFh40000h-47FFFh1000X X X SA1264Kbytes32Kwords90000h-9FFFFh48000h-4FFFFh1001X X X SA1364Kbytes32Kwords A0000h-AFFFFh50000h-57FFFh1010X X X SA1464Kbytes32Kwords B0000h-BFFFFh58000h-5FFFFh1011X X X SA1564Kbytes32Kwords C0000h-CFFFFh60000h-67FFFh1100X X X SA1664Kbytes32Kwords D0000h-DFFFFh68000h-6FFFFh1101X X X SA1764Kbytes32Kwords E0000h-EFFFFh70000h-77FFFh1110X X X SA1864Kbytes32Kwords F0000h-FFFFFh78000h-7FFFFh1111X X XNote: Byte mode:address range A18:A-1, word mode:address range A18:A0.MX29LV800BT/BBBLOCK DIAGRAMCONTROL INPUT LOGICPROGRAM/ERASE HIGH VOLTAGEWRITE STATE MACHINE (WSM)STATEREGISTERMX29LV800BT/BBFLASH ARRAYX-DECODERADDRESS LATCHAND BUFFERY -PASS GATEY -DECODERARRAY SOURCE HVCOMMAND DATADECODERCOMMAND DATA LATCHI/O BUFFERPGM DATA HVPROGRAM DATA LATCHSENSE AMPLIFIERQ0-Q15/A-1A0-A18CE#OE#WE#RESET#MX29LV800BT/BBAUTOMATIC PROGRAMMINGThe MX29L V800BT/BB is byte programmable using the Automatic Programming algorithm. The Automatic Pro-gramming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming time at room temperature of the MX29LV800BT/BB is less than 10 seconds.AUTOMATIC PROGRAMMING ALGORITHM MXIC's Automatic Programming algorithm requires the user to only write program set-up commands (including 2 unlock write cycle and A0H) and a program command (program data and address). The device automatically times the programming pulse width, provides the pro-gram verification, and counts the number of sequences. The device provides an unlock bypass mode with faster programming. Only two write cycles are needed to pro-gram a word or byte, instead of four. A status bit similar to DA TA# polling and a status bit toggling between con-secutive read cycles, provide feedback to the user as to the status of the programming operation. Refer to write operation status, table 8, for more information on these status bits.AUTOMATIC CHIP ERASEThe entire chip is bulk erased using 10 ms erase pulses according to MXIC's Automatic Chip Erase algorithm. T ypical erasure at room temperature is accomplished in less than 25 second. The Automatic Erase algorithm automatically programs the entire array prior to electri-cal erase. The timing and verification of electrical erase are controlled internally within the device. AUTOMATIC SECTOR ERASEThe MX29LV800BT/BB is sector(s) erasable using MXIC's Auto Sector Erase algorithm. The Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase. The timing and verification of electrical erase are controlled inter-nally within the device. An erase operation can erase one sector, multiple sectors, or the entire device.AUTOMATIC ERASE ALGORITHMMXIC's Automatic Erase algorithm requires the user to write commands to the command register using stan-dard microprocessor write timings. The device will auto-matically pre-program and verify the entire array. Then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecu-tive read cycles provides feedback to the user as to the status of the erasing operation.Register contents serve as inputs to an internal state-machine which controls the erase and programming cir-cuitry. During write cycles, the command register inter-nally latches address and data needed for the program-ming and erase operations. During a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of WE# or CE#, whichever happens first.MXIC's Flash technology combines years of EPROM experience to produce the highest levels of quality, reli-ability, and cost effectiveness. The MX29LV800BT/BB electrically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes are programmed by us-ing the EPROM programming mechanism of hot elec-tron injection.During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the device stays in read mode. After the state machine has completed its task, it will allow the command regis-ter to respond to its full command set. AUTOMATIC SELECTThe auto select mode provides manufacturer and de-vice identification, and sector protection verification, through identifier codes output on Q7~Q0. This mode is mainly adapted for programming equipment on the de-vice to be programmed with its programming algorithm. When programming by high voltage method, automatic select mode requires VID (11.5V to 12.5V) on address pin A9 and other address pin A6, A1 and A0 as referring to Table 3. In addition, to access the automatic select codes in-system, the host can issue the automatic se-MX29LV800BT/BBlect command through the command register withoutrequiring VID, as shown in table 5.T o verify whether or not sector being protected, the sec-tor address must appear on the appropriate highest or-der address bit (see Table 1 and Table 2). The rest ofaddress bits, as shown in table 3, are don't care. Onceall necessary bits have been set as required, the pro-gramming equipment may read the corresponding iden-tifier code on Q7~Q0.TABLE 3. MX29LV800BT/BB AUTO SELECT MODE OPERATIONA18A11A9A8A6A5A1A0Description Mode CE#OE#WE#| | | |Q15~Q0A12A10A7A2Manufacturer Code L L H X X VID X L X L L C2H Read Device ID Word L L H X X VID X L X L H22DAH Silicon(T op Boot Block)Byte L L H X X VID X L X L H XXDAHID Device ID Word L L H X X VID X L X L H225BH (Bottom Boot Block)Byte L L H X X VID X L X L H XX5BHXX01H Sector Protection L L H SA X VID X L X H L(protected) Verification XX00H(unprotected) NOTE:SA=Sector Address, X=Don't Care, L=Logic Low, H=Logic HighMX29LV800BT/BBQUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE ( for MX29L V800BT/ BB)MX29LV800BT/BB is capable of operating in the CFI mode. This mode all the host system to determine the manufacturer of the device such as operating param-eters and configuration. Two commands are required in CFI mode. Query command of CFI mode is placed first, then the Reset command exits CFI mode. These are described in T able 6.The single cycle Query command is valid only when the device is in the Read mode, including Erase Suspend, Standby mode, and Read ID mode; however, it is ig-nored otherwise.The Reset command exits from the CFI mode to the Read mode, or Erase Suspend mode, or read ID mode. The command is valid only when the device is in the CFI mode.TABLE 4-1. CFI mode: Identification Data Values(All values in these tables are in hexadecimal)Description Address Address Data(Byte Mode)(Word Mode) Query-unique ASCII string "QRY"201000512211005224120059 Primary vendor command set and control interface ID code2613000228140000 Address for primary algorithm extended query table2A1500402C160000 Alternate vendor command set and control interface ID code (none)2E17000030180000 Address for secondary algorithm extended query table (none)32190000341A0000 TABLE 4-2. CFI Mode: System Interface Data Values(All values in these tables are in hexadecimal)Description Address Address Data(Byte Mode)(Word Mode) VCC supply, minimum (2.7V)361B0027 VCC supply, maximum (3.6V)381C0036 VPP supply, minimum (none)3A1D0000 VPP supply, maximum (none)3C1E0000 Typical timeout for single word/byte write (2N us)3E1F0004 Typical timeout for Minimum size buffer write (2N us)40200000 Typical timeout for individual block erase (2N ms)4221000A Typical timeout for full chip erase (2N ms)44220000 Maximum timeout for single word/byte write times (2N X Typ)46230005 Maximum timeout for buffer write times (2N X Typ)48240000 Maximum timeout for individual block erase times (2N X Typ)4A250004 Maximum timeout for full chip erase times (not supported)4C260000MX29LV800BT/BB TABLE 4-3. CFI Mode: Device Geometry Data Values(All values in these tables are in hexadecimal)Description Address Address Data(Byte Mode)(Word Mode) Device size (2N bytes)4E270014 Flash device interface code (refer to the CFI publication 100)5028000252290000 Maximum number of bytes in multi-byte write (not supported)542A0000562B0000 Number of erase block regions582C0004 Erase block region 1 information (refer to the CFI publication 100)5A2D00005C2E00005E2F004060300000 Erase block region 2 information62310001643200006633002068340000 Erase block region 3 information6A3500006C3600006E37008070380000 Erase block region 4 information7239000E743A0000763B0000783C0001 TABLE 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values(All values in these tables are in hexadecimal)Description Address Address Data(Byte Mode)(Word Mode) Query-unique ASCII string "PRI"804000508241005284420049 Major version number, ASCII86430031 Minor version number, ASCII88440030 Address sensitive unlock (0=required, 1= not required)8A450000 Erase suspend (2= to read and write)8C460002 Sector protect (N= # of sectors/group)8E470001 Temporary sector unprotected (1=supported)90480001 Sector protect/unprotected scheme92490004 Simultaneous R/W operation (0=not supported)944A0000 Burst mode type (0=not supported)964B0000 Page mode type (0=not supported)984C0000MX29LV800BT/BBTABLE 5. MX29LV800BT/BB COMMAND DEFINITIONSFirst Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus Command Bus Cycle Cycle Cycle Cycle Cycle CycleCycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Reset 1XXXH F0HRead1RA RDRead Silicon ID Word4555H AAH2AAH55H555H90H ADI DDIByte4AAAH AAH555H55H AAAH90H ADI DDISector Protect Word4555H AAH2AAH55H555H90H(SA)XX00HVerify x02H XX01HByte4AAAH AAH555H55H AAAH90H(SA)00Hx04H01HProgram Word4555H AAH2AAH55H555H A0H PA PDByte4AAAH AAH555H55H AAAH A0H PA PDChip Erase Word6555H AAH2AAH55H555H80H555H AAH2AAH55H555H10H Byte6AAAH AAH555H55H AAAH80H AAAH AAH555H55H AAAH10H Sector Erase Word6555H AAH2AAH55H555H80H555H AAH2AAH55H SA30H Byte6AAAH AAH555H55H AAAH80H AAAH AAH555H55H SA30H Sector Erase Suspend1XXXH B0HSector Erase Resume1XXXH30HCFI Query Word155H98Byte1AAH98Note:1.ADI = Address of Device identifier; A1=0, A0 = 0 for manufacturer code,A1=0, A0 = 1 for device code. A2-A18=do not care.(Refer to table 3)DDI = Data of Device identifier : C2H for manufacture code, 22DA/DA(T op), and 225B/5B(Bottom) for device code.X = X can be VIL or VIHRA=Address of memory location to be read.RD=Data to be read at location RA.2.P A = Address of memory location to be programmed.PD = Data to be programmed at location P A.SA = Address of the sector.3.The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or555H to Address A10~A-1 in byte mode.Address bit A11~A18=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA).Write Sequence may be initiated with A11~A18 in either state.4.For Sector Protect Verify operation: If read out data is 01H, it means the sector has been protected. If read out data is 00H,it means the sector is still not being protected.5.Any number of CFI data read cycle are permitted.MX29LV800BT/BBTABLE 6. MX29LV800BT/BB BUS OPERATIONNOTES:1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to T able 5.2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V .3. Refer to T able 5 for valid Data-In during a write operation.4. X can be VIL or VIH.5. Code=00H/XX00H means unprotected.Code=01H/XX01H means protected.6.A18~A12=Sector address for sector protect.7.The sector protect and chip unprotected functions may also be implemented via programming equipment.sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress.COMMAND DEFINITIONSDevice operations are selected by writing specific ad-dress and data sequences into the command register.Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table 5 defines the valid register commandADDRESSQ8~Q15DESCRIPTION CE#OE#WE#RESET#A18A10A9A8A6A5A1A0Q0~Q7BYTE BYTE A12A11A7A2=VIH =VIL ReadLLHHAINDoutDoutQ8~Q14=High Z Q15=A-1Write L H L H AIN DIN(3)DIN ResetX X X L X High Z High Z High Z Temporary sector unlock X X X VID AIN DIN DIN High Z Output Disable L HH H X High Z High Z High Z Standby Vcc ±XX Vcc ± X High Z High Z High Z 0.3V 0.3V Sector Protect L H L VID SA X X X L X H L DIN X X Chip Unprotected L H L VID X X X X H X H L DIN X X Sector Protection VerifyLLHHSAXVIDXLXHLCODE(5)XXMX29LV800BT/BBREQUIREMENTS FOR READING ARRAY DATAT o read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH.The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid address on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. WRITE COMMANDS/COMMAND SEQUENCEST o program data to the device or erase sectors of memory , the system must drive WE# and CE# to VIL, and OE# to VIH.The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a byte, instead of four. The "byte Program Command Sequence" section has details on programming data to the device using both standard and Unlock Bypass command sequences.An erase operation can erase one sector, multiple sectors , or the entire device. T able indicates the address space that each sector occupies. A "sector address" consists of the address bits required to uniquely select a sector. The "Writing specific address and data commands or sequences into the command register initiates device operations. Table 1 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. Section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation.After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on Q7-Q0. Standard read cycle timings apply in this mode.Refer to the Autoselect Mode and Autoselect Command Sequence section for more information.ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification table and timing diagrams for write operations. STANDBY MODEWhen using both pins of CE# and RESET#, the device enter CMOS Standby with both pins held at Vcc ± 0.3V. If CE# and RESET# are held at VIH, but not within the range of VCC ±0.3V, the device will still be in the standby mode, but the standby current will be larger. During Auto Algorithm operation, Vcc active current (Icc2) is required even CE# = "H" until the operation is completed. The device can be read with standard access time (tCE) from either of these standby modes, before it is ready to read data.OUTPUT DISABLEWith the OE# input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins to be in a high impedance state.RESET# OPERATIONThe RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tri-states all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrityCurrent is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3V, the standby current will be greater.The RESET# pin may be tied to system reset circuitry.A system reset would that also reset the Flash memory, enabling the system to read the boot-up firmware fromMX29LV800BT/BBREAD/RESET COMMANDThe read or reset operation is initiated by writing the read/reset command sequence into the command reg-ister. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register contents are altered.If program-fail or erase-fail happen, the write of F0H will reset the device to abort the operation. A valid com-mand must then be written to place the device in the desired state.SILICON-ID READ COMMANDFlash memories are intended for use in applications where the local CPU alters memory contents. As such, manu-facturer and device codes must be accessible while the device resides in the target system. PROM program-mers typically access signature codes by raising A9 to a high voltage (VID). However, multiplexing high volt-age onto address lines is not generally desired system design practice.The MX29LV800BT/BB contains a Silicon-ID-Read op-eration to supple traditional PROM programming meth-odology. The operation is initiated by writing the read silicon ID command sequence into the command regis-ter. Following the command write, a read cycle with A1=VIL, A0=VIL retrieves the manufacturer code of C2H/ 00C2H. A read cycle with A1=VIL, A0=VIH returns the device code of DAH/22DAH for MX29L V800BT, 5BH/ 225BH for MX29LV800BB.SET-UP AUTOMATIC CHIP/SECTOR ERASE COMMANDSChip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command 80H. Two more "unlock" write cy-cles are then followed by the chip erase command 10H or sector erase command 30H.The Automatic Chip Erase does not require the device to be entirely pre-programmed prior to executing the Au-tomatic Chip Erase. Upon executing the Automatic Chip Erase, the device will automatically program and verify the entire memory for an all-zero data pattern. When the device is automatically verified to contain an all-zero pattern, a self-timed chip erase and verify begin. The erase and verify operations are completed when the data on Q7 is "1" at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations.When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required).If the Erase operation was unsuccessful, the data on Q5 is "1" (see Table 8), indicating the erase operation exceed internal timing limit.The automatic erase begins on the rising edge of the last WE# or CE# pulse, whichever happens first in the command sequence and terminates when the data on Q7 is "1" at which time the device returns to the Read mode, or the data on Q6 stops toggling for two consecu-tive read cycles at which time the device returns to the Read mode.the Flash memory.If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH.Refer to the AC Characteristics tables for RESET# parameters and to Figure 22 for the timing diagram.。

MBM29LV800 中文

灵活的扇区擦写机制
1. 单 16K、两个 8K 字节、单 32K 字节、十五个 64K 字节 2. 单扇区、多扇区、扇区块的擦写 3. 用户可定义单或多扇区的保护
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总体描述
MBM29LV800TA/BA 是一个 8M 位，3.0V 的 FLASH 存储器，可以形成 1M 8 位或 512K 16 位两种模式。MBM29LV800TA/BA 有 48－pin TOSP；44－pin SOP； 48－ball FBGA 三种封装。这种器件在系统中用 3.0V 进行编程擦写操作。擦写操作不必用 12.0V 和 5.0V 供电。器件同标准 EPROM 一样可以重复编程使用。
功能描述
读模式：
MBM29LV800TA/BA 要在输出引脚获得数据须满足两个控制条件同时满足。/CE 是能量使能，被用来决定此芯片是否被选择使用。/OE 在芯片被选择是表示可以读数据。
地址的读取时间与地址线上稳定输出有效的数据时间相吻合，芯片的使能信号/CE 比数据信号和数据信号提供的时间要长。输出使能信号在/OE 的下降沿后变化，使数据在输出引脚一直有效。（假设地址信号在 tACC-tOE 时间段已经稳定）当没有改变地址信号在通电后读数据，必须将输入硬件复位或使/OE 从高电平变到低电平。

MBM29LV160TE

s PRODUCT LINE UP
Part No. VCC = 3.3 V Ordering Part No. VCC = 3.0 V Max. Address Access Time (ns) Max. CE Access Time (ns) Max. OE Access Time (ns)
+0.3 V –0.3 V +0.6 V –0.3 V
MBM29LV160TE/160BE 70 — 70 70 30 — 90 90 90 35 — 12 120 120 50
MBM29LV160TE/BE-70/90/12
(Continued)
The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The MBM29LV160TE/BE is erased when shipped from the factory. The device features single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been comleted, the device internally resets to the read mode. The MBM29LV160TE/BE also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the address locations being programmed or erased. These locations need re-writing after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up firmware from the Flash memory. Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. The MBM29LV160TE/BE memory electrically erases all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection. * : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.

MX29LV160CBMI-90G资料

MX29LV160C T/B16M-BIT [2Mx8/1Mx16] CMOS SINGLE VOLTAGE3V ONLY FLASH MEMORY•Ready/Busy# pin (RY/BY#)- Provides a hardware method of detecting program or erase operation completion.•Sector protection- Hardware method to disable any combination of sectors from program or erase operations- Temporary sector unprotect allows code changes in previously locked sectors.•CFI (Common Flash Interface) compliant- Flash device parameters stored on the device and provide the host system to access•100,000 minimum erase/program cycles•Latch-up protected to 100mA from -1V to VCC+1V •Boot Sector Architecture - T = Top Boot Sector - B = Bottom Boot Sector•Low VCC write inhibit is equal to or less than 1.4V •Package type:- 44-pin SOP - 48-pin TSOP - 48-ball CSP- All Pb-free devices are RoHS Compliant •Compatibility with JEDEC standard- Pinout and software compatible with single-power supply Flash•10 years data retentionFEATURES•Extended single - supply voltage range 2.7V to 3.6V •2,097,152 x 8/1,048,576 x 16 switchable •Single power supply operation- 3.0V only operation for read, erase and program operation•Fully compatible with MX29LV160B device •Fast access time: 55R/70/90ns •Low power consumption- 30mA maximum active current - 0.2uA typical standby current •Command register architecture- Byte/word Programming (9us/11us typical)- Sector Erase (Sector structure 16K-Bytex1,8K-Bytex2, 32K-Bytex1, and 64K-Byte x31)•Auto Erase (chip & sector) and Auto Program- Automatically erase any combination of sectors with Erase Suspend capability.- Automatically program and verify data at specified address•Erase Suspend/Erase Resume- Suspends sector erase operation to read data from,or program data to, any sector that is not being erased,then resumes the erase.•Status Reply- Data# Polling & Toggle bit for detection of program and erase operation completion.GENERAL DESCRIPTIONThe MX29L V160C T/B is a 16-mega bit Flash memory organized as 2M bytes of 8 bits or 1M words of 16 bits.MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29LV160C T/B is packaged in 44-pin SOP , 48-pin TSOP and 48-ball CSP . It is designed to be reprogrammed and erased in system or in standard EPROM programmers.The standard MX29LV160C T/B offers access time as fast as 55ns, allowing operation of high-speed micropro-cessors without wait states. To eliminate bus conten-tion, the MX29LV160C T/B has separate chip enable (CE#) and output enable (OE#) controls.MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29LV160C T/B uses a command register to manage this functionality. The command register allows for 100%TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maxi-mum EPROM compatibility.MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cy-cling. The MX29LV160C T/B uses a 2.7V~3.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms.The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up pro-tection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.MX29LV160C T/BPIN CONFIGURATIONSPIN DESCRIPTIONSYMBOL PIN NAME A0~A19Address Input Q0~Q14Data Input/OutputQ15/A-1Q15(Word mode)/LSB addr(Byte mode)CE#Chip Enable Input WE#Write Enable Input BYTE#Word/Byte Selection input RESET#Hardware Reset Pin/Sector Protect UnlockOE#Output Enable Input RY/BY#Ready/Busy OutputVCC Power Supply Pin (2.7V~3.6V)GNDGround Pin48 TSOP (Standard Type) (12mm x 20mm)44 SOP(500 mil)A B C D E F GH6A13A12A14A15A16BYTE#Q15/A-1GND 5A9A8A10A11Q7Q14Q13Q64WE#RESET#NCA19Q5Q12VCC Q43RY/BY#NC A18NC Q2Q10Q11Q32A7A17A6A5Q0Q8Q9Q11A3A4A2A1A0CE#OE#GND48-Ball CSP 6mm x 8mm (Ball Pitch=0.8mm) Top View, Balls Facing Down234567891011121314151617181920212244434241403938373635343332313029282726252423RESET#A18A17A7A6A5A4A3A2A1A0CE#GND OE#Q0Q8Q1Q9Q2Q10Q3Q11WE#A19A8A9A10A11A12A13A14A15A16BYTE#GND Q15/A-1Q7Q14Q6Q13Q5Q12Q4VCCM X 29L V 160C T /BA15A14A13A12A11A10A9A8A19NC WE#RESET#NC NC RY/BY#A18A17A7A6A5A4A3A2A1123456789101112131415161718192021222324A16BYTE#GND Q15/A-1Q7Q14Q6Q13Q5Q12Q4VCC Q11Q3Q10Q2Q9Q1Q8Q0OE#GND CE#A0484746454443424140393837363534333231302928272625MX29LV160C T/BMX29LV160C T/BBLOCK STRUCTURETable 1: MX29LV160CT SECTOR ARCHITECTURESector Sector Size Address range Sector Address Byte Mode Word Mode Byte Mode(x8) Word Mode(x16)A19A18A17A16A15A14A13A12 SA064Kbytes32Kwords000000-00FFFF00000-07FFF00000X X X SA164Kbytes32Kwords010000-01FFFF08000-0FFFF00001X X X SA264Kbytes32Kwords020000-02FFFF10000-17FFF00010X X X SA364Kbytes32Kwords030000-03FFFF18000-1FFFF00011X X X SA464Kbytes32Kwords040000-04FFFF20000-27FFF00100X X X SA564Kbytes32Kwords050000-05FFFF28000-2FFFF00101X X X SA664Kbytes32Kwords060000-06FFFF30000-37FFF00110X X X SA764Kbytes32Kwords070000-07FFFF38000-3FFFF00111X X X SA864Kbytes32Kwords080000-08FFFF40000-47FFF01000X X X SA964Kbytes32Kwords090000-09FFFF48000-4FFFF01001X X X SA1064Kbytes32Kwords0A0000-0AFFFF50000-57FFF01010X X X SA1164Kbytes32Kwords0B0000-0BFFFF58000-5FFFF01011X X X SA1264Kbytes32Kwords0C0000-0CFFFF60000-67FFF01100X X X SA1364Kbytes32Kwords0D0000-0DFFFF68000-6FFFF01101X X X SA1464Kbytes32Kwords0E0000-0EFFFF70000-77FFF01110X X X SA1564Kbytes32Kwords0F0000-0FFFFF78000-7FFFF01111X X X SA1664Kbytes32Kwords100000-10FFFF80000-87FFF10000X X X SA1764Kbytes32Kwords110000-11FFFF88000-8FFFF10001X X X SA1864Kbytes32Kwords120000-12FFFF90000-97FFF10010X X X SA1964Kbytes32Kwords130000-13FFFF98000-9FFFF10011X X X SA2064Kbytes32Kwords140000-14FFFF A0000-A7FFF10100X X X SA2164Kbytes32Kwords150000-15FFFF A8000-AFFFF10101X X X SA2264Kbytes32Kwords160000-16FFFF B0000-B7FFF10110X X X SA2364Kbytes32Kwords170000-17FFFF B8000-BFFFF10111X X X SA2464Kbytes32Kwords180000-18FFFF C0000-C7FFF11000X X X SA2564Kbytes32Kwords190000-19FFFF C8000-CFFFF11001X X X SA2664Kbytes32Kwords1A0000-1AFFFF D0000-D7FFF11010X X X SA2764Kbytes32Kwords1B0000-1BFFFF D8000-DFFFF11011X X X SA2864Kbytes32Kwords1C0000-1CFFFF E0000-E7FFF11100X X X SA2964Kbytes32Kwords1D0000-1DFFFF E8000-EFFFF11101X X X SA3064Kbytes32Kwords1E0000-1EFFFF F0000-F7FFF11110X X X SA3132Kbytes16Kwords1F0000-1F7FFF F8000-FBFFF111110X X SA328Kbytes4Kwords1F8000-1F9FFF FC000-FCFFF11111100 SA338Kbytes4Kwords1FA000-1FBFFF FD000-FDFFF11111101 SA3416Kbytes8Kwords1FC000-1FFFFF FE000-FFFFF1111111XNote: Byte mode: address range A19:A-1, word mode:address range A19:A0.MX29LV160C T/BTable 2: MX29LV160CB SECTOR ARCHITECTURESector Sector Size Address range Sector Address Byte Mode Word Mode Byte Mode (x8)Word Mode (x16)A19A18A17A16A15A14A13A12 SA016Kbytes8Kwords000000-003FFF00000-01FFF0000000X SA18Kbytes4Kwords004000-005FFF02000-02FFF00000010 SA28Kbytes4Kwords006000-007FFF03000-03FFF00000011 SA332Kbytes16Kwords008000-00FFFF04000-07FFF000001X X SA464Kbytes32Kwords010000-01FFFF08000-0FFFF00001X X X SA564Kbytes32Kwords020000-02FFFF10000-17FFF00010X X X SA664Kbytes32Kwords030000-03FFFF18000-1FFFF00011X X X SA764Kbytes32Kwords040000-04FFFF20000-27FFF00100X X X SA864Kbytes32Kwords050000-05FFFF28000-2FFFF00101X X X SA964Kbytes32Kwords060000-06FFFF30000-37FFF00110X X X SA1064Kbytes32Kwords070000-07FFFF38000-3FFFF00111X X X SA1164Kbytes32Kwords080000-08FFFF40000-47FFF01000X X X SA1264Kbytes32Kwords090000-09FFFF48000-4FFFF01001X X X SA1364Kbytes32Kwords0A0000-0AFFFF50000-57FFF01010X X X SA1464Kbytes32Kwords0B0000-0BFFFF58000-5FFFF01011X X X SA1564Kbytes32Kwords0C0000-0CFFFF60000-67FFF01100X X X SA1664Kbytes32Kwords0D0000-0DFFFF68000-6FFFF01101X X X SA1764Kbytes32Kwords0E0000-0EFFFF70000-77FFF01110X X X SA1864Kbytes32Kwords0F0000-0FFFFF78000-7FFFF01111X X X SA1964Kbytes32Kwords100000-10FFFF80000-87FFF10000X X X SA2064Kbytes32Kwords110000-11FFFF88000-8FFFF10001X X X SA2164Kbytes32Kwords120000-12FFFF90000-97FFF10010X X X SA2264Kbytes32Kwords130000-13FFFF98000-9FFFF10011X X X SA2364Kbytes32Kwords140000-14FFFF A0000-A7FFF10100X X X SA2464Kbytes32Kwords150000-15FFFF A8000-AFFFF10101X X X SA2564Kbytes32Kwords160000-16FFFF B0000-B7FFF10110X X X SA2664Kbytes32Kwords170000-17FFFF B8000-BFFFF10111X X X SA2764Kbytes32Kwords180000-18FFFF C0000-C7FFF11000X X X SA2864Kbytes32Kwords190000-19FFFF C8000-CFFFF11001X X X SA2964Kbytes32Kwords1A0000-1AFFFF D0000-D7FFF11010X X X SA3064Kbytes32Kwords1B0000-1BFFFF D8000-DFFFF11011X X X SA3164Kbytes32Kwords1C0000-1CFFFF E0000-E7FFF11100X X X SA3264Kbytes32Kwords1D0000-1DFFFF E8000-EFFFF11101X X X SA3364Kbytes32Kwords1E0000-1EFFFF F0000-FFFFF11110X X X SA3464Kbytes32Kwords1F0000-1FFFFF F8000-FFFFF11111X X XNote: Byte mode:address range A19:A-1, word mode:address range A19:A0.MX29LV160C T/BBLOCK DIAGRAMCONTROL INPUT LOGICPROGRAM/ERASE HIGH VOLTAGEWRITE STATE MACHINE (WSM)STATE REGISTERFLASH ARRAYX-DECODERADDRESS LATCHAND BUFFERY -PASS GATEY -DECODERARRAY SOURCE HVCOMMAND DATADECODERCOMMAND DATA LATCHI/O BUFFERPGM DATA HVPROGRAM DATA LATCHSENSE AMPLIFIERQ0-Q15/A-1A0-A19CE#OE#WE#RESET#MX29LV160C T/BAUTOMATIC PROGRAMMINGThe MX29L V160C T/B is byte/word programmable using the Automatic Programming algorithm. The Automatic Programming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming time at room temperature of the MX29LV160C T/B is less than 18 sec (byte)/12 sec (word).AUTOMATIC PROGRAMMING ALGORITHMMXIC's Automatic Programming algorithm requires the user to only write program set-up commands (including 2 unlock write cycle and A0H) and a program command (program data and address). The device automatically times the programming pulse width, provides the pro-gram verification, and counts the number of sequences.A status bit similar to Data# Polling and a status bit toggling between consecutive read cycles, provide feed-back to the user as to the status of the programming operation. Refer to write operation status, table 7, for more information on these status bits.AUTOMATIC CHIP ERASEThe entire chip is bulk erased using 10 ms erase pulses according to MXIC's Automatic Chip Erase algorithm. T ypical erasure at room temperature is accomplished in less than 25 second. The Automatic Erase algorithm automatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device.AUTOMATIC SECTOR ERASEThe MX29L V160C T/B is sector(s) erasable using MXIC's Auto Sector Erase algorithm. The Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase. The timing and verifi-cation of electrical erase are controlled internally within the device. An erase operation can erase one sector, multiple sectors, or the entire device.AUTOMATIC ERASE ALGORITHMMXIC's Automatic Erase algorithm requires the user to write commands to the command register using stan-dard microprocessor write timings. The device will auto-matically pre-program and verify the entire array. Then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecutive read cycles provides feedback to the user as to the sta-tus of the erasing operation.Register contents serve as inputs to an internal state-machine which controls the erase and programming cir-cuitry. During write cycles, the command register inter-nally latches address and data needed for the program-ming and erase operations. During a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of WE# or CE#, whichever happens first.MXIC's Flash technology combines years of EPROM experience to produce the highest levels of quality, reli-ability, and cost effectiveness. The MX29LV160C T/B electrically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes are programmed by us-ing the EPROM programming mechanism of hot electron injection.During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the device stays in read mode. After the state machine has completed its task, it will allow the command regis-ter to respond to its full command set.AUTOMATIC SELECTThe automatic select mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on Q7~Q0. This mode is mainly adapted for programming equipment on the de-vice to be programmed with its programming algorithm. When programming by high voltage method, automatic select mode requires VID (11.5V to 12.5V) on address pin A9. Other address pin A6, A1 and A0 as referring to T able 3. In addition, to access the automatic select codes in-system, the host can issue the automatic select com-mand through the command register without requiring VID, as shown in table 5.To verify whether or not sector being protected, the sec-tor address must appear on the appropriate highest orderMX29LV160C T/BA19A11A9A8A6A5A1A0Description Mode CE#OE#WE#RESET# || | |Q15~Q0A12A10A7A2Read Silicon ID LLHHXXVID XL XLLC2HManufacture Code Device ID Word L L H H X X VID X L X L H 22C4H (Top Boot Block)Byte L L H H X X VID X L X L H XXC4H Device IDWordL L H H X X VID X L X L H 2249H (Bottom Boot Block)ByteL L H H X X VID X L X L H XX49H XX01HSector Protection LLHHSAXVIDXLXHL(protected)VerificationXX00H(unprotected)TABLE 3. MX29LV160C T/B AUTO SELECT MODE BUS OPERATION (A9=VID)NOTE: SA=Sector Address, X=Don't Care, L=Logic Low, H=Logic Highaddress bit (see T able 1 and T able 2). The rest of address bits, as shown in T able 3, are don't care. Once all neces-sary bits have been set as required, the programming equipment may read the corresponding identifier code on Q7~Q0.MX29LV160C T/BQUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODEMX29L V160C T/B is capable of operating in the CFI mode. This mode all the host system to determine the manu-facturer of the device such as operating parameters and configuration. T wo commands are required in CFI mode. Query command of CFI mode is placed first, then the Reset command exits CFI mode. These are described in T able 4.The single cycle Query command is valid only when the device is in the Read mode, including Erase Suspend, Standby mode, and Automatic Select mode; however, it is ignored otherwise.The Reset command exits from the CFI mode to the Read mode, or Erase Suspend mode, or Automatic Se-lect mode. The command is valid only when the device is in the CFI mode.Table 4-1. CFI mode: Identification Data Values(All values in these tables are in hexadecimal)Description Address Address Data(Byte Mode)(Word Mode) Query-unique ASCII string "QRY"201000512211005224120059 Primary vendor command set and control interface ID code2613000228140000 Address for primary algorithm extended query table2A1500402C160000 Alternate vendor command set and control interface ID code (none)2E17000030180000 Address for secondary algorithm extended query table (none)32190000341A0000 Table 4-2. CFI Mode: System Interface Data Values(All values in these tables are in hexadecimal)Description Address Address Data(Byte Mode)(Word Mode) VCC supply, minimum (2.7V)361B0027 VCC supply, maximum (3.6V)381C0036 VPP supply, minimum (none)3A1D0000 VPP supply, maximum (none)3C1E0000 Typical timeout for single word/byte write (2N us)3E1F0004 Typical timeout for Minimum size buffer write (2N us) (not supported)40200000 Typical timeout for individual sector erase (2N ms)4221000A Typical timeout for full chip erase (2N ms)44220000 Maximum timeout for single word/byte write times (2N X Typ)46230005 Maximum timeout for buffer write times (2N X Typ)48240000 Maximum timeout for individual sector erase times (2N X Typ)4A250004 Maximum timeout for full chip erase times (not supported)4C260000MX29LV160C T/B Table 4-3. CFI Mode: Device Geometry Data Values(All values in these tables are in hexadecimal)Description Address Address Data(Byte Mode)(Word Mode) Device size (2N bytes)4E270015 Flash device interface code (x8/x16 async.)5028000252290000 Maximum number of bytes in multi-byte write (not supported)542A0000562B0000 Number of erase sector regions582C0004 Erase sector region 1 information (refer to the CFI publication 100)5A2D00005C2E00005E2F004060300000 Erase sector region 2 information62310001643200006633002068340000 Erase sector region 3 information6A3500006C3600006E37008070380000 Erase sector region 4 information7239001E743A0000763B0000783C0001 Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values(All values in these tables are in hexadecimal)Description Address Address Data(Byte Mode)(Word Mode) Query-unique ASCII string "PRI"804000508241005284420049 Major version number, ASCII86430031 Minor version number, ASCII88440030 Address sensitive unlock (0=required, 1= not required)8A450000 Erase suspend (2= to read and write)8C460002 Sector protect (N= # of sectors/group)8E470001 Temporary sector unprotect (1=supported)90480001 Sector protect/chip unprotect scheme92490004 Simultaneous R/W operation (0=not supported)944A0000 Burst mode type (0=not supported)964B0000 Page mode type (0=not supported)984C0000MX29LV160C T/Bin the improper sequence will reset the device to the read mode. Table 5 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress.COMMAND DEFINITIONSDevice operations are selected by writing specific ad-dress and data sequences into the command register.Writing incorrect address and data values or writing them First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus CommandBusCycleCycleCycleCycleCycle CycleCycle AddrData Addr Data Addr Data Addr DataAddrData Addr DataReset 1XXXH F0H Read1RARDRead Silicon IDWord 4555H AAH 2AAH 55H 555H 90H ADI DDI Byte4AAAH AAH 555H 55H AAAH 90H ADI DDI Sector Protect Word4555H AAH 2AAH55H555H90H (SA)XX00H Verifyx02HXX01H Byte4AAAH AAH 555H55HAAAH90H (SA)00H x04H01H Program Word 4555H AAH 2AAH 55H 555H A0H PA PD Byte4AAAH AAH 555H 55H AAAH A0H PAPDChip Erase Word 6555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H Byte6AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H AAAH 10H Sector Erase Word 6555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H Byte6AAAH AAH 555H 55HAAAH80H AAAH AAH555H 55HSA30HSector Erase Suspend 1XXXH B0H Sector Erase Resume 1XXXH 30H CFI QueryWord 155H 98ByteAAHTABLE 5. MX29L V160C T/B COMMAND DEFINITIONSNote:1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacturer code,A1=0, A0 = 1 for device code. A2-A19=do not care. (Refer to table 3)DDI = Data of Device identifier : C2H for manufacture code, C4H/49H (x8) and 22C4H/2249H (x16) for device code. X = X can be VIL or VIHRA=Address of memory location to be read. RD=Data to be read at location RA.2.PA = Address of memory location to be programmed. PD = Data to be programmed at location PA. SA = Address of the sector to be erased.3.The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or 555H to Address A10~A-1 in byte mode.Address bit A11~A19=X=Don't care for all address commands except for Program Address (P A) and Sector Address (SA). Write Sequence may be initiated with A11~A19 in either state.4. For Sector Protect Verify operation: If read out data is 01H, it means the sector has been protected. If read out data is 00H,it means the sector is still not being protected.5. Any number of CFI data read cycles are permitted.MX29LV160C T/BTABLE 6. MX29L V160C T/B BUS OPERATIONADDRESS Q8~Q15 DESCRIPTION CE#OE#WE#RE- A19A11A9A8A6A5A1A0Q0~Q7BYTE BYTESET#A12A10A7A2=VIH=VIL Read L L H H AIN Dout Dout Q8~Q14=High ZQ15=A-1 Write L H L H AIN DIN(3)DINReset X X X L X High Z High Z High Z Temporary sector unlock X X X VID AIN DIN DIN High Z Output Disable L H H H X High Z High Z High Z Standby Vcc±X X Vcc±X High Z High Z High Z0.3V0.3VSector Protect L H L VID SA X X X L X H L DIN X XChip Unprotect L H L VID X X X X H X H L DIN X X Sector Protection Verify L L H H SA X VID X L X H L CODE(5)X XNOTES:1.Manufacturer and device codes may also be accessed via a command register write sequence. Refer to T able 4.2. VID is the high voltage, 11.5V to 12.5V.3.Refer to T able 5 for valid Data-In during a write operation.4.X can be VIL or VIH.5.Code=00H/XX00H means unprotected.Code=01H/XX01H means protected.6.A19~A12=Sector address for sector protect.7.The sector protect and chip unprotect functions may also be implemented via programming equipment.MX29LV160C T/BREQUIREMENTS FOR READING ARRAY DATAT o read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should re-main at VIH.The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory con-tent occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid address on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. WRITE COMMANDS/COMMAND SEQUENCESTo program data to the device or erase sectors of memory, the system must drive WE# and CE# to VIL, and OE# to VIH.An erase operation can erase one sector, multiple sec-tors, or the entire device. T able 1 and T able 2 indicate the address space that each sector occupies. A "sector ad-dress" consists of the address bits required to uniquely select a sector. The Writing specific address and data commands or sequences into the command register ini-tiates device operations. Table 5 defines the valid regis-ter command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. Section has de-tails on erasing a sector or the entire chip, or suspend-ing/resuming the erase operation.After the system writes the "read silicon-ID" and "sector protect verify" command sequence, the device enters the "read silicon-ID" and "sector protect verify" mode. The system can then read "read silicon-ID" and "sector protect verify" codes from the internal register (which is separate from the memory array) on Q7-Q0. Standard read cycle timings apply in this mode. Refer to the "read silicon-ID" and "sector protect verify" Mode and "read silicon-ID" and "sector protect verify" Command Se-quence section for more information.ICC2 in the DC Characteristics table represents the ac-tive current specification for the write mode. The "AC Characteristics" section contains timing specification table and timing diagrams for write operations. STANDBY MODEWhen using both pins of CE# and RESET#, the device enter CMOS Standby with both pins held at Vcc ± 0.3V. If CE# and RESET# are held at VIH, but not within the range of VCC ± 0.3V, the device will still be in the standby mode, but the standby current will be larger. During Auto Algorithm operation, Vcc active current (ICC2) is required even CE# = "H" until the operation is completed. The device can be read with standard access time (tCE) from either of these standby modes, before it is ready to read data.OUTPUT DISABLEWith the OE# input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins to be in a high impedance state.RESET# OPERATIONThe RESET# pin provides a hardware method of reset-ting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write com-mands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be re-initiated once the device is ready to accept another com-mand sequence, to ensure data integrity.Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3V, the standby current will be greater.The RESET# pin may be tied to system reset circuitry.A system reset would that also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.If RESET# is asserted during a program or erase opera-tion, the RY/BY# pin remains a "0" (busy) until the inter-MX29LV160C T/Bnal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset op-eration is complete. If RESET# is asserted when a pro-gram or erase operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# pa-rameters and to Figure 22 for the timing diagram.READ/RESET COMMANDThe read or reset operation is initiated by writing the read/ reset command sequence into the command register. Microprocessor read cycles retrieve array data. The de-vice remains enabled for reads until the command regis-ter contents are altered.If program-fail or erase-fail happen, the write of F0H will reset the device to abort the operation. A valid com-mand must then be written to place the device in the desired state.SILICON-ID READ COMMANDFlash memories are intended for use in applications where the local CPU alters memory contents. As such, manu-facturer and device codes must be accessible while the device resides in the target system. PROM program-mers typically access signature codes by raising A9 to a high voltage (VID). However, multiplexing high voltage onto address lines is not generally desired system de-sign practice.The MX29LV160C T/B contains a Silicon-ID-Read op-eration to supple traditional PROM programming meth-odology. The operation is initiated by writing the read silicon ID command sequence into the command regis-ter. Following the command write, a read cycle with A1=VIL, A0=VIL retrieves the manufacturer code of C2H/ 00C2H. A read cycle with A1=VIL, A0=VIH returns the device code of C4H/22C4H for MX29L V160CT, 49H/2249H for MX29L V160CB.The system must write the reset command to exit the "Silicon-ID Read Command" code.AUTOMATIC CHIP ERASE COMMANDSChip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command 80H. T wo more "unlock" write cycles are then followed by the chip erase command 10H. The device does not require the system to entirely pre-program prior to executing the Automatic Chip Erase. Upon executing the Automatic Chip Erase, the device will automatically program and verify the entire memory for an all-zero data pattern. When the device is auto-matically verified to contain an all-zero pattern, a self-timed chip erase and verify begin. The erase and verify operations are completed when the data on Q7 is "1" at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations.When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required).If the Erase operation was unsuccessful, the data on Q5 is "1" (see Table 8), indicating the erase operation ex-ceed internal timing limit.The automatic erase begins on the rising edge of the last WE# or CE# pulse, whichever happens first in the com-mand sequence and terminates when either the data on Q7 is "1" at which time the device returns to the Read mode or the data on Q6 stops toggling for two consecu-tive read cycles at which time the device returns to the Read mode.。

Am29LV160BB90WCIB资料

July 2003The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-inally developed the specification, these products will be offered to customers of both AMD and Fujitsu.Continuity of SpecificationsThere is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate,and changes will be noted in a revision summary.Continuity of Ordering Part NumbersAMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document.For More InformationPlease contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.Am29L V160BData SheetPublication Number 21358 Revision G Amendment +1 Issue Date February 1, 1999元器件交易网This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.Publication# 21358Rev: G Amendment/+1 Issue Date: February 1999Am29LV160B16 Megabit (2 M x 8-Bit/1 M x 16-Bit)CMOS 3.0 Volt-only Boot Sector Flash Memory DISTINCTIVE CHARACTERISTICSs Single power supply operation—Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications —Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with highperformance 3.3 volt microprocessorss Manufactured on 0.32 µm process technologys High performance—Full voltage range: access times as fast as 80 ns —Regulated voltage range: access times as fast as70 nss Ultra low power consumption (typical values at 5MHz)—200 nA Automatic Sleep mode current—200 nA standby mode current—9 mA read current—20 mA program/erase currents Flexible sector architecture—One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-one 64 Kbyte sectors (byte mode)—One 8 Kword, two 4 Kword, one 16 Kword, and thirty-one 32 Kword sectors (word mode)—Supports full chip erase—Sector Protection features:A hardware method of locking a sector to preventany program or erase operations within that sectorSectors can be locked in-system or viaprogramming equipmentTemporary Sector Unprotect feature allows codechanges in previously locked sectorss Unlock Bypass Program Command—Reduces overall programming time when issuing multiple program command sequences s Top or bottom boot block configurations availables Embedded Algorithms—Embedded Erase algorithm automatically preprograms and erases the entire chip or anycombination of designated sectors—Embedded Program algorithm automatically writes and verifies data at specified addresses s Minimum 1,000,000 write cycle guarantee per sectors20-year data retention at 125°C—Reliable operation for the life of the systems Package option—48-ball FBGA—48-pin TSOP—44-pin SOs CFI (Common Flash Interface) compliant —Provides device-specific information to the system, allowing host software to easilyreconfigure for different Flash devicess Compatibility with JEDEC standards—Pinout and software compatible with single-power supply Flash—Superior inadvertent write protections Data# Polling and toggle bits—Provides a software method of detecting program or erase operation completions Ready/Busy# pin (RY/BY#)—Provides a hardware method of detecting program or erase cycle completion (not availableon 44-pin SO)s Erase Suspend/Erase Resume—Suspends an erase operation to read data from, or program data to, a sector that is not beingerased, then resumes the erase operations Hardware reset pin (RESET#)—Hardware method to reset the device to reading array dataGENERAL DESCRIPTIONThe Am29LV160B is a 16 Mbit, 3.0 Volt-only Flash memory organized as 2,097,152 bytes or 1,048,576 words. The device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed in-system with the standard system 3.0 volt V CC supply. A 12.0 V V PP or 5.0 V CC are not required for write or erase operations. The device can also be programmed in standard EPROM programmers.The device offers access times of 70, 80, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.The device requires only a single 3.0 volt power sup-ply for both read and write functions. Internally gener-ated and regulated voltages are provided for the program and erase operations.The Am29LV160B is entirely command set compatible with the JEDEC single-power-supply Flash stan-dard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that auto-matically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facili-tates faster programming times by requiring only two write cycles to program data instead of four.Device erasure occurs by executing the erase com-mand sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.Hardware data protection measures include a low V CC detector that automatically inhibits write operations dur-ing power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved.The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When ad-dresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.2Am29LV160BAm29LV160B 3PRODUCT SELECTOR GUIDENote:See “AC Characteristics” for full specifications.BLOCK DIAGRAMFamily Part Number Am29LV160BSpeed OptionRegulated Voltage Range: V CC =3.0–3.6 V 70RFull Voltage Range: V CC = 2.7–3.6 V8090120Max access time, ns (t ACC )708090120Max CE# access time, ns (t CE )708090120Max OE# access time, ns (t OE )30303550Input/Output Buffers X-DecoderY-Decoder Chip Enable Output EnableLogicErase Voltage GeneratorPGM Voltage GeneratorTimerV CC DetectorState Control Command RegisterV CC V SS WE#BYTE#CE#OE#STBSTBDQ0–DQ15 (A-1)Sector Switches RY/BY#RESET#Data LatchY-GatingCell MatrixA d d r e s s L a t c hA0–A1921358G-1CONNECTION DIAGRAMS21358G-2 4Am29LV160BCONNECTION DIAGRAMSSpecial Handling InstructionsSpecial handling is required for Flash Memory products in FBGA packages.Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.21358G-3Am29LV160B5PIN CONFIGURATIONA0–A19=20 addressesDQ0–DQ14=15 data inputs/outputsDQ15/A-1=DQ15 (data input/output, word mode),A-1 (LSB address input, byte mode) BYTE#=Selects 8-bit or 16-bit modeCE#=Chip enableOE#= Output enableWE#=Write enableRESET#=Hardware reset pinRY/BY#= Ready/Busy output(N/A SO 044)V CC= 3.0 volt-only single power supply(see Product Selector Guide for speedoptions and voltage supply tolerances) V SS=Device groundNC=Pin not connected internally LOGIC SYMBOL21358G-4 2016 or 8DQ0–DQ15(A-1)A0–A19CE#OE#WE#RESET#BYTE#RY/BY#(N/A SO 044)6Am29LV160BAm29LV160B 7ORDERING INFORMATION Standard ProductsAMD standard products are available in several packages and operating ranges. The order number (Valid Combi-nation) is formed by a combination of the elements below.Valid CombinationsValid Combinations list configurations planned to be sup-ported in volume for this device. Consult the local AMD salesoffice to confirm availability of specific valid combinations and to check on newly released combinations.DEVICE NUMBER/DESCRIPTION Am29LV160B16 Megabit (2M x 8-Bit/1M x 16-Bit) CMOS Flash Memory 3.0 Volt-only Read, Program, and EraseCE 70R AM29LV160B T OPTIONAL PROCESSING Blank =Standard Processing B =Burn-in(Contact an AMD representative for more information)TEMPERATURE RANGEC =Commercial (0°C to +70°C)I =Industrial (–40°C to +85°C)E =Extended (–55°C to +125°C)PACKAGE TYPEE =48-Pin Thin Small Outline Package (TSOP)Standard Pinout (TS 048)F =48-Pin Thin Small Outline Package (TSOP)Reverse Pinout (TSR048)S =44-Pin Small Outline Package (SO 044)WC =48-ball Fine-Pitch Ball Grid Array (FBGA)0.80 mm pitch, 8 x 9 mm package (FBC048)SPEED OPTIONSee Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T =Top Sector B =Bottom SectorValid Combinations For TSOP and SO Packages AM29LV160BT70R,AM29LV160BB70R EC, FC, SCAM29LV160BT80,AM29LV160BB80EC, EI, EE, FC, FI, FE,SC, SI, SE AM29LV160BT90,AM29LV160BB90AM29LV160BT120,AM29LV160BB120Valid Combinations for FBGA Packages Order NumberPackage Marking AM29LV160BT70R,AM29LV160BB70R WCCL160BT70R,L160BB70R CAM29LV160BT80,AM29LV160BB80WCC,WCI,WCEL160BT80V ,L160BB80VC, I, E AM29LV160BT90,AM29LV160BB90L160BT90V ,L160BB90VAM29LV160BT120,AM29LV160BB120L160BT12V ,L160BB12VDEVICE BUS OPERATIONSThis section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register it-self does not occupy any addressable memory loca-tion. The register is composed of latches that store the commands, along with the address and data informa-tion needed to execute the command. The contents of the register serve as inputs to the internal state ma-chine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.Table 1.Am29LV160B Device Bus OperationsLegend:L = Logic Low = V IL, H = Logic High = V IH, V ID = 12.0 ± 0.5 V, X = Don’t Care, A IN = Address In, D IN = Data In, D OUT = Data Out Notes:1.Addresses are A19:A0 in word mode (BYTE# = V IH), A19:A-1 in byte mode (BYTE# = V IL).2.The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “SectorProtection/Unprotection” section.Word/Byte ConfigurationThe BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word configura-tion. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ15–DQ0 are active and con-trolled by CE# and OE#.If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are ac-tive and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. Requirements for Reading Array DataTo read array data from the outputs, the system must drive the CE# and OE# pins to V IL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should re-main at V IH. The BYTE# pin determines whether the de-vice outputs array data in words or bytes.The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the mem-ory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that as-sert valid addresses on the device address inputs pro-duce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered.See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifica-tions and to Figure 13 for the timing diagram. I CC1 in the DC Characteristics table represents the active cur-rent specification for reading array data.Operation CE#OE#WE#RESET#Addresses(Note 1)DQ0–DQ7DQ8–DQ15BYTE#= V IHBYTE#= V ILRead L L H H A IN D OUT D OUT DQ8–DQ14 = High-Z,DQ15 = A-1 Write L H L H A IN D IN D INStandby V CC±0.3 VX XV CC±0.3 VX High-Z High-Z High-ZOutput Disable L H H H X High-Z High-Z High-Z Reset X X X L X High-Z High-Z High-ZSector Protect (Note 2)L H L V ID Sector Address,A6 = L, A1 = H,A0 = LD IN X XSector Unprotect (Note 2)L H L V ID Sector Address,A6 = H, A1 = H,A0 = LD IN X XT emporary SectorUnprotectX X X V ID A IN D IN D IN High-Z8Am29LV160BWriting Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V IL, and OE# to V IH.For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration” for more information.The device features an Unlock Bypass mode to facili-tate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word/Byte Program Command Sequence” section has details on programming data to the device using both s tandard and Unlock B ypass command sequences.An erase operation can erase one sector, multiple sec-tors, or the entire device. Tables 2 and 3 indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. The “Command Definitions”section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” and “Autoselect Command Sequence” sections for more information.I CC2 in the DC Characteristics table represents the ac-tive current specification for the write mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations.Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and I CC read specifications apply. Refer to “Write Operation Status” for more information, and to “AC Characteris-tics” for timing diagrams.Standby ModeWhen the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, inde-pendent of the OE# input.The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V CC ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at V IH, but not within V CC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data.If the device is deselected during erasure or program-ming, the device draws active current until the operation is completed.In the DC Characteristics table, I CC3 and I CC4 repre-sents the standby current specification.Automatic Sleep ModeThe automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. I CC4 in the DC Characteristics table represents the automatic sleep mode current specification.Am29LV160B9RESET#: Hardware Reset PinThe RESET# pin provides a hardware method of reset-ting the device to reading array data. When the system drives the RESET# pin to V IL for at least a period of t RP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET# pulse. The device also resets the internal state ma-chine to reading array data. The operation that was in-terrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS±0.3 V, the device draws CMOS standby current (I CC4). If RESET# is held at V IL but not within V SS±0.3 V, the standby current will be greater.The RESET# pin may be tied to the system reset cir-cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm-ware from the Flash memory.If RESET# is asserted during a program or erase op-eration, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t READY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not ex-ecuting (RY/BY# pin is “1”), the reset operation is completed within a time of t READY (not during Embed-ded Algorithms). The system can read data t RH after the RESET# pin returns to V IH.Refer to the AC Characteristics tables for RESET# pa-rameters and to Figure 14 for the timing diagram. Output Disable ModeWhen the OE# input is at V IH, output from the device is disabled. The output pins are placed in the high imped-ance state.Table 2.Sector Address Tables (Am29LV160BT)Note:Address range is A19:A-1 in byte mode and A19:A0 in word mode. See “Word/Byte Configuration” section.Sector A19A18A17A16A15A14A13A12Sector Size (Kbytes/Kwords)Address Range (in hexadecimal)Byte Mode (x8)Word Mode (x16)SA000000X X X 64/32000000–00FFFF 00000–07FFF SA100001X X X 64/32010000–01FFFF 08000–0FFFF SA200010X X X 64/32020000–02FFFF 10000–17FFF SA300011X X X 64/32030000–03FFFF 18000–1FFFF SA400100X X X 64/32040000–04FFFF 20000–27FFF SA500101X X X 64/32050000–05FFFF 28000–2FFFF SA600110X X X 64/32060000–06FFFF 30000–37FFF SA700111X X X 64/32070000–07FFFF 38000–3FFFF SA801000X X X 64/32080000–08FFFF 40000–47FFF SA901001X X X 64/32090000–09FFFF 48000–4FFFF SA1001010X X X 64/320A0000–0AFFFF 50000–57FFF SA1101011X X X 64/320B0000–0BFFFF 58000–5FFFF SA1201100X X X 64/320C0000–0CFFFF 60000–67FFF SA1301101X X X 64/320D0000–0DFFFF 68000–6FFFF SA1401110X X X 64/320E0000–0EFFFF 70000–77FFF SA1501111X X X 64/320F0000–0FFFFF 78000–7FFFF SA1610000X X X 64/32100000–10FFFF 80000–87FFF SA1710001X X X 64/32110000–11FFFF 88000–8FFFF SA1810010X X X 64/32120000–12FFFF 90000–97FFF SA1910011X X X 64/32130000–13FFFF 98000–9FFFF SA2010100X X X 64/32140000–14FFFF A0000–A7FFF SA2110101X X X 64/32150000–15FFFF A8000–AFFFF SA2210110X X X 64/32160000–16FFFF B0000–B7FFF SA2310111X X X 64/32170000–17FFFF B8000–BFFFF SA2411000X X X 64/32180000–18FFFF C0000–C7FFF SA2511001X X X 64/32190000–19FFFF C8000–CFFFF SA2611010X X X 64/321A0000–1AFFFF D0000–D7FFF SA2711011X X X 64/321B0000–1BFFFF D8000–DFFFF SA2811100X X X 64/321C0000–1CFFFF E0000–E7FFF SA2911101X X X 64/321D0000–1DFFFF E8000–EFFFF SA3011110X X X 64/321E0000–1EFFFF F0000–F7FFF SA31111110X X 32/161F0000–1F7FFF F8000–FBFFF SA32111111008/41F8000–1F9FFF FC000–FCFFF SA33111111018/41FA000–1FBFFF FD000–FDFFF SA341111111X16/81FC000–1FFFFFFE000–FFFFFTable 3.Sector Address Tables (Am29LV160BB)Note:Address range is A19:A-1 in byte mode and A19:A0 in word mode. See the “Word/Byte Configuration” section.Sector A19A18A17A16A15A14A13A12Sector Size (Kbytes/Kwords)Address Range (in hexadecimal)Byte Mode (x8)Word Mode (x16)SA00000000X 16/8000000–003FFF 00000–01FFF SA1000000108/4004000–005FFF 02000–02FFF SA2000000118/4006000–007FFF 03000–03FFF SA3000001X X 32/16008000–00FFFF 04000–07FFF SA400001X X X 64/32010000–01FFFF 08000–0FFFF SA500010X X X 64/32020000–02FFFF 10000–17FFF SA600011X X X 64/32030000–03FFFF 18000–1FFFF SA700100X X X 64/32040000–04FFFF 20000–27FFF SA800101X X X 64/32050000–05FFFF 28000–2FFFF SA900110X X X 64/32060000–06FFFF 30000–37FFF SA1000111X X X 64/32070000–07FFFF 38000–3FFFF SA1101000X X X 64/32080000–08FFFF 40000–47FFF SA1201001X X X 64/32090000–09FFFF 48000–4FFFF SA1301010X X X 64/320A0000–0AFFFF 50000–57FFF SA1401011X X X 64/320B0000–0BFFFF 58000–5FFFF SA1501100X X X 64/320C0000–0CFFFF 60000–67FFF SA1601101X X X 64/320D0000–0DFFFF 68000–6FFFF SA1701110X X X 64/320E0000–0EFFFF 70000–77FFF SA1801111X X X 64/320F0000–0FFFFF 78000–7FFFF SA1910000X X X 64/32100000–10FFFF 80000–87FFF SA2010001X X X 64/32110000–11FFFF 88000–8FFFF SA2110010X X X 64/32120000–12FFFF 90000–97FFF SA2210011X X X 64/32130000–13FFFF 98000–9FFFF SA2310100X X X 64/32140000–14FFFF A0000–A7FFF SA2410101X X X 64/32150000–15FFFF A8000–AFFFF SA2510110X X X 64/32160000–16FFFF B0000–B7FFF SA2610111X X X 64/32170000–17FFFF B8000–BFFFF SA2711000X X X 64/32180000–18FFFF C0000–C7FFF SA2811001X X X 64/32190000–19FFFF C8000–CFFFF SA2911010X X X 64/321A0000–1AFFFF D0000–D7FFF SA3011011X X X 64/321B0000–1BFFFF D8000–DFFFF SA3111100X X X 64/321C0000–1CFFFF E0000–E7FFF SA3211101X X X 64/321D0000–1DFFFF E8000–EFFFF SA3311110X X X 64/321E0000–1EFFFF F0000–F7FFF SA3411111XXX64/321F0000–1FFFFFF8000–FFFFFAutoselect ModeThe autoselect mode provides manufacturer and de-vice identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register.When using programming equipment, the autoselect mode requires V ID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Table 4. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see T ables 2 and 3). Table 4 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corre-sponding identifier code on DQ7-DQ0.To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 9. This method does not require V ID. See “Command Definitions” for details on using the autoselect mode.Table 4.Am29LV160B Autoselect Codes (High Voltage Method)L = Logic Low = V IL, H = Logic High = V IH, SA = Sector Address, X = Don’t care.Note: The autoselect codes may also be accessed in-system via command sequences. See Table 9.Sector Protection/UnprotectionThe hardware sector protection feature disables both program and erase operations in any sector. The hard-ware sector unprotection feature re-enables both pro-gram and erase operations in previously protected sectors.The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details.It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode” for details. Sector protection/unprotection can be implemented via two methods. The primary method requires V ID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algo-rithms and Figure 23 shows the timing diagram. This method uses standard microprocessor bus cycle tim-ing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle.The alternate method intended only for programming equipment requires V ID on address pin A9 and OE#. This method is compatible with programmer routines written for earlier 3.0 volt-only AMD flash devices. De-tails on this method are provided in a supplement, pub-lication number 21468. Contact an AMD representative to request a copy.Description Mode CE#OE#WE#A19toA12A11toA10A9A8toA7A6A5toA2A1A0DQ8toDQ15DQ7toDQ0Manufacturer ID: AMD L L H X X V ID X L X L L X01hDevice ID:Am29LV160B (Top Boot Block)Word L L HX X V ID X L X L H22h C4h Byte L L H X C4hDevice ID:Am29LV160B (Bottom Boot Block)Word L L HX X V ID X L X L H22h49h Byte L L H X49hSector Protection Verification L L H SA X V ID X L X H L X01h(protected) X00h(unprotected)。

EN29LV160T-90B资料

0.FEATURES• 3.0V, single power supply operation- Minimizes system level power requirements• High performance- Access times as fast as 70 ns• Low power consumption (typical values at 5 MHz)- 9 mA typical active read current- 20 mA typical program/erase current- 1 µA typical standby current (standard access time to active mode)• Flexible Sector Architecture:- One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, andthirty-one 64 Kbyte sectors (byte mode) - One 8 Kword, two 4 Kword, one 16 Kword and thirty-one 32 Kword sectors (word mode) - Supports full chip erase- Individual sector erase supported - Sector protection:Hardware locking of sectors to preventprogram or erase operations within individual sectorsAdditionally, temporary Sector GroupUnprotect allows code changes in previously locked sectors.• High performance program/erase speed- Byte program time: 8µs typical - Sector erase time: 500ms typical - Chip erase time: 17.5s typical• JEDEC Standard program and erase commands• JEDEC standard DATA polling and toggle bits feature• Single Sector and Chip Erase • Sector Unprotect Mode• Embedded Erase and Program Algorithms • Erase Suspend / Resume modes:Read and program another Sector during Erase Suspend Mode• 0.23 µm triple-metal double-poly triple-well CMOS Flash Technology • Low Vcc write inhibit < 2.5V• >100K program/erase endurance cycle• Package Options - 48-pin TSOP (Type 1) - 48 ball 6mm x 8mm FBGA • Commercial Temperature RangeGENERAL DESCRIPTIONThe EN29LV160 is a 16-Megabit, electrically erasable, read/write non-volatile flash memory, organized as 2,097,152 bytes or 1,048,576 words. Any byte can be programmed typically in 8µs. The EN29LV160 features 3.0V voltage read and write operation, with access times as fast as 70ns to eliminate the need for WAIT states in high-performance microprocessor systems.The EN29LV160 has separate Output Enable (OE ), Chip Enable (CE ), and Write Enable (WE) controls, which eliminate bus contention issues. This device is designed to allow either single Sector or full chip erase operation, where each Sector can be individually protected againstprogram/erase operations or temporarily unprotected to erase or program. The device can sustain a minimum of 100K program/erase cycles on each Sector.EN29LV160 ******PRELIMINARY DRAFT******16 Megabit (2048K x 8-bit / 1024K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-onlyCONNECTION DIAGRAMSA6 A5 A4A1A3 A2 FBGATop View, Balls Facing DownA13A9 A3 RY/BY#WE# A7 B6 B5 B4B1B3 B2 A12A8 A4NCRESET# A17 C6C5C4C1C3C2A14A10 A2A18NCA6 D6 D5 D4D1D3 D2 A15A11 A1NCA19A5 E6E5E4E1E3E2A16DQ7A0DQ2DQ5DQ0F6F5F4F3F2BYTE#DQ14CE#DQ10DQ12DQ8G6G5G4G3G2DQ15/A-1DQ13OE#DQ11Vcc DQ9H6H5H3H2VssDQ6VssDQ4DQ1F1G1H4H1DQ312 3 4 5 6 78 91011 12 1314 15 16 17 18 19202122 2324 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25Standard TSOPA15A14A13A12A11A10A9A8A19NC WE#RESET#NCNC RY/BY#A18A17A7A6A5A4A3A2A1A16 BYTE# VssDQ15/A-1DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 Vcc DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# Vss CE# A0TABLE 1. PIN DESCRIPTION FIGURE 1. LOGIC DIAGRAM Pin Name FunctionA0-A19 20AddressesDQ0-DQ14 15 Data Inputs/OutputsDQ15 / A-1 DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode)CE# ChipEnable OE# OutputEnable RESET# Hardware Reset PinRY/BY# Ready/BusyOutput WE# WriteEnableVcc Supply Voltage(2.7-3.6V)Vss Ground NC Not Connected to anythingBYTE# Byte/WordModeEN29LV160A0 – A19WECEOERY/BY ResetByteTable 2. Sector Address Tables (EN29LV160T)Address Range (in hexadecimal)Sector A19 A18 A17 A16 A15 A14A13A12Sector Size(Kbytes/ Kwords)Byte mode (x8) Word Mode(x16) SA0 0 0 0 0 0 X X X 62/32 000000–00FFFF 00000–07FFF SA1 0 0 0 0 1 X X X 64/32 010000–01FFFF 08000–0FFFF SA2 0 0 0 1 0 X X X 64/32 020000–02FFFF 10000–17FFF SA3 0 0 0 1 1 X X X 64/32 030000–03FFFF 18000–1FFFF SA4 0 0 1 0 0 X X X 64/32 040000–04FFFF 20000–27FFF SA5 0 0 1 0 1 X X X 64/32 050000–05FFFF 28000–2FFFF SA6 0 0 1 1 0 X X X 64/32 060000–06FFFF 30000–37FFF SA7 0 0 1 1 1 X X X 64/32 070000–07FFFF 38000–3FFFF SA8 0 1 0 0 0 X X X 64/32 080000–08FFFF 40000–47FFF SA9 0 1 0 0 1 X X X 64/32 090000–09FFFF 48000–4FFFF SA10 0 1 0 1 0 X X X 64/32 0A0000–0AFFFF 50000–57FFF SA11 0 1 0 1 1 X X X 64/32 0B0000–0BFFFF 58000–5FFFF SA12 0 1 1 0 0 X X X 64/32 0C0000–0CFFFF 60000–67FFF SA13 0 1 1 0 1 X X X 64/32 0D0000–0DFFFF 68000–6FFFF SA14 0 1 1 1 0 X X X 64/32 0E0000–0EFFFF 70000–77FFF SA15 0 1 1 1 1 X X X 64/32 0F0000–0FFFFF 78000–7FFFF SA16 1 0 0 0 0 X X X 64/32 100000–10FFFF 80000–87FFF SA17 1 0 0 0 1 X X X 64/32 110000–11FFFF 88000–8FFFF SA18 1 0 0 1 0 X X X 64/32 120000–12FFFF 90000–97FFF SA19 1 0 0 1 1 X X X 64/32 130000–13FFFF 98000–9FFFF SA20 1 0 1 0 0 X X X 64/32 140000–14FFFF A0000–A7FFF SA21 1 0 1 0 1 X X X 64/32 150000–15FFFF A8000–AFFFF SA22 1 0 1 1 0 X X X 64/32 160000–16FFFF B0000–B7FFF SA23 1 0 1 1 1 X X X 64/32 170000–17FFFF B8000–BFFFF SA24 1 1 0 0 0 X X X 64/32 180000–18FFFF C0000–C7FFF SA25 1 1 0 0 1 X X X 64/32 190000–19FFFF C8000–CFFFF SA26 1 1 0 1 0 X X X 64/32 1A0000–1AFFFF D0000–D7FFF SA27 1 1 0 1 1 X X X 64/32 1B0000–1BFFFF D8000–DFFFF SA28 1 1 1 0 0 X X X 64/32 1C0000–1CFFFF E0000–E7FFF SA29 1 1 1 0 1 X X X 64/32 1D0000–1DFFFF E8000–EFFFF SA30 1 1 1 1 0 X X X 64/32 1E0000–1EFFFF F0000–F7FFF SA31 1 1 1 1 1 0 X X 32/16 1F0000–1F7FFF F8000–FBFFF SA32 1 1 1 1 1 1 0 0 8/4 1F8000–1F9FFF FC000–FCFFF SA33 1 1 1 1 1 1 0 1 8/41FA000–1FBFFF FD000–FDFFFSA34 1 1 1 1 1 1 1 X16/8 1FC000–1FFFFF FE000–FFFFFTable 3. Sector Address Tables (EN29LV160B)Address Range (in hexadecimal) Sector A19 A18 A17 A16 A15 A14A13A12Sector Size (Kbytes/ Kwords)Byte mode (x8)Word Mode(x16) SA0 0 0 0 0 0 0 0 X 16/8 000000–003FFF 00000–01FFF SA1 0 0 0 0 0 0 1 0 8/4 004000–005FFF 02000–02FFF SA2 0 0 0 0 0 0 1 18/4006000–007FFF 03000–03FFFSA3 0 0 0 0 0 1 X X 32/16 008000–00FFFF 04000–07FFF SA4 0 0 0 0 1 X X X 64/32 010000–01FFFF 08000–0FFFF SA5 0 0 0 1 0 X X X 64/32 020000–02FFFF 10000–17FFF SA6 0 0 0 1 1 X X X 64/32 030000–03FFFF 18000–1FFFF SA7 0 0 1 0 0 X X X 64/32 040000–04FFFF 20000–27FFF SA8 0 0 1 0 1 X X X 64/32 050000–05FFFF 28000–2FFFF SA9 0 0 1 1 0 X X X 64/32 060000–06FFFF 30000–37FFF SA10 0 0 1 1 1 X X X 64/32 070000–07FFFF 38000–3FFFF SA11 0 1 0 0 0 X X X 64/32 080000–08FFFF 40000–47FFF SA12 0 1 0 0 1 X X X 64/32 090000–09FFFF 48000–4FFFF SA13 0 1 0 1 0 X X X 64/32 0A0000–0AFFFF 50000–57FFF SA14 0 1 0 1 1 X X X 64/32 0B0000–0BFFFF58000–5FFFFSA15 0 1 1 0 0 X X X 64/32 0C0000–0CFFFF 60000–67FFF SA16 0 1 1 0 1 X X X 64/32 0D0000–0DFFFF 68000–6FFFF SA17 0 1 1 1 0 X X X 64/32 0E0000–0EFFFF 70000–77FFF SA18 0 1 1 1 1 X X X 64/32 0F0000–0FFFFF 78000–7FFFF SA19 1 0 0 0 0 X X X 64/32 100000–10FFFF 80000–87FFF SA20 1 0 0 0 1 X X X 64/32 110000–11FFFF 88000–8FFFF SA21 1 0 0 1 0 X X X 64/32 120000–12FFFF 90000–97FFF SA22 1 0 0 1 1 X X X 64/32 130000–13FFFF 98000–9FFFF SA23 1 0 1 0 0 X X X 64/32 140000–14FFFF A0000–A7FFF SA24 1 0 1 0 1 X X X 64/32 150000–15FFFF A8000–AFFFF SA25 1 0 1 1 0 X X X 64/32 160000–16FFFF B0000–B7FFF SA26 1 0 1 1 1 X X X 64/32 170000–17FFFF B8000–BFFFF SA27 1 1 0 0 0 X X X 64/32 180000–18FFFF C0000–C7FFF SA28 1 1 0 0 1 X X X 64/32 190000–19FFFF C8000–CFFFF SA29 1 1 0 1 0 X X X 64/32 1A0000–1AFFFF D0000–D7FFF SA30 1 1 0 1 1 X X X 64/32 1B0000–1BFFFF D8000–DFFFF SA31 1 1 1 0 0 X X X 64/32 1C0000–1CFFFF E0000–E7FFF SA32 1 1 1 0 1 X X X 64/32 1D0000–1DFFFF E8000–EFFFF SA33 1 1 1 1 0 X X X 64/32 1E0000–1EFFFF F0000–F7FFF SA34 1 1 1 1 1 X X X 64/321F0000–1FFFFF F8000–FFFFFPRODUCT SELECTOR GUIDEProduct Number EN29LV160Regulated Voltage Range: Vcc=3.0 – 3.6 VSpeed OptionFull Voltage Range: Vcc=2.7 – 3.6 V-70 -90Max Access Time, ns (t acc ) 70 90Max CE# Access, ns (t ce ) 70 90Max OE# Access, ns (t oe ) 30 35BLOCK DIAGRAMWECE OEState ControlCommand RegisterErase Voltage GeneratorInput/Output BuffersProgram Voltage GeneratorChip Enable Output EnableLogicData LatchY-Decoder X-DecoderY-GatingCell MatrixTimerVcc DetectorA0-A19Vcc VssDQ0-DQ15 (A-1)Address LatchBlock Protect SwitchesSTBSTBRY/BYTABLE 3. OPERATING MODES16M FLASH USER MODE TABLEDQ8-DQ15Operation CE# OE# WE# Reset# A0-A19 DQ0-DQ7 Byte# = V IH Byte#= V IL Read L L H H A IN D OUT D OUT High-Z Write L H L H A IN D IN D IN High-Z CMOS Standby V cc ± 0.3V X X V cc ± 0.3V X High-Z High-Z High-Z TTL Standby H X X H X High-Z High-Z High-Z Output Disable L H H H X High-Z High-Z High-Z Hardware Reset X X X L X High-Z High-Z High-Z TemporarySector Unprotect X X X V IDA IN D IN D IN XNotes:L=logic low= V IL , H=Logic High= V IH , V ID =11 ± 0.5V, X=Don’t Care (either L or H, but not floating!), D IN =Data In, D OUT =Data Out, A IN =Address InTABLE 4. DEVICE IDENTIFICTION (Autoselect Codes)16M FLASH MANUFACTURER/DEVICE ID TABLENote:1. A8=H is recommended for Manufacturing ID check. If a manufacturing ID is read with A8=L, the chip will output a configuration code 7Fh2. A9 = VID is for HV A9 Autoselect mode only. A9 must be ≤ Vcc (CMOS logic level) for Command Autoselect Mode.Description Mode A19 to A12A11 toA10A92A8A7A6A5 to A2A1 A0 DQ8to DQ15 DQ7 to DQ0 Manufacturer ID:EonL L H X X V IDH1X L X L L X 1CH Word L L H22h C4H Device ID (top bootblock) Byte L L H X X V ID X X L X L H X C4H Word L L H22h49H Device ID(bottom bootblock)Byte L L HX X V IDXXLXLHX 49H X01h(Protected)Sector ProtectionVerification L L H SA X V IDX X L X H LX00h(Unprotected)OE CE WEUSER MODE DEFINITIONSWord / Byte ConfigurationThe signal set on the BYTE# Pin controls whether the device data I/O pins DQ15-DQ0 operate in the byte or word configuration. When the Byte# Pin is set at logic ‘1’, then the device is in word configuration, DQ15-DQ0 are active and are controlled by CE# and OE#.On the other hand, if the Byte# Pin is set at logic ‘0’, then the device is in byte configuration, and only data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.Standby ModeThe EN29LV160 has a CMOS-compatible standby mode, which reduces the current to < 1µA (typical). It is placed in CMOS-compatible standby when the CE pin is at V CC± 0.5. RESET# and BYTE# pin must also be at CMOS input levels. The device also has a TTL-compatible standby mode, which reduces the maximum V CC current to < 1mA. It is placed in TTL-compatible standby when the pin is at V IH. When in standby modes, the outputs are in a high-impedance state independent of the OE input.Read ModeThe device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm.After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” for more additional information.The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” additional details.Output Disable ModeWhen the CE or OE pin is at a logic high level (V IH), the output from the EN29LV160 is disabled. The output pins are placed in a high impedance state.Auto Select Identification ModeThe autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ15–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register.When using programming equipment, the autoselect mode requires V ID (10.5 V to 11.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes table. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the remaining address bits that are don’t-care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15–DQ0.To access the autoselect codes in-system; the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require V ID. See “Command Definitions” for details on using the autoselect mode.Write ModeProgramming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. The Command Definitions in Table 5 show the address and data requirements for the byte program command sequence.When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. See “Write Operation Status” for information on these status bits.Any commands written to the device during the Embedded Program Algorithm are ignored.Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set DQ5 to “1”, or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”.Sector Protection/UnprotectionThe hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors.There are two methods to enabling this hardware protection circuitry. The first one requires only that the RESET# pin be at V ID and then standard microprocessor timings can be used to enable or disable this feature. See Flowchart 7a and 7b for the algorithm and Figure 12 for the timings.When doing Sector Unprotect, all the other sectors should be protected first.The second method is meant for programming equipment. This method requires V ID be applied to both OE# and A9 pin and non-standard microprocessor timings are used. This method is described in a separate document called EN29LV160 Supplement, which can be obtained by contacting a representative of Eon Silicon Solution, Inc.Temporary Sector UnprotectThis feature allows temporary unprotection of previously protectedsector groups to change data while in-system. The Sector Unprotectmode is activated by setting the RESET# pin to V ID. During this mode,formerly protected sectors can be programmed or erased by simplyselecting the sector addresses. Once is removed from the RESET#pin, all the previously protected sectors are protected again. Seeaccompanying figure and timing diagrams for more details.COMMON FLASH MEMORYINTERFACE(CFI)The common flash interface (CFI) specification outlines device and host systems software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support canStartReset#=V ID(note 1)Perform Erase or ProgramOperationsReset#=V IHTemporary SectorUnprotect Completed (note 2)Notes:1. All protected sectors unprotected.2. Previously protected sectors protected again.then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendirs can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 5-8. In word mode, the upper address bits (A7–MSB) must be all zeros. To terminate reading CFI data, the system must write the reset command.The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode and the system can read CFI data at the addresses given in Tables 5–8. The system must write the reset command to return the device to the autoselect mode.Table 5. CFI Query Identification StringAdresses (Word Mode)Adresses(Byte Mode) Data Description10h 11h 12h 20h22h24h0051h0052h0059hQuery Unique ASCII string “QRY”13h 14h 26h28h0002h0000hPrimary OEM Command Set15h 16h 2Ah2Ch0040h0000hAddress for Primary Extended Table17h 18h 2Eh30h0000h0000hAlternate OEM Command set (00h = none exists)19h 1Ah 32h34h0000h0000hAddress for Alternate OEM Extended Table (00h = none exists Table 6. System Interface StringAddresses (Word Mode)Addresses(Byte Mode) Data Description1Bh 36h 0027hVccMin(write/erase)D7-D4: volt, D3 –D0: 100 millivolt1Ch 38h 0036h Vcc Max (write/erase)D7-D4: volt, D3 –D0: 100 millivolt1Dh 3Ah 0000h Vpp Min. voltage (00h = no Vpp pin present)1Eh 3Ch 0000h Vpp Max. voltage (00h = no Vpp pin present)1Fh 3Eh 0004hTypical timeout per single byte/word write 2^N µs20h 40h 0000hTypical timeout for Min, size buffer write 2^N µs (00h = notsupported)21h 42h 000Ah Typical timeout per individual block erase 2^N ms22h 44h 0000h Typical timeout for full chip erase 2^N ms (00h = not supported) 23h 46h 0005h Max. timeout for byte/word write 2^N times typical24h 48h 0000h Max. timeout for buffer write 2^N times typical25h 4Ah 0004h Max. timeout per individual block erase 2^N times typical26h 4Ch 0000h Max timeout for full chip erase 2^N times typical (00h = notsupported)Table 7. Device Geometry DefinitionAddresses (Word mode)Addresses(Byte Mode) Data Description27h 4Eh 0015h Device Size = 2^N byte28h 29h 50h 52h 0002h 0000h Flash Device Interface description (refer to CFI publication 100) 2Ah 2Bh 54h 56h 0000h 0000h Max. number of byte in multi-byte write = 2^N (00h = not supported)2Ch 58h 0004h Number of Erase Block Regions within device 2Dh 2Eh 2Fh 30h 5Ah 5Ch 5Eh 60h 0000h 0000h 0040h 0000h Erase Block Region 1 Information(refer to the CFI specification of CFI publication 100)31h 32h 33h 34h 62h 64h 66h 68h 0001h 0000h 0020h 0000h Erase Block Region 2 Information35h 36h 37h 38h 6Ah 6Ch 6Eh 70h 0000h 0000h 0080h 0000h Erase Block Region 3 Information39h 3Ah 3Bh 3Ch72h 74h 76h 78h001Eh 0000h 0000h 0001hErase Block Region 4 InformationTable 8. Primary Vendor-specific Extended QueryAdresses (Word Mode)Addresses (Byte Mode)Data Description 40h 41h 42h 80h 82h 84h 0050h0052h 0049hQuery-unique ASCII string “PRI” 43h 86h 0031h Major version number, ASCII 44h88h0030h Minor version number, ASCII45h 8Ah 0000hAddress Sensitive Unlock0 = Required, 1 = Not Required 46h 8Ch 0002hErase Suspend0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 8Eh 0001hSector Protect0 = Not Supported, X = Number of sectors in per group 48h 90h 0001hSector Temporary Unprotect00 = Not Supported, 01 = Supported 49h 92h 0004h Sector Protect/Unprotect scheme01 = 29F040 mode, 02 = 29F016 mode,03 = 29F400 mode, 04 = 29LV800A mode 4Ah 94h 0000hSimultaneous Operation00 = Not Supported, 01 = Supported 4Bh 96h 0000hBurst Mode Type00 = Not Supported, 01 = Supported 4Ch 98h 0000hPage Mode Type00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word PageHardware Data protectionThe command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes as seen in the Command Definitions table. Additionally, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by false system level signals during Vcc power up and power down transitions, or from system noise.Low V CC Write InhibitWhen Vcc is less than V LKO, the device does not accept any write cycles. This protects data during Vcc power up and power down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until Vcc is greater than V LKO. The system must provide the proper signals to the control pins to prevent unintentional writes when Vcc is greater than V LKO. Write Pulse “Glitch” protectionNoise pulses of less than 5 ns (typical) on OE, CE or W E do not initiate a write cycle.Logical InhibitWrite cycles are inhibited by holding any one of OE = VIL, CE = VIH, or W E = VIH. To initiate a write cycle, CE and W E must be a logical zero while OE is a logical one. If CE, W E, and OE are all logical zero (not recommended usage), it will be considered a read.Power-up Write InhibitDuring power-up, the device automatically resets to READ mode and locks out write cycles. Even with CE = V IL, W E = V IL and OE = V IH, the device will not accept commands on the rising edge of W E.COMMAND DEFINITIONSThe operations of the EN29LV160 are selected by one or more commands written into the command register to perform Read/Reset Memory, Read ID, Read Sector Protection, Program, Sector Erase, Chip Erase, Erase Suspend and Erase Resume. Commands are made up of data sequences written at specific addresses via the command register. The sequences for the specified operation are defined in the Command Definitions table (Table 5). Incorrect addresses, incorrect data values or improper sequences will reset the device to Read Mode.Table 9. EN29LV160 Command DefinitionsBus Cycles1stWrite Cycle 2ndWrite Cycle 3rdWrite Cycle4thWrite Cycle5thWrite Cycle6thWrite Cycle Command SequenceC y c l e sAdd DataAdd DataAdd DataAdd DataAdd DataAdd DataRead 1 RA RDReset 1 xxx F0Word555 2AA555000/1007F/1CManufacturerID Byte 4AAA AA55555AAA90000/2007F/1CWord 555 2AA555 x0122C4 Device ID Top Boot Byte 4 AAA AA55555 AAA 90x02 C4Word 555 2AA555 x01 2249Device ID Bottom Boot Byte 4AAA AA55555AAA 90x02 49XX00Word5552AA555(SA)X02XX0100A u t o s e l e c tSector Protect Verify Byte4AAA AA55555AAA90(SA)X0401Word 555 2AA555ProgramByte 4 AAA AA55555 AAAA0 PA PDWord555 2AA555Unlock BypassByte3 AAA AA55555 AAA 20Unlock Bypass Program 2 XXX A0 PA PD Unlock Bypass Reset2 XXX 90 XXX 00 Word555 2AA555 5552AA 555Chip EraseByte 6 AAA AA55555 AAA 80 AAA AA 555 55 AAA 10Word555 2AA555 5552AASector EraseByte6 AAA AA55555 AAA 80 AAA AA 555 55 SA 30Erase Suspend 1 xxx B0 Erase Resume1 xxx 30Address and Data values indicated in hexRA = Read Address: address of the memory location to be read. This is a read cycle. RD = Read Data: data read from location RA during Read operation. This is a read cycle. PA = Program Address: address of the memory location to be programmed. X = Don’t-Care PD = Program Data: data to be programmed at location PASA = Sector Address: address of the Sector to be erased or verified. Address bits A19-A12 uniquely select any Sector.Reading Array DataThe device is automatically set to reading array data after power up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm.Following an Erase Suspend command, Erase Suspend mode is entered. The system can read array data using the standard read timings, with the only difference in that if it reads at an address within erase suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception.The Reset command must be issued to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See next section for details on Reset.Reset CommandWriting the reset command to the device resets the device to reading array data. Address bits are don’t-care for this command.The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete.The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend).If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).Autoselect Command SequenceThe autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. This is an alternative to the method that requires V ID on address bit A9 and is intended for PROM programmers.Two unlock cycles followed by the autoselect command initiate the autoselect command sequence. Autoselect mode is then entered and the system may read at addresses shown in Table 4 any number of times, without needing another command sequence.The system must write the reset command to exit the autoselect mode and return to reading array data. Word / Byte Programming CommandThe device may be programmed by byte or by word, depending on the state of the Byte# Pin. Programming the EN29LV160 is performed by using a four bus-cycle operation (two unlock write cycles followed by the Program Setup command and Program Data Write cycle). When the program command is executed, no additional CPU controls or timings are necessary. An internal timer terminates the program operation automatically. Address is latched on the falling edge of CE or W E, whichever is last; data is latched on the rising edge of CE or W E, whichever is first. Programming status may be checked by sampling data on DQ7 (DATA polling) or on DQ6 (toggle bit). ). When the program operation is successfully completed, the device returns to read mode and the user can read the data programmed to the device at that address. Note that data can not be programmed from a 0 to a 1. Only an erase operation can change a data from 0 to 1. When programming time limit is exceeded, DQ5 will produce a logical “1” and a Reset command can return the device to Read mode.Unlock BypassTo speed up programming operation, the Unlock Bypass Command may be used. Once this feature is activated, the shorter two cycle Unlock Bypass Program command can be used instead of the normal four cycle Program Command to program the device. This mode is exited after issuing the Unlock Bypass Reset Command. The device powers up with this feature disabled.。

AM29BDD160GB20APBE资料

NOTE: For new designs, S29CD016G supersedes Am29BDD160G and is the factory-recommended migration path for this device. Please refer to the S29CD016G datasheet for specifications and ordering information.
The Am29BDD160 is a 16 Megabit, 2.5 Volt-only single power su pply bu rs t mode fl as h memory dev i ce . The dev i ce c a n b e conf i g u red for e i ther 1,04 8 ,576 word s i n 16- bi t mode or 524,2 88 do ub le word s i n 32-bit mode. The device can also be programmed in standard EPROM programmers. The device offers a configurable burst interface to 16/32-bit microprocessors and microcontrollers. To eliminate bus contention, each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Additional control inputs are required for synchronous burst operations:

EN29LV160B-70TP资料

0.FEATURES• 3.0V, single power supply operation- Minimizes system level power requirements• High performance- Access times as fast as 70 ns• Low power consumption (typical values at 5 MHz)- 9 mA typical active read current- 20 mA typical program/erase current- 1 µA typical standby current (standard access time to active mode)• Flexible Sector Architecture:- One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, andthirty-one 64 Kbyte sectors (byte mode) - One 8 Kword, two 4 Kword, one 16 Kword and thirty-one 32 Kword sectors (word mode) - Supports full chip erase- Individual sector erase supported - Sector protection:Hardware locking of sectors to preventprogram or erase operations within individual sectorsAdditionally, temporary Sector GroupUnprotect allows code changes in previously locked sectors.• High performance program/erase speed- Byte program time: 8µs typical - Sector erase time: 500ms typical - Chip erase time: 17.5s typical• JEDEC Standard program and erase commands• JEDEC standard DATA polling and toggle bits feature• Single Sector and Chip Erase • Sector Unprotect Mode• Embedded Erase and Program Algorithms • Erase Suspend / Resume modes:Read and program another Sector during Erase Suspend Mode• 0.23 µm triple-metal double-poly triple-well CMOS Flash Technology • Low Vcc write inhibit < 2.5V• >100K program/erase endurance cycle• Package Options - 48-pin TSOP (Type 1) - 48 ball 6mm x 8mm FBGA • Commercial Temperature RangeGENERAL DESCRIPTIONThe EN29LV160 is a 16-Megabit, electrically erasable, read/write non-volatile flash memory, organized as 2,097,152 bytes or 1,048,576 words. Any byte can be programmed typically in 8µs. The EN29LV160 features 3.0V voltage read and write operation, with access times as fast as 70ns to eliminate the need for WAIT states in high-performance microprocessor systems.The EN29LV160 has separate Output Enable (OE ), Chip Enable (CE ), and Write Enable (WE) controls, which eliminate bus contention issues. This device is designed to allow either single Sector or full chip erase operation, where each Sector can be individually protected againstprogram/erase operations or temporarily unprotected to erase or program. The device can sustain a minimum of 100K program/erase cycles on each Sector.EN29LV160 ******PRELIMINARY DRAFT******16 Megabit (2048K x 8-bit / 1024K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-onlyCONNECTION DIAGRAMSA6 A5 A4A1A3 A2 FBGATop View, Balls Facing DownA13A9 A3 RY/BY#WE# A7 B6 B5 B4B1B3 B2 A12A8 A4NCRESET# A17 C6C5C4C1C3C2A14A10 A2A18NCA6 D6 D5 D4D1D3 D2 A15A11 A1NCA19A5 E6E5E4E1E3E2A16DQ7A0DQ2DQ5DQ0F6F5F4F3F2BYTE#DQ14CE#DQ10DQ12DQ8G6G5G4G3G2DQ15/A-1DQ13OE#DQ11Vcc DQ9H6H5H3H2VssDQ6VssDQ4DQ1F1G1H4H1DQ312 3 4 5 6 78 91011 12 1314 15 16 17 18 19202122 2324 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25Standard TSOPA15A14A13A12A11A10A9A8A19NC WE#RESET#NCNC RY/BY#A18A17A7A6A5A4A3A2A1A16 BYTE# VssDQ15/A-1DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 Vcc DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# Vss CE# A0TABLE 1. PIN DESCRIPTION FIGURE 1. LOGIC DIAGRAM Pin Name FunctionA0-A19 20AddressesDQ0-DQ14 15 Data Inputs/OutputsDQ15 / A-1 DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode)CE# ChipEnable OE# OutputEnable RESET# Hardware Reset PinRY/BY# Ready/BusyOutput WE# WriteEnableVcc Supply Voltage(2.7-3.6V)Vss Ground NC Not Connected to anythingBYTE# Byte/WordModeEN29LV160A0 – A19WECEOERY/BY ResetByteTable 2. Sector Address Tables (EN29LV160T)Address Range (in hexadecimal)Sector A19 A18 A17 A16 A15 A14A13A12Sector Size(Kbytes/ Kwords)Byte mode (x8) Word Mode(x16) SA0 0 0 0 0 0 X X X 62/32 000000–00FFFF 00000–07FFF SA1 0 0 0 0 1 X X X 64/32 010000–01FFFF 08000–0FFFF SA2 0 0 0 1 0 X X X 64/32 020000–02FFFF 10000–17FFF SA3 0 0 0 1 1 X X X 64/32 030000–03FFFF 18000–1FFFF SA4 0 0 1 0 0 X X X 64/32 040000–04FFFF 20000–27FFF SA5 0 0 1 0 1 X X X 64/32 050000–05FFFF 28000–2FFFF SA6 0 0 1 1 0 X X X 64/32 060000–06FFFF 30000–37FFF SA7 0 0 1 1 1 X X X 64/32 070000–07FFFF 38000–3FFFF SA8 0 1 0 0 0 X X X 64/32 080000–08FFFF 40000–47FFF SA9 0 1 0 0 1 X X X 64/32 090000–09FFFF 48000–4FFFF SA10 0 1 0 1 0 X X X 64/32 0A0000–0AFFFF 50000–57FFF SA11 0 1 0 1 1 X X X 64/32 0B0000–0BFFFF 58000–5FFFF SA12 0 1 1 0 0 X X X 64/32 0C0000–0CFFFF 60000–67FFF SA13 0 1 1 0 1 X X X 64/32 0D0000–0DFFFF 68000–6FFFF SA14 0 1 1 1 0 X X X 64/32 0E0000–0EFFFF 70000–77FFF SA15 0 1 1 1 1 X X X 64/32 0F0000–0FFFFF 78000–7FFFF SA16 1 0 0 0 0 X X X 64/32 100000–10FFFF 80000–87FFF SA17 1 0 0 0 1 X X X 64/32 110000–11FFFF 88000–8FFFF SA18 1 0 0 1 0 X X X 64/32 120000–12FFFF 90000–97FFF SA19 1 0 0 1 1 X X X 64/32 130000–13FFFF 98000–9FFFF SA20 1 0 1 0 0 X X X 64/32 140000–14FFFF A0000–A7FFF SA21 1 0 1 0 1 X X X 64/32 150000–15FFFF A8000–AFFFF SA22 1 0 1 1 0 X X X 64/32 160000–16FFFF B0000–B7FFF SA23 1 0 1 1 1 X X X 64/32 170000–17FFFF B8000–BFFFF SA24 1 1 0 0 0 X X X 64/32 180000–18FFFF C0000–C7FFF SA25 1 1 0 0 1 X X X 64/32 190000–19FFFF C8000–CFFFF SA26 1 1 0 1 0 X X X 64/32 1A0000–1AFFFF D0000–D7FFF SA27 1 1 0 1 1 X X X 64/32 1B0000–1BFFFF D8000–DFFFF SA28 1 1 1 0 0 X X X 64/32 1C0000–1CFFFF E0000–E7FFF SA29 1 1 1 0 1 X X X 64/32 1D0000–1DFFFF E8000–EFFFF SA30 1 1 1 1 0 X X X 64/32 1E0000–1EFFFF F0000–F7FFF SA31 1 1 1 1 1 0 X X 32/16 1F0000–1F7FFF F8000–FBFFF SA32 1 1 1 1 1 1 0 0 8/4 1F8000–1F9FFF FC000–FCFFF SA33 1 1 1 1 1 1 0 1 8/41FA000–1FBFFF FD000–FDFFFSA34 1 1 1 1 1 1 1 X16/8 1FC000–1FFFFF FE000–FFFFFTable 3. Sector Address Tables (EN29LV160B)Address Range (in hexadecimal) Sector A19 A18 A17 A16 A15 A14A13A12Sector Size (Kbytes/ Kwords)Byte mode (x8)Word Mode(x16) SA0 0 0 0 0 0 0 0 X 16/8 000000–003FFF 00000–01FFF SA1 0 0 0 0 0 0 1 0 8/4 004000–005FFF 02000–02FFF SA2 0 0 0 0 0 0 1 18/4006000–007FFF 03000–03FFFSA3 0 0 0 0 0 1 X X 32/16 008000–00FFFF 04000–07FFF SA4 0 0 0 0 1 X X X 64/32 010000–01FFFF 08000–0FFFF SA5 0 0 0 1 0 X X X 64/32 020000–02FFFF 10000–17FFF SA6 0 0 0 1 1 X X X 64/32 030000–03FFFF 18000–1FFFF SA7 0 0 1 0 0 X X X 64/32 040000–04FFFF 20000–27FFF SA8 0 0 1 0 1 X X X 64/32 050000–05FFFF 28000–2FFFF SA9 0 0 1 1 0 X X X 64/32 060000–06FFFF 30000–37FFF SA10 0 0 1 1 1 X X X 64/32 070000–07FFFF 38000–3FFFF SA11 0 1 0 0 0 X X X 64/32 080000–08FFFF 40000–47FFF SA12 0 1 0 0 1 X X X 64/32 090000–09FFFF 48000–4FFFF SA13 0 1 0 1 0 X X X 64/32 0A0000–0AFFFF 50000–57FFF SA14 0 1 0 1 1 X X X 64/32 0B0000–0BFFFF58000–5FFFFSA15 0 1 1 0 0 X X X 64/32 0C0000–0CFFFF 60000–67FFF SA16 0 1 1 0 1 X X X 64/32 0D0000–0DFFFF 68000–6FFFF SA17 0 1 1 1 0 X X X 64/32 0E0000–0EFFFF 70000–77FFF SA18 0 1 1 1 1 X X X 64/32 0F0000–0FFFFF 78000–7FFFF SA19 1 0 0 0 0 X X X 64/32 100000–10FFFF 80000–87FFF SA20 1 0 0 0 1 X X X 64/32 110000–11FFFF 88000–8FFFF SA21 1 0 0 1 0 X X X 64/32 120000–12FFFF 90000–97FFF SA22 1 0 0 1 1 X X X 64/32 130000–13FFFF 98000–9FFFF SA23 1 0 1 0 0 X X X 64/32 140000–14FFFF A0000–A7FFF SA24 1 0 1 0 1 X X X 64/32 150000–15FFFF A8000–AFFFF SA25 1 0 1 1 0 X X X 64/32 160000–16FFFF B0000–B7FFF SA26 1 0 1 1 1 X X X 64/32 170000–17FFFF B8000–BFFFF SA27 1 1 0 0 0 X X X 64/32 180000–18FFFF C0000–C7FFF SA28 1 1 0 0 1 X X X 64/32 190000–19FFFF C8000–CFFFF SA29 1 1 0 1 0 X X X 64/32 1A0000–1AFFFF D0000–D7FFF SA30 1 1 0 1 1 X X X 64/32 1B0000–1BFFFF D8000–DFFFF SA31 1 1 1 0 0 X X X 64/32 1C0000–1CFFFF E0000–E7FFF SA32 1 1 1 0 1 X X X 64/32 1D0000–1DFFFF E8000–EFFFF SA33 1 1 1 1 0 X X X 64/32 1E0000–1EFFFF F0000–F7FFF SA34 1 1 1 1 1 X X X 64/321F0000–1FFFFF F8000–FFFFFPRODUCT SELECTOR GUIDEProduct Number EN29LV160Regulated Voltage Range: Vcc=3.0 – 3.6 VSpeed OptionFull Voltage Range: Vcc=2.7 – 3.6 V-70 -90Max Access Time, ns (t acc ) 70 90Max CE# Access, ns (t ce ) 70 90Max OE# Access, ns (t oe ) 30 35BLOCK DIAGRAMWECE OEState ControlCommand RegisterErase Voltage GeneratorInput/Output BuffersProgram Voltage GeneratorChip Enable Output EnableLogicData LatchY-Decoder X-DecoderY-GatingCell MatrixTimerVcc DetectorA0-A19Vcc VssDQ0-DQ15 (A-1)Address LatchBlock Protect SwitchesSTBSTBRY/BYTABLE 3. OPERATING MODES16M FLASH USER MODE TABLEDQ8-DQ15Operation CE# OE# WE# Reset# A0-A19 DQ0-DQ7 Byte# = V IH Byte#= V IL Read L L H H A IN D OUT D OUT High-Z Write L H L H A IN D IN D IN High-Z CMOS Standby V cc ± 0.3V X X V cc ± 0.3V X High-Z High-Z High-Z TTL Standby H X X H X High-Z High-Z High-Z Output Disable L H H H X High-Z High-Z High-Z Hardware Reset X X X L X High-Z High-Z High-Z TemporarySector Unprotect X X X V IDA IN D IN D IN XNotes:L=logic low= V IL , H=Logic High= V IH , V ID =11 ± 0.5V, X=Don’t Care (either L or H, but not floating!), D IN =Data In, D OUT =Data Out, A IN =Address InTABLE 4. DEVICE IDENTIFICTION (Autoselect Codes)16M FLASH MANUFACTURER/DEVICE ID TABLENote:1. A8=H is recommended for Manufacturing ID check. If a manufacturing ID is read with A8=L, the chip will output a configuration code 7Fh2. A9 = VID is for HV A9 Autoselect mode only. A9 must be ≤ Vcc (CMOS logic level) for Command Autoselect Mode.Description Mode A19 to A12A11 toA10A92A8A7A6A5 to A2A1 A0 DQ8to DQ15 DQ7 to DQ0 Manufacturer ID:EonL L H X X V IDH1X L X L L X 1CH Word L L H22h C4H Device ID (top bootblock) Byte L L H X X V ID X X L X L H X C4H Word L L H22h49H Device ID(bottom bootblock)Byte L L HX X V IDXXLXLHX 49H X01h(Protected)Sector ProtectionVerification L L H SA X V IDX X L X H LX00h(Unprotected)OE CE WEUSER MODE DEFINITIONSWord / Byte ConfigurationThe signal set on the BYTE# Pin controls whether the device data I/O pins DQ15-DQ0 operate in the byte or word configuration. When the Byte# Pin is set at logic ‘1’, then the device is in word configuration, DQ15-DQ0 are active and are controlled by CE# and OE#.On the other hand, if the Byte# Pin is set at logic ‘0’, then the device is in byte configuration, and only data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.Standby ModeThe EN29LV160 has a CMOS-compatible standby mode, which reduces the current to < 1µA (typical). It is placed in CMOS-compatible standby when the CE pin is at V CC± 0.5. RESET# and BYTE# pin must also be at CMOS input levels. The device also has a TTL-compatible standby mode, which reduces the maximum V CC current to < 1mA. It is placed in TTL-compatible standby when the pin is at V IH. When in standby modes, the outputs are in a high-impedance state independent of the OE input.Read ModeThe device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm.After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” for more additional information.The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” additional details.Output Disable ModeWhen the CE or OE pin is at a logic high level (V IH), the output from the EN29LV160 is disabled. The output pins are placed in a high impedance state.Auto Select Identification ModeThe autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ15–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register.When using programming equipment, the autoselect mode requires V ID (10.5 V to 11.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes table. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the remaining address bits that are don’t-care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15–DQ0.To access the autoselect codes in-system; the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require V ID. See “Command Definitions” for details on using the autoselect mode.Write ModeProgramming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. The Command Definitions in Table 5 show the address and data requirements for the byte program command sequence.When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. See “Write Operation Status” for information on these status bits.Any commands written to the device during the Embedded Program Algorithm are ignored.Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set DQ5 to “1”, or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”.Sector Protection/UnprotectionThe hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors.There are two methods to enabling this hardware protection circuitry. The first one requires only that the RESET# pin be at V ID and then standard microprocessor timings can be used to enable or disable this feature. See Flowchart 7a and 7b for the algorithm and Figure 12 for the timings.When doing Sector Unprotect, all the other sectors should be protected first.The second method is meant for programming equipment. This method requires V ID be applied to both OE# and A9 pin and non-standard microprocessor timings are used. This method is described in a separate document called EN29LV160 Supplement, which can be obtained by contacting a representative of Eon Silicon Solution, Inc.Temporary Sector UnprotectThis feature allows temporary unprotection of previously protectedsector groups to change data while in-system. The Sector Unprotectmode is activated by setting the RESET# pin to V ID. During this mode,formerly protected sectors can be programmed or erased by simplyselecting the sector addresses. Once is removed from the RESET#pin, all the previously protected sectors are protected again. Seeaccompanying figure and timing diagrams for more details.COMMON FLASH MEMORYINTERFACE(CFI)The common flash interface (CFI) specification outlines device and host systems software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support canStartReset#=V ID(note 1)Perform Erase or ProgramOperationsReset#=V IHTemporary SectorUnprotect Completed (note 2)Notes:1. All protected sectors unprotected.2. Previously protected sectors protected again.then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendirs can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 5-8. In word mode, the upper address bits (A7–MSB) must be all zeros. To terminate reading CFI data, the system must write the reset command.The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode and the system can read CFI data at the addresses given in Tables 5–8. The system must write the reset command to return the device to the autoselect mode.Table 5. CFI Query Identification StringAdresses (Word Mode)Adresses(Byte Mode) Data Description10h 11h 12h 20h22h24h0051h0052h0059hQuery Unique ASCII string “QRY”13h 14h 26h28h0002h0000hPrimary OEM Command Set15h 16h 2Ah2Ch0040h0000hAddress for Primary Extended Table17h 18h 2Eh30h0000h0000hAlternate OEM Command set (00h = none exists)19h 1Ah 32h34h0000h0000hAddress for Alternate OEM Extended Table (00h = none exists Table 6. System Interface StringAddresses (Word Mode)Addresses(Byte Mode) Data Description1Bh 36h 0027hVccMin(write/erase)D7-D4: volt, D3 –D0: 100 millivolt1Ch 38h 0036h Vcc Max (write/erase)D7-D4: volt, D3 –D0: 100 millivolt1Dh 3Ah 0000h Vpp Min. voltage (00h = no Vpp pin present)1Eh 3Ch 0000h Vpp Max. voltage (00h = no Vpp pin present)1Fh 3Eh 0004hTypical timeout per single byte/word write 2^N µs20h 40h 0000hTypical timeout for Min, size buffer write 2^N µs (00h = notsupported)21h 42h 000Ah Typical timeout per individual block erase 2^N ms22h 44h 0000h Typical timeout for full chip erase 2^N ms (00h = not supported) 23h 46h 0005h Max. timeout for byte/word write 2^N times typical24h 48h 0000h Max. timeout for buffer write 2^N times typical25h 4Ah 0004h Max. timeout per individual block erase 2^N times typical26h 4Ch 0000h Max timeout for full chip erase 2^N times typical (00h = notsupported)Table 7. Device Geometry DefinitionAddresses (Word mode)Addresses(Byte Mode) Data Description27h 4Eh 0015h Device Size = 2^N byte28h 29h 50h 52h 0002h 0000h Flash Device Interface description (refer to CFI publication 100) 2Ah 2Bh 54h 56h 0000h 0000h Max. number of byte in multi-byte write = 2^N (00h = not supported)2Ch 58h 0004h Number of Erase Block Regions within device 2Dh 2Eh 2Fh 30h 5Ah 5Ch 5Eh 60h 0000h 0000h 0040h 0000h Erase Block Region 1 Information(refer to the CFI specification of CFI publication 100)31h 32h 33h 34h 62h 64h 66h 68h 0001h 0000h 0020h 0000h Erase Block Region 2 Information35h 36h 37h 38h 6Ah 6Ch 6Eh 70h 0000h 0000h 0080h 0000h Erase Block Region 3 Information39h 3Ah 3Bh 3Ch72h 74h 76h 78h001Eh 0000h 0000h 0001hErase Block Region 4 InformationTable 8. Primary Vendor-specific Extended QueryAdresses (Word Mode)Addresses (Byte Mode)Data Description 40h 41h 42h 80h 82h 84h 0050h0052h 0049hQuery-unique ASCII string “PRI” 43h 86h 0031h Major version number, ASCII 44h88h0030h Minor version number, ASCII45h 8Ah 0000hAddress Sensitive Unlock0 = Required, 1 = Not Required 46h 8Ch 0002hErase Suspend0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 8Eh 0001hSector Protect0 = Not Supported, X = Number of sectors in per group 48h 90h 0001hSector Temporary Unprotect00 = Not Supported, 01 = Supported 49h 92h 0004h Sector Protect/Unprotect scheme01 = 29F040 mode, 02 = 29F016 mode,03 = 29F400 mode, 04 = 29LV800A mode 4Ah 94h 0000hSimultaneous Operation00 = Not Supported, 01 = Supported 4Bh 96h 0000hBurst Mode Type00 = Not Supported, 01 = Supported 4Ch 98h 0000hPage Mode Type00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word PageHardware Data protectionThe command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes as seen in the Command Definitions table. Additionally, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by false system level signals during Vcc power up and power down transitions, or from system noise.Low V CC Write InhibitWhen Vcc is less than V LKO, the device does not accept any write cycles. This protects data during Vcc power up and power down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until Vcc is greater than V LKO. The system must provide the proper signals to the control pins to prevent unintentional writes when Vcc is greater than V LKO. Write Pulse “Glitch” protectionNoise pulses of less than 5 ns (typical) on OE, CE or W E do not initiate a write cycle.Logical InhibitWrite cycles are inhibited by holding any one of OE = VIL, CE = VIH, or W E = VIH. To initiate a write cycle, CE and W E must be a logical zero while OE is a logical one. If CE, W E, and OE are all logical zero (not recommended usage), it will be considered a read.Power-up Write InhibitDuring power-up, the device automatically resets to READ mode and locks out write cycles. Even with CE = V IL, W E = V IL and OE = V IH, the device will not accept commands on the rising edge of W E.COMMAND DEFINITIONSThe operations of the EN29LV160 are selected by one or more commands written into the command register to perform Read/Reset Memory, Read ID, Read Sector Protection, Program, Sector Erase, Chip Erase, Erase Suspend and Erase Resume. Commands are made up of data sequences written at specific addresses via the command register. The sequences for the specified operation are defined in the Command Definitions table (Table 5). Incorrect addresses, incorrect data values or improper sequences will reset the device to Read Mode.Table 9. EN29LV160 Command DefinitionsBus Cycles1stWrite Cycle 2ndWrite Cycle 3rdWrite Cycle4thWrite Cycle5thWrite Cycle6thWrite Cycle Command SequenceC y c l e sAdd DataAdd DataAdd DataAdd DataAdd DataAdd DataRead 1 RA RDReset 1 xxx F0Word555 2AA555000/1007F/1CManufacturerID Byte 4AAA AA55555AAA90000/2007F/1CWord 555 2AA555 x0122C4 Device ID Top Boot Byte 4 AAA AA55555 AAA 90x02 C4Word 555 2AA555 x01 2249Device ID Bottom Boot Byte 4AAA AA55555AAA 90x02 49XX00Word5552AA555(SA)X02XX0100A u t o s e l e c tSector Protect Verify Byte4AAA AA55555AAA90(SA)X0401Word 555 2AA555ProgramByte 4 AAA AA55555 AAAA0 PA PDWord555 2AA555Unlock BypassByte3 AAA AA55555 AAA 20Unlock Bypass Program 2 XXX A0 PA PD Unlock Bypass Reset2 XXX 90 XXX 00 Word555 2AA555 5552AA 555Chip EraseByte 6 AAA AA55555 AAA 80 AAA AA 555 55 AAA 10Word555 2AA555 5552AASector EraseByte6 AAA AA55555 AAA 80 AAA AA 555 55 SA 30Erase Suspend 1 xxx B0 Erase Resume1 xxx 30Address and Data values indicated in hexRA = Read Address: address of the memory location to be read. This is a read cycle. RD = Read Data: data read from location RA during Read operation. This is a read cycle. PA = Program Address: address of the memory location to be programmed. X = Don’t-Care PD = Program Data: data to be programmed at location PASA = Sector Address: address of the Sector to be erased or verified. Address bits A19-A12 uniquely select any Sector.Reading Array DataThe device is automatically set to reading array data after power up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm.Following an Erase Suspend command, Erase Suspend mode is entered. The system can read array data using the standard read timings, with the only difference in that if it reads at an address within erase suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception.The Reset command must be issued to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See next section for details on Reset.Reset CommandWriting the reset command to the device resets the device to reading array data. Address bits are don’t-care for this command.The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete.The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend).If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).Autoselect Command SequenceThe autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. This is an alternative to the method that requires V ID on address bit A9 and is intended for PROM programmers.Two unlock cycles followed by the autoselect command initiate the autoselect command sequence. Autoselect mode is then entered and the system may read at addresses shown in Table 4 any number of times, without needing another command sequence.The system must write the reset command to exit the autoselect mode and return to reading array data. Word / Byte Programming CommandThe device may be programmed by byte or by word, depending on the state of the Byte# Pin. Programming the EN29LV160 is performed by using a four bus-cycle operation (two unlock write cycles followed by the Program Setup command and Program Data Write cycle). When the program command is executed, no additional CPU controls or timings are necessary. An internal timer terminates the program operation automatically. Address is latched on the falling edge of CE or W E, whichever is last; data is latched on the rising edge of CE or W E, whichever is first. Programming status may be checked by sampling data on DQ7 (DATA polling) or on DQ6 (toggle bit). ). When the program operation is successfully completed, the device returns to read mode and the user can read the data programmed to the device at that address. Note that data can not be programmed from a 0 to a 1. Only an erase operation can change a data from 0 to 1. When programming time limit is exceeded, DQ5 will produce a logical “1” and a Reset command can return the device to Read mode.Unlock BypassTo speed up programming operation, the Unlock Bypass Command may be used. Once this feature is activated, the shorter two cycle Unlock Bypass Program command can be used instead of the normal four cycle Program Command to program the device. This mode is exited after issuing the Unlock Bypass Reset Command. The device powers up with this feature disabled.。

MBM29DL162BD-90PFTN资料

• 0.33 µm Process Technology • Simultaneous Read/Write operations (dual bank) Multiple devices available with different bank sizes (Refer to “MBM29DL16XTD/BD Device Bank Divisions Table” in sGENERAL DESCRIPTION) Host system can program or erase in one bank, then immediately and simultaneously read from the other bank Zero latency between read and write operations Read-while-erase Read-while-program • Single 3.0 V read, program, and erase Minimizes system level power requirements (Continued)
* : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
2
元器件交易网
MBM29DL16XTD/BD-70/90
s GENERAL DESCRIPTION
元器件交易网
FUJITSU SEMICONDUCTOR DATA SHEET
DS05-20874-7E
FLASH MEMORY
CMOS
16M (2M × 8/1M × 16) BIT
MBM29DL16XTD/BD -70/90

MX29LV320CTXEI-90资料

MX29LV320C T/B32M-BIT [4M x 8 / 2M x 16] SINGLE VOLTAGE3V ONLY FLASH MEMORY FEATURESGENERAL FEATURES•4,194,304 x 8 / 2,097,152 x 16 switchable•Sector Structure- 8K-Byte x 8 and 64K-Byte x 63•Extra 64K-Byte sector for security- Features factory locked and identifiable, and cus-tomer lockable•Twenty-Four Sector Groups- Provides sector group protect function to prevent pro-gram or erase operation in the protected sector group - Provides chip unprotect function to allow code chang-ing- Provides temporary sector group unprotect function for code changing in previously protected sector groups •Single Power Supply Operation- 2.7 to 3.6 volt for read, erase, and program opera-tions•Latch-up protected to 250mA from -1V to Vcc + 1V •Low Vcc write inhibit is equal to or less than 1.4V •Compatible with JEDEC standard- Pinout and software compatible to single power sup-ply Flash•Fully compatible with MX29LV320A T/B device PERFORMANCE•High Performance- Fast access time: 70/90ns- Fast program time: 7us/word typical utilizing acceler-ate function- Fast erase time: 0.9s/sector, 35s/chip (typical)•Low Power Consumption- Low active read current: 10mA (typical) at 5MHz- Low standby current: 200nA (typical)•Minimum 100,000 erase/program cycle•10 years data retentionSOFTWARE FEATURES•Erase Suspend/ Erase Resume- Suspends sector erase operation to read data from or program data to another sector which is not being erased•Status Reply- Data# Polling & T oggle bits provide detection of pro-gram and erase operation completion•Support Common Flash Interface (CFI) HARDWARE FEATURES•Ready/Busy# (RY/BY#) Output- Provides a hardware method of detecting program and erase operation completion•Hardware Reset (RESET#) Input- Provides a hardware method to reset the internal state machine to read mode•WP#/ACC input pin- Provides accelerated program capabilityP ACKAGE•48-Pin TSOP•48-Ball CSP•All Pb-free devices are RoHS CompliantGENERAL DESCRIPTIONThe MX29L V320C T/B is a 32-mega bit Flash memory organized as 4M bytes of 8 bits and 2M words of 16 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29LV320C T/B is packaged in 48-pin TSOP and 48-ball CSP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers. The standard MX29L V320C T/B offers access time as fast as 70ns, allowing operation of high-speed micropro-cessors without wait states. To eliminate bus conten-tion, the MX29LV320C T/B has separate chip enable (CE#) and output enable (OE#) controls.MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29LV320C T/B uses a command register to manage this functionality.MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and program mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fieldsfor erase and programming operations produces reliableMX29LV320C T/Bcycling. The MX29LV320C T/B uses a 2.7V to 3.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms.The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamperes on address and data pin from -1V to VCC + 1V.AUTOMATIC PROGRAMMINGThe MX29L V320C T/B is byte/word programmable using the Automatic Programming algorithm. The Automatic Programming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming time at room temperature of the MX29LV320C T/B is less than 36 seconds.AUTOMATIC PROGRAMMING ALGORITHMMXIC's Automatic Programming algorithm require the user to only write program set-up commands (including 2 un-lock write cycle and A0H) and a program command (pro-gram data and address). The device automatically times the programming pulse width, provides the program veri-fication, and counts the number of sequences. A status bit similar to Data# Polling and a status bit toggling be-tween consecutive read cycles, provide feedback to the user as to the status of the programming operation. AUTOMATIC CHIP ERASEThe entire chip is bulk erased using 50 ms erase pulses according to MXIC's Automatic Chip Erase algorithm. T ypical erasure at room temperature is accomplished in less than 35 seconds. The Automatic Erase algorithm automatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device.AUTOMATIC SECTOR ERASEThe MX29LV320C T/B is sector(s) erasable using MXIC's Auto Sector Erase algorithm. Sector erase modes allow sectors of the array to be erased in one erase cycle. The Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase. The timing and verification of electri-cal erase are controlled internally within the device. AUTOMATIC ERASE ALGORITHMMXIC's Automatic Erase algorithm requires the user to write commands to the command register using stand-ard microprocessor write timings. The device will auto-matically pre-program and verify the entire array. Then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecutive read cycles provides feedback to the user as to the sta-tus of the programming operation.Register contents serve as inputs to an internal state-machine which controls the erase and programming cir-cuitry. During write cycles, the command register inter-nally latches address and data needed for the program-ming and erase operations. During a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of WE# .MXIC's Flash technology combines years of EPROM experience to produce the highest levels of quality, relia-bility, and cost effectiveness. The MX29LV320C T/B elec-trically erases all bits simultaneously using Fowler-Nord-heim tunneling. The bytes/words are programmed by using the EPROM programming mechanism of hot elec-tron injection.During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the device stays in read mode. After the state machine has completed its task, it will allow the command regis-ter to respond to its full command set.MX29LV320C T/BMX29LV320C T/BMX29LV320C T/BTable 1.a: MX29LV320CT SECTOR GROUP ARCHITECTURESector Sector Sector Address Sector Size (x8) (x16)Group A20-A12(Kbytes/Kwords)Address Range Address Range1SA0000000xxx64/32000000h-00FFFFh000000h-07FFFh1SA1000001xxx64/32010000h-01FFFFh008000h-0FFFFh1SA2000010xxx64/32020000h-02FFFFh010000h-17FFFh1SA3000011xxx64/32030000h-03FFFFh018000h-01FFFFh2SA4000100xxx64/32040000h-04FFFFh020000h-027FFFh2SA5000101xxx64/32050000h-05FFFFh028000h-02FFFFh2SA6000110xxx64/32060000h-06FFFFh030000h-037FFFh2SA7000111xxx64/32070000h-07FFFFh038000h-03FFFFh3SA8001000xxx64/32080000h-08FFFFh040000h-047FFFh3SA9001001xxx64/32090000h-09FFFFh048000h-04FFFFh3SA10001010xxx64/320A0000h-0AFFFFh050000h-057FFFh3SA11001011xxx64/320B0000h-0BFFFFh058000h-05FFFFh4SA12001100xxx64/320C0000h-0CFFFFh060000h-067FFFh4SA13001101xxx64/320D0000h-0DFFFFh068000h-06FFFFh4SA14001110xxx64/320E0000h-0EFFFFh070000h-077FFFh4SA15001111xxx64/320F0000h-0FFFFFh078000h-07FFFFh5SA16010000xxx64/32100000h-10FFFFh080000h-087FFFh5SA17010001xxx64/32110000h-11FFFFh088000h-08FFFFh5SA18010010xxx64/32120000h-12FFFFh090000h-097FFFh5SA19010011xxx64/32130000h-13FFFFh098000h-09FFFFh6SA20010100xxx64/32140000h-14FFFFh0A0000h-0A7FFFh6SA21010101xxx64/32150000h-15FFFFh0A8000h-0AFFFFh6SA22010110xxx64/32160000h-16FFFFh0B0000h-0B7FFFh6SA23010111xxx64/32170000h-17FFFFh0B8000h-0BFFFFh7SA24011000xxx64/32180000h-18FFFFh0C0000h-0C7FFFh7SA25011001xxx64/32190000h-19FFFFh0C8000h-0CFFFFh7SA26011010xxx64/321A0000h-1AFFFFh0D0000h-0D7FFFh7SA27011011xxx64/321B0000h-1BFFFFh0D8000h-0DFFFFh8SA28011100xxx64/321C0000h-1CFFFFh0E0000h-0E7FFFh8SA29011101xxx64/321D0000h-1DFFFFh0E8000h-0EFFFFh8SA30011110xxx64/321E0000h-1EFFFFh0F0000h-0F7FFFh8SA31011111xxx64/321F0000h-1FFFFFh0F8000h-0FFFFFh9SA32100000xxx64/32200000h-20FFFFh100000h-107FFFh9SA33100001xxx64/32210000h-21FFFFh108000h-10FFFFh9SA34100010xxx64/32220000h-22FFFFh110000h-117FFFh9SA35100011xxx64/32230000h-23FFFFh118000h-11FFFFh10SA36100100xxx64/32240000h-24FFFFh120000h-127FFFh10SA37100101xxx64/32250000h-25FFFFh128000h-12FFFFh10SA38100110xxx64/32260000h-26FFFFh130000h-137FFFh10SA39100111xxx64/32270000h-27FFFFh138000h-13FFFFhMX29LV320C T/BSector Sector Sector Address Sector Size (x8) (x16)Group A20-A12(Kbytes/Kwords)Address Range Address Range11SA40101000xxx64/32280000h-28FFFFh140000h-147FFFh11SA41101001xxx64/32290000h-29FFFFh148000h-14FFFFh11SA42101010xxx64/322A0000h-2AFFFFh150000h-157FFFh11SA43101011xxx64/322B0000h-2BFFFFh158000h-15FFFFh12SA44101100xxx64/322C0000h-2CFFFFh160000h-147FFFh12SA45101101xxx64/322D0000h-2DFFFFh168000h-14FFFFh12SA46101110xxx64/322E0000h-2EFFFFh170000h-177FFFh12SA47101111xxx64/322F0000h-2FFFFFh178000h-17FFFFh13SA48110000xxx64/32300000h-30FFFFh180000h-187FFFh13SA49110001xxx64/32310000h-31FFFFh188000h-18FFFFh13SA50110010xxx64/32320000h-32FFFFh190000h-197FFFh13SA51110011xxx64/32330000h-33FFFFh198000h-19FFFFh14SA52110100xxx64/32340000h-34FFFFh1A0000h-1A7FFFh14SA53110101xxx64/32350000h-35FFFFh1A8000h-1AFFFFh14SA54110110xxx64/32360000h-36FFFFh1B0000h-1B7FFFh14SA55110111xxx64/32370000h-37FFFFh1B8000h-1BFFFFh15SA56111000xxx64/32380000h-38FFFFh1C0000h-1C7FFFh15SA57111001xxx64/32390000h-39FFFFh1C8000h-1CFFFFh15SA58111010xxx64/323A0000h-3AFFFFh1D0000h-1D7FFFh15SA59111011xxx64/323B0000h-3BFFFFh1D8000h-1DFFFFh16SA60111100xxx64/323C0000h-3CFFFFh1E0000h-1E7FFFh16SA61111101xxx64/323D0000h-3DFFFFh1E8000h-1EFFFFh16SA62111110xxx64/323E0000h-3EFFFFh1F0000h-1F7FFFh17SA631111110008/43F0000h-3F1FFFh1F8000h-1F8FFFh18SA641111110018/43F2000h-3F3FFFh1F9000h-1F9FFFh19SA651111110108/43F4000h-3F5FFFh1FA000h-1FAFFFh20SA661111110118/43F6000h-3F7FFFh1FB000h-1FBFFFh21SA671111111008/43F8000h-3F9FFFh1FC000h-1FCFFFh22SA681111111018/43FA000h-3FBFFFh1FD000h-1FDFFFh23SA691111111108/43FC000h-3FDFFFh1FE000h-1FEFFFh24SA701111111118/43FE000h-3FFFFFh1FF000h-1FFFFFh Note:The address range is A20:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH)Top Boot Security Sector AddressesSector Address Sector Size(x8)(x16)A20~A12(Kbytes/Kwords)Address Range Address Range111111xxx64/323F0000h-3FFFFFh1F8000h-1FFFFFhMX29LV320C T/BTable 1.b: MX29L V320CB SECTOR GROUP ARCHITECTURESector Sector Sector Address Sector Size (x8) (x16)Group A20-A12(Kbytes/Kwords)Address Range Address Range1SA00000000008/4000000h-001FFFh000000h-000FFFh2SA10000000018/4002000h-003FFFh001000h-001FFFh3SA20000000108/4004000h-005FFFh002000h-002FFFh4SA30000000118/4006000h-007FFFh003000h-003FFFh5SA40000001008/4008000h-009FFFh004000h-004FFFh6SA50000001018/400A000h-00BFFFh005000h-005FFFh7SA60000001108/400C000h-00DFFFh006000h-006FFFh8SA70000001118/400E000h-00FFFFh007000h-007FFFh9SA8000001xxx64/32010000h-01FFFFh008000h-00FFFFh9SA9000010xxx64/32020000h-02FFFFh010000h-017FFFh9SA10000011xxx64/32030000h-03FFFFh018000h-01FFFFh10SA11000100xxx64/32040000h-04FFFFh020000h-027FFFh10SA12000101xxx64/32050000h-05FFFFh028000h-02FFFFh10SA13000110xxx64/32060000h-06FFFFh030000h-037FFFh10SA14000111xxx64/32070000h-07FFFFh038000h-03FFFFh11SA15001000xxx64/32080000h-08FFFFh040000h-047FFFh11SA16001001xxx64/32090000h-09FFFFh048000h-04FFFFh11SA17001010xxx64/320A0000h-0AFFFFh050000h-057FFFh11SA18001011xxx64/320B0000h-0BFFFFh058000h-05FFFFh12SA19001100xxx64/320C0000h-0CFFFFh060000h-067FFFh12SA20001101xxx64/320D0000h-0DFFFFh068000h-06FFFFh12SA21001110xxx64/320E0000h-0EFFFFh070000h-077FFFh12SA22001111xxx64/320F0000h-0FFFFFh078000h-07FFFFh13SA23010000xxx64/32100000h-10FFFFh080000h-087FFFh13SA24010001xxx64/32110000h-11FFFFh088000h-08FFFFh13SA25010010xxx64/32120000h-12FFFFh090000h-097FFFh13SA26010011xxx64/32130000h-13FFFFh098000h-09FFFFh14SA27010100xxx64/32140000h-14FFFFh0A0000h-0A7FFFh14SA28010101xxx64/32150000h-15FFFFh0A8000h-0AFFFFh14SA29010110xxx64/32160000h-16FFFFh0B0000h-0B7FFFh14SA30010111xxx64/32170000h-17FFFFh0B8000h-0BFFFFh15SA31011000xxx64/32180000h-18FFFFh0C0000h-0C7FFFh15SA32011001xxx64/32190000h-19FFFFh0C8000h-0CFFFFh15SA33011010xxx64/321A0000h-1AFFFFh0D0000h-0D7FFFh15SA34011011xxx64/321B0000h-1BFFFFh0D8000h-0DFFFFh16SA35011100xxx64/321C0000h-1CFFFFh0E0000h-0E7FFFh16SA36011101xxx64/321D0000h-1DFFFFh0E8000h-0EFFFFh16SA37011110xxx64/321E0000h-1EFFFFh0F0000h-0F7FFFh16SA38011111xxx64/321F0000h-1FFFFFh0F8000h-0FFFFFhMX29LV320C T/BSector Sector Sector Address Sector Size (x8) (x16)Group A20-A12(Kbytes/Kwords)Address Range Address Range17SA39100000xxx64/32200000h-20FFFFh100000h-107FFFh17SA40100001xxx64/32210000h-21FFFFh108000h-10FFFFh17SA41100010xxx64/32220000h-22FFFFh110000h-117FFFh17SA42100011xxx64/32230000h-23FFFFh118000h-11FFFFh18SA43100100xxx64/32240000h-24FFFFh120000h-127FFFh18SA44100101xxx64/32250000h-25FFFFh128000h-12FFFFh18SA45100110xxx64/32260000h-26FFFFh130000h-137FFFh18SA46100111xxx64/32270000h-27FFFFh138000h-13FFFFh19SA47101000xxx64/32280000h-28FFFFh140000h-147FFFh19SA48101001xxx64/32290000h-29FFFFh148000h-14FFFFh19SA49101010xxx64/322A0000h-2AFFFFh150000h-157FFFh19SA50101011xxx64/322B0000h-2BFFFFh158000h-15FFFFh20SA51101100xxx64/322C0000h-2CFFFFh160000h-167FFFh20SA52101101xxx64/322D0000h-2DFFFFh168000h-16FFFFh20SA53101110xxx64/322E0000h-2EFFFFh170000h-177FFFh20SA54101111xxx64/322F0000h-2FFFFFh178000h-17FFFFh21SA55110000xxx64/32300000h-30FFFFh180000h-187FFFh21SA56110001xxx64/32310000h-31FFFFh188000h-18FFFFh21SA57110010xxx64/32320000h-32FFFFh190000h-197FFFh21SA58110011xxx64/32330000h-33FFFFh198000h-19FFFFh22SA59110100xxx64/32340000h-34FFFFh1A0000h-1A7FFFh22SA60110101xxx64/32350000h-35FFFFh1A8000h-1AFFFFh22SA61110110xxx64/32360000h-36FFFFh1B0000h-1B7FFFh22SA62110111xxx64/32370000h-37FFFFh1B8000h-1BFFFFh23SA63111000xxx64/32380000h-38FFFFh1C0000h-1C7FFFh23SA64111001xxx64/32390000h-39FFFFh1C8000h-1CFFFFh23SA65111010xxx64/323A0000h-3AFFFFh1D0000h-1D7FFFh23SA66111011xxx64/323B0000h-3BFFFFh1D8000h-1DFFFFh24SA67111100xxx64/323C0000h-3CFFFFh1E0000h-1E7FFFh24SA68111101xxx64/323D0000h-3DFFFFh1E8000h-1EFFFFh24SA69111110xxx64/323E0000h-3EFFFFh1F0000h-1F7FFFh24SA70111111xxx64/323F0000h-3FFFFFh1F8000h-1FFFFFh Note:The address range is A20:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH)Bottom Boot Security Sector AddressesSector Address Sector Size (x8) (x16)A20~A12(Kbytes/Kwords)Address Range Address Range111111xxx64/32000000h-00FFFFh00000h-07FFFhMX29LV320C T/BOperation CE#OE#WE#RE-WP#/Addresses Q0~Q7Q8 ~ Q15SET#A CC (Note 2)Byte#=VIH Byte#=VIL Read L L H H L/H A IN D OUT D OUT Q8-A14Write (Note 1)L H L H Note 3A IN D IN D IN =High-Z Accelerate LHLHV HHA IND IN D INQ15=A-1Program Standby VCC ±XXVCC ±HXHigh-ZHigh-ZHigh-Z0.3V 0.3V Output Disable L H H H L/H X High-Z High-Z High-Z Reset X X X L L/H XHigh-ZHigh-ZHigh-Z Sector Group LHL VIDL/HSector Addresses,DIN, DOUT XXProtect (Note 2)A6=L, A1=H, A0=L Chip Unprotect LHLV IDNote 3Sector Addresses,D IN , D OUT XX(Note 2)A6=H, A1=H, A0=LT emporary Sector XXXV IDNote 3A IND IND INHigh-ZGroup UnprotectLegend:L=Logic LOW=V IL , H=Logic High=V IH , V ID =12.0±0.5V, V HH =11.5-12.5V, X=Don't Care, A IN =Address IN, D IN =Data IN,D OUT =Data OUTNotes:1.When the WP#/ACC pin is at V HH , the device enters the accelerated program mode. See "Accelerated Program Operations" for more information.2.The sector group protect and chip unprotect functions may also be implemented via programming equipment. See the "Sector Group Protection and Chip Unprotection" section.3.If WP#/ACC=V IL , the two outermost boot sectors remain protected. If WP#/ACC=V IH , the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in "Sector/Sector Block Protection and Unprotection". If WP#/ACC=V HH , all sectors will be unprotected.4.DIN or Dout as required by command sequence, data polling, or sector protection algorithm.5.Address are A20:A0 in word mode (BYTE#=V IH ), A20:A-1 in byte mode (BYTE#=V IL ).Table 2. BUS OPERATION--1MX29LV320C T/BBUS OPERATION--2A20A11A8A5Operation CE#OE#WE#to to A9to A6to A1A0Q0-Q7Q8-Q15A12A10A7A2X L X L L C2H X Read Silicon ID L L H X X VIDManufacturer CodeX L X L H A7H22h(word) Read Silicon ID L L H X X VIDMX29L V320CT X (byte)X L X L H A8H22h(word) Read Silicon ID L L H X X VIDMX29L V320CB X (byte)X L X H L01h(1),X Sector Protect L L H SA X VIDVerification or 00hX L X H H99h(2),X Security Sector L L H X X VIDIndicater Bit (Q7) or 19hNotes:1.Code=00h means unprotected, or code=01h protected.2.Code=99 means factory locked, or code=19h not factory locked.MX29LV320C T/BREQUIREMENTS FOR READING ARRAY DATAT o read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should re-main at VIH.The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory con-tent occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid address on the device address inputs produce valid data on the de-vice data outputs. The device remains enabled for read access until the command register contents are altered. WRITE COMMANDS/COMMAND SEQUENCEST o program data to the device or erase sectors of memory , the system must drive WE# and CE# to VIL, and OE# to VIH.An erase operation can erase one sector, multiple sec-tors , or the entire device. Table 1 indicates the address space that each sector occupies. A "sector address" consists of the address bits required to uniquely select a sector. Writing specific address and data commands or sequences into the command register initiates device operations. Table 3 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. Section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation.After the system writes the Automatic Select command sequence, the device enters the Automatic Select mode. The system can then read Automatic Select codes from the internal register (which is separate from the memory array) on Q7-Q0. Standard read cycle timings apply in this mode. Refer to the Automatic Select Mode and Au-tomatic Select Command Sequence section for more in-formation.ICC2 in the DC Characteristics table represents the ac-tive current specification for the write mode. The "AC Characteristics" section contains timing specification table and timing diagrams for write operations.ACCELERATED PROGRAM OPERATIONThe device offers accelerated program operations through the ACC function. If the system asserts VHHon WP#/ ACC pin, the device will provide the fast programming time to user. This function is primarily intended to allow faster manufacturing throughput during production. Re-moving VHHfrom the WP#/ACC pin returns the device to normal operation. Note that the WP#/ACC pin must not be at VHHfor operations other than accelerated program-ming, or device damage may result.STANDBY MODEMX29L V320C T/B can be set into Standby mode with two different approaches. One is using both CE# and RESET# pins and the other one is using RESET pin only. When using both pins of CE# and RESET#, a CMOS Standby mode is achieved with both pins held at VCC ±0.3V. Under this condition, the current consumed is less than 0.2uA (typ.). If both of the CE# and RESET# are held at VIH, but not within the range of VCC ±0.3V, the device will still be in the standby mode, but the standby current will be larger. During Auto Algorithm operation, Vcc active current (ICC2) is required even CE# = "H" until the operation is completed. The device can be read with standard access time (tCE) from either of these standby modes.When using only RESET#, a CMOS standby mode is achieved with RESET# input held at Vss ± 0.3V, Under this condition the current is consumed less than 1uA (typ.). Once the RESET# pin is taken high, the device is back to active without recovery delay.In the standby mode the outputs are in the high imped-ance state, independent of the OE# input.MX29L V320C T/B is capable to provide the Automatic Standby Mode to restrain power consumption during read-out of data. This mode can be used effectively with an application requested low power consumption such as handy terminals.To active this mode, MX29LV320C T/B automatically switch themselves to low power mode when MX29L V320C T/B addresses remain stable during ac-cess time of tACC+30ns. It is not necessary to control CE#, WE#, and OE# on the mode. Under the mode, the current consumed is typically 0.2uA (CMOS level).MX29LV320C T/BOUTPUT DISABLEWith the OE# input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins to be in a high impedance state.RESET# OPERATIONThe RESET# pin provides a hardware method of reset-ting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write com-mands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrityCurrent is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3V, the standby current will be greater.The RESET# pin may be tied to system reset circuitry.A system reset would that also reset the Flash memory, enabling the system to read the boot-up firm-ware from the Flash memory.If RESET# is asserted during a program or erase opera-tion, the RY/BY# pin remains a "0" (busy) until the inter-nal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset op-eration is complete. If RESET# is asserted when a pro-gram or erase operation is not executing (RY/BY# pin is "1"), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH.Refer to the AC Characteristics tables for RESET# pa-rameters and to Figure 14 for the timing diagram. SECTOR GROUP PROTECT OPERATIONThe MX29L V320C T/B features hardware sector group protection. This feature will disable both program and erase operations for these sector group protected. Sec-tor protection can be implemented via two methods.The primary method requires VID on the RESET# only. This method can be implemented either in-system or via programming equipment. This method uses standard mi-croprocessor bus cycle timing. Refer to Figure 13 for tim-ing diagram and Figure 14 illustrates the algorithm for the sector group protection operation.The alternate method intended only for programming equipment, must force VID on address pin A9 and con-trol pin OE#, (suggest VID = 12V) A6 = VIL and CE# = VIL(see Table 2). Programming of the protection circuitry begins on the falling edge of the WE# pulse and is termi-nated on the rising edge. Contact MXIC for details.T o verify programming of the protection circuitry, the pro-gramming equipment must force VIDon address pin A9 ( with CE# and OE# at VIL and WE# at VIH). When A1=1, it will produce a logical "1" code at device output Q0 for a protected sector. Otherwise the device will produce 00H for the unprotected sector. In this mode, the addresses, except for A1, are don't care. Address locations with A1= VIL are reserved to read manufacturer and device codes.(Read Silicon ID)It is also possible to determine if the group is protected in the system by writing a Read Silicon ID command. Performing a read operation with A1=VIH, it will produce a logical "1" at Q0 for the protected sector.CHIP UNPROTECT OPERATIONThe MX29L V320C T/B also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code. It is recommended to protect all sectors before activating chip unprotect mode.The primary method requires VID on the RESET# only. This method can be implemented either in-system or via programming equipment. This method uses standard microprocessor bus cycle timing. Refer to Figure 13 for timing diagram and Figure 14 illustrates the algorithm for the sector group protection operation.The alternate method intended only for programming equipment, must force VID on address pin A9 and con-trol pin OE#, (suggest VID = 12V) A6 = VIL and CE# = VIL(see Table 2). Programming of the protection circuitry begins on the falling edge of the WE# pulse and is termi-nated on the rising edge. Contact MXIC for details.MX29LV320C T/BIt is also possible to determine if the chip is unprotected in the system by writing the Read Silicon ID command.Performing a read operation with A1=VIH, it will produce 00H at data outputs(Q0-Q7) for an unprotected sector. It is noted that all sectors are unprotected after the chip unprotect algorithm is completed.TEMPORARY SECTOR GROUP UNPROTECT OPERA-TIONThis feature allows temporary unprotection of previously protected sector to change data in-system. The Tempo-rary Sector Unprotect mode is activated by setting the RESET# pin to V ID (11.5V-12.5V). During this mode, for-merly protected sectors can be programmed or erased as un-protected sector. Once V ID is remove from the RESET# pin, all the previously protected sectors are pro-tected again.WRITE PROTECT (WP#)The write protect function provides a hardware method to protect boot sectors without using V ID .If the system asserts VIL on the WP#/ACC pin, the de-vice disables program and erase functions in the two "out-ermost" 8 Kbyte boot sectors independently of whether those sectors were protected or unprotected using the method described in Sector/Sector Group Protection and Chip Unprotection". The two outermost 8 Kbyte boot sec-tors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-configured device.If the system asserts VIH on the WP#/ACC pin, the de-vice reverts to whether the two outermost 8K Byte boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two sectors depends on whether they were last protected or unpro-tected using the method described in "Sector/Sector Group Protection and Chip Unprotection".Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result.AUTOMATIC SELECT OPERATIONFlash memories are intended for use in applications where the local CPU alters memory contents. As such, manu-facturer and device codes must be accessible while the device resides in the target system. PROM program-mers typically access signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not generally desired system design prac-tice.MX29L V320C T/B provides hardware method to access the Automatic Select operation. This method requires V ID on A9 pin, VIL on CE#, OE#, A6, and A1 pins. When applying VIL on A0 pin, the device will output MXIC's manufacture code of C2H. When applying VIH on A0 pin,the device will output MX29LV320C T/B device code of 22A7h and 22A8h.VERIFY SECTOR GROUP PROTECT ST ATUS OPERA-TIONMX29L V320C T/B provides hardware method for sector group protect status verify. This method requires V ID on A9 pin, VIH on WE# and A1 pins, VIL on CE#, OE#, A6,and A0 pins, and sector address on A12 to A20 pins.When the identified sector is protected, the device will output 01H. When the identified sector is not protect, the device will output 00H.SECURITY SECTOR FLASH MEMORY REGION The Security Sector (Security Sector) feature provides a Flash memory region that enables permanent part iden-tification through an Electronic Serial Number (ESN). The Security Sector is 64 Kbytes (32 Kwords) in length, and uses a Security Sector Indicator Bit (Q7) to indicate whether or not the Security Sector is locked when shipped from the factory. This bit is per-manently set at the fac-tory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field.MXIC offers the device with the Security Sector either factory locked or customer lockable. The factory-locked version is always protected when shipped from the fac-tory, and has the Security on Silicon Sector (Security Sector) Indicator Bit permanently set to a "1". The cus-tomer-lockable version is shipped with the unprotected,allowing customers to utilize the that sector in any man-ner they choose. The customer-lockable version has the Security on Silicon Sector (Security Sector) Indicator Bit permanently set to a "0". Thus, the Security Sector Indi-cator Bit prevents customer-lockable devices from being。