IEEE1149.1
边界扫描测试技术
IEEE1149.1-1990标准，要求在集成电路中加入边界扫描电路，在板级测试时，可以在主控器的控制下，构成一条在集成电路边界绕行的移位寄存器链，对板内集成电路的所有引脚进行扫描，通过将测试数据串行输入到该寄存器链的方法，检查发现PCB上的器件焊接故障和板内连接故障。
IEEE1149.1定义了边界扫描器件的四线测试访问端口（TAP）：TDI、TDO、TCK、TMS，常称为JTAG接口。
TDI（测试数据输入）、TDO（测试数据输出）、TCK（测试时钟）、TMS （测试模式选择）。
TAP控制器支持的几种测试模式：外测试，内测时，运行测试等等。
具有边界扫描功能器件的每一个引脚都与一个串行移位寄存器（SSR）的单元相接，称为边界扫描单元。
边界扫描单元连在一起构成一个移位寄存器链，用于控制和检测器件引脚。
IEEE1149.1标准测试结构：TAP、TAP控制器、指令寄存器和数据寄存器。
TAP控制器由TCK和TMS控制。
在测试逻辑内部，一系列边界扫描指令寄存器以及解码逻辑处于TAP控制器控制之下，并将TDI信号经过可控的延迟之后从TDO输出。
指令寄存器用于设置数据寄存器(Data Register)的工作模式。
有两种数据寄存器必须存在，一是旁路寄存器（Bypass Register），而是边界寄存器(Boundary Register)。
TAP控制器：包含16个状态的有限状态机，由TCK上升沿采样的TMS状态来控制。
指令寄存器：指令寄存器由串行移位寄存器和并行锁存寄存器组成，长度等于器件边界扫描测试指令的长度。
指令寄存器的行为由TAP控制器的状态决定，根据移入指令的内容将某一数据寄存器连接到TDI和TDO之间。
在进行测试操作时，测试指令首先经TDI移入指令寄存器，然后送入指令锁存器，最后TAP控制器将锁存器中的指令译码后，配合其输出信号来控制其它扫描逻辑。
数据寄存器：1.旁路寄存器不需要并行锁存寄存器，且长度只由1位。
基于IEEE1149.1标准的通用测试机的设计与实现
１ 引言
在现代 电子应用 系统 中 ，随着超 大规模集成
电路 （ Ｌ Ｉ、表 面 安装 器 件 （ ＭＤ） 多芯 片 组 Ｖ Ｓ） Ｓ 、 件 （ Ｍ） ＭＣ 、多层 电路 板 （ Ｃ ＭＰ Ｂ）的发展 ，器 件
不仅可以对 电路进行互连测试 、总线测试 、上拉／ 下拉 电阻测试 、簇测试，还可 以对 Ｆ Ａ Ｈ、Ｃ Ｌ ＬＳ ＰＤ 或 Ｆ Ｇ 等可编程器件进行在线编程。止是由于 ＰＡ
Ｄｅ ｉ ｎ ａ ｄ Ｒｅ ｌ ａ ｉ ｎ ｏ ｅ ｅ ａ ｓｅ ｓ ｄ ｏ ｓｇ ｎ ａ ｉ ｔｏ ｆＧ ｎ ｒ ｌ ｚ Ｔｅ ｔ ｒＢａ ｅ ｎ
Ｉ ＥＥＥ１ ４ ． ｔ ｎ ａ ｄ ９ １Ｓ ａ ｄ ｒ １
Ｚ ＨＯＮＧ ， Ｍ Ｅ Ｂｏ ＮＧ ｔ ｉｎ ｃ ｎ ｅ Ｓｈ ｏ ｏ Ｉｓｕ ｎ ｔ ｉ ｃ ＆Ｏ ｔ－ ｌ ｔ ｎｃ ｎ ｉｅｒ ｇ ＵＡ ｒ ａｏ Ｓ ｅ ｐｏＥｅ ｒ ｉｓ ｇｎｅｉ ，Ｂ Ａ，Ｂ ｉｎ ０ ８ ，Ｃ ｉａ ｃｏ Ｅ ｎ ｅ ｉｇ１ ０ ３ ｈ ） ｊ ０ ｎ
Ａｂ ｔ ａ ｔ Ｆ ｒｓ ｌ ｉ ｇ ｔ ｅ ｔｓ ｒ ｂ ｅ ｆｃｒ ｕ ｔ ｎ ｂ ａ ｄ ｓ ｇ ｒｓ ｓｅ ｓａ ｅ ｈ ｅ ｉ ｃ ｅ ｆｇ ｎ ｒ ｌ ｓｒ ｃ： ｏ ｏ ｖ ｎ ｈ ｅ ｔｐ ｏ ｌｍｓ ｏ ｉｃ ｉｓｏ ｏ ｒ －ｔ ｅ ｏ ｙ ｔｍ－ｔｇ ，ｔ ｅ ｄ ｓｇｎ ｓ ｈ ｍｅ ｏ ｅ ｅ ａ ａ ｔｓｅ ａ ｅ ｎ Ｉ ｅ ｔｒｂ ｓ ｄｏ ＥＥＥ ４ ． ｔｎ ａ ｄ ｉ ｒ ｓ ｎ ｅ ｎｔ ｉ ａ ｅ ． ｅｔ ｓｅ ａ ｅ ｌ ｅｃｒ ｕｔ ’ ｎ ｌ ｅａ ｄｏ －ｉｅｔ ｓｓ １ ９ １ｓ ｄ ｓｐ ｅ ｅ ｔｄ ｉ ｈ ｓｐ ｐ ｒ Ｔｈ ｔｒｃ ｎｒ ａ ｉ ｉｃ ｉｓ ｏ －ｉ ｎ ｆ ｌｎ ｅ ｔ ． １ ａ ｒ ｅ ｚ ｎ Ｉ ｄ ｉ ｏ ， ｙ ｕ ｉ ｇ ａ ｍｂ ｄ ｅ ｅ ｈ ｏｌｇ ，ｓ ｃ ｓＤＳＰ ＰＧＡ ｔ ， ｈ ｅ ｔｒｗｉｌ ａ ｅｔ ｅ ｆ ａｕ ｅ ｍａ ｌｓｚ ， ｎ ａ ｄｔ ｎ ｂ ｓｎ ｎ ｅ ｅ ｄ ｄ ｔｃ ｎ ｏ ｙ ｕ ｈ ａ ｉ ，Ｆ ｅｃ ｔ ｅ ｔｓｅ ｌ ｈ ｖ ｈ ｅ ｔｒ ｓｏｆｓ ｌ ｉｅ － ｌ ｗ－ ｏ ｔ ｇ ｎ ｒ ｌｐ ｒ ｏ ｅａ ｄ ｅ ｓ － ｍｂ ｄ ｎ ． ｏ ｃ ｓ， ｅ ｅ ａ－ ｕ ｐ ｓ ｎ ａ ｙ ｅ ｅ ｍｅ ｔ Ｋｅ ｒ ： ｓｅ ； ｅ ｅ ａ－ ｕ ｏ ｅ ｏ －ｉ ｅｔ ｓ； ｆ－ｉｅｔ ｓ； ｏ ｎ ａ ｙ ｓ ａ ＢＩ ｙ ｗｏ ｄｓ Ｔｅ ｔｒ ｇ ｎ ｒ ｌｐ ｒ ｓ ； ｎ ｌ ｔ ｏ ｌ ｅ ｔ ｂ ｕ ｄ ｒ －ｃ ｎ； Ｔ ｐ ｎ ｅ ｎ
关于JTAG的一些资料
1. 什么是JtagJTAG(Joint Test Action Group)是一种国际标准测试协议（IEEE 1149.1兼容），主要用于芯片内部测试。
现在多数的高级器件都支持JTAG协议，如DSP、FPGA器件等。
标准的JTAG接口是4线：TMS、 TCK、TDI、TDO，分别为模式选择、时钟、数据输入和数据输出线。
JTAG最初是用来对芯片进行测试的，基本原理是在器件内部定义一个TAP （Test Access Port）通过专用的JTAG测试工具对进行内部节点进行测试。
JTAG 测试允许多个器件通过JTAG接口串联在一起，形成一个JTAG链，能实现对各个器件分别测试。
现在，JTAG接口还常用于实现ISP（In-System rogrammable），对FLASH等器件进行编程。
JTAG编程方式是在线编程，传统生产流程中先对芯片进行预编程现再装到板上因此而改变，简化的流程为先固定器件到电路板上，再用JTAG编程，从而大大加快工程进度。
JTAG接口可对PSD芯片内部的所有部件进行编程2. JTAG的一些说明通常所说的JTAG大致分两类，一类用于测试芯片的电气特性，检测芯片是否有问题；一类用于Debug；一般支持JTAG的CPU内都包含了这两个模块。
一个含有JTAG Debug接口模块的CPU，只要时钟正常，就可以通过JTAG接口访问CPU的内部寄存器和挂在CPU总线上的设备，如FLASH，RAM，SOC（比如4510B，44Box，AT91M系列）内置模块的寄存器，象UART，Timers，GPIO等等的寄存器。
上面说的只是JTAG接口所具备的能力，要使用这些功能，还需要软件的配合，具体实现的功能则由具体的软件决定。
例如下载程序到RAM功能。
了解SOC的都知道，要使用外接的RAM，需要参照SOC DataSheet的寄存器说明，设置RAM的基地址，总线宽度，访问速度等等。
有的SOC则还需要Remap，才能正常工作。
JTAG基本原理
JTAG(Joint Test Action Group，联合测试行动组)是一种国际标准测试协议(IEEE 1149.1兼容)。标准的JTAG接口是4线——TMS、TCK、TDI、TDO，分别为模式选择、时钟、数据输入和数据输出线。
JTAG的主要功能有两种，或者说JTAG主要有两大类：一类用于测试芯片的电气特性，检测芯片是否有问题；另一类用于Debug，对各类芯片以及其外围设备进行调试。一个含有JTAG Debug接口模块的CPU，只要时钟正常，就可以通过JTAG接口访问CPU的内部寄存器、挂在CPU总线上的设备以及内置模块的寄存器。本文主要介绍的是Debug功能。
当芯片处于调试状态时，边界扫描寄存器可以将芯片和外围的输入／输出隔离开来。通过边界扫描寄存器单元，可以实现对芯片输入／输出信号的观察和控制。对于芯片的输入引脚，可以通过与之相连的边界扫描寄存器单元把信号(数据)加载到该引脚中去；对于芯片的输出引脚，也可以通过与之相连的边界扫描寄存器“捕获”该引脚上的输出信号。在正常的运行状态下，边界扫描寄存器对芯片来说是透明的，所以正常的运行不会受到任何影响。这样，边界扫描寄存器提供了一种便捷的方式用于观测和控制所需调试的芯片。另外，芯片输入／输出引脚上的边界扫描(移位)寄存器单元可以相互连接起来，任芯片的周围形成一个边界扫描链(Boundary-Scan Chain)。边界扫描链可以串行地输入和输出，通过相应的时钟信号和控制信号，就可以方便地观察和控制处在调试状态下的芯片。
◇STCK：时钟返回信号，在IEEE 1149.1标准里非强制要求。
◇DBGRQ：目标板上工作状态的控制信号。在IEEE 1149.1标准里没有要求，只是在个别目标板(例如STR710)中会有。
简单地说，PC机对目标板的调试就是通过TAP接口完成对相关数据寄存器(DR)和指令寄存器(IR)的访问。
IEEE-JTAG-1149[1].1-2001
![IEEE-JTAG-1149[1].1-2001](https://img.taocdn.com/s3/m/f4092d0102020740be1e9b29.png)
s
s s
AL 10Sept.-97 1149.1(JTAG)-Tut.I-4
JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory
Standard Test Access Port ...
User Register TDI Bypass Register TMS TCK TAP Controller DR IR Decode Logic Instruction Register TDO
1 unit of cost 10 units of cost 100 units of cost 1,000 units of cost
1997 TI Test Symposium
JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory
Conventional Methods of Test
s s s
Real JTAG Applications For More Information Q&A
(10 minutes) (5 minutes) (10 minutes)
1997 TI Test Symposium
AL 10Sept.-97 1149.1(JTAG)-Tut.I-2
JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory
CORE
s
s
AL 10Sept.-97 1149.1(JTAG)-Tut.I-6
1997 TI Test Symposium
JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory
边界扫描技术和IEEE 1149.1标准
～一
（） ２ 测试 配 或 ｔ Ｂ之间的连线 。 ＇ Ｃ ２边界扫描的硬件结构和 Ｉ Ｅ １９ １ 准 Ｅ Ｅ １４ ． 标 根据 ＩＥ １ 标准 ， Ｅ Ｅ １４ １ ９ 边界扫描设计 的硬 件应 包括以下四个部分 ： （１ １测 存取通道（ Ａ ） ＴＰ ；
（ Ｔ Ｐ控 制 器 ； ２）Ａ
（） ３ 指令寄存器（ｒ ； ｉ） ｔ （） ４ 测试数据寄存器组 （Ｄ ） ＴＲ； 其中测试数 据寄 存 器组 ＇Ｒ又包 括边 缘 扫捕 寄存 器 （ Ｓ ． 旁路 寄存 器 （ Ｙ 和器 件标 志 寄存 器 Ｉ Ｄ ＢＢ 、 ） Ｂ Ｒ） （ Ｒ 。同时还包 括一个或几个专用 的其他寄存器 。 Ｉ ） Ｄ
。
收稿 ｉ ：０ １ ２ ３ ｔ期 ２ ０ —１ —０
维普资讯
边界 扫描技 术和 ＩＥ １９． 标 准 Ｅ Ｅ ｌ４ Ｉ
２ ［ ｏＩ 数 据 ， 也可输 出数据 （） ２ 所有 的寄存器 可连接成一个移位寄存器
（ ｌ ｔ ｎ ｓＥｇ ｅｒ ｇＣ ｌｇ ， ａａ Ｕ ￣ ｒｔ ｏ Ｂ睁 曲晤． ａｊ ｇ ２ １ Ｏ Ｅ ｃ ｏｉ ｎｉ ｅｉ ｏ ｅ Ｎ ｖｌ ｍ ＇ ｓ ｆ ｅｒ ｃ ｎ ｎ ｌｅ ｅｉ ｙ Ｎ ｎｎ ， １ｇ ） ｉ Ｃ
Ａｂａ ｔ ｈｓ ｐ Ｐ ｒｉｔ ｌｅ ｓｔ ｅ ｔ ， ￣ ｏ ｙ ｏ ｍｄ Ｉ ｓ￣ ：Ｔ ｉ ａ ｅ ｒ ｕ ｅ ｈ ｅ ｌ ｌ ｇ ｆ ｎ ｍ： ｃｕ ｙ￣ｍｉａ ｄ Ｉ ｔ １ ９ １ ｓａ ｄ ｒ ｎ ｉｃｓ ｅ ｔ ｕ ＆ｍ ｔ ｕ ｎ ＥＥ ；１ ４ ． ｔｎ ａ ｄ ａ ｄ ｄｓ ｕ ｓｓ ｉ ｆｎ ￣ｎａ ， ｓ ｌ
jtag标准ieee1149.1解析
IEEE1149.1标准是一项用于测试和故障诊断集成电路的重要标准，而JTAG（Joint Test Action Group）是这项标准的主要推动者之一。
本文将对IEEE1149.1标准进行解析，从其定义、原理、应用等多个角度进行分析，帮助读者更好地理解和应用这一标准。
一、 IEEE1149.1标准的定义IEEE1149.1标准，也称为边界扫描标准或JTAG标准，是一项由IEEE 制定的用于测试集成电路的标准。
该标准于1990年发布，已被广泛应用于半导体工业、电子制造业等领域。
通过在芯片内部设置边界扫描链，可以实现对芯片内部连接和状态的测试和调试，从而提高了集成电路的可靠性和稳定性。
二、 IEEE1149.1标准的原理1. 边界扫描链IEEE1149.1标准的核心是边界扫描链（boundary scan ch本人n），通过在集成电路的引脚上添加扫描逻辑，实现了对芯片内部连接和状态的测试。
这种边界扫描链可以将芯片的内部引脚与外部引脚进行连接，从而实现对芯片内部信号的观测和控制。
2. TAP控制器IEEE1149.1标准还引入了TAP（Test Access Port）控制器，用于与边界扫描链进行通信和控制。
TAP控制器可以对边界扫描链进行初始化、数据传输和状态控制，从而实现对集成电路的测试和调试。
三、 IEEE1149.1标准的应用1. 芯片测试IEEE1149.1标准最主要的应用是用于集成电路的测试。
通过在芯片内部设置边界扫描链，可以实现对芯片内部连接和状态的测试，从而发现潜在的故障和缺陷。
2. 芯片调试除了测试功能，IEEE1149.1标准还可以用于集成电路的调试。
通过边界扫描链和TAP控制器，工程师可以对集成电路进行状态观测和信号控制，从而快速定位和分析故障原因。
3. 芯片编程IEEE1149.1标准还可以用于集成电路的编程。
一些可编程逻辑器件（如FPGA）可以通过边界扫描信息口进行编程，实现对逻辑器件内部配置和状态的控制。
ieee1149 JTAG标准
IEEE 1149.1 TestabilityIntroductionDesign for Test(DFT), also known as design for testability, is a process that incorporates rules and techniques in the design of a product to make testing easier.Structured design for test is a system methodology rather than a collection of discrete techniques. This methodology impacts all phases of product's life, from device circuit design through field service. Design for test is used to manage complexity, minimize development time, and reduce manufacturing cost.Testing has two major aspects: control and observation. In order to test any system it is necessary to put the system into a known state, supply known input data (test data), and observe the system to see if it performs as designed and manufactured. If control and observation cannot be carried out, there is no way to know empirically if the system performs in the proper manner.During the normal product development flow, testing (it may be known by different names) takes place at many points during the process. If testing is considered at the chip design level, its benefits can be used at all levels of electronic assembly; from chip through system-level testing. See Figure 1-1.Figure 1-1. Chip Through System-Level TestDesigners usually test various functions to validate their design. Manufacturing and customer groups subject the design to an assortment of unique criteria to see if the concept works in practice. Is it manufacturable? Will it stand up to real-world operating conditions? Will repair be cost efficient? In addition to direct testability considerations, production managers want features designed into the product to help them minimize scrap and manufacturing costs. Good system-testability methodology provides an integrative function throughout the product development cycle and allows materials created during an early phase of development to be reused in later phases. Various chip designers have used this integration feature as a tool to help manage the development of complex products.Testability provides companies with a firmer grasp on the economic and market-window constraints due to product development. One major workstation manufacturer claimed :∙Test program development would have been nearly impossible without scan techniques.∙Chip-level test development time fell from 1 man-year to about 20 hours.∙Board-level test development time fell from multiple man-years to about a week.∙Three months were cut off development time.Overall Rationale for Design for TestManufacturers of state-of-the-art electronic product face a unique set of problems. Although modem circuit density, high device speed, surface-mount packaging, and complex board-interconnected technology have a positive influence on state-of-the-art electronic systems, these factors can adversely affect ability to verify correct design and operation. Increased complexity and lack of physical access to circuitry makes for costly and time-consuming testing using traditional test techniques.Reduced Cost and Higher QualityReacting to this complexity with an eye on the bottom line, manufacturers may opt to perform less rigorous testing. Manufacturers who choose the less rigorous techniques as an expeditious alternative to the expense of full testing gamble their technical credibility in the market place and expose themselves to the high cost of product returns. In today’s global electronics marketplace, a manufacturer who delivers poorly tested products does not remain competitive. The cost for detecting and identifying faults using traditional test methods increases by an order of magnitude as a circuit’s level of complexity increases. These increased costs and development time reduce profit margins, delay product introduction, and reduce time-to-market windows. An increasing number of companies have simultaneously improved their product quality and profit margins by adopting system-level (integrative) design methods. Design for test is one such system-level approach.Benefits Over Standard Test MethodsTime to market is more important than ever before in the high technology marketplace. Companies that can produce quality products with a short product development cycle-time have a competitive advantage. Designing testability into a system can play an important role in introducing a new high-technology product with an expected five-year live cycle to market on time. Table 1-1 shows various product development time/budget scenarios and the resulting project profitability.Product A Product B Product C To Market: on time on time 6 month later Budget: on 50% over onProfit Over 5 Years: 100% 96% 66%Table 1-1. High-Technology Products ScenariosAdding testability to a product increases design time and costs while reducing cost of design validation, manufacturing test, and system maintenance.The system design phase of product development represents only 15% of product’s total life-cycle costs. However, the system design phase has a 70% impact on product‘s operation and support costs over the product’s total life. (Source: Mitr e Corporation, 1987 Government Microcircuit Applications Conference)The majority of faults found on boards, such a solder joints (shorts and opens), components (wrong device, missing device, wrong orientation, wire bond failure, and stuck pins), etch integrity, and connector faults, make up over 95% of failures found. Structured technique such as boundary-scan technique allows for pins-out testing to detect this failures easily. (Source: Teradyne)The additional costs of designing testability into a system during the system design phase can be more than made up over the product’s total life.Design cycle times have shortened significantly over the years while test program development time has increased, necessitating that companies adopt structured or repeatable methodologies. Table 1-2 documents the increase in test program development in time as a test requirements increase.1977 - 1980 3 - 6 months1981 - 1983 6 - 12 months1984 - 1986 9 - 18 months1987 - 1990 12 - 24 monthsTable 1-2. Time of Develop Test Programs (in Man Months)Standard Test Solutions Versus Proprietary SolutionsEmbedded test, emulation, and maintenance circuitry are well defined and understood within the test community. Previously, the lack of standards caused these structures to be implemented in an ad hoc and proprietary manner. Since proprietary solutions are usually more expensive and labor intensive, the added costs further limited the use of these test circuits. Boundary-scan testing combined with the common test bus interface and test protocol has these benefits:∙Provides a standard and cost effective solution to traditional test problems∙Opens up new applicationsThe ability of reuse previously developed test data and to use less costly test equipment means that this approach yields products that are less expensive to manufacture. An Industry Standard - IEEE 1149.1 - 1990 (JTAG)In 1985, an ad hoc group composed of key electronic manufacturers formed a group called JTAG (Joined Test Action Group). JTAG had over 200 members around the world including major electronics and semiconductors manufacturers. This group met to establish solution to the problems of board test and to promote a solution as an industry standard. The solution, which became IEEE Std. 1149.1-1990. IEEE Standard Test Access Port and Boundary-Scan Architecture, is the basis for TI testability products. The IEEE Std.1149.1 allows test instructions and data to be serially loaded into device and enables the subsequent test results to be serially read out.Every IEEE 1149.1 - compatible device has four additional pins - two for control an one each for serial test data input and output. To be compatible, a component must have certain basic test features, but the IEEE 1149.1 specification allows designers to add test features to meet their own unique requirements. The specification was adopted as an IEEE standard in February of 1990.Benefits of TestabilityThis chapter explains how designing testability into devices eliminates problems associated with traditional testing and improves quality and efficiency.Traditional TestingTraditional board-level and device-level testing consumes a great deal of time and requires special hardware and complex Automated Test Equipment (ATE) for each type of board or device. This results in increased costs and development time. In addition, extensive testing is necessary for the heightening reliability standards and performance standards in the defence, aerospace, automotive, computer, and communications industries. These extensive tests can delay the market introduction of products, disrupt Just-In-Time (JIT) manufacturing flows, and limit the productivity of standard ATE operations. This creates numerous problems because time to market is more important than ever before in the high-technology marketplace. Companies that produce quality products with a short product-development cycle time have a competitive advantage.Efficient TestingAn innovative approach to the problems inherent with traditional testing is to incorporate design-for-test techniques that allow embedded testing to be performed. For example, data can be scanned in to stimulate internal system nodes while the component or circuit is embedded within the system. During the same scan, the previous condition of each node is scanned out. This saves test time and reduces the number of test vectors needed. Lower Cost for TestingThe additional costs of designing testability into a system during the design phase is more than made up over the products total life. This is accomplished by reducing the test program development time, minimizing fixture complexity, and allowing for the use of lower cost ATE solutions. Another cost benefit is the economy of scale gained by having a standard test approach that spans design, test, manufacture, field repairs, and maintenance. Production Time SavingsBoard-level boundary-scan testing is easily implemented using TI’s line of IEEE 1149.1 testability devices such as:∙Octal and Widebus™ buffers∙ASICs and FPGAs∙DSPs, microprocessors, and controllersThese IEEE1149.1-compliant devices are included in board design with little modification to existing circuitry. Embedded testability greatly reduces the need for other test points on the board and offers these advantages:∙Greatly simplified test fixtures∙Reduced fixture construction time∙Sophisticated build-in test and debug operationsMany ICs on boards may be tested together using the serial IEEE 1149.1test bus under the control of ASSET software.Easier Board-Level IsolationFault isolation on a printed circuit board can be greatly improved by electronically isolating suspect areas using boundary-scannable devices. The IEEE1149.1 test bus controls boundary-scannable devices to place them in EXTEST for pins-out testing. This effectively partitions offer isolates circuitry for separate testing. Partitioning the system using IEEE 1149.1-compliant devices reduces the number of patterns required for testing each circuit area. See Figure 2-1 for an example of a design than can be partitioned.Simple Access to CircuitsHighly integrated, modern, multi-layer systems or ICs with fine-pitch pins are virtually impossible to access using manual probes or ATE. Some boards require extensive fixturing or even some redesign before they can be tested effectively. TI’s testability devices with boundary-scan architecture eliminate physical access problems. These parts provide the designer with testability for the most complex and hard-to-access circuits, and add controllability of test circuits. In addition, a designer can easily observe and control internal device functions.Figure 2-1. Boundary-Scan Testing Using the IEEE 1149.1 BusBoundary-Scan Architecture and IEEE Std 1149.1Boundary scan is a special type of scan path with a register added at every I/0 pin on a device. Although this requires the addition of a special test latch on some pins, the technique offers several important benefits. The most obvious benefit offered by the boundary-scan technique is allowing fault isolation at the component level. Such an isolation requirement is common in telecommunications switching environments where prompt field repair is critical.A major problem driving the development of the IEEE 1149.1 boundary-scan standard is the adverse effect of surface-mount technology. The inclusion of a boundary-scan path in surface-mount components, in many cases, affords the only way to perform continuity tests between devices. By placing a known value on an output buffer of one device and observing the input buffer of another interconnected device, it is easy to see if the Printed Wiring Boards (PWB) net is electrically connected. Failure of this simple test indicates broken circuit traces, cold solder joints, solder bridges, or Electrostatic Discharge (ESD) induced failures in an IC buffer-all common problems on PWBs.A less obvious advantage of the boundary-scan methodology is the ability to apply predeveloped functional pattern sets to the I/0 pins of the IC by way of the scan path. IC manufacturers and ASIC developers create functional pattern sets for DC test purposes. Subsets of these patterns can be reused for in-circuit functional IC testing. Reusing existing patterns in the development of system diagnostics can save large amounts of development resources, especially if many of the ICs in a system have embedded boundary-scan paths.The IEEE 1149.1 standard is a common protocol and boundary-scan architecture developed into an industrial standard after thousands of man hours of cooperative development by approximately 200 major international electronics firms. Early contributors in the development of the IEEE 1149.1 standard were AT&T, DEC, Ericsson, IBM, Nixdorf, Philips, Siemens, and Texas Instruments. These companies recognized that only a nonproprietary architecture would encourage companies to offer the compatible integrated circuits, test equipment, and CAD software needed to bring product development, manufacturing, and test costs under control in today's competitive electronics marketplace. Many people believe that boundary-scan architecture will do for development, manufacturing, and test what the RS-232C standard did for computer peripherals.Boundary-Scan OverviewBoundary scan is the application of a scan path at the boundary (I/O) of ICs to provide controllability and observability access via scan operations. In Figure 3-1, an IC is shown with an application-logic section and related input and output, and a boundary-scan path consisting of a series of boundary-scan cells (BSC), in this case one BSC per IC function pin.Figure 3-1. Boundary-Scan ExampleThe BSCs are interconnected to form a scan path between the host IC's Test Data Input (TDI) pin and Test Data Output (TDO) pin. During normal IC operation, input and output signals pass freely through each BSC, from the Normal Data Input (NDI), to the Normal Data Output (NDO). However, when the boundary-test mode is entered, the IC's boundary is controlled in such a way that test stimulus can be shifted in and applied from each BSC output (NDO), and test response can be captured at each BSC input (NDI) and shifted out for inspection. External testing of wiring interconnects and neighboring ICs on a board assembly is accomplished by applying test stimulus from the output BSCs and capturing test response at the input BSCs. As an option, internal testing of the application logic can be accomplished by applying test stimulus from the input BSCs and capturing test response at the output BSCs. The implementation of a scan path at the boundary of IC designs provides an embedded testing capability that can overcome the physical access problems in current and future board designs.Test Interface and Boundary-Scan ArchitectureThe IEEE 1149.1 architecture is shown in Figure 3-2. The architecture consists of an Instruction Register, a Bypass Register, a Boundary-Scan Register (highlighted), an optional User Data Register, and a test interface referred to as a Test Access Port (TAP). In Figure 3-2, the Boundary-Scan Register (BSR), a serially accessed Data Register comprised of a series of boundary-scan cells (BSCs), is shown at the input and output boundary of the IC.The Instruction Register and Data Registers are separate scan paths arranged between the primary Test Data Input (TDI) pin and primary Test Data Output (TDO) pin. This architecture allows the TAP to select and shift data through one of the two types of scan paths, instruction or data, without accessing the other scan path.Figure 3-2. Boundary-Scan ArchitectureTest Access Port and OperationThe TAP is controlled by the Test Clock (TCK) and Test Mode Select (TMS) inputs. These two inputs determine whether an Instruction Register scan or Data Register scan is performed. The TAP consists of a small controller design, driven by the TCK input, which responds to the TMS input as shown in the state diagram in Figure 3-3. The IEEE 1149.1 testbus uses both clock edges of TCK. TMS and TDI are sampled on the rising edge of TCK, while TDO changes on the falling edge of TCK.Figure 3-3. TAP State DiagramThe main state diagram consists of six steady states; Test-Logic-Reset, Run-Test/Idle, Shift-DR, Pause-DR, Shift-IR, and Pause-IR. A unique feature of this protocol is that only one steady state exists for the condition when TMS is set high: the Test-Logic-Reset state. This means that a reset of the test logic can be achieved within five TCKs or less by setting the TMS input high.At power up or during normal operation of the host IC, the TAP is forced into the Test-Logic-Reset state by driving TMS high and applying five or more TCKs. In this state, the TAP issues a reset signal that places all test logic in a condition that does not impede normal operation of the host IC. When test access is required, a protocol is applied via the TMS and TCK inputs, causing the TAP to exit the Test-Logic-Reset state and move through the appropriate states. From the Run-Test/Idle state, an Instruction Register scan or a Data Register scan can be issued to transition the TAP through the appropriate states shown in Figure 3-3.The states of the Data and Instruction Register scan blocks are mirror images of each other adding symmetry to the protocol sequences. The first action that occurs when either block is entered is a capture operation. For the Data Registers, the Capture-DR state is used to capture (or parallel load) the data into the selected serial data path. If the BSR is the selected Data Register, the normal data inputs (NDI) is captured during this state. In the Instruction Register, the Capture-IR state is used to capture status information into the Instruction Register.From the Capture state, the TAP transitions to either the Shift or Exit1 state. Normally the Shift state follows the Capture state so that test data or status information can be shifted out for inspection and new data shifted in. Following the Shift state, the TAP either returns to the Run-Test/Idle state via the Exit1 and Update states or enters the Pause state via Exit1. The reason for entering the Pause state is to temporarily suspend the shifting of data through either the Data or Instruction Register while a required operation, such as refilling a tester memory buffer, is performed. From the Pause state shifting can resume by re-entering the Shift state via the Exit2 state or terminated by entering the Run-Test/Idle state via the Exit2 and Update states.Upon entering the Data or Instruction Register scan blocks, shadow latches in the selected scan path are forced to hold their present state during the Capture and Shift operations. The data being shifted into the selected scan path is not output through the shadow latch until the TAP enters the Update-DR or Update-IR state. The Update state causes the shadow latches to update (or parallel load) with the new data that has been shifted into the selected scan path.In Figure 3-4, the TAP control output signals are shown along with the Instruction and Data Register interconnects.Figure 3-4. TAP Output Control Interconnect DiagramIEEE 1149.1 RegistersThis section contains descriptions of the required and optional registers specified in IEEE Std 1149.1-1990.Instruction Register (Required)The Instruction Register is responsible for providing the address and control signals required to access a particular Data Register in the scan path. The Instruction Register is accessed when the TAP receives an Instruction Register scan protocol. During an Instruction Register scan operation the SELECT output from the TAP (Figure 3-4) selects the output ofthe Instruction Register to drive the TDO pin. A general Instruction Register architecture is shown in Figure 3-5.Figure 3-5. General Instruction Register ArchitectureThe Instruction Register consists of an instruction shift register and an instruction shadow latch. The instruction shift register (Figure 3-5) consists of a series of shift register bits arranged to form a single scan path between the TDI and TDO pins of the host IC. During Instruction Register scan operations, the TAP exerts control via the Instruction Register shift enable (SHIFTIR) and Instruction Register Clock (CLOCKIR) signals to cause the instruction shift register to preload status information and shift data from TDI to TDO. Both the preload and shift operations occur on the rising edge of TCK; however, the data shifted out from the host IC from TDO occurs on the falling edge of TCK. The status inputs are user-defined observability inputs, except for the two least significant bits, which are always 01 for scan-path testing purposes. (The Instruction Register has a minimum length of two bits.) When activated, the RESET* input sets the instruction shift register to be set to all ones. This forces the device into the functional mode and selects the Bypass Register (or the Device Identification Register if one is present).The instruction shadow register (Figure 3-5) consists of a series of latches, one latch for each instruction shift register bit. During an Instruction Register scan operation, the latches remain in their present state. At the end of the Instruction Register scan operation, the Instruction Register update (UPDATEIR) input updates the latches with the new instruction installed in the instruction shift register. When activated, the RESET* input sets the latches to all ones.Data RegistersThe IEEE 1149.1 standard requires two Data Registers; Boundary-Scan Register and Bypass Register, with a third, optional, Device Identification Register. Additional user-defined Data Registers may be included. The Data Registers are arranged in parallel from the primary TDI input to the primary TDO output. The Instruction Register supplies the address that allows one of the Data Registers to be accessed during a Data Register scan operation. During a Data Register scan operation, the addressed scan register receives TAP control via the Data Register shift enable (SHIFTDR) and Data Register clock (CLOCKDR) inputs to preload test response and shift data from TDI to TDO. During a Data Register scan operation, the SELECT output from the TAP (Figure 3-4) selects the output of the Data Register to drivethe TDO pin. When one scan path in the Data Register is being accessed, all other scan paths remain in their present state.Figure 3-6. Test Data Register ArchitectureBoundary-Scan Register- The Boundary-Scan Register (BSR) consists of a series of boundary-scan cells (BSCs) arranged to form a scan path around the boundary of the host IC. The BSCs provide the controllability and observability features required to perform boundary-scan testing as described in the Boundary-Scan Overview section of this chapter. Shadow latches in the BSCs, driving the NDO outputs remain in their present state during a Data Register scan operation. At the end of a Data Register scan operation, the Data Register update (UPDATEDR) input updates the shadow latches with the new boundary test pattern to be applied from the NDO outputs of the BSCs.Figure 3-7 shows a conceptual view of a Control-and-Observe BSC.Figure 3-7. Conceptual View of a Control-and-Observe BSCBypass Register (Required) - The Bypass Register consists of a single scan register bit. When selected, the Bypass Register provides a single bit scan path between TDI and TDO. The Bypass Register allows abbreviating the scan path through devices that are not involved in the test. The Bypass Register is selected when the Instruction Register is loaded witha pattern of all ones to satisfy the IEEE 1149.1 Bypass instruction requirement.Device Identification Register (Optional) - The Device Identification Register is an optional register defined by IEEE 1149.1, to identify the device's manufacturer, part number, revision, and other device-specific information. Figure 3-8 shows the bit assignments defined for the Device Identification Register. These bits can be scanned out of the Identification Register after being selected.Figure 3-8. Structure of the Device Identification RegisterAlthough the Device Identification Register is optional, IEEE 1149.1 specification has dedicated an instruction to select this register. The Device Identification Register is selected when the Instruction Register is loaded with the IDCODE instruction, which is defined by the vendor.Manufacturer's identification codes (Bit1 through Bit11) are assigned, maintained, and updated by the EIA/JEDEC office. Any company can be added to the JEDEC Standard Manufacturer's Identification Code (Publication JEP106) by request to the JEDEC office at 202-457-4973.IEEE 1149.1 Required InstructionsThe IEEE 1149.1 standard defines nine test instructions. Of the nine instructions, three are required and six are optional. The following subsections contain brief descriptions of each required test instruction.BYPASS InstructionThe required BYPASS instruction allows the IC to remain in a functional mode and selects the Bypass Register to be connected between TDI and TDO. The BYPASS instruction allows serial data to be transferred through the IC from TDI to TDO without affecting the operation of the IC. The bit code of this instruction is defined to be all ones by the IEEE 1149.1 standard.SAMPLE/PRELOAD InstructionThe required SAMPLE/PRELOAD instruction allows the IC to remain in its functional mode and selects the Boundary-Scan Register to be connected between TDI and TDO. During this instruction, the Boundary-Scan Register can be accessed via a data scan operation, to take a sample of the functional data entering and leaving the IC. This instruction is also used to preload test data into the Boundary-Scan Register prior to loading an EXTEST instruction. The bit code for this instruction is defined by the user.EXTEST InstructionThe required EXTEST instruction places the IC into an external boundary test mode and selects the Boundary-Scan Register to be connected between TDI and TDO. During this instruction, the Boundary-Scan Register is accessed to drive test data off-chip via the boundary outputs and receive test data off-chip via the boundary inputs. The bit code of this instruction is defined by the 1149.1 standard to be all zeros.IEEE 1149.1 Optional InstructionsThe following subsections contain brief descriptions of the optional IEEE 1149.1 instructions.INTEST InstructionThe optional INTEST instruction places the IC in an internal boundary test mode and selects the Boundary-Scan Register to be connected between TDI and TDO. During this instruction, the Boundary-Scan Register is accessed to drive test data on-chip via the boundary inputs and receive test data on-chip via the boundary outputs. The bit code of this instruction is defined by the user.RUNBIST InstructionThe optional RUNBIST instruction places the IC into a self-test mode, enables a comprehensive self-test of the IC's core logic, and selects a user-specified Data Register to be connected between TDI and TDO. During this instruction, the boundary outputs are controlled so that they cannot interfere with neighboring ICs during the RUNBIST operation. Also, the boundary inputs are controlled so that external signals cannot interfere with the RUNBIST operation. The bit code of this instruction is defined by the user.CLAMP InstructionThe optional CLAMP instruction sets the outputs of an IC to logic levels determined by the contents of the Boundary-Scan Register and selects the Bypass Register to be connected between TDI and TDO. Before you load this instruction, you can preset the contents of the Boundary-Scan Register with a SAMPLE/PRELOAD instruction. During this instruction, data can be shifted through the Bypass Register from TDI to TDO without affecting the condition of the outputs. The bit code of this instruction is defined by the IC designer.HIGHZ InstructionThe optional HIGHZ instruction sets the three-state outputs of an IC to a disabled state and selects the Bypass Register to be connected between TDI and TDO. During this instruction, data can be shifted through the Bypass Register from TDI to TDO without affecting the condition of the IC outputs. The bit code of this instruction is defined by the IC designer.IDCODE InstructionThe optional IDCODE instruction allows the IC to remain in its functional mode and selects an optional Device Identification Register to be connected between TDI and TDO. The Identification Register (see Figure 3-8) is a 32-bit shift register containing information regarding the IC manufacturer, device type, and version code. Accessing the Identification Register does not interfere with the operation of the IC. Also, access to the Identification Register should be immediately available, via a TAP data scan operation, after power-up of the IC or after the TAP has been reset using the optional TRST* pin or by issuing a Test-Logic-Reset instruction. The bit code of this instruction is defined by the IC device designer. USERCODE InstructionThe optional USERCODE instruction allows the IC to remain in its functional mode and selects a User Data Register to be connected between TDI and TDO. The User Data。
JATG_联合测试行为组织_接口协议
JATG 简介A. JTAG简述JTAG - Joint Test Active Group 是一种国际标准测试协议(IEEE1149.1兼容) , 主要用于芯片内部测试. 现在多数高级器件都支持JTAG协议,如DSP,FPGA器件等.标准的JTAG接口是4线: TMS - TCK - TDI -TDO , 分别为模式选择,时钟,数据输入,数据输出线 .JTAG最初是用来对芯片进行测试的，JTAG的基本原理是在器件内部定义了一个TAP(Test Access Port),通过专用的JTAG测试工具对内部节点进行测试. JTAG 测试允许多个器件通过JTAG接口串联在一起,形成一个JTAG链, 能实现对各个器件分别测试. 现在JTAG接口还常用于实现ISP等,对FLASH等器件进行编程. JTAG编程方式是在线编程,传统生产方式中对芯片进行预编程先再装到板子上因此而改变,简化的流程为先固定器件到电路板上,再用JTAG编程,从而大大加快工程进度. JTAG接口可对PSD芯片内部的所有部件进行编程.具有JTAG接口的芯片都有下列引脚定义. TCK : 测试时钟输入 . TDI: 测试数据输入,数据通过TDI输入JTAG口. TDO:测试数据输出，数据通过TDO从JTAG 口输出．TMS:测试模式选择，TMS用来设置JTAG口处于某种特定的测试模式．可选引脚TRST:测试复位，输入引脚，低电平有效. 含有JTAG接口的芯片种类比较多：CPU , DSP ,CPLD等．JTAG内部有一个状态机，称为TAP控制器．TAP控制器的状态机通过TCK和TMS进行状态的改变，实现数据和指令的输入． JTAG标准定义了一个串行的移位寄存器，寄存器的每一个单元分配给IC芯片的相应引脚，每一个独立的单元称为BSC(Boundary-Scan Cell)边界扫描单元．这个串联的BSC在IC内部构成了JTAG回路，所有的BSR(Boundary-Scan-Register)通过JTAG测试激活，平时这些引脚保持正常的IC功能．以含有JTAG接口的StrongARM SA1110为例，Flash为intel的28F128J32 16M 的容量．SA1110的JTAG的TCK,TMS,TDI,TDO分别接PC并口的2,3,4,11线上，通过程序对JTAG口的控制指令和目标代码从PC的并口写入JTAG的BSR中．在设计PCB时必须将SA1110的数据线，地址线及控制线与FLASH的地址线，数据线，控制线相连．因SA1110的数据线，地址线及控制线引脚上都有相应的BSC,只要用JTAG指令将数据，地址及控制信号送到其BSC中，就可以通过BSC对应的引脚将信号送给FLASH，实现对FLASH的操作．通过对TCK,TMS等的设置,可以将JTAG设置为接收指令或数据状态,JTAG常用指令如下: SAMPLE/PRELOAD: 用此指令采样BSC内容或将数据写入BSC单元. EXTEST: 当执行此指令时,BSC的内容通过引脚送到与其连接的相应芯片的引脚,我们就通过这种指令实现在线写FLASH. BYPASS: 此指令将一个移位寄存器轩于移位回路中,即仅有一个移位寄存器处于TDI和TDO之间. 在PCB电路设计好后,即可用程序先将对JTAG的控制指令,通过TDI送入JTAG控制器的指令寄存器中.再通过TDI将要写flash的地址,数据及控制线信号入BSR中,并将数据锁存到BSC中,用EXTEST指令通过BSC将写入FLASH.电路设计和编程中的注意事项. 1.FLASH芯片的WE,CE,OE等控制线必须与SA1110的BSR相连,只有这样才能通过BSR控制FLASH的相应引脚. 2.JTAG口和PC并口的连接线要尽量短,原则上不大于15CM. 3.FLASH在擦除和编程时所需的工作电流比较大，在选用系统的供电芯片时必须加以考虑. 4.为提高FLASH的编程速度,尽量使TCK不低于6MHZ,可编写烧写FLASH程序时实现.B. JTAG引脚定义1.TCK 为TAP操作提供一个独立、基本的时钟信号，TAP的所有操作都是通过这个时钟信号来驱动的2.TMS用来控制TAP状态机的转换，通过TMS信号可以控制TAP在不同的状态间相互转换，TMS信号在TCK信号的上升沿有效3.TDI是数据输入的接口，所有输入到特定寄存器的数据都要通过TDI一位一位串行输入的4.TDO是数据输出的接口，所有从特定寄存器输出的数据都要通过TDO一位一位串行输出的5.TRST可以用来对TAP Controller进行复位，该信号线可选，TMS也可以对其复位6.VTREF接口信号电平参考电压一般直接接Vsupply，这个可以用来确定ARM 的JTAG接口逻辑电平7.RTCK可选项，由目标端反馈给仿真器的时钟信号，用来同步TCK信号的产生，不使用时直接接地8.System Reset可选项，与目标板上的系统复位信号相连，可以直接对目标系统复位，同时可以检测目标系统的复位情况，为了防止误触发应在目标端加上适当的上拉电阻ER IN用户自定义输入，可以接到一个IO口上，用来接受上位机的控制ER OUT用户自定义输出，可以接到一个IO口上，用来向上位机反馈一个状态由于JTAG经常使用排线连接，为了增强抗干扰能力，在每条信号线间加上地线就出现了这种20针的接口。
(技术规范标准)先进测试标准和技术体系研究
先进测试标准和技术体系研究孟汉城，奚全生(北京航天测控公司, 北京 100037)0 概述测试是测量与试验的简称。
测量内涵：对被检测对象的物理、化学、工程技术等方面的参量做数值测定工作。
试验内涵：是指在真实情况下或模拟情况下对被研究对象的特性、参数、功能、可靠性、维修性、适应性、保障性、反应能力等进行测量和度量的研究过程。
试验与测量技术是紧密相连，试验离不开测量。
在各类试验中，通过测量取得定性定量数值，以确定试验结果。
而测量是随着产品试验的阶段而划分的，不同阶段的试验内容或需求则有相对应的测量设备和系统，用以完成试验数值、状态、特性的获取、传输、分析、处理、显示、报警等功能。
产品测试是通过试验和测量过程，对被检测对象的物理、化学、工程技术等方面的参量、特性等做数值测定工作，是取得对试验对象的定性或定量信息的一种基本方法和途径。
测试的基本任务是获取信息。
因此，测试技术是信息科学的源头和重要组成部分。
信息是客观事物的时间、空间特性，是无所不在，无时不存的。
但是人们为了某些特定的目的，总是从浩如烟海的信息中把需要的部分取得来，以达到观测事物某一本值问题的目的。
所需了解的那部分信息以各种技术手段表达出来，提供人们观测和分析，这种对信息的表达形式称之为“信号”，所以信号是某一特定信息的载体。
信息、信号、测试与测试系统之间的关系可以表述为：获取信息是测试的目的，信号是信息的载体，测试是通过测试系统、设备得到被测参数信息的技术手段。
同时，在军事装备及产品全寿命周期内要进行试验测试性设计与评价，并通过研制相应的试验检测设备、试验测试系统（含软、硬件）确保军事装备和产品达到规定动作的要求，以提高军事装备和产品的完好性、任务成功性，减少对维修人力和其它资源要求，降低寿命周期费用，并为管理提供必要的信息。
全寿命过程又称为全寿命周期，是指产品从论证开始到淘汰退役为止的全过程。
产品全寿命过程的划分，各国有不同的划分。
美国把全寿命过程划分为6个阶段：初步设计、批准、全面研制、生产、使用淘汰（退役）。
JTAG边界扫描介绍
第二节 IEEE.1149标准结构
IEEE1149.1BST结构：当器件工作在JTAG BST模式时，使用4个I/O引脚和一个可选引脚TRST作为JTAG引脚。这4个I/O引脚是：TDI 、TDO、 TMS 和TCK。下表概括了这些引脚的功能。
4，就开始做程序了，也是重要的一步建立边界扫描链。一般的结合电路图和网表分析出扫描连了，有的可能不止一条，要一一分清楚。分清楚号，在软件里建立。并且导入BSDL编译。BSDL很多都可以从IC厂商的网站上download，有的不提供download可以找RD问他们的sales要，一定要有BSDL，否则没办法继续。建好了扫描链以后就可以在板子上验证扫描链是否正确，就是检查扫描链的完整性。
2，有了开发平台你就要接受他们的培训，这种专业的软件需要有人教才会上手快，不要舍不得培训费，不培训以后的麻烦大了去了，供应商也会觉得你烦，不过通常都老板决定，苦乐都是员工受的。
上面都是准备工作，废话多了：）
3，培训好了就开始做吧。各家的开发基本的都大同小异，先准备资料吧，需要些什么呢？总的来说"软"的部分需要电路图，网表，BSDL，BOM，有的可能还有测试要求的spec。硬的部分就是实板和电源了。最后软硬都齐了，工作就有效率了。
今天就简单写点吧，希望对想入门的朋友理个头绪，同行们也可以做个比较坚定。这里有一点需要说明的是，我这里讲的可不是编写边界扫描开发和运行平台，讲的仅仅是基于开发平台的程序开发，就像在VC++里写MFC。下面就一步步告诉你怎么写了。
1，你要买个开发平台，知名的有ASSET-InterTech，Corelis，Goepel，JTAG，都是国外的，规模也比较大，小的就不说了，也是挺多的，推荐这些是因为他们比较完善的软件和售后服务。
基于IEEE Std 1149.1-2001标准的TAP控制器设计
边 界扫 描测试 技术 在降低 产 品测试 成本 ， 提高 产 品质 量 和可靠 性 以及 缩 短 产 品上 市 时 间 等方 面 有 显著 的 优点 ．所 以 ， 界扫 描技术 一 提 出就 受到 边 电子行 业 的关注 和广为 接受 ， 目前 已得 到 了很 多应 用 ¨ ．现在 ， 一些 国际性 的大公 司 如 Ｃ ｒｌ ． Ａ ｏｅｉ Ｊ Ｇ， ｓＴ
Ａ ｅｌｇ ， ｇｅｔＣｓｏ等公 司 已经 致 力 于开 发 满 ｅｕｏｉ Ａ ｉｎ，ｉ ｅ ｌ ｃ
足相 关 测 试协议 的测试仪 器 和集成 电路 ．
获 等功 能 ．这 些 功 能 的实 现 是 由测 试控 制 逻 辑 来
控 制的 ．测试 控制 逻辑 由两 条信号线 驱动 ： 试 方 测 式 选 择 线 （ Ｍ ，Ｔ ｓ Ｍ ｄ ｅ ｃ ｅ
要求 Ｉ 至少 有 四个 可利 用 的测 试 管脚 ， 将 它 Ｃ中 或 们 附加到 其他 的功 能管 脚上 ． 边界 扫描测 试技 术 的工作 原 理 是 ：１ Ｇ 测试 Ｊ’ Ａ 仪利 用一 个 四线 测 试接 口， 测试数据 以串行 方式 将 由 Ｔ Ｉ 人 到 边 界扫 描 寄 存 器 中 ， 过 Ｔ Ｄ输 通 ＭＳ发 送
（Ｃ Ｔ Ｋ，Ｔ ｓ Ｃｏｋ 线 ．所 以 ， ｅｔ ｌｃ ） 整个 边 界 扫 描 测 试
１ 关 于 Ｉ Ｅ ｔ ９ １—２ ０ Ｅ Ｅ Ｓｄｌ４ ． １ ０１
１９ ９ ０年 的 １４ ． ９ １标 准 并 没有 将 该 体 系 结 １ 构 中 的问题 考虑得 很周 到 ．在 后 来 的 １ 年 中 ， ０余 ＩＥ Ｅ Ｅ计算 机 协会对 该协议 进行 了不 断 的修订 和补 充 ． ９ ９年 ， 布 了 Ｉ Ｅ ｔ １４ ． １９ 发 Ｅ Ｅ Ｓｄ １９ ４标 准 ， 主要 解 决模 拟集 成 电 路 的可 测 试 性 问题 ．由于 在 混 合 系统 中 ， 拟模 块 和数 字模 块有 着 符种关 系 ，Ｅ Ｅ 模 ＩＥ 计 算 机协 会 又 对 １４ ． １９ １标 准进 行 了 修订 ， 就 是 这 下 面 使用 到 的 Ｉ Ｅ ｔｌ４ ． — ０ １ 准 ． Ｅ Ｅ Ｓｄ ９ １ ２ ０ 标 １
JTAG协议规范1149.1和1149.7
Doing More with Less – An IEEE 1149.7 Embedded Tutorial : Standard for Reduced-pin and Enhanced-functionality Test Access Port andBoundary-Scan ArchitectureAdam W LeyASSET InterTech, Inc. Richardson TX, USAAbstractIEEE Std 1149.7 offers a means to reduce chip pins dedicated to test (and debug) access while enhancing the functionality of the Test Access Port (TAP) as a complementary superset of the original IEEE Std 1149.1 (JTAG). Extended features such as hot-plug immunity, power management, optimization of scan throughput, access to instrumentation, and access to custom technologies provide welcome improvements for debug. Further, the boundary-scan architecture is bolstered to ensure full support for test. This important advancement in test and debug interfaces is well suited for access to multiple cores on SOC or multiple die in SIP or POP.1.IntroductionIn the 1980s, the Joint Test Action Group (JTAG) was formed to address a growing concern about diminishing test access to chips on boards due to the adoption of surface-mount assembly methods and ongoing miniaturization of chip packages. In 1990, their efforts culminated in the ratification of IEEE Std 1149.1 – Standard Test Access Port and Boundary-Scan Architecture. While 1149.1 was firmly rooted in the needto solve the problems of board test, as exemplified by the provision for boundary scan, the proponents of the standard realized the need for a generalized means of low-level access to components on boards and in systems that would suit a wide range of uses. As a result, the 1149.1 test access port (TAP), as specified, has met this need.In fact, even before the ink was dry, the 1149.1 TAP was being exploited for purposes beyond board test. In these early days, its utility was deployed to support access to chips for in-circuit emulation (debug), albeit often with additional pins for proprietary signals. Somewhat later, the ubiquity of the 1149.1 TAP was exploited in a normative sense for in-system configuration of programmable devices by way of IEEE Std 1532. Later still, use of the 1149.1 TAP as a debug interface was standardized by NEXUS 5001 (although still requiring additional signaling for many cases). Today, for the same reasons of utility and ubiquity, the 1149.1 TAP is considered the most likely means of access to chips that support embedded instruments per P1687 (informally known as Internal JTAG or IJTAG).Notwithstanding the exceptional merits of the 1149.1 TAP, ongoing industry momentum toward greater miniaturization and still more integration led some to the conclusion that a makeover was needed [1]. In particular, they proposed to enhance its functionality and utility in applications debug, but also to reduce pins to be better suited to multi-core/ multi-die architectures. IEEE Std 1149.7 [2, 3, 4, 5] has been developed to meet these needs [6, 7, 8, 9, 10, 11, 12].1.1What is IEEE 1149.7IEEE 1149.7 is a standard for a test access port and associated architecture that offers reduced pins and enhanced functionality. With regard to pin reduction, whereas the conventional 1149.1 TAP (TAP.1) requires at least four signals (with a fifth, for test reset, being optional), the reduced-pin 1149.7 TAP (TAP.7) requires only two signals (with the possibility for encoding the optional test reset function onto these). Further, with regard to functionality enhancement, it is expected that, in many cases, extended signaling needs for uses such as applications debug can be met on no more than two pins. Even while delivering these benefits, 1149.7 has taken great pains to preserve the investment that the industry has made in 1149.1 for chips and on boards. Particularly, 1149.7 adopts the entirety of the 1149.1 boundary-scan architecture to fully support board test and in-system configuration. Further, 1149.7 does not replace 1149.1, but rather adapts it and extends it, building upon its foundation and legacy. For example, as illustrated in Figure 1, an 1149.1 chip can be adapted easily to provide a TAP.7. As well, TAP.7s can coexist with TAP.1s on boards and, in some cases, even on the same board-level TAP connections.“before”“after”Figure 1—Adaptation of 1149.1 to 1149.71.2IEEE 1149.7 Key ObjectivesThe key objectives for 1149.7 fall broadly into three categories – system architecture, applications debug, and legacy infrastructure (to include test).Benefits for system architecture derive from the appropriate accommodation of multiple on-chip embedded TAP Controllers (EMTAPC), the reduction of pins, the adoption of glue-less star topology, independence from CPU/debug technology, and provisions for power management. Where intellectual property (IP) blocks may each contain EMTAPCs, multiples of these may be accommodated on a complex system-on-chip (SOC). While reduced pin count has inherent value with respect to miniaturization, consider as well that, in combination with the star topology, fewer pins better support the new 3D packaging methodologies such as system-in-package (SIP). These typically involve the stacking of die as shown in Figure 2; conversely, a daisy-chaining implementation is not only more difficult but also is not 1149.1 compliant. Of course, the same can be said for package-on-package (POP). Further, independence from particular CPU/debug technologies supports similar integrations even where chips may incorporate CPU IP from multiple sources. Facilities that permit the test logic to enter power-down modes support increasingly aggressive power management requirements.Figure 2—Star topology for a 3-die SIPFor applications debug, the TAP.7 provides advanced capability that reduces or eliminates the need for signaling beyond the two wires. Extensions provided include robust hot connect, increased throughput by way of scan optimization, higher operating frequency, and transport of background instrumentation data and/ or custom protocols. Of course, independence from CPU/debug technology also accrues here because uniform tool sets can support chips with heterogeneous CPUs.Finally, as concerns the legacy infrastructure, the objectives are two-fold – first, honor 1149.1 by preserving the test infrastructure that has been built up around it and on which the industry depends; and second, maintain a level of compliance such that existing intellectual property in chips, on boards, and in debug and test systems (DTS) can be adapted at low cost.2. Overview/ How it WorksAt the highest level of abstraction, 1149.7 provides for a chip-level TAP.7 Controller that bridges the conventional 1149.1-accessible System Test Logic (STL) to the four (five) or two (three) wires of the chip-level TAP.7 (the test reset signal is optional in either case). The STL has its own 1149.1 chip-level TAP Controller (CLTAPC) and all of the associated test logic architecture, including a chip-level boundary-scan register and related EXTEST, PRELOAD, and SAMPLE instructions.Seeking to extend 1149.1 in a compatible fashion, 1149.7 starts with the observation that the TAP Controller (TAPC) at the core of 1149.1 is a two-wire control means, even in the conventional series topology, as shown in Figure 3.TCK TDITDOTMSFigure 3—Conventional series topology, highlighting the starwiring for TCK/TMSPer 1149.1 convention, the starred TCK/TMS can only advance the TAPC state, which in turn invokes TDI/TDO for scan operations, but, absent instruction register scans, does not change the mode of the test logic. Thus, the key concept of 1149.7 continues with the observation that control extensions might be overlaid on sequences of TAPC states (more details on this later).Thus, 1149.7 adds its own commands and registers on which the other layers of extended functionality are based. These additional layers add scan formats, direct addressability, packetization of scan data (TMS, TDI, and/ or TDO information) onto the TMS wire (hence, re-designated TMSC), and finally packetization of non-scan information onto TMSC to provide for transport of background and/ or custom data.As such, 1149.7 supports a number of capability classes (six in number, designated as T0 - T5). So the TAP.7 Controller is configurable to support the required capability for a given implementation. The primary functional units are illustrated in Figure 4 and are designated as follows: Advanced Protocol Unit (APU), Extended Protocol Unit (EPU), Pin-Sharing Logic (PSL), and Reset and Selection Unit (RSU). The manner in which these items are invoked (or not) for given capability classes will be described in subsequent sections.TDI(C)nTRST EPU TAP.7TDO(C)TCK(C)TMS(C)TAP.7 ControllerFigure 4—Notional view of the 1149.7 architecture2.1 Capability classesRegardless of which capability class is implemented, a given TAP.7 must implement all of the mandatory features of its own class as well as those of all lower-numbered classes (T0 < T5). The classes are generally considered in two primary groupings: those which extend 4-wire operation (T0 – T3) and those which provide the reduced-pin, 2-wire operation (T4 – T5).T0–foundationAs the foundation of all TAP.7 capabilities, T0 begins with 1149.1-Specified behavior, such that the T0 STL is 100 percent compliant to 1149.1 including provisions for the mandatory chip-level boundary-scan architecture. With 1149.7 T0, the chip-level device identification register becomes mandatory.Of the TAP.7 Controller elements shown in Figure 4, only the RSU is permitted as an option; the other items are reserved for higher classes.Where the RSU is implemented, this would be done, as for any other class, to permit Escape Sequences and/ or Selection/Deselection Alerts to be available to manage the sharing of TAP.7 signaling across technologies and topologies. When the TAP.7 Adapter TAPC (ADTAPC) is deselected, the CLTAPC will be parked. These topics will be addressed in greater detail with T3 where the RSU becomes mandatory.Of particular note, even where the chip has multiple EMTAPCs, as might be the case for a complex SOC that implements a mix of several core IP blocks, the T0 STL shall provide 1149.1-Specified behavior from the Test-Logic-Reset TAPC state. 1149.7 identifies several means by which EMTAPCs can be selected under the control of the CLTAPC. A further method is defined for managing multiple die-level TAPCs in a similar manner for SIP. T1–commands and registersWith T1, the 1149.7 mechanism providing extended control by way of TCK/TMS is invoked to access 1149.7 commands and registers. These functions pertain to the EPU as illustrated in Figure 4. So, the EPU block of the TAP.7 Controller is present for T1. Otherwise, excepting the RSU, as for T0, all other blocks are reserved for higher classes.As described earlier, the extended control mechanism operates without disruption to the conventional 1149.1 TAPC state machine. Rather, it uses a particular state sequence, which is benign to normal 1149.1 operations, to initiate 1149.7-defined action.The state sequence of interest is known as a zero-bit DR scan (ZBS) and these are to be operated only while all of the CLTAPCs in the selected topology operate BYPASS or IDCODE so as to ensure that they do not disrupt normal system operation. In fact, ZBS detection is validated only when no IR scans have intervened since the last occurrence of the Test-Logic-Reset TAPC state.The progression of states that is recognized as a ZBS is illustrated in Figure 5.ScanCapture-DRExit1-DRExit2-DRUpdate-DRShift-DRPause-DR1110111abFigure 5—Zero-bit scan (ZBS)There are actually two different paths, labeled as “a” and “b” in Figure 5, that can implement a ZBS. In either case, the state sequence of interest is defined as follows: from the Select-DR-Scan TAPC state, proceed to the Update-DR TAPC state without passing the Shift-DR TAPC state. From the Test-Logic-Reset TAPC state, wherein the ZBS count is set to zero, the extended control mechanism is initiated when at least two ZBSs are detected before a subsequent non-zero-bit DR scan, which locks the ZBS count. A locked ZBS count of two provides access to the 1149.7 commands and registers. Locked ZBS counts greater than two access higher control levels that will not be detailed here.Once the ZBS count is locked, and a control level set, it is only unlocked when the control level is exited by entry to either the Select-IR-Scan or Test-Logic-Reset TAPC states or by certain 1149.7 commands and events that are used to synchronize T4 and T5 operations.At control level 2, commands are recognized, without the use of TDI/TDO pins, by counting the number of TCK(C)ticks in the Shift-DR TAPC state for two scans that immediately follow the completion of the non-zero-bit DR scan that locked the ZBS count. Each of these two primary command words is coded in 5 bits, ensuring that these counts need not exceed 31. All commands include two such parts for a total code length of 10 bits. In most cases, the command and register operations are concluded in these two parts but in some (only three) special cases a third part (a DR scan of a length determined by the control register addressed by the command) is required.T1 mandates a given minimum set of such commands and the registers that they address. Additionally, some commands, registers, and associated functions are optional, notably those that invoke directed test reset generation and request for functional reset.Additionally, T1 provides for power management through four modes of power control for the test logic. These four modes are: allow power down if TCK stops at logic one for more than 1 ms, allow power down if TCK stops at logic one for more than 1 ms in the Test-Logic-Reset TAPC state, allow power down if the device is in the Test-Logic-Reset TAPC state, and do not allow power down (the test logic is always powered).Given that a power-down mode is supported, the test logic is directed to resume powered operation when the Run-Test/Idle TAPC state is forced for at least 100 ms and at least 3 TCK(C) ticks.T2–scan formatsThe 1149.7 scan formats are introduced in T2. A T2 TAP.7 supports JScan0 – JScan2; other scan formats are reserved for higher classes.Of the TAP.7 Controller elements shown in Figure 4, for T2, as for T1, only the EPU is mandatory with the RSU permitted as an option; the other items are reserved for higher classes. For T2 versus T1, the EPU adds the commands and registers associated with the scan formats. As regards the function of these scan formats, JScan0 provides 1149.1-Specified behavior while JScan1 provides for the deselection of the CLTAPC in favor of a 1-bit scan path (so-called Super Bypass) that is active for IR scans as well as DR scans and JScan2 provides for activation/deactivation of the Super Bypass according to the value of an 1149.7 register.A T2 TAP.7 can opt either for JScan0 or JScan1 as its startup behavior. The latter case is described as providing hot-plug immunity since it should permit live connection (or disconnection) of the TAP.7 signals to be non-disruptive to the test logic.T3–direct addressabilityFinally, with T3, the star topology (4 wire), as in Figure 6, is supported. This comes by adding the means for direct addressability and the JScan3 scan format that provides for scans to star-4 topologies.Figure 6—Star-4 topologyOf the TAP.7 Controller elements shown in Figure 4, T3 adds the RSU as a mandatory element in addition to the EPU. For T3 versus T2, the EPU adds the commands and registers associated with direct addressability. Note that for T3, the TDI and TDO signals are re-designated as TDIC and TDOC, respectively.Concerning the RSU for T3, it is required to implement Escape Sequences for reset and for selection/ deselection and may optionally implement Selection and Deselection Alerts. Escape Sequences involve the detection and counting of a number of edges on TMS(C) driven while TCK(C) is held at logic 1. The count of such edges determines the action to be taken in response to the Escape Sequence. Alerts are specific predefined sequences of 128 bits as driven on TMS(C).The resource invoked for support of direct addressability is the TAP.7 Controller Address (TCA), as shown in Figure 7. The values corresponding to DEVICE_ID are inherited from the 1149.1 device identification register capture value for the CLTAPC. The assignment of the NODE_ID is made by some implementation-specific means that is not defined by 1149.7. The NODE_ID serves to distinguish multiple TAP.7s on a given topology branch where they are of the same device type.Figure 7—TAP.7 Controller Address (TCA)A key provision required to facilitate scans to the star-4 topology is the prevention of drive conflict on TDOC. The JScan3 format is managed so that when multiple TAP.7 Controllers are requested to participate, then drive on TDOC will be inhibited.As discussed in more detail in 4.1, test applications require the ability to coordinate the simultaneous entry of all devices of interest into and/ or through the Capture-xR, Update-xR, and Run-Test/Idle TAPC states. At first glance, the star topology would seem not to support this requirement. But in addition to the JScan3 scan format, T3 adds the Scan Selection Directives (SSD) to deal with this matter. The SSDs make use of Pause-xR TAPC states as parking states to which simultaneous scan captures aredirected and from which simultaneous scan updates are directed. Scan shift operations, as necessitated by the star topology are done on a device-by-device basis and are both directed from and to the Pause-xR TAPC states. T4–packetization of scan data (2-pin scan formats)With T4, a number of additional scan formats are added to support the advanced protocol, which is operated on two pins. The TCK/TMS pins are re-designated as TCKC/TMSC, respectively. The corresponding star-2 topology is illustrated in Figure 8. Note that TMSC is bidirectional.TMSCTCKCFigure 8—Star-2 topologyOf course, these additions require the provision of the APU of Figure 4. As well, since the TDIC/TDOC pins are optional since they are not used for 2-pin operation, where they are provided the PSL also becomes an option. Where a T4 TAP.7 does not provide the TDIC/TDOC pins in any configuration, it is described as narrow and designated as T4N. Where a T4 TAP.7 does have a configuration that provides the TDIC/TDOC pins, it is described as wide and designated as T4W.One of the more basic scan formats that supports the advanced protocol is OScan1. The serialization of the scan packet for OScan1 is illustrated in Figure 9. As shown, the TDI bit information is inverted. Also, for each cycle in which the TDO bit appears it is driven from the selected device in the target system back to the DTS.TCKCTMSC stateFigure 9—Scan packet serialization – OScan1Other scan formats in the OScan series provide for optimizations in which the scan packets omit bits that can be known to carry no significant information. An example worth noting is the OScan7 format which is optimized for downloads from the DTS to the target system. For OScan7, as illustrated in Figure 10, only the TDI bit information is included in the packets sent during Shift-xR TAPC states.TCKC nTDI nTDI nTDI nTDI nTDI nTDI nTDI nTDI nTDITMSC Shift-xRShift-xRShift-xRstateFigure 10—Scan packet serialization – OScan7Further performance optimization that can be obtained for T4 is by invoking falling-edge sampling for TMSC which, presuming hold times still can be met, delivers a degree of improvement in setup times that would allow the TCKC frequency to be increased (perhaps doubled).T5–transport of non-scan data (2-pin mode)At the top of the classes, T5 offers the capability to interleave transfers of non-scan data among the scan transfers. This is referred to as transport and has two variants – background data transport (BDX) and custom data transport (CDX).Both types of transport can use any combination of Run-Test/Idle, Pause-xR, and Update-xR TAPC states after which to insert transport packets. The distinction is that, whereas BDX has fixed allocation of I/O bandwidth available to the chip-level data channel, CDX has a custom allocation of I/O bandwidth as determined/ defined by the chip-level unit.2.2 Selection hierarchyWhile some aspects of the selection hierarchy have been described above, some additional detail is warranted as it is a key aspect of the 1149.7 system architecture.In general, where selection is enabled within the hierarchy, those items not selected are effectively offline/ parked and respond only to particular selection requests on the TAP.7 signaling. Those that are selected are online and respond to the TAP.7 signaling according to the protocols for which they are configured.Five levels in the selection hierarchy are elaborated below. For each level of the hierarchy, one or more selection mechanisms may pertain. - TechnologyWhere the 1149.7 technology can be placed offline, the TAP.7 signaling can be shared with other technologies- TopologyW here the constituent 1149.7 devices can be placed offline (a function required for T3 and above), the TAP.7 signaling can be shared among any topology branches, whether series, star-2, or star-4 - Adapter (i.e., ADTAPC)1149.7 devices comprising a selected topology branch will share TAP.7 signaling and, where the topology branch is star-2 or star-4, a given device may be selected for a given operation- Chip (i.e., CLTAPC)For a selected ADTAPC, the CLTAPC may be offline and will require selection when it must be operated- Core (i.e., EMTAPC)For a selected CLTAPC, given EMTAPC(s) of interest may be offline and will require selection when it (they) must be operated3.Implications for DebugIn many respects, 1149.7 was defined by and for the debug community. Thus, many of the implications, considerations, and supporting features have already been addressed in the elaboration of the basic 1149.7 functions as described above. Still some of these bear specific mention in this context.3.1Debug considerationsChief among the considerations for debug are ease and efficiency. Of course, these unfold across multiple dimensions and are often intertwined.EaseThe highest degree of visibility and control is required to drive the analysis tools that can get to the bottom of thorny problems that arise in today’s multi-threaded, multi-core, real-time embedded systems. 1149.7 promises to bring value to this equation by consolidating debug access for multiple cores onto a smaller number of chip pins.Other features tending toward ease of debug are the hot-plug immunity and system interrogation.EfficiencyCertainly 1149.7 enjoys a performance boost relative to 1149.1 with its various optimizations for scan throughput and its ability to improve link utilization by using otherwise idle non-scan states to transport background instrumentation data.3.2Debug featuresAs one would expect, 1149.7 brings a wealth of features to address debug ease and efficiency.Access consolidationSeveral aspects of the 1149.7 system architecture provide for access consolidation: management of EMTAPCs (T0), star topology (T3), pin reduction (T4N/T5N), and capability for the TAP.7 to transport background data and custom protocols (T5). All of these result in making debug instrumentation more accessible and, hence, easier to use. Hot-plug immunityLive connection without system disruption is vital and is enabled by the offline at startup (T3 or any with RSU) and Super Bypass at startup (T2) features. System interrogationA method for topology interrogation (T3) is provided and enumeration of controllers can be made by undirected allocation of Controller IDs (CID) (T3), as in Figure 11. These features allow the system architecture to be discovered by the debug tool at connect time.Each participating chip drives its AT[n]on wired-OR basis (logic 1 inactive)All supporting chips without CID participate;chips with a CID do not participate.For each participating chip, its aliasing targetAT[35:0] = TCA[34:0] + 0Final n?Each chip that detects that itsAT[n] != TDO drops outNext nThe chip that matched all 36 bitsof its AT to all 36 bits of TDOwins and gets the CIDFigure 11—CID Allocation, Undirected Optimization of scan throughputPerhaps above all, 1149.7 offers a great number of opportunities to optimize scan throughput. Super Bypass (T2) results in shorter scan chains for series topology. Star topology (T3) offers direct addressability and, hence, scan operation in only the target of interest.Advanced protocol (T4) offers still further improvements based on scan packet optimization on one hand and falling-edge timing (and thereby clock doubling) on the other.Improved link utilizationBDX and CDX (T5) allow the link to be used for transport of instrumentation data even during non-scan states, which would otherwise be idle.4.Implications for TestWhile 1149.7 primarily has been developed for the benefit of applications debug, it also has gone to considerable lengths to ensure that the test legacy of the original 1149.1 is honored. Among the several test-related provisions are the scan selection directives that ensure update/ capture/ run-test synchronization and the definition of suitable test languages.4.1Test considerationsWhile 1149.7 does not change radically how 1149.1 boundary scan/ test is being used today, there are some new considerations for test that arise with the 1149.7 architecture. Primary among these are the divergence inscan-state sequencing and series/star interoperability. Other considerations worth mention are hierarchical navigation, power control, and large-system applications. Scan-state sequencingThe typical test application has requirements for scan-state sequencing that necessitate coordination of application of stimuli across multiple distinct components (with their own boundary-scan registers) on a given unit under test (UUT). Consider the case where several components have distinct 3-state outputs on a shared wire junction. If the distinct output control cells in each of these components were not updated in a coordinated fashion, a contention could be present on the shared wire. The simplest means of such coordination is to ensure that all components pass simultaneously through the Update-DR TAPC state. As well, while it might not be necessary in some cases, the coordination of the acquisition of response generally also is required (or at least preferred). At the least, where specific response to given stimuli is required, the distinct responses for each component involved must all be acquired before the applied stimulus is changed. Here again, the simplest means for such is to ensure that all components pass simultaneously through the Capture-DR TAPC state (in fact, simultaneity may be strictly required in some special cases).Some test applications, such as the testing of advanced digital networks per IEEE Std 1149.6, have an additional requirement that all components participating in such testing must pass simultaneously through the Run-Test/Idle TAPC state.Conventional scan sequencing for test applications presuming series topology is illustrated in Figure 12.Run-Test-Idle1Select-DR-ScanCapture-DRExit1-DRExit2-DRUpdate-DRShift-DRPause-DR110111Figure 12—Scan-state sequence (conventional) for testapplications, series topologyThis conventional scan-state sequence can be broken down as follows:- (in yellow) all components on the UUT (series topology) pass through the Capture-DR TAPC state wherein responses (to a previously applied stimulus) are acquired in concert- (in red) all components on the UUT (series topology) enter and remain in the Shift-DR TAPC state until all responses have been exported and all new stimuli have been imported- (in blue) all components on the UUT (series topology) pass through the Update-DR TAPC state wherein new stimuli are applied in concert- (in grey) all components on the UUT (series topology) dwell in/ pass through the Run-Test/Idle TAPC state wherein transient stimuli may be generated in concert The divergence introduced by the 1149.7 star topology is that, due to shared wiring of TDIC and TDOC for star-4 or TMSC for star-2, only one component may be operated in the Shift-DR TAPC state at a time.Fortunately, we can take from the above discussion that the Shift-DR TAPC state is actually neutral to the requirements of the test application. Thus, the needs of the test application can be served, even for a star topology if each of the TAPC states Capture-DR, Update-DR, and Run-Test/Idle can be operated in concert across all of the UUT components of interest.It is for just this purpose that the scan selection directives (SSD) were devised. Figure 13 illustrates the scan-state sequence made possible by the SSDs (star topology).Run-Test-Idle1Select-DR-ScanCapture-DRExit1-DRExit2-DRUpdate-DRShift-DRPause-DR11111Figure 13—Scan-state sequence for test applications,modified for star topology。
一种兼容IEEE1149.1接口的模拟电压监测器的应用
一种兼容IEEE1149.1接口的模拟电压监测器的应用
杜影;王石记;安百岳
【期刊名称】《计算机测量与控制》
【年(卷),期】2010(018)010
【摘要】针对模拟电压监测的技术现状,提出以支持IEEE1149.1接口标准的模拟电压监测器进行电压监测电路设计;简要介绍了模拟电压监测器的基本结构、操作原理和应用方式;通过实际电压电路可测性设计方案的制定分析、实验和测试,说明了该电压监测器的优势和特点;同时,文中提出应用FPGA作为内建自测试(BIST)控制器执行监测操作,是边界扫描技术与BIST技术结合应用的一次创新;最后的应用结果表明,该监测器的使用为电路设计人员的可测性设计提供了一种新思路和参考方法.
【总页数】3页(P2427-2429)
【作者】杜影;王石记;安百岳
【作者单位】北京航天测控技术开发公司,北京,100041;北京航天测控技术开发公司,北京,100041;北京航天测控技术开发公司,北京,100041
【正文语种】中文
【中图分类】TP273
【相关文献】
1.高压、低电流电压监测器MAX6459及其应用 [J], 方佩敏
2.一种轻量级的Win32应用程序二进制接口兼容方案 [J], 周海洋;黄小大
3.程控交换机五号与中国一号信号模拟接口设备的兼容使用 [J], 尹培生
4.全兼容IEEE1149.1的MIPS CPU CORE可测性设计 [J], 陆正毅;孙承绶;程君侠
5.采用高压模拟/I^2L兼容工艺的用户线接口电路设计 [J], 于宗光;常桂兰;贺洁因版权原因，仅展示原文概要，查看原文内容请购买。
边界扫描结构和IEEE1149_1标准
基于进入数据寄存器扫描或指令寄存器扫描模 块，在捕捉和移位操作过程中，在选定的扫描通道 中的影像锁存器保持当前状态，当TAP进入UpdateDR或Update-IR状态时，移入到选定扫描通道的数 据通过影像锁存器输出，刷新状态使影像锁存器刷 新（或并行加载）移位到所选择的扫描通道中的新 数据。图4给出了TAP控制输出信号以及指令寄存器 与数据寄存器的互联。
2 边界扫描结构、测试访问端口及测试操作
IEEE 1149.1标准规定的边界扫描结构由指令 寄存器、旁路寄存器、边界扫描寄存器、可选的用 户数据寄存器、测试读取端口（TAP）组成，如图2 所示，该图中边界扫描寄存器（BSR）是由一组BSC 组成的串行读取数据寄存器，这些边界扫描单元在 IC的输入输出边界上。指令寄存器和数据寄存器是 在主要的测试数据输入（TDI）管脚和输出管脚之 间独立的扫描通道，该结构允许TAP在不进入其他 扫描通道的情况下，通过指令或数据两种扫描通道 选择和移动数据。[4]
边界扫描技术的一个不太明显的优点就是通过 扫描路径，应用预先开发的功能模式给IC的I/O管脚 设置一定的值，对DC测试，IC的生产商和ASIC的 开发者产生功能模式设置。这些模式可以在IC的线 上功能测试中重复使用，在系统诊断中对这些模式 的重复使用可以节省大量的开发资源，尤其对于多 种IC具有嵌入的边界扫描通道的系统更是如此。[2]
JR仓针脚定义
JR仓针脚定义Test Clock Input(TCK)-----强制要求1TCK在IEEE1149.1标准里是强制要求的。
TCK为TAP的操作提供了一个独立的、基本的时钟信号，TAP的所有操作都是通过这个时钟信号来驱动的。
Test Mode Selection Input(TMS)-----强制要求2TMS信号在TCK的上升沿有效。
TMS在IEEE1149.1标准里是强制要求的。
TMS信号用来控制TAP状态机的转换。
通过TMS信号，可以控制TAP在不同的状态间相互转换。
Test Data Input(TDI)-----强制要求3TDI在IEEE1149.1标准里是强制要求的。
TDI是数据输入的接口。
所有要输入到特定寄存器的数据都是通过TDI接口一位一位串行输入的（由TCK驱动）。
Test Data Output(TDO)-----强制要求4TDO在IEEE1149.1标准里是强制要求的。
TDO是数据输出的接口。
所有要从特定的寄存器中输出的数据都是通过TDO接口一位一位串行输出的（由TCK驱动）。
Test Reset Input(TRST)----可选项1这个信号接口在IEEE1149.1标准里是可选的，并不是强制要求的。
TRST可以用来对TAP Controller进行复位（初始化）。
因为通过TMS也可以对TAP Controll进行复位（初始化）。
所以有四线JTAG与五线JTAG之分。
(VTREF)-----强制要求5接口信号电平参考电压一般直接连接Vsupply。
这个可以用来确定ARM的JTAG接口使用的逻辑电平（比如3.3V还是5.0V?Return Test Clock(RTCK)----可选项2可选项，由目标端反馈给仿真器的时钟信号,用来同步TCK信号的产生,不使用时直接接地。
System Reset(nSRST)----可选项3可选项,与目标板上的系统复位信号相连,可以直接对目标系统复位。