MEMORY存储芯片MT48LC8M16A2P-6AL中文规格书
MEMORY存储芯片MT48LC32M8A2-6A G中文规格书
Automotive Mobile LPDDR2 SDRAM MT42L64M16D1, MT42L32M32D1Features•Ultra low-voltage core and I/O power supplies–V DD2 = 1.14–1.30V–V DDCA/V DDQ = 1.14–1.30V–V DD1 = 1.70–1.95V•Clock frequency range–533–10 MHz (data rate range: 1066–20 Mb/s/pin)•Four-bit prefetch DDR architecture•Eight internal banks for concurrent operation •Multiplexed, double data rate, command/address inputs; commands entered on every CK edge •Bidirectional/differential data strobe per byte of data (DQS/DQS#)•Programmable READ and WRITE latencies (RL/WL)•Programmable burst lengths: 4, 8, or 16•Per-bank refresh for concurrent operation•On-chip temperature sensor to control self refresh rate•Partial-array self refresh (PASR)•Deep power-down mode (DPD)•Selectable output drive strength (DS)•Clock stop capability•RoHS-compliant, “green” packagingTable 1: Key Timing ParametersOptions Marking •V DD2: 1.2V L •Configuration–8 Meg x 16 x 8 banks x 1 die64M16– 4 Meg x 32 x 8 banks x 1 die32M32•Device type–LPDDR2-S4, 1 die in package D1•FBGA “green” package–134-ball FBGA (10mm x11.5mm)HE •Timing – cycle time– 1.875ns @ RL = 8-18– 2.5ns @ RL = 6-25•Special options–Automotive grade (Package-levelburn-in)A •Operating temperature range–From –40°C to +85°C IT–From –40°C to +105°C AT •Revision:A Note: 1.For Fast t RCD/t RP, contact factory.AC TimingTable 86: AC TimingNotes 1–2 apply to all parameters and conditions. AC timing parameters must satisfy the t CK minimum conditions (in mul-tiples of t CK) as well as the timing specifications when values for both are indicated.。
MEMORY存储芯片MT48LC8M16A2P-6A L中文规格书
Table 55: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)8Gb: x4, x8, x16 DDR3L SDRAM Electrical Characteristics and AC Operating ConditionsInput Operating ConditionsTable 21: DDR3L 1.35V DC Electrical Characteristics and Input ConditionsNotes: 1.V REFCA(DC) is expected to be approximately 0.5 × V DD and to track variations in the DClevel. Externally generated peak noise (non-common mode) on V REFCA may not exceed ±1% × V DD around the V REFCA(DC) value. Peak-to-peak AC noise on V REFCA should not ex-ceed ±2% of V REFCA(DC).2.DC values are determined to be less than 20 MHz in frequency. DRAM must meet specifi-cations if the DRAM induces additional AC noise greater than 20 MHz in frequency.3.V REFDQ(DC) is expected to be approximately 0.5 × V DD and to track variations in the DC level. Externally generated peak noise (non-common mode) on V REFDQ may not exceed ±1% × V DD around the V REFDQ(DC) value. Peak-to-peak AC noise on V REFDQ should not ex-ceed ±2% of V REFDQ(DC).4.V REFDQ(DC) may transition to V REFDQ(SR) and back to V REFDQ(DC) when in SELF REFRESH,within restrictions outlined in the SELF REFRESH section.5.V TT is not applied directly to the device. V TT is a system supply for signal termination re-sistors. Minimum and maximum values are system-dependent.8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – DC and AC。
MEMORY存储芯片MT48LC8M16A2TG-75IT G中文规格书
InitializationThe following sequence is required for power-up and initialization, as shown in Fig-ure 46 (page 125):1.Apply power. RESET# is recommended to be below 0.2 × V DDQ during power rampto ensure the outputs remain disabled (High-Z) and ODT off (R TT is also High-Z).All other inputs, including ODT, may be undefined.During power-up, either of the following conditions may exist and must be met:•Condition A:–V DD and V DDQ are driven from a single-power converter output and areramped with a maximum delta voltage between them of ˂V ื 300mV. Slope re-versal of any power supply signal is allowed. The voltage levels on all balls oth-er than V DD, V DDQ, V SS, V SSQ must be less than or equal to V DDQ and V DD onone side, and must be greater than or equal to V SSQ and V SS on the other side.–Both V DD and V DDQ power supplies ramp to V DD,min and V DDQ,min withint V DDPR = 200ms.–V REFDQ tracks V DD × 0.5, V REFCA tracks V DD × 0.5.–V TT is limited to 0.95V when the power ramp is complete and is not applieddirectly to the device; however, t VTD should be greater than or equal to 0 toavoid device latchup.•Condition B:–V DD may be applied before or at the same time as V DDQ.–V DDQ may be applied before or at the same time as V TT, V REFDQ, and V REFCA.–No slope reversals are allowed in the power supply ramp for this condition.2.Until stable power, maintain RESET# LOW to ensure the outputs remain disabled(High-Z). After the power is stable, RESET# must be LOW for at least 200μs to be-gin the initialization process. ODT will remain in the High-Z state while RESET# isLOW and until CKE is registered HIGH.3.CKE must be LOW 10ns prior to RESET# transitioning HIGH.4.After RESET# transitions HIGH, wait 500μs (minus one clock) with CKE LOW.5.After the CKE LOW time, CKE may be brought HIGH (synchronously) and onlyNOP or DES commands may be issued. The clock must be present and valid for atleast 10ns (and a minimum of five clocks) and ODT must be driven LOW at leastt IS prior to CKE being registered HIGH. When CKE is registered HIGH, it must becontinuously registered HIGH until the full initialization process is complete.6.After CKE is registered HIGH and after t XPR has been satisfied, MRS commandsmay be issued. Issue an MRS (LOAD MODE) command to MR2 with the applicablesettings (provide LOW to BA2 and BA0 and HIGH to BA1).7.Issue an MRS command to MR3 with the applicable settings.8.Issue an MRS command to MR1 with the applicable settings, including enablingthe DLL and configuring ODT.9.Issue an MRS command to MR0 with the applicable settings, including a DLL RE-SET command. t DLLK (512) cycles of clock input are required to lock the DLL.10.Issue a ZQCL command to calibrate R TT and R ON values for the process voltagetemperature (PVT). Prior to normal operation, t ZQinit must be satisfied.11.When t DLLK and t ZQinit have been satisfied, the DDR3 SDRAM will be ready fornormal operation.mode can be used. Figure 45 depicts a general procedure for exiting write levelingmode. After the last rising DQS (capturing a 1 at T0), the memory controller should stop driving the DQS signals after t WLO (MAX) delay plus enough delay to enable the memo-ry controller to capture the applicable prime DQ state (at ~Tb0). The DQ balls become undefined when DQS no longer remains LOW, and they remain undefined until t MOD after the MRS command (at Te1).The ODT input should be de-asserted LOW such that ODTLoff (MIN) expires after the DQS is no longer driving LOW. When ODT LOW satisfies t IS, ODT must be kept LOW (at ~Tb0) until the DRAM is ready for either another rank to be leveled or until the normal mode can be used. After DQS termination is switched off, write level mode should be disabled via the MRS command (at Tc2). After t MOD is satisfied (at Te1), any valid com-mand may be registered by the DRAM. Some MRS commands may be issued after t MRD (at Td1).Figure 45: Write Leveling Exit ProcedureCKCK#Command ODTR TT(DQ)AddressR TT DQS, R TT DQS#DQS, DQS#DQ Note: 1.The DQ result, = 1, between Ta0 and Tc0, is a result of the DQS, DQS# signals capturingCK HIGH just after the T0 state.。
MEMORY存储芯片MT48LC16M16A2P-6A ITG中文规格书
Table 50: DDR3L Differential Output Driver Characteristics V OX(AC)Notes:1.RZQ of 240˖ ±1% with RZQ/7 enabled (default 34˖ driver) and is applicable after prop-er ZQ calibration has been performed at a stable temperature and voltage (V DDQ = V DD ;V SSQ = V SS ).2.See Figure 31 (page 75) for the test load configuration.3.See Figure 30 (page 74) for an example of a differential output signal.4.For a differential slew rate between the list values, the V OX(AC) value may be obtainedby linear interpolation.Figure 30: Differential Output SignalV OHMIN outputMAX outputV OLV OX(AC)maxV OX(AC)minReference Output LoadFigure 31 (page 75) represents the effective reference load of 25ȍ used in defining the relevant device AC timing parameters (except ODT reference timing) as well as the out-put slew rate measurements. It is not intended to be a precise representation of a partic-ular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the tim-ing reference load to a system environment.Figure 31: Reference Output Load for AC Timing and Output Slew RateV TT = V DDQ /2V SSSlew Rate Definitions for Single-Ended Output SignalsThe single-ended output driver is summarized in Table 48 (page 72). With the reference load for timing measurements, the output slew rate for falling and rising edges is de-fined and measured between V OL(AC) and V OH(AC) for single-ended signals.Table 51: Single-Ended Output Slew Rate Definition4Gb: x4, x8, x16 DDR3L SDRAMOutput Characteristics and Operating Conditionsleast once every 70.3μs. When T C is greater than 85°C, but less the 95°C, the refresh peri-od is 32ms. When T C is greater than 95°C, but less the 105°C, the refresh period is 16ms.37.Although CKE is allowed to be registered LOW after a REFRESH command whent REFPDEN (MIN) is satisfied, there are cases where additional time such as t XPDLL (MIN) is required.38.ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins toturn on. ODT turn-on time maximum is when the ODT resistance is fully on. The ODT reference load is shown in Figure 24 (page 63). This output load is used for ODT timings (see Figure 31 (page 75)).Designs that were created prior to JEDEC tightening the maxi-mum limit from 9ns to 8.5ns will be allowed to have a 9ns maximum.39.Half-clock output parameters must be derated by the actual t ERR10per and t JITdty wheninput clock jitter is present. This results in each parameter becoming larger. The parame-ters t ADC (MIN) and t AOF (MIN) are each required to be derated by subtracting both t ERR10per (MAX) and t JITdty (MAX). The parameters t ADC (MAX) and t AOF (MAX) are required to be derated by subtracting both t ERR10per (MAX) and t JITdty (MAX).4Gb: x4, x8, x16 DDR3L SDRAMElectrical Characteristics and AC Operating Conditions。
MEMORY存储芯片MT48LC16M16A2P-6AITG中文规格书
Bus Operations CE# LOW and RST# HIGH enable READ operations. The device internally decodes up-per address inputs to determine the accessed block. ADV# LOW opens the internal ad-dress latches. OE# LOW activates the outputs and gates selected data onto the I/O bus.Bus cycles to/from the device conform to standard microprocessor bus operations. Busoperations and the logic levels that must be applied to the device control signal inputsare shown here.Table 9: Bus OperationsNotes: 1.Refer to the Device Command Bus Cycles for valid DQ[15:0] during a WRITE operation.2.X = "Don’t Care" (H or L).3.RST# must be at V SS ± 0.2V to meet the maximum specified power-down current. ReadTo perform a READ operation, RST# and WE# must be de-asserted while CE# and OE#are asserted. CE# is the device-select control. When asserted, it enables the device. OE#is the data-output control. When asserted, the addressed flash memory data is drivenonto the I/O bus.WriteTo perform a WRITE operation, both CE# and WE# are asserted while RST# and OE# arede-asserted. During a WRITE operation, address and data are latched on the rising edgeof WE# or CE#, whichever occurs first. The Command Bus Cycles table shows the buscycle sequence for each of the supported device commands, while the Command Codesand Definitions table describes each command.Note: WRITE operations with invalid V CC and/or V PP voltages can produce spurious re-sults and should not be attempted.Output DisableWhen OE# is de-asserted, device outputs DQ[15:0] are disabled and placed in High-Zstate, WAIT is also placed in High-Z.StandbyWhen CE# is de-asserted the device is deselected and placed in standby, substantiallyreducing power consumption. In standby, the data outputs are placed in High-Z, inde-pendent of the level placed on OE#. Standby current (I CCS) is the average current meas-Status RegisterRead Status RegisterTo read the status register, issue the READ STATUS REGISTER command at any address.Status register information is available at the address that the READ STATUS REGISTER,WORD PROGRAM, or BLOCK ERASE command is issued to. Status register data is auto-matically made available following a word program, block erase, or block lock com-mand sequence. Reads from the device after any of these command sequences will out-put the devices status until another valid command is written (e.g. READ ARRAY com-mand).The status register is read using single asynchronous mode or synchronous burst modereads. Status register data is output on DQ[7:0], while 0x00 is output on DQ[15:8]. Inasynchronous mode, the falling edge of OE# or CE# (whichever occurs first) updatesand latches the status register contents. However, when reading the status register insynchronous burst mode, CE# or ADV# must be toggled to update status data.The device write status bit (SR7) provides the overall status of the device. SR[6:1]present status and error information about the PROGRAM, ERASE, SUSPEND, V PP, andBLOCK LOCK operations.Note: Reading the status register is a nonarray READ operation. When the operation oc-curs in asynchronous page mode, only the first data is valid and all subsequent data areundefined. When the operation occurs in synchronous burst mode, the same data wordrequested will be output on successive clock edges until the burst length requirementsare satisfied.Table 16: Status Register DescriptionNotes: 1.Default value = 0x80.2.Always clear the status register prior to resuming ERASE operations. This eliminates sta-tus register ambiguity when issuing commands during ERASE SUSPEND. If a commandLatency CountThe latency count (LC) bits tell the device how many clock cycles must elapse from therising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until thefirst valid data word is driven to DQ[15:0]. The input clock frequency is used to deter-mine this value. The First Access Latency Count figure shows the data output latency fordifferent LC settings.Figure 13: First Access Latency CountCLK [C]Address [A]ADV# [V]DQ[15:0] [D/Q]DQ[15:0] [D/Q]DQ[15:0] [D/Q]DQ[15:0] [D/Q]DQ[15:0] [D/Q]DQ[15:0] [D/Q]DQ[15:0] [D/Q]DQ[15:0] [D/Q]Note: 1.First Access Latency Count Calculation:•1 / CLK frequency = CLK period (ns)•n x (CLK period) ≥t AVQV (ns) – t CHQV (ns)•Latency Count = nFigure 14: Example Latency Count Setting Using Code 3CLKCE#ADV#A[MAX:1]D[15:0]End of Wordline ConsiderationsEnd of wordline (EOWL) wait states can result when the starting address of the burst op-eration is not aligned to a 16-word boundary; that is, A[4:1] of the start address does not equal 0x0. The figure below illustrates the end of wordline wait state(s) that occur after the first 16-word boundary is reached. The number of data words and wait states is summarized in the table below.Figure 15: End of Wordline Timing DiagramCLK ADV#OE#WAIT#A[MAX:1]DQ[15:0]Figure 18: Buffer Program ProcedureNotes: 1.Word count values on DQ0:DQ15 are loaded into the count register. Count ranges forthis device are N = 0000h to 01FFh.2.Device outputs the status register when read.3.Write buffer contents will be programmed at the device start or destination address.4.Align the start address on a write buffer boundary for maximum programming perform-ance; that is, A[9:1] of the start address = 0).5.Device aborts the BUFFERED PROGRAM command if the current address is outside theoriginal block address.6.Status register indicates an improper command sequence if the BUFFERED PROGRAMcommand is aborted. Follow this with a CLEAR STATUS REGISTER command.7.Device defaults to SR output data after BUFFERED PROGRAMMING SETUP command(E8h) is issued . CE# or OE# must be toggled to update the status register . Don’t issuethe READ SR command (70h); it is interpreted by the device as buffer word count.8.Full status check can be done after erase and write sequences complete. Write FFh afterthe last operation to reset the device to read array mode.Figure 19: Buffered Enhanced Factory Programming (BEFP) Procedure。
MEMORY存储芯片MT48LC16M16A2P-6AG中文规格书
14.t CH (ABS) is the absolute instantaneous clock high pulse width as measured from onerising edge to the following falling edge.15.t CL (ABS) is the absolute instantaneous clock low pulse width as measured from one fall-ing edge to the following rising edge.16.The cycle-to-cycle jitter t JITcc is the amount the clock period can deviate from one cycleto the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL locking time.17.The cumulative jitter error t ERRnper, where n is the number of clocks between 2 and 50,is the amount of clock time allowed to accumulate consecutively away from the average clock over n number of clock cycles.18.t DS (base) and t DH (base) values are for a single-ended 1 V/ns slew rate DQs (DQs are at2V/ns for DDR3-1866) and 2 V/ns slew rate differential DQS, DQS#; when DQ single-ended slew rate is 2V/ns, the DQS differential slew rate is 4V/ns.19.These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transi-tion edge to its respective data strobe signal (DQS, DQS#) crossing.20.The setup and hold times are listed converting the base specification values (to whichderating tables apply) to V REF when the slew rate is 1 V/ns (DQs are at 2V/ns forDDR3-1866). These values, with a slew rate of 1 V/ns (DQs are at 2V/ns for DDR3-1866), are for reference only.21.When the device is operated with input clock jitter, this parameter needs to be deratedby the actual t JITper (larger of t JITper (MIN) or t JITper (MAX) of the input clock (output deratings are relative to the SDRAM input clock).22.Single-ended signal parameter.23.The DRAM output timing is aligned to the nominal or average clock. Most output pa-rameters must be derated by the actual jitter error when input clock jitter is present, even when within specification. This results in each parameter becoming larger. The fol-lowing parameters are required to be derated by subtracting t ERR10per (MAX): t DQSCK (MIN), t LZDQS (MIN), t LZDQ (MIN), and t AON (MIN). The following parameters are re-quired to be derated by subtracting t ERR10per (MIN): t DQSCK (MAX), t HZ (MAX), t LZDQS (MAX), t LZDQ (MAX), and t AON (MAX). The parameter t RPRE (MIN) is derated by sub-tracting t JITper (MAX), while t RPRE (MAX) is derated by subtracting t JITper (MIN).24.The maximum preamble is bound by t LZDQS (MAX).25.These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its re-spective clock signal (CK, CK#) crossing. The specification values are not affected by the amount of clock jitter applied, as these are relative to the clock signal crossing. These parameters should be met whether clock jitter is present.26.The t DQSCK (DLL_DIS) parameter begins CL + AL - 1 cycles after the READ command.27.The maximum postamble is bound by t HZDQS (MAX).mands requiring a locked DLL are: READ (and RDAP) and synchronous ODT com-mands. In addition, after any change of latency t XPDLL, timing must be met.29.t IS (base) and t IH (base) values are for a single-ended 1 V/ns control/command/addressslew rate and 2 V/ns CK, CK# differential slew rate.30.These parameters are measured from a command/address signal transition edge to itsrespective clock (CK, CK#) signal crossing. The specification values are not affected by the amount of clock jitter applied as the setup and hold times are relative to the clock signal crossing that latches the command/address. These parameters should be metwhether clock jitter is present.31.For these parameters, the DDR3 SDRAM device supports t n PARAM (n CK) = RU(t PARAM[ns]/t CK[AVG] [ns]), assuming all input clock jitter specifications are satisfied. For exam-ple, the device will support t n RP (n CK) = RU(t RP/t CK[AVG]) if all input clock jitter specifi-cations are met. This means that for DDR3-800 6-6-6, of which t RP = 5ns, the device will support t n RP = RU(t RP/t CK[AVG]) = 6 as long as the input clock jitter specifications are met. That is, the PRECHARGE command at T0 and the ACTIVATE command at T0 + 6 are valid even if six clocks are less than 15ns due to input clock jitter.32.During READs and WRITEs with auto precharge, the DDR3 SDRAM will hold off the in-ternal PRECHARGE command until t RAS (MIN) has been satisfied.33.When operating in DLL disable mode, the greater of 4CK or 15ns is satisfied for t WR.34.The start of the write recovery time is defined as follows:•For BL8 (fixed by MRS or OTF): Rising clock edge four clock cycles after WL •For BC4 (OTF): Rising clock edge four clock cycles after WL•For BC4 (fixed by MRS): Rising clock edge two clock cycles after WL35.RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in High-Z. Until RESET# is LOW, the outputs are at risk of driving and could result in exces-sive current, depending on bus activity.36.The refresh period is 64ms when T C is less than or equal to 85°C. This equates to an aver-age refresh rate of 7.8125μs. However, nine REFRESH commands should be asserted at least once every 70.3μs. When T C is greater than 85°C, the refresh period is 32ms.37.Although CKE is allowed to be registered LOW after a REFRESH command whent REFPDEN (MIN) is satisfied, there are cases where additional time such as t XPDLL (MIN)is required.38.ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins to turn on. ODT turn-on time maximum is when the ODT resistance is fully on. The ODT reference load is shown in Figure 20 (page 53). Designs that were created prior to JEDEC tightening the maximum limit from 9ns to 8.5ns will be allowed to have a 9ns maxi-mum.39.Half-clock output parameters must be derated by the actual t ERR10per and t JITdty when input clock jitter is present. This results in each parameter becoming larger. The parame-ters t ADC (MIN) and t AOF (MIN) are each required to be derated by subtracting both t ERR10per (MAX) and t JITdty (MAX). The parameters t ADC (MAX) and t AOF (MAX) are required to be derated by subtracting both t ERR10per (MAX) and t JITdty (MAX).40.ODT turn-off time minimum is when the device starts to turn off ODT resistance. ODT turn-off time maximum is when the DRAM buffer is in High-Z. The ODT reference load is shown in Figure 20 (page 53). This output load is used for ODT timings (see Figure 27(page 65)).41.Pulse width of a input signal is defined as the width between the first crossing of V REF(DC) and the consecutive crossing of V REF(DC).42.Should the clock rate be larger than t RFC (MIN), an AUTO REFRESH command should have at least one NOP command between it and another AUTO REFRESH command. Ad-ditionally, if the clock rate is slower than 40ns (25 MHz), all REFRESH commands should be followed by a PRECHARGE ALL command.43.DRAM devices should be evenly addressed when being accessed. Disproportionate ac-cesses to a particular row address may result in a reduction of REFRESH characteristics or product lifetime.44.When two V IH(AC) values (and two corresponding V IL(AC) values) are listed for a specific speed bin, the user may choose either value for the input AC level. Whichever value is used, the associated setup time for that AC level must also be used. Additionally, one V IH(AC) value may be used for address/command inputs and the other V IH(AC) value may be used for data inputs.For example, for DDR3-800, two input AC levels are defined: V IH(AC175),min andV IH(AC150),min (corresponding V IL(AC175),min and V IL(AC150),min ). For DDR3-800, the address/command inputs must use either V IH(AC175),min with t IS(AC175) of 200ps or V IH(AC150),min with t IS(AC150) of 350ps; independently, the data inputs must use either V IH(AC175),min with t DS(AC175) of 75ps or V IH(AC150),min with t DS(AC150) of 125ps.45.The JEDEC t RFC specification is 350ns. Micron's 8Gb design offers the option of operat-ing t RFC at 310ns, t RFC(FAST). The user should note that as t RFC decreases there is a pro-portional IDD5B increase. See the Electrical Characteristics – 1.35V IDD Specifications sec-tion for IDD values.8Gb: x4, x8, x16 DDR3L SDRAMElectrical Characteristics and AC Operating ConditionsCommand and Address Setup, Hold, and DeratingThe total t IS (setup time) and t IH (hold time) required is calculated by adding the data sheet t IS (base) and t IH (base) values (see Table 56; values come from the Electrical Characteristics and AC Operatioing Conditions Table to the Δt IS and Δt IH derating val-ues (see Table 57 (page 91), Table 58 (page 91) or Table 59 (page 92)) respectively.Example: t IS (total setup time) = t IS (base) + Δt IS. For a valid transition, the input signal has to remain above/below V IH(AC)/V IL(AC) for some time t VAC (see Table 60 (page 92)).Although the total setup time for slow slew rates might be negative (for example, a valid input signal will not have reached V IH(AC)/V IL(AC) at the time of the rising clock transi-tion), a valid input signal is still required to complete the transition and to reachV IH(AC)/V IL(AC) (see Figure 11 (page 43) for input signal requirements). For slew rates that fall between the values listed in Table 57 (page 91) and Table 59 (page 92), the derat-ing values may be obtained by linear interpolation.8Gb: x4, x8, x16 DDR3L SDRAMCommand and Address Setup, Hold, and DeratingTable 61: DDR3L Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-BasedTable 62: DDR3L Derating Values for t DS/t DH – AC160/DC90-BasedTable 63: DDR3L Derating Values for t DS/tDH – AC135/DC100-BasedFigure 34: Nominal Slew Rate and t VAC for t DS (DQ – Strobe)V SSSetup slew raterising signalSetup slew ratefalling signal==V DDQV IH(AC)minV IH(DC)minV REF(DC)V IL(DC)maxV IL(AC)maxDQSDQS#CK#CKV IH(AC)min - V REF(DC)ΔTRV REF(DC) - V IL(AC)maxΔTFNote: 1.The clock and the strobe are drawn on different time scales.。
MEMORY存储芯片MT48LC8M16A2F4-75IT中文规格书
Figure 19: DLL-Off Mode Read Timing OperationCK_cCK_t CommandAddress DQS_t, DQS_c (DLL-on)DQS_c (DLL-on)DQS_t, DQS_c (DLL-off)DQS_c (DLL-off)DQS_c (DLL-off)DQS_t, DQS_c (DLL-off)Don’t CareTransitioning dataFine Granularity Refresh ModeMode Register and Command Truth TableThe REFRESH cycle time (t RFC) and the average refresh interval (t REFI) can be pro-grammed by the MRS command. The appropriate setting in the mode register will set a single set of REFRESH cycle times and average refresh interval for the device (fixed mode), or allow the dynamic selection of one of two sets of REFRESH cycle times and average refresh interval for the device (on-the-fly mode [OTF]). OTF mode must be ena-bled by MRS before any OTF REFRESH command can be issued.Table 49: MRS DefinitionThere are two types of OTF modes (1x/2x and 1x/4x modes) that are selectable by pro-gramming the appropriate values into the mode register MR3 [8:6]. When either of the two OTF modes is selected, the device evaluates the BG0 bit when a REFRESH com-mand is issued, and depending on the status of BG0, it dynamically switches its internal refresh configuration between 1x and 2x (or 1x and 4x) modes, and then executes the corresponding REFRESH operation.Table 50: REFRESH Command Truth Tablet REFI and t RFC ParametersThe default refresh rate mode is fixed 1x mode where REFRESH commands should be issued with the normal rate; that is, t REFI1 = t REFI(base) (for T C ื 85°C), and the dura-tion of each REFRESH command is the normal REFRESH cycle time (t RFC1). In 2x mode (either fixed 2x or OTF 2x mode), REFRESH commands should be issued to the device at the double frequency (t REFI2 = t REFI(base)/2) of the normal refresh rate. In 4x mode, the REFRESH command rate should be quadrupled (t REFI4 = t REFI(base)/4). Per 4Gb: x4, x8, x16 DDR4 SDRAM Fine Granularity Refresh Mode。
MEMORY存储芯片MT48LC8M16A2P-6AITL中文规格书
CommandsDESELECT The DESELT (DES) command (CS# HIGH) prevents new commands from being execu-ted by the DRAM. Operations already in progress are not affected.NO OPERATION The NO OPERATION (NOP) command (CS# LOW) prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affec-ted.ZQ CALIBRATION LONGThe ZQ CALIBRATION LONG (ZQCL) command is used to perform the initial calibra-tion during a power-up initialization and reset sequence (see Figure 50 (page 137)).This command may be issued at any time by the controller, depending on the systemenvironment. The ZQCL command triggers the calibration engine inside the DRAM. Af-ter calibration is achieved, the calibrated values are transferred from the calibration en-gine to the DRAM I/O, which are reflected as updated R ON and ODT values.The DRAM is allowed a timing window defined by either t ZQinit or t ZQoper to performa full calibration and transfer of values. When ZQCL is issued during the initializationsequence, the timing parameter t ZQinit must be satisfied. When initialization is com-plete, subsequent ZQCL commands require the timing parameter t ZQoper to be satis-fied.ZQ CALIBRATION SHORTThe ZQ CALIBRATION SHORT (ZQCS) command is used to perform periodic calibra-tions to account for small voltage and temperature variations. A shorter timing windowis provided to perform the reduced calibration and transfer of values as defined by tim-ing parameter t ZQCS. A ZQCS command can effectively correct a minimum of 0.5% R ONand R TT impedance error within 64 clock cycles, assuming the maximum sensitivitiesspecified in DDR3L 34 Ohm Output Driver Sensitivity (page 69).ACTIVATEThe ACTIVATE command is used to open (or activate) a row in a particular bank for asubsequent access. The value on the BA[2:0] inputs selects the bank, and the addressprovided on inputs A[n:0] selects the row. This row remains open (or active) for accessesuntil a PRECHARGE command is issued to that bank.A PRECHARGE command must be issued before opening a different row in the samebank.READThe READ command is used to initiate a burst read access to an active row. The addressprovided on inputs A[2:0] selects the starting column address, depending on the burstlength and burst type selected (see Burst Order table for additional information). Thevalue on input A10 determines whether auto precharge is used. If auto precharge is se-lected, the row being accessed will be precharged at the end of the READ burst. If autoprecharge is not selected, the row will remain open for subsequent accesses. The valueon input A12 (if enabled in the mode register) when the READ command is issued de-termines whether BC4 (chop) or BL8 is used. After a READ command is issued, theREAD burst may not be interrupted.Table 72: READ Command SummaryWRITEThe WRITE command is used to initiate a burst write access to an active row. The valueon the BA[2:0] inputs selects the bank. The value on input A10 determines whether autoprecharge is used. The value on input A12 (if enabled in the MR) when the WRITE com-mand is issued determines whether BC4 (chop) or BL8 is used.Input data appearing on the DQ is written to the memory array subject to the DM inputlogic level appearing coincident with the data. If a given DM signal is registered LOW,the corresponding data will be written to memory. If the DM signal is registered HIGH,the corresponding data inputs will be ignored and a WRITE will not be executed to thatbyte/column location.Table 73: WRITE Command SummaryPRECHARGEThe PRECHARGE command is used to de-activate the open row in a particular bank orin all banks. The bank(s) are available for a subsequent row access a specified time (t RP)after the PRECHARGE command is issued, except in the case of concurrent auto pre-charge. A READ or WRITE command to a different bank is allowed during a concurrentauto precharge as long as it does not interrupt the data transfer in the current bank anddoes not violate any other timing parameters. Input A10 determines whether one or allbanks are precharged. In the case where only one bank is precharged, inputs BA[2:0] se-lect the bank; otherwise, BA[2:0] are treated as “Don’t Care.”After a bank is precharged, it is in the idle state and must be activated prior to any READor WRITE commands being issued to that bank. A PRECHARGE command is treated asa NOP if there is no open row in that bank (idle state) or if the previously open row isalready in the process of precharging. However, the precharge period is determined bythe last PRECHARGE command issued to the bank.REFRESHThe REFRESH command is used during normal operation of the DRAM and is analo-gous to CAS#-before-RAS# (CBR) refresh or auto refresh. This command is nonpersis-tent, so it must be issued each time a refresh is required. The addressing is generated bythe internal refresh controller. This makes the address bits a “Don’t Care” during a RE-FRESH command. The DRAM requires REFRESH cycles at an average interval of 7.8μs(maximum when T C 85°C or 3.9μs maximum when T C 95°C). The REFRESH periodbegins when the REFRESH command is registered and ends t RFC (MIN) later.To allow for improved efficiency in scheduling and switching between tasks, some flexi-bility in the absolute refresh interval is provided. A maximum of eight REFRESH com-mands can be posted to any given DRAM, meaning that the maximum absolute intervalbetween any REFRESH command and the next REFRESH command is nine times themaximum average interval refresh rate. Self refresh may be entered with up to eight RE-FRESH commands being posted. After exiting self refresh (when entered with postedREFRESH commands), additional posting of REFRESH commands is allowed to the ex-tent that the maximum number of cumulative posted REFRESH commands (both pre-and post-self refresh) does not exceed eight REFRESH commands.At any given time, a maximum of 16 REFRESH commands can be issued within2 x t REFI.Figure 42: Refresh ModeDon’t CareIndicates break in time scaleCKCK#Command CKE AddressA10BA[2:0]DQ 4DM 4DQS, DQS#4Notes:1.NOP commands are shown for ease of illustration; other valid commands may be possi-ble at these times. CKE must be active during the PRECHARGE, ACTIVATE, and REFRESH commands, but may be inactive at other times (see Power-Down Mode (page 187)).2.The second REFRESH is not required, but two back-to-back REFRESH commands are shown.3.“Don’t Care” if A10 is HIGH at this point; however, A10 must be HIGH if more than one bank is active (must precharge all active banks).4.For operations shown, DM, DQ, and DQS signals are all “Don’t Care”/High-Z.5.Only NOP and DES commands are allowed after a REFRESH command and until t RFC(MIN) is satisfied.SELF REFRESHThe SELF REFRESH command is used to retain data in the DRAM, even if the rest of the system is powered down. When in self refresh mode, the DRAM retains data without ex-ternal clocking. Self refresh mode is also a convenient method used to enable/disable the DLL as well as to change the clock frequency within the allowed synchronous oper-ating range (see Input Clock Frequency Change (page 129)). All power supply inputs (including V REFCA and V REFDQ ) must be maintained at valid levels upon entry/exit and during self refresh mode operation. V REFDQ may float or not drive V DDQ /2 while in self refresh mode under the following conditions:•V SS < V REFDQ < V DD is maintained•V REFDQ is valid and stable prior to CKE going back HIGH•The first WRITE operation may not occur earlier than 512 clocks after V REFDQ is valid •All other self refresh mode exit timing requirements are met。
MEMORY存储芯片MT48LC4M16A2TG-6中文规格书
supplies (including V REF ) must be within the specified limits prior to exiting DPD (see AC and DC Operating Conditions).To exit DPD, CKE must be HIGH, t ISCKE must be complete, and the clock must be sta-ble. To resume operation, the device must be fully reinitialized using the power-up initi-alization sequence.Figure 63: Deep Power-Down Entry and Exit TimingCK/CK#CKE CS#CMD Don’t CareNotes: 1.The initialization sequence can start at any time after Tx + 1.2.t INIT3 and Tx + 1 refer to timings in the initialization sequence. For details, see Mode Register Definition.Input Clock Frequency Changes and Stop EventsInput Clock Frequency Changes and Clock Stop with CKE LOWDuring CKE LOW, Mobile LPDDR2 devices support input clock frequency changes and clock stop under the following conditions:•Refresh requirements are met•Only REFab or REFpb commands can be in process•Any ACTIVATE or PRECHARGE commands have completed prior to changing the fre-quency•Related timing conditions,t RCD and t RP , have been met prior to changing the fre-quency•The initial clock frequency must be maintained for a minimum of two clock cycles af-ter CKE goes LOW•The clock satisfies t CH(abs) and t CL(abs) for a minimum of two clock cycles prior to CKE going HIGHFor input clock frequency changes, t CK(MIN) and t CK(MAX) must be met for each clock cycle.After the input clock frequency is changed and CKE is held HIGH, additional MRW commands may be required to set the WR, RL, etc. These settings may require adjust-ment to meet minimum timing requirements at the target clock frequency.Preliminary1Gb: x16, x32 Automotive Mobile LPDDR2 SDRAM Input Clock Frequency Changes and Stop EventsFigure 30: Write Data Mask – Second Data Bit MaskedDon’t CareNote: 1.For the data mask function, WL = 2, BL = 4 is shown; the second data bit is masked.PRECHARGE CommandThe PRECHARGE command is used to precharge or close a bank that has been activa-ted. The PRECHARGE command is initiated with CS# LOW, CA0 HIGH, CA1 HIGH, CA2LOW, and CA3 HIGH at the rising edge of the clock. The PRECHARGE command can be used to precharge each bank independently or all banks simultaneously. For 4-bank de-vices, the AB flag and bank address bits BA0 and BA1 are used to determine which bank(s) to precharge. For 8-bank devices, the AB flag and the bank address bits BA0,BA1, and BA2 are used to determine which bank(s) to precharge. The prechargedbank(s) will be available for subsequent row access t RPab after an all bank PRECHARGE command is issued, or t RPpb after a single-bank PRECHARGE command is issued.To ensure that 8-bank devices can meet the instantaneous current demand required to operate, the row precharge time (t RP) for an all bank PRECHARGE in 8-bank devices (t RPab) will be longer than the row precharge time for a single-bank PRECHARGE (t RPpb). For 4-bank devices, t RPab is equal to t RPpb.ACTIVATE to PRECHARGE timing is shown in ACTIVATE Command.Preliminary1Gb: x16, x32 Automotive Mobile LPDDR2 SDRAM PRECHARGE Command。
MEMORY存储芯片MT48LC8M16A2P-75IT中文规格书
Write LevelingFor better signal integrity, DDR4 memory modules use fly-by topology for the com-mands, addresses, control signals, and clocks. Fly-by topology has benefits from the re-duced number of stubs and their length, but it also causes flight-time skew between clock and strobe at every DRAM on the DIMM. This makes it difficult for the controller to maintain t DQSS, t DSS, and t DSH specifications. Therefore, the device supports a write leveling feature to allow the controller to compensate for skew. This feature may not be required under some system conditions, provided the host can maintain the t DQSS, t DSS, and t DSH specifications.The memory controller can use the write leveling feature and feedback from the device to adjust the DQS (DQS_t, DQS_c) to CK (CK_t, CK_c) relationship. The memory con-troller involved in the leveling must have an adjustable delay setting on DQS to align the rising edge of DQS with that of the clock at the DRAM pin. The DRAM asynchronously feeds back CK, sampled with the rising edge of DQS, through the DQ bus. The controller repeatedly delays DQS until a transition from 0 to 1 is detected. The DQS delay estab-lished though this exercise would ensure the t DQSS specification. Besides t DQSS, t DSS and t DSH specifications also need to be fulfilled. One way to achieve this is to combine the actual t DQSS in the application with an appropriate duty cycle and jitter on the DQS signals. Depending on the actual t DQSS in the application, the actual values for t DQSL and t DQSH may have to be better than the absolute limits provided in the AC Timing Parameters section in order to satisfy t DSS and t DSH specifications. A conceptual tim-ing of this scheme is shown below.Figure 22: Write Leveling Concept, Example 1diff_DQSdiff_DQSDQ diff_DQSDQ T0T1T2T3T4T5CK_cCK_tT6T7CK_c CK_tSource Destination DQS driven by the controller during leveling mode must be terminated by the DRAM based on the ranks populated. Similarly, the DQ bus driven by the DRAM must also be terminated at the controller.All data bits carry the leveling feedback to the controller across the DRAM configura-tions: x4, x8, and x16. On a x16 device, both byte lanes should be leveled independently.Therefore, a separate feedback mechanism should be available for each byte lane. The upper data bits should provide the feedback of the upper diff_DQS(diff_UDQS)-to-clock relationship; the lower data bits would indicate the lower diff_DQS(diff_LDQS)-to-clock relationship.4Gb: x4, x8, x16 DDR4 SDRAM Write LevelingCRC Write Data FeatureCRC Write DataThe CRC write data feature takes the CRC generated data from the DRAM controller and compares it to the internally CRC generated data and determines whether the two match (no CRC error) or do not match (CRC error).Figure 107: CRC Write Data OperationWRITE CRC DATA Operation A DRAM controller generates a CRC checksum using a 72-bit CRC tree and forms the write data frames, as shown in the following CRC data mapping tables for the x4, x8, and x16 configurations. A x4 device has a CRC tree with 32 input data bits used, and the re-maining upper 40 bits D[71:32] being 1s. A x8 device has a CRC tree with 64 input data bits used, and the remaining upper 8 bits dependant upon whether DM_n/DBI_n is used (1s are sent when not used). A x16 device has two identical CRC trees each, one for the lower byte and one for the upper byte, with 64 input data bits used by each, and the remaining upper 8 bits on each byte dependant upon whether DM_n/DBI_n is used (1s are sent when not used). For a x8 and x16 DRAMs, the DRAM memory controller must send 1s in transfer 9 location whether or not DM_n/DBI_n is used.The DRAM checks for an error in a received code word D[71:0] by comparing the re-ceived checksum against the computed checksum and reports errors using the ALERT_n signal if there is a mismatch. The DRAM can write data to the DRAM core without waiting for the CRC check for full writes when DM is disabled. If bad data is written to the DRAM core, the DRAM memory controller will try to overwrite the bad data with good data; this means the DRAM controller is responsible for data coherency when DM is disabled. However, in the case where both CRC and DM are enabled via 4Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature。
MEMORY存储芯片MT46V8M16FJ-6中文规格书
fresh mode, the DLL remains disabled even upon exit of SELF REFRESH operation untilit is re-enabled and reset.The DRAM is not tested to check—nor does Micron warrant compliance with—normalmode timings or functionality when the DLL is disabled. An attempt has been made tohave the DRAM operate in the normal mode where reasonably possible when the DLLhas been disabled; however, by industry standard, a few known exceptions are defined:•ODT is not allowed to be used•The output data is no longer edge-aligned to the clock•CL and CWL can only be six clocksWhen the DLL is disabled, timing and functionality can vary from the normal operationspecifications when the DLL is enabled (see DLL Disable Mode (page 125)). Disablingthe DLL also implies the need to change the clock frequency (see Input Clock Frequen-cy Change (page 129)).Output Drive StrengthThe DDR3 SDRAM uses a programmable impedance output buffer. The drive strengthmode register setting is defined by MR1[5, 1]. RZQ/7 (34ȍ [NOM]) is the primary outputdriver impedance setting for DDR3 SDRAM devices. To calibrate the output driver im-pedance, an external precision resistor (RZQ) is connected between the ZQ ball andV SSQ. The value of the resistor must be 240ȍ ±1%.The output impedance is set during initialization. Additional impedance calibration up-dates do not affect device operation, and all data sheet timings and current specifica-tions are met during an update.To meet the 34ȍ specification, the output drive strength must be set to 34ȍ during initi-alization. To obtain a calibrated output driver impedance after power-up, the DDR3SDRAM needs a calibration command that is part of the initialization and reset proce-dure.OUTPUT ENABLE/DISABLEThe OUTPUT ENABLE function is defined by MR1[12], as shown in Figure 56 (page146). When enabled (MR1[12] = 0), all outputs (DQ, DQS, DQS#) function when in thenormal mode of operation. When disabled (MR1[12] = 1), all DDR3 SDRAM outputs(DQ and DQS, DQS#) are tri-stated. The output disable feature is intended to be usedduring I DD characterization of the READ current and during t DQSS margining (writeleveling) only.TDQS EnableTermination data strobe (TDQS) is a feature of the x8 DDR3 SDRAM configuration thatprovides termination resistance (R TT) and may be useful in some system configurations.TDQS is not supported in x4 or x16 configurations. When enabled via the mode register(MR1[11]), the R TT that is applied to DQS and DQS# is also applied to TDQS and TDQS#.In contrast to the RDQS function of DDR2 SDRAM, DDR3’s TDQS provides the termina-tion resistance R TT only. The OUTPUT DATA STROBE function of RDQS is not providedby TDQS; thus, R ON does not apply to TDQS and TDQS#. The TDQS and DM functionsshare the same ball. When the TDQS function is enabled via the mode register, the DMfunction is not supported. When the TDQS function is disabled, the DM function is pro-vided, and the TDQS# ball is not used. The TDQS function is available in the x8 DDR3DLL Disable ModeIf the DLL is disabled by the mode register (MR1[0] can be switched during initializationor later), the DRAM is targeted, but not guaranteed, to operate similarly to the normalmode, with a few notable exceptions:•The DRAM supports only one value of CAS latency (CL = 6) and one value of CASWRITE latency (CWL = 6).•DLL disable mode affects the read data clock-to-data strobe relationship (t DQSCK),but not the read data-to-data strobe relationship (t DQSQ, t QH). Special attention isrequired to line up the read data with the controller time domain when the DLL is dis-abled.•In normal operation (DLL on), t DQSCK starts from the rising clock edge AL + CLcycles after the READ command. In DLL disable mode, t DQSCK starts AL + CL - 1 cy-cles after the READ command. Additionally, with the DLL disabled, the value oft DQSCK could be larger than t CK.The ODT feature (including dynamic ODT) is not supported during DLL disable mode.The ODT resistors must be disabled by continuously registering the ODT ball LOW byprogramming R TT,nom MR1[9, 6, 2] and R TT(WR) MR2[10, 9] to 0 while in the DLL disablemode.Specific steps must be followed to switch between the DLL enable and DLL disablemodes due to a gap in the allowed clock rates between the two modes (t CK [AVG] MAXand t CK [DLL_DIS] MIN, respectively). The only time the clock is allowed to cross thisclock rate gap is during self refresh mode. Thus, the required procedure for switchingfrom the DLL enable mode to the DLL disable mode is to change frequency during selfrefresh:1.Starting from the idle state (all banks are precharged, all timings are fulfilled, ODTis turned off, and R TT,nom and R TT(WR) are High-Z), set MR1[0] to 1 to disable theDLL.2.Enter self refresh mode after t MOD has been satisfied.3.After t CKSRE is satisfied, change the frequency to the desired clock rate.4.Self refresh may be exited when the clock is stable with the new frequency fort CKSRX. After t XS is satisfied, update the mode registers with appropriate values.5.The DRAM will be ready for its next command in the DLL disable mode after thegreater of t MRD or t MOD has been satisfied. A ZQCL command should be issuedwith appropriate timings met.。
MEMORY存储芯片MT48V8M16LFFF-8中文规格书
Data MaskThe DATA MASK (DM) function, also described as a partial write, has been added to the device and is supported only for x8 and x16 configurations (x4 is not supported). The DM function shares a common pin with the DBI and TDQS functions. The DM function applies only to WRITE operations and cannot be enabled at the same time the write DBI function is enabled. Refer to the TDQS Function Matrix table for valid configurations for all three functions (TDQS/DM/DBI).CA Parity Persistent Error ModeNormal CA parity mode (CA parity persistent mode disabled) no longer performs CA parity checking while the parity error status bit remains set at 1. However, with CA pari-ty persistent mode enabled, CA parity checking continues to be performed when the parity error status bit is set to a 1.ODT Input Buffer for Power-DownThis feature determines whether the ODT input buffer is on or off during power-down.If the input buffer is configured to be on (enabled during power-down), the ODT input signal must be at a valid logic level. If the input buffer is configured to be off (disabled during power-down), the ODT input signal may be floating and the device does not pro-vide R TT(NOM) termination. However, the device may provide R TT(Park) termination de-pending on the MR settings. This is primarily for additional power savings.CA Parity Error StatusThe device will set the error status bit to 1 upon detecting a parity error. The parity error status bit remains set at 1 until the device controller clears it explicitly using an MRS command.CRC Error StatusThe device will set the error status bit to 1 upon detecting a CRC error. The CRC error status bit remains set at 1 until the device controller clears it explicitly using an MRS command.CA Parity Latency ModeCA parity is enabled when a latency value, dependent on t CK, is programmed; this ac-counts for parity calculation delay internal to the device. The normal state of CA parity is to be disabled. If CA parity is enabled, the device must ensure there are no parity er-rors before executing the command. CA parity signal (PAR) covers ACT_n, RAS_n/A16 ,CAS_n/A15, WE_n/A14, and the address bus including bank address and bank group bits. The control signals CKE, ODT, and CS_n are not included in the parity calculation.4Gb: x4, x8, x16 DDR4 SDRAM Mode Register 5Figure 169: Rx Mask DQ-to-DQS Timings DQS, DQs Data-In at DRAM Ball DQS, DQs Data-In at DRAM BallRx Mask Rx Mask – Alternative ViewDRAMbDRAMb Notes: 1.DQx represents an optimally centered mask.DQy represents earliest valid mask.DQz represents latest valid mask.2.DRAMa represents a DRAM without any DQS/DQ skews.DRAMb represents a DRAM with early skews (negative t DQS2DQ).DRAMc represents a DRAM with delayed skews (positive t DQS2DQ).3.This figure shows the skew allowed between DRAM-to-DRAM and between DQ-to-DQ for a DRAM. Signals assume data is center-aligned at DRAM latch.TdiPW is not shown; composite data-eyes shown would violate TdiPW.V CENTDQ,midpoint is not shown but is assumed to be midpoint of V diVW .The previous figure shows the basic Rx mask requirements. Converting the Rx mask re-quirements to a classical DQ-to-DQS relationship is shown in the following figure. It should become apparent that DRAM write training is required to take full advantage of the Rx mask.4Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation。
MEMORY存储芯片MT48LC8M16A2B4-6AITL中文规格书
Electrical Specifications – Program/Erase CharacteristicsTable 33: Program/Erase CharacteristicsNotes: 1.Four total partial-page programs to the same page. If ECC is enabled, then the device islimited to one partial-page program per ECC user area, not exceeding four partial-pageprograms per page.2.t CBSY MAX time depends on timing between internal program completion and data-in.3.Parameters are with internal ECC enabled.4.Typical is nominal voltage and room temperature.5.Typical t R_ECC is under typical process corner, nominal voltage, and at room tempera-ture.6.Data transfer from Flash array to data register with internal ECC disabled.7.AC characteristics may need to be relaxed if I/O drive strength is not set to full.8.Typical program time is defined as the time within which more than 50% of the pagesare programmed at nominal voltage and room temperature.RE#CE#ALE CLE I/Ox RDYFigure 91: READ ID OperationWE#CE#ALE CLE RE#Figure 92: PROGRAM PAGE OperationCE#ALE CLE RE#RDYI/OxFigure 93: PROGRAM PAGE Operation with CE# “Don’t Care”CLE CE#ALE Figure 94: PROGRAM PAGE Operation with RANDOM DATA INPUTWE#CE#ALE CLE RE#RDYI/OxFigure 95: PROGRAM PAGE CACHEDon’t CareFigure 96: PROGRAM PAGE CACHE Ending on 15hDon’t CareI/O6 = 1, ReadyI/O5= 1, ReadyI/O0= 0, Last page PROGRAM successful I/O1= 0, Last page – 1 PROGRAM successful。
MEMORY存储芯片MT48LC8M16A2P-6A IT中文规格书
Table 54: Electrical Characteristics and AC Operating Conditions (Continued)Notes: 1.AC timing parameters are valid from specified T C MIN to T C MAX values.2.All voltages are referenced to V SS .3.Output timings are only valid for R ON34 output buffer selection.4.The unit t CK (AVG) represents the actual t CK (AVG) of the input clock under operation.The unit CK represents one clock cycle of the input clock, counting the actual clock edges.5.AC timing and I DD tests may use a V IL -to-V IH swing of up to 900mV in the test environ-ment, but input timing is still referenced to V REF (except t IS, t IH, t DS, and t DH use the AC/DC trip points and CK, CK# and DQS, DQS# use their crossing points). The minimum slew rate for the input signals used to test the device is 1 V/ns for single-ended inputs and 2 V/ns for differential inputs in the range between V IL(AC) and V IH(AC).6.All timings that use time-based values (ns, μs, ms) should use t CK (AVG) to determine the correct number of clocks (Table 54 (page 73) uses CK or t CK [AVG] interchangeably). In the case of noninteger results, all minimum limits are to be rounded up to the nearest whole integer, and all maximum limits are to be rounded down to the nearest whole integer.7.Strobe or DQS diff refers to the DQS and DQS# differential crossing point when DQS is the rising edge. Clock or CK refers to the CK and CK# differential crossing point when CK is the rising edge.8.This output load is used for all AC timing (except ODT reference timing) and slew rates.The actual test load may be different. The output signal voltage reference point is V DDQ /2 for single-ended signals and the crossing point for differential signals (see Fig-ure 26 (page 65)).9.When operating in DLL disable mode, Micron does not warrant compliance with normal mode timings or functionality.8Gb: x4, x8, x16 DDR3L SDRAM Electrical Characteristics and AC Operating Conditions34 Ohm Output Driver ImpedanceThe 34˖ driver (MR1[5, 1] = 01) is the default driver. Unless otherwise stated, all timings and specifications listed herein apply to the 34˖ driver only. Its impedance R ON is de-fined by the value of the external reference resistor RZQ as follows: R ON34 = RZQ/7 (with nominal RZQ = 240˖ ±1%) and is actually 34.3˖ ±1%.Table 35: DDR3L 34 Ohm Driver Impedance CharacteristicsNotes: 1.Tolerance limits assume RZQ of 240˖ ±1% and are applicable after proper ZQ calibra-tion has been performed at a stable temperature and voltage: V DDQ = V DD ; V SSQ = V SS ).Refer to DDR3L 34 Ohm Output Driver Sensitivity (page 60) if either the temperature or the voltage changes after calibration.2.Measurement definition for mismatch between pull-up and pull-down (MM PUPD ). Meas-ure both R ON(PU) and R ON(PD) at 0.5 × V DDQ :MM PUPD = ×100R ON(PU) - R ON(PD)R ON,nom3.For IT and AT devices, the minimum values are derated by 6% when the device operates between –40°C and 0°C (T C ).A larger maximum limit will result in slightly lower minimum currents.8Gb: x4, x8, x16 DDR3L SDRAM Output Driver Impedance。
MEMORY存储芯片MT48LC8M16A2TG-6A IT L中文规格书
Parameter
Maximum peak amplitude allowed for overshoot area (see Figure 12)
Maximum peak amplitude allowed for undershoot area (see Figure 13)
Maximum overshoot area above VDD (see Figure 12)
ACTIVATE to internal READ or WRITE delay time
PRECHARGE command period
ACTIVATE-to-ACTIVATE or REFRESH command period
ACTIVATE-to-PRECHARGE command period
4
ns
3
ns
4
ns
4
ns
3
ns
4
ns
3
ns
4
ns
4
ns
3
ns
4
ns
4
ns
4
ns
4
ns
3
CK
CK
Notes:
1. The -107 speed grade is backward compatible with 1600, CL = 11 (-125) , 1333, CL = 9 (-15E) and 1066, CL = 7 (-187E).
4. Reserved settings are not allowed.
8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – DC and AC
MEMORY存储芯片MT48V8M16LFFF-8 ES中文规格书
Figure 16: RESET Procedure at Power Stable ConditionCKE R TTBG, BACK_t, CK_c Command Td Tc Don’t CareODT Th Ti Tj TkRESET_nTe TaTb Tf V DD , V DDQV PPTg Notes: 1.From time point Td until Tk, a DES command must be applied between MRS and ZQCLcommands.2.MRS commands must be issued to all mode registers that have defined settings.3.In general, there is no specific sequence for setting the MRS locations (except for de-pendent or co-related features, such as ENABLE DLL in MR1 prior to RESET DLL in MR0,for example).4.TEN is not shown; however, it is assumed to be held LOW.Uncontrolled Power-Down SequenceIn the event of an uncontrolled ramping down of V PP supply, V PP is allowed to be less than V DD provided the following conditions are met:•Condition A: V PP and V DD /V DDQ are ramping down (as part of turning off) from nor-mal operating levels.•Condition B: The amount that V PP may be less than V DD /V DDQ is less than or equal to 500mV .•Condition C: The time V PP may be less than V DD is ื10ms per occurrence with a total accumulated time in this state ื100ms.4Gb: x4, x8, x16 DDR4 SDRAM RESET and Initialization Procedurea.Repair will be initiated to the target DRAM only if all DQ during bit 0 through bit 7 are LOW. The bank under repair does not get the REFRESH command applied to it.b.Repair will not be initiated to the target DRAM if any DQ during bit 0 through bit 7 is HIGH.1.JEDEC states: All DQs of target DRAM should be LOW for 4t CK. If HIGH is driven to all DQs of a DRAM consecutively for equal to or longer than2t CK, then DRAM does not conduct hPPR and retains data if REF com-mand is properly issued; if all DQs are neither LOW for 4t CK nor HIGHfor equal to or longer than 2t CK, then hPPR mode execution is un-known.c.DQS should function normally.4.REF command may be issued anytime after the WRA command followed by WL +4n CK + t WR + t RP .a.Multiple REF commands are issued at a rate of t REFI or t REFI/2, however back-to-back REF commands must be separated by at least t REFI/4 when the DRAM is in hPPR mode.b.All banks except the bank under repair will perform refresh.5.Issue PRE after t PGM time so that the device can repair the target row during t PGM time.a.Wait t PGM_Exit after PRE to allow the device to recognize the repaired target row address.6.Issue MR4[13] 0 command to hPPR mode disable.a.Wait t PGMPST for hPPR mode exit to complete.b.After t PGMPST has expired, any valid command may be issued.The entire sequence from hPPR mode enable through hPPR mode disable may be re-peated if more than one repair is to be done.After completing hPPR mode, MR0 must be re-programmed to a prehPPR mode state if the device is to be accessed.After hPPR mode has been exited, the DRAM controller can confirm if the target row was repaired correctly by writing data into the target row and reading it back.Figure 75: hPPR WRA – Entry'RQ¶W &DUH 4Gb: x4, x8, x16 DDR4 SDRAM Post Package Repair。
MEMORY存储芯片MT48LC16M16A2B4-6A IT G中文规格书
PRECHARGEThe PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row activation a specified time (t RP) after the PRECHARGE command is issued, except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank is al-lowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. After a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command is allowed if there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. However,the precharge period will be determined by the last PRECHARGE command issued to the bank.REFRESHREFRESH is used during normal operation of the DDR2 SDRAM and is analogous to CAS#-before-RAS# (CBR) REFRESH. All banks must be in the idle mode prior to issuing a REFRESH command. This command is nonpersistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a “Don’t Care” during a REFRESH command.SELF REFRESHThe SELF REFRESH command can be used to retain data in the DDR2 SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR2SDRAM retains data without external clocking. All power supply inputs (including Vref)must be maintained at valid levels upon entry/exit and during SELF REFRESH opera-tion.The SELF REFRESH command is initiated like a REFRESH command except CKE is LOW. The DLL is automatically disabled upon entering self refresh and is automatically enabled upon exiting self refresh.Mode Register (MR)The mode register is used to define the specific mode of operation of the DDR2 SDRAM.This definition includes the selection of a burst length, burst type, CAS latency, operat-ing mode, DLL RESET, write recovery, and power-down mode, as shown in Figure 36(page 79). Contents of the mode register can be altered by re-executing the LOADMODE (LM) command. If the user chooses to modify only a subset of the MR variables,all variables must be programmed when the command is issued.The MR is programmed via the LM command and will retain the stored information un-til it is programmed again or until the device loses power (except for bit M8, which is self-clearing). Reprogramming the mode register will not alter the contents of the mem-ory array, provided it is performed correctly.The LM command can only be issued (or reissued) when all banks are in the precharged state (idle state) and no bursts are in progress. The controller must wait the specified time t MRD before initiating any subsequent operations such as an ACTIVATE com-mand. Violating either of these requirements will result in an unspecified operation.2Gb: x4, x8, x16 DDR2 SDRAM Mode Register (MR)AC Overshoot/Undershoot SpecificationTable 26: Address and Control BallsTable 27: Clock, Data, Strobe, and Mask BallsFigure 22: OvershootMaximum amplitudeV DD /V DDQ V SS /V SSQ V o l t s (V )Time (ns)Figure 23: UndershootV SS /V SSQTime (ns)V o l t s (V )Table 28: AC Input Test Conditions2Gb: x4, x8, x16 DDR2 SDRAM AC Overshoot/Undershoot Specification。
MEMORY存储芯片MT48LC16M16A2TG-6A中文规格书
Toggling Static HIGH
0 1 2 3 4
nRAS
0 nRC
nRC + 1 nRC + 2 nRC + 3 nRC + 4
nRC + nRAS
1
1
nRRD + 2
D 100001000F0
–
nRRD + 3
Repeat cycle nRRD + 2 until 2 × nRRD - 1
2
2 × nRRD
Repeat sub-loop 0, use BA[2:0] = 2
3
3 × nRRD
Repeat sub-loop 1, use BA[2:0] = 3
Table 39: DDR3L IDD7 Measurement Loop
CK, CK# CKE
Sub-Loop Cycle Number Command
CS# RAS# CAS# WE# ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data3
Toggling Static HIGH
Notes: 1. DQ, DQS, DQS# are midlevel. 2. DM is LOW. 3. Only selected bank (single) active.
2Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – IDD Specifications and Conditions
MEMORY存储芯片MT48V8M16LFFF-10 ES中文规格书
CAS WRITE LatencyCAS WRITE latency (CWL) is defined by MR2[5:3] as shown in the MR2 Register Defini-tion table. CWL is the delay, in clock cycles, between the internal WRITE command and the availability of the first bit of input data. The device does not support any half-clock latencies. The overall WRITE latency (WL) is defined as additive latency (AL) + parity la-tency (PL) + CAS WRITE latency (CWL): WL = AL +PL + CWL.Low-Power Auto Self RefreshLow-power auto self refresh (LPASR) is supported in the device. Applications requiring SELF REFRESH operation over different temperature ranges can use this feature to opti-mize the I DD6 current for a given temperature range as specified in the MR2 Register Definition table.Dynamic ODTIn certain applications and to further enhance signal integrity on the data bus, it is de-sirable to change the termination strength of the device without issuing an MRS com-mand. This may be done by configuring the dynamic ODT (R TT(WR)) settings in MR2[11:9]. In write leveling mode, only R TT(NOM) is available.Write Cyclic Redundancy Check Data BusThe write cyclic redundancy check (CRC) data bus feature during writes has been added to the device. When enabled via the mode register, the data transfer size goes from the normal 8-bit (BL8) frame to a larger 10-bit UI frame, and the extra two UIs are used for the CRC information.4Gb: x4, x8, x16 DDR4 SDRAM Mode Register 2Logic Equations for a ×8 DeviceDQ0 = MT0DQ5 = MT5DQ1 = MT1DQ6 = MT6DQ2 = MT2DQ7 = MT7DQ3 = MT3DQS_t = MT8DQ4 = MT4DQS_c = MT9Logic Equations for a ×16 DeviceDQ0 = MT0DQ10 = INV DQ2DQ1 = MT1DQ11 = INV DQ3DQ2 = MT2DQ12 = INV DQ4DQ3 = MT3DQ13 = INV DQ5DQ4 = MT4DQ14 = INV DQ6DQ5 = MT5DQ15 = INV DQ7DQ6 = MT6LDQS_t = MT8DQ7 = MT7LDQS_c = MT9DQ8 = INV DQ0UDQS_t = INV LDQS_t DQ9 = INV DQ1UDQS_c = INV LDQS_cCT Input Timing RequirementsPrior to the assertion of the TEN pin, all voltage supplies, including V REFCA , must be val-id and stable and RESET_n registered high prior to entering CT mode. Upon the asser-tion of the TEN pin HIGH with RESET_n, CKE, and CS_n held HIGH; CLK_t, CLK_c, and CKE signals become test inputs within t CTECT_Valid. The remaining CT inputs become valid t CT_Enable after TEN goes HIGH when CS_n allows input to begin sampling, pro-vided inputs were valid for at least t CT_Valid. While in CT mode, refresh activities in the memory arrays are not allowed; they are initiated either externally (auto refresh) or in-ternally (self refresh).The TEN pin may be asserted after the DRAM has completed power-on. After the DRAM is initialized and V REFDQ is calibrated, CT mode may no longer be used. The TEN pin may be de-asserted at any time in CT mode. Upon exiting CT mode, the states and the integrity of the original content of the memory array are unknown. A full reset of the memory device is required.After CT mode has been entered, the output signals will be stable within t CT_Valid after the test inputs have been applied as long as TEN is maintained HIGH and CS_n is main-tained LOW.4Gb: x4, x8, x16 DDR4 SDRAM Connectivity Test Mode。
MEMORY存储芯片MT48V8M16LFFF-8IT中文规格书
The auto precharge feature is engaged when a READ or WRITE command is issued with A10 HIGH. The auto precharge feature uses the RAS lockout circuit to internally delay the PRECHARGE operation until the ARRAY RESTORE operation has completed. The RAS lockout circuit feature allows the PRECHARGE operation to be partially or com-pletely hidden during burst READ cycles when the auto precharge feature is engaged.The PRECHARGE operation will not begin until after the last data of the burst write se-quence is properly stored in the memory array.REFRESH CommandThe REFRESH command (REF) is used during normal operation of the device. This command is nonpersistent, so it must be issued each time a refresh is required. The de-vice requires REFRESH cycles at an average periodic interval of t REFI. When CS_n,RAS_n/A16, and CAS_n/A15 are held LOW and WE_n/A14 HIGH at the rising edge of the clock, the device enters a REFRESH cycle. All banks of the SDRAM must be pre-charged and idle for a minimum of the precharge time, t RP (MIN), before the REFRESH command can be applied. The refresh addressing is generated by the internal DRAM re-fresh controller. This makes the address bits “Don’t Care” during a REFRESH command.An internal address counter supplies the addresses during the REFRESH cycle. No con-trol of the external address bus is required once this cycle has started. When the RE-FRESH cycle has completed, all banks of the SDRAM will be in the precharged (idle)state. A delay between the REFRESH command and the next valid command, except DES, must be greater than or equal to the minimum REFRESH cycle time t RFC (MIN),as shown in Figure 83 (page 146).Note: The t RFC timing parameter depends on memory density.In general, a REFRESH command needs to be issued to the device regularly every t REFI interval. To allow for improved efficiency in scheduling and switching between tasks,some flexibility in the absolute refresh interval is provided for postponing and pulling-in the REFRESH command. A limited number REFRESH commands can be postponed depending on refresh mode: a maximum of 8 REFRESH commands can be postponed when the device is in 1X refresh mode; a maximum of 16 REFRESH commands can be postponed when the device is in 2X refresh mode; and a maximum of 32 REFRESH commands can be postponed when the device is in 4X refresh mode.When 8 consecutive REFRESH commands are postponed, the resulting maximum inter-val between the surrounding REFRESH commands is limited to 9 × t REFI (see Figure 84(page 146)). For both the 2X and 4X refresh modes, the maximum interval between sur-rounding REFRESH commands allowed is limited to 17 × t REFI2 and 33 × t REFI4, re-spectively.A limited number REFRESH commands can be pulled-in as well. A maximum of 8 addi-tional REFRESH commands can be issued in advance or “pulled-in” in 1X refresh mode,a maximum of 16 additional REFRESH commands can be issued when in advance in 2X refresh mode, and a maximum of 32 additional REFRESH commands can be issued in advance when in 4X refresh mode. Each of these REFRESH commands reduces the number of regular REFRESH commands required later by one. Note that pulling in more than the maximum allowed REFRESH commands in advance does not further re-duce the number of regular REFRESH commands required later, so that the resulting maximum interval between two surrounding REFRESH commands is limited to 9 × t RE-FI (Figure 85 (page 146)), 17 × t RFEI2, or 33 × t REFI4. At any given time, a maximum of 16 additional REF commands can be issued within 2 × t REFI, 32 additional REF2 com-4Gb: x4, x8, x16 DDR4 SDRAM REFRESH CommandDLL-On/Off Switching ProceduresThe DLL-off mode is entered by setting MR1 bit A0 to 0; this will disable the DLL for subsequent operations until the A0 bit is set back to 1.DLL Switch Sequence from DLL-On to DLL-OffTo switch from DLL-on to DLL-off requires the frequency to be changed during self re-fresh, as outlined in the following procedure:1.Starting from the idle state (all banks pre-charged, all timings fulfilled, and, to dis-able the DLL, the DRAM on-die termination resistors, R TT(NOM), must be in High-Z before MRS to MR1.)2.Set MR1 bit A0 to 1 to disable the DLL.3.Wait t MOD.4.Enter self refresh mode; wait until t CKSRE/t CKSRE_PAR is satisfied.5.Change frequency, following the guidelines in the Input Clock Frequency Change section.6.Wait until a stable clock is available for at least t CKSRX at device inputs.7.Starting with the SELF REFRESH EXIT command, CKE must continuously be regis-tered HIGH until all t MOD timings from any MRS command are satisfied. In addi-tion, if any ODT features were enabled in the mode registers when self refresh mode was entered, the ODT signal must continuously be registered LOW until all t MOD timings from any MRS command are satisfied. If R TT(NOM) was disabled in the mode registers when self refresh mode was entered, the ODT signal is "Don't Care."8.Wait t XS_FAST, t XS_ABORT, or t XS, and then set mode registers with appropriate values (an update of CL, CWL, and WR may be necessary; a ZQCL command can also be issued after t XS_FAST).•t XS_FAST: ZQCL, ZQCS, and MRS commands. For MRS commands, only CL and WR/RTP registers in MR0, the CWL register in MR2, and gear-down mode in MR3 may be accessed provided the device is not in per-DRAM addressability mode. Access to other device mode registers must satisfy t XS timing.•t XS_ABORT: If MR4 [9] is enabled, then the device aborts any ongoing refresh and does not increment the refresh counter. The controller can issue a valid command after a delay of t XS_ABORT. Upon exiting from self refresh, the device requires a minimum of one extra REFRESH command before it is put back into self refresh mode. This requirement remains the same regardless of the MRS bit setting for self refresh abort.•t XS: ACT, PRE, PREA, REF , SRE, PDE, WR, WRS4, WRS8, WRA, WRAS4, WRAS8,RD, RDS4, RDS8, RDA, RDAS4, and RDAS8.9.Wait t MOD to complete.The device is ready for the next command.4Gb: x4, x8, x16 DDR4 SDRAM DLL-On/Off Switching Procedures。
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Architecture
These devices use NAND Flash electrical and command interfaces. Data, commands,and addresses are multiplexed onto the same pins and received by I/O control circuits.The commands received at the I/O control circuits are latched by a command register and are transferred to control logic circuits for generating internal signals to control de-vice operations. The addresses are latched by an address register and sent to a row de-coder to select a row address, or to a column decoder to select a column address.Data is transferred to or from the NAND Flash memory array, byte by byte (x8) or word by word (x16), through a data register and a cache register.
The NAND Flash memory array is programmed and read using page-based operations and is erased using block-based operations. During normal page operations, the data and cache registers act as a single register. During cache operations, the data and cache registers operate independently to increase data throughput. The status register reports the status of die operations.
Figure 8: NAND Flash Die (LUN) Functional Block Diagram
LOCK Note:
1.The LOCK pin is used on the 1.8V device.
Command Definitions Table 7: Command Set
Table 7: Command Set (Continued)
Notes: 1.Busy means RDY = 0.
2.These commands can be used for interleaved die (multi-LUN) operations (see Interleaved
Die (Multi-LUN) Operations (page 106)).
3.Do not cross plane address boundaries when using READ for INTERNAL DATA MOVE and
PROGRAM for INTERNAL DATA MOVE.
4.These commands supported only with ECC disabled.
5.Issuing a READ PAGE CACHE series (31h, 00h-31h, 3Fh) command when the array is busy
(RDY = 1, ARDY = 0) is supported if the previous command was a READ PAGE (00h-30h)
or READ PAGE CACHE series command; otherwise, it is prohibited.
6.Issuing a PROGRAM PAGE CACHE (80h-15h) command when the array is busy (RDY = 1,
ARDY = 0) is supported if the previous command was a PROGRAM PAGE CACHE
(80h-15h) command; otherwise, it is prohibited.
7.OTP commands can be entered only after issuing the SET FEATURES command with the
feature address.
Table 10: READ ID Parameters for Address 20h
Table 11: Parameter Page Data Structure (Continued)。