NM24C09U中文资料
AT24C1024W-10SU-2.7;AT24C1024Y4-10YU-2.7;AT24C1024W-10SU-2.7 SL383;中文规格书,Datasheet资料
1Features•Low-voltage Operation –2.7 (V CC = 2.7V to 5.5V)•Internally Organized 131,072 x 8•Two-wire Serial Interface•Schmitt Triggers, Filtered Inputs for Noise Suppression •Bidirectional Data Transfer Protocol•400 kHz (2.7V) and 1 MHz (5V) Clock Rate•Write Protect Pin for Hardware and Software Data Protection •256-byte Page Write Mode (Partial Page Writes Allowed)•Random and Sequential Read Modes •Self-timed Write Cycle (5 ms Typical)•High Reliability–Endurance: 100,000 Write Cycles/Page –Data Retention: 40 Years•8-lead PDIP , 8-lead EIAJ SOIC, 8-lead LAP and 8-lead SAP Packages •Die Sales: Wafer Form, Waffle Pack and Bumped DieDescriptionThe AT24C1024 provides 1,048,576 bits of serial electrically erasable and program-mable read only memory (EEPROM) organized as 131,072 words of 8 bits each. The device’s cascadable feature allows up to two devices to share a common two-wire bus. The device is optimized for use in many industrial and commercial applicationswhere low-power and low-voltage operation are essential. The devices are available in space-saving 8-lead PDIP , 8-lead EIAJ SOIC, 8-lead Leadless Array (LAP) and 8-lead SAP packages. In addition, the entire family is available in 2.7V (2.7V to 5.5V)versions.Table 1. Pin ConfigurationsPin Name Function A1Address Input SDA Serial Data SCL Serial Clock Input WP Write Protect NCNo Connect8-lead PDIP8-lead Leadless ArrayBottom View 8-lead SOIC8-lead SAPBottom View2AT24C10241471O–SEEPR–3/07Figure 1. Block DiagramAbsolute Maximum Ratings*Operating Temperature..................................–55°C to +125°C *NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Storage Temperature.....................................–65°C to +150°C Voltage on Any Pinwith Respect to Ground....................................–1.0V to +7.0V Maximum Operating Voltage..........................................6.25V DC Output Current........................................................5.0 mA3AT24C10241471O–SEEPR–3/07Pin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.DEVICE/ADDRESSES (A1): The A1 pin is a device address input that can be hardwired or left not connected for hardware compatibility with other AT24Cxx devices. When the A1 pin is hardwired, as many as two 1024K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). If the A1 pin is left floating, the A1 pin will be internally pulled down to GND if the capacitive coupling to the circuit board V CC plane is <3 pF. If coupling is >3 pF, Atmel recommends connecting the A1 pin to GND.WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP is connected high to V CC , all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND if the capacitive coupling to the circuit board V CC plane is <3 pF. If coupling is >3 pF, Atmel recom-mends connecting the pin to GND. Switching WP to V CC prior to a write operation creates a software write-protect function.MemoryOrganizationAT24C1024, 1024K SERIAL EEPROM: The 1024K is internally organized as 512 pages of 256 bytes each. Random word addressing requires a 17-bit data word address.4AT24C10241471O–SEEPR–3/07Table 2. Pin Capacitance (1)Table 3. DC CharacteristicsNote:1.V IL min and V IH max are reference only and are not tested.Applicable over recommended operating range from T A = 25°C, f = 1.0 MHz, V CC = +2.7VSymbol Test ConditionMax Units Conditions C I/O Input/Output Capacitance (SDA)8pF V I/O = 0V C IN Input Capacitance (A 1, SCL)6pFV IN = 0VApplicable over recommended operating range from: T AI = –40°C to +85°C, V CC = +2.7V to +5.5V, T AC = 0°C to +70°C,V CC = +2.7V to +5.5V (unless otherwise noted)Symbol Parameter Test ConditionMin TypMax Units V CC Supply Voltage 2.75.5V I CC Supply Current V CC = 5.0V READ at 400 kHz 2.0mA I CC Supply Current V CC = 5.0V WRITE at 400 kHz 5.0mA I SB Standby Current V CC = 2.7V V IN = V CC or V SS3.0µA V CC = 5.5V 6.0µA I LI Input Leakage Current V IN = V CC or V SS 0.10 3.0µA I LO Output Leakage CurrentV OUT = V CC or V SS0.053.0µA V IL Input Low Level (1)–0.6V CC x 0.3V V IH Input High Level (1)V CC x 0.7V CC + 0.5V V OL Output Low LevelV CC = 3.0VI OL = 2.1 mA0.4V5AT24C10241471O–SEEPR–3/07Table 4. AC Characteristics (1)R L (connects to V CC ): 1.3 k Ω (2.7V, 5V)Input pulse voltages: 0.3 V CC to 0.7 V CC Input rise and fall times: ≤50 nsInput and output timing reference voltages: 0.5 V CC 2.This parameter is ensured by characterization only.Applicable over recommended operating range from T A = –40°C to +85°C, V CC = +2.7V to +5.5V, C L = 100 pF (unless otherwise noted)Symbol ParameterTest Conditions MinMax Units f SCL Clock Frequency, SCL 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V 1000400kHz t LOW Clock Pulse Width Low 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V 0.41.3µs t HIGH Clock Pulse Width High 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V 0.40.6µs t AA Clock Low to Data Out Valid4.5V ≤ V CC ≤5.5V 2.7V ≤ V CC ≤ 5.5V 0.050.050.550.9µs t BUF Time the bus must be free before a new transmission can start (2) 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V 0.51.3µs t HD.STA Start Hold Time 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V 0.250.6µs t SU.STA Start Setup Time 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V0.250.6µs t HD.DAT Data In Hold Time 0µs t SU.DAT Data In Setup Time 100ns t R Inputs Rise Time (2)0.3µs t F Inputs Fall Time (2) 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V 100300ns t SU.STO Stop Setup Time 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V0.250.6µs t DH Data Out Hold Time 50ns t WRWrite Cycle Time10ms Endurance (2) 5.0V, 25°C, Page Mode 100KWrite Cycles6AT24C10241471O–SEEPR–3/07Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop condition as defined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 5 on page 8).STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the Stop command will place the EEPROM in a standby power mode (see Figure 5 on page 8).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowl-edge that it has received each word.STANDBY MODE: The AT24C1024 features a low-power standby mode which is enabled: a)upon power-up and b)after the receipt of the stop bit and the completion of any internal operations.MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps:1.Clock up to 9 cycles.2.Look for SDA high in each cycle while SCL is high.3.Create a start condition.Device Power Up And Power Down RecommendationPOWER UP: It is recommended to power up from 0V to full VCC in less than 1ms and then hold for at least 100µs at full VCC level before first operation.POWER DOWN: It is recommended to power down from full VCC to 0V in less than 1ms and then hold at 0V for at least 0.5s before power up. It is not recommended to VCC power down to non-zero volt and then slowly go to zero volt.7AT24C10241471O–SEEPR–3/07Figure 2. Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O ®)Figure 3. Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)Note:1.The write cycle time t WR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.Figure 4.Data Validity8AT24C10241471O–SEEPR–3/07Figure 5. Start and Stop DefinitionFigure 6. Output AcknowledgeDevice AddressingThe 1024K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 7 on page 11). The device address word consists of a mandatory one, zero sequence for the first five most significant bits as shown. This is common to all two-wire EEPROM devices.The 1024K uses the one device address bit, A1, to allow up to two devices on the same bus.The A1 bit must compare to the corresponding hardwired input pin. The A1 pin uses an inter-nal proprietary circuit that biases it to a logic low condition if the pin is allowed to float.The seventh bit (P 0) of the device address is a memory page address bit. This memory page address bit is the most significant bit of the data word address that follows. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return to a standby state.DATA SECURITY: The AT24C1024 has a hardware data protection scheme that allows the user to write-protect the entire memory when the WP pin is at V CC.9AT24C10241471O–SEEPR–3/07WriteOperationsBYTE WRITE: To select a data word in the 1024K memory requires a 17-bit word address.The word address field consists of the P 0 bit of the device address, then the most significant word address followed by the least significant word address (see Figure 8 on page 11)A write operation requires the P 0 bit and two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero. The addressing device, such as a microcontroller,then must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, T WR , to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 8 on page 11).PAGE WRITE: The 1024K EEPROM is capable of 256-byte page writes.A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 255 more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must ter-minate the page write sequence with a stop condition (see Figure 9 on page 11).The data word address lower 8 bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 256 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. The address “rollover” during write is from the last byte of the current page to the first byte of the same page.ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero, allowing the read or write sequence to continue.10AT24C10241471O–SEEPR–3/07ReadOperationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations:current address read, random address read and sequential read.CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “rollover”during read is from the last byte of the last memory page, to the first byte of the first page.Once the device address with the read/write select bit set to one is clocked in and acknowl-edged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condi-tion (see Figure 10 on page 11).RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition.The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a fol-lowing stop condition (see Figure 11 on page 12).SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-dom address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will con-tinue. The sequential read operation is terminated when the microcontroller does not respond with a zero, but does generate a following stop condition (see Figure 12 on page 12).分销商库存信息:ATMELAT24C1024W-10SU-2.7AT24C1024Y4-10YU-2.7AT24C1024W-10SU-2.7SL383。
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品牌产品型号芯片配置海尔2晶10芯IC:HI2023E+1108+5812海尔高清OST-666 2晶6芯IC:M88VS2000+241674K.1+M88TS2020海尔高清OST-666 3晶12芯IC:High032E+His121+M88TS2020海尔3晶10芯(9针接口)IC:HI2023E+1108+5812+ESMTM12L64164A-GNR1T80AB 海尔高清OST-666 2晶6芯IC:Hi2023E+3160+TS2020欧视达ABS-209B 3晶10芯IC:GX3001+GX1121+LW37 欧视达ABS-209B 3晶11芯IC:GX3001+5037+8211欧视达ABS-309B 3晶11芯IC:GX3001+GX1121+MGCE5037欧视达AS-900S 1晶11芯IC:GX6121+25L80+LW37城市之宝BEX868 Y32S-93AT 2晶10芯IC:HTV903F+A VL1108+TS2020通达Y35S-8BAT/Y35S-8CAT 2晶10芯IC:HTV903+A VL1108+5812通达Y30S-01BT 2晶12芯IC:HTV903+A VL1108+2020 皇朝HSR-268 10芯IC:Hi2023+A VL1108+5812小霸王TDX-668E ABS-S1 1晶6芯IC:Hi2023+Hi3102+FT8211+HT1117天地星小霸王TDX-328B 1晶10芯IC:ALi M3328F+5810天地星小霸王TDX-668A (9针接口)IC:HI2023+1108+夏普头天地星小霸王TDX-668B 2晶振IC:HTV903+A VL1108EGA+RDA5812+25L8005天地星小霸王(三星数码王)TDX-668B 单晶6芯.针脚定义①-TXD ②-RXD ③VCC ④-GND ⑤-BL IC:Hi2023E+RDA5812+A VL1108E+MXT8211a+25L8005天地星（原大盒中星九号）3晶IC:Hi2023+1108+5037天地星TDX-668B 2晶10芯IC:Hi2023+A VL1108+5812天地星小霸王TDX-668C 2晶6芯IC:HTV903+A VL1108EGA+RDK5812+25F80小霸王TDX-328B 1晶10芯IC:ALi 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2晶6芯IC:Hi2023E+Hi3122+A V2020 松下高清OST168 2晶10芯IC:Hi2023E+Hi3121+A V2020 松下科技PS-228 11芯IC:Hi2023+Hi3122+5812松下科技PS-228 2晶6芯IC:M88VS2000+M88TS2020+ES261474K松下科技PS-228 1晶12芯N88VS2000+ES261344K+M88TS2020高频头+T25P80+S163816STS松下科技PS-228 2晶IC:HTV903+1108+2020松下科技PS-228 2晶10芯IC:GX3001+GX1211+5812松下数码王OST-266 10芯(4针)针脚定义①-GND ②-RXD ③-TXD ④VCCIC:Hi2023E+Hi3106+2020松下数码王OST-266 2晶6芯IC:M88VS2000+M88TS2020+261414k+25F80松下数码王OST-266 2晶6芯IC:Hi2023E+Hi3102E+M88TS2020+MXT8211松下高清OST-466 2晶10芯IC:Hi2023e+Hi3121+MBBTS2020+MBDA80CG松下科技星3晶6芯IC:Hi2023+A VL1108+WGCE5037松下科技星.海尔数码.海信数码单双晶+6芯IC:Hi2023E+Hi3102(3121)+5812中星科技单晶14芯IC:Hi2023E+1108+5812+25L8单晶14芯中星科技ZG-N02 12芯IC:GX3001+A V2020中星科技2晶10芯针脚定义①-GND ②-RXD ③-TXD ④VCCIC:Hi2023EC+Hi3102E+5812+M12L64164A中兴科技ABS-S323 2晶10芯IC:Hi2023EC+HI3102E+5812+M12L64164A村村通ABS-S323- 2晶10芯针脚定义①-GND ②-RXD ③-TXD ④VCCIC:Hi2023EC+Hi3122E+5812村村通2晶6芯IC:HN4+0001+5812村村通ZL5188 1晶13芯IC:HTV903+1108+SHARP高频头村村通ZL-5188A 2晶11芯IC:HTV903+A VL1108+RDK5812村村通ZL-5188B 2晶13芯IC:HTV903+A VL1108+RDK5812 村村通ZL-5188B 2晶10芯IC:HTV903+A VL1108EGA+5812村村通ZL5188B 1晶13芯IC:HTV903+A V1108+SHARP6306村村通ZJ-11 IC:HTV903+1108+夏普头S7ZH6306村村通wx-666 3晶10芯IC:GX3001+GX1121+RDK5812村村通ZL-6188 2晶10芯IC:HTV903+A VL1108EGA+5812村村通ZL-6188C 10芯IC:GX3001+GX1121+RDK5812村村通DTH(铁壳) 3晶12芯IC:A VL1108EG+HTV903F+A V2020村村通001 3晶10芯IC:GX3001+GX1121+RDK5812村村通ABS-S GD-1008 3晶10芯IC:Hi2023E+A VL1108E+ZL10037+F16-100HIP村村通ABS-S888AIC:Hi2023EC+Hi3121+ET8211+RDA5812+25X80视美人ABS-S PS-1288 2晶10芯IC:Hi3102E+Hi2023EC+A V2020视美人PS-1288 ICM88VS2000+ES256454K+M88TS2020 视美人2晶10芯IC:Hi2023+3106+A V2020太平鸟HJ321 3晶10芯针脚定义①-GND .②-RXD .③-TXD .④VCCIC:GX3001+GX1121+TS2020太平鸟HJ321 3晶11芯IC:GX3001+GX1121+5812焦点yj5888 2晶10芯IC:HTV903+A VL1108+RDA5812幸运之星YJ5988 2晶10芯IC:HTV903F+A VL1108EGa+A V2020克莱尔HT701 1晶10芯IC:A VL1108EG+HTV903F+M88TS2000中电电子J-6288 ABS-S 3晶12芯IC:GX3001+GX1121+5812小福星3晶11芯针脚定义①-GND .②-(空) .③-RXD .④-TXD (）IC:GX3001+GX1121+5812东仕DIS-2000K 单晶10芯IC:HTV903F+A VL1108E+A V2020Souy Ericsson英文机2晶10芯IC:GX3001+GX1121+A V2020高斯贝尔/歌德威尔ABS-208F 3晶14芯针脚定义①-GND .②-TXD .③-RXD .④VCC .⑤-BL IC:A VL1108EG+Hi2023+5812高斯贝尔ABS-208 1晶14芯(5针).针脚定义①-GND .②-TXD .③-RXD .④VCC .⑤-BL IC:A VL1108EG+Hi2023+5812歌德威尔ABS-208H/高斯贝尔208P 3晶14芯针脚定义①-GND .②-TXD .③-RXD .④VCCIC:M3330E+A VL1108EG+A V2020+M12L64164高斯贝尔ABS-208P/歌德威尔208H 1晶14芯针脚定义①-GND .②-TXD .③-RXD .④VCC .⑤-BL IC:A VL1108EGi+Hi2023+5812高斯贝尔ABS-208P/歌德威尔208H 1晶14芯针脚定义①-GND .②-TXD .③-RXD .④VCCIC:M3330E+A VL1108EG+A V2020+M12L64164A高斯贝尔ABS—208F IC:Hi2023+A VL1108EGA+M88TS2020高斯贝尔ABS—208 2晶14芯IC:HTV903+1108+5812吉祥ABS-208C IC:Hi2023+A VL1108EGa+GST GAIM-18R ABS-STUNER吉祥ABS-2009B 3晶14芯IC:GX3001+GX1121+RDK5812吉祥ABS-2009大铁壳2晶IC:GX3001+GX1121+夏普高频头ABS-2009 2晶12芯IC:HTV903+1108+GAIM-18R歌德威尔ABS-208 3晶6芯IC:D61216GJ+1108+5812歌德威尔ABS-208 3晶14芯(9针接口)IC:M3330+1108+5812高斯贝尔ABS-208 3晶(9针母串口)IC:A VL1108+Hi2023+GAIM-18RIC:D61216GJ100+A VL1108EG+S29AL016D70TF102+ISSI高斯贝尔ABS-208N 铁壳(9针母串口) IC42s16400F高斯贝尔ABS-208 IC:D61216GJ+A V1108+29AL016D+5812高斯贝尔ABS-208S 1晶IC:NECD61216GJ+A VL1108EGa+高频头高斯贝尔ABS-208Q 1晶14芯IC:A VL1108EGA+M3330E+M12L64164A+A V2020ABS-S LX-3688A 1晶12芯IC:GX3001+GX1121+5812现代V4、V5 3晶9芯IC:GX3001+GX1121+5812+EN25D80+HY57V641620ETP-6 集信科技V6铁壳(海尔机芯) 3晶9芯针脚定义①VCC .②-TXD .③-RXD .④-GNDIC:1108EG(Hi3121)+Hi2023+5812.集信科技V4.V6(铁壳) 2晶9芯( B型)针脚定义①VCC .②-RXD .③-TXD .④-GNDIC:0001(GX3001)+HN4F74+5812集信科技V4 .V6(铁壳) 2晶10芯针脚定义①VCC. ②-RXD .③-TXD .④-GNDIC:00001(GX3001)+HN4LSW+S6416AHTA+5812集信科技V4.V6(铁壳)IC:HN4LSW+S6416AHTA-6BZH+EN25F80-1000CP+5812集信科技V4.V6(铁壳)IC:0002P1M43700ta06+5812+EN25F80+TM8211+POL4558 集信科技V4.V5 1晶10芯(A型)针脚定义①VCC .②-RXD .③-TXD .④-GNDIC:0002(GX6121)+5812+M12L64164A艾雷特2晶10芯IC:M88VS2000+ES256454K+M88TS2020艾雷特V5IC:HN4F910931M2EE+0001G1K729-1TA060932+5812艾雷特ALT5812 IC:GX3001+GX1121+5812艾雷特ALT600A 2晶11芯IC:M3330E+A VL108的+夏普高频头艾雷特ALT600A/吉祥ABS-2009 2晶IC:GX3001+GX1121-ES29L160FB+SHARP高频头艾雷特ALT600GIC:HTV903+A VL1108+25L160+ST2020(Y32S-8BAT 081113)艾雷特ALT6812 1晶10芯IC:GX6121+RDA5812+ZB-1A艾雷特ALT6815 1晶10芯IC:GX6121-RDA5812-2B-1A艾雷特ALT7815 3晶10芯IC:GX3001+1121+TS2020艾雷特1000 黑珍珠V4.V5 1晶10芯IC:0002(GX6121)+EEPLDA+5812+M12L64164A艾雷特alt 7812 3晶10芯IC:GX3001+GX1121+5812艾雷特ALT7812 3晶11芯针脚定义①VCC .②-RXD .③-TXD .④-GNDIC:GX3001+GX1121+5812艾雷特ALT600c 2晶10芯IC:GX3001+GX1121+5812艾雷特ALT600c 2晶11芯IC:GX3001+GX1121+5812艾雷特ALT600c 1晶11芯IC:CH216H+A VL1108+C6XS-8CA深圳亿通DVB-V5 10芯IC:HN4N46+EN25F80+G1N540-1TA06+IS42S16400-7T+581亿通电子WS-3688ZL 1晶10芯IC:Hi2023EC+Hi3102E+A V2020中大WS-3688ZJ (铁壳) 1晶10芯针脚定义①-GND .②-RXD .③-TXD .④VCCIC:Hi2023EC+Hi3102E+A V2020中大WS-3688ZJ (铁壳) 2晶10芯IC:Hi2023+A VL1108EG+夏普高频头皇视HSR-208A 2晶10芯IC:Hi2023E+A VL1108EG+A V2020皇视HSR-208B 2晶10芯IC:Hi2023+1108+2020皇视HSR-208B 单晶10芯IC:3330+1108+2020皇视HSR-208B 单晶10芯针脚定义①-GND ②-TXD ③-RXD ④-VCCIC:Hi2023EC+Hi3102+A V2020皇视HSR-2090 2晶11芯IC:Hi2023+1108EGa+夏普头++EN29LV160皇视HSR-210A 单晶6芯IC:Hi2023ec+Hi3122e+A V2020 皇视HSR-260A 铁盒2晶10芯IC:Hi+1108+SHARP夏普头皇视HRS-268 3晶10芯IC:Hi2023EC+Hi3102E+A V2020 皇视HRS-268 2晶10芯IC:Hi2023EC+Hi3121+5812皇视HSR-268 单晶10线IC:HTV903+A VL1108+5812皇视HSR-268 单晶10线IC:Hi2023+Hi3121+A V2020皇视HRS-268 3晶10芯IC:Hi2023EC+A VL1108+5812皇视HSR-260B 3晶10芯IC:Hi2023+1108+2020皇视HSR-260B/索尼高清258 1晶10芯IC:2023E+3121+A V2020皇视HSR-260B 3晶10芯IC:HI2023+1108+5812皇朝HSR-268 10芯IC:Hi2023+A VL1108+5812凯恩斯KES-2066S 6芯针脚定义①-TXD .②-RXD .③VCC .④-GND .⑤-BL IC:Hi3122E+Hi2023ECE+N25F80凯恩斯KES-2077Z 1晶6芯针脚定义①-TXD .②-RXD .③VCC .④-GND .⑤-BL IC:Hi2023EC+3122E+5812凯恩斯2077ABS 2晶10芯IC:M3330+A VL1108+5812凯恩斯2077ABS 2晶10芯IC:Hi2023+1108E+5812+25L800凯恩斯KES-2088S 2晶6芯IC:Hi2023EC+HI3102E+RDA5812凯恩斯KES-2088S 2晶10芯IC:Hi2023EC+HI3102E+RDA5812凯恩斯KES-2088S 2晶6芯针脚定义①-TXD .②-RXD .③VCC .④-GND .⑤-BL IC:Hi2023EC+HI3122E+RDA5812凯恩斯KES-2088Z (5针).针脚定义①-TXD .②-RXD .③VCC .④-GND .⑤-BL IC:Hi2023EC+HI3102E+RDA5812凯恩斯KES-2099S 2晶6芯IC:Hi2023EC+Hi3102E+5812+25L80凯恩斯KES-2188T 3晶10芯IC:Hi2023+1108+5812凯恩斯KES-2188T 3晶12芯IC:Hi2023+1108E+5037凯恩斯KES-2288S 3晶10芯IC:M3330E+A VL1108+RDA5812+M12L64164A凯恩斯KES-2688b 2晶10芯IC:Hi2023e+1108e+5812 凯恩斯KES-2688S 2晶10芯IC:Hi2023e+1108e+5812凯恩斯KES-2788S 3晶10芯IC:Hi2023E+A VL1108EGa+5812凯恩斯KES-2788S 2晶6芯IC:Hi2023EC+Hi3122E+5812凯恩斯KES-5188 11芯IC:HTV903+A VL1108EGA+A V2020凯恩斯KES-5188A铁盒2晶10芯IC:HTV903F+A VL1108+RDK5812+F80+PT8211凯恩斯KES-5188B 2晶13芯IC:HTV903+RDA5812+A VL1108+8211+F80美路3晶13芯IC:Hi2023E+1108+2119美路2晶12芯IC:GX3003+GX1121+5812美路MR-1809 IC:Hi2023E+A VL1108E+高频头MAX2119C 美路MR-5598铁壳3晶12芯IC:GX3003+GX1121+5812 美路MR-5598 3晶12芯针脚定义①VCC. ②-RXD .③-TXD .④-GNDIC:Hi2023E+1108+2119C美路-5798 IC:Hi2023E+1108+2119C美路-5598 IC:Hi2023+1108+GAIM-18R+29lv160ZY 5518A 2晶10芯IC:Hi2023E+3102E+5812万利达ZY-5518A 1晶6芯((5针))IC:Hi2023E+Hi3102E+5812万利达ZY-5518A 2晶10芯IC:CX3001+GX1121+5812万利达ZY-5518A 3晶10芯(9针接口)IC:Hi2023+1108+5812长虹新一代3晶10芯IC:HI2023E+1108E+FL016ALF长虹新一代，海尔数码、海信数码单双晶体6芯IC:HI2023E+3102(3121)+5812长虹数码CH930 3晶12芯IC:HTV903F+1108+A V2020+M80长虹精品TC-6688ABS 2晶10芯IC:HTV903+A VL1108EG+5812长虹精工YJ5978 1晶10芯IC:HTV903F+1108EGa+2000+F80-100+8211长虹KES-2099S 2晶5芯IC:Hi2023+Hi3102E+5812长虹KES 2晶6芯IC:Hi2023+Hi3102+5812长虹CH920 3晶6芯IC:HTV903F+1108EGa+A V2020+25L80航天天信WTD198J 2晶12芯(9针接口)IC:GX3001+GX1121+5812+ES29LV160FB-70TG航天珠江WTD-198J 2晶12芯IC:GX3001+GX1121+5812 航天珠江ABS-209B IC:GX3001+GX1121++WGSE5037航天数码ABS-3809 2晶12芯IC:GX3001+GX1121+5812航天直播HT-168 3晶12芯IC:Hi2023+1108+夏普头航天高清王-HS-166 2晶12芯IC:Hi2023EC+Hi3102E+RDA5812航天高清王HS-169 2晶12芯针脚定义①-GND .②-TX .③-RX .④-VCCIC:Hi2023EC+3122+5812天诚TCD-219ABS 2晶10芯IC:M3330E+A VL1108EGA+5812天诚TCD-299Z 2晶10芯IC:Hi2023+3206+5812天诚TD-299Z 2晶5芯IC:Hi2023+3206+5812天诚TD-2992 2晶6芯IC:Hi3122E+Hi2023E+5812+F80+MXT8211天诚539 2晶10芯IC:HTV903+A V1108+5812天诚519型2晶10芯IC:HTV903+1108E+5812天诚TCD-239ABS 3晶10芯IC:M3330+1108+5812 天诚TCD-239ABS 2晶10芯IC:Hi2023+1108E+5812 天诚TCD-239 2晶10芯IC:M3330E+1108E+5812天诚TCD-299ABS 2晶10芯IC:Hi2023EC+Hi3121+5812天诚TCD-319ABS 3晶10芯IC:Hi2023E0914+A VL1108EGa+RDA5812天诚TCD-319ABS 3晶12芯IC:Hi2302+A VL1108+5037 天诚TCD-369ABS 3晶10芯IC:Hi2023+1108+5812天诚TCD-369ABS 3晶10芯IC:M3330E+1108+5812天诚TCD-369ABS 3晶5芯IC:Hi2023+1108+WCGE5037天诚TCD-509ABS 3晶10芯IC:M3330E-A VL1108EGa-5812天诚TCD-509ABS 10芯(5针)IC:Hi2023+A VL1108+5812+M12L6416A天诚TCD-539ABS 2晶10芯(5针)针脚定义①-RX .②-TX .③VCC .④-GND .⑤-BLIC:M3330E+A VL1108+25L80+5812天诚TCD-579ABS 2晶10芯IC:Hi2023+Hi1108+5812天诚TCD-579ABS 3晶10芯IC:HiM3330+A VL1108EGa+RDA5812天诚TCD-589ABS 3晶10芯IC:Hi2023+1108+5812天诚TCD-689ABS铁壳机2晶12芯(9针接口)IC:Hi2023+A VL1108+夏普头天诚TC-ABS1108A 11芯IC:Hi2023EC+A VL1108+5812 TCD--239ABS 2晶10芯IC:M3330E+A VL1108E+5812 TCD-339ABS 3晶10芯(9针接口) IC:Hi2023+1108+5812TCD-509ABS 3晶10芯IC:Hi2023E0915+A VL1108EGa+RDA5812TCD-509ABS 2晶10芯(5针) IC:Hi2023EC+HI3121+5812TCD-519ABS 2晶10芯IC:Hi2023+A VL1108+5812TCD-599 2晶10芯IC:M3330+A VL1008+5812TCD-219ABS 2晶振10芯针脚定义①-TXD .②-RXD .③-VCC .④-GND .⑤-BLIC:Hi2023EC+Hi3121+5812爱普思DVB-2568 3晶10芯IC:HTV903+1121+2020卓异5518A 3晶10芯IC:Hi2023E+1108+5812卓异5518A(铁壳)3晶11芯IC:Hi2023E+1108+5812卓异5518A(铁壳)2晶11芯(9针接口) IC:Hi2023+1108+夏普独立高频头卓异5518A G 1晶10芯爱百信针脚定义①-GND .②-TXD .③-RXD .④VCCIC:HTV903+A VL1108+5812卓异ZY-5518A G 驰骋天下针脚定义①-GND .②-RXD .③-TXD .④VCCIC:HTV903+A VL1108+5812+F80卓异5518AG 2晶11芯针脚定义①-GND .②-RXD .③-TXD .④VCC ⑤-BL IC:Hi2023E+1108+5812卓异ZY-5518A H 春1晶6芯针脚定义①-GND .②-TXD .③-RXD .④VCCIC:GX3001+5812+25L8005卓异ZY-5518A H 春2晶10芯针脚定义①-GND .②-TXD .③-RXD .④VCC .⑤-BLIC:Hi2023E+HI3121+5812+F25L008A卓异ZY-5518A H 秋针脚定义①-GND .②-RXD .③-TXD .④VCC 升级接口在内部PCB上IC:GX6121+5812+F80卓异ZY-5518A H 秋1晶10芯针脚定义①-GND .②-RXD .③-TXD .④VCC ⑤-BLIC:Hi2023EC+Hi3102E+5812+F80-100卓异ZY-5518A H至尊王牌2晶10芯针脚定义①-GND .②-TXD .③-RXD .④VCCIC:GX3001+GX1121+5812+25L8005卓异ZY-5518A H 财富2晶6 芯针脚定义①-GND .②-TXD .③-RXD .④VCC .⑤-BLIC:芯片掩磨+5812+80L100绿达PS-1288 3晶12芯IC:Hi2023E+ABS090520+M88TS2020绿达PS-1288 2晶12芯IC:Hi2023+Hi3021+A V2020绿达视美人\卓异1晶10芯IC:Hi2023EC+Hi3121+2020 绿达金统帅3晶10芯IC:M3330+1108+5812三星DQ88/DQ66 IC:HTV903F+A VL1108+A V2020三星高清王2晶12芯IC:GX3001+GX1121+5812三星高清DQ88 3晶12芯IC:HTV903F+A VL1108+A V2020 三星数码王TDX668B 2晶6芯针脚定义①-RXD .②-TXD .③-GND .④VCC. ⑤-BLIC:Hi2023+1108+5812三星数码王TDX668B 2晶6芯IC:HTV903F+A VL1108E+5812三星数码王668C 2晶6芯IC:HTV903F+A VL1108E+5812三星数码王TDX668E 1晶6芯IC:Hi2023EC+3102C+5812三星HSR-208C 1晶10芯IC:Hi2023E+Hi3102+MXT8211+A V2020+F25L08pA三星小霸王ABS-S 2009 2晶10芯IC:CX3001+CX1121+5812三星小霸王2900 (9针接口)IC:Hi2023E+A VL1108+MAX2119三星王国-KL6350 1晶11芯IC:HTV903+A VL1108EGa+EDA5812开门红KSP638 2晶10芯IC:HTV903F+A VL1108E+A V2020开门红KSP638 1晶10芯IC:CT216H+A VL1108EGa+A V2020日立创新TDX-668B 2晶6芯针脚定义①-RXD .②-TXD .③-GND .④VCC. ⑤-BLIC:Hi2023+A VL1108+5812志高之星HS166 2晶12芯IC:Hi3102+Hi2023+5812志高之星HS169 2晶12芯IC:Hi2023EC+Hi3012E+RDA5812A+EM638165TS-6G金牛ABS-1108 3晶10芯IC:Hi2023+1108+5812小灵通2晶6线IC:Hi2023+1108+5812福临门ABS-S 3晶9线IC:GX1121+GX3001+5812C60S-93AT 单晶10芯IC:CT216H+A VL1108EGa+A V2020 ABS-2301 单晶10芯针脚定义①-GND.②-TXD.③-RX .④VCCIC:Hi2023EC+Hi3211E+5812+25L8005其乐达CT216 2晶10芯IC:CT216+1108+A V2020科海6228 1晶11芯IC:HTV903+A VL1108EGa+RDa5812+25X16A VSIG科海6228-CT216H 1晶11芯IC:CT216H+1108EGa+M88TS2020科海C623S-91AT 单晶10芯IC:CT210H+A VL1108+2020 科海炫彩6888 IC:HTV903+A VL1108EGa+RDa5812科海2888（小天使）2晶10芯IC:HTV903+A VL1108EGa+RDa5812大旗920 3晶12芯IC:HTV903+A VL1108+A V2020大旗DQ920 3晶12芯IC:GX3001+GX1121+5812+25X16 大旗930 3晶12芯IC:HTV903+A VL1108+A V2020众昌电子ABS--2088 2晶10芯IC:Hi2023+A VL1108+5812众昌电子ABS-2087 2晶10芯IC:M3330+A VL1108+5812 创维S600 3晶IC:M3330E+A VL1108E+5812创维新一代3晶10芯IC:Hi2023E+1108+5037+FL016A 中广通XC-B188 3晶12芯IC:GX3001+GX1121+5812深圳知音ABSTAR KT-2309 3晶10芯IC:Hi2023+A VL1108E+5812知音科技ABSTAR KT1028H 2晶振10芯IC:Hi2023+A VL1108+GST GAIM-18R铁壳ABS-2009 2晶11芯IC:Hi2023+1108+夏普头王牌数码OST-366 2晶6芯针脚定义①-GND ②-RXD .③-TXD .④VCCIC:Hi3102+Hi2023EC+A V2020王牌数码王GM-ABS1108A 2晶10芯针脚定义①-GND .②-TXD .③-RXD .④VCCIC:GX3001+GX1121+5812+25L8005王牌数码王GM-ABS1108A 10芯IC:Hi2023+A VL1108+5812JIXIANG ABS-208 2晶14芯(9针接口)IC:Hi2023+1108+GST GAIM-18R ABS TUNER 夏普头JIXIANG-ABS208 2晶IC:D6121+1108+GST高频头East Star 2晶10芯IC:M3330-1108-GST GAIM-18R高频头小福星abs 2008 3晶12芯IC:GX3001+GX1211+5812通达C60S-93AT/C62S-91AT 1晶10芯IC:CT216H+A VL1108E+2020威特斯ZL-5188A 2晶13芯IC:HTV903+A VL1108+RDK5812威特斯ZL-5188B 2晶11芯IC:GX3001+GX1121+5812迷你星3晶13芯IC:GX3001+GX1121+5812+F16-100HIP高星HS-312 3晶12芯IC:GX3001+GX1121+5812北大高科3晶9芯IC:GX3001+GX1211+5812思达科ABS-S 801型2晶10芯IC:GX3001+GX1121+5810思达科ABS-S 802G 2晶10芯IC:GX3001+GX1211+5812思达科ABS-S 803A 1晶10芯IC:A VL1118+A V2020+25D80V思达科ABS-S 803G IC:GX3001+GX1211+5812思达科ABS-S 806H IC:GX3001+GX1211+5812思达科ABS-S 806H IC:A VL1118+A V2020+DSD4M16G思达科ABS-S 806H IC:HN4J7G+G2A954+5812+25X80思达科ABS-S807 1晶5芯IC:A VL1118a+A V2020+806H金霸王JBW-6688 2晶11芯IC:HTV903F+A VL1108EGa+A V2020+8211金霸王JBW-6688 IC:GX3001+GX1211+5812阿德尔ADE-168 IC:HY903+A VL1108EG+A V2020阿德尔ADE131金刚IC:HTV903F+A VL1108E+M88TS2020 海西小霸王TD299Z 2晶6芯IC:Hi2023E+Hi3122+5812 同洲CY-668S 1晶12芯IC:HM1512+1108+5812喜旺ABS5398 IC:Hi2023+1108E+MAX2119C喜旺ABS-5798 12芯IC:GX3001+GX1211+5812喜旺ABS-3809 2晶12芯IC:GX3001+GX1121+RDA5812希旺598 2晶12芯(9针接口) IC:Hi2023+1108+SHRP 高频头彩虹视霸CY84 1晶10芯IC:HTV903F+A VL1108+M88TS2020彩虹视霸A10S-9AAT 1晶10芯IC:A VL1118+SM42S16400B1-7+F80九洲村村通DVS-398F IC:CT216H+ALV1108+SHRP高频头金星ABS-208 1晶14芯IC:Hi2023+A VL1108+铁壳高频头威克2晶6芯(5针) IC:HTV903+1108+5812华尔HR731A1 3晶12芯IC:CX3001+CX1121+SHARP高频头爱普斯3晶9芯IC:HTV903+A V2020+A VL1108EG爱普斯2568 3晶10芯IC:HTV903+A V2020+A VL1108EG 爱普斯IC:GX3001+GX1211+A V2020+2J10X未来视佳ADEI88 3晶9芯IC:HTV903F+A V2020+A VL1108EG黑金刚TRT006 1晶10芯IC:A VL1118+A V2020+4558+F80-100DX-668 2晶10芯针脚定义①-RXD .②-TXD .③VCC .④-GND .⑤-BLIC:Hi2023EC_Hi3102E+5812+F80-100傲天海-吉祥2晶12芯针脚定义①-GND ②-RXD ③-TXD ④VCCIC:GX3001+GX1121+RDA5812高频头+P8075火星漫步LJ6008 1晶10芯IC:HTV903F+A VL1108+M88TS2020+F80-100王牌新一代TD-299Z针脚定义①- . ②-TXD .③-RXD .④-GND ⑤-IC:Hi2023E+Hi3122+5812王牌HJ360 3晶10芯IC:GX1120+GX3001+TS2020TVWALKER ABS-2008 1晶6芯IC:D61216GJ+1108E+SHARP头吉祥988 (ZJ-111) 1晶11芯IC:HTV903 +1108+高频头北京北电科林3晶12芯IC:Hi2023+A VL1108EGa+SHARP高频头家家福BEX811 1晶10芯IC:24645K2+M88VS2000+M88TS2020家家福ADE158 IC:HTV903+A VL1108+M88TS2020华星科技2晶IC:Hi2023+A VL1108+5812亚视达ABR-S(H11) 2晶10芯IC:HTV903+1108E+A V2020HSTAR 3晶10芯IC:Hi2023+A VL1108EGa+M88IS2020长江电讯ABS-2008型铁壳(9针接口)IC:D61216GJ+A VL1108EG+夏普头全家福3晶IC:Hi2023E+A VL1108EG+M88TS2020 畅想BEX818 1晶10芯IC:HTV903+A VL1108+A V2020 必佳GF-901 2晶10芯针脚定义①-GND .②-RXD .③-TXD .④VCCIC:HTV903+1108+A V2020KSP600G 飓风(华亚) 2晶10芯针脚定义①-GND ②-TXD ③-RXD ④VCCIC:HTV903+1108+M88TS2020+25D80万家乐TB002 (5针)IC:Hi2023EC+Hi3102E+M88TS2020+25X80A V万家乐2晶6芯IC:M3330+ALi1108+5812+F80-75奥伟科技ABS-800 3晶(9针接口)IC:GX3001+GX1121+5812奥伟科技ABS-900E 2晶12芯IC:CT216+A VL1108+独立高频头GAIR-08R天眼HSTER3晶10芯IC:Hi2023E+A VL1108+5812飞翔ADE351 2晶10芯IC:HTV903F+A VL1108EG+M88TS2000星视通XC-B268 1晶10芯IC:HTV903+A VL1108+5812星视通XC-C268 1晶11芯IC:HTV903 A VL1108 5812奥维科技ABS-600 3晶12芯IC:GX3001+GX1121+A V2020 超的个人论坛转载分享本资源。
24c02中文官方资料手册pdf
ｗ 址输入脚 A0 A1 A2 可悬空或连接到 Vss 如果只有一个 24WC01 被总线寻址 这三个地址输入
脚 A0 A1 A2 必须连接到 Vss
当使用 24WC04 时最多可连接 4 个器件 该器件仅使用 A1 A2 地址管脚 A0 管脚未用 可以连
符号
参数
最小
典型
最大 单位
测试条件
ICC 电源电流
3
mA
FSCL=100KHz
ISB ILI ILO VIL VIH VOL1 VOL2
备用电流(Vcc=5.0V) 输入漏电流 输出漏电流 输入低电压 输入高电压 输出低电压 输出低电压
1 Vcc 0.7
0
A
10
A
10
A
Vcc 0.3 V
Vcc+0.5 V
s
tHD: DAT
数据输入保持时间
0
0
ns
tSUl: DAT
数据输入建立时间
50
50
ns
tR
SDA 及 SCL 上升时间
1
0.3
s
tF
SDA 及 SCL 下降时间
300
300
ns
tSU: STO
停止信号建立时间
4
0.6
s
tDH
数据输出保持时间
100
100
ns4Biblioteka 海纳电子资讯网： ｗｗｗ．ｆｐｇａ－ａｒｍ．ｃｏｍ
上电时序
符号
参数
最大
单位
tPUR
上电到读操作
1
NM24C08中文资料
Pin Names
A2 VSS SDA SCL NC VCC Device Address Input Ground Serial Data I/O Serial Clock Input No Connection Power Supply
Dual-in-Line Package (N), SO Package (M8) and TSSOP Package (MT8)
NOTE: Pins designated as "NC" are typically unbonded pins. However some of them are bonded for special testing purposes. Hence if a signal is applied to these pins, care should be taken that the voltage applied on these pins does not exceed the VCC applied to the device. This will ensure proper operation.
Connection Diagrams
Dual-in-Line Package (N), SO Package (M8) and TSSOP Package (MT8)
NC NC A2 VSS 1 2 8 7 VCC NC SCL SDA
DS500071-2
NM24C08
3 4 6 5
See Package Number N08E, M08A and MTC08
2
NM24C08/09 Rev. G
元器件交易网
NM24C08/09 – 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
AT24C04A-10TE-2.7中文资料
1Features•Write Protect Pin for Hardware Data Protection –Utilizes Different Array Protection Compared to the AT24C02/04/08/16•Medium-voltage and Standard-voltage Operation –5.0 (V CC = 4.5V to 5.5V)–2.7 (V CC = 2.7V to 5.5V)•Internally Organized 256 x 8 (2K), 512 x 8 (4K), 1024 x 8 (8K) or 2048 x 8 (16K)•Two-wire Serial Interface•Schmitt Trigger, Filtered Inputs for Noise Suppression •Bidirectional Data Transfer Protocol •400 kHz (2.7V, 5V) Clock Rate•8-byte Page (2K), 16-byte Page (4K, 8K, 16K) Write Modes •Partial Page Writes Allowed•Self-timed Write Cycle (5 ms Max)•High Reliability–Endurance: One Million Write Cycles –Data Retention: 100 Years•Automotive Grade, Extended Temperature, and Lead-Free/Halogen-Free Devices Available•8-lead PDIP , 8-lead JEDEC SOIC, and 8-lead TSSOP PackagesDescriptionThe AT24C02A/04A/08A/16A provides 2048/4096/8192/16384 bits of serial electri-cally erasable and programmable read-only memory (EEPROM) organized as 256/512/1024/2048 words of 8 bits each. The device is optimized for use in many automotive applications where low-power and low-voltage operation are essential.The A T24C02A/04A/08A/16A is available in space-saving 8-lead PDIP , 8-lead JEDEC SOIC, and 8-lead TSSOP packages and is accessed via a two-wire serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V) version.Table 1. Pin Configurations2AT24C02A/04A/08A/16A5083A–SEEPR–9/04Figure 1. Block DiagramPin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that must be hardwired for the AT24C02A. As many as eight 2K devices may be addressed on a single bus system. (Device addressing is discussed in detail under Device Addressing, page 9).The AT24C04A uses the A2 and A1 inputs for hardwire addressing, and a total of four 4K devices may be addressed on a single bus system. The A0 pin is a no-connect.Absolute Maximum Ratings**NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.3AT24C02A/04A/08A/16A5083A–SEEPR–9/04The AT24C08A only uses the A2 input for hardwire addressing, and a total of two 8K devices may be addressed on a single bus system. The A0 and A1 pins are no-connects.The AT24C16A does not use the device address pins, which limits the number of devices on a single bus to one. The A0, A1, and A2 pins are no-connects.WRITE PROTECT (WP): The AT24C02A/04A/08A/16A have a WP pin that provides hardware data protection. The WP pin allows normal read/write operations when con-nected to ground (GND). When the WP pin is connected to V CC , the write protection feature is enabled and operates as shown. (See Table 1.)Table 1. Write ProtectMemory OrganizationAT24C02A, 2K SERIAL EEPROM: The 2K is internally organized with 32 pages of 8bytes each. Random word addressing requires an 8-bit data word address.AT24C04A, 4K SERIAL EEPROM: The 4K is internally organized with 32 pages of 16bytes each. Random word addressing requires a 9-bit data word address.AT24C08A, 8K SERIAL EEPROM: The 8K is internally organized with 64 pages of 16bytes each. Random word addressing requires a 10-bit data word address.AT24C16A, 16K SERIAL EEPROM: The 16K is internally organized with 128 pages of 16 bytes each. Random word addressing requires an 11-bit data word address.Note:This parameter is characterized and is not 100% tested.Table 2. Pin Capacitance4AT24C02A/04A/08A/16A5083A–SEEPR–9/04Note:1.V IL min and V IH max are reference only and are not tested.Table 3. DC CharacteristicsApplicable over recommended operating range from: T AE = −40°C to +125°C, V CC = +2.7V to +5.5V5AT24C02A/04A/08A/16A5083A–SEEPR–9/04Note:1.This parameter is characterized and is not 100% tested (T A = 25°C).2.This parameter is characterized and is not 100% tested.Table 4. AC CharacteristicsApplicable over recommended operating range from T AE = −40°C to +125°C, V CC = +2.7V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted).6AT24C02A/04A/08A/16A5083A–SEEPR–9/04Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-nal device. Data on the SDA pin may change only during SCL low time periods (see Figure 2). Data changes during SCL high periods will indicate a start or stop condition as defined in Figure 2.Figure 2. Data ValiditySTART CONDITION: A high-to-low transition of SDA with SCL high is a start condition that must precede any other command (see Figure 3).Figure 3. Start and Stop DefinitionSTOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 3).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a “0” to acknowledge that it has received each word. This happens during the ninth clock cycle.STANDBY MODE: The AT24C02A/04A/08A/16A features a low-power standby mode that is enabled (a) upon power-up and (b) after the receipt of the STOP bit and the com-pletion of any internal operations.7AT24C02A/04A/08A/16A5083A–SEEPR–9/04MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps:1.Clock up to 9 cycles.2.Look for SDA high in each cycle while SCL is high.3.Create a start condition as SDA is high.Figure 4. Bus TimingFigure 5. Write Cycle TimingNote:The write cycle time t WRis the time from a valid stop condition of a write sequence to the end of the interval clear/write cycle.8AT24C02A/04A/08A/16A5083A–SEEPR–9/04Figure 6.Output Acknowledge9AT24C02A/04A/08A/16A5083A–SEEPR–9/04Device AddressingThe 2K, 4K, and 8K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation, as shown in Figure 7.Figure 7. Device AddressThe device address word consists of a mandatory “1”, “0” sequence for the first four most significant bits as shown. This is common to all the EEPROM devices.The next three bits are the A2, A1, and A0 device address bits for the 2K EEPROM.These three bits must compare to their corresponding hardwired input pins.The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their corre-sponding hardwired input pins. The A0 pin is no-connect.The 8K EEPROM only uses the A2 device address bit with the next two bits being for memory page addressing. The A2 bit must compare to its corresponding hardwired input pin. The A1 and A0 pins are no-connect.The 16K EEPROM does not use the device address pins, which limits the number of devices on a single bus to one. The A0, A1, and A2 pins are no-connects.The eighth bit of the device address is the read/write operation select bit. A read opera-tion is initiated if this bit is high, and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made, the chip will return to a standby state.Write OperationsBYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgement. Upon receipt of this address, the EEPROM will again respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a “0” and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time,the EEPROM enters an internally-timed write cycle, t WR , to the nonvolatile memory. All inputs are disabled during this write cycle, and the EEPROM will not respond until the write is complete, as shown in Figure 8.10AT24C02A/04A/08A/16A5083A–SEEPR–9/04Figure 8. Byte WritePAGE WRITE: The 2K EEPROM is capable of an 8-byte page write, and the 4K, 8K,and 16K devices are capable of 16-byte page writes.A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven (2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a “0”after each data word received. The microcontroller must terminate the page write sequence with a stop condition, as shown in Figure 9.Figure 9. Page WriteThe data word address lower three (2K) or four (4K, 8K, 16K) bits are internally incre-mented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address,internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight (2K) or sixteen (4K, 8K, 16K) data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten.ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-ing a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a “0” allowing the read or write sequence to continue.11AT24C02A/04A/08A/16A5083A–SEEPR–9/04Read OperationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to “1”. There are three read operations: current address read, random address read and sequential read.CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first page. The address “roll over” during write is from the last byte of the cur-rent page to the first byte of the same page.Once the device address with the read/write select bit set to “1” is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out.The microcontroller does not respond with an input “0” but does generate a following stop condition, as shown in Figure 10.Figure 10. Current Address ReadRANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a “0” but does generate a following stop condition, as shown in Figure 11.Figure 11. Random ReadSEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequen-tial read will continue. The sequential read operation is terminated when the12AT24C02A/04A/08A/16A5083A–SEEPR–9/04microcontroller does not respond with a “0” but does generate a following stop condition,as shown in Figure 12.Figure 12.Sequential Read13AT24C02A/04A/08A/16A5083A–SEEPR–9/04Note:For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables (Table 3 on page 4 and Table 4 on page 5).AT24C02A Ordering Information14AT24C02A/04A/08A/16A5083A–SEEPR–9/04Note:For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables (Table 3 on page 4 and Table 4 on page 5).AT24C04A Ordering Information15AT24C02A/04A/08A/16A5083A–SEEPR–9/04Note:For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables (Table 3 on page 4 and Table 4 on page 5).AT24C08A Ordering Information16AT24C02A/04A/08A/16A5083A–SEEPR–9/04Note:For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table (Table 3 on page 4 and Table 4 on page 5).AT24C16A Ordering Information17AT24C02A/04A/08A/16A5083A–SEEPR–9/04Packaging Information8P3 – PDIP18AT24C02A/04A/08A/16A5083A–SEEPR–9/048S1 – JEDEC SOIC19AT24C02A/04A/08A/16A5083A–SEEPR–9/048A2 – TSSOP5083A–SEEPR–9/04Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise,to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL ’S TERMS AND CONDI-TIONS OF SALE LOCATED ON ATMEL ’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.Atmel CorporationAtmel Operations2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 487-2600Regional HeadquartersEuropeAtmel SarlRoute des Arsenaux 41Case Postale 80CH-1705 Fribourg SwitzerlandTel: (41) 26-426-5555Fax: (41) 26-426-5500AsiaRoom 1219Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong KongTel: (852) 2721-9778Fax: (852) 2722-1369Japan9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JapanTel: (81) 3-3523-3551Fax: (81) 3-3523-7581Memory2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 436-4314Microcontrollers2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 436-4314La Chantrerie BP 7060244306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18Fax: (33) 2-40-18-19-60ASIC/ASSP/Smart CardsZone Industrielle13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00Fax: (33) 4-42-53-60-011150 East Cheyenne Mtn. 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AT24c02最全的中文资料
CA T24C 161/162(16K)，CAT24C081 /082(8K) CAT24C041/042(4K)，CAT24C021/022(2K)I2C串行CMOS E2PROM,精确的复位控制器和看门狗定时器控制电路特性•数据线上的看门狗定时器(仅对CA T24Cxxl)籲可编程复位门槛电平籲高数据传送速率为400KHz和I2C总线兼容• 2.7V至6V的工作电压•低功耗CMOS工艺籲16字节页写缓冲区籲片内防误擦除写保护籲高低电平复位信号输出——精确的电源电压监视器——可选择5V、3.3V和3V的复位门槛电平•100万次擦写周期•数据保存可长达100年•8脚DIP或SOIC封装•商业级、工业级和汽车温度范围概述CA T24Cxxx是集E2PROM存储器，复位微控制器和看门狗定时器三种流行功能与一体的芯片。
CAT24C161/162 (16K)，CAT24C081/082 (8K)，CA T24C041/042 (4K)和CAT24C021/022 (2K)以I2C是串行CMOS E2PROM器件。
釆用CMOS工艺大降低了器件的功耗。
CA T24Cxxx 另一特点是16字节的页写缓冲区，提供8脚DIP和SOIC 封装。
CA T24Cxxx的复位功能和看门狗定时器功能保证系统出现故障的时候能给CPU —个复位信号。
CA T24Cxxx 的2脚输出低电平复位信号，7脚输出高电平复位信号。
CAT24Cxxl看狗溢出信号从SDA脚输出。
CAT24Cxx2不具备看门狗功能。
绝对最大参数工作温度：-55°C〜125°C贮存温度：-65°C〜15°C各管脚承受对地电压：-2.0V〜Vcc+2.0V VCC对地电压范围：-2.0V〜7.0V 最大功耗： 1.0W管脚焊接温度(10S): 300 °C输出短路电流：100mA管脚配置]V C C ]RESET方框图表一直流操作特性表二上电时序管脚介绍WP：写保护将该管脚接Vcc，E2PRON就实现写保护（只读)。
NUC微控制器产品系列说明书
M251 Feature
。 Arm® Cortex®-M23 。 运行速度可达 48 MHz
M252 Feature
。 USB 2.0 全速设备无需外 挂晶振
M253 Feature
。 USB 2.0 全速设备无需外 挂晶振
。 高达五路 UART 。 CAN FD x1
2
Low Power
TrustZone
AEC-Q100
Market Trend
随着电子应用对低功耗或电池供电的需 求日益增加，现今的应用必须尽量降低 能源消耗，甚至在极端情况下，可能需 要倚赖单颗电池来维持长达 15 至 20 年 运转
低功耗应用情景包含手持式设备、居家、 AIoT、IIoT (工业物联网) 等应用情景， 使用范围十分广泛
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*USCI: Universal Serial Control Interface Controller
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1.8 3.3 5 M253
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3.3 5 M071
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3.3 5 M051
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1.8 3.3 Nano100
M480 M460 M471 M453 M452 M451
E CU E CU
U C
U
Arm9™
AT24C512B_08中文资料
AT24C512B_08中文资料FeaturesLow-voltage and Standard-voltage Operation–1.8v (V CC = 1.8V to 3.6V)–2.5v (V CC = 2.5V to 5.5V)?Internally Organized 65,536 x 8?Two-wire Serial InterfaceSchmitt Triggers, Filtered Inputs for Noise Suppression ?Bidirectional Data Transfer Protocol1 MHz (2.5V , 5.5V), 400 kHz (1.8V) CompatibilityWrite Protect Pin for Hardware and Software Data Protection ?128-byte Page Write Mode (Partial Page Writes Allowed)?Self-timed Write Cycle (5 ms Max)?High Reliability–Endurance: 1,000,000 Write Cycles –Data Retention: 40 Years ?Lead-free/Halogen-free Devices8-lead PDIP , 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP , 8-ball dBGA2, and 8-lead Ultra Thin Small Array (SAP) PackagesDie Sales: Wafer Form, Waffle Pack and Bumped DieDescriptionThe AT24C512B provides 524,288 bits of serial electrically erasable and programma-ble read only memory (EEPROM) organized as 65,536 words of 8 bits each. The device’s cascadable feature allows up to eight devices to share a common two-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space-saving 8-pin PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP,8-ball dBGA2 and 8-lead Ultra Thin SAP packages. In addition, the entire family is available in 1.8V (1.8V to 3.6V) and 2.5V (2.5V to 5.5V) versions.T able 0-1.Pin ConfigurationsPin Name Function A0–A2Address Inputs SDA Serial Data SCL Serial Clock Input WPWrite ProtectRev. 5297A–SEEPR–1/08Two-wire Serial EEPROM512K (65,536 x 8)AT24C512Bwith Three Device Address Inputs8-lead PDIP8-lead TSSOPBottom View8-lead SOIC8-ball dBGA2Bottom View25297A–SEEPR–1/08AT24C512BFigure 0-1.Block Diagram Absolute Maximum Ratings*Operating T emperature..................................–55°C to +125°C *NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Storage T emperature.....................................–65°C to +150°C Voltage on Any Pinwith Respect to Ground....................................–1.0V to +7.0V Maximum Operating Voltage ..........................................6.25V DC Output Current........................................................5.0 mA35297A–SEEPR–1/08AT24C512B1.Pin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices.DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hardwired (directly toGND or to Vcc) for compatibility with other AT24Cxx devices.When the pins are hardwired, as many as eight 512K devices may be addressed on a single bus system. (Device addressing is discussed in detail under “Device Addressing,” page 8.) A device is selected when a corresponding hardware and software match is true. If these pins are left floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capaci-tive coupling that may appear during customer applications, Atmel ? recommends always connecting the address pins to a known state. When using a pull-up resistor, Atmel recommends using 10k Ω or less.WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP is connected directly to Vcc, all write operations to the memory are inhib-ited. If the pin is left floating, the WP pin will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel rec ommends using 10k Ω or less.45297A–SEEPR–1/08AT24C512B2.Memory OrganizationAT24C512B, 512K SERIAL EEPROM: The 512K is internally organized as 512 pages of 128-bytes each. Random word addressing requires a 16-bit data word address.Note:1.This parameter is characterized and is not 100% tested.Note:1.V IL min and V IH max are reference only and are not tested.Table 2-1.Pin Capacitance (1)Applicable over recommended operating range from: T A = 25°C, f = 1.0 MHz, V CC = +1.8V to +5.5VSymbol Test ConditionMax Units Conditions C I/O Input/Output Capacitance (SDA)8pF V I/O = 0V C IN Input Capacitance (A 0, A 1, SCL) 6pFV IN = 0VTable 2-2.DC CharacteristicsApplicable over recommended operating range from: T AI = –40°C to +85°C, V CC = +1.8V to +5.5V (unless otherwise noted) Symbol Parameter Test ConditionMin TypMax Units V CC1Supply Voltage 1.8 3.6V V CC2Supply Voltage 2.55.5V I CC Supply Current V CC = 5.0V READ at 400 kHz 2.0mAI CC Supply Current V CC = 5.0V WRITE at 400 kHz 3.0mA I SB1Standby CurrentV CC = 1.8V V IN = V CC or V SS1.0μA V CC = 3.6V 3.0μA I SB2Standby Current V CC =2.5V V IN = V CC or V SS2.0μA V CC = 5.5V 6.0μA I LI Input Leakage Current V IN = V CC or V SS 0.10 3.0μA I LO Output Leakage CurrentV OUT = V CC or V SS0.053.0μA V IL Input Low Level (1)–0.6V CC x 0.3V V IH Input High Level (1)V CC x 0.7V CC + 0.5V V OL1Output Low Level V CC = 1.8V I OL = 0.15 mA 0.2V V OL2Output Low LevelV CC = 3.0VI OL = 2.1 mA 0.4V55297A–SEEPR–1/08AT24C512BNotes:1.This parameter is ensured by characterization only.2.AC measurement conditions:R L (connects to V CC ): 1.3 k Ω (2.5V , 5V), 10 k Ω (1.8V)Input pulse voltages: 0.3 V CC to 0.7 V CC Input rise and fall times: ≤ 50 nsInput and output timing reference voltages: 0.5 V CCTable 2-3.AC Characteristics (Industrial Temperature)Applicable over recommended operating range from T AI = ?40°C to +85°C, V CC = +1.8V to +5.5V, CL = 100 pF (unless oth-erwise noted). Test conditions are listed in Note 2.Symbol Parameter1.8-volt2.5, 5.0-volt Units MinMax MinMax f SCL Clock Frequency, SCL 4001000kHz t LOW Clock Pulse Width Low 1.30.4μs t HIGH Clock Pulse Width High 0.60.4μs t i Noise Suppression Time (1)10050ns t AA Clock Low toData Out Valid 0.050.90.050.55μs t BUF Time the bus must be free before a new transmission can start (1) 1.30.5μs t HD.ST A Start Hold Time 0.60.25μs t SU.ST A Start Set-up Time 0.60.25μs t HD.DA T Data In Hold Time 00μs t SU.DAT Data In Set-up Time 100 100ns t R Inputs Rise Time (1)0.30.3μs t F Inputs Fall Time (1)300 100ns t SU.STO Stop Set-up Time 0.60.25μs t DH Data Out Hold Time 5050ns t WRWrite Cycle Time 55ms Endurance (1)25°C, Page Mode, 3.3V1,000,000Write Cycles65297A–SEEPR–1/08AT24C512B3.Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device.Data on the SDA pin may change only during SCL low time periods (see Figure 3-4 on page 8).Data changes during SCL high periods will indicate a start or stop condition as defined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 3-5 on page 8).STOP CONDITION: A low-to-high transition of SDA with SCLhigh is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Fig-ure 3-5 on page 8).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowl-edge that it has received each word.STANDBY MODE: The AT24C512B features a low power standby mode which is enabled: a)upon power-up and b) after the receipt of the STOP bit and the completion of any internal operations.Software Reset: After an interruption in protocol, power loss or system reset, any 2-wire part can be protocol reset by following these steps: (a) Create a start bit condition, (b)clock 9 cycles, (c) create another start bit followed by stop bit condition as shown below.The device is ready for next communication after above steps have been completed.Figure 3-1.Protocol Reset Condition75297A–SEEPR–1/08AT24C512BFigure 3-3.Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)Note:1.The write cycle time t WRis the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.85297A–SEEPR–1/08AT24C512BFigure 3-4.Data ValidityFigure 3-5.Start and Stop DefinitionFigure 3-6.Output Acknowledge95297A–SEEPR–1/08AT24C512B4.Device AddressingThe 512K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 6-1 on page 10). The device address word con-sists of a mandatory “1”, “0” sequence for the f irst four most significant bits as shown. This is common to all two-wire EEPROM devices.The 512K uses the three device address bits A2, A1, A0 to allow as many as eight devices on the same bus. These bits must compare to their corresponding hardwired input pins. The A2, A1and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float.The eighth bit of the device address is the read/writeoperation select bit. A read operation is ini-tiated if this bit is high and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made,the device will return to a standby state.DATA SECURITY: The AT24C512B has a hardware data protection scheme that allows the user to Write Protect the whole memory when the WP pin is at V CC .5.Write OperationsBYTE WRITE: A write operation requires two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a “0”. The addressing device, such as a microcontroller, then must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, t WR , to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 6-2 on page 10).PAGE WRITE: The 512K EEPROM is capable of 128-byte page writes.A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 127 more data words. The EEPROM will respond with a “0” after each data word received. The microcontroller must termi-nate the page write sequence with a stop condition (see Figure 6-3 on page 11).The data word address lower 7 bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the follow-ing byte is placed at the beginning of the same page. If more than 128 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. The address roll over during write is from the last byte of the current page to the first byte of the same page.ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The Read/Write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a “0”, allowing the read or write sequence to continue.105297A–SEEPR–1/08AT24C512B6.Read OperationsRead operations are initiated the same way as write operations with the exception that the Read/Write select bit in the device address word is set to “1”. There are three read operations:current address read, random address read and sequential read.CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by “1”. This address stays validbetween operations as long as the chip power is maintained. The address roll over during read is from the last byte of the last memory page, to the first byte of the first page.Once the device address with the Read/Write select bit set to “1” is clocked in and acknowl-edged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input “0” but does generate a following stop condition (see Figure 6-4 on page 11).RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the Read/Write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a “0” but does generate a following stop condition (see Figure 6-5 on page 11).SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-dom address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will roll over and the sequential read will continue. The sequential read operation is terminated when the micr ocontroller does not respond with a “0” but does generate a following stop condition (see Figure 6-6 on page 11).Figure 6-1.Device AddressFigure 6-2.Byte Write115297A–SEEPR–1/08AT24C512BFigure 6-3.Page WriteFigure 6-4.Current Address ReadFigure 6-5.Random ReadFigure 6-6.Sequential Read125297A–SEEPR–1/08AT24C512BNotes: 1.“-B” denotes bulk2.“-T” denotes tape and reel. SOIC = 4K per reel. TSSOP and dBGA2 = 5K per reel. SAP = 3K per reel. EIAJ = 2K per reel.3.Available in tape and reel, and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request.Please contact Serial Interface Marketing.Ordering InformationOrdering CodeVoltage Package Operation RangeA T24C512B-PU (Bulk form only) 1.88P3Lead-free/Halogen-free/Industrial Temperature (–40°C to 85°C)A T24C512B-PU25 (Bulk form only) 2.58P3A T24C512BN-SH-B (1) (NiPdAu Lead Finish) 1.88S1A T24C512BN-SH-T (2) (NiPdAu Lead Finish) 1.88S1A T24C512BN-SH25-B (1) (NiPdAu Lead Finish) 2.58S1A T24C512BN-SH25-T (2) (NiPdAu Lead Finish) 2.58S1A T24C512BW-SH-B (1) (NiPdAu Lead Finish) 1.88S2A T24C512BW-SH-T (2) (NiPdAu Lead Finish) 1.88S2A T24C512BW-SH25-B (1) (NiPdAu Lead Finish) 2.58S2A T24C512BW-SH25-T (2) (NiPdAu Lead Finish) 2.58S2A T24C512B-TH-B (1) (NiPdAu Lead Finish) 1.88A2A T24C512B-TH-T (2) (NiPdAu Lead Finish) 1.88A2A T24C512B-TH25-B (1) (NiPdAu Lead Finish) 2.58A2A T24C512B-TH25-T (2) (NiPdAu Lead Finish) 2.58A2A T24C512BY7-YH-T (2) (NiPdAu Lead Finish) 1.88Y7A T24C512BY7-YH25-T (2) (NiPdAu Lead Finish) 2.58Y7A T24C512BU2-UU-T (2) 1.88U2-1A T24C512B-W-11(3)1.8Die SaleIndustrial Temperature (–40°C to 85°C)Package Type8P38-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 8S18-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)8S28-lead, 0.200” Wide Plastic Gull Wing Small Outline Package (EIAJ SOIC)8A28-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)8Y78-lead, 6.00 mm x 4.90 mm Body, Ultra Thin, Dual Footprint, Non-leaded, Small Array Package (SAP)8U2-1 8-ball, die Ball Grid Array Package (dBGA2)Options–1.8Low-voltage (1.8V to 3.6V)–2.5Low-voltage (2.5V to 5.5V)135297A–SEEPR–1/08AT24C512B7.Part marking scheme:7.18-PDIP(1.8V)7.28-PDIP(2.5V)TOP MARKSeal YearY = SEAL YEARWW = SEAL WEEK | Seal Week6: 2006 0: 2010 02 = Week 2 | | |7: 2007 1: 2011 04 = Week 4 |---|---|---|---|---|---|---|---| 8: 2008 2: 2012 :: : :::: : A T M L U Y W W 9: 2009 3: 2013 :: : :::: :: |---|---|---|---|---|---|---|---| 50 = Week 50 2 F B 152 = Week 52|---|---|---|---|---|---|---|---| * Lot NumberLot Number to Use ALL Characters in Marking |---|---|---|---|---|---|---|---| |BOTTOM MARKPin 1 Indicator (Dot)No Bottom MarkTOP MARKSeal YearY = SEAL YEARWW = SEAL WEEK | Seal Week6: 2006 0: 2010 02 = Week 2 | | |7: 2007 1: 2011 04 = Week 4 |---|---|---|---|---|---|---|---| 8: 2008 2: 2012 :: : :::: : A T M L U Y W W 9: 2009 3: 2013 :: : :::: :: |---|---|---|---|---|---|---|---| 50 = Week 50 2 F B 252 = Week 52|---|---|---|---|---|---|---|---| * Lot NumberLot Number to Use ALL Characters in Marking |---|---|---|---|---|---|---|---| |BOTTOM MARKPin 1 Indicator (Dot)No Bottom Mark145297A–SEEPR–1/08AT24C512B7.38-SOIC(1.8V)7.48-SOIC(2.5V)TOP MARKSeal YearY = SEAL YEARWW = SEAL WEEK | Seal Week6: 2006 0: 2010 02 = Week 2 | | |7: 2007 1: 2011 04 = Week 4 |---|---|---|---|---|---|---|---| 8: 2008 2: 2012 :: : :::: : A T M L H Y W W 9: 2009 3: 2013 :: : :::: :: |---|---|---|---|---|---|---|---| 50 = Week 50 2 F B 152 = Week 52|---|---|---|---|---|---|---|---| * Lot NumberLot Number to Use ALL Characters in Marking |---|---|---|---|---|---|---|---| |BOTTOM MARKPin 1 Indicator (Dot)No Bottom MarkTOP MARKSeal YearY = SEAL YEARWW = SEAL WEEK | Seal Week6: 2006 0: 2010 02 = Week 2 | | |7: 2007 1: 2011 04 = Week 4 |---|---|---|---|---|---|---|---| 8: 2008 2: 2012 :: : :::: : A T M L H Y W W 9: 2009 3: 2013 :: : :::: :: |---|---|---|---|---|---|---|---| 50 = Week 50 2 F B 252 = Week 52|---|---|---|---|---|---|---|---| * Lot NumberLot Number to Use ALL Characters in Marking |---|---|---|---|---|---|---|---| |BOTTOM MARKPin 1 Indicator (Dot)No Bottom Mark155297A–SEEPR–1/08AT24C512B7.58-TSSOP(1.8V)7.68-TSSOP(2.5V)TOP MARKPin 1 Indicator (Dot)Y = SEAL YEAR WW = SEAL WEEK |6: 2006 0: 2010 02 = Week 2 |---|---|---|---| 7: 2007 1: 2011 04 = Week 4 * H Y W W 8: 2008 2: 2012 :: : :::: : |---|---|---|---|---| 9: 2009 3: 2013:: : :::: :: 2 F B 1 * 50 = Week 50|---|---|---|---|---|52 = Week 52BOTTOM MARK|---|---|---|---|---|---|---|Country of originC 0 0|---|---|---|---|---|---|---| A A A A A A A |---|---|---|---|---|---|---| <- Pin 1 IndicatorTOP MARKPin 1 Indicator (Dot)Y = SEAL YEAR WW = SEAL WEEK |6: 2006 0: 2010 02 = Week 2 |---|---|---|---| 7: 2007 1: 2011 04 = Week 4 * H Y W W 8: 2008 2: 2012 :: : :::: : |---|---|---|---|---| 9: 2009 3: 2013:: : :::: :: 2 F B 2 * 50 = Week 50 |---|---|---|---|---| 52 = Week 52BOTTOM MARK|---|---|---|---|---|---|---|Country of originC 0 0|---|---|---|---|---|---|---| A A A A A A A |---|---|---|---|---|---|---| <- Pin 1 Indicator165297A–SEEPR–1/08AT24C512B7.78-Ultra Thin SAP (1.8V)7.88-Ultra Thin SAP (2.5V)TOP MARKSeal Year| Seal Week Y = SEAL YEARWW = SEAL WEEK | | |6: 2006 0: 2010 02 = Week 2 |---|---|---|---|---|---|---|---| 7: 2007 1: 2011 04 = Week 4 A T M L H Y W W 8: 2008 2: 2012 :: : :::: : |---|---|---|---|---|---|---|---| 9: 2009 3: 2013:: : :::: :: 2 F B 150 = Week 50 |---|---|---|---|---|---|---|---| 52 = Week 52Lot Number|---|---|---|---|---|---|---|---| * |Pin 1 Indicator (Dot)TOP MARKSeal Year| Seal Week Y = SEAL YEARWW = SEAL WEEK | | |6: 2006 0: 2010 02 = Week 2 |---|---|---|---|---|---|---|---| 7: 2007 1: 2011 04 = Week 4 A T M L H Y W W 8: 2008 2: 2012 :: : :::: : |---|---|---|---|---|---|---|---| 9: 2009 3: 2013:: : :::: :: 2 F B 250 = Week 50 |---|---|---|---|---|---|---|---| 52 = Week 52Lot Number|---|---|---|---|---|---|---|---| * |Pin 1 Indicator (Dot)175297A–SEEPR–1/08AT24C512B7.8dBGA2TOP MARKLINE 1-------> 2FBU LINE 2-------> YMTC|<-- Pin 1 This Corner P = Country of OriginY = ONE DIGIT YEAR CODE 4: 2004 7: 20075: 2005 8: 20086: 2006 9: 2009M = SEAL MONTH (USE ALPHA DESIGNATOR A-L) A = JANUARY B = FEBRUARY " " """"""" J = OCTOBER K = NOVEMBERL = DECEMBERTC = TRACE CODE (ATMEL LOT NUMBERS TO CORRESPOND WITH ATK TRACE CODE LOG BOOK)188.Package Information U2-1 - dBGA2195297A–SEEPR–1/08AT24C512B8P3 – PDIP。
24C0224C04中文资料
概述
CAT24WC01/02/04/08/16 是 一 个 1K/2K/4K/8K/16K 位 串 行 CMOS E2PROM
128/256/512/1024/2048 个 8 位字节 CATALYST 公司的先进 CMOS 技术实质上减少了器件的功耗 CAT24WC01 有一个 8 字节页写缓冲器 CAT24WC02/04/08/16 有一个 16 字节页写缓冲器 该器件通过 I2C 总线接口进行操作 有一个专门的写保护功能
目 录
1 CSI24WC0 1/02/04/08/16 ……………………………….2-10 2 CSI24WC32/64…………………………………………...11-18 3 CSI24WC128. ……………………………..…………….19-26 4 CSI24WC256. ………………………….….…………….27-34
6
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1 个 CAT24WC16 可单独被系统寻址 从器件 8 位地址的最低位 作为读写控制位 进行读操作 0 表示对从器件进行写操作
1 表示对从器件
图2
写周期时序
w
图3 起始/停止时序
. w w
s u mc
n c . y
器件寻址
主器件通过发送一个起始信号启动发送过程 然后发送它所要寻址的从器件的地址 8 位从器件地 址的高 4 位固定为 1010 见图 5 接下来的 3 位 A2 A1 A0 为器件的地址位 用来定义哪个器件 以及器件的哪个部分被主器件访问 上述 8 个 CAT24WC01/02 4 个 CAT24WC04 2 个 CAT24WC08
OMEGA CN9300, CN9400, CN9500 和 CN9600 系列控制器产品说明书
Load
The relay output is allocated to SP1 and wired to switch the load (heater) using a contactor
Common Mode Rejection:
Specifications
Power: 100 to 240 Vac, ±10%, 50 to 60 Hz, 4 VA; optional 12 or 24 Vac/Vdc, ±20%, 50 to 60 Hz, 4 VA polarity is not required; the controllers are fitted with an internal 250 mA time lag fuse
CN9400/CN9600 Dual Display: Lower Display: 9 mm (0.35") orange LED output indicators-flashing SP1: Square green SP2: Round red SP3: 2nd round red (CN9600 only)
CN9600 Series Unique Features U Multi Ramp and Soak:
31 Programs, 126 Segments U Assured Soak U mA or V Linear Inputs U mA or V Linear Outputs U Three Outputs Standard U Analog Retransmission U High Accuracy ±0.1% Display of Linear Input
CN9300, CN9400, CN9500 Linear
EXC-24CG900U;中文规格书,Datasheet资料
7. Category Temperature Range -40 to +85 °C
Constitution Mar. 1, 2006
Circuit Components Business Unit Panasonic Electronic Devices Co., Ltd.
/
Humidity
Humidity Load Life
Constitution Mar. 1, 2006
Bending Strength
No abnormality of appearance Impedance variation: within ±30 %
45
45
2
Vibration
Directions: 2 h each in X, Y, and Z directions (Total: 6 h) Frequency range: 10 to 55 to 10 Hz (Sweep rate: 1 min) Amplitude: 1.5 mm
2. Dimensions in mm (not to scale)
E F C A B D
A 1.25±0.15 (.049±.006)
B 1.00±0.15 (.039±.006)
C 0.5±0.1 (.02±.004)
D 0.20±0.15 (.008±.006)
E 0.55±0.10 (.022±.004)
151XC24C06009 Date of Issue : March 06.2006 Digi Key
Classification : New
Issue No.
:
Changed
PRODUCT SPECIFICATION FOR APPROVAL
AT24C1024介绍
AT24C10242 线串行EEPROM特性低电压操作：2.7（Vcc=2.7V to 5.5V）内部组织：131,072*8 位=1M2 线串行接口施密特触发器，噪声抑制滤波输入双向数据传输协议时钟速率：400kHz(2.7V)和1MHz(5V) 硬件写保护引脚和软件数据保护256 字节页写模式(允许部分页面写入)随机和顺序读写模式自定义写周期(5ms)高可靠性：耐久力：写周期/页100,000 次数据保留：40 年8 引脚PDIP，8 引脚有铅SOIC 封装，8 引脚无铅阵列和8 引脚球状dBGA 封装描述AT24C1024 提供1,048,567 位的串行可电擦除和可编程只读存储器（EEPROM），它的每8 位组成一个字节，共131,072 个字节。
该设备的级联功能允许多达2 个设备共亨同一条2- 线总线。
该设备适合用于许多工业和商业，应用必要的低功耗和低电压的操作。
该器件可提供节省空间的8 引脚PDIP，8 引脚有铅SOIC 封装，8 引脚无铅阵列和8 引脚球状dBGA 封装。
另外，这一系列产品允许在2.7V（2.7V~5.5V）下工作。
绝对最大额定值：工作温度：-55~+125存储温度：-65~+150任何引脚的对地电压：-1.0V~+7.0V最大工作电压：6.25V 直流输出电流：5.0mA注意：强制高出“绝对最大额定值”可能导致设备的永久损坏。
设备的压力等级和功能操作只有在这些或超出本规范所标明的其他任何条件下是不允许的。
长时间工作在绝对最大额定值的条件下可能影响设备的可靠性。
引脚描述：串行时钟（SCL）：SCL 的输入是在时钟的上升沿数据进入每个EEPROM 设备和下降沿数据输出每个设备。
串行数据（SDA）：SDA 引脚是双向串行数据传输的。
这个引脚是漏极输出的，可以与其它的漏极开路或集电极开路的设备线或。
器件/ 页地址（A1 ）：A1 引脚是设备的输入地址，它能够通过导线与不兼容的设备AT24C128/256/512 连接。
Belling BL24CM1A 1M位 EEPROM 产品说明书
Features⚫Compatible with all I2C bidirectional data transfer protocol⚫Memory array:–1024 Kbits (128 Kbytes) of EEPROM–Page size: 256 bytes–Additional Write lockable page⚫Single supply voltage and high speed:–⚫Random and sequential Read modes⚫Write:–Byte Write within 5 ms–Page Write within 5 ms–Partial Page Writes Allowed⚫Write Protect Pin for Hardware Data Protection ⚫Schmitt Trigger, Filtered Inputs for Noise Suppression⚫High-reliability–Endurance: 4 Million Write Cycles–Data Retention: 100 Years⚫Enhanced ESD/Latch-up protection–HBM 8000V⚫8-lead PDIP/SOP/TSSOP/UDFN/WLCSP packagesDescription⚫The BL24CM1A provides 1048576 bits of serial electrically erasable and programmable read-only memory (EEPROM), organized as 131072 words of 8 bits each.⚫The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. ⚫The BL24CM1A offers an additional page, named the Identification Page (256 bytes). The Identification Page can be used to store sensitive application parameters which can be (later) permanently locked in Read-only mode.Pin ConfigurationNC A1 A2 GNDVCCWPNCA1A2GNDNCA1A2GNDVCCWPVCCWP １２３４8765１２３４１２３４87658765８-lead PDIP８-lead SOP８-lead TSSOPSCLSDASCLSDASCLSDAWLCSPSDA VccSCLA2A1NCGNDWPNCA1A2GNDVCCWP１２３４8765UDFNSCLSDAPin DescriptionsPin Name Type Functions A1-A2I Address Inputs SDA I/O Serial Data SCL I Serial Clock Input WP I Write ProtectGND P Ground VccPPower SupplyBlock DiagramSTART STOP LOGICSERIAL CONTROLLOGICSCL SDAGNDVcc DEVICE ADDRESS COMPARATORLOADCCMPDATA WORD ADRESS COUNTERLOADINCX DECODERY DECODER SERIAL MUXEEPROMENDATA RECOVERY HIGH VOLTAGE PUMP/TIMINGDOUT/ACKNOWLEDGEDINDOUTA1A2WPDEVICE/PAGE ADDRESSES (A2 and A1): The A2 and A1 pins are device address inputs that are hard wirefor the BL24CM1A. Four 1M devices may be addressed on a single bus system (device addressing is discussedin detail under the Device Addressing section).SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open- collector devices.SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.WRITE PROTECT (WP): The BL24CM1A has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protection pin is connected to Vcc, the write protection feature is enabled and operates as shown in the following Table 2.Table 1Figure 1WP Pin Status BL24CM1AAt VCC Full(1024K)ArrayAt GND Normal Read/Write OperationsTable 2Functional Description1. Memory OrganizationBL24CM1A, 1M SERIAL EEPROM: Internally organized with 512 pages of 256 bytes each, the 1M requires a 17-bit data word address for random word addressing.2. Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 2). Data changes during SCL high periods will indicate a start or stop condition as defined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 3).STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 3).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a "0" to acknowledge that it has received each word. This happens during the ninth clock cycle.STANDBY MODE: The BL24CM1A features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations.MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps:1. Clock up to 9 cycles.2. Look for SDA high in each cycle while SCL is high.3. Create a start condition.DATA STABLEDATA STABLEDATA CHANGESDASCLFigure 2. Data ValiditySDASCLSTARTSTOPFigure 3. Start and Stop DefinitionSCL DATA INDATA OUTSTARTACKNOWLEDGE189Figure 4. Output Acknowledge3. Device AddressingThe 1M EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 5)The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown. This is common to all the Serial EEPROM devices.The 1M EEPROM uses A2 and A1 device address bits and one world address bit to allow as much as four devices on the same bus. These 2 device address bits must be compared to their corresponding hardwired input pins. The A2 and A1 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float.The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip will return to a standby state.MSB LSB1010A2A1B16R/WB15B14B13B12B11B10B9B8B7B6B5B4B3B2B1B0Figure 5. Device Address and two 8-bit data word addressDATA SECURITY: The BL24CM1A has a hardware data protection scheme that allows the user to write protect the entire memory when the WP pin is at VCC.4. Write OperationsBYTE WRITE: A write operation requires two 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 6).SDA LINE STARTDEVICEADDRESSWRITEMSBLSBR/WACKFIRST WORDADDRESSSECOND WORDADDRESSACKLSBACKLSBACKLSBSTOPDATAFigure 6. Byte WritePAGE WRITE: The Page Write mode allows up to 256 bytes to be written in a single Write cycle. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 255 more data words. The EEPROM will respond with a “0” after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 7).ST A R TDEVICEADDRESSWRITEMSBLSBR/WACKFIRST WORDADDRESSSECOND WORDADDRESSACKLSBACKLSBACKSTOPDATA(n)ACKACKDATA(n+1)DATA(n+1)SDALINEFigure 7. Page WriteThe data word address lower eight bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 256 data words are transmitted to the EEPROM, the data word address will "roll over" and previous data will be overwritten.WRITE IDENTIFICATION PAGE: The Identification Page (256 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. It is written by issuing the Write Identification Page instruction. This instruction uses the same protocol and format as Page Write (into memory array), except for the following differences:•Device type identifier = 1011b•MSB address bits B16/B8 are don't care except for address bit B10 which must be "0".LSB address bits B7/B0 define the byte address inside the Identification page.If the Identification page is locked, the data bytes transferred during the Write Identification Page instruction are not acknowledged (NoAck).ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a "0", allowing the read or write sequence to continue.5. Read OperationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to "1". There are three read operations: current address read, random address read and sequential read.CURRENT ADDRESS READ:The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address "roll over" during read is from the last byte of the last memory page to the first byte of the first page. The address "roll over" during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input "0" but does generate a following stop condition (see Figure 8).ST A R TDEVICEADDRESSREADMSBLSBR/WACKSTOPDATANOACKSDALINEFigure 8. Current Address ReadRANDOM READ:A random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 9)STA R TDEVICEADDRESSWRITEMSBLSBR/WACK1st,2nd WORDADDRESSACKLSBSTOPDATA(n)DEVICEADDRESSSTARTREADACKNOACK DUMMY WRITESDALINEFigure 9. Random ReadSEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 10).DEVICE ADDRESS READR/WACKACKACKACKSTOP DATA(n)DATA(n+1)DATA(n+2)DATA(n+x)NOACKSDALINEFigure 10. Sequential ReadREAD IDENTIFICATION PAGE: The Identification Page (256 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode.The Identification Page can be read by issuing an Read Identification Page instruction. This instruction uses the same protocol and format as the Random Address Read (from memory array) with device type identifier defined as 1011b. The MSB address bits B16/B8 are don't care, the LSB address bits B7/B0 define the byte address inside the Identification Page. The number of bytes to read in the ID page must not exceed the page boundary (e.g.: when reading the Identification Page from location 10d, the number of bytes should be less than or equal to 246, as the ID page boundary is 256 bytes)LOCK IDENTIFICATION PAGE: The Lock Identification Page instruction (Lock ID) permanently locks the Identification page in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with the following specific conditions:Device type identifier = 1011bAddress bit B10 must be ‘1’; all other address bits are don't careThe data byte must be equal to the binary value xxxx xx1x, where x is don't careElectrical CharacteristicsAbsolute Maximum Stress Ratings：⚫DC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V⚫Input / Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND-0.3V to VCC+0.3V⚫Operating Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40℃ to +85℃⚫Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65℃ to +150℃⚫Electrostatic pulse (Human Body model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8000VComments：Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.DC Electrical CharacteristicsApplicable over recommended operating range from: TA = -40℃to +85℃, VCC = +2.0V to +5.5V (unless otherwise noted)Parameter Symbol Min Typ Max Unit Condition Supply Voltage V CC1 2.0- 5.5V-Supply Current VCC=5.0V I CC1-0.260.5mA READ at 400KHZSupply Current VCC=5.0V I CC2-0.280.5mA WRITE at 400KHZSupply Current VCC=5.0V I SB1-0.030.5μA V IN=V CC or V SSInput Leakage Current I L1-0.10 1.0μA V IN=V CC or V SSOutput Leakage Current I LO-0.05 1.0μA V OUT=V CC or V SSInput Low Level V IL1-0.3-V CC×0.3V V CC=1.7V to 5.5VInput High Level V IH1V CC×0.7-V CC+0.3V V CC=1.7V to 5.5VOutput Low Level VCC=1.7V V OL1--0.2V I OL=2.1mAOutput Low Level VCC=5.0V V OL2--0.4V I OL=3.0mATable 3Pin CapacitanceParameter Symbol Min Typ Max Unit ConditionInput/Output Capacitance(SDA)C I/O--8pF V IO=0VInput Capacitance(A1,A2,SCL)C IN--6pF V IN=0VTable 4AC Electrical CharacteristicsApplicable over recommended operating range from TA = -40℃ to +85℃, VCC = +2.0V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted)Min Typ Max Min Typ Max Clock Frequency,SCL f SCL --400--1000KHZ Clock Pulse Width Low t LOW 1.3--0.5--μs Clock Pulse Width High t HIGH 0.6--0.26--μs Noise Suppression Time t I --50--50ns Clock Low to Data Out Valid t AA --0.9--0.45μs Time the bus must be free before a new transmission can start t BUF 1.3--0.5--μs Start Hold Time t HD:STA 0.6--0.25--μs Start Setup Time t SU:STA 0.6--0.25--μs Data In Hold Time t HD:DAT 0--0--μs Data in Setup Time t SU:DAT 100--100--ns Input Rise Time(1)t R --0.3--0.12μs Input Fall Time(1)t F --0.3--0.12μs Stop Setup Time t Su:STO 0.6--0.25--μs Data Out Hold Time t DH 50--50--ns Write Cycle Time t WR - 3.55- 3.55ms 5.0V,25℃,Byte Mode(1)Endurance4M--4M--Write CycleParameterSymbol 2.0V ≤V CC ﹤2.5V 2.5V ≤V CC ﹤5.5V UnitsNotes:1. This parameter is characterized and is not 100% tested.2. AC measurement conditions: RL (connects to VCC): 1.3 kInput pulse voltages: 0.3 VCC to 0.7 VCC Input rise and fall time: 50 nsInput and output timing reference voltages: 0.5 VCCThe value of RL should be concerned according to the actual loading on the user's system.Table 5Bus TimingSCLSDA_INSDA_OUTt SU.STAt HD.STAt LOW t Ft HIGHt LOWt HD.DATt SU.DATt Rt SU.STOt BUFt DHt AAFigure 11. SCL: Serial Clock, SDA: Serial Data I/OWrite Cycle TimingtWR(1)ACKSTOP CONDITIONSTART CONDITIONSCLSDAWord nFigure 12. SCL: Serial Clock, SDA: Serial Data I/ONotes:The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.Package InformationPDIP Outline Dimensionsb2eLAA2ceA E1COMMON DIMENSIONS (Unit of Measure=mm)SYMBOL MIN NOM MAX A 3.60 3.80 4.00A2 3.20 3.30 3.40b 0.44-0.53b2c 0.24-0.32D 9.059.259.45E1 6.156.35 6.55e eA eB 7.62-9.30L2.54BSC 7.62BSC1.52BSC3.00BSCeBDEBe A A1DE1LΦSYMBOL MIN NOM MAXA 1.35- 1.75A10.10-0.23 B0.39-0.48 C0.21-0.26D 4.70 4.90 5.10E1 3.70 3.90 4.10E 5.80 6.00 6.20eL0.50-0.80Φ0"-8"1.27BSCCOMMON DIMENSIONS(Unit of Measure=mm)CE1E Top ViewD ebA1A Side ViewL1LEnd ViewSYMBOL MIN NOM MAXD 2.90 3.00 3.10E 6.20 6.40 6.60E1 4.30 4.40 4.50A-- 1.20A10.05-0.15b0.21-0.30eL0.450.600.75L10.65BSC1.00REFCOMMON DIMENSIONSUnit of Measure=mmPIN 1 DOT BY MARKINGTOP VIEWb eLD2E2ED A3AA1PIN #1 IDENTIFICATIONCHAMFERPKG REF MIN NOM MAX A 0.500.550.60A10.00-0.05A3D 1.95 2.00 2.05E 2.95 3.00 3.05b 0.200.250.30L 0.200.300.40D2 1.25 1.40 1.50E2 1.15 1.30 1.40eCOMMON DIMENSION(MM)UT:ULTRA THIN 0.15REF0.50BSCBOTTOM VIEWSIDE VIEWWLCSPEG GA2A A1be1FFe 2eSYMBOL MIN NOM MAX A 0.4250.4650.505A10.1700.1900.210A20.2550.2750.295D 1.944 1.964 1.984E 1.4801.500 1.520e e1e2e3b F 0.5290.5490.569G0.2300.2500.2700.500BSC 0.500BSC 1.000BSC 0.270BSC 0.866BSC DMarking DiagramSOPBL24CM1ASSSSSPSSSSS : Lot IDTSSOPBL24CM1ASSSSSSSSSS : Lot IDUDFNBLFAYYWWYY: yearWW :weekWLCSPAYWY:The last digits of the yearW:week code.Y1...345 (90)Year2011...201320142015 (20192020)W A…Y Z a…y zWeek1...252627 (5152)Ordering InformationBL 24C M1 A-PA R CFeatureS: Standard (default, Pb Free RoHS Std.)C: Green (Halogen Free)Packing typeR: Tape and ReelT: TubePackage TypePA: SOP-8LSF: TSSOP-8LNT: UDFN-8LCS: WLCSPDA: PDIP-8LGenerationA: A VersionDensityM1: 1MbitProduct Family24C: IIC Interface EEPROMRevision historyVersion 1.00 BL24CM1AInitial versionVersion 1.01 BL24CM1AAdd WLCSP and UDFN Package informationVersion 1.02 BL24CM1AUpdate the Package Information。
九齐单片机休眠电流
九齐单片机休眠电流
九齐单片机（NY8A051F，NY8A054E，NY8A062D，NY8A062E等）是一款基于RISC精简指令集架构的8位微控制器，采用CMOS制程，专为多IO产品的应用而设计，例如遥控器、风扇/灯光控制或是游乐器周边等。
在性能方面，九齐单片机具有低成本、高性能等显著优势。
总之，关于九齐单片机的休眠电流，根据相关资料，其休眠电流可低至20nA。
这意味着在休眠模式下，九齐单片机的功耗非常低，有利于延长电池寿命和降低系统功耗。
然而，具体的休眠电流可能会因不同型号和应用场景而略有差异。
因此，在实际应用中，需要根据具体需求选择合适的九齐单片机型号。
FM24C1024A_ds_chs
器件/页 地址脚(A2，A1)：A2、A1 是硬件连接的器 件地址输入引脚（或空接），可作为和其他 FM24CXX 系列器件的兼容引脚。当这些引脚作为硬件连接的地
17volt25volt55volt符号参数最小值最大值最小值最大值最小值最大值单位fbscl输入时钟频率40010001000khztblow时钟脉宽低电平时间1300400400nstbhigh时钟脉宽高电平时间600400400nstb噪声抑制时间1005050nstbaa时钟低至数据有效时间1009005055050550nstbbuf两次指令间的总线空闲时间1300500500nstbhdsta起始条件保持时间600250250nstbsusta起始条件建立时间600250250nsnstbsudat数据建立时间100100100nstb输入上升时间300300300nstb输入下降时间300100100nstbsusto停止条件建立时间600250250nstbdh数据输出保持时间505050nstbwrmsendurance50v25c页操作模式1000000writecycles交流参数测试条件
FM24C1024A 两线制串行 EEPROM
技术手册
7
器件操作
时钟及数据传输：SDA 引脚通常被外围器件拉高。SDA 引脚的数据应在 SCL 为低时变化（参见图 4）；当数据 在 SCL 为高时变化，将视为下文所述的一个起始或停 止命令。
向 EEPROM 返回一个应答信号。收到该应答信号后， EEPROM 会继续输出下一组 8 位的数据。若此时没有 得到主控器件的应答信号，EEPROM 会停止读出数据， 直到主控器件返回一个停止命令来结束读周期。
华芯商城知识讲堂：24C02参数详解及写入源程序
今天华芯商城的知识讲堂给大家介绍一款热门的元器件24C02。
24C02是一个2K串行CMOS E2PROM，内部含有256个8位字节，该器件通过I2C总线接功能列表，主要在存储一些掉电后还要保存数据的场合，在上次运行时，保存的数据，在下一次运行时还能够调出。
24c02采用的IIC总线，是一种2线总线，我们在试验中用IO来模拟这种总线，至于总线的时序和原理，请参考相关资料。
如果您不想研究，也没有关系，我们在程序中已经为你写好了，现在和今后您都可以只调用就是，不必花时间和精力去研究。
我们将24c02的两条总线接在了P26和P27上，因此，必须先定义：sbit SCL=P2^7;sbit SDA=P2^6;在这个试验中，我们写入了一个字节数值0x88到24c02的0x02的位置。
写入完成后，P10灯会亮起，我们再在下一课来读出这个字节来验证结果。
下面一起来看具体代码吧：#define uchar unsigned char //定义一下方便使用#define uint unsigned int#define ulong unsigned long#include //包括一个52标准内核的头文件//本课试验写入一个字节到24c02中char code dx516[3] _at_ 0x003b;//这是为了仿真设置的#define WriteDeviceAddress 0xa0 //定义器件在IIC总线中的地址 #define ReadDviceAddress 0xa1sbit SCL=P2^7;sbit SDA=P2^6;sbit P10=P1^0;//定时函数void DelayMs(uint number){uchar temp;for(;number!=0;number--){for(temp=112;temp!=0;temp--) ;}}//开始总线void Start(){SDA=1;SCL=1;SDA=0;SCL=0;}//结束总线void Stop() {SCL=0;SDA=0;SCL=1;SDA=1;}//测试ACK bit TestAck() {bit ErrorBit; SDA=1;SCL=1;ErrorBit=SDA;SCL=0;return(ErrorBit);}//写入8个bit到24c02Write8Bit(uchar input){uchar temp;for(temp=8;temp!=0;temp--){SDA=(bit)(input&0x80);SCL=1;SCL=0;input=input<<1;}}//写入一个字节到24c02中void Write24c02(uchar ch,uchar address){Start();Write8Bit(WriteDeviceAddress);TestAck();Write8Bit(address);TestAck();Write8Bit(ch);TestAck();Stop();DelayMs(10);}//本课试验写入一个字节到24c02中void main(void) // 主程序{Write24c02(0x88,0x02);// 将0x88写入到24c02的第2个地址空间 P10=0; //指示运行完毕while(1); //程序挂起}24C02参数详解及写入源程序以上就是24C02的源程序代码，如果你想了解更多，欢迎登录华芯商城官网查看。
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Standard VCC (4.5V to 5.5V) DC Electrical Characteristics
Symbol Parameter Test Conditions Min
ICCA ISB ILI ILO VIL VIH VOL Active Power Supply Current Standby Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage IOL = 3 mA fSCL = 400 KHz fSCL = 100 KHz VIN = GND or VCC VIN = GND to VCC VOUT = GND to VCC –0.3 VCC x 0.7
Temp. Range
Voltage Operating Range
SCL Clock Frequency
Blank F Ultralite
Density
08 09 C W
Interface
24 NM
3
NM24C08U/09U Rev. B.1
元器件交易网
Limits Typ (Note 1)
0.2 10 0.1 0.1
Units Max
1.0 50 1 1 VCC x 0.3 VCC + 0.5 0.4 mA µA µA µA V V V
Low VCC (2.7V to 5.5V) DC Electrical Characteristics
Symbol Parameter Test Conditions Min
General Description,
The NM24C08U/09U devices are 8K (8,192) bit serial interface CMOS EEPROMs (Electrically Erasable Programmable ReadOnly Memory). These devices fully conform to the Standard I2C™ 2-wire protocol which uses Clock (SCL) and Data I/O (SDA) pins to synchronously clock data between the "master" (for example a microprocessor) and the "slave" (the EEPROM device). In addition, the serial interface allows a minimal pin count packaging designed to simplify PC board layout requirements and offers the designer a variety of low voltage and low power options. NM24C09U incorporates a hardware "Write Protect" feature, by which, the upper half of the memory can be disabled against programming by connecting the WP pin to VCC. This section of memory then effectively becomes a ROM (Read-Only Memory) and can no longer be programmed as long as WP pin is connected to VCC. Fairchild EEPROMs are designed and tested for applications requiring high endurance, high reliability and low power consumption for a continuously reliable non-volatile solution for all markets.
元器件交易网
NM24C08U/NM24C09U – 8K-BitŁ Serial EEPROM 2-Wire Bus Interface
Ordering Information NM 24 C XX U F LZ E XX
Package
NM24C08U/NM24C09U – 8K-BitŁ Serial EEPROM 2-Wire Bus Interface
Product Specifications Absolute Maximum Ratings
Ambient Storage Temperature All Input or Output Voltages with Respect to Ground Lead Temperature (Soldering, 10 seconds) ESD Rating –65°C to +150°C 6.5V to –0.3V +300°C 2000V min.
1
元器件交易网
NM24C08U/NM24C09U – 8K-BitŁ Serial EEPROM 2-Wire Bus Interface
Connection Diagrams
Dual-In-Line Package (N), SO Package (M8), and TSSOP Package (MT8)
Functions
I I2C™ compatible interface I 8,192 bits organized as 1,024 x 8 I Extended 2.7V – 5.5V operating voltage I 100 KHz or 400 KHz operation I Self timed programming cycle (6ms typical) I "Programming complete" indicated by ACK polling I NM24C09U: Memory "Upper Block" Write Protect pin
Pin Names
NC A2 VSS SDA SCL WP VCC No Connection Device Address Input Ground Serial Data I/O Serial Clock input Write Protect Power Supply
2
NM24C08U/09U Rev. B.1
Features
I The I2C™ interface allows the smallest I/O pincount of any EEPROM interface I 16 byte page write mode to minimize total write time per byte I Typical 200µA active current (ICCA) I Typical 1µA standby current (ISB) for "L" devices and 0.1µA standby current for "LZ" devices I Endurance: Up to 1,000,000 data changes I Data retention greater than 40 years
Dual-In-Line Package (N), SO Package (M8), and TSSOP Package (MT8)
NC NC A2 VSS 1 2 3 4 8 7 VCC WP SCL SDA
DS800009-5
NM24C09U
6 5
Top View See Package Number N08E, M08A, and MTC08
Letter
N M8 MT8 None V E Blank L LZ
Description
8-pin DIP 8-pin SOIC 8-pin TSSOP 0 to 70°C -40 to +125°C -40 to +85°C 4.5V to 5.5V 2.7V to 5.5V 2.7V to 5.5V and <1µA Standby Current 100KHz 400KHz CS100UL Process 8K 8K with Write Protect CMOS Technology Total Array Write Protect IIC Fairchild Non-Volatile Memory
Limits Typ (Note 1)
0.2 1 0.1 10 0.1 0.1
Units Max
1.0 10 1 50 1 1 VCC x 0.3 VCC + 0.5 0.4 mA µA µA µA µA µA V V V
ILI ILO VIL VIH VOL
Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage
Block Diagram
VCC VSS WP H.V. GENERATION TIMING &CONTROL START STOP LOGIC CONTROL LOGIC SLAVE ADDRESS REGISTER & COMPARATOR E2PROM ARRAY
SDA
SCL
XDEC
A2
WORD ADDRESS COUNTER