FPGA可编程逻辑器件芯片XC2S100-5FGG456C中文规格书

GTX-to-Board Interface
Analog Design Guidelines
Overview
In designs with FPGAs that contain GTX transceivers, the overall system performance of a
communication link is highly dependent on the characteristics of the power supply and
clocking design on both endpoints. This section discusses guidelines and
recommendations for these topics.
As a prerequisite, the design guidelines outlined in the Virtex-5 FPGA PCB Designer’s Guide
must be observed to keep the power supply and switching noise on the board to a
minimum. Additionally, it is highly recommended to use Point-of-Load (POL) power
Refer to the book EMC and the Printed Circuit Board[Ref7] by Mark I. Montrose,
sponsored by the IEEE Electromagnetic Compatibility Society, for additional guidelines.
Implementation of these guidelines not only improves system margins but is a prerequisite
for compliance to regulations as defined by Federal Communications Commission (FCC)
and the Verband Deutscher Elektrotechniker (VDE) regarding Electromagnetic
Compatibility (EMC), Electromagnetic Interference (EMI), and Radio Frequency
Interference (RFI).
Ports and Attributes
Table10-1 defines the analog pins.
Table 10-1:Analog Pins
Pins Dir Description
MGTAVCC In (Pad)MGTAVCC is the analog supply for the internal analog circuits of the GTX_DUAL tile.
MGTAVCCPLL In (Pad)MGTAVCCPLL is the analog supply for the shared PMA PLL of the GTX_DUAL tile.
MGTAVTTRX In (Pad)MGTAVTTRX is the analog supply for the receiver circuits and termination of the GTX_DUAL tile.
MGTAVTTRXC In (Pad)FXT only: MGTAVTTRXC is the analog supply for resistor calibration and standby circuit of the entire device.
Chapter 10:GTX-to-Board Interface
Table 10-2 defines the analog attributes.MGTAVTTRXC_R
In (Pad)
TXT only: MGTAVTTRXC_R is the analog supply for resistor calibration and standby circuit of the right transceiver column.
MGTAVTTRXC_L In (Pad)
TXT only: MGTAVTTRXC_L is the analog supply for resistor calibration and standby circuit of the left transceiver column.MGTAVTTTX In (Pad)
MGTAVTTTX is the analog supply for the transmitter
termination and driver circuits and reference clock routing of the GTX_DUAL tile.
MGTREFCLKP MGTREFCLKN In (Pad)Differential clock input pin pair (1) for the reference clock of the GTX_DUAL tile.
MGTRREF In (Pad)FXT only: MGTRREF is the reference resistor input for the entire device.
MGTRREF_R In (Pad)TXT only: MGTRREF_R is reference resistor input for the right transceiver column.
MGTRREF_L
In (Pad)
TXT only: MGTRREF_L is reference resistor input for the left transceiver column.
Notes:
1.This clock can only be accessed by the FPGA logic through the REFCLKOUT port.
Table 10-2:
Analog Attributes
Attribute
Type
Description
CLKINDC_B
Boolean
Must be set to TRUE. Oscillators driving the dedicated reference clock inputs must be AC coupled.
When set to FALSE for testing, the common mode voltage of the driving circuit must match the common mode voltage of the differential clock input pair (MGTCLKP , MGTCLKN). The differential swing must not exceed the maximum differential swing of the clock input pair.(1, 2)CLKRCV_TRST Boolean
When set to FALSE, switches off the internal termination resistors of the differential clock input pair. This results in a high-impedance input characteristic that is only intended for testing.
When set to TRUE, the differential clock input pair is terminated with a 100Ω differential impedance. Each clock input in (MGTCLKP , MGTCLKN) is contacted via a 50Ω resistor to a midterm nominal voltage of 0.8V .(1, 2)
TERMINATION_CTRL[4:0]
5-bit Binary
Controls the internal termination calibration circuit. Refer to Table 10-5, page 259 for encoding.
Table 10-1:
Analog Pins (Cont’d)
Pins
Dir Description
Resistor Calibration Circuit
Resistor Calibration Circuit
The resistor calibration circuit in the GTX transceiver is used to precisely calibrate the TX and RX termination resistors via an external precision reference resistor.
Table 10-1 defines the resistor calibration circuit pins used for TX and RX termination resistor calibration.TERMINATION_IMP_0TERMINATION_IMP_1
Integer
Selects the termination impedance for the TX driver and receiver.
See Figure 10-4 calibrating the impedance
values. Always set to 50, which selects the 50Ω termination impedance. The RocketIO™ GTX Transceiver Wizard automatically sets the TERMINATION_IMP_(0/1) attributes to 50.TERMINATION_OVRD Boolean
Selects whether the external 59Ω(3)precision resistor connected to the MGTRREF pin or an override value is used, as defined by TERMINATION_CTRL[4:0].
Notes:
1.Violation of the rules outlined in this section result in a marginal or dysfunctional design, device degradation in the future, or device damage.
2.Consult DS202: Virtex-5 FPGA Data Sheet for the common mode voltage values and the associated differential swing and operating conditions.
3.The nominal value of the external precision resistor RREF connected to the MGTRREF pin is different for LXT/SXT devices and FXT/TXT devices. For LXT/SXT devices with GTP_DUAL tiles, RREF is 50Ω nominal. For FXT/TXT devices with GTX_DUAL tiles, RREF is 59Ω nominal.
Table 10-2:Analog Attributes (Cont’d)
Attribute
Type
Description
Table 10-3:
Resistor Calibration Circuit Pins
Pins
Dir Description
MGTAVTTRXC In (Pad)FXT only: MGTAVTTRXC is the analog supply for resistor calibration and standby circuit of the entire device.
MGTAVTTRXC_L
In (Pad)
TXT only: MGTAVTTRXC_L is the analog supply for resistor calibration and standby circuit of the left transceiver column.MGTAVTTRXC_R In (Pad)
TXT only: MGTAVTTRXC_R is the analog supply for resistor calibration and standby circuit of the right transceiver column.
MGTRREF In (Pad)FXT only: MGTRREF is the reference resistor input for the entire device.
MGTRREF_L In (Pad)TXT only: MGTRREF_L is reference resistor input for the left transceiver column.
MGTRREF_R
In (Pad)
TXT only: MGTRREF_R is reference resistor input for the right transceiver column.
Chapter 10:GTX-to-Board Interface
Resistor Calibration Circuit。