S4610

Benefits
l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness
l Fully Characterized Capacitance and Avalanche SOA
l Enhanced body diode dV/dt and dI/dt Capability
PD - 96906B
D 2Pak IRFS4610
TO-220AB IRFB4610
TO-262IRFSL4610
IRFB4610IRFS4610IRFSL4610
HEXFET ® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching
l
Hard Switched and High Frequency Circuits S
D G S
D G S
D G
IRF/B/S/SL4610
Notes:
Repetitive rating; pulse width limited by max. junction temperature.
Limited by T Jmax , starting T J = 25°C, L = 0.39mH
R G = 25Ω, I AS = 44A, V GS =10V. Part not recommended for use above this value.
I SD ≤ 44A, di/dt ≤ 660A/µs, V DD ≤ V (BR)DSS , T J ≤ 175°C. Pulse width ≤ 400µs; duty cycle ≤ 2%.
C oss eff. (TR) is a fixed capacitance that gives the same charging time
as C oss while V DS is rising from 0 to 80% V DSS .
C oss eff. (ER) is a fixed capacitance that gives the same energy as C oss while V DS is rising from 0 to 80% V DSS .
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994. R θ is measured at T J approximately 90°C
IRF/B/S/SL4610
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance vs. Temperature
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage 1
10
100
V DS , Drain-to-Source Voltage (V)
1000
2000
3000
4000
5000
6000
C , C a p a c i t a n c e (p F )
20
40
60
80
100
120
140
Q G Total Gate Charge (nC)
04
8
12
16
20V G S , G a t e -t o -S o u r c e V o l t a g e (V )
IRF/B/S/SL4610
Fig 8. Maximum Safe Operating Area
Fig 10. Drain-to-Source Breakdown Voltage
Fig 11. Typical C OSS Stored Energy
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
0.1
1.0
10.0100.0
1000.0
I S D , R e v e r s e D r a i n C u r r e n t (A )
25
50
75
100
125
150
175
T J , Junction Temperature (°C)
020
40
60
80
I D , D r a i n C u r r e n t (A )
T J , Junction Temperature (°C)
V
, D r a i n -t o -S o u r c e B r e a k d o w n V o l t a g e
20
40
60
80
100
V DS, Drain-to-Source Voltage (V)0.0
0.51.01.52.0
E n e r g y (µJ
)
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
0400
800
1200
1600
E A S , S i n g l e P u l s e A v a l a n c h e E n e r g y (m J )
1
10
100
1000
V DS , Drain-toSource Voltage (V)
0.1
1
10
100
1000I D , D r a i n -t o -S o u r c e C u r r e n t (A
)
IRF/B/S/SL4610
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 14. Typical Avalanche Current vs.Pulsewidth
Fig 15. Maximum Avalanche Energy vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at )
1.Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T jmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT jmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P D (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I av = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed T jmax (assumed as
25°C in Figure 14, 15).
t av = Average time in avalanche.
D = Duty cycle in avalanche = t av ·f
Z thJC(D, t av) = Transient thermal resistance, see Figures 13)
P D (ave) = 1/2 ( 1.3·BV·I av) =D T/ Z thJC
I av =2D T/ [1.3·BV·Z th]
E AS (AR) = P D (ave)·t av
tav (sec)
A
v
a
l
a
n
c
h
e
C
u
r
r
e
n
t
(
A
)
255075100125150175
Starting T J , Junction Temperature (°C)
100
200
300
400
E
A
R
,
A
v
a
l
a
n
c
h
e
E
n
e
r
g
y
(
m
J
)
IRF/B/S/SL4610
Fig. 17 - Typical Recovery Current vs. di f /dt
Fig 16. Threshold Voltage Vs. Temperature
Fig. 19 - Typical Stored Charge vs. di f /dt
Fig. 18 - Typical Recovery Current vs. di f /dt
T J , Temperature ( °C )V G S (t h ) G a t e t h r e s h o l d V o l t a g e (V )
di f / dt - (A / µs)
I R R M - (A )
di f / dt - (A / µs)
I R R M - (A )
di f / dt - (A / µs)
Q R R - (n C )
di f / dt - (A / µs)
Q R R - (n C )
IRF/B/S/SL4610
Fig 23a. Switching Time Test Circuit Fig 23b.
Switching Time Waveforms
V V DS
90%
d(on)
d(off)
r
f
Fig 22b. Unclamped Inductive Waveforms
Fig 22a.
Unclamped Inductive Test Circuit
I AS
V DD
Id
Qgs1
Qgs2Qgd Qgodr
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
® Power MOSFETs
* V GS = 5V for Logic Level Devices
IRF/B/S/SL4610
TO-220AB Package Outline Dimensions are shown in millimeters (inches)
TO-262 Package Outline
IRF/B/S/SL4610
11
Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at for sales contact information . 11/04
D 2Pak Tape & Reel Information
3
4
4
TRR
FEED DIRECTION
1.85 (.073)
1.65 (.065)
1.60 (.063)1.50 (.059)
4.10 (.161)3.90 (.153)
TRL
FEED DIRECTION 10.90 (.429)10.70 (.421)
16.10 (.634)15.90 (.626)
1.75 (.069)1.25 (.049)
11.60 (.457)11.40 (.449)
15.42 (.609)15.22 (.601)
4.72 (.136)4.52 (.178)
24.30 (.957)23.90 (.941)
0.368 (.0145)0.342 (.0135)
1.60 (.063)1.50 (.059)
13.50 (.532)12.80 (.504)330.00(14.173) MAX.
27.40 (1.079)23.90 (.941)
60.00 (2.362) MIN.
30.40 (1.197) MAX.
26.40 (1.039)24.40 (.961)
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.。