FPGA可编程逻辑器件芯片XC3S700A-4FG400I中文规格书

Chapter 38:Debugging Debugging Write and Read Sanity Checks
Calibration Overview
Throughout calibration, read and write/read sanity checks are performed to ensure that as each stage of calibration completes, proper adjustments and alignments are made allowing writes and reads to be completed successfully. Sanity checks are performed as follows:•Check for DQS Gate after DQS Preamble Detection
•Read Sanity Check after Read DQS Centering (Simple)
•Write/Read Sanity Check after Write Latency Calibration
•Write/Read Sanity Check after Read DQS Centering (Complex)
•Write/Read Sanity Check after Read V REF Training (Reserved)
•Write/Read Sanity Check after Write DQS-to-DQ Centering (Complex)
•Write/Read Sanity Check after Write V REF Training (Reserved)
•Write/Read Sanity check after Read DQS Centering Multi-Rank Adjustment (For ranks other than the first one)
•Write/Read Sanity check after DQS Gate Multi-Rank Adjustment when there is more than one rank
Each sanity check performed uses a different data pattern to expand the number of patterns checked during calibration.
Table 38-38:Sanity Check Data Patterns
Sanity Check Stage Data Pattern (as stored) – 32
bits, 4 bits concatenated
together each as
{f3,r3,f2,r2,f1,r1,f0,r0}.
Data on DQ bus (nibble) as would
be seen in a simulation or a scope
–r0 f0 r1 f1 r2 f2 r3 f3
DQS Gate Sanity Check0xAAAAAAAA0F0F_0F0F Read Sanity Check0xAAAAAAAA0F0F_0F0F Write/Read Sanity Check 00x399C4E27937E_C924 Write/Read Sanity Check 10x3587D5DC E4F1_B837 Write/Read Sanity Check 20x919CD315B254_F02E Write/Read Sanity Check 30x4E2562E55AD8_07B1 Write/Read Sanity Check 40x2C6C9AAA03CF_2D43
Data swizzling (bit reordering) is completed within the UltraScale PHY. Therefore, the data visible on BUS_DATA_BURST and a scope in hardware is ordered differently compared to what would be seen in ChipScope. Figures are examples of how the data is converted for the sanity check data patterns.Write/Read Sanity Check 5Rank = 0 (No sanity check)
Rank = 1 (0x75294A2F)
Rank = 2 (0x75294A30)
Rank = 3 (0x75294A31)
Rank = 0 (No sanity check)Rank = 1 (D397_8DA0)Rank = 2 (C286_9DA0)Rank = 3 (D286_9DA0)Write/Read Sanity Check 6(1)Rank = 0 (0xE5742542)
Rank = 1 (0xE5742543)
Rank = 2 (0xE5752442)
Rank = 3 (0xE5752443)
Rank = 0 (A1E0_4ED8)Rank = 1 (B1E0_4ED8)Rank = 2 (C1E0_4ED8)Rank = 3 (D1E0_4ED8)
Notes:
1.For 3DS systems, the Write/Read Sanity Check 6 is repeated for each stack in a given rank. For each stack, the data pattern is adjusted by adding 0x100 to the data pattern (as stored) for the base rank pattern. For example, for rank 0, stack 0 would be data pattern 0xE5742542 as shown in the table, but rank 0, stack 1 the pattern would be 0xE5742642 (and show up as 83E0_4ED8 on the DQ bus).Table 38-38:Sanity Check Data Patterns (Cont’d)
Sanity Check Stage Data Pattern (as stored) – 32 bits, 4 bits concatenated together each as {f3,r3,f2,r2,f1,r1,f0,r0}.
Data on DQ bus (nibble) as would be seen in a simulation or a scope –r0 f0 r1 f1 r2 f2 r3 f3
RDLVL_IDELAY_FINAL_BYTE8_BIT4 04a
RDLVL_IDELAY_FINAL_BYTE8_BIT5 04c
RDLVL_IDELAY_FINAL_BYTE8_BIT6 04d
RDLVL_IDELAY_FINAL_BYTE8_BIT7 04a
RDLVL_NQTR_CENTER_FINAL_NIBBLE0 064
RDLVL_NQTR_CENTER_FINAL_NIBBLE1 06b
RDLVL_NQTR_CENTER_FINAL_NIBBLE2 066
RDLVL_NQTR_CENTER_FINAL_NIBBLE3 06b
RDLVL_NQTR_CENTER_FINAL_NIBBLE4 062
RDLVL_NQTR_CENTER_FINAL_NIBBLE5 06c
RDLVL_NQTR_CENTER_FINAL_NIBBLE6 067
RDLVL_NQTR_CENTER_FINAL_NIBBLE7 069
RDLVL_NQTR_CENTER_FINAL_NIBBLE8 065
RDLVL_NQTR_CENTER_FINAL_NIBBLE9 05d
RDLVL_NQTR_CENTER_FINAL_NIBBLE10 05d
RDLVL_NQTR_CENTER_FINAL_NIBBLE11 05c
RDLVL_NQTR_CENTER_FINAL_NIBBLE12 061
RDLVL_NQTR_CENTER_FINAL_NIBBLE13 051
RDLVL_NQTR_CENTER_FINAL_NIBBLE14 054
RDLVL_NQTR_CENTER_FINAL_NIBBLE15 04f
RDLVL_NQTR_CENTER_FINAL_NIBBLE16 063
RDLVL_NQTR_CENTER_FINAL_NIBBLE17 06d
RDLVL_PQTR_CENTER_FINAL_NIBBLE0 064
RDLVL_PQTR_CENTER_FINAL_NIBBLE1 06a
RDLVL_PQTR_CENTER_FINAL_NIBBLE2 066
RDLVL_PQTR_CENTER_FINAL_NIBBLE3 068
RDLVL_PQTR_CENTER_FINAL_NIBBLE4 061
RDLVL_PQTR_CENTER_FINAL_NIBBLE5 06d
RDLVL_PQTR_CENTER_FINAL_NIBBLE6 067
RDLVL_PQTR_CENTER_FINAL_NIBBLE7 06c
RDLVL_PQTR_CENTER_FINAL_NIBBLE8 069
RDLVL_PQTR_CENTER_FINAL_NIBBLE9 060
RDLVL_PQTR_CENTER_FINAL_NIBBLE10 061
RDLVL_PQTR_CENTER_FINAL_NIBBLE11 061
RDLVL_PQTR_CENTER_FINAL_NIBBLE12 066
RDLVL_PQTR_CENTER_FINAL_NIBBLE13 056
RDLVL_PQTR_CENTER_FINAL_NIBBLE14 058
RDLVL_PQTR_CENTER_FINAL_NIBBLE15 058
RDLVL_PQTR_CENTER_FINAL_NIBBLE16 061
RDLVL_PQTR_CENTER_FINAL_NIBBLE17 06b
Hardware Measurements
No hardware measurements are available because no command or data are sent to the memory during this stage. Algorithm only goes through previously collected data.。