第二章 cadence ic5141教程版图部分
ic5141使用教程
图 1.17
编辑后 inv 的 symbol
保存并退出 symbol 的编辑界面， 同样退出原理图编辑器。 至此原理图的输入 完成。
5．创建仿真电路图
完成电路原理图的输入之后， 为了对设计进行仿真和性能分析， 需要建立一 个仿真平台，将电源、各种激励信号输入待测的电路 inv，然后采用仿真器进行 分析。 （1） 建立设计原理图： 在命令解释器窗口 CIW 中选菜单项 FileNewCellview , 出现“Create New File”对话框，如图 1.18 所示填写、选择相应的选项，点击 OK 按钮，进入原理图编辑器 virtuoso schematic editor 界面。 （同前述电路原理图 输入时的操作一样） 。
仍然是按照图 1.19 的内容填写表项，点击 Hide 按钮，在原理图编辑其中就 会出现编辑过的 inv 的 symbol， 直接摆放即可。 同样的操作添加 vdd 和 gnd 符号， 注意这里采用的是 analogLIb 库中的元件 （在测试电路图中除待测电路 dut 之外， 其余器件均来自 analogLib） 。添加电源和地选符号项选择列表如下图 1.20、1.21 所示。
图 1.14
inv 原理图
4．创建 symbol
完成原理图之后，为便于进行仿真，需要进行 symbol 的创建。 （1）生成符号图：在原理图编辑窗口，点击菜单项 DesignCreate Cellview From Cellview，出现 symbol 生成选项表（图 1.15 上部分） ，点击 OK 按钮出现 图 1.15 下部分。
cadence_ic5141usr6安装说明
c@dence_i_c5141和mm$im61的安装过程和配置方法。
系统的考虑，按照道理来说应该是所有的linux系统都能安装运行i_c5141的，只不过因为各个linux组件实现不完全统一，所以在安装i_c5141的时候会出现各种问题，但是只要你有相关linux系统的知识，对于linux一些基本设计理念比较熟悉的话，应该都是可以通过调整系统来安装运行i_c5141的。
安装i_c5141的过程实际上就是一个根据c@dence给出的错误信息进行debug的过程，你把所有的bug都解决了，软件也就自然能运行了。
现在已知可以运行i_c5141的系统rehl，centos，suse，ubuntu还有archlinux。
推荐使用的系统是rehl或是centos，这两个应该是兼容性最好的，当然下面的安装过程还是以archlinux为例来讲解的。
1 确认所用linux系统的tar版本在1.14以下，否则不能正常解压安装包。
2 下载安装包，包括：Update_IC50.46.006_lnx86_1of4.tarUpdate_IC50.46.006_lnx86_2of4.tarUpdate_IC50.46.006_lnx86_3of4.tarUpdate_IC50.46.006_lnx86_4of4.tarCadence.Base.IC5141.Lnx86.3CDs[.ck].rar，---这个是5141的三个base包合成一个了。
Base_MMSIM61_lnx86_1of2.tarBase_MMSIM61_lnx86_2of2.tar用tar xvf filename全部解压缩，将得到的update包放在一个文件夹内，如/ic/IC50.46.006_lnx86.Update，base包会解压到另一个文件夹，如/ic/base_5141，将mm_sim的cd1和cd2放在另一个文件夹内，如/ic/mm_sim。
关于Cadenceic5141的安装
关于Cadenceic5141的安装关于Cadenceic5141的安装2008-04-17版权声明：转载时请以超链接形式标明文章原始出处和作者信息及本声明/logs/19205304.html[绝对原创]经过一个多星期的反复摸索和实验，在无数次的重装与删除之后，本先生终于把万恶的Cadence塞到了笔记本里（洒花庆祝一下）。
在参考了网上无数大牛门的安装心得之后，决定写下此文。
一来为以后重装（呸呸呸……不吉利）留下技术参考，二来为和本先生一样的菜鸟抛砖引玉。
我的失败就是你们的经验啊，上帝啊，我不入地狱谁入地狱。
阿拉真主，阿弥陀佛…… 废话说完了，进入正题。
Cadence软件很好用，但安装起来很麻烦，所以在决定安装之前，需要做以下几件事情。
第一，下载安装文件。
IC5141一共是七张盘。
包括3张Base 和4张Update。
本先生只下到三张Base,Update没有找到。
如果谁有希望提供一下哈。
基本安装用Base就可以了，Update有当然更好，不过没有也基本不影响使用。
另外还要准备好license文件。
各大论坛都有，自己找吧，这里就不提供了。
如果找不到链接的本人提供一个地方，去上交BBS的微电子版块找找看，那里有一个内部的FTP，下载速度很快的，差不多300K/s,两个小时可以下完的。
IC5141和IC610的版本都有，还有MMSIM610，教育网的同志们可以去下。
具体地址就不提供了，我也忘记了。
第二，安装Linux。
现在Linux的版本很多，麻烦各位挑的时候别太随意。
本人在这里吃了很大的亏。
一般来说，版本越新的安装的难度就越大。
具体原因是这样的。
Linux的进程机制分两种。
Linuxthreads和NPTL，其中早期的Linux支持前者，随着内核的升级，目前版本的Linux都已经放弃了对Linuxthreads的支持，转为采用NPTL。
很不幸的是，IC5141采用了比较保守的原则，只支持Linuxthreads，所以一定要在支持Linuxthreads的Linux内核下才能够运行。
cadence教程IC设计工具原理
15
EDA概述
CADENCE
• 软核IP（soft IP）是用可综合的硬件描述语言描述的 RTL级电路功能块，不涉及用与什么工艺相关的电路 和电路元件实现这些描述。 • 优点：设计周期短，设计投入少，不涉及物理实现， 为后续设计留有很大发挥空间，增大了IP的灵活性和 适应性。 • 缺点：会有一定比例的后续工序无法适应软核IP设计， 从而造成一定程度的软核IP修正，在性能上有较大的 不可预知性。
20
EDA概述
CADENCE
• EDA技术特征：
（1）硬件采用工作站和PC机。 （2）具有IP模块化芯核的设计和可重复利用功能。 （3）EDA技术采用高级硬件描述语言描述硬件结构、参 数和功能，具有系统级仿真和综合能力。
21
EDA概述
CADENCE
• EDA工具一般由两部分组成：
逻辑工具 物理工具
CADENCE
IC设计工具原理
（Cadence应用）
哈尔滨工程大学微电子学专业
1
第一章 IC设计基础
CADENCE
• 集成电路设计就是根据电路功能和性能 的要求，在正确选择系统配置、电路形 式、器件结构、工艺方案和设计规则的 情况下，尽量减小芯片面积，降低设计 成本，缩短设计周期以保全全局优化， 设计出满足要求的集成电路。其最终的 输出是掩模版图，通过制版和工艺流片 得到所需的集成电路。
10
IC设计基础
CADENCE
• 典型的实际分层次设计流程：
11
IC设计基础
CADENCE
• 分层次设计流程主要适用于数字系统设 计，模拟IC设计基本上是手工设计。 • 即便是数字IC设计，也需要较多的人工 干预。
12
IC设计基础
第一章 cadence ic5141教程schematic及其仿真
图 1-2-3 Open File 窗口 Exit 项退出 Cadence 软件包。 二．Tools 菜单 在 Tools 菜单下，主要的菜单项有 Library Manager、Library Path Editor 等。 Library Manager 项打开的是库管理器（Library Manager）窗口，如图 1-2-4 所示。
ｃａｄｅｎｃｅ ｃｄｓSPICE 的使用说明
第一章． Cadence cdsSPICE 的使用说明
Cadence cdsSPICE 也是众多使用 SPICE 内核的电路模拟软件之一。因此他在使用 上会有部分同我们平时所用到的 PSPICE 相同。这里我将侧重讲一下它的一些特殊用法。
§ 1－1 进入 Cadence 软件包
图 1-3-1 Composer-Schematic Editing 窗口 选择 Add/Component 菜单，打开相应添加元件的窗口，如图 1-3-2 所示。点击 Browse， 会弹出 library manager 窗口，一些常用的元器件都在 Analoglib 库中。 View Name 一般选择 symbol，instance Names 不用自己填，系统会自己加上去 。添加完元件后需设定元件的模型 名称（如果必须的话）以及一些参数的值，特别是 mos 管和三极管，一定要填 model name，
1
ｃａｄｅｎｃｅ ｃｄｓSPICE 的使用说明 i——在光标处插入正文； x——删除光标处的字符； :wq——存盘退出； 要记著一点，在插入态处，不能打入指令，必需先按〈Esc〉键，返回指令态。假若户不知 身处何态，也可以按〈Esc〉键，不管处于何态，都会返回指令态其它的一些命令请读者自己参 阅有关的书籍。
IC5141完整安装过程
＊**＊＊*＊**＊*＊***＊＊*前序*＊＊＊**＊＊*＊*＊*＊＊＊***＊＊***＊*＊*******＊＊＊**＊＊＊Red Hat Enterprise Linux Server 5不支持安装IC5141,需要安装IC610或者更高版本，所以这里采用的是Red hat Enterprise 4。
下面是建立的两个linux下的用户，后面这个xue是自己建立的用户，用于安装后仿软件.因为要改变环境变量，所以还是自己建立一个用户比较好,不要用root用户.超级账户：root 密码111111普通用户：xue 密码111111linux命令大全http://linux.chinaitlab。
com/special/linuxcom/（1）adduser xue (在系统中增加xue用户)(2) passwd xue （为xue用户设置密码，记住该密码）解压缩tar文件tar –xvzf ［文件名］或者直接右键extract创建文件夹的桌面快捷方式ln -s /mnt/hgfs/xpshare/ /root/Desktop/关机shutdown -h now 重启rebootLinux设置在原窗口下打开子窗口选择File Browser然后edit-Preferences钩上＊＊＊＊***＊＊*＊*＊*****＊**＊*＊**＊＊***＊***＊*＊＊＊＊**＊＊****＊*＊**＊**＊**＊＊＊*＊*＊＊*安装虚拟机：直接点击安装文件安装。
虚拟机软件的安装省略，非常简单，跟普通软件安装一样。
（有一点要注意:64位的WIN7系统要选择典型安装，不要全部安装，否则安装不成功）安装red hat 4：选择New Virtual Machine选择Linux，版本Red Hat Enterprise Linux 4选择第一个a single file 在虚拟机界面上选择菜单栏的VM，点击这个菜单底下的Settings,会出现如下图。
关于IC5141版图操作中GuardRing的创建
?endType "flush" ?beginExt 0.000000 ?endExt 0.000000 ?justification "center" ?offset 0.000000 ?offsetSubPath list( list(
问题依次解决。 版图界面，点击菜单上的“Create”---->“Multipart Path”，不要急着开始画 path，按一下“F3”，打开关于 “Multipart Path”设置的界面。
这个界面中，东西比较多，其他的不讲，就针对我们目前的问题，给出解决办法。 点击“Save Template...”按钮
这个其实是一个 skill 语言编写的简单“guardring”模板文件，内容也十分简单易懂。
下面继续讲解如何在关闭 icfb 后，下次启动，能够继续使用当前设置好的“guardring”模板。 在自己的根目录下，一般都有一个“.cdsinit”的隐藏文件，打开，加上一句： load “~/csmc05.mpp.templates.il” 保存退出，这样，下次重启 icfb 的时候，就会自动的加载这个模板文件，也就是说可以直接使用，而不至 于每次都去重新设置一遍。
此界面中输入框中，已经默认填写了一个文件名（~/csmc05.mpp.templates.il），表示将保存当前“pgr1”的 “guardring”到一个路径为“/home/user/”，名称为“csmc05.mpp.templates.il”的文件中。 这个具体的路径和文件名称都是可以自由输入的，其实目的就是保存一个模板文件。 本文就不设置其他，默认设置完毕，点击"OK"就可以了。 切换到自己的根目录下，可以看到生成了一个名称为“csmc05.mpp.templates.il”的文件。打开这个文件， 内容如下： prog((tech techLibName techFileName)
cadence5141安装与指令说明
cadence5141安装与指令说明cadence 5141 安装在linux下安装cadence(设定安装文件放在windows下d盘,为hda5)1切换用户到超级用户:(以下均省略提示符,隔行表示直接输入的字符)Su /切换用户,缺省为超级用户,若是切换普通用户在su后空格加用户名888888 /超级用户密码cd / /至系统根目录2 在系统根目录下建立一个安装目录,如edamkdir eda /建立安装目录文件chmod –R 755 eda /更改文件属性使之能够被普通用户使用chown -R b704:b704 eda /具体释放权限给某个用户3 创建挂载点和执行安装的临时文件cd /mntmkdir evol 挂载d盘的文件夹.起引导作用,不是实际存储mkdir cdrom /用于挂载iso文件,类似光驱mkdir temp4 挂载文件mount /dev/hda5 /mnt/evol /将windows下的硬盘d挂载到本地挂载点cd /mnt/evoldircp -r ic5141 /mnt/temp /将安装文件放置在临时文件夹cd /mnt/tempdircd ic5141dirmount -o loop cd1.iso /mnt/cdrom /挂载iso文件到光驱cd /cd /mnt/cdromdir.setup.sh /执行安装文件5 根据提示进行安装,基本上选择默认设置即可:须注意三点选择安装内容的时候,选a 即全选提示安装信息置放在哪时.选择4(anolog catalog,而不选择默认的2-email)最后确定安装的路径的时候输入以下信息/eda/ic51,自动会提示在eda下创建ic51文件安装进行过程中加入新的iso文件时另开终端执行,安装结束即执行了100%时,选择q退出即可,不需理会其他选项.6 安装结束,在安装ic5141的目录下即/eda/ic51 下新建一个文件夹license,然后将license.dat拷贝到此目录下,具体文件放在mnt/temp/ic5141/lic_setings/license(这一步可以直接在文件系统里拷贝)7 将文件/eda/ic51/tools.lnx86重命名,命令为:(cd /eda/ic51)ln -s tools.lnx86 tools8 将配置文件.bashrc 和.cdsinit文件拷贝到个人用户的根目录下具体配置文件放在/mnt/temp/ic5141/lic_setings 个人用户根目录/home/b704cd /mnt/temp/ic5141/lic_setingscp .bashrc /home/b704cp .cdsinit /home/b7049 用vi命令打开.bashrc 文件,把安装路径修改成与安装路径相一致并保存: /eda/ic51vi /home/b704/.bashrc (最好先进入子目录cd /home/b704) 将修改好的.bashrc 文件写入内存source .bashrc10 运行icfb&, 没用问题即可使用.将u盘挂载在linux下的命令是:mkdir /mnt/usbmount -t vfat/dev/sda1/mnt/usb当出现没有读写权限的文件,需要释放权限的话,比如是/home/b704/m 文件夹下的文件有如下问题时chown -R b704:b704/home/b704/m使用Cadence需要加入Library的问题:以使用chrt库为例先将chrt的库文件拷贝到/home/b704/chrt 下这一步可以直接进行文件夹一级的操作,不用使用命令格式运行icfb& 在菜单选项处的tool里选择Library manager->进入新一级的窗口编辑框选择edit ->Library path 又进入一级窗口编辑框选择edit->add Library. 出现一个路径选择窗口chrt chrt _basic 在此添加chrt chrt_dig_basic命令说明用户切换命令su 默认设置为超级用户root,需要以密码进入;若进入普通用户的话:su用户名进入文件命令cd 如:cd/mnt/evol 返回上一次进入的目录路径:cd --返回到root 根目录:cd创建文件命令用mkdir直接创建全路径,如mkdir /mnt/temp/usb 或者是先进入cd /mnt/temp 再创建目录mkdir usb显示文件命令有两种形式ls/mnt/temp 这种方式并没有改变提示符所显示的目录路径cd /mnt/temp 进入目录路径再现是目录文件:dir文件拷贝命令cp –r 源文件路径目录文件路径如cp -r /mnt/evol/ic5141 /mnt/temp 若拷贝的仅仅是文件不用添加-r选项.重命名命令ln –s 源文件目的文件这个命令的重命名是新建一个文件,对源文件的东西进行复制,并不会对源文件做任何处理,即源文件仍然不错修改的存在删除文件命令rm 目的文件rm -r 目的目录root下的mnt目录文件是专门为挂载外来文件的,常用于挂载如windows操作系统下的硬盘,usb 接口等:将u盘挂载再linux下的命令是:mkdir /mnt/usbmount -t vfat/dev/sda1 /mnt/usb挂载windows下的硬盘mount/dev/hda5 /mnt/evol (如d盘) 挂载镜像文件iso文件mount –o loop **.iso /mnt/cdrom当出现没有读写权限的文件,需要释放权限的话,比如是/home/b704/m 文件夹下的文件有如上问题时chmod -R 755 /home/b704/m /更改文件属性使之能够被普通用户使用chown -R b704:b704 /home/b704/m /具体释放权限给某个用户vi命令时可以对文件进行编辑的命令.通常这种被操作不是文件夹,而是个可编译的文件.修改用户进口令Passwd注意创建用户必须是以root用户名进入才可以执行Useradd 用户名Passwd 用户名输入密码并予以确认.清楚当前屏幕信息Clear。
cadence教程-IC设计工具原理共页课件 (二)
cadence教程-IC设计工具原理共页课件 (二) - Cadence教程-IC设计工具原理共页课件
1. 什么是Cadence？
Cadence是一家专门从事电子设计自动化软件的公司。
其产品涵盖了芯片设计、系统设计、封装设计和PCB设计等领域。
Cadence的软件被广泛应用于半导体、通信、计算机、消费电子等行业。
2. Cadence的主要产品
Cadence的主要产品包括Virtuoso、Allegro、OrCAD、Sigrity等。
其中，Virtuoso是一款用于模拟、布局和验证芯片的工具；Allegro是
一款用于PCB设计的工具；OrCAD是一款用于电路设计的工具；
Sigrity则是一款用于信号完整性分析的工具。
3. Cadence的应用领域
Cadence的软件被广泛应用于各种电子产品的设计和制造中，如手机、平板电脑、笔记本电脑、服务器、网络设备、汽车电子、医疗设备等。
在半导体行业中，Cadence的软件被用于设计各种芯片，如处理器、存储器、模拟集成电路、射频集成电路等。
4. Cadence的优势
Cadence的软件具有高度的可靠性、灵活性和易用性。
其产品支持多种操作系统，如Windows、Linux、Solaris等。
此外，Cadence还提供了丰富的教程和技术支持，帮助用户更好地使用其软件。
5. Cadence的未来发展
随着电子行业的不断发展，Cadence的软件也在不断升级和改进。
未来，Cadence将继续加强与各大芯片厂商和设备厂商的合作，开发出更加先进和适用的软件，为电子行业的发展做出更大的贡献。
Cadence 手册详细图解 英文版
Cadence IC Design ManualFor EE5518ZHENG Huan QunLin Long YangRevised onMay 2017Department of Electrical & Computer EngineeringNational University of SingaporeContents1 INTRODUCTION (4)1.1 Overview of Design Flow (4)1.2 Getting Started with Cadence (6)1.3 Using Online Help (8)1.4 Exit Cadence (8)2 SCHEMATIC ENTRY (9)2.1 Creating a New Design Library (9)2.2 Creating a Schematic Cellview (10)2.3 Adding Components to Schematic (11)2.4 Adding Pins to Schematic (12)2.5 Adding Wires to Schematic (13)2.6 Saving Your Design (14)3 SYMBOL AND TEST CIRCUIT CREATION (15)3.1 Creating Symbol (15)3.2 Editing Symbol (16)3.3 Building Test Bench (18)4 SIMULATING YOUR CIRCUIT (21)4.1 Start the Simulation Environment (21)4.2 Selecting Project Directory (21)4.3 Setup Model Library (22)4.4 Choosing the Desired Analysis (22)4.5 Setup Variables (23)4.6 Saving Simulation Data (24)4.7 Saving Output for Plotting (24)4.8 Viewing the Netlists (25)4.9 Running the Simulation (25)5 PHYSICAL LAYOUT (28)5.1 Layout vs Symbol of CMOS Devices (28)5.2 Starting Layout Editor (29)5.3 Vias (31)5.4 Changing the Grid (33)5.5 Inserting and Editing Instances (34)5.6 Drawing Shapes / Paths (35)5.7 Creating Pins (36)6 DESIGN VERIFICATION: DRC AND LVS (38)6.1 Performing DRC (38)6.2 Performing LVS (40)6.3 Performing PEX (41)7 POST‐LAYOUT SIMULATION (45)7.1 Simulation the Extracted Cell View (45)8 CONCLUSION (46)1INTRODUCTIONThis manual describes how to use Cadence IC design tools. It covers the whole design cycle, from the front-end to the back-end, i.e., from the pre-layout design to the post-layout design.The manual aims to provide a guide for fresh users. Following the manual, users can start doing analog IC design even though the users don’t have any knowledge of the tools.An inverter is used to illustrate the whole cycle of analog IC design, and Cadence Generic 45nm (cg45nm) kit is the technology library used for implementing the inverter. The method stated in the manual can be applied to other type of analog circuit design.1.1Overview of Design FlowFigure 1 shows a typical analog IC design flow.The design flow starts from schematic entry with the Cadence schematic capture tool –Schematic Editor. Devices or cells from the cg45nm or other libraries are used to build your circuit. Your design is hierarchical; therefore higher level schematics also incorporate cells which you have already developed. The schematics which you enter at this stage therefore typically consist of a number of base library cells and also lower level cells designed yourself.These are described in Sections 2 and 3 of the manual.When you have finished designing a particular circuit, you need to simulate it to ensure that it works as expected. It would be unlikely that your circuit works as expected at the first time so you have to repeat the cycle to improve the circuit, as shown in Figure 1, until the circuit works satisfactorily. This must be done for each sub-circuit of your design and then for the top level design. How to simulate and view the performance of simulation results are presented in Sections 4 of the manual.When the performance of the circuit is satisfactory, it is ready to start the physical design or layout of the circuit. The layout starts with the cell or device placement. Once the cells have been placed, routing can be carried out. Routing connects the cells/device of the design.After finishing placement and routing, the layout has to go through the Design Rule Check (DRC) with rule decks provided by PDK provider, to ensure that there is no design rule violation in the layout. The layout has to be rectified accordingly to the rules’ requirement till it passes DRC.Upon a successful DRC, it is Layout-versus-Schematic (LVS) check, to assure that all connections in the layout are correct. The layout has to be amended accordingly to the schematic If LVS doesn’t pass. DRC has to be done whenever layout is changed. The process is repeated until the LVS passes.Figure 1. Analog IC Design FlowThe next step is parasitic extraction (PEX) to get the extracted view of the circuit, which is used for post–layout simulation. The extracted view includes the parasitic effects in both the instances/devices and the required wiring interconnects of the circuit.Following DRC, LVS and PEX, it is post-layout simulation. The post-layout simulation is essential to make sure that the circuit with the extra parasitic parameters functions well and still meet the design specifications. If the performance of the post-layout simulation is not acceptable, back to the stage of schematic entry to check the circuit. Basically, re-design the circuit is necessary. Repeat the whole flow until the results of the post-layout simulation meet the design specifications.If everything is satisfactory, the next stage is GDSII Generation. It generates a file which depicts the low level geometry of layout. GDSII format is industry standard format suitable fora semiconductor company to fabricate and manufacture the chip of layout. This is briefed inthe last section of the manual.1.2Getting Started with CadenceUpon logging into your account, you will be brought to the Linux Desktop Environment.Right click on the desktop and click Open Terminal to open a “window” on the desktop. This window is the Linux command line prompt at which you can run Linux commands. After running a Linux command, this window also shows the output of the command.The following steps show how to start Cadence with cg45nm kit.A.Create a working directory - project (it can be any name as you like) with thecommand:mkdir projectwhere mkdir is Linux command and the project is the directory name;B.Enter the working directory with the command:cd projectwhere the cd is the Linux command;C.Type the followings commands to do the environment setup for using Cadence Generic45nm PDK.cp /app11/cg45nm/USERS/cds.lib .cp /app11/cg45nm/USERS/assura_tech.lib .cp /app11/cg45nm/USERS/pvtech.lib .D.Start cadence in the working directory – project with the following command:virtuoso &where virtuoso is the command to start Cadence IC design tool.Now, Cadence tools are successfully started. Keeps only the Command Input Window (CIW) which is shown in Figure 2.Figure 2. CIW WindowDo not close this CIW and try to keep it in view whenever you are using Cadence. Error messages and output from some of the tools are always sent to the CIW. If something doesn't appear to be working, always check the CIW for error messages. In addition, the CIW allows the user great control over Cadence by interpreting skill commands which are typed into it.E.In the CIW, select Tools Library Manager. The Library Manager pop up as inFigure 3. The Library Manager is where you create, add, copy, delete and organizeyour libraries and cell views.Figure 3. Library Manager WindowYou can see that the library gpdk045 appears in the Library column of the librarymanager.Now, you have started Cadence tool and loaded the cg45nm kit successfully. There are some documents in /app11/cg45nm/ gpdk045_v4_0/docs, and you can always refer to these documents for the information such as devices, device models, DRC rules and others related to cg45nm kit.Next time, you need only to repeat the steps B and D, for launching Cadence virtuoso and doing your project.1.3Using Online HelpCadence provides a comprehensive online manuals for all Cadence tools. You can launch the online help by typing the following command at the Linux prompt.cdnshelpThis invokes the online software manuals. Alternately, there is a help menu on each Cadence window. Manual which is related to that window related will pop-up once clicking on the help button.1.4Exit CadenceTo exit Cadence, just click on the cross sign X or File Exit in CIW. It is necessary to exit Cadence when it is not in use. Your library file would be locked or cannot edited next time if Cadence was not exited properly.2SCHEMATIC ENTRYNow that Cadence is running, you are almost ready to start entering schematics. However, you must first create a library which will be used to store all the parts of your design. Then, schematic can be created in the library.2.1Creating a New Design LibraryA.In the Library Manager window, select File→New→Library. New Library formpops up as shown in Figure 4.B.In the New Library form referring to Figure 4, key in your design library name(example: test) in the field of Name, and then click Ok.C.Click Ok in the pop-up window - the Technology File for New Library, referring toFigure 5.D.Choose gpdk045 in the Attach Library to Technology Library form, referring toFigure 6, and then click Ok.Figure 4. New Library FormFigure 5. Technology File for New Library FormFigure 6. Attach Library to Technology File FormA new library, named test, should appear in your Library Manager window.2.2 Creating a Schematic CellviewA.In Library Manager, select the Library where you would like to create a schematic. Then,select File→New→Cell View.B.Set up the New File form as Figure 7Figure 7. Create CellViewC.Click OK when done. A blank schematic window for the "inv" (your cell name)schematic appears.Explore the functions available by putting your mouse over the toolbar and fixed menu icons.In addition, note that some of the menu selections have alphabets listed to the right of them. These are bind-key or shortcut-key definitions which are very useful in the long run.Test them out during the schematic drawing in subsequent steps.2.3Adding Components to SchematicFigure 8 shows the schematic which you are going to patch, and the property of each component is listed in Table 1.Figure 8. Inverter CircuitTabel 1. Component Properties of Figure 8: Inverter CircuitComponents Library Name Cell Name PropertiesPMOS gpdk045 pmos1v l:45nm w:120nm (default size)NMOS gpdk045 nmos1v l:45nm w:120nm (default size)Here is the example on how to add component instances by placing cell views from libraries. Type “i” bind-key or select Create Instance in the schematic window or click on the menu bar to display Add Instance form. Then in the Add Instance window, select gpdk045as Library, choose the NMOS transistor by selecting nmos1v in Cell and also choose symbol as View, as shown in Figure 9.Figure 9. Add Instance FormSimilarly, add the pmos1v into the schematic. As an example, here we just keep all theparameters as default.If you place a component with the wrong parameter values, select the component and type “q” bindkey or use the Edit→Properties→Objects command to change the parameters. Use the Edit→Move command or type “m” if you place components in the wrong location.2.4Adding Pins to SchematicYou must place I/O pins in your schematic to identify the inputs and the outputs. A pin can be an input, output or an input-output (bi-directional) pin.Type “p” or select Add →Pin from inv Schematic Window or click the Pin fixed menuicon in the schematic window. The Add Pin form appears as Figure 10.Figure 10. Add Pin FormClick Hide and move you cursor to the Schematic Window. Place pins at the correct places and click right mouse key to rotate the pin if necessary.Add pins according to Table 2, paying attention to the direction.Table 2. Pin Names and Direction of invPin Names DirectionVin InputVout OutputVDD, GND Input-OutputCaution: Do not use the add component form to place schematic pins.2.5 Adding Wires to SchematicAdd wires to connect the components and pins in the design.A.Type “w” or select Add →Wire (narrow) in Schematic Window or click (narrow)fixed menu icon.B.In the schematic window, click on a pin of one of your components as the first pointfor your wiring. A diamond shape appears over the starting point of this wire.C.Follow the prompts at the bottom of the design window and click left mouse key onthe destination point for your wire.D.Continue wiring the schematic. When done wiring, press Esc with your cursor in theschematic window to cancel wiring.2.6Saving Your DesignCheck the design to ensure that it is correct and save the design.A.Click the Check and Save icon in the schematic window.B.Observe the CIW output area, for the information of the check and save action.3SYMBOL AND TEST CIRCUIT CREATIONSymbols are useful when creating designs as it is impractical to show every transistor on the top level schematic. Instead, the symbols of cells are created in order to instantiate them in the higher level schematics and make them more readable (i.e. hierarchical designs). Create a symbol for your design so you can place it in a test circuit for simulation.3.1Creating SymbolA.In the inv schematic window, select Create → Cellview → From Cellview. CellviewFrom Cellview pops up as shown in Figure 11.Figure 11. Cellview From Cellview FormB.Click OK in the Cellview From Cellview form. The Symbol Generation Options formappears as Figure 12. Enter the information listed in Table 3 for the symbol.Table 3: Pin SpectificationsLeft Pins : VinRight Pins : VoutTop Pins: VDDBottom Pins: GNDFigure 12. Symbol Generation Options FormC.Click OK in the Symbol Generation Options form. A window with a symbol createdautomatically by the tools pops up, referring to Figure 13.Figure 13. Symbol Generated AutomaticallyD.Observe the CIW output pane and note the messages stating Adding ‘CDFinformation ...’.3.2Editing SymbolYou can modify the symbol to have a more meaningful shape for easy recognition.A.Move your cursor over the symbol, until the entire green rectangle is highlighted. Clickleft to select it.B.Click Delete icon in the symbol window to delete the green rectangle.C.Select Create→Shape→Polygon. Follow the prompts at the bottom of the symbol, anddraw the triangle shown in Figure 14.D.Type “m” or click Move icon in the symbol window, move the pins to the finaldestination.E.Select [@partName], and use Edit→Properties→Object to change it to inverter asshown in Figure 14.Figure 14. Edit Object Properties FormF.Save your edited symbol view. The final symbol is shown in Figure 15.Figure 15. Symbol of inv3.3Building Test BenchTo test the inverter that you have just built, you need to create a test bench. This test bench will also be used during the post-layout simulation.Creating an inv_test schematic cellview with the below information, following the steps listed in Section 2 – SCHEMATIC ENTRY. The test bench is as shown in Figure 17.Library Name : testCell Name : inv_testView Name : schematicLibrary Name Cell Name Propertiestest inv_testanalogLib Vdc VDDanalogLib vpulse Referring to Figure 16analogLib gnd GNDanalogLib cap 1f FFigure 16. Vpulse FormFigure 17. Test Bench – inv_test for inv CircuitNote:There are wire names Vin and Vout in Figure 17. These can be created by clicking on Create Wire Name on the inv_test schematic window. Key in Vin Vout in the Names field of the Add Wire Name form, and then click Hide. Moving your mouse to the schematic window, click the wire where you want it to be named in the same sequence as typing the names in the Names field.4SIMULATING YOUR CIRCUITBefore starting the simulation, make sure that the schematic (inv_test) is open, then perform the following steps.4.1Start the Simulation EnvironmentIn your schematic window, select Launch →ADE L. The Analog Design Environment (ADE) window appears as shown in Figure 18.Figure 18. ADE Window4.2Selecting Project DirectoryIn the ADE window, select Setup→Simulator/ Directory/ Host. A Choosing Simulator form appears as Figure 19. In the Project Directory blank, type in /var/tmp/(desired folder name) to save your simulation files in the /var/tmp directory on the local server. Click OK to confirm.Figure 19. Choosing Simulator/Directory/Host FormAs each user account has a limited quota, this helps to conserve memory space in your account and prevents you from exceeding your account quota. However, note that contents in this folder is deleted periodically every 30 days automatically.4.3Setup Model LibraryIn the ADE window, select Setup Model Libraries. The Model Library setup form appears. Double click the column of section, and then click the down arrow to choose tt which is typical N and P model parameters. The model library setup for the inv_test circuit is shown in Figure 20. Click ok on the setup form to finish the settings.The information of models can be found in/app11/cg45nm/gpdk045_v4_0/docs/gpdk045_pdk_referenceManual.pdf.Figure 20. Model Library Setup for inv_test4.4Choosing the Desired AnalysisIn the ADE window, click the Choose Analyses icon . The Choosing Analyses form appears. Cadence ADE is able to run several types of simulations consecutively. You are then able to view the signals from different simulations at the same time. In this example, we will do transient analysis, so we shall setup transient analyses through the ADE as Figure 21.Figure 21. Setup for Transient Analyses4.5Setup VariablesThere is a variable, VDD, in the inv_test circuit. We need to set a value to it before starting simulation.In the ADE window, click Variables. Enter the name as the variable name VDD, then set the valueas 1.1, and finally click Ok. Please take note that 1.1v is the nominal voltage for this technology.Figure 22. Editing Design Variables4.6Saving Simulation DataThe simulation environment is configured to save all node voltages in the design by default. In larger designs, where saving all of the data requires too much disk space, you can select a specific set of node to save. Following steps show you how to select terminals to save.A.In the ADE window, select Outputs→Save All.B.The Keep Options form appears. Do not modify the form at this time. However, if youneed to save less data, under the first option “Select signals to output”, Click “selected”.4.7Saving Output for PlottingSelect the signals that you would like to observe.A.Select Outputs→To Be Plotted→Select On Design.B.Note that if you click on wires / nets, voltage signals are selected. If you click onconnection nodes, currents flowing through that note and into the component are saved.C.Follow the prompts at the bottom of the schematic window. Click on the output wireslabeled with Vout and Vin (select the wire that you want to monitor).D.Press Esc with your cursor in the schematic window when finished.Now you have set up the simulation environment which as shown in Figure 23. You can save the simulation state. This saves all the information such as the Model Path, outputs, analyses, environment options, and variables so that you do not need to set these parameters the next time again.Figure 23. ADE window with completed settingsIn the ADE window, select Session→Save State. Tick Cellview and then click OK. You can recall your settings by selecting Session→Load State.4.8Viewing the NetlistsSometimes, you need to view the netlist of your circuit or design. You can do so through the ADE, select Simulation→Netlist→Create / Display / Recreate.If there are any errors encountered during this step, check the messages in the CIW and retrace your steps to see that all data was entered properly.4.9Running the SimulationSelect Simulation→Netlist and Run to start the simulation or click on the Run Simulation icon in the Simulation Window. After the simulation is done, a waveform window will pop up showing the simulation results as Figure 24.Click on the waveform window to separate Vin and Vout.You can create a horizontal or vertical marker by clicking Marker on the waveform window. For example, creating a horizontal marker on Figure 24 with put Y Postion at 0.5*VDD=550mV, and then zoom in. The waveform window will look like Figure 25. Delays of the inverter could be found from the reading on the marker.Figure 24. Output of SimulationFigure 25. Waveform with Marker.Explore the icons on the toolbar as well as the various items on the menu. Try to add markers as that is something that will be used often during your simulations. You can also update the titles and labels on your plot to make them easy to read or more meaningful, if necessary.*Quick Tip : Shortcuts “a” and “b” to place a delta marker where you observe the difference between two points. What does shortcuts “v” and “h” do?There are many other functions available in the calculator tool, explore and play around with them.By now, you have finished pre-layout simulation (schematic level simulation). Next, you need to draw the layout of the inverter circuit and then do post-layout simulation to check your circuitperformance.5 PHYSICAL LAYOUTBy now, you should know how to create and simulate your circuit. Once the performance of your design is satisfactory, the next step in the process of making an integrated circuit chip is to create a layout. What is a layout? A layout is basically a drawing of the masks from which your design will be fabricated. Therefore, layout is just as critical as specifying the parameters of your devices.Before we get into the layout, first you need to understand the design rules for layout. Design rules give guidelines for generating layouts. They dictate spaces between wells, sizes of contacts, minimum spacing between a poly and a metal, and many other similar rules.Design rules are essential to any successful layout design, since they account for the various allowances that need to be given during actual fabrication and to account for the sizes and the steps involved in generating masks for the final layout. Note that the layout is very much process dependent, since every process has a certain fixed number of available masks for layout and fabrication.You may find more details on the Design Rules Manual (DRM):/app11/cg45nm/gpdk045_v_4_0/docs/gpdk045_drc.pdf5.1 Layout vs Symbol of CMOS DevicesIn this section, we look at only three devices: nmos1v and pmos1v. Check the process document, you can find the information for other devices.Figure 26 shows the nmos1v device. From layout view, you can see that the terminal B is the black background of the layout window.Figure 26. Layout vs Symbol of NMOSFigure 27 shows the pmos1v device, which looks similar to NMOS device but with P type implant (orange-stripe layer) and N-well (purple surrounding layer). G D SBFigure 27. Layout vs Symbol of PMOS5.2Starting Layout EditorNow we are going to create a new layout in the cell “inv” in “test” library.A.In Library Manager, select File→New→Cellview ... A Create New File form pops up.B.Select "test" as Library Name; enter "inv" as Cell Name, "layout" as View Name.C.Choose Open with Layout XL, and then click OK.Figure 28. Create Cellview – LayoutUseful layerselectionfeatureFigure 29. Layout WindowCell "inv" with "layout" view in library "test" will be created. It is opened up automatically, followed by inv schematic window, as shown in Figure 29. The layout editor contains two main sub-windows, namely the Layers sub-window on the left and Layout Editing window on the right. Notice the Layers sub-window on the left side of the layout view. This sub-window displays the fabrication layers defined in the technology. You can find the cross sectional profile in the process documents.Each layer is represented by a different color and pattern for easier differentiation. The black background on the right can be interpreted as the p-substrate of the wafer.To hide a layer, use the middle scroll button to click on a layer. To disable a layer from use, use the right mouse button.You might notice that some layer names appear more than once in the Layers sub-window. For example, Metal1 appears two times: one as Metal1 drawing, the other as Metal1 pin. Metal1 drawing is a layer with drawing purpose, and such layers with drawing purposes will be fabricated in the mask. The pin layers are symbolic layers and serve to indicate position of I/O pins and define net names. Such layers are not part of the mask layout and will not be fabricated.5.3ViasVias are used to connect between layers, much like those used in PCB design.There are different types of vias for different layer pairs. Normally a via is only for connecting two successive layers, e.g., Metal 1 and Metal 2. In case there is a metal jump between more than two layers, via stacking is required.In the layout window, click Create→Via or type “o” to bring up the via menu. Place the vias on the layout editing window, you can observe the layers that are involved in each type of via. Experiment with the different modes and configurations in the via menu to create arrays and stacks of vias as well. For example,A.Click on Create→Via, the Create Via window pops up as figure 30 shows.B.Choose M1_PO under Via Definition, and click on the layout window to place it andthen press Esc button to stop the placing. You can change the number of Rows and Columns on the Create Via form.C.To view the layers of M1_PO, click to select it first and then press Shift + f key. Observethe via appears different.D.To check the layers used in via M1_PO, select it and then click Edit→Hierarchy→Flatten as shown in figure 31. Click OK on the pop-up form shown in Figure 32.E.Now, you can separate the layers and check layers’ property to find out the layers’ name.Via M1_PO connects layers Metal 1 and Poly as shown in Figure 33.Try to explore different options (Rows, Columns, Stack, etc.) under via menu by yourself, this will be very helpful for layout drawing.Figure 30. Create Via windowsFigure 31. Edit ViaFigure 32. Flatten FormFigure 33. Via M1_POThe M1_PSUB and M1_NWELL contacts are substrate and n-well contacts that are used to connect the bulks of the NMOS and PMOS respectively. For the inverter circuit used in this manual, the bulks of the NMOS and PMOS need to be connected to ground (GND) and VDD respectively.5.4Changing the GridIn Figure 29, the black window on the right is the layout editing window. The position of the cursor in layout editing window is indicated by the coordinate showed on the top right corner of the window after X: and Y:. The unit here is "µm". Move your cursor around the editing window and see the X: Y: values change with step size 0.1. Change the step size to 0.005 as that is the minimum step size for this technology.From Layout Editing window pull down menu, select Options →Display... change "X Snap Spacing" and "Y Snap Spacing" to 0.005 then click on "OK". Now move the cursor around the editing window again, you will see the X: Y: values change with step size 0.005.There are raw grid and fine grid (as small dots) on the window background. If you cannot clearly see the raw grids, from pull down menu select Window →Zoom out by 2In addition to pull down menu and bind key "z", "Zoom Out" is also listed in the picture tool bar to the left of the window. Find it and try it out.Also you may use up, down, left, and right arrows to move around the design window. You will need to use "Zoom in" and "Zoom out" and those arrows many times throughout your design process. So it's not a bad idea to practice them a little bit now.To save and close the cell view, from Virtuoso Editing window, Select Design →Save.。
详细图文IC5141安装说明
操作系统：CentOS-5.5-i386；虚拟机：VMwareWorkstation-6；软件：cadence ic5141 USR6和Base 1、安装CentOS-5.5，在软件定制部分需要立即定制，然后选择旧版支持，Java软件等等。
软件定制选择如下：桌面环境全选；应用程序全选；开发全选；基本系统全选；虚拟化全选；服务器选windows文件服务器，万维网服务器，打印支持。
2、由于CentOS-5.5的tar-1.15.1，sort-5.97，expr-5.97版本过高，需要用tar-1.14，sort-5.2.1，expr-5.2.1才能正常解压安装，而这几个程序可以在CentOS-4.8中找到。
之后，使用root账户登录，分别对应替换高版本的/bin/tar，/bin/sort，/usr/bin/expr。
此处记得备份CentOS-5.5的原件哦！（另外，我也给出了CentOS-4.8和CentOS-5.5中的程序，以便大家下载）3、新建一个用户kury（这个根据喜好，但此处我用kury说明），在/home/kury目录中新建文件夹cadence_install。
之后，在cadence_install里面新建文件夹base，update，用于存放IC5141的base 包跟update包。
base包在电驴上有：ed2k://|file|Cadence.Base.IC5141.Lnx86.3CDs[.ck].rar|1201102747|A4DE108A291CC6BDD86D8E46D3E5 A677|h=PWYDUTUBIMHDVZ2EDLNMRNAKGAVIWJFA|/USR6 update包在论坛里有：/viewthread.php?tid=219912&highlight=USR6此处需要说明，在CentOS-5.5下安装必须要有这两个包，不然不能运行cadence！！！4、解压：Cadence.Base.IC5141.Lnx86.3CDs[.ck] 得到三个base包，一个cadence_license_full.dat；解压：Update_IC50.46.006_lnx86得到四个update包。
cadence教程IC设计工具原理课件
21
EDA概述
CADENCE
• EDA应用于三方面： 印制电路板的设计（PCB） 可编程数字系统设计（CPLD、 FPGA、SOPC） IC设计（ASIC, Soc）
26
EDA概述
CADENCE
• EDA主要供应商：
VHDL仿真 行为综合 逻辑综合 可测性设计 低功耗设计 布局布线
后仿真
Cadence Vantage Synopsys Synopsys Alta Synopsys Compass Mentor Graphics Synopsys Sunrise Compass Synopsys Epic Cadence Avant! Mentor Graphics Synopsys Cadence Compass IKOS Vantage
（4）物理版图设计和验证工具（Cadence公司的Virtuoso Layout Editor，Synopsys公司的ComsSE ,Tanner公司的 L-edit）
（5）模拟电路编辑与仿真（Synopsys公司的HSpice ， Cadence公司的Spectre Simulator ,Tanner公司的S-edit）
第一章 IC设计基础
CADENCE
• 集成电路设计就是根据电路功能和性能 的要求，在正确选择系统配置、电路形 式、器件结构、工艺方案和设计规则的 情况下，尽量减小芯片面积，降低设计 成本，缩短设计周期以保全全局优化， 设计出满足要求的集成电路。其最终的 输出是掩模版图，通过制版和工艺流片 得到所需的集成电路。
• 缺点：会有一定比例的后续工序无法适应软核IP设计， 从而造成一定程度的软核IP修正，在性能上有较大的 不可预知性。
可能是史上最完美的IC5141安装说明档
1、硬件需求（1）内存128M以上（2）硬盘空间10G以上（IC5141安装后约占3G）（3）能被RHEL AS4支持的显卡2、安装RHEL AS4（1）安装X Window（2）安装GNOME、KDE（3）安装所有的开发包工具（4）安装旧版软件支持（5）禁用防火墙和SELinux（6）显卡颜色选用8位或24位（7）默认语言选择英文二、安装步骤1、以root用户登录2、把三张光盘复制到硬盘上，不能直接在光盘上安装(1) mkdir /tmp/ic5141(2) mount /dev/cdrom /media/cdrom(3) cp /media/cdrom/* /tmp/ic5141 -R(4) umount /media/cdrom(5) eject注：以上给出的是第一张盘的复制，另外两张只要重复(2)~(5)就可以全部复制到硬盘中，复制完成，可以在/tmp/ic5141中看到三个目录：CDROM1、CDROM2、CDROM3。
3、添加一个普通用户，该用户用于安装及使用IC5141，不推荐使用root用户进行IC5141的安装和运行。
(1) adduser icer (在系统中增加icer用户)(2) passwd icer (为icer用户设置密码，记住该密码，接下去需要使用)4、建立一个目录，用于IC5141的安装(1) mkdir /eda (在根目录下建立eda目录)(2) chmod 755 /eda (把/eda目录设置为目录所属者完全控制，其他人可进入)(3) chown icer.icer /eda (把/eda目录的所属者及所属组改为icer)4、切换到icer用户，以便进行后续的安装工作(1) su - icer (注意：不要省略中间的连字符，否则将忽略针对该用户的环境变量设置)(1) cd /tmp/ic5141/CDROM1(2) ./SETUP.SH6、IC5141安装程序安装步骤(1) 在“Specify path of install directory \c[OR type [RETURN] to exit]: \c”的提示下输入安装目录：/eda (本例以安装到/eda为例，故输入/eda)(2) 在“Do you want o start softload? [y/n]: \c”的提示下输入y(3) 此后，依次选择：1) Load A vailable Products1) Local2) Otherdon't view README file4) Cadence Cataloga) All of the above2) List Installed Products3) Linux Operating System (lnx86)q) Quit7、安装完成后，设置icer用户的环境变量，内容如下：(1) cd ~(2) vi .bashrc######################################################### .bashrc# User specific aliases and functions# Source global definitionsif [ -f /etc/bashrc ]; then. /etc/bashrcfiCDSDIR=/edaCDS_ROOT=/edaCDS_INST_DIR=/edaCDS_INSTALL_DIR=/eda/tools/dfII/export CDS_LIC_FILE=$CDS_ROOT/share/license/license.datexportPA TH=$CDS_ROOT/tools/bin:$CDS_ROOT/tools/dfII/bin:$CDS_INSTALL_DIR/bin:$CDS_R OOT/tools/spectre/bin:$PA THexport CDS_Netlisting_Node Analogexport LD_ASSUME_KERNEL=2.4.0########################################################8、创建/eda/tools软链接，用于指向/eda/tools.lnx86目录，IC5141中有许多地方是访问/eda/tools目录的。
5141教程
图 1.17
编辑后 inv 的 symbol
保存并退出 symbol 的编辑界面， 同样退出原理图编辑器。 至此原理图的输入 完成。
5．创建仿真电路图
完成电路原理图的输入之后， 为了对设计进行仿真和性能分析， 需要建立一 个仿真平台，将电源、各种激励信号输入待测的电路 inv，然后采用仿真器进行 分析。 （1） 建立设计原理图： 在命令解释器窗口 CIW 中选菜单项 FileNewCellview , 出现“Create New File”对话框，如图 1.18 所示填写、选择相应的选项，点击 OK 按钮，进入原理图编辑器 virtuoso schematic editor 界面。 （同前述电路原理图 输入时的操作一样） 。
图 1.4 选择器件
如图 1.4 选中相应的 pmos 器件的 symbol 后，点击 close 按钮关闭该 library browser 对话框。随后出现 pmos 器件参数表，如图 1.5 所示，按照设计要求添上 相应的参数。当然该表亦可直接填写。
图 1.5 pmos 器件参数表
点击图 1.5 的 Hide 按钮，在原理图编辑器中出现随鼠标移动的 pmos 管的 symbol，放置到相应的位置即可，如下图 1.6 所示。
图 1.20 vdd 例化选项表
图 1.21 gnd 例化选项表
添加负载电容，摆放时点击 Rotate 按钮将其横放；同样设置电源 vdc 和输入信
（A）
（B）
图 1.22 激励与负载表项 Nhomakorabea（C）
号，各个表项分别如图 1.22 所示的内容填写即可。当然在分析的过程中，这些 数值都是可以更改的。 （3）器件互联：连线这里不详述，操作同电路原理图输入。最后得到的电路图 与下图所示一致。
ic5141使用教程
图 1.23 inv 测试电路原理图
择菜单项 DesignCheck and Save （shift-x） ， 至此， 测试电路图的输入完成， 但先不要关闭该原理图编辑窗口。
6．对电路进行仿真分析
对于 ic5141 模拟设计环境 ADE 来说，默认的仿真器是 spectre，这里直接采 用 spectre 对设计进行仿真和分析。关于 spectre 的使用，可以参见联机文档，这 里不详述。 （1）启动模拟设计环境 ADE（Analog Design Environment） ：在 图 1.23 的窗口中 选择菜单项 ToolsAnalog Environment，随即启动 ADE。我们的电路仿真与分 析就要在该平台下进行。 窗口如图 1.24 所示。 ADE 还可以于 CIW 窗口中选择菜
仍然是按照图 1.19 的内容填写表项，点击 Hide 按钮，在原理图编辑其中就 会出现编辑过的 inv 的 symbol， 直接摆放即可。 同样的操作添加 vdd 和 gnd 符号， 注意这里采用的是 analogLIb 库中的元件 （在测试电路图中除待测电路 dut 之外， 其余器件均来自 analogLib） 。添加电源和地选符号项选择列表如下图 1.20、1.21 所示。
1. 环境配置
登陆 Linux 之后进入的目录即是用户的家目录，可以用 PWD 命令查看当前 工作目录并用 cd 命令回至家目录。 首先在家目录下编辑文件 .bashrc（在 Linux 下文件或者目录前面有一个点 （.）的为隐藏，需要用 ls –a 命令查看） ，保证文件中有这样几行： export export export export CDS_ROOT=/opt/eda/cadence/ic5141 CDS_LIC_FILE=$CDS_ROOT/share/license/license.dat CDS_Netlisting_Mode=Analog PATH=$CDS_ROOT/tools/bin:$CDS_ROOT/tools/dfII/bin: $CDS_ROOT/tools/dracula/bin:$PATH export export MOZILLA_HOME=/usr/bin/netscape CDSHOME=/opt/eda/cadence/ic5141
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第二章．Virtuoso Editing的使用简介全文将用一个贯穿始终的例子来说明如何绘制版图。
这个例子绘制的是一个最简单的非门的版图。
§ 2－1 建立版图文件使用library manager。
首先，建立一个新的库myLib，关于建立库的步骤，在前文介绍cdsSpice时已经说得很清楚了，就不再赘述。
与前面有些不同的地方是：由于我们要建立的是一个版图文件，因此我们在technology file选项中必须选择compile a new tech file,或是attach to an exsiting tech file。
这里由于我们要新建一个tech file，因此选择前者。
这时会弹出load tech file的对话框，如图2-1-1所示。
图2-1-1在ASCII Technology File中填入csmc1o0.tf即可。
接着就可以建立名为inv的cell了。
为了完备起见，读者可以先建立inv的schematic view和symbol view（具体步骤前面已经介绍，其中pmos长6u，宽为0.6u。
nmos长为3u，宽为0.6u。
model 仍然选择hj3p和hj3n）。
然后建立其layout view，其步骤为：在tool中选择virtuoso－layout，然后点击ok。
§ 2－2绘制inverter掩膜版图的一些准备工作首先，在library manager中打开inv这个cell的layout view。
即打开了virtuoso editing窗图2-2-1 virtuoso editing窗口口，如图2-2-1所示。
版图视窗打开后，掩模版图窗口显现。
视窗由三部分组成：Icon menu , menu banner ,status banner.Icon menu(图标菜单)缺省时位于版图图框的左边，列出了一些最常用的命令的图标,要查看图标所代表的指令，只需要将鼠标滑动到想要查看的图标上，图标下方即会显示出相应的指令。
menu banner（菜单栏）,包含了编辑版图所需要的各项指令，并按相应的类别分组。
几个常用的指令及相应的快捷键列举如下：Zoom In -------放大 (z)Zoom out by 2------- 缩小2倍(Z)Save ------- 保存编辑(f2) Delete ------- 删除编辑(Del)Undo ------- 取消编辑(u)Redo -------恢复编辑 (U)Move ------- 移动(m)Stretch ------- 伸缩(s)Rectangle -------编辑矩形图形(r)Polygon ------- 编辑多边形图形(P)Path ------- 编辑布线路径(p) Copy -------复制编辑 (c) status banner（状态显示栏），位于menu banner的上方，显示的是坐标、当前编辑指令等状态信息。
在版图视窗外的左侧还有一个层选择窗口（Layer and Selection Window LSW）。
LSW视图的功能：1）可选择所编辑图形所在的层；2）可选择哪些层可供编辑；3）可选择哪些层可以看到。
由于我们所需的部分版图层次在初始LSW中并不存在，因此下一步要做的是：建立我们自己的工艺库所需的版图层次及其显示属性。
为了简单起见，以下仅列出绘制我们这个版图所需的最少版图层次。
层次名称说明Nwell N阱Active 有源区Pselect P型注入掩膜Nselect N型注入掩膜Contact 引线孔，连接金属与多晶硅/有源区Metal1 第一层金属，用于水平布线，如电源和地Via 通孔，连接metal1和metal2Metal2 第二层金属，用于垂直布线，如信号源的I/O口Text 标签Poly 多晶硅，做mos的栅下图是修改后的LSW。
图2-2-2 LSW如何来修改LSW中的层次呢？以下就是步骤：1．切换至CIW窗口，在technology file的下拉菜单中选择最后一项edit layers出现如图窗口图2-2-3 edit layers2．在technology library中选择库mylib，先使用delete 功能去除不需要的层次。
然后点击add添加必需的层次，add打开如下图的窗口：图2-2-4其中，layer name中填入所需添加的层的名称。
Abbv是层次名称缩写。
Number是系统给层次的内部编号，系统保留128－256的数字作为其默认层次的编号而将1－127留给开发者创造新层次。
Purpose是所添加层次的功用，如果是绘图层次，一般选择drawing。
Priority是层次在LSW中的排序位置。
其余的选项一般保持默认值。
在右边是图层的显示属性。
可以直接套用其中某些层次的显示属性。
也可以点击edit resources自己编辑显示属性。
如图2-2-5所示（这个窗口还可以在LSW中调出）编辑方法很简单，读者可以自己推敲，就不再赘述。
上述工作完毕后就得到我们所需的层次。
接着我们就可以开始绘制版图了。
§ 2－3 绘制版图一．画pmos的版图（新建一个名为pmos的cell）1．画出有源区在LSW中，点击active（dg），注意这时LSW顶部显示active字样，说明active层为当前所选层次。
然后点击icon menu中的rectangle icon，在vituoso editing窗口中画一个宽为 3.6u，长为6u的矩形。
这里我们为了定标，必须得用到标尺。
点击misc/ruler即可得到。
清除标尺点击misc/clear ruler。
如果你在绘制时出错，点击需要去除的部分，然后点击delete icon。
2．画栅在LSW中，点击poly（dg），画矩形。
与有源区的位置关系如下图：0.6u6u(gate width)1.5u3.6u图2-2-5 display resource editor3．画整个pmos为了表明我们画的是pmos管，我们必须在刚才图形的基础上添加一个pselect层，这一层将覆盖整个有源区0.6u。
接着，我们还要在整个管子外围画上nwell，它覆盖有源区1.8u。
如下图所示：pselect1.8unwell4．衬底连接pmos的衬底（nwell）必须连接到vdd。
首先，画一个1.2u乘1.2u的active矩形；然后在这个矩形的边上包围一层nselect层（覆盖active0。
6u）。
最后将nwell的矩形拉长，完成后如下图所示：nselectactivepselect这样一个pmos的版图就大致完成了。
接着我们要给这个管子布线。
二．布线pmos管必须连接到输入信号源和电源上，因此我们必须在原图基础上布金属线。
1．首先我们要完成有源区（源区和漏区）的连接。
在源区和漏区上用contact（dg）层分别画三个矩形，尺寸为0.6乘0.6。
注意：contact间距为1.5u。
2．用metal1（dg）层画两个矩形，他们分别覆盖源区和漏区上的contact，覆盖长度为0.3u。
3．为完成衬底连接，我们必须在衬底的有源区中间添加一个contact。
这个contact每边都被active覆盖0.3u。
4．画用于电源的金属连线，宽度为3u。
将其放置在pmos版图的最上方。
布线完毕后的版图如下图所示：图2-3-1 pmos版图通过以上步骤我们完成了pmos的版图绘制。
接下来我们将绘制出nmos的版图。
三．画nmos的版图绘制nmos管的步骤同pmos管基本相同（新建一个名为nmos的cell）。
无非是某些参数变化一下。
下面给出nmos管的图形及一些参数，具体绘制步骤就不再赘述。
图2-3-2nmos四．完成整个非门的绘制及绘制输入、输出1．新建一个cell（inv）。
将上面完成的两个版图拷贝到其中，并以多晶硅为基准将两图对齐。
然后，我们可以将任意一个版图的多晶硅延长和另外一个的多晶硅相交。
2．输入：为了与外部电路连接，我们需要用到metal2。
但poly和metal2不能直接相连，因此我们必须得借助metal1完成连接。
具体步骤是：a．在两mos管之间画一个0.6乘0.6的contactb．在这个contact上覆盖poly，过覆盖0.3uc．在这个contact的左边画一个0.6乘0.6的via，然后在其上覆盖metal2（dg），过覆盖0.3ud．用metal1连接via和contact，过覆盖为0.3u从下图中可以看得更清楚：metal13．连起来（任意延长一个的metal1，与另一个相交）。
然后在其上放置一个via，接着在via上放置metal2。
五．作标签1．在LSW中选择层次text（d3），点击create/label，在弹出窗口中的label name中填入vdd！并将它放置在版图中相应的位置上。
2．按同样的方法创制gnd！、A和Out的标签。
完成后整个的版图如下：图2-3-4 非门的版图至此，我们已经完成了整个非门的版图的绘制。
下一步将进行DRC检查，以检查版图在绘制时是否有同设计规则不符的地方。