外文翻译-温度计

毕业论文(设计)文献翻译本翻译源自于：CNKI毕业设计名称：基于单片机的转速温度智能测控系统设计外文翻译名称：DS18B20 温度计学生姓名：蔡信鹏院 (系)：电子信息工程学院专业班级：电气10901指导教师：李金辅导教师：李金时间：2013年2月至2013年6月DS18B20 数字温度计Ching Dai著，蔡信鹏译描述DS18B20 数字温度计提供9至12位温度读数，指示器件的温度。

信息经过单线接口送入DS18B20或送出，因此从中央处理器到DS18B20仅需连接一条（和地）。

读、写和完成温度变换所需的电源可以有数据线本身提供，而不需要外部电源。

因为每一个DS18B20有唯一的系列号，因此多个DS18B20可以存在于同一条单线总线上。

这允许在许多不同的地方放置温度灵敏器件。

此特性的应用范围包括HVAC环境控制，建筑物、设备或机械内的温度检测，以及过程监视和控制中的温度检测。

特性独特的单线接口，只需一个接口引脚即可通信。

多点能力使分布式温度检测应用得以简化。

不需要外部元件。

可用数据线供电，提供3.0V到5.5V的电源。

不需备份电源。

测量范围从-55°C到+125°C，等效的华氏温标范围是-67°F到+257°F以9到12位数字值方式读出温度。

在750毫秒内把12位温度变换为数字。

用户可定义的，非易失性的温度警告设置。

告警搜索命令识别和寻址温度在编定的极限之外的器件（温度告警情况）。

应用范围包括恒温控制，工业系统，消费类产品，温度计或任何热敏系统。

引脚排列引脚说明GND–地DQ –数字输入输出VDD–可选的VDDNC –不连接详细引脚说明综述图1的方框图表示DS18B20的主要部件。

DS18B20有三个主要的数据部件：1）64为激光ROM，2）温度灵敏元件，3）非易失性温度告警触发器TH和TL。

器件从单线的通信线取得其电源，在信号线为高电平的时间周期内，把能量贮存在内部的电容器中，在单信号线为低电平的时间期内断开此电源，直到信号线变为高电平重新接上寄生（电容）电源为止，作为另一种可供选择的方法，DS18B20也用外部5V电源供电。

与DS18B20的通信经过一个单线接口。

在单线接口情况下，在ROM操作未定建立之前不能使用存贮器和控制操作。

主机必须首先提供五种ROM操作命令之一：1）读ROM，2）符合ROM，3）搜索ROM,4)跳过ROM，5)告警搜索。

这些命令对每一个器件的64位激光ROM部分进行操作。

如果在单线上有许多器件，那么可以挑选出一个特定的器件，并给总线上的主机指示存在多少器件及其类型。

在成功地执行了ROM操作序列之后，可使用贮存2器和控制操作。

然后主机可以提供六种存贮器和操作命令之一。

一个操作命令指示DS18B20完成温度测量。

改测量的结果放入DS18B20的高速暂存存贮器，通过发出读暂存存储器内容的存储器操作命令可以读出此结果。

每一温度告警触发器TH和TL构成一个字节的EPROM。

如果不对DS18B20施加告警搜索命令，这些寄存器用作通用用户存储器。

使用存储器操作命令可以写TH和TL。

对这些寄存器的读访问通过便簮存储器。

所以数据均以最低有效位在前的方式被读写。

单线总线系统单线总线是一种具有一个总线主机和一个或若干个从机的系统。

DS18B20起从机的作用。

这种总线系统的讨论分为三个题目:硬件接法，处理顺序，以及单线信号（信号类型与定时）。

硬件接法根据定义，单线总线只有一根线：这一点很重要的，即线上的第一个器件能在适当的时间驱动该总线。

为了做到这一点第一个连接到总线上的器件必须具有漏极开路或三态输出。

DS18B20的单线接口。

多站总线由单线总线和多个与之相连的从属器件组成。

单线总线要求近似等于5 k.单线总线的空闲状态是高电平。

不管任何原因，如果执行需要被挂起，那么，若要重新恢复执行，总线必须保持在空闲状态。

如果不满足这一点且总线保持在低电平时间大于480微秒，那么总线上所有的器件均被复位。

硬件连接图处理顺序经过单线总线接口访问DS18B20的协议如下：初始化ROM操作命令存贮器操作命令处理/数据初始化单线总线上的所有处理均从初始化序列开始。

初始化序列包括总线主机发出一复位脉冲，接着由从属器件送出存在脉冲。

ROM操作命令一旦总线主机检测到从属器件的存在，他便可以发出器件ROM操作命令之一。

所有ROM操作命令均由8位长，这些命令列表如下：读ROM [33H]此命令允许总线主机读DS18B20的8位产品系列编码，唯一的48位序列号，以及8位的CRC。

此命令只能在总线上仅有一个DS18B20得情况下可以使用。

如果总线上存在多于一个得从属器件，那么所有从片企图同时发送时将发生数据冲突的现象。

符合ROM [55h]符合ROM命令。

后继以64位的ROM数据序列，允许总线主机对多点总线上的DS18B20寻址。

只有与64位ROM序列严格相符的DS18B20才能对后继的存贮器操作命令作出响应。

所有与64位ROM序列不符的从片将等待复位脉冲。

此命令在总线数据上有单个或多个器件的情况下均可使用。

跳过ROM[CCh]在单点总线系统中，此命令通过允许总线主机不提供64位ROM编码而访问存储器操作来节省时间。

如果在总线上存在多于一个得从属器件而且在跳过ROM 命令之后发出读命令，那么由于多个从片同时发送数据，会在总线上发生数据冲突搜索ROM[F0h]当系统开始工作时，总线主机可能不知道单线总线上的器件个数或者不知道其64位ROM编码。

搜索ROM命令允许总线主机使用一种消去处理来识别总线上的所有从片的64位ROM编码。

告警搜索[ECh]此命令的流程与搜索ROM命令相同。

但是，仅在最近一次温度测量出现告警的情况下，DS18B20才对此命令作出响应。

告警的条件定义为温度高于TH或低于TL。

只要DS18B20一上电，告警条件就保持在设置状态，直到另一次温度测量告警。

ROM搜索举例ROM搜索过程是简单三步过程的重复：读一位，读核位的补码，然后写所需的那一位的值。

总线主机在ROM的每一位上完成这一简单的三步过程。

在全部过程完成之后，总线主机便知道一个器件中ROM的内容，器件中其余的数以及他们的ROM编码可以游另外一个过程来识别。

以下ROM搜索过程的例子假设四个不同的器件连接到同一条单线总线上。

四个器件的ROM数据如下所示：ROM1 00110101…ROM2 10101010…ROM3 11110101…ROM4 00010001…搜索过程如下：1.总线主机通过发出复位脉冲开始初始化序列，从属器件通过发出同时的存在脉冲作出响应。

2.然后总线主机在单线总线上发出搜索人ROM命令。

3.总线主机从单线过程中读一位。

每一器件通过把他们各自ROM数据的第一位的值放到单线总线上来作出响应。

ROM1和ROM4:将把一个0放在单线总线上，即，把它拉至低电平。

ROM2和3通过使总线停留在高电平而把1放在单线总线上。

结果是线上所有器件的逻辑与，因此总线主机接收到一个0.总线主机读另一位。

因此搜索ROM数据命令正在执行，所以单线总线上所有器件通过把各自ROM数据第一位的补码放到单线总线上来对这第二个读作出响应。

ROM1和ROM2把1放在单总线上，使之处于高电平。

ROM2和ROM3把0放在单线上，因此他将被拉至低电平。

对于第一个ROM数据位的补码总线主机观察到得仍是一个0.总线主机便可决定单线总线上有一些第一位为0的器件和一些第一位为1的器件。

4.总线主机写一个0.在这次搜索过程的其余部分，将不选择ROM2和ROM3，仅留下连接到单线总线的ROM1和ROM4。

5.总线主机再执行两次读，并在一个1位之后接收到一个0位，这表示所有还连接在总线上的器件的第二个ROM数据位为0.6.总线主机接着写一个0，使ROM1和ROM4二者保持连接。

7.总线主机执行两次连读，并接收到两次0数据位。

这表示连接着的器件ROM数据的第三位都是1数据位和0数据位。

8.总线主机写一个数据位。

这将不选择ROM1而把ROM4作为唯一仍连接着的器件加以保留。

9.总线主机读ROM4的ROM数据位的剩余部分，而且访问需要的部件。

这就完成了第一个过程并且唯一的识别单线总线上的部件。

10.总线主机通过重复步骤1至7开始一个新的ROM搜索序列。

11.总线主机写一个1，这将不与ROM4发生联系，而唯一的与ROM1仍保持着联系。

12.总线主机对于ROM1读出ROM位的剩余部分而且，如果需要的话，与内部逻辑通信。

这就完成了第二个ROM搜索过程，在其中ROM中的另一个被找到。

13.总线主机通过重复步骤1至3开始一次新的ROM搜索。

注意下述内容：在第一次ROM搜索过程中，总线主机知道一个单线器件的唯一的ID号。

取得部件唯一ROM编码的时间为：960us+(8+3×64)us=13.16ms因此总线主机每秒钟能够识别75个不同的单线器件。

DS18B20 Digital ThermometerChing DaiDESCRIPTIONThe DS18B20 Digital Thermometer provides 9 to 12-bit (configurable) temperature readings which indicate the temperature of the device.Information is sent to/from the DS18B20 over a 1-Wire interface, so that only one wire (and ground) needs to be connected from a central microprocessor to a DS18B20. Power for reading, writing, and performing temperature conversions can be derived from the data line itself with no need for an external power source.Because each DS18B20 contains a unique silicon serial number, multiple DS18B20s can exist on the same 1-Wire bus. This allows for placing temperature sensors in many different places. Applications where this feature is useful include HV AC environmental controls, sensing temperatures inside buildings, equipment or machinery, and process monitoring and control.FEATURESUnique 1-Wire interface requires only one port pin for communicationMultidrop capability simplifies distributed temperature sensing applicationsRequires no external componentsCan be powered from data line. Power supply range is 3.0V to 5.5VZero standby power requiredMeasures temperatures from -55°C to+125°C. Fahrenheit equivalent is -67°F to +257°FThermometer resolution is programmable from 9 to 12 bitsConverts 12-bit temperature to digital word in 750 ms (max.)User-definable, nonvolatile temperature alarm settingsAlarm search command identifies and addresses devices whose temperature is outside of programmed limits (temperature alarm condition)Applications include thermostatic controls, industrial systems, consumerproducts,thermometers, or any thermally sensitivesystem.PIN ASSIGNMENTPIN DESCRIPTIONGND - GroundDQ - Data In/OutVDD - Power Supply V oltageNC - No ConnectDETAILED PIN DESCRIPTIONOVERVIEWThe block diagram of Figure 1 shows the major components of the DS18B20. The DS18B20 has four main data components: 1) 64-bit lasered ROM, 2) temperature sensor, 3) nonvolatile temperature alarm triggers TH and TL. The device derives its power from the 1-Wire communication line by storing energy on an internal capacitor during periods of time when the signal line is high and continues to operate off this power source during the low times of the 1-Wire line until it returns high to replenishthe parasite (capacitor) supply. As an alternative, the DS18B20 may also be powered from an external 3 volt - 5.5 volt supply.DS18B20 BLOCK DIAGRAM Figure 1Communication to the DS18B20 is via a 1-Wire port. With the 1-Wire port, the memory and control functions will not be available before the ROM function protocol has been established. The master must first provide one of five ROM function commands: 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, or 5) Alarm Search. These commands operate on the 64-bit lasered ROM portion of eachdevice and can single out a specific device if many are present on the 1-Wire line as well as indicate to the bus master how many and what types of devices are present. After a ROM function sequence has been successfully executed, the memory and control functions are accessible and the master may then provide any one of the six memory and control function commands.One control function command instructs the DS18B20 to perform a temperature measurement. The result of this measurement will be placed in the DS18B20’s scratch-pad memory, and may be read by issuing a memory function command which reads the contents of the scratchpad memory. The temperature alarm triggers TH and TL consist of 1 byte EEPROM each. If the alarm search command is not applied to the DS18B20, these registers may be used as general purpose user memory. The scratchpad also contains a configuration byte to set the desired resolution of the temperature to digital conversion. Writing TH, TL, and the configuration byte is done using a memory function command. Read access to these registers is through the scratchpad. All data is read and written least significant bit first.1-WIRE BUS SYSTEMThe 1-Wire bus is a system which has a single bus master and one or more slaves. The DS18B20 behaves as a slave. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types and timing).HARDWARE CONFIGURATIONThe 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open drain or 3-state outputs. The 1-Wire port of the DS18B20 (DQ pin) is open drain with an internal circuit equivalent to that shown in Figure 9. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The 1-The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idle state if the transaction is to resume. Infinite recovery time can occur between bits so long as the 1-Wire bus is in the inactive (high) state during the recovery period. If this does not occur and the bus is left low for more than 480 s, all components on the bus will be reset.HARDWARE CONFIGURATIONTRANSACTION SEQUENCEThe protocol for accessing the DS18B20 via the 1-Wire port is as follows:_ Initialization_ ROM Function Command_ Memory Function Command_ Transaction/DataINITIALIZATIONAll transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS18B20 is on the bus and is ready to operate. For more details, see the “1-Wire Signaling” section.ROM FUNCTION COMMANDSOnce the bus master has detected a presence, it can issue one of the five ROM function commands. All ROM function commands are 8 bits long. A list of these commands follows (refer to flowchart in Figure 5)Read ROM [33h]This command allows the bus master to read the DS18B20’s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can only be used if there is a single DS18B20 on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired AND result).Match ROM [55h]The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS18B20 on a multidrop bus. Only the DS18B20 that exactly matches the 64-bit ROM sequence will respond to the following memory function command. All slaves that do not match the 64-bit ROM sequence will wait for a reset pulse. This command can be used with a single or multiple devices on the bus.Skip ROM [CCh]This command can save time in a single drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and a Read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired AND result).Search ROM [F0h]When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or their 64-bit ROM codes. The search ROMcommand allows the bus master to use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus.Alarm Search [ECh]The flowchart of this command is identical to the Search ROM command. However, the DS18B20 will respond to this command only if an alarm condition has been encountered at the last temperature measurement. An alarm condition is defined as a temperature higher than TH or lower than TL. The alarm condition remains set as long as the DS18B20 is powered up, or until another temperature measurement reveals a non-alarming value. For alarming, the trigger values stored in EEPROM are taken into account. If an alarm condition exists and the TH or TL settings are changed, another temperature conversion should be done to validate any alarm conditions.Example of a ROM SearchThe ROM search process is the repetition of a simple three-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple, three-step routine on each bit of the ROM. After one complete pass, the bus master knows the contents of the ROM in one device. The remaining number of devices and their ROM codes may be identified by additional passes.The following example of the ROM search process assumes four different devices are connected to the same 1-Wire bus. The ROM data of the four devices is as shown:ROM1 00110101...ROM2 10101010...ROM3 11110101...ROM4 00010001...The search process is as follows:1. The bus master begins the initialization sequence by issuing a reset pulse. The slave devices respond by issuing simultaneous presence pulses.2. The bus master will then issue the Search ROM command on the 1-Wire bus.3. The bus master reads a bit from the 1-Wire bus. Each device will respond by placing the value of the first bit of their respective ROM data onto the 1-Wire bus. ROM1 and ROM4 will place a 0 onto the 1-Wire bus, i.e., pull it low. ROM2 and ROM3 will place a 1 onto the 1-Wire bus by allowing the line to stay high. The resultis the logical AND of all devices on the line, therefore the bus master sees a 0. The bus master reads another bit. Since the Search ROM data command is being executed,all of the devices on the 1-Wire bus respond to this second read by placing the complement of the first bit of their respective ROM data onto the 1-Wire bus. ROM1 and ROM4 will place a 1 onto the 1-Wire, allowing the line to stay high. ROM2 and ROM3 will place a 0 onto the 1-Wire, thus it will be pulled low. The bus master again observes a 0 for the complement of the first ROM data bit. The bus master has determined that there are some devices on the 1-Wire bus that have a 0 in the first position and others that have a 1. The data obtained from the two reads of the three-step routine have the following interpretations:4. The bus master writes a 0. This deselects ROM2 and ROM3 for the remainder of this search pass,leaving only ROM1 and ROM4 connected to the 1-Wire bus.5. The bus master performs two more reads and receives a 0-bit followed by a 1-bit. This indicates that all devices still coupled to the bus have 0s as their second ROM data bit.6. The bus master then writes a 0 to keep both ROM1 and ROM4 coupled.7. The bus master executes two reads and receives two 0-bits. This indicates that both 1-bits and 0-bits exist as the 3rd bit of the ROM data of the attached devices.8. The bus master writes a 0-bit. This deselects ROM1, leaving ROM4 as the only device stillconnected.9. The bus master reads the remainder of the ROM bits for ROM4 and continues to access the part ifdesired. This completes the first pass and uniquely identifies one part on the 1-Wire bus.10. The bus master starts a new ROM search sequence by repeating steps 1 through 7.11. The bus master writes a 1-bit. This decouples ROM4, leaving only ROM1 still coupled.12. The bus master reads the remainder of the ROM bits for ROM1 and communicates to the underlying logic if desired. This completes the second ROM search pass, in which another of the ROMs was found.13. The bus master starts a new ROM search by repeating steps 1 through 3.NOTE:The bus master learns the unique ID number (ROM data pattern) of one 1-Wire device on each ROMSearch operation. The time required to derive the part’s unique ROM code is:The bus master is therefore capable of identifying 75 different 1-Wire devices per second.。