反激同步整流芯片FAN6024应用资料中文版

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,OPA602BP,OPA602AU2K5,OPA602AU2K5E4,OPA602APG4,OPA602AUE4,OPA602AUG4, 规格书,Datasheet 资料

Copyright © 1987, Texas Instruments Incorporated

芯天下--/
ABSOLUTE MAXIMUM RATINGS(1)
Supply Voltage ............................................................................... ±18VDC Internal Power Dissipation (TJ ≤ +175°C) .................................... 1000mW Differential Input Voltage .............................................................. Total VS Input Voltage Range ............................................................................ ±VS Storage Temperature Range P and U Packages ....................................................... –40°C to +125°C Operating Temperature Range P and U Packages ........................................................ –25°C to + 85°C Lead Temperature U Package, SO (3s) .................................................................... +260°C Output Short-Circuit to Ground (+25°C) ................................... Continuous Junction Temperature .................................................................... +175°C NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability.

主流微波雷达人体红外感应LD602芯片规格书

主流微波雷达人体红外感应LD602芯片规格书一、概括LD602是一款专为热释电红外传感器信号放大及处理输出的数模混合专用芯片，内部集成了运算放大器、双门限电压比较器、参考电压源、延时时间定时器和封锁时间定时器及状态控制器等，专用于防盗报警系统、人体门控制装置、照明控制开关等场合。

LD602电源工作电压为+3V～+6V，采用CMOS工艺数模混合相结合的集成电路，8个引脚数封装设计，降低了外围电路元件数和整体成本,节省了PCB板空间。

二、应用场合■红外报警器/语音迎宾器■红外感应灯■自动门控控制■自动灯光照明系统■微波雷达感应开关■森林防火报警器三、主要特点●静态功耗小，3V工作电源时功耗小于45uA,5V工作电源时功耗小于75uA，非常适合电池供电系统应用,QQ:298391364●高输入阻抗运算放大器，可与多种传感器匹配，进行信号处理，可作为微波人体感应处理芯片●双向鉴幅器，可有效抑制干扰●内置参考电压，供内部比较器和运放的参考电压●内设延时时间定时器和封锁时间定时器，改变振荡器频率即可设定定时延时时间●8脚红外热释电专用芯片，外围电路简单，成本低●外围元器件少，只需配置第一级运放的增益和振荡器的RC器件即能可靠工作●工作电压+3V~+6V●封装形式SOP8●包装方式管装四、引脚定义五、引脚说明引脚号引脚名功能描述1OUT1内部第一级运放的输出端2IN1内部第一级运放的输入端3VC 触发禁止端当该脚VC电压<0.2Vdd时，禁止触发,即输出信号OUT一直保持低电平当该脚VC电压>0.2Vdd时，允许触发,即输出状态跟随输入信号触发4A 可重复触发和不可重复触发控制端当A=“1”时，允许重复触发当A=“0”时，不可重复触发5GND芯片地6OUT2控制信号输出端，高电平有效输出7CT 振荡器控制端，该脚需对地外接一个振荡电容和对Vdd外接一个上拉电阻8VIN电源输入端，范围3V~6V六、经典常用电路红外感应应用电路微波人体感应方案其中Q2为微波三极管，天线为板载微波天线。

ADC12062CIVF中文资料

TL H 11490ADC12062 12-Bit1 MHz 75 mW A D Converter with Input Multiplexer and Sample HoldDecember1994 ADC1206212-Bit 1MHz 75mW A D Converterwith Input Multiplexer and Sample HoldGeneral DescriptionUsing an innovative multistep conversion technique the12-bit ADC12062CMOS analog-to-digital converter digitizessignals at a1MHz sampling rate while consuming a maxi-mum of only75mW on a single a5V supply TheADC12062performs a12-bit conversion in three lower-res-olution‘‘flash’’conversions yielding a fast A D without thecost and power dissipation associated with true flash ap-proachesThe analog input voltage to the ADC12062is tracked andheld by an internal sampling circuit allowing high frequencyinput signals to be accurately digitized without the need foran external sample-and-hold circuit The multiplexer outputis available to the user in order to perform additional exter-nal signal processing before the signal is digitizedWhen the converter is not digitizing signals it can be placedin the Standby mode typical power consumption in thismode is100m WFeaturesY Built-in sample-and-holdY Single a5V supplyY Single channel or2channel multiplexer operationY Low Power Standby modeKey SpecificationsY Sampling rate1MHz(min)Y Conversion time740ns(typ)Y Signal-to-Noise Ratio f IN e100kHz69 5dB(min)Y Power dissipation(f s e1MHz)75mW(max)Y No missing codes over temperature GuaranteedApplicationsY Digital signal processor front endsY InstrumentationY Disk drivesY Mobile telecommunicationsY Waveform digitizersBlock DiagramTL H 11490–1 Ordering InformationIndustrial(b40 C s T A s a85 )PackageADC12062BIV V44Plastic Leaded Chip CarrierADC12062BIVF VGZ44A Plastic Quad Flat PackageADC12062CIV V44Plastic Leaded Chip CarrierADC12062CIVF VGZ44A Plastic Quad Flat PackageADC12062EVAL Evaluation BoardTRI-STATE is a registered trademark of National Semiconductor CorporationC1995National Semiconductor Corporation RRD-B30M75 Printed in U S AAbsolute Maximum Ratings(Notes1 2)If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage(V CC e DV CC e AV CC)b0 3V to a6V Voltage at Any Input or Output b0 3V to V CC a0 3V Input Current at Any Pin(Note3)25mA Package Input Current(Note3)50mA Power Dissipation(Note4)875mW ESD Susceptibility(Note5)2000V Soldering Information(Note6)V Package Infrared 15seconds a300 C VF PackageVapor Phase(60seconds)a215 C Infrared(15seconds)a220 C Storage Temperature Range b65 C to a150 C Maximum Junction Temperature(T JMAX)150 C Operating Ratings(Notes1 2)Temperature Range T MIN s T A s T MAX ADC12062BIV ADC12062CIVADC12062BIVF ADC12062CIVF b40 C s T A s a85 C Supply Voltage Range(DV CC e AV CC)4 5V to5 5VConverter Characteristics The following specifications apply for DV CC e AV CC e a5V V REF a(SENSE)e a4 096V V REF b(SENSE)e AGND and f s e1MHz unless otherwise specified Boldface limits apply for T A e T J from T MIN to T MAX all other limits T A e T J e a25 CSymbol Parameter ConditionsTyp Limit Units (Note7)(Note8)(Limit)Resolution12BitsDifferential Linearity Error T A e25 C g0 4g0 8LSB(max)T MIN to T MAX g0 95LSB(max)Integral Linearity Error T MIN to T MAX(BIV Suffix)g0 4g1 0LSB(max) (Note9)TA e a25 C(CIV Suffix)g0 4g1 0LSB(max)T MIN to T MAX(CIV Suffix)g1 5LSB(max) Offset Error T MIN to T MAX(BIV Suffix)g0 3g1 25LSB(max)T A e a25 C(CIV Suffix)g0 3g1 25LSB(max)T MIN to T MAX(CIV Suffix)g2 0LSB(max) Full Scale Error T MIN to T MAX(BIV Suffix)g0 2g1 0LSB(max)T A e a25 C(CIV Suffix)g0 2g1 0LSB(max)T MIN to T MAX(CIV Suffix)g1 5LSB(max) Power Supply Sensitivity DV CC e AV CC e5V g10%g1 0LSB(max) (Note15)R REF Reference Resistance750500X(min) 1000X(max)V REF(a)V REF a(SENSE)Input Voltage AV CC V(max)V REF(b)V REF b(SENSE)Input Voltage AGND V(min)V IN Input Voltage Range To V IN1 V IN2 or ADC IN AV CC a0 05V V(max)AGND b0 05V V(min) ADC IN Input Leakage AGND to AV CC b0 3V0 13m A(max) C ADC ADC IN Input Capacitance25pFMUX On-Channel Leakage AGND to AV CC b0 3V0 13m A(max)MUX Off-Channel Leakage AGND to AV CC b0 3V0 13m A(max) C MUX Multiplexer Input Cap7pFMUX Off Isolation f IN e100kHz92dB2Dynamic Characteristics(Note10)The following specifications apply for DV CC e AV CC e a5V V REF a(SENSE)e a4 096V V REF b(SENSE)e AGND R S e25X f IN e100kHz 0dB from fullscale and f s e1MHz unless otherwise specified Boldface limits apply for T A e T J from T MIN to T MAX all other limits T A e T J e a25 CSymbol Parameter ConditionsTyp Limit Units (Note7)(Note8)(Limit)SINAD Signal-to-Noise Plus T MIN to T MAX7168 0dB(min) Distortion RatioSNR Signal-to-Noise Ratio T MIN to T MAX7269 5dB(min) (Note11)THD Total Harmonic Distortion T A e a25 C b82b74dBc(max) (Note12)T MIN to T MAX b70dBc(max) ENOB Effective Number of Bits T MIN to T MAX11 511 0Bits(min) (Note13)IMD Intermodulation Distortion f IN e102 3kHz 102 7kHz b80dBc DC Electrical Characteristics The following specifications apply for DV CC e AV CC e a5V V REF a(SENSE)e a4 096V V REF b(SENSE)e AGND and f s e1MHz unless otherwise specified Boldface limits apply for T A e T J from T MIN to T MAX all other limits T A e T J e a25 CSymbol Parameter ConditionsTyp Limit Units (Note7)(Note8)(Limit)V IN(1)Logical‘‘1’’Input Voltage DV CC e AV CC e a5 5V2 0V(min)V IN(0)Logical‘‘0’’Input Voltage DV CC e AV CC e a4 5V0 8V(max) I IN(1)Logical‘‘1’’Input Current0 11 0m A(max) I IN(0)Logical‘‘0’’Input Current0 11 0m A(max)V OUT(1)Logical‘‘1’’Output Voltage DV CC e AV CC e a4 5VI OUT e b360m A2 4V(min)I OUT e b100m A4 25V(min) V OUT(0)Logical‘‘0’’Output Voltage DV CC e AV CC e a4 5V0 4V(max)I OUT e1 6mAI OUT TRI-STATE Output Pins DB0–DB110 13m A(max)Leakage CurrentC OUT TRI-STATE Output Capacitance Pins DB0–DB115pFC IN Digital Input Capacitance4pFDI CC DV CC Supply Current23mA(max) AI CC AV CC Supply Current1012mA(max) I STANDBY Standby Current(DI CC a AI CC)PD e0V20m A3AC Electrical Characteristics The following specifications apply for DV CC e AV CC e a5V V REF a(SENSE)e a4 096V V REF b(SENSE)e AGND and f s e1MHz unless otherwise specified Boldface limits apply for T A e T J from T MIN to T MAX all other limits T A e T J e a25 CSymbol Parameter ConditionsTyp Limit Units (Note7)(Note8)(Limits)f s Maximum Sampling Rate1MHz(min)(1 t THROUGHPUT)t CONV Conversion Time740600ns(min) (S H Low to EOC High)980ns(max)t AD Aperture Delay20ns (S H Low to Input Voltage Held)t S H S H Pulse Width5ns(min)550ns(max)t EOC S H Low to EOC Low9560ns(min) 125ns(max)t ACC Access Time C L e100pF1020ns(max) (RD Low or OE High to Data Valid)t1H t0H TRI-STATE ControlR L e1k C L e10pF2540ns(max) (RD High or OE Low to Databus TRI-STATE)t INTH Delay from RD Low to INT High C L e100pF3560ns(max)t INTL Delay from EOC High to INT Low C L e100pFb25b35ns(min) b10ns(max)t UPDATE EOC High to New Data Valid515ns(max)t MS Multiplexer Address Setup Time50ns(min) (MUX Address Valid to EOC Low)t MH Multiplexer Address Hold Time50ns(min) (EOC Low to MUX Address Invalid)t CSS CS Setup Time20ns(min) (CS Low to RD Low S H Low or OE High)t CSH CS Hold Time20ns(min) (CS High after RD High S H High or OE Low)t WU Wake-Up Time1m s (PD High to First S H Low)Note1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is functional These ratings do not guarantee specific performance limits however For guaranteed specifications and test conditions see the Electrical Characteris-tics The guaranteed specifications apply only for the test conditions listed Some performance characteristics may degrade when the device is not operated under the listed test conditionsNote2 All voltages are measured with respect to GND(GND e AGND e DGND) unless otherwise specifiedNote3 When the input voltage(V IN)at any pin exceeds the power supply rails(V IN k GND or V IN l V CC)the absolute value of current at that pin should be limited to25mA or less The50mA package input current limits the number of pins that can safely exceed the power supplies with an input current of25mA to twoNote4 The maximum power dissipation must be derated at elevated temperatures and is dictated by T JMAX i JA and the ambient temperature T A The maximum allowable power dissipation at any temperature is P D e(T JMAX b T A) i JA or the number given in the Absolute Maximum Ratings whichever is lower i JA for the V (PLCC)package is55 C W i JA for the VF(PQFP)package is62 C W In most cases the maximum derated power dissipation will be reached only during fault conditions4Note5 Human body model 100pF discharged through a1 5k X resistor Machine model ESD rating is200VNote6 See AN-450‘‘Surface Mounting Methods and Their Effect on Product Reliability’’or the section titled‘‘Surface Mount’’found in a current National Semiconductor Linear Data Book for other methods of soldering surface mount devicesNote7 Typicals are at a25 C and represent most likely parametric normNote8 Tested limits are guaranteed to National’s AOQL(Average Outgoing Quality Level)Note9 Integral Linearity Error is the maximum deviation from a straight line between the measured offset and full scale endpointsNote10 Dynamic testing of the ADC12062is done using the ADC IN input The input multiplexer adds harmonic distortion at high frequencies See the graph in the Typical Performance Characteristics section for a typical graph of THD performance vs input frequency with and without the input multiplexerNote11 The signal-to-noise ratio is the ratio of the signal amplitude to the background noise level Harmonics of the input signal are not included in its calculation Note12 The contributions from the first nine harmonics are used in the calculation of the THDNote13 Effective Number of Bits(ENOB)is calculated from the measured signal-to-noise plus distortion ratio(SINAD)using the equation ENOB e(SINAD b 1 76) 6 02Note14 The digital power supply current takes up to10seconds to decay to its final value after PD is pulled low This prohibits production testing of the standby current Some parts may exhibit significantly higher standby currents than the20m A typicalNote15 Power Supply Sensitivity is defined as the change in the Offset Error or the Full Scale Error due to a change in the supply voltageTRI-STATE Test Circuit and WaveformsTL H 11490–2TL H 11490–3TL H 11490–4TL H 11490–55Typical Performance CharacteristicsReference VoltageError Change vs Offset and Fullscale vs Reference VoltageLinearity Error Change Input VoltageMux ON Resistance vs vs Temperature Digital Supply Current vs TemperatureAnalog Supply Current on Digital Input PinsStandby Mode vs Voltage Current Consumption in vs Temperature Conversion Time (t CONV )vs TemperatureEOC Delay Time (t EOC )Spectral Response(ADC IN)SINAD vs Input Frequency (ADC IN)SNR vs Input Frequency (ADC IN)THD vs Input Frequency TL H 11490–276Typical Performance Characteristics(Continued)(Through Mux)SINAD vs Input Frequency (Through Mux)SNR vs Input Frequency (Through Mux)THD vs Input Frequency Impedance SNR and THD vs Source Reference VoltageSNR and THD vs TL H 11490–28Timing DiagramsTL H 11490–9FIGURE 1 Interrupt Interface Timing (MODE e 1 OE e 1)7Timing Diagrams (Continued)TL H 11490–10FIGURE 2 High Speed Interface Timing (MODE e 1 OE e 1 CS e 0 RD e 0)TL H 11490–11FIGURE 3 CS Setup and Hold Timing for S H RD and OEConnection DiagramsTL H 11490–13Top ViewTL H 11490–29Top View8Pin DescriptionsAV CC These are the two positive analog supplyinputs They should always be connectedto the same voltage source but arebrought out separately to allow for sepa-rate bypass capacitors Each supply pinshould be bypassed to AGND with a0 1m F ceramic capacitor in parallel with a10m F tantalum capacitorDV CC This is the positive digital supply input Itshould always be connected to the samevoltage as the analog supply AV CC Itshould be bypassed to DGND2with a0 1m F ceramic capacitor in parallel with a10m F tantalum capacitorAGND These are the power supply ground pins DGND1 There are separate analog and digital DGND2ground pins for separate bypassing of theanalog and digital supplies The groundpins should be connected to a stablenoise-free system ground All of theground pins should be returned to thesame potential AGND is the analogground for the converter DGND1is theground pin for the digital control linesDGND2is the ground return for the outputdatabus See Section6 0LAYOUT ANDGROUNDING for more informationDB0–DB11These are the TRI-STATE output pins en-abled by RD CS and OEV IN1 V IN2These are the analog input pins to the mul-tiplexer For accurate conversions no in-put pin(even one that is not selected)should be driven more than50mV belowground or50mV above V CCMUX OUT This is the output of the on-board analoginput multiplexerADC IN This is the direct input to the12-bit sam-pling A D converter For accurate conver-sions this pin should not be driven morethan50mV below AGND or50mV aboveAV CCS0This pin selects the analog input that willbe connected to the ADC12062during theconversion The input is selected based onthe state of S0when EOC makes its high-to-low transition Low selects V IN1 highselects V IN2MODE This pin should be tied to DV CCCS This is the active low Chip Select controlinput When low this pin enables the RDS H and OE inputs This pin can be tiedlowINT This is the active low Interrupt outputWhen using the Interrupt Interface Mode(Figure1) this output goes low when aconversion has been completed and indi-cates that the conversion result is avail-able in the output latches This output isalways high when RD is held low(Figure2)EOC This is the End-of-Conversion control out-put This output is low during a conversion RD This is the active low Read control inputWhen RD is low(and CS is low) the INToutput is reset and(if OE is high)data ap-pears on the data bus This pin can be tiedlowOE This is the active high Output Enable con-trol input This pin can be thought of as aninverted version of the RD input(see Fig-ure6) Data output pins DB0–DB11areTRI-STATE when OE is low Data appearson DB0–DB11only when OE is high andCS and RD are both low This pin can betied highS H This is the Sample Hold control input Theanalog input signal is held and a new con-version is initiated by the falling edge ofthis control input(when CS is low) PD This is the Power Down control input Thispin should be held high for normal opera-tion When this pin is pulled low the devicegoes into a low power standby mode V REF a(FORCE) These are the positive and negative volt-V REF b(FORCE)age reference force inputs respectivelySee Section4 REFERENCE INPUTS formore informationV REF a(SENSE) These are the positive and negative volt-V REF b(SENSE)age reference sense pins respectivelySee Section4 REFERENCE INPUTS formore informationV REF 16This pin should be bypassed to AGND witha0 1m F ceramic capacitorTEST This pin should be tied to DV CC9Functional DescriptionThe ADC12062performs a12-bit analog-to-digital conver-sion using a3step flash technique The first flash deter-mines the six most significant bits the second flash gener-ates four more bits and the final flash resolves the two least significant bits Figure4shows the major functional blocks of the converter It consists of a2 -bit Voltage Estimator a resistor ladder with two different resolution voltage spans a sample hold capacitor a4-bit flash converter with front end multiplexer a digitally corrected DAC and a capacitive volt-age dividerThe resistor string near the center of the block diagram in Figure4generates the6-bit and10-bit reference voltages for the first two conversions Each of the16resistors at the bottom of the string is equal to of the total string resist-ance These resistors form the LSB Ladder and have a voltage drop of of the total reference voltage(V REF a b V REF b)across each of them The remaining resistors form the MSB Ladder It is comprised of eight groups of eight resistors each connected in series(the lowest MSB ladder resistor is actually the entire LSB ladder) Each MSB Ladder section has of the total reference voltage across it Within a given MSB ladder section each of the eight MSB resistors has of the total reference voltage across it Tap points are found between all of the resistors in both the MSB and LSB ladders The Comparator MultipIexer can connect any of these tap points in two adjacent groups of eight to the sixteen comparators shown at the right of Figure4 This function provides the necessary reference voltages to the comparators during the first two flash con-versionsThe six comparators seven-resistor string(Estimator DAC ladder) and Estimator Decoder at the left of Figure4form Note The weight of each resistor on the LSB ladder is actually equivalent to four12-bit LSBs It is called the LSB ladder because it has thehighest resolution of all the ladders in the converter the Voltage Estimator The Estimator DAC connected be-tween V REF a and V REF b generates the reference volt-ages for the six Voltage Estimator comparators The com-parators perform a very low resoIution A D conversion to obtain an‘‘estimate’’of the input voltage This estimate is used to control the placement of the Comparator Multiplex-er connecting the appropriate MSB ladder section to the sixteen flash comparators A total of only22comparators(6 in the Voltage Estimator and16in the flash converter)is required to quantize the input to6bits instead of the64that would be required using a traditional6-bit flashPrior to a conversion the Sample Hold switch is closed allowing the voltage on the S H capacitor to track the input voItage Switch1is in position1 A conversion begins by opening the Sample Hold switch and latching the output of the Voltage Estimator The estimator decoder then selects two adjacent banks of tap points aIong the MSB ladder These sixteen tap points are then connected to the sixteen flash converters For exampIe if the input voltage is be-tween and of V REF(V REF e V REF a b V REF b) the estimator decoder instructs the comparator multiplexer to select the sixteen tap points between and ( and )of V REF and connects them to the sixteen comparators The first flash conversion is now performed producing the first6MSBs of dataAt this point Voltage Estimator errors as large as of V REF will be corrected since the comparators are connect-ed to ladder voltages that extend beyond the range speci-fied by the Voltage Estimator For example if( )V REF k V IN k( )V REF the Voltage Estimator’s comparators tied to the tap points below( )V REF will output‘‘1’’s (000111) This is decoded by the estimator decoder to‘‘10’’ The16comparators will be placed on the MSB ladderTL H 11490–14FIGURE4 Functional Block Diagram10Functional Description(Continued)tap points between( )V REF and( )V REF This overlap of ( )V REF will automatically cancel a Voltage Estimator er-ror of up to256LSBs If the first flash conversion deter-mines that the input voltage is between( )V REF and (( )V REF b LSB 2) the Voltage Estimator’s output code will be corrected by subtracting‘‘1’’ resulting in a corrected value of‘‘01’’for the first two MSBs If the first flash conver-sion determines that the input voltage is between( )V REF b LSB 2)and( )V REF the voltage estimator’s output code is unchangedThe results of the first flash and the Voltage Estimator’s output are given to the factory-programmed on-chip EEPROM which returns a correction code corresponding to the error of the MSB ladder at that tap This code is convert-ed to a voltage by the Correction DAC To generate the next four bits SW1is moved to position2 so the ladder voltage and the correction voltage are subtracted from the input voltage The remainder is applied to the sixteen flash con-verters and compared with the16tap points from the LSB ladderThe result of this second conversion is accurate to10bits and describes the input remainder as a voltage between two tap points(V H and V L)on the LSB ladder To resolve the last two bits the voltage across the ladder resistor(between V H and V L)is divided up into4equal parts by the capacitive voltage divider shown in Figure5 The divider also creates 6LSBs below V L and6LSBs above V H to provide overlap used by the digital error correction SW1is moved to posi-tion3 and the remainder is compared with these16new voltages The output is combined with the results of the Voltage Estimator first flash and second flash to yield the final12-bit resultBy using the same sixteen comparators for all three flash conversions the number of comparators needed by the multi-step converter is significantly reduced when compared to standard multi-step techniquesApplications Information1 0MODES OF OPERATIONThe ADC12062has two interface modes An interrupt read mode and a high speed mode Figures1and2show the timing diagrams for these interfacesIn order to clearly show the relationship between S H CS RD and OE the control logic decoding section of the ADC12062is shown in Figure6Interrupt InterfaceAs shown in Figure1 the falling edge of S H holds the input voltage and initiates a conversion At the end of the conver-sion the EOC output goes high and the INT output goes low indicating that the conversion results are latched and may be read by pulling RD low The falling edge of RD re-sets the INT line Note that CS must be low to enable S H or RDHigh Speed InterfaceThis is the fastest interface shown in Figure2 Here the output data is always present on the databus and the INT to RD delay is eliminatedTL H 11490–15FIGURE5 The Capacitive Voltage Divider11Applications Information (Continued)TL H 11490–16FIGURE 6 ADC Control Logic2 0THE ANALOG INPUTThe analog input of the ADC12062can be modeled as two small resistances in series with the capacitance of the input hold capacitor (C IN ) as shown in Figure 7 The S H switch is closed during the Sample period and open during Hold The source has to charge C IN to the input voltage within the sample period Note that the source impedance of the input voltage (R SOURCE )has a direct effect on the time it takes to charge C IN If R SOURCE is too large the voltage across C IN will not settle to within 0 5LSBs of V SOURCE before the conversion begins and the conversion results will be incor-rect From a dynamic performance viewpoint the combina-tion of R SOURCE R MUX R SW and C IN form a low pass filter Minimizing R SOURCE will increase the frequency re-sponse of the input stage of the converterTypical values for the components shown in Figure 7are R MUX e 100X R SW e 100X and C IN e 25pF The set-tling time to n bits ist SETTLE e (R SOURCE a R MUX a R SW ) C IN n ln (2) The bandwidth of the input circuit isf b 3dB e 1 (2 3 14 (R SOURCE a R MUX a R SW ) C IN )For maximum performance the impedance of the source driving the ADC12062should be made as small as possible A source impedance of 100X or less is recommended A plot of dynamic performance vs source impedance is given in the Typical Performance Characteristics sectionIf the signal source has a high output impedance its output should be buffered with an operational amplifier capable of driving a switched 25pF 100X load Any ringing or instabili-ties at the op amp’s output during the sampling period can result in conversion errors The LM6361high speed op amp is a good choice for this application due to its speed and its ability to drive large capacitive loads Figure 8shows the LM6361driving the ADC IN input of an ADC12062 The 100pF capacitor at the input of the converter absorbs some of the high frequency transients generated by the S H switching reducing the op amp transient response require-ments The 100pF capacitor should only be used with high speed op amps that are unconditionally stable driving ca-pacitive loadsTL H 11490–17FIGURE 7 Simplified ADC12062Input Stage12Applications Information (Continued)TL H 11490–18FIGURE 8 Buffering the Input with an LM6361High Speed Op AmpAnother benefit of using a high speed buffer is improved THD performance when using the multiplexer of the ADC12062 The MUX on-resistance is somewhat non-linear over input voltage causing the RC time constant formed by C IN R MUX and R SW to vary depending on the input voltage This results in increasing THD with increasing frequency Inserting the buffer between the MUX OUT and the ADC IN terminals as shown in Figure 8will eliminate the loading on R MUX significantly reducing the THD of the multiplexed sys-temCorrect converter operation will be obtained for input volt-ages greater than AGND b 50mV and less than AV CC a50mV Avoid driving the signal source more than 300mV higher than AV CC or more than 300mV below AGND If an analog input pin is forced beyond these voltages the cur-rent flowing through that pin should be limited to 25mA or less to avoid permanent damage to the IC The sum of all the overdrive currents into all pins must be less than 50mA When the input signal is expected to extend more than 300mV beyond the power supply limits for any reason (un-known uncontrollable input voltage range power-on tran-sients fault conditions etc )some form of input protection such as that shown in Figure 9 should be usedTL H 11490–19FIGURE 9 Input Protection13Applications Information(Continued)3 0ANALOG MULTIPLEXERThe ADC12062has an input multiplexer that is controlled by the logic level on pin S0when EOC goes low as shown in Figures1and2 Multiplexer setup and hold times with re-spect to the S H input can be determined by these two equationst MS(wrt S H)e t MS b t EOC(min)e50b60e b10ns t MH(wrt S H)e t MH a t EOC(max)e50a125e175ns Note that t MS(wrt S H)is a negative number this indicates that the data on S0must become valid within10ns after S H goes low in order to meet the setup time requirements S0must be valid for a length of(t MH a t EOC(max))b(t MS b t EOC(min))e185ns Table I shows how the input channels are assignedTABLE I ADC12062InputMultiplexer ProgrammingS0Channel0V IN11V IN2The output of the multiplexer is available to the user via the MUX OUT pin This output allows the user to perform addi-tional signal processing such as filtering or gain before the signal is returned to the ADC IN input and digitized If no additional signal processing is required the MUX OUT pin should be tied directly to the ADC IN pinSee Section9 0(APPLICATIONS)for a simple circuit that will alternate between the two inputs while converting at full speed4 0REFERENCE INPUTSIn addition to the fully differential V REF a and V REF b refer-ence inputs used on most National Semiconductor ADCs the ADC12062has two sense outputs for precision control of the ladder voltage These sense inputs compensate for errors due to IR drops between the reference source and the ladder itself The resistance of the reference ladder is typically750X The parasitic resistance(R P)of the package leads bond wires PCB traces etc can easily be0 5X to 1 0X or more This may not be significant at8-bit or10-bit resolutions but at12bits it can introduce voltage drops causing offset and gain errors as large as6LSBsThe ADC12062provides a means to eliminate this error by bringing out two additional pins that sense the exact voltage at the top and bottom of the ladder With the addition of two op amps the voltages on these internal nodes can be forced to the exact value desired as shown in Figure10TL H 11490–20FIGURE10 Reference Ladder Force and Sense Inputs14。

XC6204C30A资料

元器件交易网
XC6204 Series
! CMOS Low Power Consumption ! Dropout Voltage : 60mV @ 30mA, 200mV @ 100mA ! Maximum Output Current : 150mA ! Highly Accurate : ± 2% ! Output Voltage Range : 1.8V ~ 6.0V ! Low ESR capacitor compatible
see table next page 75 0.3 0.01 2 0.20 10 100 30 70 300 50 1.6 VIN 0.25 0.1 0.1
IOUT=30mA IOUT=30mA -40OC≤Topr≤85OC 300Hz~50kHz IOUT=50mA, f=10kHz
VCE=VIN VCE=VSS
%
M D
"'#
18~60
30 = 3.0V etc.
&
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Please note that the "B" version is the standard part. The A, C, & D versions are semi-custom parts.
1
元器件交易网
PARAMETER Output Voltage Maximum Output Current Load Regulation Dropout Voltage Supply Current Standby Current Line Regulation Input Voltage Output Voltage Temp. Characteristics Output Noise Ripple Rejection Rate Current Limiter Short-circuit Current CE "High" Voltage CE "Low" Voltage CE "High" Current CE "Low" Current

FAN6204同步整流芯片应用

385 µ H 60 T
8 T 55 kHz 41 T 6 T 6.8 700 µH 52 kHz
输出
输出电压 (Vo) 输出功率 (Po)
NBOOST 60T D5
100kΩ RHV
41T RCLAMP CCLAMP 51kΩ NP
6T NS
680uF 470uF 470uF 470uF V =19V 25V 25V 25V 25V OUT + 16Ω RSN 36kΩ RRES1 9.1kΩ RRES2 COUT1 COUT2 COUT3 COUT4
V R2 ( IN .MAX VOUT ) 4 R1 R2 n R4 1 VOUT 4 R3 R4
(2) (3)
R4 VOUT 4 R3 R4
的取值为 5~5.5。
再考虑到分压电阻和内部电路的公差，分压比 (K)
K
R2 R4 R1 R2 R3 R4
0.83 V R2 IN .MIN 0.05VOUT 0.3 R1 R2 n
(5)
应该考虑 LPC 和 RES (1~4 V) 的线性工作范围，则：
V R2 IN .MAX 4 R1 R2 n
(6) (7)
另一方面，需要考虑 LPC 和 RES (1~4 V) 的线性工作范围，则：
表 ‎
2中总结了关键参数。
关键系统参数
表 2.
PFC电路
PFC 输出电压电平 1 (PFCVo1) PFC 输出电压电平 2 (PFCVo2) 250 V 400 V
输入
输入电压范围电源频率范围 90~264 VAC 47~63 Hz
PFC 电感 (Lb) PFC 电感匝数 (Nb)

TPS60204资料

Figure 10t – Time – µs12345678910Figure 1150100150200250300350400450500V OENI It – Time – µsV I = 2.4 VFigure 12LOAD TRANSIENT RESPONSE100 mA10 mA501001502002503003.263.283.303504004505003.24t – Time – µsV I = 2.4 V012345678910t – Time – msFigure 13元器件交易网IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,enhancements, improvements, and other changes to its products and services at any time and to discontinueany product or service without notice. Customers should obtain the latest relevant information before placingorders and should verify that such information is current and complete. All products are sold subject to TI’s termsand conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale inaccordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TIdeems necessary to support this warranty. Except where mandated by government requirements, testing of allparameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design. Customers are responsible fortheir products and applications using TI components. To minimize the risks associated with customer productsand applications, customers should provide adequate design and operating safeguards.TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or processin which TI products or services are used. Information published by TI regarding third–party products or servicesdoes not constitute a license from TI to use such products or services or a warranty or endorsement thereof.Use of such information may require a license from a third party under the patents or other intellectual propertyof the third party, or a license from TI under the patents or other intellectual property of TI.Reproduction of information in TI data books or data sheets is permissible only if reproduction is withoutalteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproductionof this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable forsuch altered documentation.Resale of TI products or services with statements different from or beyond the parameters stated by TI for thatproduct or service voids all express and any implied warranties for the associated TI product or service andis an unfair and deceptive business practice. TI is not responsible or liable for any such statements.Mailing Address:Texas InstrumentsPost Office Box 655303Dallas, Texas 75265Copyright 2001, Texas Instruments Incorporated。

MBI6024 Preliminary Datasheet V2.00-EN

6F-4, No.18, Pu-Ting Rd., Hsinchu, Taiwan 30072, R.O.C.Sink Driver for LED StripsFeaturesz 3x4-channel constant-current sink driver for LED strips z Constant current range: 3~45mAz 3 groups of output current, each group is set by an external resistor z Sustaining voltage at output channels: 17V (max.) z Supply voltage 3V~5.5VzEmbedded 16-bit PWM generator- Gray scale clock generated by the embedded oscillator - S-PWM patented technologyz Two selectable modes to trade off between image quality and transmission bandwidth- 16-bit gray scale mode (with optional 8-bit dot correction) - 10-bit gray scale mode (with optional 6-bit dot correction)z Reliable data transmission- Daisy-chain topology- Two-wire transmission interface - Phase-inversed output clock- Built-in buffer for long distance transmission zFlexible PWM reset modes - Auto-synchronization mode - Manual-synchronization mode z RoHS-compliant packagesApplicationz LED strips z Mesh display z Architectural lightingProduct DescriptionMBI6024 is a 3x4-channel, constant-current, PWM-embedded sink driver for LED strips. MBI6024 provides constant current ranging from 3mA to 45mA for each output channel and are adjustable with three corresponding external resistors. Besides, MBI6024 can support both 3.3V and 5V power systems and sustain 17V at output channels.With Scrambled-PWM (S-PWM) technology, MBI6024 enhances pulse width modulation by scrambling the “on” time into several “on” periods to increase visual refresh rate at the same gray scale performance. Besides, the gray scale clock (GCLK) is generated by the embedded oscillator. Moreover, MBI6024 provides two selectable gray scale modes to trade off between image quality and transmission: 16-bit gray scale mode and 10-bit gray scale mode. The 16-bit gray scale mode provides 65,536 gray scales for each LED to enrich the color. Subject to the 16-bit gray scale mode, the 8-bit dot correction may adjust each LED by 256-step gain to compensate the LED brightness. Furthermore, the 10-bit gray scale mode provides 1,024 gray scales. Subject to the 10-bit gray scale mode, 6-bit dot correction may adjust each LED by 64-step gain.In addition, MBI6024 features a two-wire transmission interface to make cluster-to-cluster connection easier. To improve the transmission quality, MBI6024 provides phase-inversed output clock to eliminate the accumulation of signal pulse width distortion. MBI6024 is also flexible for either manual-synchronization or auto-synchronization. The manual-synchronization is to maintain the synchronization of image frames between ICs. The auto-synchronization is to achieve accurate gray scale, especially when using the built-in oscillator.2413V R-EXTA R-EXTCOUTAn OUTBnMBI6024PWM-Embedded 3x4-Channel Constant-Current Sink Driver for LED StripsSymbo l tSU tHD tPHL1 tPHL2 tPHL3 tPHL4 tPHL5 tPHL6 tPLH3 tPLH4 tPLH5 tPLH6 tw(I) tWDM tOR tOR1 tOF tOF1 FCKI FOSC VLED=4V VDS=1.0V VIH=VDD VIL=GND IOUT=20mA RL=150Ω CL=10pF C1=4.7uF C2=0.1uF C3=4.7uF CCKO=8pF CSDO=8pFSwitching Characteristics (VDD=3.3V, Ta=25°C)Characteristics Setup Time Hold Time SDI–CKI↓ CKI↓–SDI CKI↑–CKO↓ CKI↓–SDO↑↓ GCLK↑– OUTB0 , OUTA1 , Propagatio n Delay Time (“H” to “L”)OUTB2 ↓ConditionMin. 7.5 7.5 32 40 48 56 32 40 48 56 20 38 3.0 12.0 3.0 30.0 0.2 -Typ. 50 38 40 48 56 64 40 48 56 64 6.0 18.0 6.0 35.0 24.0Max. 48 56 64 72 48 56 64 72 9.0 24.0 9.0 40.0 10 -Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHzGCLK↑– OUTC1 , OUTA3 ,OUTC3↓ ↓GCLK↑– OUTA0 , OUTC0 ,OUTA2GCLK↑– OUTB1 , OUTC2 , OUTB3 ↓ GCLK↑– OUTB0 , OUTA1 ,OUTB2 ↑Propagatio n Delay Time (“L” to “H”)GCLK↑– OUTC1 , OUTA3 ,OUTC3↑ ↑GCLK↑– OUTA0 , OUTC0 ,OUTA2GCLK↑– OUTB1 , OUTC2 , OUTB3 ↑ Pulse Width Minimum Pulse Width of PWM Rise Time CKI*OUTAn ~ OUTCnCKO/SDOOUTAn ~ OUTCnFall TimeCKO/SDOOUTAn ~ OUTCnCKI* Frequency Internal Oscillator*The maximum frequency may be limited by different application conditions. Please refer to the application note for details.- 11 -October 2011, V2.00MBI6024PWM-Embedded 3x4-Channel Constant-Current Sink Driver for LED StripsTest Circuit for Electrical / Switching Characteristics- 12 -October 2011, V2.00MBI6024Timing WaveformPWM-Embedded 3x4-Channel Constant-Current Sink Driver for LED StripsSignal Input and Output with Phase-inversed Output ClockOutput Timing- 13 -October 2011, V2.00MBI6024PWM-Embedded 3x4-Channel Constant-Current Sink Driver for LED StripsPrinciple of OperationMBI6024 provides SPI-like interface (CKI, SDI), a two-wire transmission interface, to address the data, so that MBI6024 receives the data directly without a latch command. The sequence of operation should follow the steps below: Step 1. Set the configuration register Step 2. Send the dot correction data Step 3. Send the gray scale data MBI6024 receives the data packet containing targeted gray scale (GS) data from the controller, and turns on the output channels according to the gray scale data. The gray scale clock of PWM generator, GCLK, is generated by the embedded oscillator.Control Interface: SPI-Like Interface (CKI, SDI)MBI6024 adopts the SPI-like interface (CKI/SDI). By SPI-like interface, MBI6024 samples the data (SDI) at the falling edge of the clock (CKI).The following waveforms is the example of the SPI-like interface.Phase-inversed Output Clock MBI6024 enhances the capability of cascading MBI6024 by phase-inversed output clock function. By phase-inversed output clock, the clock phase will be inversed from CKI to CKO to eliminate the accumulation of the pulse width deviation. This improves the signal integrity of data transmission. The following chart illustrates the phase-inversed output clock results.Original: CKI1 Original: CKO1 Phase-Inverse Clock I:CKO2 Phase-Inverse Clock II: CKO3- 14 -October 2011, V2.00MBI6024PWM-Embedded 3x4-Channel Constant-Current Sink Driver for LED StripsThe Structure of Data PacketMBI6024’s data packet contains three parts: 1. Prefix: The prefix is a symbol of “Silent-to-Reset”, i.e. a time period for MBI6024 to distinguish two data packets. During the prefix, both CKI and SDI should be tied-low and stop for more than 172 CKI cycles. 2. Header: The header defines the cascaded IC numbers and also contains a command to decide the data type. 3. Data: This is the data for each IC. It may be gray scale data, dot correction data, or configuration data. Structure of a data packet:PrefixHeaderData- 15 -October 2011, V2.00MBI6024PWM-Embedded 3x4-Channel Constant-Current Sink Driver for LED StripsSetting the Data Types by the CommandMBI6024 provides six kinds of commands and input data types shown as the table below: Command H[5:0] 6’b11 1111 6’b10 1011 6’b11 0011 6’b10 0111 6’b10 0011 6’b11 0111 Data Type 16-bit gray scale data 10-bit gray scale data 8-bit dot correction data 6-bit dot correction data 16-bit configuration data 10-bit configuration dataOnce MBI6024 receives the SDI=1 (1’b1), MBI6024 will start to check if the data is a valid command or not. If the 6-bit data is a valid command, the driver will latch the specific data according to the protocol. If the 6-bit data is not a valid command, MBI6024 will wait for another SDI=1 (1’b1) to check the validity of the next command. Time-Out Reset for Transmission Abort Time-out reset is to prevent ICs from misreading during the data transmission. If the CKI is tied-low for more than 95 CKI cycles, MBI6024 may identify the wires as disconnection. To prevent from misreading, MBI6024 will ignore the present input data and continuously show the previous image data until the next image data is correctly recognized. The Prefix in the Beginning of a Data Packet MBI6024 identifies the data as a new data packet after time-out, so the prefix in the beginning of a data packet should be more than 172 CKI cycles. If both CKI and SDI are tied-low and stop for more than the setting of CKI time-out period, MBI6024 will start to check the valid command of the next data packet. The prefix between two data packets helps MBI6024 identify the data packet correctly. The following timing diagram illustrates the interval between two data packets in 16-bit gray scale mode.The prefix > 172 CKI cycles- 16 -October 2011, V2.00MBI6024PWM-Embedded 3x4-Channel Constant-Current Sink Driver for LED StripsDefinition of Configuration RegisterMBI6024 provides two configuration register sections: configuration register 1 (CF1) and configuration register 2 (CF2) as defined in the tables below.Configuration Register 1 (CF1):MSB Bit Default Value 9 10 8 7 0 6 11 5 4 1 3 1 2 11 1 LSB 0 0Note: Bit [15:10] should be set as “0” to avoid signal misjudgment. Bit Definition Value 11 9:8 GCLK frequency 10 (default) 01 00 7 6:5 4 Dot correction mode Reserved PWM counter reset PWM data synchronization Phase-inversed output clock Parity check 0 (default) 1 11 (default) 1 (default) 0 1 (default) 0 11 (default) 1 0 (default) Function GCLK=frequency of internal oscillator, i.e. 24MHz (typical). GCLK=oscillator frequency divided by two, i.e. 12MHz (typical). GCLK=oscillator frequency divided by four, i.e. 6MHz (typical). GCLK= oscillator frequency divided by eight, i.e. 3MHz (typical). enable dot correction, bypass dot correction Must fill in ‘11’ Reset PWM counter after programming configuration register Do not reset PWM counter after programming configuration register Automatic synchronization Manual synchronization The waveform is inversed from CKI to CKO; please set the two bits as 2b’11. Other combinations are reserved for internal tests. Enable Disable32:10- 17 -October 2011, V2.00MBI6024GCLK FrequencyPWM-Embedded 3x4-Channel Constant-Current Sink Driver for LED StripsMBI6024 provides four kinds of internal GCLK frequency, which is the internal oscillator frequency divided by 1, 2, 4, and 8, for different applications according to the bits of CF1[9:8]. The internal oscillator frequency is 24MHz (typ.); e.g. if the internal oscillator frequency is divided by 8, the GCLK frequency is 3MHz. Higher GCLK frequency provides higher visual refresh rate, but also higher EMI. If the output current is larger than 40mA, the GCLK frequency is suggested to be lower than 8MHz to keep good linearity at low gray scale level. Dot Correction Mode MBI6024 also provides 8-bit or 6-bit dot correction in 16-bit or 10-bit gray scale mode respectively. Dot correction control helps compensate LED brightness and reduces the loading of calculation in controllers. In addition, with the built-in multiplier, MBI6024 operates dot correction without sacrificing the visual refresh rate. PWM Counter Reset MBI6024 can optionally reset the PWM counter by setting the bit of CF1[4] after programming configuration register. The default setting is to reset the PWM counter to start a new PWM cycle to align the PWM output data for new setting. PWM Data Synchronization MBI6024 is also flexible for either manual-synchronization or auto-synchronization by setting the bit of CF1[3]. For auto-synchronization, the bit of CF1[3] is set to “1” (default). MBI6024 will automatically process the synchronization of previous data and next data for PWM counting. The next image data will be updated to output buffers and start PWM counting when the previous data finishes one internal PWM cycle. For manual-synchronization, the bit of CF1[3] is set to “0”. Once the next input data is correctly recognized, MBI6024 will stop the present PWM cycle and restart a new PWM cycle to show the new data immediately. The advantage of manual-synchronization is to maintain the synchronization of image frames between ICs, but the PWM cycle may not be finished, so the gray scale accuracy is slightly affected. Since S-PWM scrambles the 16-bit PWM cycle into 64 small periods, the gray scale accuracy remains good. For better gray scale performance, auto-synchronization keeps accurate gray scale especially when using the built-in oscillator, but the drawback is the synchronization of image frames between ICs. Parity Check Parity check is to check the data in the header for any error, especially to prevent the configuration register and dot correction register from miswriting.- 18 -October 2011, V2.00MBI6024PWM-Embedded 3x4-Channel Constant-Current Sink Driver for LED StripsConfiguration Register 2 (CF2):Default Value MSB Bit Value 2 1 111 LSB 0Note: Bit [15:3] should be set as “0” to avoid signal misjudgment. Bit 2 1:0 Definition Reserved Reserved Value 1 (default) 11 (default) Function Must fill in ‘1’ Must fill in ‘11’16-bit Configuration DataFor 16-bit configuration data, each word is 16 bits. Each MBI6024 needs 3 words (3x16=48 bits) for the configuration data. However, each configuration data has only 10 bits, and the MSB 6 bits of each word are invalid. Prior to the configuration data, there is a 48-bit header. MBI6024 provides parity check function to check the count of bit to prevent the data transmission error. The data format is shown below:Prefix Both CKI and SDI should be tied-low and stop for more than 172 CKI cycles. 48-bits header Bit Definition 47:42 H[5:0] 41:32 A[9:0] 31:26 25:16 H[5:0] L[9:0]Value 100011 0000000000 100011 N-1 N=Number of IC in seriesFunction The command of 16-bit configuration data Address data. Always send 10’b 0000000000 Double check the command. It should be the same as the prior H[5:0], otherwise the data packet will be ignored. Set the number of IC in series P[3:0] are parity check bits, If it is incorrect, the data packet will be ignored. P[0] is the parity check bit of L[9:0] P[0]=1 if the count of “1” within L[9:0] is odd; P[0]=0 if the count of “1” within L[9:0] is even.15:12P[3:0]0000~1111P[1] is the parity check bit of A[9:0] P[1]=1 if the count of “1” within A[9:0] is odd; P[1]=0 if the count of “1” within A[9:0] is even. P[2] is the parity check bit of H[5:0] P[2]=1 if the count of “1” within H[5:0] is odd; P[2]=0 if the count of “1” within H[5:0] is even. - 19 October 2011, V2.00MBI6024PWM-Embedded 3x4-Channel Constant-Current Sink Driver for LED StripsP[3] is the parity check bit of P[2:0] P[3]=1 if the count of “1” within P[2:0] is odd; P[3]=0 if the count of “1” within P[2:0] is even.11:10 9:0X1[1:0] L[9:0]XX N-1 N=Number of IC in seriesDon’t care. The value is suggested to be “0”. Double check the number of IC in series48-bit configuration data Bit Definition Value Function X2[5:0] are “don’t care” bits. The value is suggested to be “0”. CF1N[9:0] are 10 bits data of configuration register 1 (CF1). The 2nd 47:0 X2[5:0]~CF1N[9:0]~ X2[5:0]~CF1N[9:0]~ X3[12:0]~CF2N[2:0] CF1[9:0] double checks the data of configuration register bank 1 48b’0~48b’1 (CF1). It should be the same as the 1st CF1N[9:0]; otherwise the data will not be written into register. X3[12:0] are “don’t care” bits. The value is suggested to be “0”. CF2N[2:0] are 3 bits data of configuration register 2 (CF2) The configuration data of the last IC is sent first, followed by the previous ICs, and the first IC’s configuration data is sent in the end of the packet.- 20 -October 2011, V2.00PrefixBoth CKI and SDI should be tied-low and stop for more than 172 CKI cycles.30-bit headerBit Definition Value FunctionThe command of 10-bit configuration dataBoth CKI and SDI should be tied-low and stop for more than 172 CKI cycles. 48-bit headerBit DefinitionBoth CKI and SDI should be tied-low and stop for more than 172 CKI cycles. Bit DefinitionAccording to the above equation, the following table shows the examples:The ratio of output turn-on time1/256 x gray scale data2/256 x gray scale dataAccording to the above equation, the following table shows the examples:The ratio of output turn-on time1/64 x gray scale data2/64 x gray scale dataBoth CKI and SDI should be tied-low and stop for more than 172 CKI cycles. Bit DefinitionBoth CKI and SDI should be tied-low and stop for more than 172 CKI cycles. 30-bits headerBit DefinitionMBI6024GP Outline DrawingMBI6024GFN Outline Drawing (Max) (Max)Note 1: The unit for the outline drawing is mm.DisclaimerMacroblock reserves the right to make changes, corrections, modifications, and improvements to their products and documents or discontinue any product or service. Customers are advised to consult their sales representative for the latest product information before ordering. All products are sold subject to the terms and conditions supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. Macroblock’s products are not designed to be used as components in device intended to support or sustain life or in military applications. Use of Macroblock’s products in components intended for surgical implant into the body, or other applications in which failure of Macroblock’s products could create a situation where personal death or injury may occur, is not authorized without the express written approval of the Managing Director of Macroblock. Macroblock will not be held liable for any damages or claims resulting from the use of its products in medical and military applications.Related technologies applied to the product are protected by patents. All text, images, logos and information contained on this document is the intellectual property of Macroblock. Unauthorized reproduction, duplication, extraction, use or disclosure of the above mentioned intellectual property will be deemed as infringement.。

F24-60软件使用说明书

後再執行讀取動作。.
1.將 F24-60 軟體燒錄線接到發射或接收機。 2.按下“讀取設定”。 3.完成後按下“確定” 鍵即可。
3
燒錄新設定至遙控器 *使用軟體讀取/燒錄發射機或接收機時，請確實關閉電源或取出電池後再執行讀取動作。
1.將 F24-60 軟體燒錄線接到發射或接收機。 2.按下”燒錄設定” 。 3.完成後按下”確定”鍵即可。
關閉/離開 F24-60 程式如需關閉程式，按下離開鍵即可。
子有
电
鼎
禹
海
上
4
I. 繼電器數量
選擇發射機上各動作如按鍵﹐選擇開關及搖桿使用之繼電器數量
(1) 選擇 RS232/USB 所在使用中的 COM (2) 按下“讀取設定”(需等待數秒鐘) (3) 讀取完畢後，選擇需更改的動作之繼電器數量(選取 0 當不選用該動作) (4) 選擇完畢後，按“下一頁”
功能需在發射器為「持續發射」模式才有效，「不持續發射」時放開按
有鍵即不耗電，故不需設定。
發射機停用關機 LED 燈亮燈/關燈
有效/無效﹕當選擇有效時是指發射機有一段時間未操作而進入停用
子省電前，會發射急停信號使接收機進入關機狀態。
是指正常操作中發射機指示燈是否亮起當選擇 LED 燈“關燈”時，操作
司出
(2) 更改完畢後按“下一頁”
公 (3) 重複以上程序直到 4 個軸向設定完畢限注意 (a) 如設定中有需回上一頁做更改，任何時間可以按“上一頁” 回到所需更改的
有頁面。
(b) 參考附件 I 關於加速延遲，抑制延遲及吋動功能設定解釋。
子 (c) 根據第一頁裡(繼電器數量)裡所設定每一個軸向繼電器數量，其可用之繼電器將會顯电鼎禹海

National LMC6024 数据手册

LMC6024Low Power CMOS Quad Operational AmplifierGeneral DescriptionThe LMC6024is a CMOS quad operational amplifier which can operate from either a single supply or dual supplies.Its performance features include an input common-mode range that reaches V −,low input bias current and voltage gain (into 100k Ωand 5k Ωloads)that is equal to or better than widely accepted bipolar equivalents,while the power supply re-quirement is less than 1mW.This chip is built with National’s advanced Double-Poly Silicon-Gate CMOS process.See the LMC6022datasheet for a CMOS dual operational amplifier with these same features.Featuresn Specified for 100k Ωand 5k Ωloads n High voltage gain 120dBn Low offset voltage drift 2.5µV/˚Cn Ultra low input bias current 40fAn Input common-mode range includes V −n Operating range from +5V to +15V supply n Low distortion 0.01%at 1kHz n Slew rate 0.11V/µsnMicropower operation 1mWApplicationsn High-impedance buffer or preamplifier n Current-to-voltage converter n Long-term integrator n Sample-and-hold circuit n Peak detectorn Medical instrumentation nIndustrial controlsConnection DiagramOrdering InformationTemperature RangePackageNSC Drawing Transport Media Industrial −40˚C ≤T J ≤+85˚CLMC6024IN 14-Pin N14ARailMolded DIP LMC6024IM14-Pin M14ARail Small OutlineTape and Reel14-Pin DIP/SODS011235-1Top ViewNovember 1994LMC6024Low Power CMOS Quad Operational Amplifier©1999National Semiconductor Corporation 查询LMC6024供应商Absolute Maximum Ratings(Note1)If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Differential Input Voltage±Supply Voltage Supply Voltage(V+−V−)16V Lead Temperature(Soldering,10sec.)260˚C Storage Temperature Range−65˚C to+150˚C Voltage at Output/Input Pin(V+)+0.3V,(V−)−0.3V Current at Input Pin±5mA Current at Output Pin±18mA Current at Power Supply Pin35mA Output Short Circuit to V+(Note12)Output Short Circuit to V−(Note2) Junction Temperature150˚C ESD Tolerance(Note4)1000V Power Dissipation(Note3)Operating RatingsTemperature Range−40˚C≤T J≤+85˚C Supply Voltage Range 4.75V to15.5V Power Dissipation(Note10) Thermal Resistance(θJA),(Note11)14-Pin DIP85˚C/W 14-Pin SO115˚C/WDC Electrical CharacteristicsThe following specifications apply for V+=5V,V−=0V,V CM=1.5V,V O=2.5V,and R L=1M unless otherwise noted.Bold-face limits apply at the temperature extremes;all other limits T J=25˚C.Typical LMC6024I Symbol Parameter Conditions(Note5)Limit Units(Note6)V OS Input Offset Voltage19mV11Max ∆V OS/∆T Input Offset Voltage 2.5µV/˚C Average DriftI B Input Bias Current0.04pA200Max I OS Input Offset Current0.01pA100Max R IN Input Resistance>1TeraΩCMRR Common Mode0V≤V CM≤12V8363dB Rejection Ratio V+=15V61Min +PSRR Positive Power Supply5V≤V+≤15V8363dB Rejection Ratio61Min −PSRR Negative Power Supply0V≤V−≤−10V9474dB Rejection Ratio73Min V CM Input Common-Mode V+=5V and15V−0.4−0.1V Voltage Range For CMRR≥50DB0MaxV+−1.9V+−2.3VV+−2.5Min A V Large Signal Voltage Gain R L=100kΩ(Note7)1000200V/mVSourcing100MinSinking50090V/mV40MinR L=5kΩ(Note7)1000100V/mVSourcing75MinSinking25050V/mV20Min 2DC Electrical Characteristics(Continued)The following specifications apply for V+=5V,V−=0V,V CM=1.5V,V O=2.5V,and R L=1M unless otherwise noted.Bold-face limits apply at the temperature extremes;all other limits T J=25˚C.Typical LMC6024ISymbol Parameter Conditions(Note5)Limit Units(Note6)V O Output Voltage Swing V+=5V 4.987 4.40VR L=100kΩto2.5V 4.43Min0.0040.06V0.09MaxV+=5V 4.940 4.20VR L=5kΩto2.5V 4.00Min0.0400.25V0.35MaxV+=15V14.97014.00VR L=100kΩto7.5V13.90Min0.0070.06V0.09MaxV+=15V14.84013.70VR L=5kΩto7.5V13.50Min0.1100.32V0.40MaxI O Output Current V+=5V2213mASourcing,V O=0V9MinSinking V O=5V2113mA(Note2)9MinV+=15V4023mASourcing,V O=0V15MinSinking,V O=13V3923mA(Note12)15MinI S Supply Current All Four Amplifiers160240µAV O=1.5V280Max3AC Electrical CharacteristicsThe following specifications apply for V+=5V,V−=0V,V CM=1.5V,V O=2.5V,and R L=1M unless otherwise noted.Bold-face limits apply at the temperature extremes;all other limits T J=25˚C.Typical LMC6024ISymbol Parameter Conditions(Note5)Limit Units(Note6)SR Slew Rate(Note8)0.110.05V/µs0.03Min GBW Gain-Bandwidth Product0.35MHzθM Phase Margin50DegG M Gain Margin17dBAmp-to-Amp Isolation(Note9)130dBeInput-Referred Voltage Noise F=1kHz42Typical Performance CharacteristicsV S =±7.5V,T A =25˚C unless otherwise specifiedSupply Current vs Supply VoltageDS011235-27Input Bias Current vs TemperatureDS011235-28Common-Mode Voltage Range vs TemperatureDS011235-29Output Characteristics Current Sinking DS011235-30Output Characteristics Current Sourcing DS011235-31Input Voltage Noise vs FrequencyDS011235-32Crosstalk Rejection vs FrequencyDS011235-33CMRR vs Frequency DS011235-34CMRR vs TemperatureDS011235-355Typical Performance CharacteristicsV S =±7.5V,T A =25˚C unless otherwise specified (Continued)Power Supply Rejection Ratio vs FrequencyDS011235-36Open-Loop Voltage Gain vs TemperatureDS011235-37Open-LoopFrequency ResponseDS011235-38Gain and Phase Responses vs Load Capacitance DS011235-39Gain and PhaseResponses vs TemperatureDS011235-40Gain Error (V OS vs V OUT )DS011235-41Non-Inverting Slew Rate vs Temperature DS011235-42Inverting Slew Rate vs TemperatureDS011235-43Large-Signal PulseNon-Inverting Response (A V =+1)DS011235-44 6Typical Performance CharacteristicsV S =±7.5V,T A =25˚C unless otherwise specified (Continued)Application HintsAMPLIFIER TOPOLOGYThe topology chosen for the LMC6024is unconventional (compared to general-purpose op amps)in that the tradi-tional unity-gain buffer output stage is not used;instead,the output is taken directly from the output of the integrator,to al-low rail-to-rail output swing.Since the buffer traditionally de-livers the power to the load,while maintaining high op amp gain and stability,and must withstand shorts to either rail,these tasks now fall to the integrator.As a result of these demands,the integrator is a compound affair with an embedded gain stage that is doubly fed forward (via C f and C ff )by a dedicated unity-gain compensation driver.In addition,the output portion of the integrator is a push-pull configuration for delivering heavy loads.While sinking current the whole amplifier path consists of three gain stages with one stage fed forward,whereas while sourcing the path contains four gain stages with two fed forward.The large signal voltage gain while sourcing is comparable to traditional bipolar op amps,for load resistance of at least 5k Ω.The gain while sinking is higher than most CMOS op amps,due to the additional gain stage;however,when driv-Non-Inverting Small Signal Pulse Response (A V =+1)DS011235-45Inverting Large-Signal Pulse Response DS011235-46Inverting Small-Signal Pulse ResponseDS011235-47Stability vs Capacitive Load DS011235-4Note 13:Avoid resistive loads of less than 500Ω,as they may cause instability.Stability vs Capacitive LoadDS011235-5DS011235-6FIGURE 1.LMC6024Circuit Topology (Each Amplifier)7Application Hints(Continued)ing load resistance of 5k Ωor less,the gain will be reduced as indicated in the Electrical Characterisitics.The op amp can drive load resistance as low as 500Ωwithout PENSATING INPUT CAPACITANCERefer to the LMC660or LMC662datasheets to determine whether or not a feedback capacitor will be necessary for compensation and what the value of that capacitor would be.CAPACITIVE LOAD TOLERANCELike many other op amps,the LMC6024may oscillate when its applied load appears capacitive.The threshold of oscilla-tion varies both with load and circuit gain.The configuration most sensitive to oscillation is a unity-gain follower.See the Typical Performance Characteristics.The load capacitance interacts with the op amp’s output re-sistance to create an additional pole.If this pole frequency is sufficiently low,it will degrade the op amp’s phase margin so that the amplifier is no longer stable at low gains.The addi-tion of a small resistor (50Ωto 100Ω)in series with the op amp’s output,and a capacitor (5pF to 10pF)from inverting input to output pins,returns the phase margin to a safe value without interfering with lower-frequency circuit operation.Thus,larger values of capacitance can be tolerated without oscillation.Note that in all cases,the output will ring heavily when the load capcitance is near the threshold for oscillation.Capacitive load driving capability is enhanced by using a pull up resistor to V +Figure 3.Typically a pull up resistor con-ducting 50µA or more will significantly improve capacitive load responses.The value of the pull up resistor must be de-termined based on the current sinking capability of the ampli-fier with respect to the desired output swing.Open loop gain of the amplifier can also be affected by the pull up resistor (see Electrical Characteristics).PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORKIt is generally recognized that any circuit which must operate with less than 1000pA of leakage current requires special layout of the PC board.When one wishes to take advantage of the ultra-low bias current of the LMC6024,typically less than 0.04pA,it is essential to have an excellent layout.For-tunately,the techniques for obtaining low leakages are quite simple.First,the user must not ignore the surface leakage of the PC board,even though it may sometimes appear accept-ably low,because under conditions of high humidity or dust or contamination,the surface leakage will be appreciable.To minimize the effect of any surface leakage,lay out a ring of foil completely surrounding the LMC6024’s inputs and the terminals of capacitors,diodes,conductors,resistors,relay terminals,etc.connected to the op-amp’s inputs.See Figure 4.To have a significant effect,guard rings should be placed on both the top and bottom of the PC board.This PC foil must then be connected to a voltage which is at the same voltage as the amplifier inputs,since no leakage current can flow between two points at the same potential.For example,a PC board trace-to-pad resistance of 1012ohms,which is normally considered a very large resistance,could leak 5pA if the trace were a 5V bus adjacent to the pad of an input.This would cause a 100times degradation from the LMC6024’s actual performance.However,if a guard ring is held within 5mV of the inputs,then even a resistance of 1011ohms would cause only 0.05pA of leakage current,or per-haps a minor (2:1)degradation of the amplifier’s perfor-mance.See Figure 5a ,Figure 5b ,Figure 5c for typical con-nections of guard rings for standard op-amp configurations.If both inputs are active and at high impedance,the guard can be tied to ground and still provide some protection;see Figure 5d .DS011235-7FIGURE 2.Rx,Cx Improve Capacitive Load Tolerance DS011235-26FIGURE pensating for Large Capacitive Loads with a Pull Up Resistor 8Application Hints(Continued)The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few circuits,there is another technique which is even better than a guard ring on a PC board:Don’t insert the amplifier’s input pin into the board at all,but bend it up in the air and use only air as an in-sulator.Air is an excellent insulator.In this case you may have to forego some of the advantages of PC board con-struction,but the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring.See Figure 6.DS011235-8FIGURE 4.Example of Guard Ring in P .C.Board Layout (Using the LMC6024)DS011235-9(a)Inverting AmplifierDS011235-10(b)Non-Inverting AmplifierDS011235-11(c)FollowerDS011235-12(d)Howland Current PumpFIGURE 5.Guard Ring Connections9Application Hints(Continued)BIAS CURRENT TESTINGThe test method of Figure 7is appropriate for bench-testing bias current with reasonable accuracy.To understand its op-eration,first close switch S2momentarily.When S2is opened,thenA suitable capacitor for C2would be a 5pF or 10pF silver mica,NPO ceramic,or air-dielectric.When determining the magnitude of I −,the leakage of the capacitor and socket must be taken into account.Switch S2should be left shorted most of the time,or else the dielectric absorption of the ca-pacitor C2could cause errors.Similarly,if S1is shorted momentarily (while leaving S2shorted)where C x is the stray capacitance at the +input.Typical Single-Supply Applications(V +=5.0V DC )DS011235-13(Input pins are lifted out of PC board and soldered directly to components.All other pins connected to PC board.)FIGURE 6.Air WiringDS011235-14FIGURE 7.Simple Input Bias Current Test Circuit Photodiode Current-to-Voltage ConverterDS011235-15Note 14:A 5V bias on the photodiode can cut its capacitance by a factor of 2or 3,leading to improved response and lower noise.However,this bias on the photodiode will cause photodiode leakage (also known as its dark cur-rent).Micropower Current SourceDS011235-16(Upper limit of output range dictated by input common-mode range;lower limit dictated by minimum current requirement of LM385.) 10Typical Single-Supply Applications(V +=5.0V DC )(Continued)Low-Leakage Sample-and-HoldDS011235-17Instrumentation AmplifierDS011235-18If R1=R5,R3=R6,and R4=R7;Then∴A V ≈100for circuit shown.For good CMRR over temperature,low drift resistors should be used.Matching of R3to R6and R4to R7affects CMRR.Gain may be adjusted through R2.CMRR may be adjusted through R7.10Hz Bandpass Filter DS011235-19f O =10Hz Q =2.1Gain =−8.810Hz High-Pass Filter (2dB Dip)DS011235-20f c =10Hz d =0.895Gain =111Typical Single-Supply Applications(V +=5.0V DC )(Continued)1Hz Low-Pass Filter (Maximally Flat,Dual SupplyOnly)DS011235-21High Gain Amplifier with Offset Voltage ReductionDS011235-22Gain =−46.8Output offset voltage reduced to the level of the input offset voltage of the bottom amplifier (typically 1mV),referred to V BIAS . 12Physical Dimensions inches(millimeters)unless otherwise noted14-Pin Small Outline Molded Package(M)Order Number LMC6024IMNS Package Number M14A14-Pin Molded Dual-In-Line Package(N)Order Number LMC6024INNS Package Number N14A13LIFE SUPPORT POLICYNATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-CONDUCTOR CORPORATION.As used herein:1.Life support devices or systems are devices or sys-tems which,(a)are intended for surgical implant intothe body,or (b)support or sustain life,and whose fail-ure to perform when properly used in accordancewith instructions for use provided in the labeling,can be reasonably expected to result in a significant injury to the user.2.A critical component is any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system,or to affect its safety or effectiveness.National Semiconductor Corporation AmericasTel:1-800-272-9959Fax:1-800-737-7018Email:***************National Semiconductor EuropeFax:+49(0)180-5308586Email:**********************Deutsch Tel:+49(0)180-5308585English Tel:+49(0)180-5327832Français Tel:+49(0)180-5329358Italiano Tel:+49(0)180-5341680National Semiconductor Asia Pacific Customer Response Group Tel:65-2544466Fax:65-2504466Email:*******************National Semiconductor Japan Ltd.Tel:81-3-5639-7560Fax:81-3-5639-7507L M C 6024L o w P o w e r C M O S Q u a d O p e r a t i o n a l A m p l i f i e rNational does not assume any responsibility for use of any circuitry described,no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.。

1206F104xxx中文资料

元器件交易网Multilayer Ceramic Chip Capacitors Products – NPO, X7R, Y5VHOW TO ORDER 0603 N 101 J 500 N T Packaging Code T = 7” reel/paper tape Termination N = Ag/Ni/SnPb B = Cu/Ni/SnPb B = Bulk L = Ag/Ni/Sn C = Cu/Ni/Sn 251 = 250V 501 = 500V 102 = 1000VVoltage (VDCW) 100 = 10V 500 = 50V 160 = 16V 101 = 100V 250 = 25V 201 = 200VAPPLICATIONS ∗ ∗ ∗ ∗ ∗ LC and RC tuned circuit Filtering, Timing, & Blocking Coupling & Bypassing Frequency discriminating DecouplingCapacitance Tolerance (EIA Code) B = ±0.1pF F = ±1% K = ±10% C = ±0.25pF G = ±2% M = ±20% Z = -20+80% D = ±0.50pF J = ±5% Capacitance Two significant digits followed by # of zeros (e.g. 101 = 100pF, 102 = 1000pF, 103 = 10nF) Dielectric N = COG (NPO) Size Code 0402 0805 0603 1206 B = X7R 1210 1804 F = Y5VSCHEMATICL WT1812EENPO ∗ ∗ ∗ ∗ ∗ Ultra-stable Low dissipation factor Tight tolerance available Good frequency performance No aging of capacitance ∗ ∗ ∗ ∗X7R Semi-stable High K High volumetric efficiency Highly reliable in high temp. applications High insulation resistanceY5V ∗ High volumetric efficiency ∗ Non-polar construction ∗ General purpose, High KDIMENSIONS Size Length (L) Width (W) Termination (E) 0402 .040±0.0002 1.00±0.05 0.020±0.002 0.50±0.05 .010+.002/-.004 0.25+0.05/-0.10 0603 0.063±0.004 1.60±0.10 0.03±0.004 0.80±0.07 0.015±0.006 0.40±0.15 0805 0.080±0.006 2.00±0.15 0.050±0.006 1.25±0.15 0.020±0.008 0.50±0.20 1206 0.125±0.006 3.20±0.15 0.063±0.006 1.60±0.15 0.025±0.008 0.60±0.20 1210 0.125±0.012 3.20±0.30 0.100±0.008 2.50±0.20 0.030±0.010 0.75±0.25 1808 0.180±0.015 4.50±0.40 0.081±0.010 2.03±0.25 0.030±0.010 0.75±0.25 1812 0.180±0.015 4.50±0.40 0.125±0.012 3.20±0.30 0.030±0.010 0.75±0.25ELECTRICAL RATING Dielectric Capacitance Range Capacitance Tolerance Dissipation Factor T.C.C. Test Parameters (@25°C) Operating Temperature Insulation Resistance ≤100pF >1000pF NPO (COG) 0.5pF ~ 10nF ±0.1pF, ±0.25pF, ±0.50pF ±1%, ±2%, ±5%, ±10% >30pF, 0.1% Max 0±30ppm/°C 1.0±0.2Vrms, 1MHz±10% 1.0±0.2Vrms, 1KHz±10% -55 ~ +125°C @ 25°C +25°C, 10GΩ min or 500Ω-F min, whichever is less X7R (BME) 100pF ~ 1µF ±5%, ±10%, ±20% 6.3V: 10V & 16V: 25V & 50V: 5.0% 3.5% 2.5% Y5V 10nF ~ 10µF ±20%, -20+80% 6.3V: 10V & 16V: 25V & 50V: 5.0% 3.5% 2.5%0±15ppm/°C 1.0±0.2Vrms, 1KHz±10% -55 ~ +125°C @ 25°C +25°C, 10GΩ min or 500Ω-F min, whichever is less+30%/-80%ppm/°C 1.0±0.2Vrms, 1KHz±10% -25 ~ +85°C @ 20°C +25°C, 10GΩ min or 500Ω-F min, whichever is less570 West Lambert Road, Suite M, Brea, CA 92821 TEL: 714-255-9186 FAX: 714-255-9291American Accurate Components, Inc.1元器件交易网10 Volts – 50 VoltsDIELECTRIC SIZE EIA Cap Code VDCW 0R5 0.5pF 1R0 1 1R2 1.2 1R5 1.5 1R8 1.8 2R2 2.2 2R7 2.7 3R3 3.3 3R9 3.9 4R7 4.7 5R6 5.6 6R8 6.8 8R2 8.2 100 10pF 120 12 150 15 180 18 220 22 270 27 330 33 390 39 470 47 560 56 680 68 820 82 101 100pF 121 120 151 150 181 180 221 220 271 270 331 330 391 390 471 470 561 560 681 680 821 820 102 1000pF 122 1200 152 1500 182 1800 222 2200 272 2700 332 3300 392 3900 472 4700 562 5600 682 6800 822 8200 103 .010µF 123 12000 153 15000 183 18000 223 22000 273 27000 333 33000 393 0.39µFMLCC Products – NPO TypeNPO 10 N N N N N N N N N N N N N N N N 0402 16 25 N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N 50 N N N N N N N N N N N N N N 10 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S 0603 16 25 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S 50 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S 10 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A B B B B B B B B B B D D D D D D D D 0805 16 25 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A B B B B B B B B B B B B B B B B B B B B D D D D D D D D D D D D 50 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A B B B B B B B B B B D D D 10 1206 16 25 50 10 1210 16 25 50 10 1812 16 25 50B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B C C D D D D D D D GB B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B C C D D D D D D D GB B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B C CB B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B C CC C C C C C C C C C C C C C C C C C C C C C C C C C C C C CC C C C C C C C C C C C C C C C C C C C C C C C C C C C C CC C C C C C C C C C C C C C C C C C C C C C C C C C C C C CC C C C C C C C C C C C C C C C C C C C C C C C C C C C C CD D D D D D D D D D D D DD D D D D D D D D D D D DD D D D D D D D D D D D DD D D D D D D D D D D D D* Variations of size, capacitance, voltage, and 13” reel are available upon request.570 West Lambert Road, Suite M, Brea, CA 92821 TEL: 714-255-9186 FAX: 714-255-9291American Accurate Components, Inc.2元器件交易网100 Volts – 3000 VoltsMLCC Products – NPO TypeDIELECTRIC NPO EIA SIZE 0603 0805 1206 1210 CODE VDCW 100 100 200 250 500 100 200 250 500 1000 2000 100 200 250 500 1000 2000 100 200 0R5 0.5pF S A A A A B B B B B B 1R0 1 S A A A A B B B B B B 1R2 1.2 S A A A A B B B B B B 1R5 1.5 S A A A A B B B B B B 1R8 1.8 S A A A A B B B B B B 2R2 2.2 S A A A A B B B B B B 2R7 2.7 S A A A A B B B B B B 3R3 3.3 S A A A A B B B B B B 3R9 3.9 S A A A A B B B B B B 4R7 4.7 S A A A A B B B B B B 5R6 5.6 S A A A A B B B B B B 6R8 6.8 S A A A A B B B B B B 8R2 8.2 S A A A A B B B B B B 100 10pF S A A A A B B B B B B C C C C C C D D 120 12 S A A A A B B B B B B C C C C C C D D 150 15 S A A A A B B B B B B C C C C C C D D 180 18 S A A A A B B B B B B C C C C C C D D 220 22 S A A A A B B B B B B C C C C C C D D 270 27 S A A A A B B B B B B C C C C C C D D 330 33 S A A A A B B B B B B C C C C C C D D 390 39 S A A A A B B B B B B C C C C C C D D 470 47 S A A A A B B B B B B C C C C C C D D 560 56 S A A A A B B B B B C C C C C C D D D 680 68 S A A A B B B B B B C C C C C C D D D 820 82 S A A A B B B B B B C C C C C D D D 101 100pF S A A A C B B B B C C C C C C D D D 121 120 S A C C C B B B B C C C C C C D D D 151 150 S A C C D B B B B C C C C C D D D 181 180 S A D D B B B B C C C C C D D D 221 220 S A B B B B C C C C C D D D 271 270 S A B B B C C C C C C D D 331 330 S A B B B C C C C C D D D 391 390 B B B B C C C C C D D D 471 470 B B C C C C C C D D D 561 560 B B C C C C D D 681 680 B C C C C D D 821 820 B C C C C D D 102 1000pF B C C C C D D 122 1200 B C D D D D 152 1500 C C D D D D 182 1800 C C D D D D 222 2200 C D D D D 272 2700 C D D D D 332 3300 C D 392 3900 D 472 4700 D 562 5600 682 6800 822 8200 103 .010µF * Variations of size, capacitance, voltage, and 13” reel are available upon request. TAPE/REEL PACKAGE TYPE, QUANTITY, AND AVAILABILITY Thickness in mm A = 0.65 + 0.05/-0.15 B = 0.85 + 0.5/-0.15 C = 1.00 + 0.05/-0.15 D = 1.2 + 0.15 G = 1.60 + 0.05/-0.15 K = 2.00 + 0.2 M = 2.5 + 0.3 N = 0.5 + 0.05 S = 0.8 + 0.07 0402 Type Qty Paper 10K 0603 Type Qty Paper 4K 0805 Type Qty Paper 4K Paper 4K Plastic 3K Plastic 3K 1206 Type Qty Paper 4K Paper 4K Plastic 3K Plastic 3K Plastic 2K -1812 1808 250 500 1000 2000 3000 1000 2000 3000D D D D D D D D D D D D D D D D D D D D D D D D D D D D D DD D D D D D D D D D D D D D D D D D D D D D D D D D D DD D D D D D D D D D D D D D D D D D D D D D D DD D D D D D D D D D D D D D D D D D D DD D D D DC C C C C C C C C C C C C K K K K K KC C C C C C C C C C C K K K K KC C C C C C C C C C C C C C1210 Type QtyPlastic Plastic Plastic Plastic Plastic -3K 3K 2K 2K 1K -1808 Type Qty Plastic 2K Plastic 2K Plastic 1K Plastic 1K -1812 Type Qty Plastic 1K Plastic 1K Plastic 1K Plastic 1K -570 West Lambert Road, Suite M, Brea, CA 92821 TEL: 714-255-9186 FAX: 714-255-9291American Accurate Components, Inc.3元器件交易网10 Volts – 50 VoltsMLCC Products – X7R TypeDIELECTRIC X7R SIZE 0402 0603 0805 EIA Cap Code VDCW 10 16 25 50 10 16 25 50 10 16 25 50 10 101 100pF N N N N S S S S B B B B 121 120 N N N N S S S S B B B B 151 150 N N N N S S S S B B B B 181 180 N N N N S S S S B B B B 221 220 N N N N S S S S B B B B B 271 270 N N N N S S S S B B B B B 331 330 N N N N S S S S B B B B B 391 390 N N N N S S S S B B B B B 471 470 N N N N S S S S B B B B B 561 560 N N N N S S S S B B B B B 681 680 N N N N S S S S B B B B B 821 820 N N N N S S S S B B B B B 102 1000pF N N N N S S S S B B B B B 122 1200 N N N N S S S S B B B B B 152 1500 N N N N S S S S B B B B B 182 1800 N N N N S S S S B B B B B 222 2200 N N N N S S S S B B B B B 272 2700 N N N S S S S B B B B B 332 3300 N N N S S S S B B B B B 392 3900 N N N S S S S B B B B B 472 4700 N N S S S S B B B B B 562 5600 N N S S S S B B B B B 682 6800 N N S S S S B B B B B 822 8200 N N S S S S B B B B B 103 N N S S S S B B B B B .010µF 123 .012 N N S S S S B B B B B 153 .015 N N S S S S B B B B B 183 .018 S S S S B B B B B 223 .022 S S S S B B B B B 273 .027 S S S S B B B B B 333 .033 S S S B B B B B 393 .039 S S S B B B B B 473 .047 S S S B B B B B 563 .056 S S S B B B B B 683 .068 S S S B B B B B 823 .082 S S B B B D B 104 S S B B B D B .100µF 154 .150 D D D C 184 .180 D D D C 224 .220 D D D C 334 .330 C 474 .470 684 .680 824 .820 105 1.00µF * Variations of size, capacitance, voltage, and 13” reel are available upon request. TAPE/REEL PACKAGE TYPE, QUANTITY, AND AVAILABILITY Thickness in mm A = 0.65 + 0.05/-0.15 B = 0.85 + 0.5/-0.15 C = 1.00 + 0.05/-0.15 D = 1.2 + 0.15 F = 1.40 + 0.05/-0.15 G = 1.60 + 0.05/-0.15 S = 0.8 + 0.07 N = 0.5 + 0.05 0402 – 0603 Type Quantity 0805 – 1206 Type Quantity Paper 4K/Reel Paper 4K/Reel Plastic 3K/Reel Plastic 3K/Reel Plastic 2K/Reel Plastic 2K/Reel Type 1210 Quantity Type 1808 Quantity Type 1812 Quantity1206 16 2550101210 16 2550101812 16 2550B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B C C C CB B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B C C C CB B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B C C CC C C C C C C C C C C C C C C C C C C C C C C C C C C C C C CC C C C C C C C C C C C C C C C C C C C C C C C C C C C C C CC C C C C C C C C C C C C C C C C C C C C C C C C C C C C C CC C C C C C C C C C C C C C C C C C C C C C C C C C C C C CD D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D DD D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D DD D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D DD D D D D D D D D D D D D D D D D D D D D D D D D D D D D D DPlastic Plastic Plastic Plastic3K/Reel 3K/Reel 2K/Reel 2K/ReelPlastic Plastic Plastic Plastic3K/Reel 3K/Reel 1K/Reel 1K/ReelPlastic Plastic Plastic1K/Reel 1K/Reel 1K/ReelPaper Paper4K/Reel 10K/Reel570 West Lambert Road, Suite M, Brea, CA 92821 TEL: 714-255-9186 FAX: 714-255-9291American Accurate Components, Inc.4元器件交易网100 Volts – 3000 VoltsMLCC Products – X7R TypeDIELECTRIC X7R EIA SIZE 0603 0805 1206 1210 1812 1808 CODE VDCW 100 100 200 250 500 100 200 250 500 1000 1000 2000 100 200 250 500 1000 100 200 250 500 1000 2000 1000 1500 3000 101 100pF S B B B B 121 120 S B B B B 151 150 S B B B B 181 180 S B B B B B B B B B B B 221 220 S B B B B B B B B B B B 271 270 S B B B B B B B B B B B 331 330 S B B B B B B B B B B B 391 390 S B B B B B B B B B B B 471 470 S B B B B B B B B B B B D D C C C 561 560 S B B B B B B B B B B C D D C C C 681 680 S B B B B B B B B B B C D D C C C 821 820 S B B B B B B B B B G G D D C C C 102 1000pF S B B B B B B B B B G G C C C C C D D D D D D C C K 122 1200 S B B B B B B B B B G G C C C C C D D D D D D C C K 152 1500 S B B B B B B B B B G C C C C C D D D D D D C C 182 1800 S B B B B B B B B B G C C C C C D D D D D D C C 222 2200 S B B B B B B B B C G C C C C C D D D D D D C C 272 2700 S B B B B B B B D G C C C C C D D D D D D C D 332 3300 S B B B B B B B G G C C C C D D D D D D D C D 392 3900 S B B B B B B B G G C C C C D D D D D D C 472 4700 S B B B B B B B G G C C C C D D D D D D C 562 5600 S B B B B B G C C C C D D D D D D C 682 6800 S B B B B B G C C C C D D D D D D C 822 8200 S B B B B C C C C C D D D D D D 103 S B B B B C C C C C D D D D D D .010µF 123 .012 S B B B B C C C C D D D D 153 .015 S B B C C C C C C D D D D 183 .018 B B C C C C C C D D D D 223 .022 B C C C C C D D D D D 273 .027 B C C C C C D D D D 333 .033 B C C C D D D D 393 0.39 B C C C D D D D 473 .047 B C D D D D D D 563 .056 B C D D D 683 .068 C C D D D 823 .082 C C D D D 104 D C D D D .100µF 124 .120 D C D D D 154 .150 C D 184 .180 C D 224 .220 C D 334 .330 D 474 .470 D 684 .680 824 .820 105 1.00µF * Variations of size, capacitance, voltage, and 13” reel are available upon request. TAPE/REEL PACKAGE TYPE, QUANTITY, AND AVAILABILITY Thickness in mm A = 0.65 + 0.05/-0.15 B = 0.85 + 0.5/-0.15 C = 1.00 + 0.05/-0.15 D = 1.2 + 0.15 F = 1.40 + 0.05/-0.15 G = 1.60 + 0.05/-0.15 K = 2.00 + 0.2 S = 0.8 + 0.07 N = 0.5 + 0.05 0603-0805-1206 Type Quantity Paper 4K/Reel Paper 4K/Reel Plastic 3K/Reel Plastic 3K/Reel Plastic 2K/Reel Plastic 2K/Reel Type 1210 Quantity Type 1808 Quantity Type 1812 QuantityPlastic Plastic Plastic Plastic3K/Reel 3K/Reel 2K/Reel 2K/ReelPlastic Plastic Plastic Plastic Plastic3K/Reel 3K/Reel 1K/Reel 1K/Reel 1K/ReelPlastic Plastic Plastic Plastic1K/Reel 1K/Reel 1K/Reel 1K/Reel570 West Lambert Road, Suite M, Brea, CA 92821 TEL: 714-255-9186 FAX: 714-255-9291American Accurate Components, Inc.5元器件交易网10 Volts – 50 VoltsMLCC Products – Y5V TypeDIELECTRIC Y5V SIZE 0402 0603 0805 EIA Cap Code VDCW 10 16 25 50 10 16 25 50 10 16 25 50 10 103 N N N S S S S A A A A B .010µF 123 .012 N N N S S S S A A A A B 153 .015 N N N S S S S A A A A B 183 .018 N N N S S S S A A A A B 223 .022 N N N S S S S A A A A B 273 .027 N N N S S S S A A A A B 333 .033 N N N S S S S A A A A B 393 .039 N N N S S S S A A A A B 473 .047 N N N S S S S A A A A B 563 .056 N N S S S S A A A A B 683 .068 N N S S S S A A A A B 823 .082 N N S S S S A A A A B 104 N N S S S S A A A A B .100µF 154 .150 S S S S A A A A B 224 .220 S S S A A A A B 334 .330 S S B B B B 474 .470 S S B B B B 684 .680 S B B B 105 S B B C 1.00µF 155 1.50 C 225 2.20 C 335 3.30 D 475 4.75 D 106 10µF * Variations of size, capacitance, voltage, and 13” reel are available upon request.1206 16 25 B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B C C C C C C D D D D50 B B B B B B B B B B B B B B B B B101210 16 2550101812 16 2550C C C C C C CC C C C C C CC C C C C C CC C C CD D D D D D DD D D D D D DD D D D D D DD D D D D D D100 Volts – 500 VoltsDIELECTRIC Y5V SIZE 0805 1206 1812 EIA Cap Code VDCW 100 200 250 500 100 200 250 500 100 200 250 103 B B B B B .010µF 123 .012 B B B B B 153 .015 B B B B B 183 .018 B B B B B 223 .022 B B B B B 273 .027 B B B B B 333 .033 B B B B B 393 .039 B B B B B 473 .047 B B B B 563 .056 B B B B 683 .068 B B B B 823 .082 B C C C 104 B C C C D D D .100µF 154 .150 C D D D 224 .220 C D D D 334 .330 D D D 474 .470 D D D * Variations of size, capacitance, voltage, and 13” reel are available upon request. TAPE/REEL PACKAGE TYPE, QUANTITY, AND AVAILABILITY Thickness in mm A = 0.65 + 0.05/-0.15 B = 0.85 + 0.5/-0.15 C = 1.00 + 0.05/-0.15 D = 1.2 + 0.15 F = 1.40 + 0.05/-0.15 G = 1.60 + 0.05/-0.15 K = 2.00+0.2mm S = 0.8 + 0.07 N = 0.5 + 0.05 0402 – 0603 Type Quantity 0805 – 1206 Type Quantity Paper 4K/Reel Paper 4K/Reel Plastic 3K/Reel Plastic 3K/Reel Plastic 2K/Reel Plastic 2K/Reel Type 1210 Quantity Type 1808 Quantity Type 1812 Quantity 500Plastic Plastic Plastic Plastic3K/Reel 3K/Reel 2K/Reel 2K/ReelPlastic Plastic Plastic Plastic3K/Reel 3K/Reel 1K/Reel 1K/ReelPlastic Plastic Plastic Plastic1K/Reel 1K/Reel 1K/Reel 1K/ReelPaper Paper4K/Reel 10K/Reel570 West Lambert Road, Suite M, Brea, CA 92821 TEL: 714-255-9186 FAX: 714-255-9291American Accurate Components, Inc.6元器件交易网MLCC Products – PackagingPACKAGING ON TAPE AND REEL Size 0603 0805 T (mm) 0.90~0.70 0.70~0.50 0.90~0.70 1.05~0.85 1.35~1.05 0.90~0.70 1.05~0.85 1.35~1.05 1.05~0.85 1.35~1.05 1.05~0.85 2.15~1.85 1.35~1.05 Tape Paper Tape Paper Tape Paper Tape Plastic Tape Plastic Tape Paper Tape Plastic Tape Plastic Tape Plastic Tape Plastic Tape Plastic Tape Plastic Tape Plastic Tape Quantity 4,000/Reel 4,000/Reel 4,000/Reel 3,000/Reel 3,000/Reel 4,000/Reel 3,000/Reel 3,000/Reel 3,000/Reel 3,000/Reel 3,000/Reel 1,000/Reel 1,000/ReelAREEL FOR TAPINGTaping is in accordance with EIA RS-481 or IEC 286-3TB* C N D1206 1210 1808 1812GUnit: mm Symbol DimensionA 178 ± 2.0N 50 minC 130 ± 0.5D 20 min.B 2.0±0.5G 10.0± 1.5T 14.9max1. PAPER TAPE DIMENSIONSt Feeding hole D A B Chip Capacitors Unlt:mm P P P Direction of FeedE2. PLASTIC TAPE DIMENSIONSChip pocket t Feeding hole D A B Chip Capacitors P Po PChip pocketEF WFWk Unlt:mmDirection of FeedPAPER TAPE W F E P1 P2 P0 ∅P t1 Dimensions in mm 8.0 ± 0.3 3.5 ± 0.05 1.75 ± 0.1 4.0 ± 0.1 2.0 ± 0.05 4.0 ± 0.1 1.5 + 0.1 –0 1.2 maximumPLASTIC TAPE W F E P1 P2 P0 ∅P t1 K Dimension in mm 8.0 ± 0.3 3.5 ± 0.05 1.75 ± 0.1 4.0 ± 0.1 2.0 ± 0.05 4.0 ± 0.1 1.5 + 0.1 –0 0.3 maximum 2.0 maximum570 West Lambert Road, Suite M, Brea, CA 92821 TEL: 714-255-9186 FAX: 714-255-9291American Accurate Components, Inc.7。

ADAM-6024中文资料

U C T I N F O R M A T I O N B &B E L E C T R O N I C SModel: ADAM-6024Compact I/O Combination Solution12-channel Universal Input Output ModuleOverviewThe ADAM-6024 is a compact module that can combine several I/O interfaces, and thereby replace expensive installations that require several I/O modules. Ethernet connectivity is an added bonus.In most equipment monitoring and control applications, both analog inputs/outputs and digital inputs/outputs need to be used, even though they only serve one unit. No matter how simple the installation, you have to purchase several different I/O modules to provide a combination of I/O interfaces. After researching common I/O combinations in the field, ADAM-6024 is the result.Fewer modules, same featuresThe ADAM-6024 is a mixed I/O in ONE module with an optimized I/O portfolio of: two analog outputs, six analog inputs, two digital inputs and two digital outputs. According to research, this is suitable for 80% of single unit applications. Replacing a combination of digital I/O modules and analog I/O modules with the compact ADAM-6024 not only saves space and installation time, but also reduces module cost.Ethernet connectivityThe ADAM-6024 works as an Ethernet I/O data processing center. This product is not only a standard I/O, but also an intelligent system designed with local control functions and a Modbus/TCP standard for users to easily develop various applications over the Ethernet.Embedded web server & pre-built web page for remote monitoring and diagnosticsThe ADAM-6024 features an embedded web server and pre-built web page to display real-time I/O data values, alarm and module status through LAN or Internet. Using an Internet browser, users can easilymonitor real-time I/O data values and alarm anywhere, anytime. Moreover, users can design their own web page to replace the pre-installed web page.Features• Analog inputs with 16-bit effective resolution • 2 analog outputs • 2 digital inputs • 2 digital outputsU C T I N F O R M A T I O N B &B E L E C T R O N I C S SpecificationsAnalog InputChannels: 6 differential Effective Resolution: 16-bit Input Type: V, mA Input Range: ±10 VDC, 0-20 mA, 4-20 mA Isolation Voltage: 2,000 VDC Sampling Rate: 10 samples/sec. Input Impedance: 20 Meg. Ohms Bandwidth: 13.1 Hz @ 50 Hz; 15.72 Hz @ 60 Hz Accuracy: ±0.1 % or better Zero Drift: ±6 µV/° C Span Drift: ±25 ppm/° C CMR @ 50/60 Hz: 92 dB min.Analog Output Channels: 2 Effective Resolution: 12-bit Output Type: V, mA Output Range: 0 -10 VDC, 4-20 mA, 0-20 mA Drive Voltage: 15 VDC (for current output) Isolation Voltage: 2,000 VDC Accuracy: 0.05% of FSR Drift: ±50 ppm/° CDigital InputsChannels: 2 Dry Contact Logic level 0: close to GND Logic level 1: openDigital Outputs Channels: 2 Open Collector to 30 V 100 mA max. load Power Consumption: 4 W (typical)Ordering InformationADAM-6024 12-channel Universal Input Output Module。

MSP50C614中文资料

A flexible clock generation system enables the software to control the clock over a wide frequency range. The implementation uses a phase-locked loop (PLL) circuit that drives the processor clock at a selectable frequency between the minimum and maximum achievable. Selectable frequencies for the processor clock are spaced apart in 65.536 kHz steps. The PLL clock-reference is also selectable; either a resistor-trimmed oscillator or a crystal-referenced oscillator may be used. Internal and external clock sources are controlled separately to provide different levels of power management. The periphery consists of five 8-bit wide general-purpose I/O ports, one 8-bit wide dedicated input port, and one 16-bit wide dedicated output port. The bidirectional I/O can be configured under software control as either high-impedance inputs or as totem-pole outputs. They are controlled via addressable I/O registers. The input-only port has a programmable pullup option (70-kΩ minimum resistance) and a dedicated service interrupt. These features make the input port especially useful as a key-scan interface. A simple one-bit comparator is also included in the periphery. The comparator is enabled by a control register, and its pin access is shared with two pins in one of the general-purpose I/O ports. Rounding out the MSP50C614 periphery is a built-in pulse-density-modulated DAC (digital-to-analog converter) with direct speaker-drive capability. The functional block diagram gives an overview of the MSP50C614 functionality.

STR-F6624资料

UVLO
REF.
FUNCTIONAL BLOCK DIAGRAM
OVER-VOLT. PROTECT
DRIVE REG.
R
FAULT LATCH
S
Q
TSD
OSC
3 DRAIN 2 SOURCE
NORMALIZED ALLOWABLE AVALANCHE ENERGY in mJ
1.0 0.8 0.6 0.4 0.2
元器件交易网
Series STR-F6600 OFF-LINE
QUASI-RESONANT FLYBACK SWITCHING REGULATORS
OUTPUT MAXIMUM RATINGS at TA = +25°C
Part Number STR-F6624
VDSS (V) 450
IDM (A) 19 26 36 11.2 10 14 18 25 6.4 9.2 12
POUT (W) at VIN (V rms)
98 130
145 190
225 290
36 50
40 86
58 120
92 190
150 300
25 (no heatsink) 50 (with heat sink)
0 25
2
–
r SS
+
1.45 V
c SS
–
+
0.73 V
FEEDBACK & 1 OVER-CURRENT
PROTECTION
GROUND
Dwg. FK-002-6
Allowable package power dissipation curves are shown on page 10.

几种常见的开关电源拓扑结构及应用

几种常见的开关电源拓扑结构及应用什么是拓扑呢?所谓电路拓扑就是功率器件和电磁元件在电路中的连接方式，而磁性元件设计，闭环补偿电路设计及其他所有电路元件设计都取决于拓扑。

最基本的拓扑是Buck(降压式)、Boost(升压式)和Buck/Boost(升/降压)，单端反激(隔离反激)，正激、推挽、半桥和全桥变化器。

下面简单介绍一下常用的开关电源拓扑结构。

Buck电路首先我们要讲的就是Buck电路。

Buck电路也成为降压(step-down)变换器。

它的电路图是下面这样的：晶体管，二极管，电感，电容和负载构成了主回路，下方的控制回路一般采用PWM(脉冲宽度调制)芯片控制占空比决定晶体管的通断。

Buck电路的功能是把直流电压Ui转换成直流电压Uo，实现降压目的。

展开剩余88%反激变换器反激式开关电源是指使用反激高频变压器隔离输入输出回路的开关电源，与之对应的有正激式开关电源。

反激(FLY BACK)，具体是指当开关管接通时，输出变压器充当电感，电能转化为磁能，此时输出回路无电流;相反，当开关管关断时，输出变压器释放能量，磁能转化为电能，输出回来中有电流。

反激式开关电源中，输出变压器同时充当储能电感，整个电源体积小、结构简单，所以得到广泛应用。

应用最多的是单端反激式开关电源。

优点：元器件少、电路简单、成本低、体积小，可同时输出多路互相隔离的电压;缺点：开关管承受电压高，输出变压器利用率低，不适合做大功率电源。

Boost电路Boost(升压)电路是最基本的反激变换器。

Boost变换器又称为升压变换器、并联开关电路、三端开关型升压稳压器。

上面的图就是Boost电路图。

Boost电路是一个升压电路，它的输出电压高于输入电压。

Buck/Boost变换器Buck/Boost变换器：也叫做升降压式变换器，是一种输出电压既可低于也可高于输入电压的单管不隔离直流变换器，但它的输出电压的极性与输入电压相反。

Buck/Boost变换器可以看做是Buck变换器和Boost变换器串联而成，合并了开关管。

ED602CS资料

Part Number: ED602CS - ED606CS
PAGE 2
SYMBOLS Maxi mum Recurrent Peak Reverse Voltage Maxi mum RMS Voltage Maxi mum D C Blocki ng Voltage Maxi mum Average Forward Recti fi ed C urrent at TC=75oC Peak Forward Surge C urrent 8.3ms si ngle half si ne-wave superi mposed on rated load(JED EC method) Maxi mum Instantaneous Forward Voltage at 3.0A (Note 1) Maxi mum D C Reverse C urrent (Note 1)TA=25oC at Rated D C Blocki ng Voltage TA=100oC Maxi mum Thermal Resi stance (Note 2) Maxi mum Reverse Recovery Storage T mperature Range e V V V
Fig.4- MAXIMUM NON-REPETITIVE SURGE CURRENT
30 25
CAPACITANCE, PF
20 15 10 5 0 1 2 5 10 20 50 100 200 500
REVERSEVOLTAGE, VOLTS
Fig.5-TYPICAL JUNCTION CAPACITANCE
10 8 6 4 2 1.0 .8 .6 .4 .2 .1
TJ=25 C PULSE WIDTH=200 S m 0.9 1.10 1.30 1.50 1.70 1.90 2.10

XC6112F624资料

1/26XC6101_07_XC6111_17 ETR0207_009Preliminary◆CMOS Voltage Detector◆Manual Reset Input ◆Watchdog Functions ◆Built-in Delay Circuit ◆Detect Voltage Range: 1.6~5.0V, ± 2% ◆Reset Function is Selectable V DFL (Low When Detected) V DFH (High When Detected)■GENERAL DESCRIPTION The XC6101~XC6107, XC6111~XC6117 series aregroups of high-precision, low current consumption voltage detectors with manual reset input function and watchdog functions incorporating CMOS process technology. The series consist of a reference voltage source, delay circuit, comparator, and output driver.With the built-in delay circuit, the XC6101 ~ XC6107, XC6111 ~ XC6117 series’ ICs do not require any external components to output signals with release delay time. Moreover, with the manual reset function, reset can be asserted at any time. The ICs produce two types of output; V DFL (low when detected) and V DFH (high when detected).With the XC6101 ~ XC6105, XC6111 ~ XC6115 series’ ICs, the WD pin can be left open if the watchdog function is not used. Whenever the watchdog pin is opened, the internal counter clears before the watchdog timeout occurs. Since the manual reset pin is internally pulled up to the V IN pin voltage level, the ICs can be used with the manual reset pin left unconnected if the pin is unused.The detect voltages are internally fixed 1.6V ~ 5.0V in increments of 100mV, using laser trimming technology. Six watchdog timeout period settings are available in a range from 6.25msec to 1.6sec. Seven release delay time 1 are available in a range from 3.13msec to 1.6sec.■APPLICATIONS●Microprocessor reset circuits●Memory battery backup circuits ●System power-on reset circuits ●Power failure detection■TYPICAL APPLICATION CIRCUIT* Not necessary with CMOS output products.■FEATURESDetect Voltage Range: 1.6V ~ 5.0V, +2% (100mV increments)Hysteresis Range : V DF x 5%, TYP .(XC6101~XC6107)V DF x 0.1%, TYP .(XC6111~XC6117)Operating Voltage Range : 1.0V ~ 6.0V Detect Voltage Temperature Characteristics : +100ppm/O C (TYP .) Output Configuration : N-channel open drain,CMOSWatchdog Pin : Watchdog inputIf watchdog input maintains ‘H’ or ‘L’ within the watchdog timeout period, a reset signal is output to the RESET output pinManual Reset Pin : When driven ‘H’ to ‘L’levelsignal, the MRB pin voltage asserts forced reset on theoutput pin.Release Delay Time : 1.6sec, 400msec, 200msec,100msec, 50msec, 25msec, 3.13msec (TYP .) can be selectable.Watchdog Timeout Period : 1.6sec, 400msec, 200msec,100msec, 50msec,6.25msec (TYP .) can be selectable.■TYPICAL PERFORMANCE CHARACTERISTICS ●Supply Current vs. Input Voltage* ‘x’ represents both ‘0’ and ‘1’. (ex. XC61x1⇒XC6101 and XC6111)2/26XC6101~XC6107, XC6111~XC6117 SeriesPIN NUMBERXC6101, XC6102 XC6103 XC6104, XC6105XC6106, XC6107XC6111, XC6112 XC6113 XC6114, XC6115XC6116, XC6117SOT-25 USP-6C SOT-25 USP-6C SOT-25 USP-6C SOT-25USP-6CPIN NAMEFUNCTION1 4 - - 1 4 1 4 R ESETB Reset Output(V DFL : Low Level When Detected)2 5 2 5 2 5 2 5 V SSGround3 2 3 2 - -4 1 M RB ManualReset 4 1 4 1 4 1 - - WDWatchdog5 6 5 6 5 6 5 6 V IN Power Input - - 1 4 3 2 3 2 RESETReset Output (V DFH: High Level When Detected)■PIN CONFIGURATION SOT-25 (TOP VIEW)MRBV IN WD RESETBV SSMRBWD RESETV SSV IN RESETWD RESETBV SS V IN SOT-25 (TOP VIEW)RESETMRB RESETBV SS V IN SOT-25 (TOP VIEW) ■PIN ASSIGNMENT●SOT-25XC6101, XC6102 SeriesXC6111, XC6112 SeriesSOT-25 (TOP VIEW)XC6103 & XC6113 SeriesXC6104, XC6105 Series XC6114, XC6115 SeriesXC6106, XC6107 Series XC6116, XC6117 Series●USP-6CXC6101, XC6102 Series XC6111, XC6112 SeriesXC6103 & XC6113 SeriesXC6104, XC6105 Series XC6114, XC6115 SeriesXC6106, XC6107 Series XC6116, XC6117 SeriesUSP-6C (BOTTOM VIEW)USP-6C (BOTTOM VIEW)USP-6C (BOTTOM VIEW)USP-6C (BOTTOM VIEW)* The dissipation pad for the USP-6C package should be solder-plated in recommended mount pattern and metal masking so as to enhance mounting strength and heat release. If the pad needs to be connected to other pins, it should be connected to the V SS pin.3/26XC6101 ~ XC6107, XC6111~ XC6117SeriesRESET OUTPUTSERIES WATCHDOGMANUAL RESET V DFL (RESETB)V DFH (RESET)XC6101 XC6111 Available Available CMOS - XC6102XC6112AvailableAvailableN-channel open drain-XC6103 XC6113 Available Available - CMOS XC6104 XC6114 Available Not AvailableCMOS CMOS XC6105 XC6115 Available Not Available N-channel open drain CMOS XC6106 XC6116 Not Available AvailableCMOSCMOS XC6107XC6117Not AvailableAvailableN-channel open drainCMOSDESIGNATORDESCRIPTIONSYMBOLDESCRIPTION0 : V DF x 5% (TYP .) with hysteresis ① Hysteresis Range1 : V DF x 0.1% (TYP .) without hysteresis② Functions and Type of Reset Output1 ~ 7: Watchdog and manual functions, and reset output type as per Selection Guide in the above chartA : 3.13msec (TYP .)B : 25msec (TYP .) C: 50msec (TYP .) D : 100msec (TYP .) E : 200msec (TYP .) F : 400msec (TYP .) ③ Release Delay Time * H : 1.6sec (TYP .)0 : No WD timeout period forXC6106, XC6107, XC6116, XC6117 Series 1: 6.25msec (TYP .) 2 : 50msec (TYP .) 3 : 100msec (TYP .) 4 : 200msec (TYP .) 5 : 400msec (TYP .) ④ Watchdog Timeout Period6: 1.6sec (TYP .) ⑤⑥ Detect Voltage 16 ~ 50: Detect voltageex.) 4.5V: ⑤⇒4, ⑥⇒5M : SOT-25 ⑦ Package E : USP-6C R : Embossed tape, standard feed ⑧ Device OrientationL: Embossed tape, reverse feed* Please set the release delay time shorter than or equal to the watchdog timeout period. ex.) XC6101D427MR or XC6101D327MR■PRODUCT CLASSIFICATION ●Selection Guide ●Ordering Information XC61①②③④⑤⑥⑦⑧4/26XC6101~XC6107, XC6111~XC6117 Series■PACKAGING INFORMATION●SOT-25●USP-6C5/26XC6101 ~ XC6107, XC6111~ XC6117Series④ Represents production lot number0 to 9 and A to Z and inverted 0 to 9 and A to Z repeated. (G, I, J, O, Q, W expected.) * ‘X’ represents both ‘0’ and ‘1’. (ex. XC61X1⇒XC6101 and XC6111)■MARKING RULE●SOT-25①②③④SOT-25 (TOP VIEW)6/26XC6101~XC6107, XC6111~XC6117 Series① Represents product series② Represents release delay time MARK RELEASE DELAY TIME PRODUCT SERIES A 3.13msec XC61XxAxxxxx B 25msec XC61XxBxxxxx C 50msec XC61XxCxxxxx D 100msec XC61XxDxxxxx E 200msec XC61XxExxxxx F 400msec XC61XxFxxxxx H 1.6sec XC61XxHxxxxx③ Represents watchdog timeout period MARK WATCHDOG TIMEOUT PERIOD PRODUCT SERIES 0 XC61X6, XC61X7 series XC61Xxx0xxxx 1 6.25msec XC61Xxx1xxxx 2 50msec XC61Xxx2xxxx 3 100msec XC61Xxx3xxxx 4 200msec XC61Xxx4xxxx 5 400msec XC61Xxx5xxxx 6 1.6sec XC61Xxx6xxxx④⑤ Represents detect voltage MARK④ ⑤DETECT VOLTAGE (V)PRODUCT SERIES3 3 3.3 XC61Xxxx33xx 5 0 5.0XC61Xxxx50xx⑥ Represents production lot number0 to 9 and A to Z repeated. (G, I, J, O, Q, W excepted.)* No character inversion used. ** ‘X’ represents both ‘0’ and ‘1’. (ex. XC61X1⇒XC6101 and XC6111)MARK PRODUCT SERIES MARK PRODUCT SERIES 3 XC6101xxxxxx 8 XC6111xxxxxx 4 XC6102xxxxxx 9 XC6112xxxxxx 5 XC6103xxxxxx A XC6113xxxxxx 6 XC6104xxxxxx B XC6114xxxxxx 7 XC6105xxxxxx C XC6115xxxxxx 3 XC6106xxxxxx 8 XC6116xxxxxx 4 XC6107xxxxxx 9 XC6117xxxxxx■MARKING RULE (Continued)●USP-6CUSP-6C (TOP VIEW)7/26XC6101 ~ XC6107, XC6111~ XC6117Series■BLOCK DIAGRAMS●XC6101, XC6111 Series●XC6102, XC6112 Series●XC6103, XC6113 Series8/26XC6101~XC6107, XC6111~XC6117 Series■BLOCK DIAGRAMS (Continued)●XC6107, XC6117 Series●XC6106, XC6116 Series●XC6105, XC6115 Series●XC6104, XC6114 Series9/26XC6101 ~ XC6107, XC6111~ XC6117SeriesPARAMETERSYMBOL RATINGSUNITSV INV SS -0.3 ~ 7.0 VM RBV SS -0.3 ~ V IN +0.3 VInput Voltage WD V SS -0.3 ~ 7.0V Output Current I OUT 20 mACMOS Output RESETB/RESET V SS -0.3 ~ V IN +0.3Output Voltage N-ch Open Drain Output RESETB V SS -0.3 ~ 7.0VSOT-25 250Power Dissipation USP-6C Pd 100mWOperational Temperature Range Topr -40 ~ +85 OCStorage Temperature Range Tstg -40 ~ +125 OC■ABSOLUTE MAXIMUM RATINGSTa = 25O C10/26XC6101~XC6107, XC6111~XC6117 SeriesNOTE:*1: XC6101~XC6107 (with hysteresis) *2: XC6111~XC6117 (without hysteresis)*3: ‘X’ represents both ‘0’ and ‘1’. (ex. XC61X1⇒XC6101 and XC6111) *4: V DF(T): Setting detect voltage*5: If only “V DF ” is indicated, it represents both V DFL (low when detected) and V DFH (high when detected).PARAMETERSYMBOLCONDITIONSMIN.TYP .MAX. UNITS CIRCUITDetect Voltage V DFL V DFHV DF(T)× 0.98V DF(T) V DF(T)× 1.02 V 1 Hysteresis Range XC6101~XC6107 (*1) V HYS V DF × 0.02V DF × 0.05 V DF× 0.08 V 1Hysteresis Range XC6111~XC6117 (*2) V HYS 0 V DF × 0.001 V DFx 0.01V 1V IN =V DF(T)×0.9V - 5 11 V IN =V DF(T)×1.1V- 10 16 XC61X1/XC61X2/XC61X3XC61X4/XC61X5 (*3)(The MRB & the WD Pin: No connection) V IN =6.0V - 1218 V IN =V DF(T)×0.9V - 4 10 V IN =V DF(T)×1.1V - 8 14 Supply Current I SS XC61X6/XC61X7 (*3)(The MRB Pin: No connection)V IN = 6.0V - 1016 µA 2Operating Voltage V IN 1.0 - 6.0 V 1VIN = 1.0V 0.15 0.5 -V IN =2.0V (V DFL(T)> 2.0V) 2.0 2.5 - V IN =3.0V (V DFL(T) >3.0V) 3.0 3.5 -N-ch.V DS = 0.5V V IN =4.0V (V DFL(T) >4.0V) 3.5 4.0 - 3 V DFL Output Current (RESETB) I RBOUTCMOS,P-chV DS = 0.5V V IN = 6.0V - - 1.1 -0.8 mA 4 N-chV DS = 0.5VV IN =6.0V 4.4 4.9 - 3V IN =1.0V - - 0.08 - 0.02 V IN =2.0V (V DFH(T)> 2.0V)- - 0.50 - 0.30 V IN =3.0V (V DFH(T)>3.0V)- - 0.75 - 0.55V DFHOutput Current (RESET) I ROUT P-ch. V DS = 0.5V V IN =4.0V (V DFH(T)>4.0V)- - 0.95 - 0.75 mA 4Temperature Characteristics △V DF / △Topr ・V DF -40OC < Topr < 85 O C - +100 - ppm / O C12 3.13 5 13 25 3825 50 75 60 100 140 120 200 280 240 400 560Release Delay Time(V DF <1.8V)T DR Time until V IN is increased from1.0V to2.0Vand attains to the release time level,and the Reset output pin inverts.960 1600 2240 ms 5 2 3.13 5 13 25 38 25 50 7560 100 140 120 200 280 240 400 560 Release Delay Time(V DF >1.9V)T DRTime until V IN is increased from1.0V to (V DF x1.1V) and attains to the releasetime level,and the Reset output pin inverts. 960 1600 2240ms 5 Detect Delay Time T DFTime until V IN is decreased from 6.0V to 1.0V and attains to the detect voltage level, and the Reset output pin detectswhile the WD pin left opened.- 3 30 µs 5V DFL /V DFH CMOS Output Leak CurrentI LEAK V IN =6.0V, RESETB=6.0V (V DFL ) V IN =6.0V, RESET=0V (V DFH )- 0.01 - µA 3V DFL N-ch Open DrainOutput Leak CurrentI LEAKV IN =6.0V, RESETB=6.0V-0.010.10µA 3■ELECTRICAL CHARACTERISTICS●XC6101~XC6107, XC6111~XC6117 SeriesTa = 25O CSeriesPARAMETERSYMBOL CONDITIONS MIN.TYP . MAX. UNITS CIRCUIT3.13 6.25 9.38 25 50 7560 100 140 120 200 280240 400 560 Watchdog Timeout Period (V DF <1.8V)T WDTime until V IN increases form1.0V to2.0V andthe Reset output pin is released to go into the detection state. (WD=V SS )960 1600 2240 ms 6 3.13 6.25 9.38 25 50 75 60 100 140 120 200 280240 400 560 Watchdog Timeout Period (V DF >1.9V)T WDTime until V IN increases form1.0V to (V DF x1.1V)and the Reset output pin is released to go into the detection state. (WD=V SS )960 1600 2240 ms 6 WatchdogMinimum Pulse Width T WDIN V IN =6.0V,Apply pulse from 6.0V to 0Vto the WD pin. 300 - - ns 7 Watchdog High Level VoltageV WDH V IN =V DF x 1.1V ~ 6.0V V IN x 0.7- 6 V 7 Watchdog Low Level Voltage V WDL V IN =V DF x 1.1V ~ 6.0V0 - V IN x 0.3 V 7 V IN =6.0V, V WD =6.0V (Avg. when peak )- 12 19Watchdog Input Current I WD V IN =6.0V, V WD =0V (Avg. when peak) - 19 -12 -µA 8 Watchdog Input ResistanceR WDV IN =6.0V, V WD =0V, R WD =V IN / |I WD |315500880k Ω8PARAMETERSYMBOL CONDITIONS MIN.TYP . MAX.UNITS CIRCUITMRBHigh Level VoltageV MRH V IN =V DF x1.1V ~ 6.0V 1.4 - V IN 9MRBLow Level VoltageV MRL V IN =V DF x1.1V ~ 6.0V-0.35 V9MRBPull-up Resistance R MR V IN =6.0V, MRB=0V, R MR =V IN / |I MRB | 1.6 2.4 3.0 M Ω 10 MRB Minimum Pulse Width (*3) XC6101~XC6105 XC6111~XC6115 T MRINV IN =6.0V,Apply pulse from 6.0V to 0V tothe MRB pin 2.8 - -MRB Minimum Pulse Width (*4) XC6106, XC6107 XC6116, XC6117T MRIN V IN =6.0V,Apply pulse from 6.0V to 0V tothe MRB pin1.2 - -µs11●XC6101 ~ XC6103, XC6106 ~ XC6107, XC6111 ~ XC6113, XC6116 ~ XC6117 Series NOTE:*1: V DF(T): Setting detect voltage *2: If only “V DF ” is indicated, it represents both V DFL (low when detected) and V DFH (high when detected). *3: Watchdog function is available. *4: Watchdog function is not available.Ta = 25O CTa = 25O C ■ELECTRICAL CHARACTERISTICS (Continued)●XC6101~XC6105, XC6111~XC6115 Series■OPERATIONAL EXPLANATIONThe XC6101~XC6107, XC6111~XC6117 series compare, using the error amplifier, the voltage of the internal voltage reference source with the voltage divided by R1, R2 and R3 connected to the V IN pin. The resulting output signal from the error amplifier activates the watchdog logic, manual reset logic, delay circuit and the output driver. When the V IN pin voltage gradually falls and finally reaches the detect voltage, the RESETB pin output goes from high to low in the case of the V DFL type ICs, and the RESET pin output goes from low to high in the case of the V DFH type ICs.<RESETB / RESET Pin Output Signal>* V DFL (RESETB) type - output signal: Low when detected.The RESETB pin output goes from high to low whenever the V IN pin voltage falls below the detect voltage, or whenever the MRB pin is driven from high to low. The RESETB pin remains low for the release delay time (T DR) after the V IN pin voltage reaches the release voltage. If neither rising nor falling signals are applied to the WD pin within the watchdog timeout period, the RESETB pin output remains low for the release delay time (T DR), and thereafter the RESET pin outputs high level signal. * V DFH (RESET) type – output signal: High when detected.The RESET pin output goes from low to high whenever the V IN pin voltage falls below the detect voltage, or whenever the MRB pin is driven from high to low. The RESET pin remains high for the release delay time (T DR) after the V IN pin voltage reaches the release voltage. If neither rising nor falling signals are applied to the WD pin within the watchdog timeout period, the V OUT pin output remains high for the release delay time (T DR), and thereafter the RESET pin outputs low level signal.<Hysteresis>When the internal comparator output is high, the NMOS transistor connected in parallel to R3 is turned ON, activating the hysteresis circuit. The difference between the release and detect voltages represents the hysteresis range, as shown by the following calculations:V DF (detect voltage) = (R1+R2+R3) x Vref(R2+R3)V DR (release voltage) = (R1+R2) x Vref(R2)V HYS (hysteresis range)=V DR-V DF (V)V DR > V DF* Detect voltage (V DF) includes conditions of both V DFL (low when detected) and V DFH (high when detected).* Please refer to the block diagrams for R1, R2, R3 and Vref.Hysteresis range is selectable from V DF x 0.05V (XC6101~XC6107) or V DF x 0.001V (XC6111~XC6117).<Watchdog (WD) Pin>The XC6101~XC6107, XC6111~XC6117 series use a watchdog timer to detect malfunction or “runaway” of the microprocessor. If neither rising nor falling signals are applied from the microprocessor within the watchdog timeout period, the RESETB/RESET pin output maintains the detection state for the release delay time (T DR), and thereafter the RESET/RESETB pin output returns to the release state (Please refer to the FUNCTION CHART). The timer in the watchdog is then restarted. Six watchdog timeout period settings are available in 1.6sec, 400msec, 200msec, 100msec, 50msec, 6.25msec.<MRB Pin>Using the MRB pin input, the RESET/RESETB pin signal can be forced to the detection state. When the MRB pin is driven from high to low, the RESETB pin output goes from high to low in the case of the V DFL type ICs, and the RESET pin output goes from low to high in the case of the V DFH type. Even after the MRB pin is driven back high, the RESET/RESETB pin output maintains the detection state for the release delay time (T DR). Since the MRB pin is internally pulled up to the V IN pin voltage level, leave the MRB pin open if unused (Please refer to the FUNCTION CHART). A diode, which is an input protection element, is connected between the MRB pin and V IN pin. Therefore, if the MRB pin is applied voltage that exceeds V IN, the current will flow to V IN through the diode. Please use this IC within the stated maximum ratings (V SS -0.3 ~ V IN+0.3) on the MRB pin.<Release Delay Time>Release delay time (T DR) is the time that elapses from when the V IN pin reaches the release voltage, or when the watchdog timeout period expires with no rising signal applied to the WD pin, until the RESET/RESETB pin output is released from the detection state. Seven release delay time (T DR) watchdog timeout period settings are available in 1.6sec, 400msec, 200msec, 100msec, 50msec, 25msec, 3.13msec.<Detect Delay Time>Detect Delay Time (T DF) is the time that elapses from when the V IN pin voltage falls to the detect voltage until the RESET/ RESETB pin output goes into the detection state.Series■TIMING CHARTS●CMOS Output●T DF (CMOS Output)VINVDFL LevelGNDVIN Level VDFL Level GNDVIN x 0.1V■NOTES ON USE1. Please use this IC within the stated maximum ratings. Operation beyond these limits may cause degrading or permanent damage to the device.2. When a resistor is connected between the V IN pin and the input, the V IN voltage drops while the IC is operating and a malfunction may occur as a result of the IC’s through current. For the CMOS output products, the V IN voltage drops while the IC is operating and malfunction may occur as a result of the IC’s output current. Please be careful with using the XC6111~XC6117 series (without hysteresis).3. In order to stabilize the IC’s operations, please ensure that the V IN pin’s input frequency’s rise and fall times are more than 1 µ sec/V.4. Noise at the power supply may cause a malfunction of the watchdog operation or the circuit. In such case, please strength the line between V IN and the GND pin and connect about 0.22µF of a capacitor between the V IN pin and the GND pin.5. Protecting against a malfunction while the watchdog time out period, an ignoring time (no reaction time) occurs to the rise and fall times. Referring to the figure below, the ignoring time (no reaction time) lasts for 900µsec at maximum.GNDGNDGNDVIN Pin Wave FormWD Pin Wave FormRESETB Pin Wave Form (VDFL)SeriesPIN NAMELOGIC CONDITIONSH V IN >V DF +V HYS V IN L V IN <V DF H MRB>1.40V MRBL MRB<0.35V H When keeping W D >V WDH more than T WD L When keeping W D <V WDL more than T WD L → H V WDL → V WDH , T WDIN >300nsec WDH → L V WDH →V WDH , T WDIN >300nsecV IN MRB WD RESETB (*2) H HH LRepeat detect and release (H →L →H)H OpenH L → HH H or Open H → L H HLL *1 LV IN MRB WD RESETB (*3) H HH LRepeat detect and release (L →H →L)H OpenH L → HH H or Open H → L L HLL *1 HV IN WD RESETB (*2) RESET (*3) H HH L Repeat detect and release (H →L →H)Repeat detect and release (L →H →L)H OpenH L → HH H → L H L HL*1 L HV IN MRB RESETB (*2)RESET (*3)H H or Open H LH LL L H■PIN LOGIC CONDITIONSNOTE:*1: If only “V DF ” is indicated, it represents both V DFL (low when detected) and V DFH (high when detected).*2: For the details of each parameter, please see the electrical characteristics. V DF : Detect VoltageV HYS : Hysteresis RangeV WDH : WD High Level Voltage V WDL: WD Low Level Voltage T WDIN : WD Pulse Width T WD : WD Timeout Period■FUNCTION CHART●XC6103/XC61113 Series●XC6104/XC61114, XC6105/XC6115 Series●XC6106/XC61116, XC6107/XC6117 Series●XC6101/XC61111, XC6102/6112 Series*1: Including all logic of WD (WD=H, L, L →H, H →L, OPEN). *2: When the RESETB is High, the circuit is in the release state. When the RESETB is Low, the circuit is in the detection state. *3: When the RESET is High, the circuit is in the release state. When the RESET is Low, the circuit is in the detection state.■TEST CIRCUITSCircuit 1Circuit 2Circuit 3Circuit 4Series ■TEST CIRCUITS (Continued)Circuit 5Circuit 6Circuit 7■TEST CIRCUITS (Continued)Circuit 8Circuit 9Circuit 10Circuit 11Series■TYPICAL PERFORMANCE CHARACTERISTICS(1.1) Supply Current vs. Input Voltage(1.2) Supply Current vs. Input Voltage■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)(2) Detect, Release Voltage vs. Ambient Temperature(1.2) Supply Current vs. Input Voltage (Continued)Series■TYPICAL PERFORMANCE CHARACTERISTICS (Continued) (3-1) Output Voltage vs. Input Voltage (V DFL ) (3.1) Detect, Release Voltage vs. Input Voltage (V DFL )(3.2) Detect, Release Voltage vs. Input Voltage (V DFH )■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)(4) N-ch Driver Output Current vs. V DSSeries(6) P-ch Driver Output Current vs. Input Voltage 1■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)(8) Release Delay Time vs. Ambient Temperature(7) P-ch Driver Output Current vs. Input Voltage 2■TYPICAL PERFORMANCE CHARACTERISTICS (Continued) (10) Release Delay Time vs. Input Voltage(11) Watchdog Timeout Period vs. Input VoltageSeries■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)(14) MRB Low Level Voltage vs. Ambient Temperature(15) MRB High Level Voltage vs. Ambient Temperature* ‘X’ represents both ‘0’ and ‘1’. (ex. XC61X1⇒XC6101 and XC6111)。

FAN7314中文资料

FAN7314 LCD Backlight Inverter Drive IC元器件交易网FAN7314 LCD Backlight Inverter Drive IC元器件交易网FAN7314 LCD Backlight Inverter Drive ICPin AssignmentsPin DeﬁnitionsPin NumberPin NamePin Function Description1OLP Open Lamp Protection 2OLR Open Lamp Regulation 3ENA Enable Input 4S_S Soft Start 5GND Analog Ground 6REF 2.5V Reference Voltage 7ADIM Analog Dimming Input 8BDIM Burst Dimming Input 9EA_IN Error Ampliﬁer Input 10EA_OUT Error Ampliﬁer Output11BCT Burst Dimming Timing Capacitor 12RT Timing Resistor 13CT Timing Capacitor 14OUTD NMOSFET Drive Output D 15OUTC PMOSFET Drive Output C 16PGND Power Ground 17VIN Supply Voltage18OUT A PMOSFET Drive Output A 19OUTB NMOSFET Drive Output B 20RT1Striking Frequency ResistorFAN73142019181716151413121110987654321OLPOLRENAS_SOUTC REFADIMBDIMEA_IN EA_OUTRT1OUTB OUTA VIN PGND OUTD CT RT BCT GND元器件交易网FAN7314 LCD Backlight Inverter Drive ICAbsolute Maximum RatingsFor typical values T A = 25 ° C, V CC = 12V and for min/max values T A is the operating ambient temperature range with –25 ° C ≤ T A ≤ 85 ° C and 5V ≤ V CC ≤ 25.5V , unless otherwise speciﬁed.Notes:1. Thermal resistance test board:Size: 76.2mm x 114.3mm x 1.6mm(1S0P)JEDEC standard: JESD51-2, JESD51-32. Assume no ambient airflow.ESD LevelElectrical CharacteristicsFor typical values T A = 25 ° C, V CC = 12V and for min/max values T A is the operating ambient temperature range with –25 ° C ≤ T A ≤ 85 ° C and 5V ≤ V CC ≤ 25.5V , unless otherwise speciﬁed.SymbolParameterValueUnitV CC Supply Voltage5 to 25.5V T opr Operating T emperature Range -25 to 85 ° C Tj Junction T emperature 150 ° C Tstg Storage T emperature Range -65 to 150° C R θ JA Thermal Resistance Junction-Air (1, 2) 70 ° C/W PdPower Dissipation1.8WParameterPins ConditionsLevelUnitHuman Body Model (HBM)All pinsR = 1.5k Ω , C = 100pF 2000VMachine Model (MM)All pins except for BDIM C = 200pF300BDIM250SymbolCharacteristicsTest ConditionMin.Typ.Max.UnitREFERENCE SECTION (Recommend X7R Capacitor)∆ Vref Line Regulation 5 ≤ V CC ≤ 25.5V–225mV V25 2.5V Regulation Voltage 2.452.5 2.55V OSCILLATOR SECTION (Main)foscOscillation FrequencyT A = 25 ° C, Ct = 270pF Rt = 18k110.4115119.6kHzCt = 270pF , Rt = 18k108115122Vcth CT High Voltage – 2.0–V Vctl CT Low Voltage –0.5–V OSCILLATOR SECTION (Burst)foscbOscillation FrequencyT A = 25 °C, Ctb = 10nF , Rt = 18k204.75225245.25HzCtb = 10nF , Rt = 18k201225248Vbcth BCT High Voltage –2–V VbctlBCT Low Voltage–0.5–V元器件交易网FAN7314 LCD Backlight Inverter Drive ICERROR AMP SECTIONOpen Loop Gain (1) –80–dB Unit Gain Bandwidth (1)–1.5–MHz Veh Feedback Output High Voltage EA_IN = 0V2.13 2.4 2.57V lsin Output Sink Current EA_OUT = 1.5V ––-1mA lsur Output Source Current EA_OUT = 1.5V1––mA Iolr EA_IN Driving Current On OLR 75105135µA Iburst EA_IN Driving Current On Burst Dimming6185109µA VfbhFeedback High Voltage On Burst Dimming R(EA_IN) = 60k ΩVa + 0.1Va + 0.4Va + 0.7VSOFT START SECTION I SS Soft Start CurrentS_S = 2V468µA Vssh Soft Start Clamping Voltage 2.32.653V PROTECTION SECTIONVolp0Open Lamp Protection Voltage 0Start at open lamp 2.2 2.5 2.8V Volp1Open Lamp Protection Voltage 1Normal → open lamp1.3 1.5 1.7V Volr Open Lamp Regulation Voltage 1.7522.25V IolpOpen Lamp Protection Charging Current0.71.42.1µAUNDER VOLTAGE LOCK OUT SECTION Vth Start Threshold Voltage ––5V Ist Start Up CurrentV CC = Vth–0.2–130180µA Iop Operating Supply Current V CC = 12V – 1.54mA Isb Stand-by Current V CC = 12V–200370µA ON/OFF SECTIONVon On State Input Voltage 2–5V Voff Off Stage Input Voltage ––0.7V OUTPUT SECTIONVpdhv PMOS Gate High Voltage V CC = 12V –Vcc –V Vphlv PMOS Gate Low Voltage V CC = 12V Vcc–10.5Vcc–8.5Vcc–6.5V Vndhv NMOS Gate Drive Voltage V CC = 12V 6.58.510.5V Vndhv NMOS Gate Drive Voltage V CC = 12V –0–V Vpuv PMOS Gate Voltage With UVLO ActivatedV CC = Vth–0.2Vcc–0.3––V Vnuv NMOS Gate Voltage With UVLO Activated V CC = Vth–0.2––0.3V T r Rising Time (1) V CC = 12V , Cload = 2nF –200500ns TfFalling Time (1)V CC = 12V , Cload = 2nF–200500nsSymbol CharacteristicsTest Condition Min.Typ.Max.UnitElectrical Characteristics (Continued)For typical values T A = 25 ° C, V CC = 12V and for min/max values T A is the operating ambient temperature range with –25 ° C ≤ T A ≤ 85 ° C and 5V ≤ V CC ≤25.5V , unless otherwise speciﬁed.元器件交易网FAN7314 LCD Backlight Inverter Drive ICNotes:1. These parameters, although guranteed, are not 100% tesed in production.2. Specifications to -25°C to 85°C are guaranteed by design based on final characterization results.MAX./MIN. OVERLAPMin. Overlap Between Diagonal Switches (1)fosc = 100kHz –0–%Max. Overlap Between Diagonal Switches (1)fosc = 100kHz–100–%DELAY TIMEPDR_A/NDR_B (1)Rt = 18k –450–ns PDR_C/NDR_D (1)Rt = 18k–450–nsSymbol CharacteristicsTest ConditionMin.Typ.Max.Unit元器件交易网FAN7314 LCD Backlight Inverter Drive ICMain oscillator: The timing capacitors (CTs) are charged by the reference current source. The current source is formed by the timing resistor (R T ). The timing resistor’s voltage is regulated at 1.25V . The sawtooth waveform (see top of next column) charges up to 2V .Once this voltage is reached, the capacitors begin dis-charging down to 0.5V . Next, the timing capacitors start charging again and a new switching cycle begins. The main frequency can be programmed by adjusting the R T and C T values. The main frequency can be calculated as shown below:Burst oscillator & burst dimming: The timing capaci-tors (BCTs) are charged by the reference current source,which is formed by the timing resistor (R T ). The timing resistor’s voltage is regulated at 1.25V . The sawtooth waveform charges up to 2V . Once this voltage is reached, the capacitors begin discharging down to 0.5V Next the timing capacitors start charging again and a new switching cycle begins. The burst dimming fre-quency can be programmed by adjusting the R T and BC T values. The burst dimming frequency can be calcu-lated as shown below:f = 19------------------------------ 3.75FAN7314 LCD Backlight Inverter Drive ICOpen lamp regulation & open lamp protection:It isnecessary to suspend power stage operation if an openlamp occurs, because the power stage has high gain.When a voltage higher than 2V is applied to the OLR pin,the part enters regulation mode and controls theEA_OUT voltage. This limits the lamp voltage by sum-ming 105µA into the feedback node. At the same time,the OLP capacitor, connected to the OLP pin, is chargedby the 1.4µA internal current source. Once it reaches2.5V, the IC enters shut down where all the output ishigh.Output Drives: The four output drives are designed sothat switches A and B, C and D never turn on simulta-neously. The OUT A-OUTB pair is intended to drive onehalf-bridge in the external power stage. The OUTC-OUTD pair will drive the other half-bridge.FAN7314 LCD Backlight Inverter Drive ICFAN7314 LCD Backlight Inverter Drive ICFAN7314 LCD Backlight Inverter Drive IC4. Winding Speciﬁcation5. BOM of the Application Circuit Pin No.WireTurnsInductanceLeakage InductanceRemarks5 → 2 1 UEW 0.45 φ12180µH 7.2µH 1KHz, 1V 7 → 91 UEW 0.04 φ2430 (270 x 9)7.2H330mH1KHz, 1VPart Ref.ValueDescription/VendorPart Ref.ValueDescription/VendorFuse C5220p 50V 1608 J F124V 3AFuse C61µ50V 2012 K Resistor (SMD)C710µ16V 3216R1330K 1608 J C810µ16V 3216R256K 1608 F C91µ16V 1608 K R318K 1608 F C1015p 3KV 3216R422K 1608 F C1115p 3KV 3216R527K 1608 F C1215p 3KV 3216R682K 1608 F C1315p 3KV 3216R8100K 1608 F C1410n 50V 1608 K R99.1K 1608 F C1510n 50V 1608 K R111K 1608 F C17 2.2n 50V 1608 Z R121K 1608 F C18 2.2n 50V 1608 Z R131K 1608 F C19 2.2n 50V 1608 Z R14100K 1608 F C20 2.2n 50V 1608 Z R1510K 1608 F C2110n 50V 1608 Z R161K 1608 F C251µ50V 2012 K R171K 1608 F C260.1µ16V 1608 K R181K 1608 F C271µ50V 2012 K R191K 1608 F C2810n 50V 1608 Z R2010K 1608 J C2910n 50V 1608 K R2110K 1608 J C3010n50V 1608 K R2210K 1608 J Diode / TR (SMD)R2310K 1608 J D1BAW56Fairchildsemi R2410K 1608 J D3BAV70Fairchildsemi R2510K 1608 J D4BAV70Fairchildsemi R261K 1608 F D6BAV99Fairchildsemi R2710K1608 J D7BAV99Fairchildsemi Capacitor (SMD)D8BAV99Fairchildsemi C10.22µ16V 1608 K D9BAV99Fairchildsemi C21µ50V 2012 K D10BAW56Fairchildsemi C3 4.7n 50V 1608 K D11BAW56Fairchildsemi C44.7n50V 1608 KQ1KST2222FairchildsemiFAN7314 LCD Backlight Inverter Drive IC 5. BOM of the Application Circuit (Continued)Part Ref.Value Description/Vendor Part Ref.Value Description/Vendor Electrolytic capacitor Wafer (SMD)C22220µ25V CN135001WR-02AMOSFET (SMD)CN235001WR-02AM1FDS8958A Fairchildsemi CN335001WR-02AM2FDS8958A Fairchildsemi CN435001WR-02ATransformer (SMD)CN512505WR-10TX1EFD2124Supported by Namyang electronics(http://www.namyangelec.co.kr)TX2EFD2124FAN7314 LCD Backlight Inverter Drive ICFAN7314 LCD Backlight Inverter Drive IC。

MBI6024

____________________ MBI6024 Application Note V1.00-CN____________________MBI6024为针对LED 应流驱图1 过时 A-Token寻来数传稳将为计压降项 V DD 压项.. 计 CKI频率项 CKI 时项.. 产项 / 时压击连计产了带 .. 测试应 V LED 压应图1. LED计图2为MBI6024应路图图2. LED 应路图____________________ MBI6024 Application Note V1.00-CN____________________1. 压降项LED 串时为线产压降 LED 不图3为压降图过 LED 许压降压降 V DS 压转压(LED 亮度不 ) 颗IC V DD不 (传不 )图3. 压降图简单较给DC/DC converter 12V 24V DC/DC converter 降压给V LED 图4 V LED 压计V LED, MIN. = (V F, MAX. x n) + V DS (1)图4. V LED 压计图V F,MAX. LED顺压 n LED串颗数 /OUTn 压为17V LED V LED 过17V将对IC 伤 V LED 压应请 16V LED 7V 12V给DC/DC converter, DC/DC converter 将12V降压 7V给V LED 为V DD 压为5V 颗LDO 将7V降 5V给V DD 图5 选择LDO时 Input voltage 压 Dropout Voltage Maximum junction temperature 则将 MBI6024 V DD 压稳度若DC/DC converter 压 5V 则V DD 须 4.7uF 10uF 0.1uF 来 LED切换图6____________________ MBI6024 Application Note V1.00-CN____________________图5. DC/DC converter 图图6. 图DC/DC converter 应来压稳若绕线则绕线须图7 C d 应压来调图8为图9为不图7.图8.图9. 不PCB layout 时议 0 (R 8) Bead 开DC/DC converter MBI6024 来降 DC/DC converter switching 路V DDV DD____________________ MBI6024 Application Note V1.00-CN____________________2. V DD 压项MBI6024 V DD若不将 IC内逻辑断不度降图10 V DD 为5V时 V IH/V IL 断为3.65V 1.4V V DD为4V时 V IH/V IL 断 2.92V 1.12V 断降将讯现压降项图10. V DD不图3. 项当串颗线 1颗压 DC/DC converter 压须针对线规计压降将图11 AWG26 导 (Maximum Conductor Resistance)为152Ω/km 谓1km 传线 152Ω 当 40mA 则串 10颗将产 2.08V 压降串颗数图11. 图4. 线选择项当讯时讯产 cross-talk现图12 为了现讯 GND将讯开图13 对绞线 cross-talk 请线选择线时为线径宽杂传议 AWG26 线 200 传线额流不 VIN 流 1为线规当选择AWG26线时流须 3.5A 则线过许流热图12. cross-talk 现图13. 线1. 线规5. 讯质量项图14为讯质量图15~17为错误讯质量计路时须预留 (R 1,2,3,4) 为图18 线不 (R 1,2,3,4) 不应须选择过 (over-shoot)/ (under-shoot) 压 R 3,4 时R 1,2, 开路别 CKO/SDO 降时不过则过传败若 R 1,2 时R 3,4 0 别须 0.28×V DD 为则将传败讯 cross-talk 现过则须讯 GND 将讯开请线选择项____________________ MBI6024 Application Note V1.00-CN____________________图14. 讯质量图15. 错误讯质量 ( 不 )图16. 错误讯质量 (过/ 压过 )图17. 错误讯质量 (cross-talk过 )图18. 预留CKISDICKISDICKISDI____________________ MBI6024 Application Note V1.00-CN____________________6. 过度应力项积产级 ESD 计为让LED 更过度应力 Electrical Overstress EOS 力 EOS 组图19 TVS1,2,3 选择态压 (Transient Voltage Suppressor TVS)时a. 压(V RWM) 5Vb. 压(V C) 5Vc. CKO/SDO / 降时讯传频率 off-state (C j)议为3pF 图 TVS2,3 若 V DD 则不图 TVS1d. TVS应 MBI6024 便 EOS进路 EOS图19. 过度应力组7. LED 顺压项过 V LED 让IC 不热对LED 顺压(V F) 筛选 LED顺压8. 流项MBI6024 (R5,6,7) 来调 LED 流(I OUT) 当 LED 流利列 R ext5,6,7R ext5,6,7 = (0.61V / I OUT) x 23 (2)R ext5,6,7 IC R ext 压议误 (tolerance)为1% 来较流____________________ MBI6024 Application Note V1.00-CN____________________9. 流项当当 R ext 稳流则IC /OUTA,B,C 压(V DS) 维转压(Knee Voltage) 为了压降 IC IC V DS 压议转压(Knee Voltage) +0.2V 图20 图21为MBI6024 不 R ext LED 流压关图不流V DS 压图20. V DD为5V时 I OUT V DS关图21. V DD为3.3V时 I OUT V DS关____________________ MBI6024 Application Note V1.00-CN____________________讯计1. CKI频率项MBI6024 CKI频率 200kHz FPGA 读数时CKI不讯度较 MCU 为虑 8051 4 clocks cycles/machine (4T) SPI MCU2. CKI 时项MBI6024 Time-out 来数 Time-out 利内荡检测CKI 数当CKI 时过Time-out 时 MBI6024 略数阶数为图22 读储时较现CKI 读时不过CKI Time-out 数 2 Time-out CKI 数选择 4 (default为95~172 CKI cycle) CF2[1:0]选择CKI 数当选择default 时当CKI 过95 CKI 数时 MBI6024 略数 CKI 172 CKI 数 MBI6024 略数图22. CKI 时图2. 4 CKI time-out 数图23为 CKI 时过例当Time-out 为11(95~172 CKI cycle) CKI 为1us CKI 96us 则CKI 时满 Time-out MBI6024 略数 CKI 过172us时 MBI6024将略资料图23. CKI 时过例____________________ MBI6024 Application Note V1.00-CN____________________3. 讯MBI6024 讯 SPI-like 利 CKI 缘来 SDI 图24图24. SPI-like 图讯应该时数a. 时时为CKI SDI 时pull low(T d0) 时为了让MBI6024 阶数更时 (T frame) 时须满T d0 T frame T D0 (3)T d0 > CKI time-out period (4)T D0为传数时 16-bits T D0= T CKI x 48 x (4 x N+1) 10-bits T D0= T CKI x 30 x (4 x N+1) N为串颗数 T CKI为CKI 时 CKI Time-out 数选择 4 (default为95~172 CKI cycle) CF2[1:0]来缩 Time-out CKI 数图25 选择default 时时 172 CKI 数 MBI6024 Time-out gray scale data图25. 时图例:串 64颗 MBI6024 16-bits grayscale data CKI time-out period 为11(default) CKI (T CKI) 1us(1/1MHz) 更时为16.67ms (1/60Hz) 则Confidential ____________________ MBI6024 Application Note V1.00-CN____________________(1) 时为T d0 = 16.67ms –1us x 48 x (4 x 64+1) = 4.33ms 时 172 CKIcycle(172 x 1us =172us) 图26图26. 时为4.33ms 图b.为了让颗MBI6024 阶数阶数须 H(Command Header) A(Address) L(Length) P(Parity Check)Command Header说MBI6024 6 Command 选择 3 须数态 Command Header Command 16- bit Gray scale data 则 6b’1111113. 6 CommandAddress Length说MBI6024寻 A-Token A-Token 理过串将Address Length 传颗IC 过颗IC Address 1 为 1颗IC寻图27 当Address Length 时数 Latch Address Length 写当 MBI6024 Length 串 IC 颗数 1 写串 2颗MBI6024 Length为1(10’b0000000001) Address 串颗数关须 0(10b’0000000000)图27. Address累图Confidential____________________ MBI6024 Application Note V1.00-CN____________________Parity Check 说MBI6024 parity check 认 Command Header Address Length 传过错显不当parity check若 Command Header Address Length 现错误该数将 parity check 为 parity check 认为0(关闭) 过 CF1[0]来开 parity check 为parity check 例 parity check P[3]为P[2:0] / 结图28图28. parity check 例MBI6024串 2颗时针对不 command 时例a. 16- bit Configuration Data图29. 16-bit Configuration data 例颗IC Configuration 资料 3x16 bits 为Length 为1(10’b0000000001) Header 2x3x16 bits Configuration data X2,CF1 连续 2 X3,CF2 1 bit CF1Bit Function9:8 PWM clock frequency selection = 10 (internal oscillator divided by two) 7 0 6:5 GCLK source selection = 11 (Internal oscillator) 4 PWM counter reset = 1(PWM counter reset after configuring control register) 3 PWM data synchronization=1(Automatic synchronization) 2:1 Clock reverse = 11 0 Parity check =1(Enable)CF2Bit Function 2 Time-out =1(Enable)1:0 CKI time-out period selection =01(23~44 CKI)____________________ MBI6024 Application Note V1.00-CN____________________b. 10- bit Configuration Data图30. 10-bit Configuration data 例颗IC Configuration data 3x10 bits 为Length为1(10’b0000000001) Header 2x3x10 bits Configuration data CF1 连续 2 CF2 1 bit 16- bit Configuration Datac. 8- bit Dot Correction Data图31. 8-bit dot correction data 例Header里 2 Command Header 须 6b’110011 8-bit dot correction data 须连续 2 图 C2C2,B2B2,… 为Length为1(10’b0000000001) Header 2x3x4x16 bits dot correction datad. 6- bit Dot Correction Data图32. 6-bit dot correction data 例Header里 2 Command Header 须 6b’100111 6-bit dot correction data 1 图 ZC2,ZB2,… 为Length为1(10’b0000000001) Header 2x3x4x10 bits dot correction data____________________ MBI6024 Application Note V1.00-CN____________________e. 16- bit Gray Scale Data图33. 16-bit gray scale data 例Header里 2 Command Header 须 6b’111111 为Header里 Length为1(10’b0000000001) Header 2x3x4x16 bits gray scale dataf. 10- bit Gray Scale Data图34. 10-bit gray scale data 例Header里 Command Header 须 6b’101011 为Header里 Length为1(10’b0000000001) Header 2x3x4x10 bits gray scale data____________________ MBI6024 Application Note V1.00-CN____________________产1. / 时压击连计进行连 / 时为了 LED 连连产不压击 IC 烧关闭进行将连 GND 计较VIN来降 / 时产不压击图35 图36 顺议讯讯图35. 连计( )图36. 连计(讯 )2. 产LED 产时应 : 骤1 时请关闭骤2 对带静应进行静 LED 连骤3 认路骤4 认线讯线连导线都连骤5 进行应骤6 产进行时应关闭残压释进行3. 了带带为带对MBI6024 V DD /GND/CKI/SDI/CKO/SDO 产流压 IC 烧了过度应力连 GND 请带4. 路项a. 路 (Printed Circuit board PCB) 过应 (Empty Solder) 冷 cold solder) 锡裂(Split Solder)b. 组时应 PCBc. PCB 较计议选择较 PCB 弯冷锡裂组断裂____________________ MBI6024 Application Note V1.00-CN____________________测试为 CKI频率 LED 讯质量颗数不调组请 1MHz CKI频率测试稳度 RGB 阶为16’b0101010101010101 10’b010*******R→G→B→W→R→G… 亮LED 若显 500kHz为 CKI频率现 LED 亮 LED 不为若现频率将 LED 亮环该频率请降频率 200kHz为若200kHz 时请认CKI/SDI讯 IC 断错误应V LED 压应LED串数较应 LED 压(V LED) /OUTn 压 /OUTn关闭时将对IC 伤简单 (R9~20) MBI6024 /OUTn 当IC /OUTn开时降 V DS 压转压V knee 当IC /OUTn关闭时 LED 流过许流产压降 V DS 压不过/OUTn 压图37图37. V LED 压应路图利骤计1. 觉LED亮度时流 I LED-CUT(Max.)2.R9~20 = (V LED - N x V F,LED-CUT(Max.)) / I LED-CUT (5)V LED - N x V F,LED-CUT(Max.) 须 17V N为LED串颗数 V F,LED-CUT(Max.)为LED 流I LED-CUT(Max.)时顺压3. 将R9~20 MBI6024 /OUTn 关闭/OUTn 认/OUTn 压V DS 17V____________________ MBI6024 Application Note V1.00-CN____________________例 V LED为24V 串 11颗亮度LED 则3. 例 LED I-V数1. 3 LED 觉亮度流 I LED-CUT(Max.)为0.0024mA2. (5) R9~20 = (24V - 11 x 1.48V)/0.0024mA =3.2MΩ( 0603 3.3 MΩ)24V - 11 x 1.48V=7.72V < 17V3. 将R9~20 MBI6024 /OUTn 关闭/OUTn 测V DS为7.61V 认压 17V觉LED亮度。

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外部器件设计
(a) 反激整流的应用如图 1 所示， LPC和RES管脚的电阻需要根据LPT 控制进行适当设计。根据图3，当LPC端电压在一个消隐时序（ tLPC-EN ）内高于 VLPC-EN 时， SR 的栅极准备输出。当 LPC 端电压跌落到低于 VLPC-TH-HIGH (0.05VOUT) 时， SR MOSFET 开始输出。因此， VLPC-EN 必须高于 VLPCTH-HIGH ，否则 SR MOSFET 不能导通。所以， LPC 端的电压分压器R1和R2, 应该满足下式：
VIN .MIN VO ) R1 R2 n 30.4 2 VO R2 0.3 40 根据方程（2）可以得到LPC的分压比的最小值为： 0.83 (
R1 R2 R2 ( VIN .MAX VOUT ) n 24.4 4
R2
Clamping circuit could be a voltage regulator or voltage clamping components
1 R3 R4 19 VO 3.8 4 R4 4.96
因此，R3和R4分别选为36kΩ和9.1kΩ。
© 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 7/29/11
3
AN-6204
VLPC
VLPC-HIGH 0.83VLPC-HIGH 0.05VOUT
T
Figure 4.
VIN/n VIN/n+VOUT VOUT
采用FAN6204时正激续流整流的典型波形
VLPC
VLPC-HIGH 0.83VLPC-HIGH 0.05VOUT
Blanking time
Figure 3. 采用FAN6204时QR反激变换器的典型波形
V R2 0.83 ( IN .MIN VOUT ) 0.05VOUT 0.3 R1 R2 n
(1)
(b) 双管正激式续流整流的应用图2给出了一种将FAN6204应用于正激续流二极管整流的典型应用电路。由于VLPC-EN 必须大于 VLPC-TH-HIGH，因此LPC端的电压分压器R1和R2，需要满足下式：
Table 1. 系统指标输入输入电压范围电源频率范围输出输出电压(Vo) 输出功率(Po) 19V 90W 90~264VAC 47~63Hz
根据设计指南，计算出关键参数，并在表 2 中给予总结。
Table 2. 关键系统参数 PFC 部分 PFC输出电压电平1 (PFCVo1) PFC 输出电压电平 2 (PFCVo2) PFC 电感量 (Lb) PFC 电感匝数(Nb) 副边绕组匝数 (NAUX) 最小开关频率 (fs,min,PFC) PWM部分 PWM 变压器原边电感匝数(NP) PWM 变压器副边绕组匝数(NAUX) PWM 变压器的匝比 (n) 原边电感 (LP) 最小开关频率(fs,min,PWM) 41T 6T 6.8 700µ H 52kHz 250V 400V 385µ H 60T 8T 55kHz
(4)
由于 RES 和 LPC 之间的分压比（ Voltage Scale-Down Ratio）（K）是5，所以CT (tCT.DIS) 的放电时间和电感电流的放电时间（ tL.DIS ）相等。然而，考虑到分压电阻和内部电路的公差，为了保证tCT.DIS小与tL.DIS，分压比(Scale-Down Ratio) （K ）应该大于5。K的典型值为 5~5.5。

AN-6204
FAN6204 — 反激和正激续流整流的同步整流控制器
引言
本应用手册给出了飞兆半导体次级同步整流控制器（ SR ） FAN6204 的设计要点，适用于连续导通模式（CCM）、断续导通模式（DCM）、准谐振（QR）反激式变换器以及双管正激续流整流（图1和图2）。 FAN6204采用了独创的线性预测时序控制技术，用于决定 SR MOSFET 的开通与关断时序。该控制技术只需检测变压器绕组电压和输出电压，无需检测 MOSFET的电流，因此可以实现抗噪性。另外，本技术无需来自原边的通讯信号，因而减少了外部器件数量，简化了PCB布局。在异常测试条件下，由于线性预测时序（LPT）控制和因果時序功能 (Causal Function) 有可能无法保证安全运行，因此应该使用一些保护功能。在负载变化的测试条件下，本芯片使用了错误因果时序保护 (Fault Causal Timing Protection) 、栅極扩展限制保护（ Gate Expand Limit Protection ）和 RES 瞬降保护（ RES Dropping Protection ）。当LPC/RES电阻损坏时，LPC/RES管脚悬浮 / 短接保护可以防止 SR 控制器的错误操作。另外，内部过温度保护（ OTP ）和 VDD 过电压保护（VDD OVP ）可使FAN6204避免在高温和输出过电压条件下的不可控问题。本芯片使用了一种绿色模式功能来提高空载和轻载下的效率。在绿色模式下， SR 控制器关断 SR 的驱动电路来降低工作电流，保证在轻载条件下功率损耗维持在一个较低水平。
(2)
R4 VOUT 4 R3 R4
(7)
再考虑到分压电阻和内部电路的公差，分压比 (ScaleDown Ratio)K的取值为5~5.5。
R4 1 VOUT 4 R3 R4
K
(3)
R2 R4 R1 R2 R3 R4
Body diode of SR MOSFET Body diode of SR MOSFET Primary MOSFET
4
RES
VRES
R4
GND
6
AGND
Figure 2. 双管正激续流整流的典型应用电路
© 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 7/29/11

AN-6204
APPLICATION NOTE
( 设计范例 ) 假设在一反激系统中的输入线电压的最
VDD部分当输出端电压VO控制在5V和24V之间时，可以将VO用作 FAN6204 的 VDD 。如果 VO 不在这个范围，则可使用变压器的一个额外绕组给VDD提供能量。图5给出了电路简图。为了阻止 VDD 电源电压的变化，可以使用稳压器或者电压钳位元件，比如使用稳压二极管将 VDD 钳位在一个适当的范围。
VOUT
Q2 Q1 D1
R1
LPC 8 8 5 5 VDD 3 3 GATE RES 7 7
R3
Clamping Circuit
FAN6204 FAN6204
4 4 6 6
大值（ VIN.MAX ）和最小值（ VIN. Min ）分别为373V 和 127V ；输出电压是 19V ；变压器匝比（n ）是4.75 。根据方程（1）可以得到LPC的分压比最大值为：
NBOOST 60T D5
100kΩ RHV
41T RCLAMP CCLAMP 51kΩ NP
6T NS
0.83 V R2 IN .MIN 0.05VOUT 0.3 R1 R2 n
(5)
应该考虑LPC和RES（1~4V）的线性工作范围，则：
V R2 IN .MAX 4 R1 R2 n
(6)
另一方面，需要考虑 LPC 和 RES （ 1~4V ）的线性工作范围，则:
V R2 ( IN .MAX VOUT ) 4 R1 R2 n
Q1 R1
VIN
IDS
n:1
ISR
VOUT
Q2
VDET
GATE VDD
3 5
R3
VLPC
R2
LPC
8
FAN6204
4 6
RES
7
VRES
R4
GND
AGND
Figure 1. 反激式变换器的典型应用电路
VIN Q1
VDET
Q3
VOUT
GATE VDD Q2 R1 R2
3 5 7
R3
VLPC LPC 8 FAN6204
4
AN-6204
APPLICATION NOTE
设计范例
本节给出了采用 FAN6921 时 90W （ 19V/4.74A ）适配器的设计实例。 PFC 输出电压在低输入交流电压时为 250V ，高输入交流电压时为 400V 。根据技术规格，所有的关键器件都经过了处理，并且给出了最终的实验结果。
VGS
Primary MOSFET Synchr onous Rectifier MOSFET
VDET
R2 R4 K R1 R2 R3 R4
Body diode of SR MOSFET Body diode of SR MOSFET
VIN/n
(4)
VOUT
VGS
Primary MOSFET Synchr onous Rectifier MOSFET
APPLICATION NOTE
印刷电路板的布局
图6 给出了 FAN6204 在某一变换器中的原理图。良好的 PCB布局可以提高电源系统效率、最大限度抑制EMI，并且防止电源在浪涌/静电释放试验中的损坏。 IC侧： LPC和RES管脚的参考地直接连接到IC的AGND。 (轨迹1) IC 的 GND 和 AGND 管脚应该通过一条短粗的布线或者较宽区域的布线连在一起。（轨迹 1 和轨迹 2） VDD 的参考地应该连接到 IC的这个接地区域，然后VDD的参考地连接到COUT的地。（轨迹3） LPC和RES的布线应该远离磁性元件。系统侧：由于轨迹4是二次侧的功率环路，因此越短越好。在次级，Y-CAP应该通过一条粗线连接到COUT的地（轨迹5）。