实验三 8位乘法器的设计
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实验三8位乘法器的设计
一、实验目的
1)了解8位乘法器的工作原理
2)熟悉MAX+plusII软件的基本使用方法
3)熟悉EDA实验开发的基本使用方法
4)学习VHDL程序中数据对象，数据类型，顺序语句，并行语句的综合使用
二、实验内容
设计一个由8位加法器构成的以时序逻辑方式设计的8位乘法器。其乘法原理是：乘法通过逐项位移相加原理来实现，以被乘数的最低位开始，若为1，则乘数左移后与上一次和相加，若为0，左移后以全零相加，直至被乘数的最高位。
三、实验条件
开发软件：MAX+plus II 9.23 Baseline
硬件设备：装有windows7的pc机
四、实验设计
1)系统的原理框架图
2)VHDL源程序
andarith.vhd源代码
library ieee;
use ieee.std_logic_1164.all;
entity andarith is
port(abin:in std_logic;
din:in std_logic_vector(7 downto 0); dout: out std_logic_vector(7 downto 0)); end entity andarith;
architecture art of andarith is
begin
process(abin, din)is
begin
for i in 0 to 7 loop
dout(i)<=din(i)and abin;
end loop;
end process;
end architecture art;
arictl.vhd源代码
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity arictl is
port(clk:in std_logic; start: in std_logic; clkout:out std_logic; rstall: out std_logic; ariend: out std_logic);
end entity arictl;
architecture art of arictl is
signal cnt4b:std_logic_vector(3 downto 0); begin
rstall<=start;
process(clk, start)is
begin
if start='1' then cnt4b<="0000";
elsif clk'event and clk='1'then
if cnt4b<8 then
cnt4b<=cnt4b+1;
end if;
end if;
end process;
process (clk,cnt4b,start)is
begin
if start='0'then
if cnt4b<8 then
clkout<=clk; ariend<='0';
else clkout<='0'; ariend<='1';
end if;
else clkout<=clk; ariend<='0';
end if;
end process;
end architecture art;
sreg8b.vhd
library ieee;
use ieee.std_logic_1164.all;
entity sreg8b is
port (clk: in std_logic;
load: in std_logic;
din: std_logic_vector(7 downto 0);
qb: out std_logic);
end entity sreg8b;
architecture art of sreg8b is
signal reg8:std_logic_vector(7 downto 0); begin
process(clk, load)is
begin
if clk'event and clk='1'then
if load='1'then reg8<=din;
else reg8(6 downto 0)<=reg8(7 downto 1); end if;
end if;
end process;
qb<=reg8(0);
end architecture art;
reg16b.vhd
library ieee;
use ieee.std_logic_1164.all;
entity reg16b is
port(clk: in std_logic;
clr: in std_logic;
d: in std_logic_vector(8 downto 0);
q: out std_logic_vector(15 downto 0));
end entity reg16b;
architecture art of reg16b is
signal r16s: std_logic_vector(15 downto 0);
begin
process(clk,clr)is
begin
if clr='1'then r16s<="0000000000000000";
elsif clk'event and clk='1'then
r16s(6 downto 0)<=r16s(7 downto 1);
r16s (15 downto 7)<=d;
end if ;
end process;
q<= r16s ;
end architecture art;
Adder8b.vhd源代码
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder8b is
port( c8:in std_logic;
a8:in std_logic_vector(7 downto 0);
b8: in std_logic_vector(7 downto 0);
s8: out std_logic_vector(7 downto 0);
co8: out std_logic
);
end entity adder8b ;
architecture art of adder8b is
component adder4b is
port(c4: in std_logic;
a4: in std_logic_vector(3 downto 0);
b4: in std_logic_vector(3 downto 0);
s4: out std_logic_vector(3 downto 0);
co4: out std_logic
);
end component adder4b;
signal sc:std_logic;
begin
u1:adder4b
port map(c4=>c8,a4=>a8(3 downto 0),b4=>b8(3 downto 0), s4=>s8(3 downto 0),co4=> sc);