High-K和Low-K电介质材料

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High-k与Low-k的分析

High-k与Low-k的分析近十年来CPU业者每发表1款新主打CPU，就会顺带标榜该芯片所用的制程技术，最初只标榜尺寸缩密性制程，而近五年来更是强调各种新材质性制程，倘若不去了解新材质制程的意义，那么也将愈来愈不了解新CPU的价值意义……过去IBM微电子发表Low k Dielectric（低介电质绝缘，或称：低介电常数绝缘）制程技术时，人们没有投入太多的注目，而今Intel在45nm制程的芯片产品发表后，也连带在45nm 制程内使用了High k/Metal Gate（高介电质金属闸极）技术，使的最近笔者经常被人问及：Low k制程与High k制程到底有何不同？问此问题的人因为被名称所迷惑，认为Low k与High k是相互矛盾的技术，且半导体业者都纷纷标榜Low k、High k等新制程技术能为芯片电路带来新的提升效益，因此迷惑也就加深，所以以下本文将对此进行更多讨论。

一、LOW-K在集成电路内部，由于ILD(Inter Layer Dielectrics，层间电介质)的存在，导线之间就不可避免地存在分布电容，或者称之为寄生电容。

分布电容不仅影响芯片的速度，也对工作可靠性构成严重威胁。

从电容器容量计算公式中我们可以看出，在结构不变的情况下，减少电介质的k值，可以减小电容的容量。

因此，使用low-k电介质作为ILD，可以有效地降低互连线之间的分布电容，从而可使芯片总体性能提升10％左右。

(1)Low-k的作用集成电路的速度由晶体管的栅延时(Gate Delay)和信号的传播延时(Propagation Delay)两个参数共同决定，延时时间越短，信号的频率越高。

栅延时主要是由MOS 管的栅极材料所决定，使用high-k材料可以有效地降低栅延时。

传播延时也称为RC 延时(RC delay)，R是金属导线的电阻，C是内部电介质形成的电容。

RC 延时的表达式为：TRC=ρε(L2/TD) 注:公式中ρ为金属的电阻率，ε(也记做k)是电介质的介电常数，L 为导线长度，T 是电介质厚度，D为金属导线厚度。

高k材料

高k栅介质材料研究黄玲10092120107 摘要在传统的MOSFET中，栅介质材料大部分采用二氧化硅，因为SiO2具有良好的绝缘性能及稳定的二氧化硅—硅衬底界面。

然而对于纳米线宽的集成电路，需要高介电常数（高k）的栅极介质材料代替二氧化硅以保持优良的漏电性能。

这些栅极候选材料必须有较高的介电常数，合适的禁带宽度，与硅衬底间有良好界面和高热稳定性。

此外，其制备加工技术最好能与现行的硅集成电路工艺相兼容。

关键字：高介电常数；MOSFET；1.引言过去的几十年中，SiO2容易在硅表面氧化生长，工艺简，单热稳定性好，作为栅介质材料，是一种非常重要的绝缘材料。

但随着集成电路规模的不断增大，需要减小器件的特征尺寸。

对于给定的电压，增加电容量有两种途径:一种是减小栅绝缘层的厚度，一种是增加绝缘层的介电常数。

对于SiO2来说，由于其介电常数较小，只有3. 9 ，当超大规模集成电路的特征尺寸小于0. 1μm时，SiO2绝缘层的厚度必须小于2nm ，这时，无法控制漏电流密度。

而且，当SiO2薄膜的厚度小于7nm 时，很难控制这么薄SiO2薄膜的针孔密度。

另外SiO2难以扩散一些电极掺杂物，比如硼。

薄氧化层带来的另一个问题是，因为反型层量子化和多晶硅栅耗尽效应的存在，使等效电容减小，导致跨导下降。

因此，有必要研究一种高介质材料（又叫高- k 材料）来代替传统的SiO2。

2.1传统晶体管结构的瓶颈及转变方向进入21 世纪以来集成电路线宽进一步缩小，SiO2栅介质层厚度成为首个进入原子尺度的关键参数，由公式C=ε *ε0* A/Tox，为了保证CMOS 晶体管的功能特性，增大C，最直接的做法是降低二氧化硅的厚度Tox，然而当Tox很小时会产生以下问题:（1）漏电流增加，使MOSFET功耗增加。

（2）杂质扩散更容易通过SiO2栅介质薄膜，从栅极扩散到衬底，影响MOSFET参数，如阈值电压（3）因为反型层量子化和多晶硅栅耗尽效应的存在，使等效电容减小，导致跨导下降。

高K介质介绍

HfTaO和HfTaON：加入Ta，特性优化明显
在HfTaO的基础上进一步引入N，可以有更优的性能，是未来的发展趋势，只是这样做使得工艺的复杂度大幅度提高，不利于量产。
SiON/高K介层叠结构：
新型高K材料存在的问题：高K材料的优化仍然是有上升空间的，关键看工艺如何控制，以及选择何种元素的加入。
高K栅介质的制备工艺：PVD,MOCVE,ALD
下图可以看出，几种特性之间的关系，也就是说针对工艺，需要有取舍的选择一定的AL含量来达到一定的目的，同时放弃一定的性能。
HfSiO和HfSiON：硅的引入还是有很多优点的，但降低了EOT，无法满足进一步缩小器件尺寸的要求，只能满足过渡期的要求，要进一步应用到更小的线宽工艺上，需要更厚的电介质厚度，即需要更高的K值材料。
高K介质介绍
最近很忙，然后又有很多事情，今天又去了上海中心，所以，好像更新的东西变少了，我还是接着更新吧！上两张今天的成果照片好了，大家欣赏一下，嘿嘿！
手机比较渣，大家随便看看得了哈！
最近也没闲着，看了篇文章，介绍给大家了解了解好了，也大概能知道高K栅介质现在大致的进展情况。
稍早一些的IC工艺技术发展蓝图，那时候只到2013年，不过轨迹基本差不多。
对于上面的负面影响，解决方案就是高K材料的选择，即选择高介电常数的介质，则以保证栅介质厚度足够厚，防止隧穿电流，同时选择使用金属栅以克服多晶硅的耗尽效应，消除硼穿透效应。
近几年研究的高K材料的焦点主要集中在以下几种材料上，现在我们知道Hf基材料已经应用在了商业芯片上，但是同时研究其它材料同样重要，因为我们不知道什么时候Hf基材料又不适合了，或者其它材料是否有比Hf基材料更优的性能，这些都是要我们去进一步研究的东西。
ALD被广泛使用：

光电晶体管的高k介电层 -回复

光电晶体管的高k介电层-回复什么是光电晶体管？光电晶体管（phototransistor）是一种光敏器件，基本结构是一个由三个或四个电极组成的晶体管，其中一个或两个电极被曝光于光源之下。

光电晶体管能够根据光线的强弱来调节电流或电压的大小。

它的原理与普通晶体管类似，但具有更高的灵敏度和响应速度。

高k介电层在光电晶体管中的作用是什么？高k介电层（high-k dielectric layer）是光电晶体管中的重要组成部分。

它位于基底层与栅极之间，起到隔离电子运动的作用。

高k介电层具有较高的介电常数（k值），使电场分布更均匀，从而提高了晶体管的性能和效能。

1. 提高灵敏度和信噪比：高k介电层能够增强电子-光子转换的效率，提高光电晶体管的灵敏度。

通过减小信号与噪声之间的差距，高k介电层能够提高光电晶体管的信噪比，使其能够更准确地捕捉和转换光信号。

2. 减小功耗和尺寸：由于高k介电层具有较高的介电常数，所以在实际应用中，只需较少的电场强度即可实现同样的电荷存储能力，从而降低功耗。

同时，高k介电层相比于传统材料，具有更小的厚度，能够在相同尺寸下提供更大的电荷存储能力，这有助于减小光电晶体管的尺寸。

3. 提高响应速度：高k介电层的快速充放电能力使得光电晶体管能够更快地响应光信号。

与低k介电层相比，高k介电层有更高的极化效率，提供了更高的输出电荷和更短的响应时间，使得光电晶体管能够更快地转换光信号为电信号。

高k介电层的制备方法和材料选择：高k介电层的制备方法和材料选择对光电晶体管的性能具有重要影响。

1. 制备方法：常见的高k介电层制备方法有物理气相沉积（Physical Vapor Deposition，PVD）、化学气相沉积（Chemical Vapor Deposition，CVD）、溶液法浸涂和热处理等。

不同的制备方法适用于不同的材料和制备条件。

2. 材料选择：常见的高k材料有铝酸铈（CeAlO3）、钛酸钡（BaTiO3）、铌酸锆（ZrNbOx）等。

半导体工艺低介损材料

半导体工艺低介损材料
半导体工艺中，低介电常数材料（low-k）是关键的组成部分。

这些材料用于制造高性能的微处理器和存储器芯片，因为它们可以降低功耗并提高处理速度。

以下是一些常见的低介电常数材料：
氟化硅玻璃（FSG）：这是一种常用的低介电常数材料，其介电常数约为3.9。

FSG具有良好的热稳定性和化学稳定性，因此被广泛用于半导体制造。

氢倍半硅氧烷（HSQ）：HSQ是一种具有极低介电常数（约2.75）的材料，主要用于高性能电子设备。

然而，它的制备过程复杂且成本高昂。

碳氧化硅（SiCOH）：SiCOH是一种有机硅化合物，其介电常数可以在2.5到3.5之间调整。

这种材料的优点是可以通过改变其化学结构来优化其性能。

多孔硅：多孔硅是一种具有高表面积和低介电常数的材料，但其制备过程复杂且难以控制。

聚对二甲苯（parylene）：parylene是一种聚合物材料，其介电常数约为2.65。

由于其优异的绝缘性能和生物相容性，parylene在微电子
学和生物医学领域都有广泛的应用。

以上这些材料都有各自的优点和缺点，选择哪种材料取决于具体的应用需求。

低介电常数 low k

低介电常数low k
低介电常数或称low-K材料是当前半导体行业研究的热门话题。

通过降低集成电路中使用的介电材料的介电常数，可以降低集成电路的漏电电流，降低导线之间的电容效应，降低集成电路发热等等。

介电常数较低的材料主要用于微电子领域，作为金属导线间绝缘的材料。

传统半导体使用二氧化硅作为介电材料，其介电常数约为4。

而真空的介电常数为1，干燥空气的介电常数接近于1。

低介电常数材料的研究与高分子材料密切相关。

随着制程的不断推进，二氧化硅已逐渐接近应用上的极限。

因此，低介电常数材料的研究成为了一个重要的研究方向。

此外，低介电常数材料在实验过程中应尽量减小电压和电流的损伤，同时可以通过表面dep层来保护材料不受损坏。

总的来说，低介电常数材料的研究是一个不断深入的过程，对于推动半导体行业的发展和提升集成电路的性能具有重要的意义。

如需了解更多信息，建议查阅相关论文或咨询专业人士。

high dielectric constant (high-k) gate dielectric materials

High-k Organic,Inorganic,and Hybrid Dielectrics for Low-Voltage OrganicField-Effect TransistorsRocı´o Ponce Ortiz,Antonio Facchetti,*and Tobin J.Marks*Department of Chemistry and the Materials Research Center,Northwestern University,2145Sheridan Road,Evanston,Illinois60208Received March31,2009 Contents1.Introduction2051.1.Theory of Dielectrics2071.1.1.Coherent Tunneling or Quantum Tunneling2071.1.2.Incoherent,Diffusive Tunneling2071.1.3.Hopping Mechanisms2071.1.4.Poole-Frenkel Effect2081.1.5.Schottky Emission2081.2.General Applications2082.Field-Effect Transistors and Organic Field-EffectTransistors2082.1.Dielectric Effects on the Figures-of-Merit ofOFET Devices2092.2.Interface Trapping Effects2113.High-k Dielectric Materials for OFETs2123.1.Inorganic Dielectrics2123.1.1.Aluminum Oxide2133.1.2.Tantalum Oxide2153.1.3.Titanium Dioxide2163.1.4.Hafnium Dioxide2173.1.5.Zirconium Dioxide2183.1.6.Cerium Dioxide218anic Dielectrics2183.2.1.Polymer Dielectrics2183.2.2.Self-Assembled Mono-and Multilayers2253.3.Hybrid Dielectrics2273.3.1.Polymeric-Nanoparticle Composites2273.3.2.Inorganic-Organic Bilayers2323.3.3.Hybrid Solid Polymer Electrolytes2354.Summary2355.Acknowledgments2366.References236 1.IntroductionThe search for high dielectric constant(high-k)gate dielectric materials forﬁeld-effect transistor-enabled(FET) applications has stimulated important research activities in both conventional and unconventional electronics.Although it is not the focus of this Review Article,high-k dielectric technology is tremendously important in the well-established silicon electronics industry.Indeed,the continuous drive to increase integrated circuit performance through shrinkage of the circuit elements requires the Si transistor dimensions to be scaled down according to the well-known Moore’s law.1Historically,this goal has been achieved by developing newoptical lithography tools,photoresist materials,and criticaldimension etch processes.However,it is now clear that,despite advances in these crucial process technologies,deviceperformance in scaled devices will be compromised becausethe traditional materials used for transistor and capacitorfabrication(silicon and silicon dioxide)have reached theirfundamental material limits.2Therefore,continuing scalingwill require the introduction of new materials.3One of thekey materials challenges,which if not addressed couldinterrupt the historical Moore’s law progression,is thereplacement of the silicon dioxide layer with new gatedielectric materials.4Despite a number of excellent proper-ties,SiO2suffers from a relatively low dielectric constant(k )3.9).Because high gate dielectric capacitance is necessary to enable the required drive currents for submicrometerdevices and because capacitance for aﬁlm is proportionalto k and inversely proportional to gate dielectric thickness(d),the SiO2layer thickness must be reduced accordinglyto scaled device dimensions.Because of the large band gapof SiO2(∼9eV)and low density of traps and defects in thebulk,the leakage current through the dielectric layer isnormally very low.However,for ultrathin SiO2ﬁlms this isno longer the case.5When the physical thickness betweenthe gate electrode and doped Si substrate becomes thinnerthan∼2nm,according to fundamental quantum mechanicallaws,the tunneling current increases exponentially with*To whom correspondence should be addressed.E-mail:a-facchetti@ (A.F.);t-marks@(T.J.M.).Rocı´o Ponce Ortiz was born in Marbella(Spain)in1980.She studied at the University of Malaga where she obtained her degree in Chemical Engineering in2003and a Ph.D.in Chemistry in2008working on vibrational spectroscopy,electrochemistry,and quantum-chemical calcula-tions of oligothiophene derivatives in Prof.Lo´pez Navarrete’s group.In 2008,she joined Prof.Tobin J.Marks’group at Northwestern University as a postdoctoral researcher.Dr.Ponce Ortiz has published25research articles.Her current research interest is molecular electronics for organic thin-ﬁlm transistors.Chem.Rev.2010,110,205–23920510.1021/cr9001275 2010American Chemical SocietyPublished on Web10/23/2009decreasing oxide thickness and dominates the leakage current.For silicon dioxide-based capacitors,the leakage current at 1V increases from ∼10-5to ∼10A/cm 2when the dielectric layer thickness decreases from ∼3to ∼1.5nm,which is a 107×current increase for a thickness change of only 2×.6,7These high leakage currents will invariably compromise the device performance as well as dissipate large amounts of power.It is therefore obvious that SiO 2as deposited with current methods will very soon reach its limit as a gate dielectric for all kinds of low power applications.Although higher power dissipation may be tolerable with some high-performance processors,it quickly leads to problems for mobile devices.Eventually,another major limitation for thin oxides may come from their reduced lifetimes.In addition,the increased operation temperatures considerably increase the gate leakage through thin oxide layers and reduce lifetimes further.8The oxide reliability thus remains one of the other major issues in CMOS scaling.9It is therefore clear that to meet next-generation device requirements,the solution is represented by using thicker dielectric layers of materials having permittivities higher than that of SiO 2.7,10,11For completely different applications,high-k gate dielec-trics are needed in unconventional electronic devices based on organic FETs.As we will describe in detail in the following sections,this research ﬁeld is also known as “organic”or “printed”electronics.Research and development on organic transistors began in the 1980s with the goal of fabricating electronic circuits by printing all FET materials components instead of deﬁning them using photolithography.If successful,this technology would allow inexpensive,low-temperature,and large area device processing as well as enable new device functions.Thus,simple electronic devices such as radiofrequency identiﬁcation (RFID)tags and sensors could be fabricated on plastic foils and integrated with commercial item packages in the supply chain.12–14Other important printed electronic products include backplane circuitries,which can be used for the fabrication of ﬂexible/bendable displays for e-paper and ﬂexible computers.There are two key interconnected challenges in this area.The ﬁrstis represented by the limited performance,particularly carrier mobility,of FETs based on printable organic semiconductors.As compared to single-crystal inorganic semiconductors,charge transport efﬁciency in these materials is reduced by the absence/limited formation of delocalized electronic bands,even in molecular crystals.Because of this limitation,the second key challenge is related to the unacceptably large power (operating voltages)needed to achieve useful FET currents when conventional gate insulators are utilized.A solution to reduce the operating voltages is to enhance gate dielectric capacitance (the drain current scales with the gate capacitance)and,therefore,to employ high-k materials.Finally,note that the dielectric material also indirectly affects FET charge transport characteristics in the semiconductor because of the different charge trapping capacities for holes and electrons.15,16This Review Article focuses on the importance,develop-ment,and implementation of high-k gate dielectrics for modern organic electronics applications.We begin by describing the basics and the theory of dielectrics followed by the operating principles of OFET devices to understand the motivations behind improving the dielectric layer permit-tivity.Next,an overview of the state-of-the-art FET perfor-mance achieved using several classes of organic,inorganic,Antonio Facchetti obtained his Laurea degree in Chemistry cum laude and a Ph.D.in Chemical Sciences from the University of Milan under the supervision of Prof.Giorgio A.Pagani.He then carried out postdoctoral research at the University of California-Berkeley with Prof.Andrew Streitwieser and at Northwestern University with Prof.Tobin J.Marks.In 2002,he joined Northwestern University where he is currently an Adjunct Associate Professor.He is a cofounder and currently the Chief Technology Ofﬁcer of Polyera Corp.Dr.Facchetti has published about 170research articles and holds 30patents.Dr.Facchetti’s research interests include organic semiconductors and dielectrics for thin-ﬁlm transistors,conducting polymers,molecular electronics,organic second-and third-order nonlinear optical materials,and organicphotovoltaics.Tobin J.Marks is the Vladimir N.Ipatieff Professor of Chemistry and Professor of Materials Science and Engineering at Northwestern University.He received his B.S.from the University of Maryland (1966)and Ph.D.from MIT (1971),and came to Northwestern immediately thereafter.Of his 75named lectureships and awards,he has received American Chemical Society Awards in Polymeric Materials,1983;Organometallic Chemistry,1989;Inorganic Chemistry,1994;the Chemistry of Materials,2001;and for Distinguished Service in the Advancement of Inorganic Chemistry,2008.He was awarded the 2000F.Albert Cotton Medal,Texas A&M American Chemical Society Section;2001Willard Gibbs Medal,Chicago American Chemical Society Section;2001North American Catalysis Society Burwell Award;2001Linus Pauling Medal,Paciﬁc Northwest American Chemical Society Sections;2002American Institute of Chemists Gold Medal;2003German Chemical Society Karl Ziegler Prize;2003Ohio State University Evans Medal;2004Royal Society of Chemistry Frankland Medal;2005Bailar Medal,Champaign-Urbana Section of the American Chemical Society,Fellow,American Academy of Arts and Sciences,1993.He is a Member,U.S.National Academy of Sciences (1993);Member,German National Academy of Sciences (2005);Fellow,Royal Society of Chemistry (2005);Fellow Chemical Research Society of India (2008);Fellow,Materials Research Society (2009);2009Herman Pines Award,Chicago Catalysis Society;2009Nelson W.Taylor Award in Materials Research,Penn.State U.;2009von Hippel Medal,Materials Research Society;2010William H.Nichols Medal,ACS New York Section.In 2006,he was awarded the National Medal of Science,the highest scientiﬁc honor bestowed by the United States Government.Marks is on the editorial boards of nine major journals,is the consultant or advisor for six major corporations and start-ups,and has published 935research articles and holds 93U.S.patents.206Chemical Reviews,2010,Vol.110,No.1Ortiz et al.and hybrid high-k dielectrics will be presented.Several strategies that are utilized to enhance not only k but also the gate capacitance by reducing the layer thickness will be covered.In this contribution,self-assembled mono-and multilayer nanodielectrics will also be described.Finally,throughout this Review,we will also discuss theoretical models and recent experimental data analyzing the effect of the k on the charge transport properties of the semiconductor.1.1.Theory of DielectricsInsulators or dielectric materials are characterized by theabsence of charge transport.17Nonetheless,when an electric ﬁeld is applied,these materials undergo a shift in charge distribution.This ﬁeld-induced polarization leads to dielectric behavior and hence to capacitance,C .If we imagine two electrodes separated by a distance d in a vacuum,the application of a voltage between them creates an electric ﬁeld that is described by E )V /d .The charge created per unit area is proportional to this electric ﬁeld,as given by eq 1.The proportionality constant between the applied voltage and the charge is called the capacitance C ,and it is described by eq 2.When a dielectric material in inserted between the electrodes,the capacitance is increased (by a factor of k ,relative dielectric constant)due to the polarizability of the dielectric.In this case,the capacitance is described by eq 3.Electronic conduction in insulating materials has been a subject of considerable interest in the quest to understand charge transport in the thin ﬁlm layers of organic electronic devices.In typical dielectric materials,the electronic states near the Fermi level are usually localized states,and the electron wave functions decay exponentially over a distance known as the localization length.18In constrast,metals have a high,generally uniform density of states,whereas semi-conductors have well-separated conduction and valence bands (separated by a band gap).In a thin ﬁlm transistor,there exist different junctions,metal -insulator,insulator -semi-conductor,and semiconductor -metal,that must be fully understood to optimize the device performance characteristics.In this Review,we will focus exclusively on conductor -dielectric interfaces.As we shall see,several theoretical models have been developed to explain conduction through these junctions.1.1.1.Coherent Tunneling or Quantum TunnelingThese terms relate to the probability of the electron to cross a dielectric barrier of height,φ,and thickness,d .This transport occurs when the dielectric layer thickness is not much greater than the localization length,and then the presence of localized states does not signiﬁcantly alter the conduction process.As a consequence of this situation,the rate of coherent tunneling decreases exponentially with the dielectric thickness,and the current density through the channel is given by the Simmons relation 19of eq 4.Here,J is the current density through the channel (A/cm 2),q is the electron charge,h is Planck’s constant,and m is the electron mass.This equation,which contains only a linear term for a rectangular tunneling barrier,accounts for the exponential dependence of the current density on the thickness (d )and the barrier height (φ)and describes “through space”tunneling.In some cases,electron -phonon interactions or interac-tions of the electron with the orbitals and the electronic structure of the molecule must be taken into account.Theoretical models that account for these interactions have been developed independently by different groups.20In this case,“through bond”tunneling becomes more efﬁcient than “through space”tunneling.Under high electric ﬁelds (exceeding the barrier height),the tunneling rate increases,and Fowler -Nordheim tunneling or “ﬁeld emission”is induced.In this case,it is necessary to modify the rectangular tunneling barrier of the Simmons equation to a triangular shape,as in eq 5,which describes the density current at high E .Here,φFN is the tunneling barrier height,E is the electric ﬁeld (V/cm),and m*is the effective electron mass.This tunneling is basically independent of temperature and also decreases exponentially with distance,19,21as in the Simmons equation.Both equations presented in this section only apply for very thin dielectric layers;22when the thickness increases sufﬁciently,other transport mechanisms must be considered.In fact,these are the mechanisms usually found for transport through self-assembled monolayers.231.1.2.Incoherent,Diffusive TunnelingIn the case of a thick barrier and a high density of localized states,it is necessary to consider the probability of the electron tunneling resonantly between two or more consecu-tive sites that are characterized by potential wells.24The process in this case may be viewed as a series of discrete steps (see Figure 1).25The mechanism can be considered to be independent of temperature and should be in principle the predominant one in the limit of very thick barriers at extremely low temperatures.181.1.3.Hopping MechanismsThese mechanisms are usually thermally activated electron transfers and are dominant at low ﬁelds and moderate temperatures.They follow the classical Arrhenius model (eq 6):Here,σis the conductivity (σ)J /E ),E a is the activation energy,and k B is the Boltzmann constant.This mechanism is similar to the diffusive tunneling process in that the electron travels between one or more sites.The major difference is that the hopping involves nuclear motion.26,27Q )ε0E )ε0V /d(1)C )Q /V )ε0/d(2)C )ε0(k /d )(3)J DT)q 2V h 2d(2m φ)1/2exp[-4πdh (2m φ)1/2](4)J FN)q 3E 28πh φFN exp[-4√2m*3qhE(q φFN )3/2](5)σ)σ0exp(-E ak B T)(6)Dielectrics for Low-Voltage Organic FETs Chemical Reviews,2010,Vol.110,No.1207The electron transfer occurs over the barrier,following the dependence on driving force predicted by Marcus theory.28Because this process involves a series of hopping sites,this thermally activated mechanism does not exhibit the expo-nential distance dependence found in coherent tunneling,but it varies in proportion to d -1.That means that for larger d ,the distance is too great for coherent tunneling,and the electron propagates more efﬁciently by hopping between “hopping”sites.1.1.4.Poole -Frenkel EffectThis approach was developed to account for the effects of “traps”in hopping electron transport.The Poole -Frenkel effect is attributed to the lowering of trapping Coulombic barriers within the molecule by the applied electric ﬁeld,and it explains the electric current in semiconductors.19a,21,29The trapped electrons contribute to the current density according to the Poole -Frenkel equation (eq 7)at high temperatures and intermediate ﬁelds.30In this equation,W is the electric ﬁeld (E )V /d ),σ0is the low ﬁeld conductivity,φB is the Frenkel -Poole barrier height,k is the dielectric permittivity,and k B is the Boltzmann constant.1.1.5.Schottky EmissionThis theory explains the electron transfer mechanism at interfaces.31A Schottky barrier arises from partial charge transfer from one layer to the other at an interface.As a result,a depletion layer or electrostatic barrier is generated.The Schottky emission or thermoionic emission is described by eq 8,and it considers that an electron can be injected through the interface once it has sufﬁcient thermal energy to surmount the potential height.32In eq 8,A*is the modiﬁed Richardson’s constant (A*)120A/cm 2·K 2),n is the diode ideality factor,E is the electricﬁeld,φS is the Schottky barrier height,εis the dielectric permittivity,and k B is the Boltzmann constant.1.2.General ApplicationsDielectrics are widely used in numerous applications.The most fundamental of these is their use as an insulating layer against electrical conduction.To be an insulator,a material must have a large band gap.In that way,there are no states available into which the electrons from the valence band can be excited.Nonetheless,there is always some voltage (the breakdown voltage)that will impart sufﬁcient energy to the electrons to be excited into this band.Once this voltage is surpassed,the dielectric will lose its insulating properties.The other two major applications of dielectrics are in capacitors 33and transistors,both of which are essential components of electronic circuits.The structures of both of these electronic devices are shown in Figure 2.A capacitor is a passive electrical component consisting of a dielectric sandwiched between two conductors.The application of a voltage across this material will,at electric ﬁelds lower than the breakdown ﬁeld of the dielectric (typically several MV/cm),34,35induce a charge separation across the insulating layer forming the capacitor.21,34An ideal capacitor is characterized by a single constant parameter,the capacitance C .Higher C values indicate that more charge may be stored for a given voltage.Nonetheless,real capacitors are not complete insulators and allow a small amount of current ﬂowing through,called leakage current.The OFET structure (Figure 2b)is similar to the capacitor structure but having an additional semiconductor layer (organic in the case of OFETs)in contact with the gate dielectric.2.Field-Effect Transistors and Organic Field-Effect TransistorsFigure 3shows the common device conﬁgurations used in ﬁeld-effect transistors (FETs).These conﬁgurations can be either bottom-gate or top-gate.In the ﬁrstconﬁgurationFigure 1.Schematic energy level diagrams for coherent and diffusive tunneling between two metals M 1and M 2.ΦT is the barrier for coherent tunneling,and R is the potential well depth of N sites spaced apart by a distance a .Reproduced with permission from ref 25.Copyright 2004American Chemical Society.J PF)σ0E exp[-q (φB -√qE /πk )k B T](7)J S )A*T 2exp[-q (φS -n √qE /4πε)k B T](8)Figure 2.Typical structures of (a)organic-based capacitors and (b)organic ﬁeld-effecttransistors.Figure 3.Different structures of organic ﬁeld-effect transistors.L ,channel length;W ,channel width.208Chemical Reviews,2010,Vol.110,No.1Ortiz et al.(bottom-gate),two different structures can be used,bottom-contact or top-contact,depending on the position of the source and drain electrodes.In the case of organicﬁeld-effect transistors(OFETs),the semiconductor layer is an organic material.Because there are a large number of excellent reviews that explain the basis of OFET function in detail,in this Review we will only comment on these aspects brieﬂy.36In principle, the characteristic that best deﬁnes an OFET is the presence of an electricﬁeld that controls and modulates the conductiv-ity of the channel between the source and drain.In the devices shown in Figure3,this electricﬁeld is created by the voltage applied between the source and gate,the gate voltage(V G),but is also dependent on the insulator/dielectric layer.Indeed,a positive/negative gate voltage will induce negative/positive charges at the insulator/semiconductor interface,and the number of these accumulated charges depends on V G and on the capacitance C of the insulator. When no voltage is applied between the source and gate(V G)0),the device is“off”.On increasing both VG and V D(voltage between source and drain),a linear current regime is initially observed at low drain voltages(V D<V G)(eq9) followed by a saturation regime at higher V D values(eq10).In these equations,(I SD)lin is the drain current in the linear regime,(I SD)sat is the drain current in the saturation regime,µis theﬁeld-effect carrier mobility of the semiconductor, W is the channel width,L is the channel length,C is the capacitance per unit area of the insulator layer,V T is the threshold voltage,V D is the drain voltage,and V G is the gate voltage.The above equations indicate that the current between the source and drain can be increased by increasing either V G or V D.Nonetheless,these two parameters can be increased to only a certain extent.As is also evident in eqs9and10, another viable approach to minimizing V G and/or increasing the electrical current is adjusting the capacitance of the gate dielectric,C,as described by eq3.This relationship makes it clear that by either increasing k or decreasing d,the device current is enhanced.Note also that a small d is required in devices using short channel lengths.Typically,d/L e0.1is necessary to ensure that theﬁeld created by V G,and not the lateralﬁeld V D,determines the charge distribution within the channel.37Several groups have adopted the approach of reducing dielectric thickness to realize low-voltage operation OFETs.For example,Vuillaume et al.employed an organic monolayer of carboxyl-terminated alkyltrichlorosilanes(thick-ness range1.9-2.6nm)with linear end groups for the gate dielectric to achieve working voltages below2V.38Halik et al.demonstrated low-voltage organic transistors using self-assembled monolayers(SAMs)of(18-phenoxyoctadecyl)-trichlorosilane,thereby enhancing the mobility of pentacene devices to∼1cm2V-1s-1due to favorable interactions at the semiconductor-dielectric interface.39Finally,Marks et al.studied self-assembled multilayers(SAMTs)grown from solution to achieve very low leakage currents and low operating voltages.40Otherﬁgures-of-merit that must also be optimized in OFET devices are the threshold voltage,I ON/I OFF ratio,and subthreshold slope(S)d V G/d(log I D)),related to how efﬁciently the gateﬁeld modulates the“off”to“on”current and how abruptly the device turns“on”.These parameters depend not only on the nature of the organic semiconductor but also on the chemical structure and dielectric properties of the insulator used,and on the capacitance resulting from interface traps,C IT,as shown in eq11for S.412.1.Dielectric Effects on the Figures-of-Merit of OFET DevicesThere are speciﬁc requirements for gate dielectrics to be used inﬁeld-effect transistors.Apart from a high capacitance, as shown in Section2,high dielectric breakdown strength,42 high levels of purity,high on/off ratios,low hysteresis, materials processability,and device stability are essential.43 To understand the role of the gate dielectric on FET device ﬁgures-of-merit,it is important to take into account that most relevant processes taking place in these devices(charge accumulation and transport)occur in close proximity to the interface between the gate dielectric and the semiconductor layer.This implies that an optimum dielectric-semiconductor interface is fundamental for efﬁcient device function.For example,threshold voltages normally depend strongly on the semiconductor and dielectric used because impurities and charge trapping sites tend to increase this value.It is also quite clear from eqs9and10that V T can be easy modulated by increasing the capacitance of the dielectric,which creates a higher density of charges in the interface at lower voltages. Several authors have also suggested that by controlling the density of semiconductor-dielectric interface states,it should be possible to modulate threshold voltages in organic transistors.44The nature of the insulator interface has also been widely shown to have a great impact on the semiconductor mobil-ity,45as wasﬁrst demonstrated by the deposition of pentacene on SiO2under different growth conditions.46,47The polarity of the dielectric interface can also inﬂuence the quality of the semiconductor layer,affecting local morphology,the density of states(DOS)in the organic semiconductor layer, and,consequently,theﬁeld-effect mobility.The latter effect was extensively analyzed by Veres et al.48on amorphous polymer-based OFETs.In their study,they investigated a number of gate insulators having varying polarity using polytriarylamines(PTAA)and poly(9,9-dioctylﬂuore-co-bithiophene)as the semiconductor materials,and they found that device performance was signiﬁcantly increased when the insulator permittivity was below2.5(see Figure4).The authors ascribed this fact to an increase of carrier localization by electronic polarization in the high-k dielectrics.To explain this phenomenon,Veres et al.proposed the graphical illustration in Figure4b,where the DOS is shown as a Gaussian distribution of localized states.As illustrated in Figure4b,as the dielectric-semiconductor interface becomes more polar,the DOS broadening becomes more severe, leading to more tail states.The authors pointed out that this effect can be only applied to organic materials where the formation of electronic bands is very limited,because random dipoles are unlikely to signiﬁcantly affect the extended states of a wide band.The theoretical approach to this qualitative explanation has been recently developed by Richards et al.49 In their work,the authors calculated the broadening of the DOS due to dipolar disorder using an analytical model as a(I SD)lin)(W/L)C(V G-V T-V D/2)V D(9)(I SD)sat)(W/2L)C(V G-V T)2(10)S)kBTeln(10)(1+C IT/C)(11)Dielectrics for Low-Voltage Organic FETs Chemical Reviews,2010,Vol.110,No.1209。

High-K和Low-K电介质材料

High-K和Low-K电介质材料不同电介质的介电常数k 相差很大，真空的k 值为1，在所有材料中最低；空气的k值为1.0006；橡胶的k值为2.5～3.5；纯净水的k值为81。

工程上根据k值的不同，把电介质分为高k(high-k)电介质和低k(low-k)电介质两类。

介电常数k ＞3.9 时，判定为high-k；而k≤3.9时则为low-k。

IBM将low-k标准规定为k≤2.8，目前业界大多以2.8作为low-k电介质的k 值上限。

一、High-K电介质材料随着集成电路的飞速发展，SiO2作为传统的栅介质将不能满足MOSFET，器件高集成度的要求，需要一种新型High-k材料来代替传统的SiO2。

[1]所谓High-K电介质材料，是一种可取代二氧化硅作为栅介质的材料。

它具备良好的绝缘属性，同时可在栅和硅底层通道之间产生较高的场效应（即高-K）。

两者都是高性能晶体管的理想属性。

High-K电介质材料应满足的要求：：(1) 高介电常数,≤50 nm CMOS 器件要求k >20；(2)与Si 有良好的热稳定性；(3)始终是非晶态，以减少泄漏电流；(4)有大的带隙和高的势垒高度，以降低隧穿电流；(5) 低缺陷态密度/ 固定电荷密度，以抑制器件表面迁移率退化。

[2]最有希望取代SiO2栅介质的高K材料主要有两大类：氮化物和金属氧化物。

1.氮化物氮化物主要包括Si3N4，SiON等。

Si3N4介电常数比SiO2高，作栅介质时漏电流比SiO2小几个数量级，Si3N4和Si的界面状态良好，不存在过渡层。

但Si3N4具有难以克服的硬度和脆性，因此Si3N4并非理想的栅介质材料。

超薄SiOxNy可代替SiO2作为栅介质，这主要是由于SiOxNy的介电常数比SiO2要高，在相同的等效栅氧化层厚度下，SiOxNy的物理厚度大于SiO2，漏电流有所降低。

在SiO2-Si界面附近含有少量的氮，这可以降低由热电子引起的界面退化，而且氮可以阻挡硼的扩散。

关于HKMG——high-K

关于HKMG——high-K metal gate随着晶体管尺⼨的不断缩⼩，HKMG技术⼏乎已经成为45nm以下制程的必备技术。

HKMG制造的晶体管结构和原来的平⾯晶体管相同，只是以High-K绝缘层代替传统的SiO2氧化层，并以⾦属材料栅极代替原来的硅材料栅极，其优势是可以提⾼晶体管的开关速度，并减⼩栅极的漏电流。

High-K绝缘层的等效氧化物厚度（EOT: equivalent oxide thickness）较薄，因此能有效降低栅极电容，晶体管的关键尺⼨能得到进⼀步的缩⼩，管⼦的驱动能⼒也能得到有效的改善。

采⽤High-K绝缘层的晶体管和采⽤硅氧化物绝缘层的晶体管相⽐，在改善沟道载流⼦迁移率⽅⾯稍有不利。

在HKMG⼯艺制作⽅⾯，业内有两种不同的实现⽅式，分别gate-first和gate-last，主要却别是⾦属栅极是在⾼温活化退⽕（high-temperature activation anneals）之前或者之后沉积到晶圆上。

Gate-first的主要⽀持者是以IBM为⾸的芯⽚知道技术联盟Fishkill Alliance，包括英飞凌，NEC，GlobalFoundries，三星，意法半导体以及东芝等公司。

Gate-last主要是Intel在使⽤，Intel在45nm制程开始制作HKMG晶体管时⼀直使⽤gate-last⼯艺；采⽤gate-last⼯艺的还有TSMC，TSMC先是⽀持gate-first⼯艺，但是后⾯可能由于在gate-first⼯艺上感觉有难度，⽽在28nm HKMG制程产品中开始使⽤gate-last⼯艺。

UMC的HKMG⼯艺⽅案较为特殊，在制作NMOS的HKMG结构时使⽤gate-first⼯艺，⽽在制作PMOS时使⽤gate-last⼯艺。

不管是Gate-last还是gate-first都是基于已有的硅栅⾃对准⼯艺的，在栅极的阻挡下通过离⼦注⼊形成源漏极，然后需要经过⾼温退⽕⼯艺，⾦属栅极在经过⾼温⼯艺步骤时可能发⽣剧烈反应和变化。

什么是HighK

什么是HighK由于二氧化硅（SiO2）具有易制性 (Manufacturability)，且能减少厚度以持续改善晶体管效能，因此过去40余年来，处理器厂商均采用二氧化硅做为制作栅极电介质的材料。

High-K究竟是什么神奇的技术？这要从处理器的制造原料说起。

由于二氧化硅（SiO2）具有易制性 (Manufacturability)，且能减少厚度以持续改善晶体管效能，因此过去40余年来，处理器厂商均采用二氧化硅做为制作闸极电介质的材料。

当英特尔导入65纳米制造工艺时，虽已全力将二氧化硅闸极电介质厚度降低至1.2纳米，相当于5层原子，但由于晶体管缩至原子大小的尺寸时，耗电和散热亦会同时增加，产生电流浪费和不必要的热能，因此若继续采用目前材料，进一步减少厚度，闸极电介质的漏电情况势将会明显攀升，令缩小晶体管技术遭遇极限。

为解决此关键问题，英特尔正规划改用较厚的High-K材料(铪hafnium元素为基础的物质）作为闸极电介质，取代沿用至今已超过40年的二氧化硅，此举也成功使漏电量降低10倍以上。

另与上一代65纳米技术相较，英特尔的45纳米制程令晶体管密度提升近2倍，得以增加处理器的晶体管总数或缩小处理器体积，令产品较对手更具竞争力，此外，晶体管开关动作所需电力更低，耗电量减少近30%，内部连接线 (interconnects) 采用铜线搭配 Low-k电介质，顺利提升效能并降低耗电量，开关动作速度约加快 20%。

由于High-k闸极电介质和现有硅闸极并不兼容，英特尔全新45纳米晶体管设计也必须开发新金属闸极材料，目前新金属的细节仍属商业机密，英特尔现阶段尚未说明其金属材料的组合。

目前采用45纳米工艺制造的Penryn处理器在服务器产品线中被命名为Xeon 5400，属于英特尔第二代四核处理器，主频最高3.16GHz，二级高速缓存最高12 MB。

英特尔的演示显示，相比四核英特尔至强5365处理器，在基于SPECjbb2005 发布/测量的数据中，四核英特尔至强x5460系列处理器可在相同平台提供25% (1.25x) 的性能提升。

半导体low k材料

半导体low k材料
半导体低k材料是指在半导体制造过程中用于减少电路中金属线与绝缘层之间的电容和信号延迟的一类材料。

传统的绝缘层材料如二氧化硅在微小尺寸的芯片中会导致信号传输延迟和能耗增加，因此需要寻找低介电常数（低k值）的材料来替代。

这种材料通常被用于制造先进的集成电路和微处理器。

半导体低k材料的选择要考虑到多个因素。

首先是介电常数，即k值，这是衡量材料绝缘性能的重要参数，k值越低表示材料的绝缘性能越好。

其次是材料的机械性能，包括弹性模量、硬度和脆性等，因为在制造过程中需要考虑到材料的加工性能和稳定性。

此外，化学稳定性也是一个重要考量因素，特别是在芯片制造过程中需要进行多道化学处理的情况下。

最后，成本也是一个重要的考量因素，因为材料的选择不仅要考虑性能，还要考虑到成本效益。

在实际应用中，半导体低k材料主要有有机低k材料和无机低k材料两大类。

有机低k材料通常是碳氢化合物的聚合物，具有较低的介电常数和良好的加工性能，但其化学稳定性和机械性能相对较差。

无机低k材料则主要是氧化物、氮化物和氟化物等化合物，具有较好的机械性能和化学稳定性，但通常介电常数略高于有机低
k材料。

总的来说，半导体低k材料在微电子制造中起着至关重要的作用，不仅可以提高芯片的性能，还可以降低功耗和延迟，因此对于半导体行业来说，低k材料的研发和应用是一个重要的课题。

高k材料

高k栅介质材料研究黄玲10092120107 摘要在传统的MOSFET中，栅介质材料大部分采用二氧化硅，因为SiO2具有良好的绝缘性能及稳定的二氧化硅—硅衬底界面。

然而对于纳米线宽的集成电路，需要高介电常数（高k）的栅极介质材料代替二氧化硅以保持优良的漏电性能。

这些栅极候选材料必须有较高的介电常数，合适的禁带宽度，与硅衬底间有良好界面和高热稳定性。

此外，其制备加工技术最好能与现行的硅集成电路工艺相兼容。

但随着集成电路规模的不断增大，需要减小器件的特征尺寸。

对于给定的电压，增加电容量有两种途径:一种是减小栅绝缘层的厚度，一种是增加绝缘层的介电常数。

而且，当SiO2薄膜的厚度小于7nm 时，很难控制这么薄SiO2薄膜的针孔密度。

另外SiO2难以扩散一些电极掺杂物，比如硼。

薄氧化层带来的另一个问题是，因为反型层量子化和多晶硅栅耗尽效应的存在，使等效电容减小，导致跨导下降。

因此，有必要研究一种高介质材料（又叫高- k 材料）来代替传统的SiO2。

半导体器件中的low-k技术

半导体集成电路中的low-k技术摘要：随着芯片集成度的不断提高，RC时延、串扰噪声和功耗等越来越成为严重的问题。

low-k(低介电常数)技术在这样的背景下产生并逐渐应用到集成电路工艺中。

low-k材料代替SiO2能够进一步提高芯片的速度，但在low-k材料带来巨大技术优势的同时，也带来了一些技术性难题。

研究新型low-k材料并提升其相应的性能，将极大的促进集成电路的发展。

关键词: 集成电路 low-k技术低介电常数多孔材料1 前言随着超大规模集成电路(VeryLarge Scale Integration,VLSI)的高速发展，芯片的集成度不断提高，特征尺寸不断减小。

金属互连的多层布线导致金属导线的电阻、线间电容和层间电容增大，从而使RC延迟时间、串扰噪声和功耗等增加，这些问题成为集成电路进一步发展的制约因素[1,2]。

为了解决上述问题，提高芯片的速度，一方面用采用Cu金属互连线代替Al金属，减少电阻(Cu电阻率为1.75 ×10-8Ω·m，Al电阻率2.83 ×10-8Ω·m)。

另一方面用low-k电介质(k<3)代替SiO2(k=3.9~4.2)，降低金属互连层间绝缘层的介电常数k[3,4]。

90 nm工艺要求k = 3.0～2.9；65 nm 工艺要求k = 2.8～2.7；45 nm 工艺要求k = 2.6～2.5[3]；32nm及以下工艺要求k值在2.4之下[5]。

因此，low-k 技术已经成为集成电路领域的重点研究内容之一。

2 low-k技术的优势图1 分布电容示意图low-k技术就是就是寻找介电常数(k)较小的材料作为芯片内部电路层之间的绝缘介质ILD(Inter Layer Dielectrics，层间电介质)，防止各层电路的相互干扰，以提升芯片的稳定性和工作频率。

集成电路的速度由晶体管的栅延时和信号的传播延时共同决定，使用high-k材料可以有效地降低栅延时。

半导体highk介质

半导体highk介质半导体highk介质：突破半导体技术瓶颈的关键随着科技的不断进步，半导体技术在现代社会中扮演着至关重要的角色。

然而，随着电子设备的不断发展和功能的不断增强，传统的半导体材料面临着一系列的挑战。

其中之一就是电子绝缘层材料的性能限制。

为了克服这一问题，科学家们引入了半导体highk介质，这一技术的出现为半导体技术的发展带来了新的希望。

半导体highk介质是一种高介电常数的材料，用于替代传统的二氧化硅（SiO2）作为电子绝缘层材料。

传统的SiO2材料在绝缘层中起到了隔离电子的作用，但随着器件尺寸的不断缩小，SiO2材料的绝缘性能逐渐变差。

这是因为当绝缘层的厚度减小到纳米级别时，SiO2材料会出现隧穿效应，导致电子泄漏，从而影响器件的性能。

半导体highk介质的引入解决了这一问题。

高介电常数意味着这种材料在相同厚度下可以提供更好的绝缘性能。

这使得半导体器件可以在更小的尺寸下工作，从而实现更高的集成度和更低的功耗。

此外，半导体highk介质还具有较高的热稳定性和较低的介电损耗，使得器件在高温环境下能够更好地工作。

半导体highk介质的研究和应用已经取得了显著的进展。

目前，最常用的半导体highk介质是氧化铝（Al2O3）、氧化钇（Y2O3）和氧化铈（CeO2）等。

这些材料具有良好的绝缘性能和热稳定性，已经成功应用于各种半导体器件中，如晶体管、电容器和存储器等。

然而，半导体highk介质的应用仍然面临一些挑战。

首先，高介电常数的材料通常具有较高的介电损耗，这会导致信号传输的能量损失。

其次，高介电常数的材料在制备过程中往往需要较高的温度，这可能会对器件的性能和稳定性产生负面影响。

此外，半导体highk介质的制备工艺也需要进一步优化，以提高材料的质量和一致性。

为了克服这些挑战，科学家们正在不断探索新的半导体highk介质材料和制备工艺。

例如，研究人员正在研究具有更低介电损耗的高介电常数材料，以提高器件的性能。

半导体器件中的low-k技术

半导体集成电路中的low-k技术摘要：随着芯片集成度的不断提高，RC时延、串扰噪声和功耗等越来越成为严重的问题。

low-k(低介电常数)技术在这样的背景下产生并逐渐应用到集成电路工艺中。

low-k材料代替SiO2能够进一步提高芯片的速度，但在low-k材料带来巨大技术优势的同时，也带来了一些技术性难题。

研究新型low-k材料并提升其相应的性能，将极大的促进集成电路的发展。

为了解决上述问题，提高芯片的速度，一方面用采用Cu金属互连线代替Al金属，减少电阻(Cu电阻率为1.75 ×10-8Ω·m，Al电阻率2.83 ×10-8Ω·m)。

另一方面用low-k电介质(k<3)代替SiO2(k=3.9~4.2)，降低金属互连层间绝缘层的介电常数k[3,4]。

90 nm工艺要求k = 3.0～2.9；65 nm 工艺要求k = 2.8～2.7；45 nm 工艺要求k = 2.6～2.5[3]；32nm及以下工艺要求k值在2.4之下[5]。

因此，low-k 技术已经成为集成电路领域的重点研究内容之一。

集成电路的速度由晶体管的栅延时和信号的传播延时共同决定，使用high-k材料可以有效地降低栅延时。

高K介质技术介绍1

高k介质技术1概述：从第一块晶体管诞生到现在，微电子经过了长达60多年的发展，发展速度惊人。

在材料方面，第一代半导体技术以Si、Ge材料为代表的，紧接着开发出了化合物半导体，以砷化镓为代表。

近年来又开发出了宽禁带半导体材料，如SiC、ZnSe等，称其为第三代半导体技术。

在工艺方面，超细微加工技术日益完善，使生产达到了亚微米以上的更高的光刻技术。

高质量的超薄氧化层、新的离子注入退火技术、高电导高熔点金属及其硅化物和浅欧姆接触、晶体完整性的大直径芯片、低温加工等一系列技术的发展，极大地提高了芯片的集成度。

在今后的发展总，微电子技术主要有三个主要发展方向：1.继续增大晶圆尺寸和缩小特征尺寸；2.集成电路(IC)将发展成为系统芯片(SOC)；3.微电子技术与其它领域相结合将产生新产业和新学科。

在增大晶圆尺寸和缩小特征尺寸这个技术下，会遇到如下挑战：（1）继续增大晶圆尺寸技术（2）Sub-100nm光刻技术（3）互连线技术（4）新器件结构与新材料。

在寻求新材料方面，主要有以下几个问题：SOI材料、应变硅、高K 介质、金属栅电极。

本文将就高K介质问题展开讨论，并最终得到自己的结论。

2高K介质遇到的问题随着集成电路集成度的不断提高，MOS 器件的特征尺寸进入到纳米领域时，随着器件特征尺寸的不断缩小器件性能逐渐趋近与物理极限。

因此，必须采用新的方法和新的技术提高器件的综合性能。

为了获得良好的器件性能，栅氧化层厚度也要相应的缩小。

对于纳米尺度的MOS 器件，其栅氧化层厚度必须低于3 nm，如此薄的氧化层会导致直接遂穿等一系列问题。

所以，选取高k 材料代替传统的SiO2 层，可以提高栅氧化层的物理厚度，大大减小直接遂穿电流。

高k 材料因其大的介电常数，可实现在SiO2具有相同EOT的情况下，其实际厚度比SiO2大得多，从而解决了SiO2因接近厚度极限而产生的很多问题，成为代替SiO2的热门材料。

但大多数高k材料是离子金属氧化物，这一基本材料特性导致高k材料作为栅介质薄层时会引发很多不可靠问题。

High-k与Low-k的分析

High-k与Low-k的分析近十年来CPU业者每发表1款新主打CPU，就会顺带标榜该芯片所用的制程技术，最初只标榜尺寸缩密性制程，而近五年来更是强调各种新材质性制程，倘若不去了解新材质制程的意义，那么也将愈来愈不了解新CPU的价值意义……过去IBM微电子发表Low k Dielectric（低介电质绝缘，或称：低介电常数绝缘）制程技术时，人们没有投入太多的注目，而今Intel在45nm制程的芯片产品发表后，也连带在45nm制程内使用了High k/Metal Gate（高介电质金属闸极）技术，使的最近笔者经常被人问及：Low k制程与High k制程到底有何不同问此问题的人因为被名称所迷惑，认为Low k与High k是相互矛盾的技术，且半导体业者都纷纷标榜Low k、High k等新制程技术能为芯片电路带来新的提升效益，因此迷惑也就加深，所以以下本文将对此进行更多讨论。

一、LOW-K在集成电路内部，由于ILD(Inter Layer Dielectrics，层间电介质)的存在，导线之间就不可避免地存在分布电容，或者称之为寄生电容。

分布电容不仅影响芯片的速度，也对工作可靠性构成严重威胁。

从电容器容量计算公式中我们可以看出，在结构不变的情况下，减少电介质的k值，可以减小电容的容量。

因此，使用low-k电介质作为ILD，可以有效地降低互连线之间的分布电容，从而可使芯片总体性能提升10％左右。

(1)Low-k的作用集成电路的速度由晶体管的栅延时(Gate Delay)和信号的传播延时(Propagation Delay)两个参数共同决定，延时时间越短，信号的频率越高。

栅延时主要是由MOS 管的栅极材料所决定，使用high-k材料可以有效地降低栅延时。

传播延时也称为RC 延时(RC delay)，R是金属导线的电阻，C是内部电介质形成的电容。

RC 延时的表达式为：TRC=ρε(L2/TD) 注:公式中ρ为金属的电阻率，ε(也记做k)是电介质的介电常数，L 为导线长度，T 是电介质厚度，D为金属导线厚度。

High-K和Low-K电介质材料

High-k与Low-k的分析

高k材料

高K介质介绍

光电晶体管的高k介电层 -回复

半导体工艺低介损材料

低介电常数 low k

high dielectric constant (high-k) gate dielectric materials

High-K和Low-K电介质材料

关于HKMG——high-K

什么是HighK

半导体low k材料

高k材料

半导体器件中的low-k技术

半导体highk介质

半导体器件中的low-k技术

高K介质技术介绍1

High-k与Low-k的分析

推荐-低介电常数材料的特点、分类及应用 精品

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