verilogHDL分频器(奇数分频和偶数分频)
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module clk_div(
//-----------input-----------
iCLK,
div,
//-----------output----------
oCLK
);
//-----------input-----------
parameter WIDE=14;
input iCLK;
input[WIDE-1:0]div;
//-----------output-----------
output oCLK;
wire oCLK_odd;
wire oCLK_even;
assign oCLK=div[0]?oCLK_odd:oCLK_even;
div_odd DUTo (.iCLK(iCLK),.oCLK(oCLK_odd),.div(div)); div_even DUTe (.iCLK(iCLK),.oCLK(oCLK_even),.div(div));
endmodule
// odd
module div_odd(
//--------input--------
iCLK,
div,
//--------output--------
oCLK
);
//--------input--------
parameter WIDE=14;
input iCLK;
input[WIDE-1:0]div;
//--------output--------
output oCLK;
reg outCLK;
/*
=========================== solve 1
=========================== reg cout;
reg[WIDE-1:0] cnt;
initial cnt=0;
wire inCLK;
reg cc;
initial cc=0;
always @(posedge cout)
cc<=~cc;
assign inCLK = iCLK^cc;
always @(posedge inCLK)
begin
if(cnt<(div[WIDE-1:1]))
begin
cnt<=cnt+1;
cout<=1'b0;
end
else
begin
cnt<=0;
cout<=1'b1;
end
end
always @(negedge iCLK)
outCLK <= cout;
assign oCLK=cc;
*/
//======================== //solve 2
//======================== reg[WIDE-1:0] cnt_a;
initial cnt_a=0;
reg[WIDE-1:0] cnt_b;
initial cnt_b=0; reg cout_a;
reg cout_b;
always @(negedge iCLK)
begin
else if(cnt_a<=(div[WIDE-1:1]))
begin
cnt_a=cnt_a+1;
cout_a=1'b1;
end
else if(cnt_a>(div[WIDE-1:1])&&cnt_a<(div[WIDE-1:0]-1))
begin
cout_a=1'b0;
cnt_a=cnt_a+1;
end
else
begin
cnt_a=0;
end
end
always @(posedge iCLK)
begin
if(cnt_b<=(div[WIDE-1:1]))
begin
cnt_b=cnt_b+1;
cout_b=1'b1;
end
else if(cnt_b>(div[WIDE-1:1])&&cnt_b<(div[WIDE-1:0]-1))
begin
cout_b=1'b0;
cnt_b=cnt_b+1;
end
else
begin
cnt_b=0;
end
end
assign oCLK = cout_a&cout_b;
endmodule
//even
module div_even(
//--------input--------
iCLK,
div,
//--------output--------
oCLK
);
//--------input--------
parameter WIDE=14;
input iCLK;
input[WIDE-1:0]div;
//--------output--------
output oCLK;
reg oCLK;
initial oCLK = 1'b0;
reg[WIDE-1:0] cnt;
initial oCLK = 0;
always @(posedge iCLK)
begin
if(cnt<(div[WIDE-1:1]-1))
cnt <= cnt + 1;
else
begin
cnt <= 0;
oCLK <= ~oCLK;
end
end
endmodule
//============================
//testbench
//============================
/*