交通灯控制系统的VHDL代码

--希望大家把有用的代码上传，共同学习交流--traffic_control,红绿灯交通控制library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity traffic_control isport( clk,rst: in std_logic;seg_bit:out std_logic_vector(1 downto 0);decode:out std_logic_vector(7 downto 0);ledcol:out std_logic_vector(2 downto 0); --南北方向控制ledrow:out std_logic_vector(2 downto 0) --东西方向控制);end entity traffic_control;architecture fms of traffic_control istype traffic_state is (s0,s1,s2,s3);type seg_state is(seg_s0,seg_s1);signal cs,ns:seg_state;signal current_state,next_state:traffic_state;signal fdiv:std_logic;signal seg_fdiv:std_logic;signal code:integer range 0 to 30;signal seg_in:integer range 0 to 30;signal countout:integer range 0 to 50;signal longcount1,longcount2,shortcount1,shortcount2:std_logic; begin--50M时钟分频为1Hz,即1s--50,000,000process(clk)variable aa: integer range 0 to 50000000;beginif clk'event and clk='1' then--if aa=49999999 then aa:=0;------需要的赋值if aa=4 then aa:=0;----测试仿真测试值else aa:=aa+1;end if;end if;--if aa<25000000 then fdiv <= '1';----真实值if aa<2 then fdiv <= '1';----------仿真值else fdiv <='0';end if;end process;--分频模块，产生5ms脉冲：250,000/50,000,000 =0.005S process(clk)variable bb: integer range 0 to 250000;beginif clk'event and clk='1' then--if bb=249999 then bb:=0;------需要的赋值if bb=4 then bb:=0;----测试仿真测试值else bb:=bb+1;end if;end if;--if bb<125000 then fdiv <= '1';----真实值if bb<2 then seg_fdiv <= '1';----------仿真值else seg_fdiv <='0';end if;end process;--计数输出后用于数码管显示process(countout)beginif countout>30 then seg_in<=(countout-30);elsif countout>0 then seg_in<=countout;else seg_in<=0;end if;end process;--状态机实现数码管显示十位与各位process(seg_fdiv,rst)beginif rst='0' then cs <=seg_s0;elsif seg_fdiv'event and seg_fdiv='1'thencs<=ns;end if;end process;--根据计数值显示在数码管process(cs,seg_in)begincase cs iswhen seg_s0 => seg_bit(0)<='0';seg_bit(1)<='1'; code<=(seg_in / 10);if cs= seg_s0 then ns<=seg_s1;else ns<=seg_s0;end if;when seg_s1 => seg_bit(0)<='1';seg_bit(1)<='0'; code<=(seg_in rem 10);if cs= seg_s1 then ns<=seg_s0;else ns<=seg_s1;end if;when others=> cs<=seg_s0;end case;end process;--七段码段译码process(code,rst)beginif rst='0' then decode<="10010000";elsecase code is------------------------------ 共阳极共阴极when 0 => decode <= "10010000";-- 0x90;0 0110 1111 -- 0x6fwhen 1 => decode <= "10011111";-- 0x9f;1 0110 0000 -- 0x60when 2 => decode <= "01011000";-- 0x58 2 1010 0111 -- 0xa7when 3 => decode <= "00011001";-- 0x19 3 1110 0110 -- 0xe6when 4 => decode <= "00010111";-- 0x17;4 1110 1000 -- 0xe8when 5 => decode <= "00110001";-- ox31;5 1100 1110 -- 0xcewhen 6 => decode <= "00110000";-- 0x30;6 1100 1111 -- 0xcfwhen 7 => decode <= "10011101";-- 0x9d;7 0110 0010 -- 0x62when 8 => decode <= "00010000";-- 0x10;8 1110 1111 -- 0xefwhen 9 => decode <= "00010001";-- 0x11;9 1110 1110 -- 0xee-- when "1010" => decode <= "00010100";-- 0x14;a-- when "1011" => decode <= "00110010";-- ox32;b-- when "1100" => decode <= "11110000";-- 0xf0;c-- when "1101" => decode <= "00011010";-- 0x1a;d-- when "1110" => decode <= "01110000";-- 0x70;e-- when "1111" => decode <= "01110100";-- 0x74;fwhen others =>null;end case;end if;end process;--40进制计数process (fdiv)variable cc:std_logic_vector(1 downto 0) ;variable count:integer range 0 to 50 ;beginif fdiv'event and fdiv='1' then--if count=0 then count:=50;--else count:=count-1; --计时50sif count=0 then count:=8 ;else count:=count-1;end if;countout<=count; --变量输出进程--if count<20 then longcount1<='1';if count>5 then longcount1<='1';--测试else longcount1<='0';end if;--if count>19 and count<23 then shortcount1<='1';if count>4 and count<6 then shortcount1<='1';--测试else shortcount1<='0';end if;--if count>22 and count<53 then longcount2<='1';if count>2 and count<5 then longcount2<='1';--测试else longcount2<='0';end if;--if count>52 then shortcount2<='1';--测试if count<2 then shortcount2<='1';else shortcount2<='0';end if;end if;end process;--状态机时序进程process(clk,rst)beginif rst='0' then current_state <=s0;elsif clk'event and clk='1'thencurrent_state<=next_state;end if;end process;--1.*绿* 红** 24；2.**黄红*黄15；3. 红** *绿* 42；4. 红*黄**黄；51--状态机控制四种状态装换，通过current_state与计时信号同时决定---默认状态编码process(current_state,next_state,longcount1,longcount2,shortcount1,shortcount2) begincase current_state iswhen s0 => ledcol<="010";ledrow<="100";if current_state=s0 and longcount1='1' then next_state<=s1;else next_state<=s0;end if;when s1 => ledcol<="001";ledrow<="101";if current_state=s1 and shortcount1='1' then next_state<=s2;else next_state<=s1;end if;when s2 => ledcol<="100";ledrow<="010";if current_state=s2 and longcount2='1' then next_state<=s3;else next_state<=s2;end if;when s3 => ledcol<="101";ledrow<="001";if current_state=s3 and shortcount2='1' then next_state<=s0;else next_state<=s3;end if;when others => next_state<=s0;end case;end process;end architecture fms;。