verilog HDL十进制加减法计数器报告
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十进制加减法计数器
1.实验要求
（1）在Modelsim环境中编写十进制加减法计数器程序；
（2）编译无误后编写配套的测试程序；
（3）仿真后添加信号，观察输出结果。
2.设计程序如下
module decade_counter
#(parameter SIZE=4)
(input clock,load_n,clear_n,updown,
input [SIZE-1:0]load_data,
output reg [SIZE-1:0]q
);
always
@(negedge load_n,negedge clear_n,posedge clock)
if (!load_n)
q<=load_data;
else if (!clear_n)
q<=0;
else //clock
if(updown)
q<=(q+1)%10;
else
begin
if(q==0)
q<=9;
else
q<=q-1;
end
endmodule
3.测试程序如下
`timescale 1ns/1ns
module test_decade_counte;
reg clock,load_n,clear_n,updown;
reg [3:0]load_data;
wire [3:0]q;
decade_counter T1(clock,load_n,clear_n,updown,load_data,q);
initial
begin
clock=0;clear_n=0;
#30 clear_n=1;load_n=0;load_data=7;
#30 load_n=1;updown=0;
#300 updown=1;
#300 updown=0;
#300 updown=1;
#300 $stop;
end
always
#10 clock=~clock;
always
@(q)
$display("At time%t,q=%d",$time,q);
endmodule
4．波形如下
5.测试结果如下
# At time 0,q= 0
# At time 30,q= 7
# At time 70,q= 6
# At time 90,q= 5
# At time 110,q= 4
# At time 130,q= 3
# At time 150,q= 2
# At time 170,q= 1
# At time 190,q= 0
# At time 210,q= 9
# At time 230,q= 8
# At time 250,q= 7
# At time 270,q= 6
# At time 290,q= 5
# At time 310,q= 4
# At time 330,q= 3
# At time 370,q= 3 # At time 390,q= 4 # At time 410,q= 5 # At time 430,q= 6 # At time 450,q= 7 # At time 470,q= 8 # At time 490,q= 9 # At time 510,q= 0 # At time 530,q= 1 # At time 550,q= 2 # At time 570,q= 3 # At time 590,q= 4 # At time 610,q= 5 # At time 630,q= 6 # At time 650,q= 7 # At time 670,q= 6 # At time 690,q= 5 # At time 710,q= 4 # At time 730,q= 3 # At time 750,q= 2 # At time 770,q= 1 # At time 790,q= 0 # At time 810,q= 9 # At time 830,q= 8 # At time 850,q= 7 # At time 870,q= 6 # At time 890,q= 5 # At time 910,q= 4 # At time 930,q= 3 # At time 950,q= 2 # At time 970,q= 3 # At time 990,q= 4 # At time 1010,q= 5 # At time 1030,q= 6 # At time 1050,q= 7 # At time 1070,q= 8 # At time 1090,q= 9 # At time 1110,q= 0 # At time 1130,q= 1 # At time 1150,q= 2 # At time 1170,q= 3 # At time 1190,q= 4 # At time 1210,q= 5
# At time 1250,q= 7