[FPGA][Verilog][SPI]简单的读写SPI接口EEPROM-93C46程序

盯着这张鬼时序图看了一天，唉，累 //=============================================================== module spi93c46 (rst, clk, sck, mo, mi, cs, led, write, read); input rst, clk, mi, write, read; output sck, cs, mo; output [7:0] led; reg [7:0] led; reg cs; reg mo; assign sck = clk;
Write19: begin mo <= 0; cs <= 0; end
Read0: cs <= 0; Read1://110+add(7bit) begin cs <= 1; mo <= 1; end Read2: mo <= 1; Read3: mo <= 0;//110 Read4: mo <= 0; Read5: mo <= 1; Read6: mo <= 1; Read7: mo <= 1; Read8: mo <= 1; Read9: mo <= 1; Read10: mo <= 1; Read11: begin mo <= 0; led[7] <= mi; end Read12: led[7] <= mi; Read13: led[6] <= mi; Read14: led[5] <= mi; Read15:
= Read16; = Read17; = Read18; = Read19; = Idle;
//第三个进程，同步时序 always 模块，格式化描述次态寄存器输出 always @ (negedge clk) case(next_state) Idle: cs <= 0; Ewen0: cs <= 0; Ewen1: begin cs <= 1; mo <= 1; end Ewen2: mo <= 0; Ewen3: mo <= 0; Ewen4: mo <= 1; Ewen5: mo <= 1;//以下四个为无用信号 Ewen6: mo <= 0; Ewen7: mo <= 0; Ewen8: mo <= 0; Ewen9: mo <= 0; Ewen10: cs <= 0;
从开始读数据手册，到研究时序，到编写 Verilog 程序，到仿真调试时序，整整 花了有 3-4 天时间。 最后时序已经完全正确， 却读不出任何数据，经过一个晚上的排查才发现是开发 板上的 DI DO SK CS 标号标错了，泪奔~~ 本来我想写一个完整的 SPI 接口出来，想了几天都没有头绪，最后还是写了一个 最简单的写数据读数据的小程序，如果做成接口也勉强可以用。 程序的功能很简单，往地址 0111111 的位置写了 00001111 的数据，地址都还没 有做成接口，固定在程序里面的。 具体用了一个状态机共 53 个状态，每一个状态都是一个 SCK 信号的处理，当然 有分为三个大状态，分别为 ENWR、WRITE、READ 93C46 要首先写 ENWR 信号才能写入数据，具体还得研究数据手册 通过这次 93C46 和上次写 18B20 的经历， 我感觉到数据手册的确是相当的重要的， 需要仔细推敲，分析每一个时序图！下次要做 I2C 接口的 24C02，1、2、3 线就 都学过拉。 当然作为初学者程序是写的那是超级的烂，欢迎拍砖
//状态机 parameter Idle = 32'd1, Ewen0=32'd10, Ewen1=32'd11, Ewen2=32'd12, Ewen3=32'd13, Ewen4=32'd14, Ewen5=32'd15, Ewen6=32'd16,Ewen7=32'd17, Ewen8=32'd18, Ewen9=32'd19, Ewen10=32'd110, Ewen11=32'd111, Write0=32'd20,Write1=32'd21,Write2=32'd22,Write3=32'd23,Write4 =32'd24, Write5=32'd25,Write6=32'd26,Write7=32'd27,Write8=32'd28,Write9 =32'd29, Write10=32'd120,Write11=32'd121,Write12=32'd122,Write13=32'd12 3,Write14=32'd124, Write15=32'd125,Write16=32'd126,Write17=32'd127,Write18=32'd12 8,Write19=32'd129,
Ewen11: cs <= 0; Write0: cs <= 0; Write1: begin cs <= 1; mo <= 1; end Write2: mo <= 0; Write3: mo <= 1;//101+add(7bit) Write4: mo <= 0; Write5: mo <= 1; Write6: mo <= 1; Write7: mo <= 1; Write8: mo <= 1; Write9: mo <= 1; Write10: mo <= 1; Write11: //data 8bit mo <= 0; Write12: mo <= 0; Write13: mo <= 0; Write14: mo <= 0; Write15: mo <= 1; Write16: mo <= 1; Write17: mo <= 1; Write18: mo <= 1;
led[4] <= Read16: led[3] <= Read17: led[2] <= Read18: led[1] <= Read19: begin led[0] <= cs <= 0; end endcase endmodule
mi; mi; mi; mi;
mi;
Read0: next_state Read1: next_state Read2: next_state Read3: next_state Read4: next_state Read5: next_state Read6: next_state Read7: next_state Read8: next_state Read9: next_state Read10: next_state Read11: next_state Read12: next_state Read13: next_state Read14: next_state Read15:
Read0=32'd30, Read1=32'd31, Read2=32'd32, Read3=32'd33, Read4=32'd34, Read5=32'd35, Read6=32'd36, Read7=32'd37, Read8=32'd38, Read9=32'd39, Read10=32'd130, Read11=32'd131, Read12=32'd132, Read13=32'd133, Read14=32'd134, Read15=32'd135, Read16=32'd136, Read17=32'd137, Read18=32'd138, Read19=32'd139; reg[31:0] current_state; reg[31:0] next_state; //第一个进程 always @(posedge clk ) if(rst) current_state <= Idle; else current_state <= next_state;//注意，使用的是非阻塞赋值
= Ewen6; = Ewen7; = Ewen8; = Ewen9; = Ewen10; = Ewen11; = Write0;
= Write1; = Write2; = Write3; = Write4; = Write5; = Write6; = Write7; = Write8; = Write9; = Write10; = Write11; = Write12; = Write13; = Write14;
= Ewen1; = Ewen2; = Ewen3; = Ewen4; = Ewen5;
Ewen5: next_state Ewen6: next_state Ewen7: next_state Ewen8: next_state Ewen9: next_state Ewen10: next_state Ewen11: next_state Write0: next_state Write1: next_state Write2: next_state Write3: next_state Write4: next_state Write5: next_state Write6: next_state Write7: next_state Write8: next_state Write9: next_state Write10: next_state Write11: next_state Write12: next_state Write13: next_state Write14:
next_state Write15: next_state Write16: next_state Write17: next_state Write18: next_state Write19: next_state