基于VHDL语言的EDA实验报告(附源码)
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EDA 实验报告
——多功能电子钟
姓名:张红义
班级：10级电科五班
学号：1008101143
指导老师：贾树恒
电子钟包括：主控模块，计时模块，闹钟模块，辅控模块，显示模块，蜂鸣器模块，分频器模块。
1．主控模块：
主要功能：控制整个系统，输出现在的状态，以及按键信息。
源代码:
libraryieee;
use ieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entity mc is
port(functionswitch,k,set,lightkey: in std_logic;
chose21,setout: out std_logic;
lightswitch:bufferstd_logic;
modeout,kmodeout : out std_logic_vector(1 downto 0);
setcs,setcm,setch,setas,setam,setah:outstd_logic);
end mc;
architecture work of mc is
signalmode,kmode:std_logic_vector(1 downto 0);
signal light,chose21buf:std_logic;
signalsetcount:std_logic_vector(5 downto 0);
begin
process(functionswitch,k,set,lightkey)
begin
iffunctionswitch'event and functionswitch='1' then
mode<=mode+'1';
end if;
iflightkey'event and lightkey='1' then
lightswitch<=not lightswitch;
end if;
if mode="01" thenchose21buf<='0';
else chose21buf<='1';
end if;
ifk'event and k='1' then
if mode="01" or mode="11" then
kmode<=kmode+'1';
end if;end if;
if set='1' then
if mode = "01" then
ifkmode="01" then setcount<="000001";
elsifkmode="10" thensetcount<="000010";
elsifkmode="11" then
setcount<="000100";
elsesetcount<="000000";
end if;
elsif mode = "11" then
ifkmode="01" then
setcount<="001000";
elsifkmode="10" then
setcount<="010000";
elsifkmode="11" then
setcount<="100000";
elsesetcount<="000000";
end if;end if;end if;
if set='0' then
setcount<="00000”;
end if;
setout<=set;
modeout<=mode;
kmodeout<=kmode;
chose21<=chose21buf;
setcs<=setcount(0);setcm<=setcount(1);setch<=setcount(2); setas<=setcount(3);setam<=setcount(4);setah<=setcount(5); end process;end work;
仿真波形：
2. 计时模块
主要功能：记录时间，正常计时。
60进制
libraryieee;
use ieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entity count60 is
port(clk ,clr :in std_logic;
co : out std_logic;
outh :out std_logic_vector(7 downto 4);
outl :out std_logic_vector(3 downto 0));
end count60 ;
architecture work of count60 is
signal bufh:std_logic_vector(7 downto 4);
signal bufl:std_logic_vector(3 downto 0);
begin
process(clk)
begin
ifclr='0' thenbufh<="0000";bufl<="0000";
elsif(clk'event and clk='1')then
if(bufh="0101"and bufl="1001")then co<='1';bufh<="0000";
bufl<="0000";
elsif(bufl="1001")then
bufl<="0000";bufh<=bufh+1;
elsebufl<=bufl+1;
co<='0'; end if;
end if;outh<=bufh;outl<=bufl;
end process;
end work;
24进制
libraryieee;
use ieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entity count24 is
port(clk :in std_logic; co: out std_logic;
outh :out std_logic_vector(7 downto 4);
outl :out std_logic_vector(3 downto 0));
end count24 ;
architecture a of count24 is
signal bufh:std_logic_vector(7 downto 4);
signal bufl:std_logic_vector(3 downto 0);
begin
process(clk)
begin
if(clk'event and clk='1')then
if(bufh="0010"and bufl="0011")then
co<='1';bufh<="0000";bufl<="0000";