(完整版)外文翻译--模拟与数字转换器-精品
外文翻译器
外文翻译器外文翻译器外文翻译器（Machine Translation）是指使用计算机等技术对外文进行自动翻译的工具。
它利用计算机语言处理、人工智能和语言学等多个领域的知识和技术，将源语言（外文）自动转化为目标语言（母语）的过程。
外文翻译器可以帮助人们快速准确地将外文内容转化为自己熟悉的语言，提高工作效率和信息获取能力。
外文翻译器的研究和发展始于上世纪40年代，最早采用的是基于规则的翻译方法，即根据语法规则和词汇库对源语言进行分析和转换。
然而，这种方法存在很多限制，因为语法和词汇库可能无法覆盖所有的语言特点和用法，导致翻译结果不准确和不流畅。
随着计算机技术和人工智能的发展，神经网络机器翻译（Neural Network Translation）成为外文翻译器的主流方法。
这种方法利用大规模平行语料库训练神经网络模型，通过模仿人类学习语言的方式自动学习源语言和目标语言之间的映射关系。
神经网络机器翻译能够更好地处理语法结构和上下文信息，翻译结果更加准确和自然。
除了神经网络机器翻译，外文翻译器还可以采用统计机器翻译（Statistical Machine Translation）等其他方法。
统计机器翻译利用大量的双语语料进行统计分析，找到最佳的翻译候选，然后根据概率模型对其进行排序和选择。
虽然统计机器翻译在一定程度上改善了翻译质量，但由于依赖于大量的语料库，对于某些语言和领域的翻译效果仍然不理想。
当前外文翻译器的发展已经进入了深度学习时代，融合了自然语言处理、深度学习和人工智能的多种技术手段。
深度学习通过建立多层神经网络模型，能够从大规模语料中自动学习和提取特征，进一步提升了翻译质量和效率。
此外，人工智能的发展还带来了一系列辅助工具，如术语提取、句子结构分析和语音识别等，能够进一步提高翻译的准确性和流畅度。
虽然外文翻译器在很大程度上改善了翻译效率和准确性，但由于语言本身的复杂性和多义性，完全依靠机器翻译仍然存在一些局限性。
dsp外文翻译
外文参考文献翻译英文题目 The Breadth and Depth of DSP 中文题目 DSP的广度和深度学院自动化与电气工程学院专业自动化姓名白学文学号 201108536指导教师王思明2015 年 04月 20日DSP的广度和深度数字信号处理是最强大的技术，将塑造二十一世纪的科学与工程之一。
革命性的变化已经在广泛的领域：通信，医疗成像，雷达和声纳，高保真音乐再现，石油勘探，仅举几例。
上述各领域已建立了深厚的DSP技术，用自己的算法，数学，和专门技术。
这种呼吸和深度的结合，使得它不可能为任何一个人掌握所有已开发的DSP技术。
DSP教育包含两个任务：学习一般适用于作为一个整体领域的概念，并学习您感兴趣的特定领域的专门技术。
本章开始描述DSP已在几个不同领域的戏剧性效果的数字信号处理的世界，我们的旅程。
革命已经开始。
1 DSP的根源独特的数据类型，它使用的信号，数字信号处理是区别于其他计算机科学领域。
在大多数情况下，这些信号源于感觉来自现实世界的数据：地震的震动，视觉图像，声波等DSP是数学，算法，并用来操纵这些信号的技术后，他们已被转换成数字形式。
这包括了各种目标，如：加强视觉图像识别和语音生成，存储和传输的数据压缩，等假设我们重视计算机模拟 - 数字转换器，并用它来获得一个现实世界的数据块。
DSP回答了这个问题：下一步怎么办？DSP的根是在20世纪60年代和70年代数字计算机时首次面世。
电脑是昂贵的，在这个时代，DSP是有限的，只有少数关键应用。
努力开拓，在四个关键领域：雷达和声纳，国家安全风险是石油勘探，可以大量资金;太空探索，其中的数据是不可替代的;和医疗成像，可节省生活。
20世纪80年代和90年代的个人电脑革命，引起新的应用DSP的爆炸。
而不是由军方和政府的需求动机，DSP的突然被带动的商业市场。
任何人士如认为他们可以使资金在迅速扩大的领域突然一个DSP供应商。
DSP的市民等产品达到：移动电话机，光盘播放器，电子语音邮件。
外文翻译Numerically Controlled (NC) Machines
本科生毕业设计（论文）外文翻译毕业设计（论文）题目：剪叉式物流液压升降台外文题目：Numerically Controlled (NC) Machines译文题目：数控机床学生姓名：张龙专业：机械设计制造及其自动化指导教师姓名：张凯评阅日期：正文内容小四号字，宋体，行距1.5倍行距。
Numerically Controlled (NC) MachinesWith automatics, programming is expensive and can be justified only for long production runs. However, with machines incorporating feedback control, programs can be provided in the form of punched tapes or punched cards, which are relatively inexpensive to produce compared with disc and drum cams. These machines are known as numerically controlled (NC) machines and can be used economically in small-batch production.As the name implies, numerical control involves control on the basis of numerical information that specifies the relative position of the tool and workpiece. From the block diagram for a machine-tool control system in Fig. 12 it can be seen that two essential elements are added to an otherwise standard machine.The first added element is a means of driving the machine table or toolholder by a servomotor, and hence the motion of the tool or workpiece depends on the signal passed to the servomotor. The second added element is a transducer that continuously monitors the position of the tool or workpiece. The signal from the transducer is compared with that obtained from the tape, and any difference (or error) is converted to analog form, amplified, and used to drive the servomotor until the tool or workpiece position agrees with the position specified by the information on the tape.Fig. 12: Feedback loop for one axis of a machine-tool control system There are two basic types of NC systems: the point-to-point, or positioning, system and the continuous-path, or contouring, system. The point-to-point system would be applied, for example, to a vertical-drilling machine. If control of the two horizontal-motion axes of the table supporting the workpiece is arranged, the machine can be programmed to locate and then drill a specified pattern of holes. In the point-to-point system the path of the tool relative to the workpiece between holes is not important, and only the coordinates of the end point of each motion of the table are specified. The continuous-path system would be applied, for example, to a vertical-milling machine that was required to end mill a complicated shape, such as cam or pocket in a workpiece. In the continuous-path system the position of the tool relative to the workpiece must be continuously controlled while workpieces are being machined.With continuous-path, or contouring, systems the position of the tool relative to the workpiece is specified by a series of coordinates, and the control system is designed to follow a path between these points by interpolation. Some machines follow a straight-line path (linear interpolation); others follow a curved path (circular or parabolic interpolation).Numerical control can be applied to motions along or about any axis,·but two or three-axis control systems are the most common. In general, vertical-milling machines and lathes utilize continuous-path, or contouring control. Vertical-drilling machines jig borers, and small milling machines often use positional control.One sophisticated form of NC machine is known as the machining center. This machine is generally a vertical-milling machine with several axes of control and with automatic tool-changing facilities. The tools are usually held in a rotary magazine, and tool changes are commanded by the punched tape. Thus, with a machining center a complicated workpiece can be completely machined on all faces except the base through a combination of milling, drilling, boring, facing, reaming, and tapping operations. This type of system is therefore most suitable for the batch production of main components.A further refinement of numerical control is adaptive control. This type of system can adapt itself to the prevailing circumstances. These circumstances are measured by the system itself and might include the power required for the machining operation, the wear of the cutting tool or grinding wheel, the forces generated, or the onset of chatter or instability. The system ideally would be designed for automatic adjustment of the feed, speed, or tool position to produce components at minimum cost and within the tolerance specified. Such a system would be very expensive and has not yet found wide application.A relatively simple adaptive control system would automatically vary the cutting speed and feed in such a way as to maximize metal-removal rates without exceeding predetermined cutting forces and power consumption. Systems of this type are relatively inexpensive and can machine under near-optimum conditions.数控机床伴随着自动化产生，只有在长期的生产运行中，编程的价格很昂贵，同时又是合理的。
3D打印外文文献翻译最新译文
3D打印外文文献翻译最新译文3D XXX years。
especially in the field of industrial product design。
The manufacturing of digital product models through 3D printing has e a trend and a hot topic。
With the gradual maturity of -level 3D printing devices。
the rise of the global 3D printing market has been promoted。
According to a research report by Global Industry Analysis Inc。
the global 3D printing market XXX n by 2018.2 The ns of 3D printingThe ns of 3D XXX。
In the medical field。
3D printing has been used to create prosthetics。
implants。
XXX industry。
3D printing has been used to create XXX industry。
3D printing has been used to create unique and XXX possibilities of 3D printing seem endless。
and it is expected to XXX industries.3 The future of 3D printingThe future of 3D printing is promising。
with the potential to transform the way we XXX 3D XXX advance。
数模摸数转换 科技英语
For large numbers of bits (e. g. >14 bits), the number of resistors needed ( 2 N − 1 ) becomes prohibitively large for most practical applications. Also, the power consumption is considerably higher than some of the slightly slower and more exotic solutions.
Figure 2.6 shows the output spectrum of a typical flash converter as determined by taking an FFT (Fast Fourier Transform) of the converter output samples for a pure sine wave input. One thing is immediately apparent.
One example is a modem which turns signals from digital to analog before transmitting those signals over communication lines such as telephone lines that carry only analog signals. The signals are turned back into digital form (demodulated) at the receiving end so that the computer can process the data in its digital format.
外文翻译--数字滤波器的仿真与实现
毕业设计(论文)外文资料翻译院系电子信息工程专业电子信息工程学生姓名班级学号外文出处百度文库附件：1.外文资料翻译译文（约3000汉字）；2.外文资料原文(与课题相关的1万印刷符号左右)。
英文原文The simulation and the realization of the digital filter With the information age and the advent of the digital world, digital signal processing has become one of today's most important disciplines and door technology. Digital signal processing in communications, voice, images, automatic control, radar, military, aerospace, medical and household appliances, and many other fields widely applied. In the digital signal processing applications, the digital filter is important and has been widely applied.1、figures Unit on :Analog and digital filtersIn signal processing, the function of a filter is to remove unwanted parts of the signal, such as random noise, or to extract useful parts of the signal, such as the components lying within a certain frequency range.The following block diagram illustrates the basic idea.There are two main kinds of filter, analog and digital. They are quite different in their physical makeup and in how they work. An analog filter uses analog electronic circuits made up from components such as resistors, capacitors and op amps to produce the required filtering effect. Such filter circuits are widely used in such applications as noise reduction, video signal enhancement, graphic equilibrium in hi-fi systems, and many other areas. There are well-established standard techniques for designing an analog filter circuit for a given requirement. At all stages, the signal being filtered is an electrical voltage or current which is the direct analogue of the physical quantity (e.g. a sound or video signal or transducer output) involved. A digital filter uses a digital processor to performnumerical calculations on sampled values of the signal. The processor may be a general-purpose computer such as a PC, or a specialized DSP (Digital Signal Processor) chip. The analog input signal must first be sampled and digitized using an ADC (analog to digital converter). The resulting binary numbers, representing successive sampled values of the input signal, are transferred to the processor, which carries out numerical calculations on them. These calculations typically involve multiplying the input values by constants and adding the products together. If necessary, the results of these calculations, which now represent sampled values of the filtered signal, are output through a DAC (digital to analog converter) to convert the signal back to analog form.Note that in a digital filter, the signal is represented by a sequence of numbers, rather than a voltage or current.The following diagram shows the basic setup of such a system.Unit refers to the input signals used to filter hardware or software. If the filter input, output signals are separated, they are bound to respond to the impact of the Unit is separated, such as digital filters filter definition. Digital filter function, which was to import sequences X transformation into export operations through a series Y.According to figures filter function 24-hour live response characteristics, digital filters can be divided into two, namely, unlimited long live long live the corresponding IIR filter and the limited response to FIR filters. IIR filters have theadvantage of the digital filter design can use simulation results, and simulation filter design of a large number of tables may facilitate simple. It is the shortcomings of the nonlinear phase; Linear phase if required, will use the entire network phase-correction. Image processing and transmission of data collection is required with linear phase filters identity. And FIR linear phase digital filter to achieve, but an arbitrary margin characteristics. Impact from the digital filter response of the units can be divided into two broad categories : the impact of the limited response (FIR) filters, and unlimited number of shocks to (IIR) digital filters.FIR filters can be strictly linear phase, but because the system FIR filter function extremity fixed at the original point, it can only use the higher number of bands to achieve their high selectivity for the same filter design indicators FIR filter called band than a few high-IIR 5-10 times, the cost is higher, Signal delay is also larger. But if the same linear phase, IIR filters must be network-wide calibration phase, the same section also increase the number of filters and net work complexity. FIR filters can be used the recursive method, not in a limited precision of a shock, and into the homes and quantitative factors of uncertainty arising from the impact of errors than IIR filter small number, and FIR filter can be used FFT algorithms, the computational speed. But unlike IIR filter can filter through the simulation results, there is no ready-made formula FIR filter must use computer-aided design software (such as MATLAB) to calculate. So, a broader application of FIR filters, and IIR filters are not very strict requirements on occasions.Unit from sub-functions can be divided into the following four categories :(1) Low-filter (LPF);(2) high-filter (HPF);(3) belt-filter (BPF);(4) to prevent filter (BSF).The following chart dotted line for the ideals of the filter frequency characteristics :2、MATLAB introducedMATLAB is a matrix laboratory (Matrix Laboratory) is intended. In addition to an excellent value calculation capability, it also provides professional symbols terms, word processing, visualization modeling, simulation and real-time control functions. MATLAB as the world's top mathematical software applications, with a strong engineering computing, algorithms research, engineering drawings, applications development, data analysis and dynamic simulation, and other functions, in aerospace, mechanical manufacturing and construction fields playing an increasingly important role. And the C language function rich, the use of flexibility, high-efficiency goals procedures. High language both advantages aswell as low level language features. Therefore, C language is the most widely used programming language. Although MATLAB is a complete, fully functional programming environment, but in some cases, data and procedures with the external environment of the world is very necessary and useful. Filter design using MATLAB, could be adjusted with the design requirements and filter characteristics of the parameters, visual simple, greatly reducing the workload for the filter design optimization.In the electricity system protection and secondary computer control, many signal processing and analysis are based on are certain types sinusoidal wave and the second harmonics of the system voltage and current signals (especially at D process), are mixed with a variety of complex components, the filter has been installed power system during the critical components. Current computer protection and the introduction of two digital signal processing software main filter. Digital filter design using traditional cumbersome formula, the need to change the parameters after recalculation, especially in high filters, filter design workload. Uses MATLAB signal processing boxes can achieve rapid and effective digital filter design and simulation.MATLAB is the basic unit of data matrix, with its directives expression mathematics, engineering, commonly used form is very similar, it is used to solve a problem than in MATLAB C, Fortran and other languages End precision much the same thing. The popular MATLAB 5.3/Simulink3.0 including hundreds of internal function with the main pack and 30 types of tool kits (Toolbox). kits can be divided into functional tool kits and disciplines toolkit. MATLAB tool kit used to expand the functional symbols terms, visualization modeling simulation, word processing and real-time control functions. professional disciplines toolkit is a stronger tool kits, tool kits control, signal processing tool kit, tool kits, etc. belonging to such communicationsMATLAB users to open widely welcomed. In addition to the internal function, all the packages MATLAB tool kits are readable document and the document could be amended, modified or users through original program the construction of new procedures to prepare themselves for kits.3、Digital filter designDigital filter design of the basic requirementsDigital filter design must go through three steps :(1) Identification of indicators : In the design of a filter, there must be some indicators. These indicators should be determined on the basis of the application. In many practical applications, digital filters are often used to achieve the frequency operation. Therefore, indicators in the form of general jurisdiction given frequency range and phase response. Margins key indicators given in two ways. The first is absolute indicators. It provides a function to respond to the demands of the general application of FIR filter design. The second indicator is the relative indicators. Its value in the form of answers to decibels. In engineering practice, the most popular of such indicators. For phase response indicators forms, usually in the hope that the system with a linear phase frequency bands human. Using linear phase filter design with the following response to the indicators strengths：①it only contains a few algorithms, no plural operations；②there is delay distortion, only a fixed amount of delay; ③the filter length N (number of bands for N-1), the volume calculation for N/2 magnitude.(2) Model approach : Once identified indicators can use a previous study of the basic principles and relationships, a filter model to be closer to the target system.(3) Achieved : the results of the above two filters, usually by differential equations, system function or pulse response to describe. According to this description of hardware or software used to achieve it.4、Introduction of DSPToday, DSP is widely used in the modern techno logy and it has been the key part of many products and played more and mo re important role in our daily life Recently, Northwestern Poly technical University Aviation Microelectronic Center has completed the design of digital signal processor co re NDSP25, which is aiming at TM S320C25 digital signal processor of Texas Instrument TM S320 series. By using top 2dow n design flow NDSP25 is compatible with instruction and interface timing of TM S320C25.Digital signal processors (DSP) is a fit for real-time digital signal processing for high-speed dedicated processors, the main variety used for real-time digital signal processing to achieve rapid algorithms. In today's digital age background, the DSP has become the communications, computer, and consumer electronics products, and other fields based device.Digital signal processors and digital signal processing is inseparably, we usually say "DSP" can also mean the digital signal processing (Digital Signal Processing), is that in this digital signal processors Lane. Digital signal processing is a cover many disciplines applied to many areas and disciplines, refers to the use of computers or specialized processing equipment, the signals in digital form for the collection, conversion, recovery, valuation, enhancement, compression, identification, processing, the signals are compliant form. Digital signal processors for digital signal processing devices, it is accompanied by a digital signal processing to produce. DSP development process is broadly divided into three phases : the 20th century to the 1970s theory that the 1980s and 1990s for the development of products. Before the emergence of the digital signal processing in the DSP can only rely on microprocessors (MPU) to complete. However, the advantage of lower high-speed real-time processing can not meet the requirements. Therefore, until the 1970s, a talent made based DSP theory and algorithms. With LSI technology development in 1982 was the first recipient of the world gave birth to the DSP chip. Years later, the second generation based on CMOS工艺DSP chips have emerged. The late 1980s, the advent of the third generation of DSP chips. DSP is the fastest-growing 1990s, there have been four successive five-generation and the generation DSP devices. After 20 years of development, the application of DSP products has been extended to people's learning, work and all aspects of life and gradually become electronics products determinants.中文翻译数字滤波器的仿真与实现随着信息时代和数字世界的到来，数字信号处理已成为当今一门极其重要的学科和技术领域。
模拟量转化英语
模拟量转化英语
模拟量转换是电子电路中的一个重要环节，它将模拟信号转换为数字信号。
在工程领域中，模拟量转换是非常重要的，因为它使我们能够进行数字信号处理和数据采集。
以下是一些模拟量转换的英语词汇和短语：
1. Analog signal - 模拟信号
2. Digital signal - 数字信号
3. Analog-to-digital converter (ADC) - 模数转换器
4. Sampling rate - 采样率
5. Resolution - 分辨率
6. Input range - 输入范围
7. Output range - 输出范围
8. Conversion time - 转换时间
9. Quantization error - 量化误差
10. Signal-to-noise ratio (SNR) - 信噪比
11. Non-linearity - 非线性
12. Offset error - 偏移误差
13. Gain error - 增益误差
14. Differential non-linearity (DNL) - 差分非线性
15. Integral non-linearity (INL) - 积分非线性
了解这些词汇和短语对于掌握模拟量转换的基础知识以及与其他工程师进行交流和合作非常有帮助。
模数转换器外文翻译
外文资料翻译The 10-bit CMOS ADC (Analog to Digital Converter) is a recycling type device with 8-channel analog inputs. It converts the analog input signal into 10-bit binary codes at a maximum conversion rate of 500KSPS with 205MHZ A/D converter clock. A/D converter operates with on-chip sample-and-hold function and power down node is supported.The LCD controller in the S3C2440 consists of the logic for transferring LCD image data from a video buffer located in system memory to an external LCD driver.The LCD controller supports monochrome,2-bit per pixel(4-level gray scale) or 4-bit per pixel (16-level gray scale) mode on a monochrome LCD,using a time-based dithering algorithm and Frame Rate Control (FRC) method and it can be interfaced with a color LCD panel at 8-bit per pixel (256-level color) and 12-bit per pixel (4096-level color) for interfacing with STN LCD.The LCD controller can be programmed to support different requirements on the screen related to the number of horizontal and vertical pixels, data line width for the data interface, interface timing and refresh rate.FEATURESTFT LCD Displays:Supports 1,2,4 or 8-bpp (bit per pixel) palletized color displays for TFTSupports 16,24-bpp non-palletized true-color displays for color TFTSupports maximum 16M color TFT at 24bit per pixel modeSupports multiple screen sizeTypical actual screen size: 640 * 480 , 320 * 240 , 160 * 160 , and othersMaximum virtual screen size is 4MbytesMaximum virtual screen size in 64K color mode : 2048*1024 and othersA/D converter classification：1. The integral type (such as TLC7135)Integral type AD work principle is the input voltage will convert time (pulse width signal) or frequency (pulse frequency), and then by the timer/counter get digital value. Its advantage is to use a simple circuit can get high resolution, but shortcomings due to a conversion precision dependent on integral time, so the conversion rate is extremely low. At the early stage of the monolithic AD converter is used mostly integral type, now compare successive type has gradually become the mainstream.2. Compare two successive type (such as TLC0831)Successive type AD by a comparison is used and DA converter through successive more logical structure, from the MSB began, in order to every will input voltage and built-in DA converter output carries on the comparison, the n timescomparison and the numerical value of output. The circuit of the scale to belong to medium. Its advantage is high speed, low power consumption, low resolution (<12 a) cheap, but high precision (> twelve) price is very high.3. Parallel comparison of type/parallel comparison type (such as TLC5510)Parallel comparison with multiple comparator type AD, only for a comparison of the conversion, also called flash (fast) type. Due to the conversion rate is extremely high, n a conversion to need 2 n-a comparator and, therefore, the size of a circuit, the price is high, only applies to the video AD converter, particularly high speed of the field. String of parallel comparison between parallel structure type AD on the type and successive comparison between type, the most typical is by 2 n/two parallel type AD converter with DA converter component, with two times the better implement conversion, so called Half flash (Half a fast) type. And into three steps or more steps called AD transform realize classification (Multistep/Subrangling) type AD, and from a conversion timing Angle can also be called as the assembly line (Pipelined) type AD and modern classification type in AD joining in the many transformations number operations and fixed the characteristics of the function. This kind of AD faster than successive type is high, circuit scale than parallel type small.4. Σ-Δ modulated (such as AD7705)Σ-Δ type AD by integrator, comparator, a DA converter and digital filters etc. In principle similar to integral type, the input voltage conversion to time (pulse width) signal, a digital filter to get digital value after the treatment. The digital circuit of the single chip basically easily, so easy to do high resolution. Mainly used for audio and measurement. 5. Capacitance array is successive typeCapacitance array type compare successive AD develops in the built-in DA converter capacitance matrix < /view/10337.htm > way, can also be called charge FenPeiXing again. The general resistor DA converters most resistance value must be consistent, in a single chip generate high precision of the resistor is not easy. If use capacitance array replace resistor, can be made with low cost high precision monolithic AD converter. Recent successive type AD converter is mostly for the capacitance array type.Pressure frequency conversion type (such as AD650)Pressure Frequency conversion model (V oltage-Frequency Converter) is through the indirect conversion way realization of conversion module. Its principle is first the input analog signal conversion into frequency, then use the counter will frequency converted into digital quantity. In theory this AD resolution can be almost unlimited increase, as long as the sampling time can meet the requirements of the output pulse frequency resolution cumulative number of width. Its advantage is high resolution, low power consumption, low price, but need to external counts circuit to complete the AD transform.ARM9E-S as an example to introduce the main ARM9 processor structure and characteristics. Its main characteristics as follows: (1) 32 bit fixed-point RISC processors, improved ARM/Thumb code interweave, enhance sexual on time-multiplier design. Support real-time (real-time) commissioning; (2) in the SRAM of instructions and data, and instructions and data storage capacity of adjustable; (3)in high speed of instructions and data buffers (cache) from 4 K bytes capacity to 1 M bytes); (4) set protection unit (protection unit), very suitable for embedded application segment and memory protection; (5) the AMBA AHB bus interface for peripherals to provide a uniform address and data bus; (6) support external coprocessor, instructions and data bus have simple handshake signaling support; (7) support standard basic logic unit "/view/1520672.htm > scanning test methodology, and support BIST (built-in-self-test); (8) support embedded tracking macro unit, support real-time tracking instructions and data.中文资料翻译10位CMOS ADC （模数转换器）是一个8通道模拟输入的再循环类型设备。
有关A D(模数)转换的外文翻译
中文4819字ICL7135 4 1/2 Digit, BCD Output, A/D ConverterThe Intersil ICL7135 precision A/D converter, with its multiplexed BCD output and digit drivers, combines dual-slope conversion reliability with +1 in 20,000 count accuracy and is ideally suited for the visual display DVM/DPM market. The 2.0000V full scale capability, auto-zero, and auto-polarity are combined with true ratiometric operation, almost ideal differential linearity and true differential input. All necessary active devices are contained on a single CMOS lC, with the exception of display drivers, reference, and a clock.The ICL7135 brings together an unprecedented combination of high accuracy, versatility, and true economy. It features auto-zero to less than 10µV, zero drift of less than 1µV/℃, input bias current of 10pA (Max), and rollover error of less than one count. The versatility of multiplexed BCD outputs is increased by the addition of several pins which allow it to operate in more sophisticated systems. These include STROBE , OVERRANGE , UNDERRANGE , RUN/HOLD and BUSY lines, making it possible to interface the circuit to a microprocessor or UART.Features* Accuracy Guaranteed to+1 Count Over Entire 20000 Counts (2.0000V Full Scale) * Guaranteed Zero Reading for 0V Input* 1pA Typical Input Leakage Current* True Differential Input* True Polarity at Zero Count for Precise Null Detection* Single Reference Voltage Required* Over range and Under range Signals Available for Auto-Range Capability* All Outputs TTL Compatible* Blinking Outputs Gives Visual Indication of Over range* Six Auxiliary Inputs/Outputs are Available for Interfacing to UARTs , Microprocessors, or Other Circuitry* Multiplexed BCD Outputs* Pb-Free Available (RoHS Compliant)Detailed DescriptionAnalog SectionEach measurement cycle is divided into four phases. They are (1) auto-zero (AZ), (2) signal-integrate (INT), (3) de-integrate (DE) and (4) zero-integrator (Zl).Auto-Zero PhaseDuring auto-zero, three things happen. First, input high and low are disconnected from the pins and internally shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback loop is closed around the system to charge the auto-zero capacitor CAZ to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the AZ accuracy is limited only by the noise of the system. In any case, the offset referred to the input is less than 10µV.Signal Integrate PhaseDuring signal integrate , the auto-zero loop is opened, the internal short is removed, and the internal input high and low are connected to the external pins. The converter then integrates the differential voltage between IN HI and IN LO for a fixed time. This differential voltage can be within a wide common mode range; within one volt of either supply. If, on the other hand, the input signal has no return with respect to the converter power supply, IN LO can be tied to analog COMMON to establish the correct common-mode voltage. At the end of this phase, the polarity of the integrated signal is latched into the polarity F/F.De-Integrate PhaseThe third phase is de-integrate or reference integrate. Input low is internally connected to analog COMMON and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the out- put to return to zero is proportional to the input signal. Specifically the digital reading displayed is:Zero Integrator PhaseThe final phase is zero integrator. First, input low is shorted to analog COMMON. Second, a feedback loop is closed around the system to input high to cause the integrator output to return to zero. Under normal condition, this phase lasts from 100 to 200 clock pulses, but after an over range conversion, it is extended to 6200 clock pulses.Differential InputThe input can accept differential voltages anywhere within the common mode range of the input amplifier; or specifically from 0.5V below the positive supply to 1V above the negative supply. In this range the system has a CMRR of 86dB typical. However, since the integrator also swings with the common mode voltage, care must be exercised to assure the integrator output does not saturate. A worst case condition would be a large positive common-mode voltage with a near full scale negative differential input voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the positive common mode voltage. For these critical applications the integrator swing can be reduced to less than the recommended 4V full scale swing with some loss of accuracy. The integrator output can swing within 0.3V of either supply without loss of linearity.Analog COMMONAnalog COMMON is used as the input low return during auto-zero and de-integrate. If IN LO is different from analog COMMON, a common mode voltage exists in the system and is taken care of by the excellent CMRR of the converter. However, in most applications IN LO will be set at a fixed known voltage (power supply common for instance). In this application, analog COMMON should be tied to the same point, thus removing the common mode voltage from the converter. The reference voltage is referenced to analog COMMON.ReferenceThe reference input must be generated as a positive voltage with respect to COMMON, Digital SectionFigure 5 shows the Digital Section of the ICL7135. The ICL7135 includes several pins which allow it to operate conveniently in more sophisticated systems. These include: Run/HOLD (Pin 25)When high (or open) the A/D will free-run with equally spaced measurement cycles every 40,002 clock pulses. If taken low, the converter will continue the full measurementcycle that it is doing and then hold this reading as long as R/H is held low. A short positive pulse (greater than 300ns) will now initiate a new measurement cycle, beginning with between 1 and 10,001 counts of auto zero. If the pulse occurs before the full measurement cycle (40,002 counts) is completed, it will not be recognized and the converter will simply complete the measurement it is doing. An external indication that a full measureme nt cycle has been completed is that the first strobe pulse (see below) will occur 101 counts after the end of this cycle. Thus, if Run/HOLD is low and has been low for at least 101 counts, the converter is holding and ready to start a new measurement when pulsed high.STROBE (Pin 26)This is a negative going output pulse that aids in transferring the BCD data to external latches, UARTs, or microprocessors. There are 5 negative going STROBE pulses that occur in the center of each of the digit drive pulses and occur once and only once for each measurement cycle starting 101 clock pulses after the end of the full measurement cycle. Digit 5 (MSD) goes high at the end of the measurement cycle and stays on for 201 counts. In the center of this digit pulse (to avoid race conditions between changing BCD and digit drives) the first STROBE pulse goes 1negative for 1/2 clock pulse width. Similarly, after digit 5, digit 24 goes high (for 200 clock pulses) and 100 pulses later the STROBE goes negative for the second time. This continues through digit 1 (LSD) when the fifth and last STROBE pulse is sent. The digit drive will continue to scan (unless the previous signal was over range) but no additional STROBE pulses will be sent until a new measurement is available.BUSY (Pin 21)BUSY goes high at the beginning of signal integrate and stays high until the first clock pulse after zero crossing (or after end of measurement in the case of an over range). The internal latches are enabled (i.e., loaded) during the first clock pulse after busy and are latched at the end of this clock pulse. The circuit automatically reverts to auto-zero when not BUSY, so it may also be considered a (Zl + AZ) signal. A very simple means for transmitting the data down a single wire pair from a remote location would be to AND BUSY with clock and subtract 10,001 counts from the number of pulses received - as mentioned previously there is one “NO-count” pulse in each reference integrate cycle.OVERRANGE (Pin 27)This pin goes positive when the input signal exceeds the range (20,000) of the converter. The output F/F is set at the end of BUSY and is reset to zero at the beginning of reference integrate in the next measurement cycle.UNDERRANGE (Pin 28)This pin goes positive when the reading is 9% of range or less. The output F/F is set at the end of BUSY (if the new reading is 1800 or less) and is reset at the beginning of signal integrate of the next reading.POLARlTY (Pin 23)This pin is positive for a positive input signal. It is valid even for a zero re ading. In other words, +0000 means the signal is positive but less than the least significant bit. The converter can be used as a null detector by forcing equal frequency of (+) and (-) readings. The null at this point should be less than 0.1 LSB. This output becomes valid at the beginning of reference integrate and remains correct until it is revalidated for the next measurement.Digit Drives (Pins 12, 17, 18, 19 and 20)Each digit drive is a positive going signal that lasts for 200 clock pulses. The scan sequence is D5 (MSD), D4 , D3 , D2 , and D1 (LSD). All five digits are scanned and this scan is continuous unless an over range occurs. Then all digit drives are blanked from the end of the strobe sequence until the beginning of Reference Integrate when D5 will start the scan again. This can give a blinking display as a visual indication of over range.BCD (Pins 13, 14, 15 and 16)The Binary coded Decimal bits B8 , B4 , B2 , and B1 are positive logic signals that go on simultaneously with the digit driver signal.Component Value SelectionFor optimum performance of the analog section, care must be taken in the selection of values for the integrator capacitor and resistor, auto-zero capacitor, reference voltage, and conversion rate. These values must be chosen to suit the particular application.Integrating ResistorThe integrating resistor is determined by the full scale input voltage and the output current of the buffer used to charge the integrator capacitor. Both the buffer amplifier and the integrator have a class A output stage with 100 µA of quiescent current. They cansupply 20µ A of drive current with negligible non-linearity. Values of 5µ A to 40 µA give good results, with a nominal of 20 µA, and the exact value of integrating resistor may be chosen by:Integrating CapacitorThe product of integrating resistor and capacitor should be selected to give the maximum voltage swing which ensures that the tolerance built-up will not saturate the integrator swing (approx. 0.3V from either supply). For +5V supplies and analog COMMON tied to supply ground, a +3.5V to +4V full scale integrator swing is fine, and 0.47µ F is nominal. In general, the value of CINT is given by:A very important characteristic of the integrating capacitor is that it has low dielect ric absorption to prevent roll-over or ratiometric errors. A good test for dielectric absorption is to use the capacitor with the input tied to the reference.This ratiometric condition should read half scale 0.9999, and any deviation is probably due to dielectric absorption. Polypropylene capacitors give undetectable errors at reasonable cost. Polystyrene and polycarbonate capacitors may also be used in less critical applications.Auto-Zero and Reference CapacitorThe physical size of the auto-zero capacitor has an influence on the noise of the system.A larger capacitor value reduces system noise. A larger physical size increases system noise. The reference capacitor should be large enough such that stray capacitance to ground from its nodes is negligible .The dielectric absorption of the reference cap and auto-zero cap are only important at power-on or when the circuit is recovering from an overload. Thus, smaller or cheaper caps can be used here if accurate readings are not required for the first few sec onds of recovery.Reference VoltageThe analog input required to generate a full scale output is REF IN V V 2The stability of the reference voltage is a major factor in the overall absolute accuracy of the converter. For this reason, it is recommended that a high quality reference be used where high-accuracy absolute measurements are being made.Rollover Resistor and DiodeA small rollover error occurs in the ICL7135, but this can be easily corrected byadding a diode and resistor in series between the INTegrator OUTput and analog COMMON or ground. The value shown in the schematics is optimum for the recommended conditions, but if integrator swing or clock frequency is modified, adjustment may be needed. The diode can be any silicon diode such as 1N914. These components can be eliminated if rollover error is not important and may be altered in value to correct other (small) sources of rollover as needed.Max Clock FrequencyThe maximum conversion rate of most dual-slope A/D converters is limited by the frequency response of the comparator. The comparator in this circuit follows the integrator ramp with a 3µs delay, and at a clock frequency of 160kHz (6µs period) half of the first reference integrate clock period is lost in delay. This means that the meter reading will change from 0 to 1 with a 50 µV input, 1 to 2 with a 150 µV input, 2 to 3 with a 250µ V input, etc. This transition at mid-point is considered desirable by most users; however, if the clock frequency is increased appreciably above 160k Hz, the instrument will flash “1” on noise peaks even when the input is shorted.For many dedicated applications where the input signal is always of one polarity, the delay of the comparator need not be a limitation. Since the non -linearity and noise do not increase substantially with frequency, clock rates of up to ~1MHz may be used. For a fixed clock frequency, the extra count or counts caused by comparator delay will be constant and can be subtracted out digitally.The clock frequency may be extended above 160kHz without this error, however, by using a low value resistor in serieswith the integrating capacitor. The effect of the resistor is to introduce a small pedestal voltage on to the integrator output at the beginning of the reference integrate phase. By careful selection of the ratio between this resistor and the integrating resistor (a few tens of ohms in the recommended circuit), the comparator delaycan be compensated and the maximum clock frequency extended by approximately a factor of 3. At higher frequencies, ringing and second order breaks will cause significant non-linearities in the first few counts of the instrument. See Application Note AN017.The minimum clock frequency is established by leakage on the auto-zero and reference caps. With most devices, measurement cycles as long as 10s give no measurable leakage error.To achieve maximum rejection of 60Hz pickup, the signal integrate cycle should be a multiple of 60Hz. Oscillator frequencies of 300kHz, 200kHz, 150kHz, 120kHz, 100kHz, 40kHz, 33 31kHz, etc. should be selected. For 50Hz rejection, oscillator frequencies of 250kHz, 16632kHz, 125kHz, 100kHz, etc. would be suitable. Note that 100kHz (2.5 readings/sec) will reject both 50Hz and 60Hz.The clock used should be free from significant phase or frequency jitter. Severalsuitable low-cost oscillators are shown in the Typical Applications section. The multiplexed output means that if the display takes significant current from he logic supply, the clock should have good PSRR.Zero-Crossing Flip-FlopThe flip-flop interrogates the data once every clock pulse after the transients of the previous clock pulse and half-clock pulse have died down. False zero-crossings caused by clock pulses are not recognized. Of course, the flip-flop delays the true zero-crossing by up to one count in every instance, and if a correction were not made, the display would always be one count too high. Therefore, the counter is disabled for one clock pulse at thebeginning of phase 3. This one-count delay compensates for the delay of the zero-crossing flip-flop, and allows the correct number to be latched into the display. Similarly, aone-count delay at the beginning of phase 1 gives an overload display of 0000 instead of 0001. No delay occurs during phase 2, so that true ratiometric readings result.Evaluating The Error SourcesErrors from the ”ideal” cycle are caused by:1. Capacitor droop due to leakage.2. Capacitor voltage change due to charge “suck -out” (the reverse of charge injection)when the switches turn off.3. Non-linearity of buffer and integrator.4. High-frequency limitations of buffer, integrator, and comparator.5. Integrating capacitor non-linearity (dielectric absorption).6. Charge lost by RFF C in charging STRAY C7. Charge lost by AZ C and INT C to charge STRAY CEach error is analyzed for its error contribution to the converter in application notes listed on the back page, specifically Application Note AN017 and Application Note AN032.NoiseThe peak-to-peak noise around zero is approximately 15µ V (peak-to-peak value not exceeded 95% of the time). Near full scale, this value increases to approximately 30 µV. Much of the noise originates in the auto-zero loop, and is proportional to the ratio of the input signal to the reference.Analog And Digital GroundsExtreme care must be taken to avoid ground loops in the layout of ICL7135 circuits, especially in high-sensitivity circuits. It is most important that return currents from digital loads are not fed into the analog ground line.Power Supplies The ICL7135 is designed to work from +5V supplies. However, in selected applications no negative supply is required. The conditions to use a single +5V supply are:1. The input signal can be referenced to the center of the common mode range of the converter.2. The signal is less than +1.5V.外文资料译文ICL7135 4 1/2Digit, BCD Output, A/D ConverterICL7135是由INTERSIL公司生产的高精度A/D转换器，它的双斜率积分转换可靠性可达到在20,000计数中有+1的误差，另外加上它的数字躯动输出端以及多路复用的二一十进制码(BCD)输出端，就可以应用于数字电压表，数字电流表的显示。
外文翻译---数字网络
附录DIGITAL NETWORKThe ISDN will be a worldwide public telecommunications network that will deliver a wide variety of services. The ISDN will be defined by the standardization of user interfaces, and will be implemented as a set of digital switches and paths supporting a broad range of traffic types and providing value-added processing services. In practice, there will be multiple networks, implemented within national boundaries, but from the user’s point of view there will be a single, uniformly accessible worldwide network.There are two key aspects to ISDN: universal access and user services. By standardizing the interfaces to ISDN, all ISDN-compatible equipment (e.g. ,telephones computer terminals, personal computers )will be able to attach to the network anywhere in the world and connect to any other attached system. This can lead to extraordinary flexibility. For example, telephone numbers could be assigned in the same fashion as U.S. social security numbers, good for a lifetime. No matter where you lived, or how often you moved, dialing the number permanently assigned to you would always ring your telephone.A digitized network is a prime requirement for integrating a variety of services that the network will support. It is appropriate to view ISDN as being evolutionary in nature and scope. The first step in the process toward realizing an ISDN is end-to-end digitization.Digitization of the telephone network in the United States began in the early 1960s. The early digitized program largely addressed the inter exchange transmission system of the metropolitan network. Use of the time division multiplexing technique, rather than the traditional frequency division multiplexing technique, resulted in an enhanced capacity of the existing telephone plant at minimal cost.Further development in transmission systems, especially those based on fiberoptic transmission techniques, have pushed the digitization program well beyondthe most optimistic projections made just a few years ago. Compared to other forms of information transport, lightware systems have proved themselves economically and will continue to be the technology of choice in the foreseeable future. Form an initial transmission capability of 45 Mbps ten years ago , the capacity of lightware systems has doubled every 18 months. Presently ,1.8Gbps systems are available, and by mid-1990, 2.2Gbps systems will be on the commercial market. End-to-end digitization is available in limited pockets in the United States today but is expected to grow sharply during the next few years. This will provide the hardware base for realizing the ISDN capability.ISDN goes much beyond having digital switching and transmission hardware on a ubiquitous basis. The main focus of ISDN is on the support of a wide range of voice and nonvoice or integrated voice/nonvoice applications over the same network. A basic tenet of ISDN is that this service integration be achieved through a limited set of usernetwork interface arrangements.Heretofore, private line and switched offerings have been made by telecommunications administrations using functionally separate networks, for example , are often isolated from one another , and interworking between them is usually a difficult technical issue. ISDN provider for these services within a common framework in order to benefit the end users , particularly from the point of view of assuring them, through easy interworking among different services, of the continuing usage of their applications well-specified and functional user-network interface characteristics and the assurance that the network transport function can be achieved using whatever technique best meets the end user’s needs, but resulting in no additional interface problems , these goals of ISDN will not be realized.Recognizing the continuing growth in digitization of the telecommunications network and the advantages and additional capabilities of an end-to-end digital network , the concept of a single integrated network was born in the 1970s. Serious efforts were soon started in the CCITT, the organization that establishes international standards for public telecommunications, on a global basis. The first set of standards for ISDN were issued by the CCITT in 1984. As ISDN is established on a global basis,a variety of voice and nonvoice services can be supported over a single , homogeneous infrastructure. Analog communication will eventually disappear , resulting in enhanced quality at reduced costs.An integrated access mechanism is a basic tenet of ISDN. The ISDN framework requires that a variety of services be accessed using common access arrangements with a limited net of access interfaces.It is easy to recognize that there are very large fixed costs in the global telecommunications network today. Since a large discontinuity in service features and pricing will be unacceptable in the telecommuni8cations marketplace , it is easy to see that it may be infeasible to move immediately to ISDN in many areas of the world. The full implementation of some ISDN concepts may take several years, possibly through the whole decade of the 1990s. In the meanwhile , ISDN systems and services will interoperate with the existing services. ISDN is thus an evolutionary concept from the standpoint of services to the end user.From a networking perspective, ISDN is a new network infrastructure that will provide a single point of access to multiple networks and to different kinds of networks. ISDN exchanges will be able to interconnect with each other. In addition, ISDN exchange will be able to connect to other existing networks, for example, X.25 packet networks. They will able to connect to other existing voice telephone networks (public not disrupted). There will also interconnect with ensure that the presently available services are not disrupted while new services employing the additional capabilities of ISDN are made available to user.Before the advent of ISDN, the premises equipment and network services provide by the common user network were assumed to be distinct elements cooperating in only limited ways in providing an end-to-end service. The concept of ISDN specifically provides for the extension of network functions into the premises equipment, and vice versa, depending on the need of the application. This requires a rich set of signaling mechanisms between the premises equipment and the network, higher speeds of transmission that both the premises equipment and the network services must support, and an integrated set of end-to-end network managementcapabilities. Within the overall concept of ISDN, all elements, whether premises based or network based, that provide a service are thus covered. This is a revolutionary departure from the practice of communications during the last 100 years. With the advance of technology in both hardware and software, the provisioning of complex interfaces and the realization of transmission speeds in the hundreds megabits per second range are now achievable, making the concepts of ISDN a reality.数字网络ISDN是一个提供各种业务的世界范围的公共电信网络。
微控制器外文翻译
附录1译文微控制器是一种功能的计算机上系统芯片。
它包含一个处理器核心，内存和可编程输入/输出外设。
微控制器包括一个集成的CPU内存和外设，能够输入和输出，它强调高集成度，相反，一个微处理器只包含一个CPU，除了通常的算术和逻辑要素一般用途的微处理器，微控制器集成了更多的要素，如读写存储器的数据存储，只读存储器存储程序，快闪记忆体的永久数据存储，外设和输入/输出接口，时钟频率只有32KHz, 微处理器微操作往往以非常低的速度相比，这是足够的典型应用。
他们消耗功率相对较小，一般将有能力保持功能，同时等待一个事件，如一个按钮，按下或中断，电力消耗，从而使它们适合用于低功耗和长期持久的电池应用。
微控制器用于自动控制产品及设备，如汽车引擎控制系统，远程控制，办公室机器，家电，电动工具和玩具。
通过降低尺寸，成本和能耗的设计相比，使用一个单独的微处理器，内存，和输入/输出设备，微控制电子控制多进程。
嵌入式设计大多数的计算机系统使用的是内嵌在其他机器，如汽车，电话，电器，和周边的计算机系统。
这些都是所谓的嵌入式系统。
虽然一些嵌入式系统是非常复杂的，很多人起码的要求，内存和程序长度，没有操作系统，软件的复杂性和低。
典型的输入和输出设备包括开关，继电器，螺线管， LED的，小的或自定义LCD 显示器，射频器件，传感器和温度传感器的数据，如温度，湿度，光水平等嵌入式系统通常有没有键盘，屏幕，硬盘，打印机，或其他公认的I / O设备的个人电脑，并且可能缺乏人际交往的任何种类的设备中断这是强制性的微控制器提供实时响应的事件是嵌入式系统的控制。
当某些事件发生时，中断系统的信号处理器可以暂停处理目前的指令序列，并开始一个中断服务例程（侦察）。
的ISR将需要执行任何处理的基础上的来源中断，然后再返回原来的指令序列。
可能是设备中断源依赖，并往往包括活动，如内部定时器溢出，完成模拟向数字的转换，一个逻辑电平变化对投入，如从一个按钮被按下，和收到的数据的通信链路。
DDS外文翻译
All About Direct Digital SynthesisWhat is Direct Digital Synthesis?Direct digital synthesis (DDS) is a method of producing an analog waveform —usually a sine wave —by generating a time-varying signal in digital form and then performing a digital-to-analog conversion. Because operations within a DDS device are primarily digital, it can offer fast switching between output frequencies, fine frequency resolution, and operation over a broad spectrum of frequencies. With advances in design and process technology, today’s DDS devices are very compact and draw little power.Why would one use a direct digital synthesizer (DDS)? Aren’t there other methods for easily generating frequencies?The ability to accurately produce and control waveforms of various frequencies and profiles has become a key requirement common to a number of industries. Whether providing agile sources of low-phase-noise variable-frequencies with good spurious performance for communications, or simply generating a frequency stimulus in industrial or biomedical test equipment applications, convenience, compactness, and low cost are important design considerations.Many possibilities for frequency generation are open to a designer, ranging from phase-locked-loop (PLL)-based techniques for very high-frequency synthesis, to dynamic programming of digital-to-analog converter (DAC) outputs to generate arbitrary waveforms at lower frequencies. But the DDS technique is rapidly gaining acceptance for solving frequency- (or waveform) generationrequirements in both communications andindustrial applications because single-chip ICdevices can generate programmable analogoutput waveforms simply and with high resolution and accuracy.Furthermore, the continual improvements in both process technolog y and design have resulted in cost and power consumption levels that were previously unthinkably low. For example, the AD9833, a DDS-based programmable waveform generator (Figure 1), operatingFigure 1. The AD9833-a one-chip waveformgenerator.at 5.5 V with a 25-MHz clock, consumes a maximum power of 30 milliwatts.What are the main benefits of using a DDS?DDS devices like the AD9833 are programmed through a high speed serial peripheral-interface (SPI), and need only an external clock to generate simple sine waves. DDS devices are now available that can generate frequencies from less than 1 Hz up to 400 MHz (based on a 1-GHz clock). The benefits of their low power, low cost, and single small package, combined with their inherent excellent performance and the ability to digitally program (and re-program) the output waveform, make DDS devices an extremely attractive solution—preferable to less-flexible solutions comprising aggregations of discrete elements. What kind of outputs can I generate with a typical DDS device?DDS devices are not limited to purelysinusoidal outputs. Figure 2 shows thesquare-, triangular-, and sinusoidal outputsavailable from an AD9833.How does a DDS device create asine wave?Here’s a breakdown of the internalcircuitry of a DDS device: its maincomponents are a phase accumulator, ameans of phase-to-amplitude conversion(often a sine look-up table), and a DAC. These blocks are represented in Figure 3.A DDS produces a sine waveat a given frequency. The frequency depends on two variables, the reference-clock frequency and the binar y number programmed into the Figure 2. Square-, triangular-, and sinusoidal outputs from a DDS.Figure 3. Components of a direct digital synthesizer.frequency register (tuning word).The binary number in the frequency register provides the main input to the phase accumulator. If a sine look-up table is used, the phase accumulator computes a phase (angle) address for the look-up table, which outputs the digital value of amplitude—corresponding to the sine of that phase angle—to the DAC. The DAC, in turn, converts that number to a corresponding value of analog voltage or current. To generate a fixed-frequency sine wave, a constant value (the phase increment—which is determined by the binary number) is added to the phase accumulator with each clock cycle. If the phase increment is large, the phase accumulator will step quickly through the sine look-up table and thus generate a high frequency sine wave. If the phase increment is small, the phase accumulator will take many more steps, accordingly generating a slower waveform.What do you mean by a complete DDS?The integration of a D/A converter and a DDS onto a single chip is commonly known as a complete DDS solution, a property common to all DDS devices from ADI.Let’s talk some more about the phase accumulator. How does it work?Continuous-time sinusoidal signals have a repetitive angular phase range of 0 to 2.The digital implementation is no different. The counter’scarry function allows the phase accumulator to act asa phase wheel in the DDS implementation.To understand this basic function, visualize thesine-wave oscillation as a vector rotating around aphase circle (see Figure 4). Each designated point onthe phase wheel corresponds to the equivalent pointon a cycle of a sine wave. As the vector rotatesaround the wheel, visualize that the sine of the anglegenerates a corresponding output sine wave. OneFigure 4. Digital phase wheel. revolution of the vector around the phase wheel, at aconstant speed, results in one complete cycle of the output sine wave. The phase accumulator provides the equally spaced angular values accompanying the vector’s linear rotation aroundthe phase wheel. The contents of the phase accumulator correspond to the points on the cycle of the output sine wave.The phase accumulator is actually a modulo- M counter that increments its stored number each time it receives a clock pulse. The magnitude of the increment is determined by the binary-coded input word (M). This word forms the phase step size between reference-clock updates; it effectively sets how many points to skip around the phase wheel. The larger the jump size, the faster the phase accumulator overflows and completes its equivalent of a sine-wave cycle. The number of discrete phase points contained in the wheel is determined by the resolution of the phase accumulator (n), which determines the tuning resolution of the DDS. For an n = 28-bit phase accumulator, an M value of 0000...0001 would result in the phase accumulator overflowing after 28 reference-clock cycles (increments). If the M value is changed to 0111...1111, the phase accumulator will overflow after only 2 reference-clock cycles (the minimum required by Nyquist). This relationship is found in the basic tuning equation for DDS architecture:n C out f M f 2⨯= where:fOUT = output frequency of the DDSM = binary tuning wordfC = internal reference clock frequency (system clock)n = length of the phase accumulator, in bitsChanges to the value of M result in immediate and phase-continuous changes in the output frequency. No loop settling time is incurred as in the case of a phase-locked loop.As the output frequency is increased, the number of samples per cycle decreases. Since sampling theory dictates that at least two samples per cycle are required to reconstruct the output waveform, the maximum fundamental output frequency of a DDS is fC/2. However, for practical applications, the output frequency is limited to somewhat less than that, improving the quality of the reconstructed waveform and permitting filtering on the output.When generating a constant frequency, the output of the phase accumulator increaseslinearly, so the analog waveform it generates is inherently a ramp.Then how is that linear output translated into a sine wave?A phase -to - amplitude lookup table is used to convert the phase-accumulator’sinstantaneous output value (28 bits for AD9833)—with unneeded less-significant bits eliminated by truncation—into the sine-wave amplitude information that is presented to the (10 -bit) D/A converter. The DDS architecture exploits the symmetrical nature of a sine wave and utilizes mapping logic to synthesize a complete sine wave from one-quarter-cycle of data from the phase accumulator. The phase-to- amplitude lookup table generates the remainingdata by reading forward then back through the lookup table. This is shown pictorially in Figure 5.Figure 5. Signal flow through the DDS architecture.关于直接数字频率合成器什么是直接数字频率合成器？直接数字频率合成器（DDS）是一种通过产生一个以数字形式时变的信号，然后执行由数字至模拟转换的方法。
外文翻译---AT89CX051微控制器的模拟-数字变换器应用
附录1 外文文献及中文翻译Analog-to-Digital Conversion Utilizing theAT89CX051 MicrocontrollersThe Atmel AT89C1051 and AT89C2051.microcontrollers feature on-chip Flash,low pin count, wide operating voltage,range and an integral analog comparator.This application note describes two low-cost analog-to-digital conversiontechniques which utilize the analog comparato r in the AT89C1051 and AT89C2051 microcontrollers.RC Analog-to-Digital ConverterThis conversion method offers. An extremely low component count at the expense of accuracy and conversion time. In the example presented below,resolution is better than 50 millivolts, accuracy is somewhat less than a tenth of a Volt and conversion time is seven milliseconds or less.As shown in Figure 1, the RC analog-todigital. conversion method requires only two resistors and a capacitor in addition to the AT89CX051 microcontroller. A microcontroller output (pin 11), which swings from approximately ground to VCC, alternately charges and discharges the capacitor connected to thenon-inverting input of the internal comparator (pin 12). The microcontrollermeasures the time required for the voltage on the capacitor to match the unknown voltage applied to the inverting input of the internal comparator (pin 13).The unknown voltage is a function of the measured time.The HP5082-7300 LED displays shown in Figure 1 are not required for the conversion, but are utilized by the software to implement a simple two-digit voltmeter.The result of the analog-to-digital conversion is displayed in volts and tenths of a volt on the two displays. The voltmeter application does not utilize the full resolution of the RC conversion software,but serves to demonstrate the method as well as providing a tool for debug.The waveformfor a typical capacitor charge/discharge cycle is shown in Figure2. The discharge portion of the curve is identical to the charge portion rotated about the line VC = VCC/2. The equations and discussion below apply to the charge portion of the cycle, except where indicated. The voltage on the capacitoras a function of time is given by the exponential equation:VC=VCC(1-e-t/RC) (1)where VC is the voltage on the capacitor at time t, VCC is the supply voltage and RC is the product of the values of the resistor and capacitor. Note that voltage is expressed in Volts, time in seconds, resistance in Ohms and capacitance in Farads. The product RC is also known as the “time constant” of the network and affects the shape of the waveform. The waveform is steepest when capacitor charging or discharging begins and flattens with time.The first problem with the RC conversion method is the difficulty of solving the exponential equation without utilizing floating point calculations and transcendental functions. On a compressed time scale, the exponential curve appears straight over much of its length, suggesting that it might be approximated by a line. This scheme fails due to the continuous variation in slope over the length of the curve, which produces significant error. It also does not address the problemwhere the curve rolls off severely near the asymptote at VCC.The microcontroller need not solve the exponential equation in real time if a lookup table is used to map pre-calculated values to each sampled time interval. This scheme allows the data to be encoded and formatted as required by the application while simplifying the conversion software. Symmetries in the data may be exploited to reduce the size of the table.The second problem with the RC conversion method is the substantial error which results from variations in component values. Figure 3 shows an exaggerated view of the variation in the voltage on the capacitor due to variations in the values of the resistor and capacitor. As shown in the figure, the variation in the voltage on the capacitor decreases as the voltage on the capacitor decreases.The symmetry of the capacitor charge/discharge cycle can be exploited to reduce the effect of variations in component values on conversion accuracy. This is done by utilizing the charge portion of the cycle to measure voltages less than VCC/2 and the discharge portion to measure voltages greater than VCC/2. The worst case error is reduced to the error at VCC/2.Before component values can be assigned, the time interval at which the comparator output is to be sampled must be determined. The sample interval should be as short as possible to maximize converter resolution and minimize conversion time. The sample interval is limited by the time required to execute the requisite code, which is determined by the clock rate of the microcontroller. In the voltmeter application, the microcontroller operates with a 12-MHz clock, resulting in a sample interval of five microseconds.The time constant (RC) affects the shape of the capacitor charge/discharge waveform. Thevalue of the time constant must be chosen so that the steepest parts of the waveform are resolvableto the desired resolution. The steepest part of the charge portion of the waveform occurs near theorigin, while the steepest part of the discharge portion occurs near VCC. Due to the symmetry ofthe waveform, the same time constant may be used for measurements made on either portion ofthe waveform.Figure 4 shows an expanded view of the relationship between voltage and sample time nearthe origin. In the figure, V is the desired voltage resolution of the converter and t is the sampleinterval determined previously. The curve labeled ’VC’ re presents the voltage on the capacitor,which appears linear at this scale. In the figure, the slope of the curve is ideal, causingsampling to occur near the center of the voltage intervals. The slope of the curve may be less thanshown, but may not be greater, or resolution will be lost. Note that the first sample is offset fromthe origin by1/2to center the sample in the first voltage interval. To obtain the minimum valueof the time constant which will produce the required slope at the first sample, solve Equation 1 forRC ：RC=-t/1n(1-VC/VCC) (2)Then set to the minimum desired resolution (0.05-volt), to the sample intervaldetermined previously (five microseconds), and calculate RC at the first sample point, whereVC = 1/2 and t = 1/2 :The product of the values of R and C must not be less than the calculated minimum timeconstant. Utilizing a resistor with a one percent tolerance and a capacitor with a five percenttolerance（Rnorm-1%）(Cnorm-5%)>4.99*10-4In the voltmeter application, the selected values of R and C are 267 kilohms and 2 nanofarads,respectively, yielding a minimum time constant of approximately 5.02•10-4. An additionalconstraint is placed on the value of R. Referring again to Figure 1, note the 5.1 kilohm pullupresistort ∆V ∆t ∆V ∆t ∆84min min (1/2)(1/2)(510) 4.9910ln[1(1/2)/[1(1/2)(0.05)/CC CC t R C V V In V ---∆-⋅===⋅--∆-connected to pin 11 of the microcontroller. This resistor is present to supplement the microcontroller’s weak internal pullup, but has the detrimental effect of changing the time constant of the RC network during the charge portion of the capacitor charge/discharge cycle. This produces an asymmetry in the charge/discharge waveform, which contributes to conversion error. To minimize the effect of differences in the capacitor charge and discharge paths, the value of R should be chosen to be much greater than the value of the pullup resistor. In the voltmeter application, the selected value of R is 267 kilohms, which exceeds the value of the pullup resistor by more than an order of magnitude.The time constant (RC), which is a function of the desired converter resolution, determines the duration of the capacitorcharge/discharge cycle. The more time required for the capacitor to charge and discharge, the greater the number of samples required in the measurement loop and the greater the number of entries in the lookup table.Figure 1. Typical Capacitor Charge/DIscharge CycleFigure 2. Capacitor Voltage Variation as a Function of RC VariationFigure 1. Figure 2Cto the symmetry of the capacitor charge/discharge waveform, the determined sample count may be used for measurements made during either portion of the cycle.From Equation 3:tmax = -RmaxCmax•ln(1-(1/2)VCC/VCC)= -(Rnom+1%)(Cnom+5%)ln(1/2)= -(1.01)(267•103)(1.05)(2•10-9)ln(1/2)=393 s.The minimum number of samples for half the cycle is:tmax/ t = (393•10-6)/(5•10-6) = 79To maximize accuracy, voltages from zero to VCC/2 are measured during the charge portionof the capacitor charge/discharge cycle and voltages from VCC to VCC/2 are measured during the discharge portion of the cycle. As a result, the total number of entries in the table is twice the number of samples calculated previously for each half cycle. The lookup table contains application-specific values corresponding to the calculated voltage at each sample. For each half cycle, the Nth entry in the table corresponds to the voltage at t = (N-interval determined previously. For the charge half cycle, the voltage at each sample is calculated by solving Equation 1 for the time elapsed since the capacitor began to charge. For the discharge half cycle, the voltage at each sample is calculated by solving the following equation for the time elapsed since the capacitor began to discharge:VC=VCC•e-t/RC (3)The size and contents of the table may vary from application to application depending on the sample interval and conversion resolution. As the resolution increases, the number of entries in the table grows.In the voltmeter application, with resolution equal to 0.05 Volt, the lookup table contains 158 entries, which is twice the number of samples per half cycle calculated above.Voltages corresponding to samples taken during the charge half cycle are calculated by-78). By settingto 5.00-volts, Equation 1 becomes:V = 5(1-e-N (.0093633))Voltages corresponding to samples taken during the discharge half cycle are calculated by-78). Using the same values as for the charge half cycle, Equation 4 becomes:V = 5•e-N(.0093633))An abbreviated list of the voltages calculated for the capacitor charge/discharge cycle is shown below. The ordering of the voltages, increasing in the first half, decreasing in the second, tracks the voltage on the capacitor and defines the ordering of the table entries.As shown by the list, the number of samples in each half cycle is greater than required to reach the midrange value of 2.500-volts. This allows for “fast” cycles which oversho ot the nominal midrange value before the last sample is taken in each half cycle. Note that the differencebetween the calculated voltages at samples N=0 and N=1 is within the desired resolution of 0.050-volt, but the difference in voltage between adjacent samples decreases as N increases. This reflects the non-linear relationship between voltage and time in the circuit.The calculated voltages shown in the list are not entered into the lookup table, but are used to determine the values of the table entries. In the voltmeter application, the calculated voltages are rounded to tenths of a volt and the result stored in the table in packed-BCD form, two digits per byte. Example: the table entry corresponding to 2.523-volts is 25 hex, which displays as 2.5-volts.The worst case conversion error may be further reduced by utilizing components with tighter tolerances. Conversion accuracy and linearity are also affected by the characteristics of the capacitor. The capacitor used in the voltmeter prototype is a polystyrene film type, which not only provides good accuracy, but analog-to-digital conversion method. Even using minimizes error due to dielectric absorption and other effects.Error sources which have not been examined include: comparator limitations; asymmetries between the charge and discharge portions of the cycle; failure of the voltage on the capacitor to reach ground or VCC; variations in VCC. The contributions to conversion error made by these sources can be expected to increase error to somewhat more than the value due to component tolerances alo.中文翻译：AT89CX051微控制器的模拟-数字变换器应用Atmel AT89C1051和AT89C2051微控制器是具有低引脚数和宽工作电压范围的单片闪光器（Flash ）和不可缺少的比较器。
计算机系统外文翻译
外文文献翻译院系机电与自动化学院专业班级电气0801 姓名原文出处 IEEE的论文评分指导教师20 12 年 2 月 18 日大多数计算机系统嵌入在今天使用其他设备,包括电话、钟表、电器、车辆和基础设施。
嵌入式系统通常很少有要求长度和记忆和程序可能需要简单但不寻常的输入/输出系统。
例如,大多数嵌入式系统中缺乏键盘,屏幕磁盘,打印机,或其他可辨认的I / O设备一台个人电脑。
他们可能控制电机、继电器或母线电压、读到的开关、可变电阻或其他电子设备与通用CPU、微控制器没有地址总线或数据总线,因为他们整合与非挥发性内存为主的公绵羊在同一芯片CPU。
因为他们需要更少的针、芯片可以放置在一个更小的、廉价的包裹记忆和其他外围设备集成在一个芯片上,作为一个单元测试的成本的增加的芯片,但是经常导致净成本降低了嵌入式系统作为一个整体。
(即使CPU,它的成本还集成外设略多于成本是一个CPU +外部外设,几乎没有芯片通常允许一个小、更便宜,降低电路板的劳动要求的电路板组装和测试)。
单片机是一个单一集成电路,通常与以下特点:中央处理器——从小、简单到复杂的32 - 4比特处理器或64位处理器输入/输出接口,如串行端口(UARTs)其他系列通信接口就像我²C、串行外设接口和控制器局域网系统互连外设(如定时器和监督来存储数据存储器,可擦可编程只读存储器,EEPROM或者闪存程序存储器——通常一个时钟生成器的石英晶体振荡器的时机,谐振器或RC电路包括类比数位转换器许多。
这种整合的数量大幅度降低芯片和数量的接线、PCB空间生产需要用分开的等价系统芯片和证明了是在嵌入式系统中非常流行,因为他们的介绍在1970年代。
单片机结构可以从许多不同的供应商在那么多品种,每个指令集建筑可以理所当然地应属于他们自己的一个范畴。
最首要的是8051,Z80和手臂的衍生物。
[引用需要]单片机(MCU或者µC)是计算机system-on-a-chip功能。
12位AD转换器中英文翻译资料
英文原文12-Bit A/D ConverterCIRCUIT OPERATIONThe AD574A is a complete 12-bit A/D converter which requires no external components to provide the complete successive approximation analog-to-digital conversion function. A block diagram of the AD574A is shown in Figure 1.Figure 1. Block Diagram of AD574A 12-Bit A-to-D ConverterWhen the control section is commanded to initiate a conversion (as described later), it enables the clock and resets the successiveapproximation register (SAR) to all zeros. Once a conversion cycle has begun, it cannot be stopped or restarted and data is not available from the output buffers. The SAR, timed by the clock, will sequence through the conversion cycle and return an end-of-convert flag to the control section. The control section will then disable the clock, bring the output status flag low, and enable control functions to allow data read functions by external command.During the conversion cycle, the internal 12-bit current output DAC is sequenced by the SAR from the most significant bit (MSB) to least significant bit (LSB) to provide an outputcurrent which accurately balances the input signal current through the 5kΩ(or10kΩ) input resistor. The comparator determines whether the addition of each successively-weighted bit current causes the DAC current sum to be greater or less than the input current; if the sum is less, the bit is left on; if more, the bit is turned off. After testing all the bits, the SAR contains a 12-bit binary code which accurately represents the input signal to within 1/2 LSB.The temperature-compensated buried Zener reference provides the primary voltage reference to the DAC and guarantees excellent stability with both time and temperature. Theupply up to 1.5 mA to an external load in addition to the requirements of the reference input resistor (0.5 mA) and bipolar offset resistorrent must be supplied over the full temperature range, an external buffer amplifier is recommended. Any external load on the AD574A reference must remain constant during conversion. The thin-film application resistors are trimmed to match the full-scale ouoperation and connected to the 10 volt reference for bipolar operation.DRIVING THE AD574 ANALOG INPUTFigure 2. Op Amp – AD574A InterfaceThe output impedance of an op amp has an open-loop value which, in a closed loop, is divided by the loop gain available at the frequency of interest. The amplifier should have acceptable loop gain at 500 kHz for use with the AD574A. To check whether the outputproperties of a signal source are suitable, monitor the AD574’s input with an oscilloscope while a conversion is in progress. Each of the 12 disturbances should subside in sorless.For applications involving the use of a sample-and-hold amplifier, the AD585 is recommended. The AD711 or AD544 op amps are recommended for dc applications. SAMPLE-AND-HOLD AMPLIFIERSaccurate 12-bit conversions of frequencies greater than a few Hz requires the use of a sample-and-hold amplifier (SHA). If the voltage of the analog input signal driving the AD574A changes by more than 1/2 LSB over the time interval needed to make a conversion, then the input requires a SHA.The AD585 is a high linearity SHA capable of directly driving the analog input of the AD574A. The AD585’s fast acquisition time, low aperture and low aperture jitter are ideally suited for high-speed data acquisition systems. Consider the AD574A converter with a-p: the maximum frequency which may be applied to achieve rated accuracy is 1.5 Hz. However, with the addition of an AD585, as shown in Figure 3, the maximum frequency increases to 26 kHz.The AD585’s low output impedance, fast-loop response, and low droop maintain 12-bits of accuracy under the changing load conditions that occur during a conversion, making it suitable for use in high accuracy conversion systems. Many other SHAs cannot achieve 12-bits of accuracy and can thus compromise a system. The AD585 is recommended for AD574A applications requiring a sample and hold.Figure 3. AD574A with AD585 Sample and HoldSUPPLY DECOUPLING AND LAYOUTCONSIDERATIONSIt is critically important that the AD574A power supplies be filtered, well regulated, and free from high frequency noise. Use of noisy supplies will cause unstable output codes. Switching power supplies are not recommended for circuits attempting to achieve 12-bit accuracy unless great care is used in filtering any switching spikes present in the output. Remember that a few millivolts of noise represents several counts of error in a 12-bit ADC.Circuit layout should attempt to locate the AD574A, associated analog input circuitry, and interconnections as far as possible from logic circuitry. For this reason, the use of wire-wrap circuit construction is not recommended. Careful printed circuit construction is preferred.UNIPOLAR RANGE CONNECTIONS FOR THE AD574AThe AD574A contains all the active components required to perform a complete 12-bit A/D conversion. Thus, for most situations, all that is necessary is connection of the power supplies (+5 V, +12 V/+15 V and –12 V/–15 V), the analog input, and the conversion initiation command, as discussed on the next page. Analog input connections and calibration are easily accomplished; the unipolar operating mode is shown in Figure 4.Figure 4. Unipolar Input ConnectionsAll of the thin-film application resistors of the AD574A are trimmed for absolute calibration. Therefore, in many applications, no calibration trimming will be required. The absolute accuracy for each grade is given in the specification tables. For example, if no trims are used, the AD574AK guaranteemax full-scale error. (Typical full-Pin 12 can be connected directly to Pin 9; the two resistors and trimmer for Pin 12 are then not needed. If the full-be connected between Pin 8 and Pin 10.The analog input is connected between Pin 13 and Pin 9 for a 0 V to +10 V input range, between 14 and Pin 9 for a 0 V to +20 V input range. The AD574A easily accommodates an input signal beyond the supplies. For the 10 volt span input, the LSB has a nominal value of 2.44 mV; for the 20 volt span, 4.88 mV.If a 10.24 V range is desired (nominal 2.5 mV/bit), the gain trimmer (R2) should be replaced by a 50Ωesistor, and a 200Ωa full-described below is now done with these trimmers. The nominal input impedance into Pin 13 is 5kΩ, and 10kΩUNIPOLAR CALIBRATIONThe AD574A is intended to have a nominal 1/2 LSB offset so that the exact analog input for a given code will be in the middle of that code (halfway between the transitions to the codes above and below it). Thus, the first transition (from 0000 0000 0000 to 0000 0000 0001) will occur for an input level of +1/2 LSB (1.22 mV for 10 V range).If Pin 12 is connected to Pin 9, the unit will behave in this manner, within specifications. If the offset trim (R1) is used, it should be trimmed as above, although a different offset canoffset trim range.The full-scale trim is done by applying a signal 1/2 LSB below the nominal full scale (9.9963 for a 10 V range). Trim R2 to give the last transition (1111 1111 1110 to 1111 1111 1111).BIPOLAR OPERATIONThe connections for bipolar ranges are shown in Figure 5. Again, as for the unipolar ranges, if the offset and gain specifications are sufficient, one or both of the trimmers showncalibration.Figure 5. Bipolar Input ConnectionsCONTROL LOGICThe AD574A contains on-chip logic to provide conversion initiation and data readoperations from signals commonly available in microprocessor systems. Figure 6 shows the internal logic circuitry of the AD574A.The control signals CE, CS, and R/C control the operation of the converter. The state of R/C when CE and CS are both asserted determines whether a data read (R/C = 1) or a convert (R/C = 0) is in progress. The register control inputs AO and 12/8 control conversion length and data format. The AO line is usually tied to the least significant bit of the address bus. If a conversion is started with AO low, a full 12-bit conversion cycleis initiated. If AO is high during a convert start, a shorter 8-bit conversion cycle results. During data read operations, AO determines whether the three-state buffers containing the 8 MSBs of the conversion result (AO = 0) or the 4 LSBs (AO = 1) are enabled. The 12/8 pin determines whether the output data is to be organized as two 8-bit words (12/8 tied to DIGITAL COMMON) or a single 12-bit word (12/8 tied to VLOGIC). The 12/8 pin is not TTL-compatible and must be hard-wired to either VLOGIC or DIGITAL COMMON. In the 8-bit mode, the byte addressed when AO is high contains the 4 LSBs from the conversion followed by four trailing zeroes. This organization allows the data lines to be overlapped for direct interface to 8-bit buses without the need for external three-state buffers. It is not recommended that AO change state during a data read operation. Asymmetrical enable and disable times of the three-state buffers could cause internal bus contention resulting in potential damage to the AD574A.Figure 6. AD574A Control LogicAn output signal, STS, indicates the status of the converter. STS goes high at the beginning of a conversion and returns low when the conversion cycle is complete.TIMINGThe AD574A is easily interfaced to a wide variety of microprocessors and other digital systems. The following discussion of the timing requirements of the AD574A control signals should provide the system designer with useful insight into the operation of the device.Figure 7 shows a complete timing diagram for the AD574A convert start operation. R/C should be low before both CE and CS are asserted; if R/C is high, a read operation will momentarily occur, possibly resulting in system bus contention. Either CE or CS may be used to initiate a conversion; however, use of CE is recommended since it includes one less propagation delay than CS and is the faster input. In Figure 7, CE is used to initiate the conversion.Figure 7Once a conversion is started and the STS line goes high, convert start commands will be ignored until the conversion cycle is complete. The output data buffers cannot be enabled during conversion.Figure 8 shows the timing for data read operations. During data read operations, access time is measured from the point where CE and R/C both are high (assuming CS is already low). If CS is used to enable the device, access time is extended by 100 ns.Figure 8. Read Cycle TimingIn the 8-bit bus interface mode (12/8 input wired to DIGITAL COMMON), the address bit, AO, must be stable at least 150 ns prior to CE going high and must remain stable during the entire read cycle. If AO is allowed to change, damage to the AD574A output buffers may result.“STAND-ALONE” OPERATIONThe AD574A can be used in a “stand-alone” mode, which is useful in systems with dedicated input ports available and thus not requiring full bus interface capability. In this mode, CE and 12/8 are wired high, CS and AO are wired low, and conversion is controlled by R/C. The three-state buffers are enabled when R/C is high and a conversion starts when R/C goes low. This allows two possible control signals—a high pulse or a low pulse. Operation with a low pulse is shown in Figure 11. In this case, the outputs are forced into the high impedance state in response to the falling edge of R/C and return to valid logic levels after the conversion cycle is completed. The STS line goes high 600 ns after R/C goes low and returns low 300 ns after data is valid.Figure 11. Low Pulse for R/C—Outputs Enabled After ConversionIf conversion is initiated by a high pulse as shown in Figure 12, the data lines are enabled during the time when R/C is high. The falling edge of R/C starts the next conversion, and the data lines return to three-state (and remain three-state) until the next high pulse of R/C.Figure 12. High Pulse for R/C—Outputs Enabled While R/C High, Otherwise High-ZUsually the low pulse for R/C stand-alone mode will be used. Figure 13 illustrates a typical stand-alone configuration for 8086 type processors. The addition of the 74F/S374 latches improves bus access/release times and helps minimize digital feedthrough to the analog portion of the converter.INTERFACING THE AD574A TO MICROPROCESSORSThe control logic of the AD574A makes direct connection to most microprocessor system buses possible. While it is impossible to describe the details of the interface connections for every microprocessor type, several representative examples will be described here.GENERAL A/D CONVERTER INTERFACECONSIDERATIONSA typical A/D converter interface routine involves several operations. First, a write to the ADC address initiates a conversion.The processor must then wait for the conversion cycle to complete, since most ADCs take longer than one instruction cycle to complete a conversion. Valid data can, of course, only be read after the conversion is complete. The AD574A provides an output signal (STS) which indicates when a conversion is in progress. This signal can be polled by the processor by reading it through an external three-state buffer (or otherinput port). The STS signal can also be used to generate an interrupt upon completion of conversion, if the system timing requirements are critical (bear in mind that the maximum conversion time of the AD574A is only 35 microseconds) and the processor has other tasks to perform during the ADC conversion cycle. Another possible time-out method is to assume that the ADC will take 35 microseconds to convert, and insert a sufficient number of “do-nothing” instructions to ensure that 35 microseconds of processor time is consumed Once it is established that the conversion is finished, the data can be read. In the case of an ADC of 8-bit resolution (or less), a single data read operation is sufficient. In the case of converters with more data bits than are available on the bus, a choice of data formats is required, and multiple read operations are needed. The AD574A includes internal logic to permit direct interface to 8-bit or 16-bit data buses, selected by connection of the 12/8 input. In 16-bit bus applications (12/8 high) the data lines (DB11 through DB0) may be connected to either the 12 most significant or 12 least significant bits of the data bus. The remaining four bits should be masked in software. The interface to an 8-bit data bus (12/8 low) is done in a left-justified format. The even address (A0 low) contains the 8 MSBs (DB11 through DB4). The odd address (A0 high) contains the 4 LSBs (DB3 through DB0) in the upper half of the byte, followed by four trailing zeroes, thus eliminating bit masking instructions.SPECIFIC PROCESSOR INTERFACE EXAMPLESZ-80 System InterfaceThe AD574A may be interfaced to the Z-80 processor in an I/O or memory mapped configuration. Figure 15 illustrates an I/O or mapped configuration. The Z-80 uses address lines A0–A7 to decode the I/O port address.An interesting feature of the Z-80 is that during I/O operations a single wait state is automatically inserted, allowing the AD574A to be used with Z-80 processors having clock speeds up to 4 MHz. For applications faster than 4 MHz use the wait state generator in Figure 16. In a memory mapped configuration the AD574A may be interfaced to Z-80 processors with clock speeds of up to 2.5 MHz.附录E 中文翻译12位-AD574A转换器电路工作原理AD574A是一个完善的12位A/D转换器，不需要外部组件提供完全的逐步逼近模拟数字转换功能。
电气类毕业设计外文翻译3
附录1 译文A/D 转换器按照转换原理可分为直接A/D 转换器和间接A/D 转换器。
所谓直接A/D 转换器，是把模拟信号直接转换成数字信号，如逐次逼近型，并联比较型等。
其中逐次逼近型A/D 转换器，易于用集成工艺实现，且能达到较高的分辨率和速度，故目前集成化A/D 芯片采用逐次逼近型者多；间接A/D 转换器是先把模拟量转换成中间量，然后再转换成数字量，如电压/时间转换型（积分型），电压/频率转换型，电压/脉宽转换型等。
其中积分型A/D 转换器电路简单，抗干扰能力强，切能作到高分辨率，但转换速度较慢。
有些转换器还将多路开关、基准电压源、时钟电路、译码器和转换电路集成在一个芯片内，已超出了单纯A/D 转换功能，使用十分方便。
ADC 经常用于通讯、数字相机、仪器和测量以及计算机系统中，可方便数字讯号处理和信息的储存。
大多数情况下，ADC 的功能会与数字电路整合在同一芯片上，但部份设备仍需使用独立的ADC。
行动电话是数字芯片中整合ADC 功能的例子，而具有更高要求的蜂巢式基地台则需依赖独立的ADC 以提供最佳性能。
ICL7107是三位半双积分型A/D转换器，属于CMOS大规模集成电路，它的最大显示值为士1999，最小分辨率为100μV。
能直接驱动共阳极LED数码管，不需要另加驱动器件，采用士5V两组电源供电，在芯片内部从V与COM+之间有一个稳定性很高的2.8V基准电源，通过电阻分压器可获得所需的基准电压。
能通过内部的模拟开关实现自动调零和自动极性显示功能，输入阻抗高，对输入信号无衰减作用。
整机组装方便，无需外加有源器件，配上电阻、电容和LED共阳极数码管，就能构成一只直流数字电压表头。
噪音低，温漂小，具有良好的可靠性，寿命长。
芯片本身功耗小于15mv(不包括LED)，不设有专门的小数点驱动信号。
使用时可将LED共阳极数数码管公共阳极接V，可以方便的+进行功能检查。
双积分型A/D转换器内部包括积分器、比较器、计数器，控制逻辑和时钟信号源。
外文翻译-模拟与数字转换器2
Analog and Digital TransducersAs mentioned previously, considerable experience has been accumulated with analog transducers, signal conditioning, A/D converters etc. , and it is natural that the majority of current systems tend to use these techniques. However, there are a number of measuring techniques that are essentially digit in nature, and which when used as separate measuring instruments require some intrgral digtal circuitry, such as frequency counters and timing circuits, to provide an indicator output. This type of transducer, if coupled to a computer, does not necessarily require the same amount of equipment since much of the processing done by the integral circuitry could be programmed and by the computer.Collins classifies the signals handled in control and instrumentation systems as follows:(1) Analog, in which the parameter of the system to be measured although initially derived in an analog form by a sensor is converted to an electrical analog, either by design or inherent in the methods adopted;(2) Coded-digital, in which a parallel digital sigal is generated, each bit radix-weighted according to some predetermined code. These are referred to in this bood as direct digital transducers;(3) Digital, in which a function, such as mean rate of a repetitive signal, is a measure of the parameter being measured. These are subsequently referred to as frequency-domain transducers.Some analog transducers are particularly suited to conversion to digital outputs using special techniques. The most popular of these are synchros, and similar devices, which produce a modulated output of a carrier frequency. For ordinary analog use, this output has to be demodulated to provide a signal whose magnitude and sign represent any displacement of the transducer’s moving element. Although it is possible to use a conventional A/D technique to produce a digital output while providing a high accuracy and resolution, and at a faster rate than is possible in the A/D converter method.Direct digital transducers are, in fact, few and far between, since there do not seem to be any natural phenomena in which some detectable characteristic changes in discrete intervals as a result of a change of pressure, or change of tempreature etc.. These are many advantages in using direct digital transducers in ordinary instrumentation systems, even if computers are not used in the complete installation.These advantages are:(1)The ease of generating, manipulating and storing digital signals, as punched tape, magnetic tape etc. ;(2)The need for high measurement accuracy and discrimination;(3)The relative immunity of a high-level digital signal to external disturbances (noise);(4)Ergonomic advantages in simplified data presentation(e. g. digital readout avoids interpretation errors in reading scales or graphs).The most active development in direct digital transducers has been in shaft encoders, which are used extensively in machine tools and aircraft systems. High resolution and accuracies can be obtained, and these devices may be mechanically coupled to provide a direct digital output of any parameter which gives rise to a measurable physical displacement. The usual displacement of these systems is that the inertia of the instrument and encoder often limit the speed of response and therefore the operating frequencies.Frequency domain transducers have a special part to play in online systems with only few variables to be measured, since the computer can act as part of an A/D conversion system and use its own registers and clock for counting pulses or measuring pulse width. In designing such systems, consideration must be given to the computer time required to access and process the trransducer output.Data Line Isolation TheoryWhen it comes to protect data lines from electrical transients, surge suppression is often the first thing that leaps to mind. The concept of surge suppression is intuitive and there are a large variety of devices on the market to choose from. Models are available to protect every-thing from your computer to answering machine as well as those serial devices found in RS-232, RS-422 and RS-485 systems.Unfortunately, in most serial communications systems,surge suppression is not the best choice. The result of most storm and inductively induced surges is to cause a difference in ground potential between points in a xommunications system. The more physical area covered by the system, the more likely those differences in ground potential will exist.The water analogy helps explain this. Instead of phenomenon water in a pipe, we’ll thi nk a little bigger and use waves on the ocean. Ask anyone what the elevation of the ocean is, and you will get an answer of zero－so common that we call it sealevel. While the average ocean elevation is zero, we know that tides and waves can cause large short-term changes in the actual height of the water. This is very similar to earth ground. The effect of a large amount of current dumped into the earth can be visualized in the same way, as a wave propa-gating outwards from the origin. Until this energy dissipates, the voltage level of the earth will vary greatly between two locations.Adding a twist to the ocean analogy, what is the best way to protect a boat from high waves? We could lash the boat to a fixed dock, forcing the boat to remain at one elevation. This will protect against small waves, but this solution obviously has limitation. While a little rough, this comparison isn’t far off from what a typical surge suppressor is trying to accom-plish. Attempting to clamp a surge of energy to a level safe for the local equipment requires that the clamping device be able to completely absorb or redirect transient energy.Instead of lashing the boat to a fixed dock let the dock float. Now the boat can rise and fall with the ocean swells (until we hit the end of our floating dock’s posts).Instead of fighting nature, we’re simply moving along with it. This is our data line isola-tion solution.Isolation is not a new idea. It has always been implemented in telephone and Ethernet equipment. For asynchronous data applications such as many RS-232, RS-422 and RS-485 systems, optical isolators are the most common isolation elements. With isolation, two different grounds (better thought of as reference voltages) can exist on opposite sides of the isolation element without any current flowing through the element. With an optical isolator, this is performed with an LED and a photosensitive transistor. Only light passes between the two elements.Another benefit of optical isolation is that it is not dependent on installation quality. Thpical surge suppressors used in data line protection use special diodes to shunt excess energy to ground. The installer must provide an extremely low imprdance ground connection to handle this energy, which can be thousands of amps at frequencies into the tens of megahertz. A small impedance in the ground connection, such as in 1.8m (6ft) of 18 gauge wire, can cause a voltage drop of hundreds of volts －enough voltage to damage most equipments. Isolation, on the other hand, does not require an additional ground connection, making it insensitive to installation quality.Isolation is not a perfect solution. An additional isolated power supply is required to support the circuitry. This supply may be built in as an isolated DC-DC converteror external. Simple surge suppressors require no power source. Isolation voltages are limited as well, usually ranging from 500V to 4000V. In some cases, applying both surge suppression and isolation is an effective solution.When choosing data line protection for a system it is important to consider all available options. There are pros and cons to both surge suppression and optical isolation, however isolation is a more effective solution for most systems. If in doubt, choose isolation.模拟与数字转换器前面我们已经提到，人们在模拟转换器、信号调节器和A/D 转换器等的使用上已经积累了大量的经验。
外文翻译--中文
多无线电发射极地和笛卡尔的相关架构的性能分析高效率开关模式功率放大器摘要：多无线电无线本文在频段的发射机架构为800 MHz - 6 GHz。
作为一个常量的后果在通信系统的演进过程中，移动发射TERS必须能够工作在不同频段和模式，根据现有的标准规格。
一个独特的多模架构的概念是一个EVO，多标准收发器lution特点是每个标准的电路并行。
多无线电概念就是优化表面和功耗。
发射机架构，使用的是抽样技术和基带，或PWM信号的编码之前，他们放大出现很好的候选人为多模。
发射机的几个原因——他们允许使用开关模式功率大、放大器的功率大，这是由于高度灵活易于集成他们的数字性质。
但是，当传输效率大，许多元素都必须考虑：信号的编码效率，射频滤波器，PA的效率。
本文探讨这些架构的利益——多无线发射器，能够支持现有的无线800兆赫和6 GHz 之间的通信标准。
它的计算和比较不同的可能architec、iMAX和LTE标准tures信号质量和发射功率的效率。
关键词：多模发射器，高效率的射频发射器，极性发射架构，笛卡尔变送器架构，E类功率放大器，PWM编码，WiMAX和LTE。
1引进和语境包括蜂窝无线通信系统通信，个人局域网（PAN），本地区域网络（LAN）和城域网（MAN）中已经提出了长足的发展。
近年来持续不断的改进。
共存同一个设备上的不同的无线标准是必要的以满足用户期望流动性，无处不在的CON-在同一时间连接和高速率的数据。
此coexis-唐塞不应增加设备的大小或减少其电池寿命。
这种演变的目标是减少外部元件数目和增加集成在低成本CMOS 技术的运移。
另一个阶段它奉行对认知无线电的演变并意味着每个阶段的沟通的灵活性链是认知无线电多。
而不是包括每个标准，通用的独立架构能够生成所有的发射器架构不同的标准波形，似乎是最好的解决办法（尤其是在消耗功率和表面占用pation）。
这个概念被称为多无线电发射机。
认知多无线电有能力multistan-dard的概念，而且是能够执行一个高效的环境频谱扫描和反应环境条件选择的拨款通信标准。
模数转换器外文翻译
附录A：英文资料翻译：模数转换器来自：维科百科通常情况下，一个AD转换器是一个将输入模拟电压（或电流）转换为一个数字号码的电子装置，数位输出，可使用不同的编码方案，如二进制，格雷码或二的互补二元。
然而，一些非电子或仅是部分电子设备，如轴角编码器，也可以考虑的ADC 。
线性的ADC大多数的ADC是被认为是线性的，虽然数位转换是一个非线形的过程（是连续空间映射为离散空间成为分段常数，因此是非线性操作）。
线性此处所说的是，输入值映射到每个产值是呈线性关系的。
非线形的ADC如果一个信号被数字化的概率密度函数的是一致的，那么，信噪比相对向量化噪声是最好的可能。
正因为如此，经常使信号在量化之前通过其累积分布函数。
这是一件好事，因为这样做可以使量化得到一个更好的解决方案。
在量化过程中，这么做是必要的。
准确性一个模数转换器有几个错误的来源。
量化误差和非线形是内在任何模拟到数字的转换。
此外，还有一个所谓的孔径误差是由于一时钟抖动，并透露，当数字化的一个信号（而不是一个单一的值）。
这些错误是衡量一个单位的所谓LSB的，这是一个缩写，至少有显着位。
在上面的例子中的1 8位ADC ，一个错误的1 LSB的是： 1 / 256的全部信号范围，或约0.4 ％。
非线形所有的ADC由于物理性质的不完善而遭受非线形的错误，造成其输出偏离线性函数（或在该案件故意非线形ADC的其他一些功能，）的，他们的投入。
这些错误，有时可以得到缓解的校准，或阻止通过测试。
重要参数的线性是积分非线性（禁毒局）和微分非线性（ dnl ）。
因此，你需要做仔细的计算当您这样做的收敛性。
模拟信号在时间上是连续的它也有必要转换为流动的数字值。
因此，这是需要界定的速度，其中新的数字值是从模拟信号采样。
新的价值观率是所谓转换器的采样率或采样频率。
一个不断变带信号可以采样（即，信号值的间隔时间t ，采样时间，测量和储存），然后原始信号，可正是转载自离散时间值由内插公式。
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模拟与数字转换器前面我们已经提到，人们在模拟转换器、信号调节器和A/D转换器等的使用上已经积累了大量的经验。
因此，目前大部分的系统自然都采用这些技术。
然而，还有很大一部分测量方法实质是数字的，在个别的测量仪中使用这些方法时，需要用到一些积分电路，如频率计数和计时电路等来提供指示输出。
另外，如果把这种转换器和电脑相连的话，就可以省去一些器材；因为很多有积分电路执行的工作可以由计算机程序代为执行。
柯林斯把在控制和测量系统中处理的信号分为以下几类：（1）模拟式。
尽管系统的被测数最初通过传感器得到的是模拟信号，然后通过设计或采用原有的方法将模拟形式的信号转换成电模拟信号。
（2）数字码式。
产生的信号是并行的数字信号，每一位的基数权重由预先编定的号码系统决定。
在本书中这些仪器称作直接数字转换器。
（3）数字式。
其中的函数是指测量参数时用到的量度标准，如对重复信号取平均值。
这些仪器在后来称为频域转换器。
特别地，一些模拟转换器适合用一些特别的技术来把模拟量转换成数字输出。
其中最通用的方法是同步法和相似仪器的方法，即产生载波频率的调制输出的方法。
在用作普通的模拟量输出仪器时，输出量必须经过解调。
解调后输出的是直流信号，支流信号的大小和方向描述了转换器运动元件的偏移。
虽然使用传统的A/D转换技术可以用来产生数字信号，在提供高精度时采用这些新技术将同步输出直接变为数字输出，比用A/D转换方法更快。
直接数字转换器实际上用得很少，因为在自然现象中很少有那种由温度变化、压力变化等因素作用而产生的可测量的离散的变化量。
在普通的仪器系统中使用直接数字转换器有如下优点（即使在完成安装时不使用计算机）：（1）容易产生、处理和存储信号，如打控带、磁带等；（2）高精度和高分辨率的需要；（3）高介数字信号对外部噪声的抗干扰性；（4）在简化数据描述时的人机工程学优势（例如：数字读出器能避免读刻度或图表时的判度错误）。
在直接数字转换器中最能起作用的发展是轴编码器。
轴编码器在机床和飞行系统中被广泛应用。
利用这些设备能达到很高的精度和分辨率，而且这些设备能进行激动连接，给出任何可测量物理偏移的直接数字输出。
这类系统通常的缺点是仪器的惯性及编码器限制了相应的速度，因而也限制了操作频率。
频域转换器在线系统（测量量较少时）有着特殊的地位。
因为计算机能担当A/D转换系统的部分工作，能用它自己的寄存器和时钟来计算脉冲和测量脉冲宽度。
在这种系统的设计中必须考虑到计算机存取和处理转换器输出所需的时间。
自动控制的应用虽然自动控制应用范围实际上是无限的，但是我们的讨论仅限于现代工业中常见的几个例子。
伺服机构虽然伺服机构本身并不是一种控制的应用，但是这种装置在自动控制中却是常用的。
伺服机构，或简单称“伺服”，是一种闭环控制系统，其中的被控变量是机械位置或机械运动。
该机构的设计使得输出能迅速而精确地响应输入信号的变化。
因此，我们能把伺服机构现象为一种随动装置。
另一种控制输出变化率或输出速度的伺服机构称为速率或速度伺服机构。
过程控制过程控制是用来表示制造过程中多变量控制的一个术语。
化工厂、炼油厂、食品加工厂、鼓风炉、轧钢机都是自动控制用于生产过程的里子。
过程控制就是把有关诸如温度、压力、流量、液位、黏度、密度、成分等这样一些过程变量控制为预期值。
发电电力工业首先关系到能量的转换与分配。
发电量可能超过几千万千瓦的现代化大型电厂需要复杂的控制系统来表明许多变量的相互关系，并提供最佳的发电量。
发电厂的控制一般认为是一种过程控制的应用，而且通常有多打100个操纵变量受计算机控制。
自动控制已广泛地用于电力分配。
电力系统通常由几个发电厂组成。
当负载波动时，电力的生产和传输要受到控制，使该系统达到运行的最低要求。
此外，大多数的大型电力系统都是相互联系的，而且两系统之间的电力流动也受到控制。
数字控制有许多加工工序，如镗床、钻床、铣削和焊接都必须以很高的精度重复进行。
数字控制是一个系统，该系统使用的是称为程序的预定指令来控制一系列运行。
完成这些预期工序的指令被编程代码，并且存储在如穿孔纸带、磁带或穿孔卡片等某个介质上。
这些指令通常以数字形式存储，故称为数字控制。
指令辨认要用工具、加工方法（如切削速度）及工具运动的轨迹（位置、方向、速度等）等参数。
运输为了向现代化城市的各个地区提供大量的运输系统，需要大型、复杂的控制系统。
目前正在进行的几条自动运输系统中有每隔几分钟的高速火车。
要保持稳定的火车流量及提供舒适的加速和停站时的制动，就需要自动控制。
飞机的飞行控制是在运输领域的另一项重要应用。
由于系统参数的范围的广泛以及控制之间的相互影响，飞行控制已被证明为最复杂的控制应用之一。
飞机控制系统实质上常常是自适应的-，即其操纵本身要适应于周围环境。
例如一架飞机的性能在低空和高空可能是根本不同的，所以控制系统就必须作为飞行高度的函数进行修正。
船舶转向和颠簸稳定控制与飞行控制相似，但是一般需要更大的功率和较低的响应速度。
张琦，杨承先．现代机电专业英语[M]．北京：清华大学出版社，20051.Analog and Digital TransducersAs mentioned previously, considerable experience has been accumulated with analog transducers signal conditioning, signal; conditioning, A/D converters etc., and it is natural that the majority of current systems tend to use these techniques. However, there are a number of measuring techniques that are essentially digit in nature, and which when used as separate measuring instruments require some integral digital circuitry, such as frequency counters and timing circuits, to provide an indicator output. This type of transducer, if coupled to a computer does not necessarily require the same amount of equipment since much of the processing done by the integral circuitry could be programmed and performed and performed by the computer.Collins classifies the signals handled in control and instrumentation systems as follows:(1) Analog, in which the parameter of the system to be measured although initially derived in an analog form by a sensor is converted to an electrical analog, either by design or inherent in the methods adopted;(2) Coded digital, in which a parallel digital signal is generated, each bit radix weighted according to some predetermined code. These are referred to in this book as direct digital transducers;(3) Digital, in which a function, such as mean rate of a repetitive signal, is ameasure of the parameter being measured. These are subsequently referred to as frequency domain transducers.Some analog transducers are particularly suited to conversion to digital outputs using special techniques. The most popular of these are synchros, and similar devices, which produce a modulated output of a carrier frequency. For ordinary analog use, this output has to be demodulated to provide a signal whose magnitude and sign represent any conventional A/D technique to produce a digital output, there are techniques by which the synchro output can be converted directly to a digital output while providing a high accuracy and resolution, and at a faster rate than is possible in the A/D converter method.(1) The ease of generating, manipulating and storing digital signals, as punched tape, magnetic tape etc.;(2) The need for high measurement accuracy and discrimination;(3) The relative immunity of a high level digital signal to external disturbances(noise);(4) Ergonomic advantages in simplified data presentation(e.g. digital readout avoids interpretation errors in reading scales or graphs).The most active development in direct digital transducer has been in shaft encoders, which are used extensively in machine tools and aircraft systems. High resolution and accuracies can be obtained, and these devices may be mechanically coupled to provide a direct digital output of any parameter which gives rise to a measurable physical displacement. The usual disadvantage of these systems is that the inertia of the instrument and encoder often limit the speed of response and therefore the operating frequencies.Frequency domain transducers have a special part to play in online systems with only few variables to be measured, since the computer can act as part of an A/D conversion system and use its own registers and clock for counting pulses or measuring pulse width. Access and process the transducer output. In designing such systems, consideration must be given to the computer time required to access and process the transducer output.Application of Automatic ControlAlthough the scope of automatic control application, we will limit this discussion to examples which are commonplace in modern industry.ServomechanismsAlthough a servomechanism is not a control application, this device is commonplace in automatic control. A servomechanism, or ‘servo’for short, is a closed-loop control system in which the controlled variable is mechanical position or motion. It is designed so that the output will quickly and precisely respond to a change in the input command. Thus we may think of a servomechanism as a following device.Another form of servomechanism in which the rate of change or velocity of the output is controlled is known as a rate or velocity servomechanism.Process ControlProcess control is a term applied to the control of variables in a manufacturing process. Chemical plants, oil refineries, food processing plants, blast furnaces, and steel mill are examples of production processes to which automatic control is applied. Process control is concerned with maintaining at a desired value such process variables as temperature, pressure, flow rate, liquid level, viscosity, density, and composition.Much current work in process control involves extending the use of the digital computer to provide direct digital control (DDC) of the process variables. In direct digital control the computer calculates the values of the manipulated variables. The decisions of the computer are applied to digital actuators in the process. Since the computer duplicates the analog controller action, these conventional controllers are no longer needed.Power GenerationThe electric power industry is primarily concerned with energy conversion and distribution. Large modern power plants which may exceed several hundred megawatts of generation require complex control systems to account for the interrelationship of the many variables and provide optimum power production. Control of power generation may be as 100 manipulated variables under computer control.Automatic control has also been extensively applied to the distribution of electric power. Power systems ate commonly made up of a number of generating plants. As load requirements fluctuate, the generation and transmission of power is controlled to achieve minimum cost of system operation. In addition, most large power systems are interconnected with each other, and the flow of power between systems is controlled.Numerical ControlThere are rainy manufacturing operations such as boring, drilling, milling, and welding which must be performed with high precision on a repetitive basis. Numerical control (NC) is a system that uses predetermined instructions called a program to control a sequence of such operations. The instructions to accomplish a desired operation ate coded and stored on some medium such as punched paper tape, magnetic tape, or punched cards. These instructions ate usually stored in the form of numbers-0bence the name numerical control. The instructions identify what tool is to be used, in what way (e.g. cutting speed), and the path of the tool movement (position, direction, velocity, etc.).TransportationTo provide mass transportation systems for modern urban areas, large, complex control systems are needed. Several automatic transportation systems now in operation have high-speed trains running at several-minute intervals. Automatic control is necessary to maintain a constant flow of trains and to provide comfortable acceleration and braking at station stops.Aircraft flight control is another important application in the transportation field. This has been proven to be one of the most complex control applications due to the wide range of system parameters and the interaction between controls. Aircraft control systems ate frequently adaptive in nature; that is, the operation adapts itself to the surrounding conditions. For example, since the behavior of an aircraft may differ radically at low and high altitudes the control system must be modified as a function of altitude.Ship-steering and toll-stabilization controls are similar to flight control but generally require fat higher powers and involve lower speeds of response.。